| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Assembly Writer Source Fragment *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| /// printInstruction - This method is automatically generated by tablegen |
| /// from the instruction set description. |
| void AArch64InstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) { |
| static const char AsmStrs[] = { |
| /* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', 9, 0, |
| /* 9 */ 's', 'h', 'a', '5', '1', '2', 's', 'u', '0', 9, 0, |
| /* 20 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', 9, 0, |
| /* 31 */ 'l', 'd', '1', 9, 0, |
| /* 36 */ 't', 'r', 'n', '1', 9, 0, |
| /* 42 */ 'z', 'i', 'p', '1', 9, 0, |
| /* 48 */ 'u', 'z', 'p', '1', 9, 0, |
| /* 54 */ 'd', 'c', 'p', 's', '1', 9, 0, |
| /* 61 */ 's', 'm', '3', 's', 's', '1', 9, 0, |
| /* 69 */ 's', 't', '1', 9, 0, |
| /* 74 */ 's', 'h', 'a', '1', 's', 'u', '1', 9, 0, |
| /* 83 */ 's', 'h', 'a', '5', '1', '2', 's', 'u', '1', 9, 0, |
| /* 94 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '1', 9, 0, |
| /* 105 */ 's', 'm', '3', 'p', 'a', 'r', 't', 'w', '1', 9, 0, |
| /* 116 */ 'r', 'a', 'x', '1', 9, 0, |
| /* 122 */ 'r', 'e', 'v', '3', '2', 9, 0, |
| /* 129 */ 'l', 'd', '2', 9, 0, |
| /* 134 */ 's', 'h', 'a', '5', '1', '2', 'h', '2', 9, 0, |
| /* 144 */ 's', 'h', 'a', '2', '5', '6', 'h', '2', 9, 0, |
| /* 154 */ 's', 'a', 'b', 'a', 'l', '2', 9, 0, |
| /* 162 */ 'u', 'a', 'b', 'a', 'l', '2', 9, 0, |
| /* 170 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', '2', 9, 0, |
| /* 180 */ 'f', 'm', 'l', 'a', 'l', '2', 9, 0, |
| /* 188 */ 's', 'm', 'l', 'a', 'l', '2', 9, 0, |
| /* 196 */ 'u', 'm', 'l', 'a', 'l', '2', 9, 0, |
| /* 204 */ 's', 's', 'u', 'b', 'l', '2', 9, 0, |
| /* 212 */ 'u', 's', 'u', 'b', 'l', '2', 9, 0, |
| /* 220 */ 's', 'a', 'b', 'd', 'l', '2', 9, 0, |
| /* 228 */ 'u', 'a', 'b', 'd', 'l', '2', 9, 0, |
| /* 236 */ 's', 'a', 'd', 'd', 'l', '2', 9, 0, |
| /* 244 */ 'u', 'a', 'd', 'd', 'l', '2', 9, 0, |
| /* 252 */ 's', 's', 'h', 'l', 'l', '2', 9, 0, |
| /* 260 */ 'u', 's', 'h', 'l', 'l', '2', 9, 0, |
| /* 268 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', '2', 9, 0, |
| /* 278 */ 'p', 'm', 'u', 'l', 'l', '2', 9, 0, |
| /* 286 */ 's', 'm', 'u', 'l', 'l', '2', 9, 0, |
| /* 294 */ 'u', 'm', 'u', 'l', 'l', '2', 9, 0, |
| /* 302 */ 's', 'q', 'd', 'm', 'l', 's', 'l', '2', 9, 0, |
| /* 312 */ 'f', 'm', 'l', 's', 'l', '2', 9, 0, |
| /* 320 */ 's', 'm', 'l', 's', 'l', '2', 9, 0, |
| /* 328 */ 'u', 'm', 'l', 's', 'l', '2', 9, 0, |
| /* 336 */ 'f', 'c', 'v', 't', 'l', '2', 9, 0, |
| /* 344 */ 'r', 's', 'u', 'b', 'h', 'n', '2', 9, 0, |
| /* 353 */ 'r', 'a', 'd', 'd', 'h', 'n', '2', 9, 0, |
| /* 362 */ 's', 'q', 's', 'h', 'r', 'n', '2', 9, 0, |
| /* 371 */ 'u', 'q', 's', 'h', 'r', 'n', '2', 9, 0, |
| /* 380 */ 's', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, |
| /* 390 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, |
| /* 400 */ 't', 'r', 'n', '2', 9, 0, |
| /* 406 */ 'f', 'c', 'v', 't', 'n', '2', 9, 0, |
| /* 414 */ 's', 'q', 'x', 't', 'n', '2', 9, 0, |
| /* 422 */ 'u', 'q', 'x', 't', 'n', '2', 9, 0, |
| /* 430 */ 's', 'q', 's', 'h', 'r', 'u', 'n', '2', 9, 0, |
| /* 440 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', '2', 9, 0, |
| /* 451 */ 's', 'q', 'x', 't', 'u', 'n', '2', 9, 0, |
| /* 460 */ 'f', 'c', 'v', 't', 'x', 'n', '2', 9, 0, |
| /* 469 */ 'z', 'i', 'p', '2', 9, 0, |
| /* 475 */ 'u', 'z', 'p', '2', 9, 0, |
| /* 481 */ 'd', 'c', 'p', 's', '2', 9, 0, |
| /* 488 */ 's', 't', '2', 9, 0, |
| /* 493 */ 's', 's', 'u', 'b', 'w', '2', 9, 0, |
| /* 501 */ 'u', 's', 'u', 'b', 'w', '2', 9, 0, |
| /* 509 */ 's', 'a', 'd', 'd', 'w', '2', 9, 0, |
| /* 517 */ 'u', 'a', 'd', 'd', 'w', '2', 9, 0, |
| /* 525 */ 's', 'm', '3', 'p', 'a', 'r', 't', 'w', '2', 9, 0, |
| /* 536 */ 'l', 'd', '3', 9, 0, |
| /* 541 */ 'e', 'o', 'r', '3', 9, 0, |
| /* 547 */ 'd', 'c', 'p', 's', '3', 9, 0, |
| /* 554 */ 's', 't', '3', 9, 0, |
| /* 559 */ 'r', 'e', 'v', '6', '4', 9, 0, |
| /* 566 */ 'l', 'd', '4', 9, 0, |
| /* 571 */ 's', 't', '4', 9, 0, |
| /* 576 */ 's', 'e', 't', 'f', '1', '6', 9, 0, |
| /* 584 */ 'r', 'e', 'v', '1', '6', 9, 0, |
| /* 591 */ 's', 'e', 't', 'f', '8', 9, 0, |
| /* 598 */ 's', 'm', '3', 't', 't', '1', 'a', 9, 0, |
| /* 607 */ 's', 'm', '3', 't', 't', '2', 'a', 9, 0, |
| /* 616 */ 'b', 'r', 'a', 'a', 9, 0, |
| /* 622 */ 'l', 'd', 'r', 'a', 'a', 9, 0, |
| /* 629 */ 'b', 'l', 'r', 'a', 'a', 9, 0, |
| /* 636 */ 's', 'a', 'b', 'a', 9, 0, |
| /* 642 */ 'u', 'a', 'b', 'a', 9, 0, |
| /* 648 */ 'p', 'a', 'c', 'd', 'a', 9, 0, |
| /* 655 */ 'l', 'd', 'a', 'd', 'd', 'a', 9, 0, |
| /* 663 */ 'f', 'a', 'd', 'd', 'a', 9, 0, |
| /* 670 */ 'a', 'u', 't', 'd', 'a', 9, 0, |
| /* 677 */ 'p', 'a', 'c', 'g', 'a', 9, 0, |
| /* 684 */ 'p', 'a', 'c', 'i', 'a', 9, 0, |
| /* 691 */ 'a', 'u', 't', 'i', 'a', 9, 0, |
| /* 698 */ 'b', 'r', 'k', 'a', 9, 0, |
| /* 704 */ 'f', 'c', 'm', 'l', 'a', 9, 0, |
| /* 711 */ 'f', 'm', 'l', 'a', 9, 0, |
| /* 717 */ 'f', 'n', 'm', 'l', 'a', 9, 0, |
| /* 724 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 9, 0, |
| /* 733 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 9, 0, |
| /* 742 */ 'b', 'r', 'k', 'p', 'a', 9, 0, |
| /* 749 */ 'c', 'a', 's', 'p', 'a', 9, 0, |
| /* 756 */ 's', 'w', 'p', 'a', 9, 0, |
| /* 762 */ 'f', 'e', 'x', 'p', 'a', 9, 0, |
| /* 769 */ 'l', 'd', 'c', 'l', 'r', 'a', 9, 0, |
| /* 777 */ 'l', 'd', 'e', 'o', 'r', 'a', 9, 0, |
| /* 785 */ 's', 'r', 's', 'r', 'a', 9, 0, |
| /* 792 */ 'u', 'r', 's', 'r', 'a', 9, 0, |
| /* 799 */ 's', 's', 'r', 'a', 9, 0, |
| /* 805 */ 'u', 's', 'r', 'a', 9, 0, |
| /* 811 */ 'c', 'a', 's', 'a', 9, 0, |
| /* 817 */ 'l', 'd', 's', 'e', 't', 'a', 9, 0, |
| /* 825 */ 'f', 'r', 'i', 'n', 't', 'a', 9, 0, |
| /* 833 */ 'c', 'l', 'a', 's', 't', 'a', 9, 0, |
| /* 841 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 9, 0, |
| /* 850 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 9, 0, |
| /* 859 */ 'p', 'a', 'c', 'd', 'z', 'a', 9, 0, |
| /* 867 */ 'a', 'u', 't', 'd', 'z', 'a', 9, 0, |
| /* 875 */ 'p', 'a', 'c', 'i', 'z', 'a', 9, 0, |
| /* 883 */ 'a', 'u', 't', 'i', 'z', 'a', 9, 0, |
| /* 891 */ 'l', 'd', '1', 'b', 9, 0, |
| /* 897 */ 'l', 'd', 'f', 'f', '1', 'b', 9, 0, |
| /* 905 */ 'l', 'd', 'n', 'f', '1', 'b', 9, 0, |
| /* 913 */ 'l', 'd', 'n', 't', '1', 'b', 9, 0, |
| /* 921 */ 's', 't', 'n', 't', '1', 'b', 9, 0, |
| /* 929 */ 's', 't', '1', 'b', 9, 0, |
| /* 935 */ 's', 'm', '3', 't', 't', '1', 'b', 9, 0, |
| /* 944 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0, |
| /* 952 */ 'l', 'd', '2', 'b', 9, 0, |
| /* 958 */ 's', 't', '2', 'b', 9, 0, |
| /* 964 */ 's', 'm', '3', 't', 't', '2', 'b', 9, 0, |
| /* 973 */ 'l', 'd', '3', 'b', 9, 0, |
| /* 979 */ 's', 't', '3', 'b', 9, 0, |
| /* 985 */ 'l', 'd', '4', 'b', 9, 0, |
| /* 991 */ 's', 't', '4', 'b', 9, 0, |
| /* 997 */ 'l', 'd', 'a', 'd', 'd', 'a', 'b', 9, 0, |
| /* 1006 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'b', 9, 0, |
| /* 1016 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'b', 9, 0, |
| /* 1026 */ 's', 'w', 'p', 'a', 'b', 9, 0, |
| /* 1033 */ 'b', 'r', 'a', 'b', 9, 0, |
| /* 1039 */ 'l', 'd', 'r', 'a', 'b', 9, 0, |
| /* 1046 */ 'b', 'l', 'r', 'a', 'b', 9, 0, |
| /* 1053 */ 'l', 'd', 'c', 'l', 'r', 'a', 'b', 9, 0, |
| /* 1062 */ 'l', 'd', 'e', 'o', 'r', 'a', 'b', 9, 0, |
| /* 1071 */ 'c', 'a', 's', 'a', 'b', 9, 0, |
| /* 1078 */ 'l', 'd', 's', 'e', 't', 'a', 'b', 9, 0, |
| /* 1087 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'b', 9, 0, |
| /* 1097 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'b', 9, 0, |
| /* 1107 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0, |
| /* 1116 */ 's', 'q', 'd', 'e', 'c', 'b', 9, 0, |
| /* 1124 */ 'u', 'q', 'd', 'e', 'c', 'b', 9, 0, |
| /* 1132 */ 's', 'q', 'i', 'n', 'c', 'b', 9, 0, |
| /* 1140 */ 'u', 'q', 'i', 'n', 'c', 'b', 9, 0, |
| /* 1148 */ 'p', 'a', 'c', 'd', 'b', 9, 0, |
| /* 1155 */ 'l', 'd', 'a', 'd', 'd', 'b', 9, 0, |
| /* 1163 */ 'a', 'u', 't', 'd', 'b', 9, 0, |
| /* 1170 */ 'p', 'r', 'f', 'b', 9, 0, |
| /* 1176 */ 'f', 'l', 'o', 'g', 'b', 9, 0, |
| /* 1183 */ 'p', 'a', 'c', 'i', 'b', 9, 0, |
| /* 1190 */ 'a', 'u', 't', 'i', 'b', 9, 0, |
| /* 1197 */ 'b', 'r', 'k', 'b', 9, 0, |
| /* 1203 */ 's', 'a', 'b', 'a', 'l', 'b', 9, 0, |
| /* 1211 */ 'u', 'a', 'b', 'a', 'l', 'b', 9, 0, |
| /* 1219 */ 'l', 'd', 'a', 'd', 'd', 'a', 'l', 'b', 9, 0, |
| /* 1229 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', 'b', 9, 0, |
| /* 1239 */ 'f', 'm', 'l', 'a', 'l', 'b', 9, 0, |
| /* 1247 */ 's', 'm', 'l', 'a', 'l', 'b', 9, 0, |
| /* 1255 */ 'u', 'm', 'l', 'a', 'l', 'b', 9, 0, |
| /* 1263 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'l', 'b', 9, 0, |
| /* 1274 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'l', 'b', 9, 0, |
| /* 1285 */ 's', 'w', 'p', 'a', 'l', 'b', 9, 0, |
| /* 1293 */ 'l', 'd', 'c', 'l', 'r', 'a', 'l', 'b', 9, 0, |
| /* 1303 */ 'l', 'd', 'e', 'o', 'r', 'a', 'l', 'b', 9, 0, |
| /* 1313 */ 'c', 'a', 's', 'a', 'l', 'b', 9, 0, |
| /* 1321 */ 'l', 'd', 's', 'e', 't', 'a', 'l', 'b', 9, 0, |
| /* 1331 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'l', 'b', 9, 0, |
| /* 1342 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'l', 'b', 9, 0, |
| /* 1353 */ 's', 's', 'u', 'b', 'l', 'b', 9, 0, |
| /* 1361 */ 'u', 's', 'u', 'b', 'l', 'b', 9, 0, |
| /* 1369 */ 's', 'b', 'c', 'l', 'b', 9, 0, |
| /* 1376 */ 'a', 'd', 'c', 'l', 'b', 9, 0, |
| /* 1383 */ 's', 'a', 'b', 'd', 'l', 'b', 9, 0, |
| /* 1391 */ 'u', 'a', 'b', 'd', 'l', 'b', 9, 0, |
| /* 1399 */ 'l', 'd', 'a', 'd', 'd', 'l', 'b', 9, 0, |
| /* 1408 */ 's', 'a', 'd', 'd', 'l', 'b', 9, 0, |
| /* 1416 */ 'u', 'a', 'd', 'd', 'l', 'b', 9, 0, |
| /* 1424 */ 's', 's', 'h', 'l', 'l', 'b', 9, 0, |
| /* 1432 */ 'u', 's', 'h', 'l', 'l', 'b', 9, 0, |
| /* 1440 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', 'b', 9, 0, |
| /* 1450 */ 'p', 'm', 'u', 'l', 'l', 'b', 9, 0, |
| /* 1458 */ 's', 'm', 'u', 'l', 'l', 'b', 9, 0, |
| /* 1466 */ 'u', 'm', 'u', 'l', 'l', 'b', 9, 0, |
| /* 1474 */ 'l', 'd', 's', 'm', 'i', 'n', 'l', 'b', 9, 0, |
| /* 1484 */ 'l', 'd', 'u', 'm', 'i', 'n', 'l', 'b', 9, 0, |
| /* 1494 */ 's', 'w', 'p', 'l', 'b', 9, 0, |
| /* 1501 */ 'l', 'd', 'c', 'l', 'r', 'l', 'b', 9, 0, |
| /* 1510 */ 'l', 'd', 'e', 'o', 'r', 'l', 'b', 9, 0, |
| /* 1519 */ 'c', 'a', 's', 'l', 'b', 9, 0, |
| /* 1526 */ 's', 'q', 'd', 'm', 'l', 's', 'l', 'b', 9, 0, |
| /* 1536 */ 'f', 'm', 'l', 's', 'l', 'b', 9, 0, |
| /* 1544 */ 's', 'm', 'l', 's', 'l', 'b', 9, 0, |
| /* 1552 */ 'u', 'm', 'l', 's', 'l', 'b', 9, 0, |
| /* 1560 */ 'l', 'd', 's', 'e', 't', 'l', 'b', 9, 0, |
| /* 1569 */ 'l', 'd', 's', 'm', 'a', 'x', 'l', 'b', 9, 0, |
| /* 1579 */ 'l', 'd', 'u', 'm', 'a', 'x', 'l', 'b', 9, 0, |
| /* 1589 */ 'd', 'm', 'b', 9, 0, |
| /* 1594 */ 'r', 's', 'u', 'b', 'h', 'n', 'b', 9, 0, |
| /* 1603 */ 'r', 'a', 'd', 'd', 'h', 'n', 'b', 9, 0, |
| /* 1612 */ 'l', 'd', 's', 'm', 'i', 'n', 'b', 9, 0, |
| /* 1621 */ 'l', 'd', 'u', 'm', 'i', 'n', 'b', 9, 0, |
| /* 1630 */ 's', 'q', 's', 'h', 'r', 'n', 'b', 9, 0, |
| /* 1639 */ 'u', 'q', 's', 'h', 'r', 'n', 'b', 9, 0, |
| /* 1648 */ 's', 'q', 'r', 's', 'h', 'r', 'n', 'b', 9, 0, |
| /* 1658 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', 'b', 9, 0, |
| /* 1668 */ 's', 'q', 'x', 't', 'n', 'b', 9, 0, |
| /* 1676 */ 'u', 'q', 'x', 't', 'n', 'b', 9, 0, |
| /* 1684 */ 's', 'q', 's', 'h', 'r', 'u', 'n', 'b', 9, 0, |
| /* 1694 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', 'b', 9, 0, |
| /* 1705 */ 's', 'q', 'x', 't', 'u', 'n', 'b', 9, 0, |
| /* 1714 */ 'b', 'r', 'k', 'p', 'b', 9, 0, |
| /* 1721 */ 's', 'w', 'p', 'b', 9, 0, |
| /* 1727 */ 'l', 'd', '1', 'r', 'q', 'b', 9, 0, |
| /* 1735 */ 'l', 'd', '1', 'r', 'b', 9, 0, |
| /* 1742 */ 'l', 'd', 'a', 'r', 'b', 9, 0, |
| /* 1749 */ 'l', 'd', 'l', 'a', 'r', 'b', 9, 0, |
| /* 1757 */ 'l', 'd', 'r', 'b', 9, 0, |
| /* 1763 */ 'l', 'd', 'c', 'l', 'r', 'b', 9, 0, |
| /* 1771 */ 's', 't', 'l', 'l', 'r', 'b', 9, 0, |
| /* 1779 */ 's', 't', 'l', 'r', 'b', 9, 0, |
| /* 1786 */ 'l', 'd', 'e', 'o', 'r', 'b', 9, 0, |
| /* 1794 */ 'l', 'd', 'a', 'p', 'r', 'b', 9, 0, |
| /* 1802 */ 'l', 'd', 't', 'r', 'b', 9, 0, |
| /* 1809 */ 's', 't', 'r', 'b', 9, 0, |
| /* 1815 */ 's', 't', 't', 'r', 'b', 9, 0, |
| /* 1822 */ 'l', 'd', 'u', 'r', 'b', 9, 0, |
| /* 1829 */ 's', 't', 'l', 'u', 'r', 'b', 9, 0, |
| /* 1837 */ 'l', 'd', 'a', 'p', 'u', 'r', 'b', 9, 0, |
| /* 1846 */ 's', 't', 'u', 'r', 'b', 9, 0, |
| /* 1853 */ 'l', 'd', 'a', 'x', 'r', 'b', 9, 0, |
| /* 1861 */ 'l', 'd', 'x', 'r', 'b', 9, 0, |
| /* 1868 */ 's', 't', 'l', 'x', 'r', 'b', 9, 0, |
| /* 1876 */ 's', 't', 'x', 'r', 'b', 9, 0, |
| /* 1883 */ 'l', 'd', '1', 's', 'b', 9, 0, |
| /* 1890 */ 'l', 'd', 'f', 'f', '1', 's', 'b', 9, 0, |
| /* 1899 */ 'l', 'd', 'n', 'f', '1', 's', 'b', 9, 0, |
| /* 1908 */ 'l', 'd', 'n', 't', '1', 's', 'b', 9, 0, |
| /* 1917 */ 'c', 'a', 's', 'b', 9, 0, |
| /* 1923 */ 'd', 's', 'b', 9, 0, |
| /* 1928 */ 'i', 's', 'b', 9, 0, |
| /* 1933 */ 'f', 'm', 's', 'b', 9, 0, |
| /* 1939 */ 'f', 'n', 'm', 's', 'b', 9, 0, |
| /* 1946 */ 'l', 'd', '1', 'r', 's', 'b', 9, 0, |
| /* 1954 */ 'l', 'd', 'r', 's', 'b', 9, 0, |
| /* 1961 */ 'l', 'd', 't', 'r', 's', 'b', 9, 0, |
| /* 1969 */ 'l', 'd', 'u', 'r', 's', 'b', 9, 0, |
| /* 1977 */ 'l', 'd', 'a', 'p', 'u', 'r', 's', 'b', 9, 0, |
| /* 1987 */ 't', 's', 'b', 9, 0, |
| /* 1992 */ 'l', 'd', 's', 'e', 't', 'b', 9, 0, |
| /* 2000 */ 's', 's', 'u', 'b', 'l', 't', 'b', 9, 0, |
| /* 2009 */ 'c', 'n', 't', 'b', 9, 0, |
| /* 2015 */ 'e', 'o', 'r', 't', 'b', 9, 0, |
| /* 2022 */ 'c', 'l', 'a', 's', 't', 'b', 9, 0, |
| /* 2030 */ 's', 'x', 't', 'b', 9, 0, |
| /* 2036 */ 'u', 'x', 't', 'b', 9, 0, |
| /* 2042 */ 'f', 's', 'u', 'b', 9, 0, |
| /* 2048 */ 's', 'h', 's', 'u', 'b', 9, 0, |
| /* 2055 */ 'u', 'h', 's', 'u', 'b', 9, 0, |
| /* 2062 */ 'f', 'm', 's', 'u', 'b', 9, 0, |
| /* 2069 */ 'f', 'n', 'm', 's', 'u', 'b', 9, 0, |
| /* 2077 */ 's', 'q', 's', 'u', 'b', 9, 0, |
| /* 2084 */ 'u', 'q', 's', 'u', 'b', 9, 0, |
| /* 2091 */ 'r', 'e', 'v', 'b', 9, 0, |
| /* 2097 */ 's', 's', 'u', 'b', 'w', 'b', 9, 0, |
| /* 2105 */ 'u', 's', 'u', 'b', 'w', 'b', 9, 0, |
| /* 2113 */ 's', 'a', 'd', 'd', 'w', 'b', 9, 0, |
| /* 2121 */ 'u', 'a', 'd', 'd', 'w', 'b', 9, 0, |
| /* 2129 */ 'l', 'd', 's', 'm', 'a', 'x', 'b', 9, 0, |
| /* 2138 */ 'l', 'd', 'u', 'm', 'a', 'x', 'b', 9, 0, |
| /* 2147 */ 'p', 'a', 'c', 'd', 'z', 'b', 9, 0, |
| /* 2155 */ 'a', 'u', 't', 'd', 'z', 'b', 9, 0, |
| /* 2163 */ 'p', 'a', 'c', 'i', 'z', 'b', 9, 0, |
| /* 2171 */ 'a', 'u', 't', 'i', 'z', 'b', 9, 0, |
| /* 2179 */ 's', 'h', 'a', '1', 'c', 9, 0, |
| /* 2186 */ 's', 'b', 'c', 9, 0, |
| /* 2191 */ 'a', 'd', 'c', 9, 0, |
| /* 2196 */ 'b', 'i', 'c', 9, 0, |
| /* 2201 */ 'a', 'e', 's', 'i', 'm', 'c', 9, 0, |
| /* 2209 */ 'a', 'e', 's', 'm', 'c', 9, 0, |
| /* 2216 */ 'c', 's', 'i', 'n', 'c', 9, 0, |
| /* 2223 */ 'h', 'v', 'c', 9, 0, |
| /* 2228 */ 's', 'v', 'c', 9, 0, |
| /* 2233 */ 'l', 'd', '1', 'd', 9, 0, |
| /* 2239 */ 'l', 'd', 'f', 'f', '1', 'd', 9, 0, |
| /* 2247 */ 'l', 'd', 'n', 'f', '1', 'd', 9, 0, |
| /* 2255 */ 'l', 'd', 'n', 't', '1', 'd', 9, 0, |
| /* 2263 */ 's', 't', 'n', 't', '1', 'd', 9, 0, |
| /* 2271 */ 's', 't', '1', 'd', 9, 0, |
| /* 2277 */ 'l', 'd', '2', 'd', 9, 0, |
| /* 2283 */ 's', 't', '2', 'd', 9, 0, |
| /* 2289 */ 'l', 'd', '3', 'd', 9, 0, |
| /* 2295 */ 's', 't', '3', 'd', 9, 0, |
| /* 2301 */ 'l', 'd', '4', 'd', 9, 0, |
| /* 2307 */ 's', 't', '4', 'd', 9, 0, |
| /* 2313 */ 'f', 'm', 'a', 'd', 9, 0, |
| /* 2319 */ 'f', 'n', 'm', 'a', 'd', 9, 0, |
| /* 2326 */ 'f', 't', 'm', 'a', 'd', 9, 0, |
| /* 2333 */ 'f', 'a', 'b', 'd', 9, 0, |
| /* 2339 */ 's', 'a', 'b', 'd', 9, 0, |
| /* 2345 */ 'u', 'a', 'b', 'd', 9, 0, |
| /* 2351 */ 'x', 'p', 'a', 'c', 'd', 9, 0, |
| /* 2358 */ 's', 'q', 'd', 'e', 'c', 'd', 9, 0, |
| /* 2366 */ 'u', 'q', 'd', 'e', 'c', 'd', 9, 0, |
| /* 2374 */ 's', 'q', 'i', 'n', 'c', 'd', 9, 0, |
| /* 2382 */ 'u', 'q', 'i', 'n', 'c', 'd', 9, 0, |
| /* 2390 */ 'f', 'c', 'a', 'd', 'd', 9, 0, |
| /* 2397 */ 's', 'q', 'c', 'a', 'd', 'd', 9, 0, |
| /* 2405 */ 'l', 'd', 'a', 'd', 'd', 9, 0, |
| /* 2412 */ 'f', 'a', 'd', 'd', 9, 0, |
| /* 2418 */ 's', 'r', 'h', 'a', 'd', 'd', 9, 0, |
| /* 2426 */ 'u', 'r', 'h', 'a', 'd', 'd', 9, 0, |
| /* 2434 */ 's', 'h', 'a', 'd', 'd', 9, 0, |
| /* 2441 */ 'u', 'h', 'a', 'd', 'd', 9, 0, |
| /* 2448 */ 'f', 'm', 'a', 'd', 'd', 9, 0, |
| /* 2455 */ 'f', 'n', 'm', 'a', 'd', 'd', 9, 0, |
| /* 2463 */ 'u', 's', 'q', 'a', 'd', 'd', 9, 0, |
| /* 2471 */ 's', 'u', 'q', 'a', 'd', 'd', 9, 0, |
| /* 2479 */ 'p', 'r', 'f', 'd', 9, 0, |
| /* 2485 */ 'n', 'a', 'n', 'd', 9, 0, |
| /* 2491 */ 'l', 'd', '1', 'r', 'q', 'd', 9, 0, |
| /* 2499 */ 'l', 'd', '1', 'r', 'd', 9, 0, |
| /* 2506 */ 'a', 's', 'r', 'd', 9, 0, |
| /* 2512 */ 'a', 'e', 's', 'd', 9, 0, |
| /* 2518 */ 'c', 'n', 't', 'd', 9, 0, |
| /* 2524 */ 's', 'm', '4', 'e', 9, 0, |
| /* 2530 */ 's', 'p', 'l', 'i', 'c', 'e', 9, 0, |
| /* 2538 */ 'f', 'a', 'c', 'g', 'e', 9, 0, |
| /* 2545 */ 'w', 'h', 'i', 'l', 'e', 'g', 'e', 9, 0, |
| /* 2554 */ 'f', 'c', 'm', 'g', 'e', 9, 0, |
| /* 2561 */ 'c', 'm', 'p', 'g', 'e', 9, 0, |
| /* 2568 */ 'f', 's', 'c', 'a', 'l', 'e', 9, 0, |
| /* 2576 */ 'w', 'h', 'i', 'l', 'e', 'l', 'e', 9, 0, |
| /* 2585 */ 'f', 'c', 'm', 'l', 'e', 9, 0, |
| /* 2592 */ 'c', 'm', 'p', 'l', 'e', 9, 0, |
| /* 2599 */ 'f', 'c', 'm', 'n', 'e', 9, 0, |
| /* 2606 */ 'c', 't', 'e', 'r', 'm', 'n', 'e', 9, 0, |
| /* 2615 */ 'c', 'm', 'p', 'n', 'e', 9, 0, |
| /* 2622 */ 'f', 'r', 'e', 'c', 'p', 'e', 9, 0, |
| /* 2630 */ 'u', 'r', 'e', 'c', 'p', 'e', 9, 0, |
| /* 2638 */ 'f', 'c', 'c', 'm', 'p', 'e', 9, 0, |
| /* 2646 */ 'f', 'c', 'm', 'p', 'e', 9, 0, |
| /* 2653 */ 'a', 'e', 's', 'e', 9, 0, |
| /* 2659 */ 'p', 'f', 'a', 'l', 's', 'e', 9, 0, |
| /* 2667 */ 'f', 'r', 's', 'q', 'r', 't', 'e', 9, 0, |
| /* 2676 */ 'u', 'r', 's', 'q', 'r', 't', 'e', 9, 0, |
| /* 2685 */ 'p', 't', 'r', 'u', 'e', 9, 0, |
| /* 2692 */ 'u', 'd', 'f', 9, 0, |
| /* 2697 */ 'b', 'i', 'f', 9, 0, |
| /* 2702 */ 'r', 'm', 'i', 'f', 9, 0, |
| /* 2708 */ 's', 'c', 'v', 't', 'f', 9, 0, |
| /* 2715 */ 'u', 'c', 'v', 't', 'f', 9, 0, |
| /* 2722 */ 's', 't', '2', 'g', 9, 0, |
| /* 2728 */ 's', 't', 'z', '2', 'g', 9, 0, |
| /* 2735 */ 's', 'u', 'b', 'g', 9, 0, |
| /* 2741 */ 'a', 'd', 'd', 'g', 9, 0, |
| /* 2747 */ 'l', 'd', 'g', 9, 0, |
| /* 2752 */ 'f', 'n', 'e', 'g', 9, 0, |
| /* 2758 */ 's', 'q', 'n', 'e', 'g', 9, 0, |
| /* 2765 */ 'c', 's', 'n', 'e', 'g', 9, 0, |
| /* 2772 */ 'h', 'i', 's', 't', 's', 'e', 'g', 9, 0, |
| /* 2781 */ 'i', 'r', 'g', 9, 0, |
| /* 2786 */ 's', 't', 'g', 9, 0, |
| /* 2791 */ 's', 't', 'z', 'g', 9, 0, |
| /* 2797 */ 's', 'h', 'a', '1', 'h', 9, 0, |
| /* 2804 */ 'l', 'd', '1', 'h', 9, 0, |
| /* 2810 */ 'l', 'd', 'f', 'f', '1', 'h', 9, 0, |
| /* 2818 */ 'l', 'd', 'n', 'f', '1', 'h', 9, 0, |
| /* 2826 */ 'l', 'd', 'n', 't', '1', 'h', 9, 0, |
| /* 2834 */ 's', 't', 'n', 't', '1', 'h', 9, 0, |
| /* 2842 */ 's', 't', '1', 'h', 9, 0, |
| /* 2848 */ 's', 'h', 'a', '5', '1', '2', 'h', 9, 0, |
| /* 2857 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0, |
| /* 2865 */ 'l', 'd', '2', 'h', 9, 0, |
| /* 2871 */ 's', 't', '2', 'h', 9, 0, |
| /* 2877 */ 'l', 'd', '3', 'h', 9, 0, |
| /* 2883 */ 's', 't', '3', 'h', 9, 0, |
| /* 2889 */ 'l', 'd', '4', 'h', 9, 0, |
| /* 2895 */ 's', 't', '4', 'h', 9, 0, |
| /* 2901 */ 's', 'h', 'a', '2', '5', '6', 'h', 9, 0, |
| /* 2910 */ 'l', 'd', 'a', 'd', 'd', 'a', 'h', 9, 0, |
| /* 2919 */ 's', 'q', 'r', 'd', 'c', 'm', 'l', 'a', 'h', 9, 0, |
| /* 2930 */ 's', 'q', 'r', 'd', 'm', 'l', 'a', 'h', 9, 0, |
| /* 2940 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'h', 9, 0, |
| /* 2950 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'h', 9, 0, |
| /* 2960 */ 's', 'w', 'p', 'a', 'h', 9, 0, |
| /* 2967 */ 'l', 'd', 'c', 'l', 'r', 'a', 'h', 9, 0, |
| /* 2976 */ 'l', 'd', 'e', 'o', 'r', 'a', 'h', 9, 0, |
| /* 2985 */ 'c', 'a', 's', 'a', 'h', 9, 0, |
| /* 2992 */ 'l', 'd', 's', 'e', 't', 'a', 'h', 9, 0, |
| /* 3001 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'h', 9, 0, |
| /* 3011 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'h', 9, 0, |
| /* 3021 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0, |
| /* 3030 */ 's', 'q', 'd', 'e', 'c', 'h', 9, 0, |
| /* 3038 */ 'u', 'q', 'd', 'e', 'c', 'h', 9, 0, |
| /* 3046 */ 's', 'q', 'i', 'n', 'c', 'h', 9, 0, |
| /* 3054 */ 'u', 'q', 'i', 'n', 'c', 'h', 9, 0, |
| /* 3062 */ 'n', 'm', 'a', 't', 'c', 'h', 9, 0, |
| /* 3070 */ 'l', 'd', 'a', 'd', 'd', 'h', 9, 0, |
| /* 3078 */ 'p', 'r', 'f', 'h', 9, 0, |
| /* 3084 */ 'l', 'd', 'a', 'd', 'd', 'a', 'l', 'h', 9, 0, |
| /* 3094 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'l', 'h', 9, 0, |
| /* 3105 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'l', 'h', 9, 0, |
| /* 3116 */ 's', 'w', 'p', 'a', 'l', 'h', 9, 0, |
| /* 3124 */ 'l', 'd', 'c', 'l', 'r', 'a', 'l', 'h', 9, 0, |
| /* 3134 */ 'l', 'd', 'e', 'o', 'r', 'a', 'l', 'h', 9, 0, |
| /* 3144 */ 'c', 'a', 's', 'a', 'l', 'h', 9, 0, |
| /* 3152 */ 'l', 'd', 's', 'e', 't', 'a', 'l', 'h', 9, 0, |
| /* 3162 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'l', 'h', 9, 0, |
| /* 3173 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'l', 'h', 9, 0, |
| /* 3184 */ 'l', 'd', 'a', 'd', 'd', 'l', 'h', 9, 0, |
| /* 3193 */ 'l', 'd', 's', 'm', 'i', 'n', 'l', 'h', 9, 0, |
| /* 3203 */ 'l', 'd', 'u', 'm', 'i', 'n', 'l', 'h', 9, 0, |
| /* 3213 */ 's', 'w', 'p', 'l', 'h', 9, 0, |
| /* 3220 */ 'l', 'd', 'c', 'l', 'r', 'l', 'h', 9, 0, |
| /* 3229 */ 'l', 'd', 'e', 'o', 'r', 'l', 'h', 9, 0, |
| /* 3238 */ 'c', 'a', 's', 'l', 'h', 9, 0, |
| /* 3245 */ 'l', 'd', 's', 'e', 't', 'l', 'h', 9, 0, |
| /* 3254 */ 's', 'q', 'd', 'm', 'u', 'l', 'h', 9, 0, |
| /* 3263 */ 's', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 9, 0, |
| /* 3273 */ 's', 'm', 'u', 'l', 'h', 9, 0, |
| /* 3280 */ 'u', 'm', 'u', 'l', 'h', 9, 0, |
| /* 3287 */ 'l', 'd', 's', 'm', 'a', 'x', 'l', 'h', 9, 0, |
| /* 3297 */ 'l', 'd', 'u', 'm', 'a', 'x', 'l', 'h', 9, 0, |
| /* 3307 */ 'l', 'd', 's', 'm', 'i', 'n', 'h', 9, 0, |
| /* 3316 */ 'l', 'd', 'u', 'm', 'i', 'n', 'h', 9, 0, |
| /* 3325 */ 's', 'w', 'p', 'h', 9, 0, |
| /* 3331 */ 'l', 'd', '1', 'r', 'q', 'h', 9, 0, |
| /* 3339 */ 'l', 'd', '1', 'r', 'h', 9, 0, |
| /* 3346 */ 'l', 'd', 'a', 'r', 'h', 9, 0, |
| /* 3353 */ 'l', 'd', 'l', 'a', 'r', 'h', 9, 0, |
| /* 3361 */ 'l', 'd', 'r', 'h', 9, 0, |
| /* 3367 */ 'l', 'd', 'c', 'l', 'r', 'h', 9, 0, |
| /* 3375 */ 's', 't', 'l', 'l', 'r', 'h', 9, 0, |
| /* 3383 */ 's', 't', 'l', 'r', 'h', 9, 0, |
| /* 3390 */ 'l', 'd', 'e', 'o', 'r', 'h', 9, 0, |
| /* 3398 */ 'l', 'd', 'a', 'p', 'r', 'h', 9, 0, |
| /* 3406 */ 'l', 'd', 't', 'r', 'h', 9, 0, |
| /* 3413 */ 's', 't', 'r', 'h', 9, 0, |
| /* 3419 */ 's', 't', 't', 'r', 'h', 9, 0, |
| /* 3426 */ 'l', 'd', 'u', 'r', 'h', 9, 0, |
| /* 3433 */ 's', 't', 'l', 'u', 'r', 'h', 9, 0, |
| /* 3441 */ 'l', 'd', 'a', 'p', 'u', 'r', 'h', 9, 0, |
| /* 3450 */ 's', 't', 'u', 'r', 'h', 9, 0, |
| /* 3457 */ 'l', 'd', 'a', 'x', 'r', 'h', 9, 0, |
| /* 3465 */ 'l', 'd', 'x', 'r', 'h', 9, 0, |
| /* 3472 */ 's', 't', 'l', 'x', 'r', 'h', 9, 0, |
| /* 3480 */ 's', 't', 'x', 'r', 'h', 9, 0, |
| /* 3487 */ 'l', 'd', '1', 's', 'h', 9, 0, |
| /* 3494 */ 'l', 'd', 'f', 'f', '1', 's', 'h', 9, 0, |
| /* 3503 */ 'l', 'd', 'n', 'f', '1', 's', 'h', 9, 0, |
| /* 3512 */ 'l', 'd', 'n', 't', '1', 's', 'h', 9, 0, |
| /* 3521 */ 'c', 'a', 's', 'h', 9, 0, |
| /* 3527 */ 's', 'q', 'r', 'd', 'm', 'l', 's', 'h', 9, 0, |
| /* 3537 */ 'l', 'd', '1', 'r', 's', 'h', 9, 0, |
| /* 3545 */ 'l', 'd', 'r', 's', 'h', 9, 0, |
| /* 3552 */ 'l', 'd', 't', 'r', 's', 'h', 9, 0, |
| /* 3560 */ 'l', 'd', 'u', 'r', 's', 'h', 9, 0, |
| /* 3568 */ 'l', 'd', 'a', 'p', 'u', 'r', 's', 'h', 9, 0, |
| /* 3578 */ 'l', 'd', 's', 'e', 't', 'h', 9, 0, |
| /* 3586 */ 'c', 'n', 't', 'h', 9, 0, |
| /* 3592 */ 's', 'x', 't', 'h', 9, 0, |
| /* 3598 */ 'u', 'x', 't', 'h', 9, 0, |
| /* 3604 */ 'r', 'e', 'v', 'h', 9, 0, |
| /* 3610 */ 'l', 'd', 's', 'm', 'a', 'x', 'h', 9, 0, |
| /* 3619 */ 'l', 'd', 'u', 'm', 'a', 'x', 'h', 9, 0, |
| /* 3628 */ 'x', 'p', 'a', 'c', 'i', 9, 0, |
| /* 3635 */ 'w', 'h', 'i', 'l', 'e', 'h', 'i', 9, 0, |
| /* 3644 */ 'p', 'u', 'n', 'p', 'k', 'h', 'i', 9, 0, |
| /* 3653 */ 's', 'u', 'n', 'p', 'k', 'h', 'i', 9, 0, |
| /* 3662 */ 'u', 'u', 'n', 'p', 'k', 'h', 'i', 9, 0, |
| /* 3671 */ 'c', 'm', 'h', 'i', 9, 0, |
| /* 3677 */ 'c', 'm', 'p', 'h', 'i', 9, 0, |
| /* 3684 */ 's', 'l', 'i', 9, 0, |
| /* 3689 */ 'g', 'm', 'i', 9, 0, |
| /* 3694 */ 'm', 'v', 'n', 'i', 9, 0, |
| /* 3700 */ 's', 'r', 'i', 9, 0, |
| /* 3705 */ 'f', 'r', 'i', 'n', 't', 'i', 9, 0, |
| /* 3713 */ 'm', 'o', 'v', 'i', 9, 0, |
| /* 3719 */ 'b', 'r', 'k', 9, 0, |
| /* 3724 */ 'm', 'o', 'v', 'k', 9, 0, |
| /* 3730 */ 's', 'a', 'b', 'a', 'l', 9, 0, |
| /* 3737 */ 'u', 'a', 'b', 'a', 'l', 9, 0, |
| /* 3744 */ 'l', 'd', 'a', 'd', 'd', 'a', 'l', 9, 0, |
| /* 3753 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', 9, 0, |
| /* 3762 */ 'f', 'm', 'l', 'a', 'l', 9, 0, |
| /* 3769 */ 's', 'm', 'l', 'a', 'l', 9, 0, |
| /* 3776 */ 'u', 'm', 'l', 'a', 'l', 9, 0, |
| /* 3783 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'l', 9, 0, |
| /* 3793 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'l', 9, 0, |
| /* 3803 */ 'c', 'a', 's', 'p', 'a', 'l', 9, 0, |
| /* 3811 */ 's', 'w', 'p', 'a', 'l', 9, 0, |
| /* 3818 */ 'l', 'd', 'c', 'l', 'r', 'a', 'l', 9, 0, |
| /* 3827 */ 'l', 'd', 'e', 'o', 'r', 'a', 'l', 9, 0, |
| /* 3836 */ 'c', 'a', 's', 'a', 'l', 9, 0, |
| /* 3843 */ 'l', 'd', 's', 'e', 't', 'a', 'l', 9, 0, |
| /* 3852 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'l', 9, 0, |
| /* 3862 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'l', 9, 0, |
| /* 3872 */ 't', 'b', 'l', 9, 0, |
| /* 3877 */ 's', 'm', 's', 'u', 'b', 'l', 9, 0, |
| /* 3885 */ 'u', 'm', 's', 'u', 'b', 'l', 9, 0, |
| /* 3893 */ 's', 's', 'u', 'b', 'l', 9, 0, |
| /* 3900 */ 'u', 's', 'u', 'b', 'l', 9, 0, |
| /* 3907 */ 's', 'a', 'b', 'd', 'l', 9, 0, |
| /* 3914 */ 'u', 'a', 'b', 'd', 'l', 9, 0, |
| /* 3921 */ 'l', 'd', 'a', 'd', 'd', 'l', 9, 0, |
| /* 3929 */ 's', 'm', 'a', 'd', 'd', 'l', 9, 0, |
| /* 3937 */ 'u', 'm', 'a', 'd', 'd', 'l', 9, 0, |
| /* 3945 */ 's', 'a', 'd', 'd', 'l', 9, 0, |
| /* 3952 */ 'u', 'a', 'd', 'd', 'l', 9, 0, |
| /* 3959 */ 't', 'c', 'a', 'n', 'c', 'e', 'l', 9, 0, |
| /* 3968 */ 'f', 'c', 's', 'e', 'l', 9, 0, |
| /* 3975 */ 'f', 't', 's', 's', 'e', 'l', 9, 0, |
| /* 3983 */ 's', 'q', 's', 'h', 'l', 9, 0, |
| /* 3990 */ 'u', 'q', 's', 'h', 'l', 9, 0, |
| /* 3997 */ 's', 'q', 'r', 's', 'h', 'l', 9, 0, |
| /* 4005 */ 'u', 'q', 'r', 's', 'h', 'l', 9, 0, |
| /* 4013 */ 's', 'r', 's', 'h', 'l', 9, 0, |
| /* 4020 */ 'u', 'r', 's', 'h', 'l', 9, 0, |
| /* 4027 */ 's', 's', 'h', 'l', 9, 0, |
| /* 4033 */ 'u', 's', 'h', 'l', 9, 0, |
| /* 4039 */ 's', 's', 'h', 'l', 'l', 9, 0, |
| /* 4046 */ 'u', 's', 'h', 'l', 'l', 9, 0, |
| /* 4053 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', 9, 0, |
| /* 4062 */ 'p', 'm', 'u', 'l', 'l', 9, 0, |
| /* 4069 */ 's', 'm', 'u', 'l', 'l', 9, 0, |
| /* 4076 */ 'u', 'm', 'u', 'l', 'l', 9, 0, |
| /* 4083 */ 'l', 'd', 's', 'm', 'i', 'n', 'l', 9, 0, |
| /* 4092 */ 'l', 'd', 'u', 'm', 'i', 'n', 'l', 9, 0, |
| /* 4101 */ 'a', 'd', 'd', 'p', 'l', 9, 0, |
| /* 4108 */ 'c', 'a', 's', 'p', 'l', 9, 0, |
| /* 4115 */ 's', 'w', 'p', 'l', 9, 0, |
| /* 4121 */ 'l', 'd', 'c', 'l', 'r', 'l', 9, 0, |
| /* 4129 */ 'l', 'd', 'e', 'o', 'r', 'l', 9, 0, |
| /* 4137 */ 'c', 'a', 's', 'l', 9, 0, |
| /* 4143 */ 'n', 'b', 's', 'l', 9, 0, |
| /* 4149 */ 's', 'q', 'd', 'm', 'l', 's', 'l', 9, 0, |
| /* 4158 */ 'f', 'm', 'l', 's', 'l', 9, 0, |
| /* 4165 */ 's', 'm', 'l', 's', 'l', 9, 0, |
| /* 4172 */ 'u', 'm', 'l', 's', 'l', 9, 0, |
| /* 4179 */ 's', 'y', 's', 'l', 9, 0, |
| /* 4185 */ 'l', 'd', 's', 'e', 't', 'l', 9, 0, |
| /* 4193 */ 'f', 'c', 'v', 't', 'l', 9, 0, |
| /* 4200 */ 'f', 'm', 'u', 'l', 9, 0, |
| /* 4206 */ 'f', 'n', 'm', 'u', 'l', 9, 0, |
| /* 4213 */ 'p', 'm', 'u', 'l', 9, 0, |
| /* 4219 */ 'f', 't', 's', 'm', 'u', 'l', 9, 0, |
| /* 4227 */ 'a', 'd', 'd', 'v', 'l', 9, 0, |
| /* 4234 */ 'r', 'd', 'v', 'l', 9, 0, |
| /* 4240 */ 'l', 'd', 's', 'm', 'a', 'x', 'l', 9, 0, |
| /* 4249 */ 'l', 'd', 'u', 'm', 'a', 'x', 'l', 9, 0, |
| /* 4258 */ 's', 'h', 'a', '1', 'm', 9, 0, |
| /* 4265 */ 's', 'b', 'f', 'm', 9, 0, |
| /* 4271 */ 'u', 'b', 'f', 'm', 9, 0, |
| /* 4277 */ 'p', 'r', 'f', 'm', 9, 0, |
| /* 4283 */ 'l', 'd', 'g', 'm', 9, 0, |
| /* 4289 */ 's', 't', 'g', 'm', 9, 0, |
| /* 4295 */ 's', 't', 'z', 'g', 'm', 9, 0, |
| /* 4302 */ 'f', 'm', 'i', 'n', 'n', 'm', 9, 0, |
| /* 4310 */ 'f', 'm', 'a', 'x', 'n', 'm', 9, 0, |
| /* 4318 */ 'd', 'u', 'p', 'm', 9, 0, |
| /* 4324 */ 'f', 'r', 'i', 'n', 't', 'm', 9, 0, |
| /* 4332 */ 'p', 'r', 'f', 'u', 'm', 9, 0, |
| /* 4339 */ 'b', 's', 'l', '1', 'n', 9, 0, |
| /* 4346 */ 'b', 's', 'l', '2', 'n', 9, 0, |
| /* 4353 */ 'r', 's', 'u', 'b', 'h', 'n', 9, 0, |
| /* 4361 */ 'r', 'a', 'd', 'd', 'h', 'n', 9, 0, |
| /* 4369 */ 'f', 'm', 'i', 'n', 9, 0, |
| /* 4375 */ 'l', 'd', 's', 'm', 'i', 'n', 9, 0, |
| /* 4383 */ 'l', 'd', 'u', 'm', 'i', 'n', 9, 0, |
| /* 4391 */ 'b', 'r', 'k', 'n', 9, 0, |
| /* 4397 */ 'c', 'c', 'm', 'n', 9, 0, |
| /* 4403 */ 'e', 'o', 'n', 9, 0, |
| /* 4408 */ 's', 'q', 's', 'h', 'r', 'n', 9, 0, |
| /* 4416 */ 'u', 'q', 's', 'h', 'r', 'n', 9, 0, |
| /* 4424 */ 's', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, |
| /* 4433 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, |
| /* 4442 */ 'o', 'r', 'n', 9, 0, |
| /* 4447 */ 'f', 'r', 'i', 'n', 't', 'n', 9, 0, |
| /* 4455 */ 'f', 'c', 'v', 't', 'n', 9, 0, |
| /* 4462 */ 's', 'q', 'x', 't', 'n', 9, 0, |
| /* 4469 */ 'u', 'q', 'x', 't', 'n', 9, 0, |
| /* 4476 */ 's', 'q', 's', 'h', 'r', 'u', 'n', 9, 0, |
| /* 4485 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', 9, 0, |
| /* 4495 */ 's', 'q', 'x', 't', 'u', 'n', 9, 0, |
| /* 4503 */ 'm', 'o', 'v', 'n', 9, 0, |
| /* 4509 */ 'f', 'c', 'v', 't', 'x', 'n', 9, 0, |
| /* 4517 */ 'w', 'h', 'i', 'l', 'e', 'l', 'o', 9, 0, |
| /* 4526 */ 'p', 'u', 'n', 'p', 'k', 'l', 'o', 9, 0, |
| /* 4535 */ 's', 'u', 'n', 'p', 'k', 'l', 'o', 9, 0, |
| /* 4544 */ 'u', 'u', 'n', 'p', 'k', 'l', 'o', 9, 0, |
| /* 4553 */ 'c', 'm', 'p', 'l', 'o', 9, 0, |
| /* 4560 */ 'f', 'c', 'm', 'u', 'o', 9, 0, |
| /* 4567 */ 's', 'h', 'a', '1', 'p', 9, 0, |
| /* 4574 */ 's', 'u', 'b', 'p', 9, 0, |
| /* 4580 */ 's', 'q', 'd', 'e', 'c', 'p', 9, 0, |
| /* 4588 */ 'u', 'q', 'd', 'e', 'c', 'p', 9, 0, |
| /* 4596 */ 's', 'q', 'i', 'n', 'c', 'p', 9, 0, |
| /* 4604 */ 'u', 'q', 'i', 'n', 'c', 'p', 9, 0, |
| /* 4612 */ 'f', 'a', 'd', 'd', 'p', 9, 0, |
| /* 4619 */ 'l', 'd', 'p', 9, 0, |
| /* 4624 */ 'b', 'd', 'e', 'p', 9, 0, |
| /* 4630 */ 's', 't', 'g', 'p', 9, 0, |
| /* 4636 */ 's', 'a', 'd', 'a', 'l', 'p', 9, 0, |
| /* 4644 */ 'u', 'a', 'd', 'a', 'l', 'p', 9, 0, |
| /* 4652 */ 's', 'a', 'd', 'd', 'l', 'p', 9, 0, |
| /* 4660 */ 'u', 'a', 'd', 'd', 'l', 'p', 9, 0, |
| /* 4668 */ 'f', 'c', 'c', 'm', 'p', 9, 0, |
| /* 4675 */ 'f', 'c', 'm', 'p', 9, 0, |
| /* 4681 */ 'f', 'm', 'i', 'n', 'n', 'm', 'p', 9, 0, |
| /* 4690 */ 'f', 'm', 'a', 'x', 'n', 'm', 'p', 9, 0, |
| /* 4699 */ 'l', 'd', 'n', 'p', 9, 0, |
| /* 4705 */ 'f', 'm', 'i', 'n', 'p', 9, 0, |
| /* 4712 */ 's', 'm', 'i', 'n', 'p', 9, 0, |
| /* 4719 */ 'u', 'm', 'i', 'n', 'p', 9, 0, |
| /* 4726 */ 's', 't', 'n', 'p', 9, 0, |
| /* 4732 */ 'a', 'd', 'r', 'p', 9, 0, |
| /* 4738 */ 'b', 'g', 'r', 'p', 9, 0, |
| /* 4744 */ 'c', 'a', 's', 'p', 9, 0, |
| /* 4750 */ 'c', 'n', 't', 'p', 9, 0, |
| /* 4756 */ 'f', 'r', 'i', 'n', 't', 'p', 9, 0, |
| /* 4764 */ 's', 't', 'p', 9, 0, |
| /* 4769 */ 'f', 'd', 'u', 'p', 9, 0, |
| /* 4775 */ 's', 'w', 'p', 9, 0, |
| /* 4780 */ 'l', 'd', 'a', 'x', 'p', 9, 0, |
| /* 4787 */ 'f', 'm', 'a', 'x', 'p', 9, 0, |
| /* 4794 */ 's', 'm', 'a', 'x', 'p', 9, 0, |
| /* 4801 */ 'u', 'm', 'a', 'x', 'p', 9, 0, |
| /* 4808 */ 'l', 'd', 'x', 'p', 9, 0, |
| /* 4814 */ 's', 't', 'l', 'x', 'p', 9, 0, |
| /* 4821 */ 's', 't', 'x', 'p', 9, 0, |
| /* 4827 */ 'f', 'c', 'm', 'e', 'q', 9, 0, |
| /* 4834 */ 'c', 't', 'e', 'r', 'm', 'e', 'q', 9, 0, |
| /* 4843 */ 'c', 'm', 'p', 'e', 'q', 9, 0, |
| /* 4850 */ 'l', 'd', '1', 'r', 9, 0, |
| /* 4856 */ 'l', 'd', '2', 'r', 9, 0, |
| /* 4862 */ 'l', 'd', '3', 'r', 9, 0, |
| /* 4868 */ 'l', 'd', '4', 'r', 9, 0, |
| /* 4874 */ 'l', 'd', 'a', 'r', 9, 0, |
| /* 4880 */ 'l', 'd', 'l', 'a', 'r', 9, 0, |
| /* 4887 */ 'x', 'a', 'r', 9, 0, |
| /* 4892 */ 'f', 's', 'u', 'b', 'r', 9, 0, |
| /* 4899 */ 's', 'h', 's', 'u', 'b', 'r', 9, 0, |
| /* 4907 */ 'u', 'h', 's', 'u', 'b', 'r', 9, 0, |
| /* 4915 */ 's', 'q', 's', 'u', 'b', 'r', 9, 0, |
| /* 4923 */ 'u', 'q', 's', 'u', 'b', 'r', 9, 0, |
| /* 4931 */ 'a', 'd', 'r', 9, 0, |
| /* 4936 */ 'l', 'd', 'r', 9, 0, |
| /* 4941 */ 'r', 'd', 'f', 'f', 'r', 9, 0, |
| /* 4948 */ 'w', 'r', 'f', 'f', 'r', 9, 0, |
| /* 4955 */ 's', 'r', 's', 'h', 'r', 9, 0, |
| /* 4962 */ 'u', 'r', 's', 'h', 'r', 9, 0, |
| /* 4969 */ 's', 's', 'h', 'r', 9, 0, |
| /* 4975 */ 'u', 's', 'h', 'r', 9, 0, |
| /* 4981 */ 'b', 'l', 'r', 9, 0, |
| /* 4986 */ 'l', 'd', 'c', 'l', 'r', 9, 0, |
| /* 4993 */ 's', 'q', 's', 'h', 'l', 'r', 9, 0, |
| /* 5001 */ 'u', 'q', 's', 'h', 'l', 'r', 9, 0, |
| /* 5009 */ 's', 'q', 'r', 's', 'h', 'l', 'r', 9, 0, |
| /* 5018 */ 'u', 'q', 'r', 's', 'h', 'l', 'r', 9, 0, |
| /* 5027 */ 's', 'r', 's', 'h', 'l', 'r', 9, 0, |
| /* 5035 */ 'u', 'r', 's', 'h', 'l', 'r', 9, 0, |
| /* 5043 */ 's', 't', 'l', 'l', 'r', 9, 0, |
| /* 5050 */ 'l', 's', 'l', 'r', 9, 0, |
| /* 5056 */ 's', 't', 'l', 'r', 9, 0, |
| /* 5062 */ 'l', 'd', 'e', 'o', 'r', 9, 0, |
| /* 5069 */ 'n', 'o', 'r', 9, 0, |
| /* 5074 */ 'r', 'o', 'r', 9, 0, |
| /* 5079 */ 'l', 'd', 'a', 'p', 'r', 9, 0, |
| /* 5086 */ 'o', 'r', 'r', 9, 0, |
| /* 5091 */ 'a', 's', 'r', 'r', 9, 0, |
| /* 5097 */ 'l', 's', 'r', 'r', 9, 0, |
| /* 5103 */ 'a', 's', 'r', 9, 0, |
| /* 5108 */ 'l', 's', 'r', 9, 0, |
| /* 5113 */ 'm', 's', 'r', 9, 0, |
| /* 5118 */ 'i', 'n', 's', 'r', 9, 0, |
| /* 5124 */ 'l', 'd', 't', 'r', 9, 0, |
| /* 5130 */ 's', 't', 'r', 9, 0, |
| /* 5135 */ 's', 't', 't', 'r', 9, 0, |
| /* 5141 */ 'e', 'x', 't', 'r', 9, 0, |
| /* 5147 */ 'l', 'd', 'u', 'r', 9, 0, |
| /* 5153 */ 's', 't', 'l', 'u', 'r', 9, 0, |
| /* 5160 */ 'l', 'd', 'a', 'p', 'u', 'r', 9, 0, |
| /* 5168 */ 's', 't', 'u', 'r', 9, 0, |
| /* 5174 */ 'f', 'd', 'i', 'v', 'r', 9, 0, |
| /* 5181 */ 's', 'd', 'i', 'v', 'r', 9, 0, |
| /* 5188 */ 'u', 'd', 'i', 'v', 'r', 9, 0, |
| /* 5195 */ 'w', 'h', 'i', 'l', 'e', 'w', 'r', 9, 0, |
| /* 5204 */ 'l', 'd', 'a', 'x', 'r', 9, 0, |
| /* 5211 */ 'l', 'd', 'x', 'r', 9, 0, |
| /* 5217 */ 's', 't', 'l', 'x', 'r', 9, 0, |
| /* 5224 */ 's', 't', 'x', 'r', 9, 0, |
| /* 5230 */ 'c', 'a', 's', 9, 0, |
| /* 5235 */ 'b', 'r', 'k', 'a', 's', 9, 0, |
| /* 5242 */ 'b', 'r', 'k', 'p', 'a', 's', 9, 0, |
| /* 5250 */ 'f', 'c', 'v', 't', 'a', 's', 9, 0, |
| /* 5258 */ 'f', 'a', 'b', 's', 9, 0, |
| /* 5264 */ 's', 'q', 'a', 'b', 's', 9, 0, |
| /* 5271 */ 'b', 'r', 'k', 'b', 's', 9, 0, |
| /* 5278 */ 'b', 'r', 'k', 'p', 'b', 's', 9, 0, |
| /* 5286 */ 's', 'u', 'b', 's', 9, 0, |
| /* 5292 */ 's', 'b', 'c', 's', 9, 0, |
| /* 5298 */ 'a', 'd', 'c', 's', 9, 0, |
| /* 5304 */ 'b', 'i', 'c', 's', 9, 0, |
| /* 5310 */ 'a', 'd', 'd', 's', 9, 0, |
| /* 5316 */ 'n', 'a', 'n', 'd', 's', 9, 0, |
| /* 5323 */ 'p', 't', 'r', 'u', 'e', 's', 9, 0, |
| /* 5331 */ 'w', 'h', 'i', 'l', 'e', 'h', 's', 9, 0, |
| /* 5340 */ 'c', 'm', 'h', 's', 9, 0, |
| /* 5346 */ 'c', 'm', 'p', 'h', 's', 9, 0, |
| /* 5353 */ 'c', 'l', 's', 9, 0, |
| /* 5358 */ 'w', 'h', 'i', 'l', 'e', 'l', 's', 9, 0, |
| /* 5367 */ 'f', 'm', 'l', 's', 9, 0, |
| /* 5373 */ 'f', 'n', 'm', 'l', 's', 9, 0, |
| /* 5380 */ 'c', 'm', 'p', 'l', 's', 9, 0, |
| /* 5387 */ 'f', 'c', 'v', 't', 'm', 's', 9, 0, |
| /* 5395 */ 'i', 'n', 's', 9, 0, |
| /* 5400 */ 'b', 'r', 'k', 'n', 's', 9, 0, |
| /* 5407 */ 'o', 'r', 'n', 's', 9, 0, |
| /* 5413 */ 'f', 'c', 'v', 't', 'n', 's', 9, 0, |
| /* 5421 */ 's', 'u', 'b', 'p', 's', 9, 0, |
| /* 5428 */ 'f', 'r', 'e', 'c', 'p', 's', 9, 0, |
| /* 5436 */ 'f', 'c', 'v', 't', 'p', 's', 9, 0, |
| /* 5444 */ 'r', 'd', 'f', 'f', 'r', 's', 9, 0, |
| /* 5452 */ 'm', 'r', 's', 9, 0, |
| /* 5457 */ 'e', 'o', 'r', 's', 9, 0, |
| /* 5463 */ 'n', 'o', 'r', 's', 9, 0, |
| /* 5469 */ 'o', 'r', 'r', 's', 9, 0, |
| /* 5475 */ 'f', 'r', 's', 'q', 'r', 't', 's', 9, 0, |
| /* 5484 */ 's', 'y', 's', 9, 0, |
| /* 5489 */ 'f', 'c', 'v', 't', 'z', 's', 9, 0, |
| /* 5497 */ 'f', 'j', 'c', 'v', 't', 'z', 's', 9, 0, |
| /* 5506 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', 'b', 't', 9, 0, |
| /* 5517 */ 's', 's', 'u', 'b', 'l', 'b', 't', 9, 0, |
| /* 5526 */ 's', 'a', 'd', 'd', 'l', 'b', 't', 9, 0, |
| /* 5535 */ 's', 'q', 'd', 'm', 'l', 's', 'l', 'b', 't', 9, 0, |
| /* 5546 */ 'e', 'o', 'r', 'b', 't', 9, 0, |
| /* 5553 */ 'c', 'o', 'm', 'p', 'a', 'c', 't', 9, 0, |
| /* 5562 */ 'r', 'e', 't', 9, 0, |
| /* 5567 */ 'l', 'd', 's', 'e', 't', 9, 0, |
| /* 5574 */ 'f', 'a', 'c', 'g', 't', 9, 0, |
| /* 5581 */ 'w', 'h', 'i', 'l', 'e', 'g', 't', 9, 0, |
| /* 5590 */ 'f', 'c', 'm', 'g', 't', 9, 0, |
| /* 5597 */ 'c', 'm', 'p', 'g', 't', 9, 0, |
| /* 5604 */ 'r', 'b', 'i', 't', 9, 0, |
| /* 5610 */ 's', 'a', 'b', 'a', 'l', 't', 9, 0, |
| /* 5618 */ 'u', 'a', 'b', 'a', 'l', 't', 9, 0, |
| /* 5626 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', 't', 9, 0, |
| /* 5636 */ 'f', 'm', 'l', 'a', 'l', 't', 9, 0, |
| /* 5644 */ 's', 'm', 'l', 'a', 'l', 't', 9, 0, |
| /* 5652 */ 'u', 'm', 'l', 'a', 'l', 't', 9, 0, |
| /* 5660 */ 's', 's', 'u', 'b', 'l', 't', 9, 0, |
| /* 5668 */ 'u', 's', 'u', 'b', 'l', 't', 9, 0, |
| /* 5676 */ 's', 'b', 'c', 'l', 't', 9, 0, |
| /* 5683 */ 'a', 'd', 'c', 'l', 't', 9, 0, |
| /* 5690 */ 's', 'a', 'b', 'd', 'l', 't', 9, 0, |
| /* 5698 */ 'u', 'a', 'b', 'd', 'l', 't', 9, 0, |
| /* 5706 */ 's', 'a', 'd', 'd', 'l', 't', 9, 0, |
| /* 5714 */ 'u', 'a', 'd', 'd', 'l', 't', 9, 0, |
| /* 5722 */ 'w', 'h', 'i', 'l', 'e', 'l', 't', 9, 0, |
| /* 5731 */ 'h', 'l', 't', 9, 0, |
| /* 5736 */ 's', 's', 'h', 'l', 'l', 't', 9, 0, |
| /* 5744 */ 'u', 's', 'h', 'l', 'l', 't', 9, 0, |
| /* 5752 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', 't', 9, 0, |
| /* 5762 */ 'p', 'm', 'u', 'l', 'l', 't', 9, 0, |
| /* 5770 */ 's', 'm', 'u', 'l', 'l', 't', 9, 0, |
| /* 5778 */ 'u', 'm', 'u', 'l', 'l', 't', 9, 0, |
| /* 5786 */ 'f', 'c', 'm', 'l', 't', 9, 0, |
| /* 5793 */ 'c', 'm', 'p', 'l', 't', 9, 0, |
| /* 5800 */ 's', 'q', 'd', 'm', 'l', 's', 'l', 't', 9, 0, |
| /* 5810 */ 'f', 'm', 'l', 's', 'l', 't', 9, 0, |
| /* 5818 */ 's', 'm', 'l', 's', 'l', 't', 9, 0, |
| /* 5826 */ 'u', 'm', 'l', 's', 'l', 't', 9, 0, |
| /* 5834 */ 'f', 'c', 'v', 't', 'l', 't', 9, 0, |
| /* 5842 */ 'h', 'i', 's', 't', 'c', 'n', 't', 9, 0, |
| /* 5851 */ 'r', 's', 'u', 'b', 'h', 'n', 't', 9, 0, |
| /* 5860 */ 'r', 'a', 'd', 'd', 'h', 'n', 't', 9, 0, |
| /* 5869 */ 'h', 'i', 'n', 't', 9, 0, |
| /* 5875 */ 's', 'q', 's', 'h', 'r', 'n', 't', 9, 0, |
| /* 5884 */ 'u', 'q', 's', 'h', 'r', 'n', 't', 9, 0, |
| /* 5893 */ 's', 'q', 'r', 's', 'h', 'r', 'n', 't', 9, 0, |
| /* 5903 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', 't', 9, 0, |
| /* 5913 */ 'f', 'c', 'v', 't', 'n', 't', 9, 0, |
| /* 5921 */ 's', 'q', 'x', 't', 'n', 't', 9, 0, |
| /* 5929 */ 'u', 'q', 'x', 't', 'n', 't', 9, 0, |
| /* 5937 */ 's', 'q', 's', 'h', 'r', 'u', 'n', 't', 9, 0, |
| /* 5947 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', 't', 9, 0, |
| /* 5958 */ 's', 'q', 'x', 't', 'u', 'n', 't', 9, 0, |
| /* 5967 */ 'f', 'c', 'v', 't', 'x', 'n', 't', 9, 0, |
| /* 5976 */ 'c', 'd', 'o', 't', 9, 0, |
| /* 5982 */ 's', 'd', 'o', 't', 9, 0, |
| /* 5988 */ 'u', 'd', 'o', 't', 9, 0, |
| /* 5994 */ 'c', 'n', 'o', 't', 9, 0, |
| /* 6000 */ 't', 's', 't', 'a', 'r', 't', 9, 0, |
| /* 6008 */ 'f', 's', 'q', 'r', 't', 9, 0, |
| /* 6015 */ 'p', 't', 'e', 's', 't', 9, 0, |
| /* 6022 */ 't', 't', 'e', 's', 't', 9, 0, |
| /* 6029 */ 'p', 'f', 'i', 'r', 's', 't', 9, 0, |
| /* 6037 */ 'c', 'm', 't', 's', 't', 9, 0, |
| /* 6044 */ 'f', 'c', 'v', 't', 9, 0, |
| /* 6050 */ 's', 's', 'u', 'b', 'w', 't', 9, 0, |
| /* 6058 */ 'u', 's', 'u', 'b', 'w', 't', 9, 0, |
| /* 6066 */ 's', 'a', 'd', 'd', 'w', 't', 9, 0, |
| /* 6074 */ 'u', 'a', 'd', 'd', 'w', 't', 9, 0, |
| /* 6082 */ 'b', 'e', 'x', 't', 9, 0, |
| /* 6088 */ 'p', 'n', 'e', 'x', 't', 9, 0, |
| /* 6095 */ 'f', 'c', 'v', 't', 'a', 'u', 9, 0, |
| /* 6103 */ 's', 'q', 's', 'h', 'l', 'u', 9, 0, |
| /* 6111 */ 'f', 'c', 'v', 't', 'm', 'u', 9, 0, |
| /* 6119 */ 'f', 'c', 'v', 't', 'n', 'u', 9, 0, |
| /* 6127 */ 'f', 'c', 'v', 't', 'p', 'u', 9, 0, |
| /* 6135 */ 'f', 'c', 'v', 't', 'z', 'u', 9, 0, |
| /* 6143 */ 'f', 'a', 'd', 'd', 'v', 9, 0, |
| /* 6150 */ 's', 'a', 'd', 'd', 'v', 9, 0, |
| /* 6157 */ 'u', 'a', 'd', 'd', 'v', 9, 0, |
| /* 6164 */ 'a', 'n', 'd', 'v', 9, 0, |
| /* 6170 */ 'r', 'e', 'v', 9, 0, |
| /* 6175 */ 'f', 'd', 'i', 'v', 9, 0, |
| /* 6181 */ 's', 'd', 'i', 'v', 9, 0, |
| /* 6187 */ 'u', 'd', 'i', 'v', 9, 0, |
| /* 6193 */ 's', 'a', 'd', 'd', 'l', 'v', 9, 0, |
| /* 6201 */ 'u', 'a', 'd', 'd', 'l', 'v', 9, 0, |
| /* 6209 */ 'f', 'm', 'i', 'n', 'n', 'm', 'v', 9, 0, |
| /* 6218 */ 'f', 'm', 'a', 'x', 'n', 'm', 'v', 9, 0, |
| /* 6227 */ 'f', 'm', 'i', 'n', 'v', 9, 0, |
| /* 6234 */ 's', 'm', 'i', 'n', 'v', 9, 0, |
| /* 6241 */ 'u', 'm', 'i', 'n', 'v', 9, 0, |
| /* 6248 */ 'c', 's', 'i', 'n', 'v', 9, 0, |
| /* 6255 */ 'f', 'm', 'o', 'v', 9, 0, |
| /* 6261 */ 's', 'm', 'o', 'v', 9, 0, |
| /* 6267 */ 'u', 'm', 'o', 'v', 9, 0, |
| /* 6273 */ 'e', 'o', 'r', 'v', 9, 0, |
| /* 6279 */ 'f', 'm', 'a', 'x', 'v', 9, 0, |
| /* 6286 */ 's', 'm', 'a', 'x', 'v', 9, 0, |
| /* 6293 */ 'u', 'm', 'a', 'x', 'v', 9, 0, |
| /* 6300 */ 'l', 'd', '1', 'w', 9, 0, |
| /* 6306 */ 'l', 'd', 'f', 'f', '1', 'w', 9, 0, |
| /* 6314 */ 'l', 'd', 'n', 'f', '1', 'w', 9, 0, |
| /* 6322 */ 'l', 'd', 'n', 't', '1', 'w', 9, 0, |
| /* 6330 */ 's', 't', 'n', 't', '1', 'w', 9, 0, |
| /* 6338 */ 's', 't', '1', 'w', 9, 0, |
| /* 6344 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0, |
| /* 6352 */ 'l', 'd', '2', 'w', 9, 0, |
| /* 6358 */ 's', 't', '2', 'w', 9, 0, |
| /* 6364 */ 'l', 'd', '3', 'w', 9, 0, |
| /* 6370 */ 's', 't', '3', 'w', 9, 0, |
| /* 6376 */ 'l', 'd', '4', 'w', 9, 0, |
| /* 6382 */ 's', 't', '4', 'w', 9, 0, |
| /* 6388 */ 's', 's', 'u', 'b', 'w', 9, 0, |
| /* 6395 */ 'u', 's', 'u', 'b', 'w', 9, 0, |
| /* 6402 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0, |
| /* 6411 */ 's', 'q', 'd', 'e', 'c', 'w', 9, 0, |
| /* 6419 */ 'u', 'q', 'd', 'e', 'c', 'w', 9, 0, |
| /* 6427 */ 's', 'q', 'i', 'n', 'c', 'w', 9, 0, |
| /* 6435 */ 'u', 'q', 'i', 'n', 'c', 'w', 9, 0, |
| /* 6443 */ 's', 'a', 'd', 'd', 'w', 9, 0, |
| /* 6450 */ 'u', 'a', 'd', 'd', 'w', 9, 0, |
| /* 6457 */ 'p', 'r', 'f', 'w', 9, 0, |
| /* 6463 */ 'l', 'd', '1', 'r', 'q', 'w', 9, 0, |
| /* 6471 */ 'l', 'd', '1', 'r', 'w', 9, 0, |
| /* 6478 */ 'w', 'h', 'i', 'l', 'e', 'r', 'w', 9, 0, |
| /* 6487 */ 'l', 'd', '1', 's', 'w', 9, 0, |
| /* 6494 */ 'l', 'd', 'f', 'f', '1', 's', 'w', 9, 0, |
| /* 6503 */ 'l', 'd', 'n', 'f', '1', 's', 'w', 9, 0, |
| /* 6512 */ 'l', 'd', 'n', 't', '1', 's', 'w', 9, 0, |
| /* 6521 */ 'l', 'd', 'p', 's', 'w', 9, 0, |
| /* 6528 */ 'l', 'd', '1', 'r', 's', 'w', 9, 0, |
| /* 6536 */ 'l', 'd', 'r', 's', 'w', 9, 0, |
| /* 6543 */ 'l', 'd', 't', 'r', 's', 'w', 9, 0, |
| /* 6551 */ 'l', 'd', 'u', 'r', 's', 'w', 9, 0, |
| /* 6559 */ 'l', 'd', 'a', 'p', 'u', 'r', 's', 'w', 9, 0, |
| /* 6569 */ 'c', 'n', 't', 'w', 9, 0, |
| /* 6575 */ 's', 'x', 't', 'w', 9, 0, |
| /* 6581 */ 'u', 'x', 't', 'w', 9, 0, |
| /* 6587 */ 'r', 'e', 'v', 'w', 9, 0, |
| /* 6593 */ 'c', 'r', 'c', '3', '2', 'x', 9, 0, |
| /* 6601 */ 'f', 'r', 'i', 'n', 't', '3', '2', 'x', 9, 0, |
| /* 6611 */ 'f', 'r', 'i', 'n', 't', '6', '4', 'x', 9, 0, |
| /* 6621 */ 'b', 'c', 'a', 'x', 9, 0, |
| /* 6627 */ 'f', 'm', 'a', 'x', 9, 0, |
| /* 6633 */ 'l', 'd', 's', 'm', 'a', 'x', 9, 0, |
| /* 6641 */ 'l', 'd', 'u', 'm', 'a', 'x', 9, 0, |
| /* 6649 */ 't', 'b', 'x', 9, 0, |
| /* 6654 */ 'c', 'r', 'c', '3', '2', 'c', 'x', 9, 0, |
| /* 6663 */ 'i', 'n', 'd', 'e', 'x', 9, 0, |
| /* 6670 */ 'c', 'l', 'r', 'e', 'x', 9, 0, |
| /* 6677 */ 'm', 'o', 'v', 'p', 'r', 'f', 'x', 9, 0, |
| /* 6686 */ 'f', 'm', 'u', 'l', 'x', 9, 0, |
| /* 6693 */ 'f', 'r', 'e', 'c', 'p', 'x', 9, 0, |
| /* 6701 */ 'f', 'r', 'i', 'n', 't', 'x', 9, 0, |
| /* 6709 */ 'f', 'c', 'v', 't', 'x', 9, 0, |
| /* 6716 */ 's', 'm', '4', 'e', 'k', 'e', 'y', 9, 0, |
| /* 6725 */ 'f', 'c', 'p', 'y', 9, 0, |
| /* 6731 */ 'f', 'r', 'i', 'n', 't', '3', '2', 'z', 9, 0, |
| /* 6741 */ 'f', 'r', 'i', 'n', 't', '6', '4', 'z', 9, 0, |
| /* 6751 */ 'b', 'r', 'a', 'a', 'z', 9, 0, |
| /* 6758 */ 'b', 'l', 'r', 'a', 'a', 'z', 9, 0, |
| /* 6766 */ 'b', 'r', 'a', 'b', 'z', 9, 0, |
| /* 6773 */ 'b', 'l', 'r', 'a', 'b', 'z', 9, 0, |
| /* 6781 */ 'c', 'b', 'z', 9, 0, |
| /* 6786 */ 't', 'b', 'z', 9, 0, |
| /* 6791 */ 'c', 'l', 'z', 9, 0, |
| /* 6796 */ 'c', 'b', 'n', 'z', 9, 0, |
| /* 6802 */ 't', 'b', 'n', 'z', 9, 0, |
| /* 6808 */ 'f', 'r', 'i', 'n', 't', 'z', 9, 0, |
| /* 6816 */ 'm', 'o', 'v', 'z', 9, 0, |
| /* 6822 */ '.', 't', 'l', 's', 'd', 'e', 's', 'c', 'c', 'a', 'l', 'l', 32, 0, |
| /* 6836 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, |
| /* 6867 */ 'b', '.', 0, |
| /* 6870 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, |
| /* 6894 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, |
| /* 6919 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, |
| /* 6942 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, |
| /* 6965 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, |
| /* 6987 */ 'h', 'i', 'n', 't', 32, '#', '1', '0', 0, |
| /* 6996 */ 'h', 'i', 'n', 't', 32, '#', '3', '0', 0, |
| /* 7005 */ 'h', 'i', 'n', 't', 32, '#', '3', '1', 0, |
| /* 7014 */ 'h', 'i', 'n', 't', 32, '#', '1', '2', 0, |
| /* 7023 */ 'h', 'i', 'n', 't', 32, '#', '1', '4', 0, |
| /* 7032 */ 'h', 'i', 'n', 't', 32, '#', '2', '4', 0, |
| /* 7041 */ 'h', 'i', 'n', 't', 32, '#', '2', '5', 0, |
| /* 7050 */ 'h', 'i', 'n', 't', 32, '#', '2', '6', 0, |
| /* 7059 */ 'h', 'i', 'n', 't', 32, '#', '7', 0, |
| /* 7067 */ 'h', 'i', 'n', 't', 32, '#', '2', '7', 0, |
| /* 7076 */ 'h', 'i', 'n', 't', 32, '#', '8', 0, |
| /* 7084 */ 'h', 'i', 'n', 't', 32, '#', '2', '8', 0, |
| /* 7093 */ 'h', 'i', 'n', 't', 32, '#', '2', '9', 0, |
| /* 7102 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, |
| /* 7115 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, |
| /* 7122 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, |
| /* 7132 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, |
| /* 7142 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, |
| /* 7157 */ 'e', 'r', 'e', 't', 'a', 'a', 0, |
| /* 7164 */ 'e', 'r', 'e', 't', 'a', 'b', 0, |
| /* 7171 */ 's', 'b', 0, |
| /* 7174 */ 'x', 'a', 'f', 'l', 'a', 'g', 0, |
| /* 7181 */ 'a', 'x', 'f', 'l', 'a', 'g', 0, |
| /* 7188 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, |
| /* 7202 */ 's', 'e', 't', 'f', 'f', 'r', 0, |
| /* 7209 */ 'd', 'r', 'p', 's', 0, |
| /* 7214 */ 'e', 'r', 'e', 't', 0, |
| /* 7219 */ 't', 'c', 'o', 'm', 'm', 'i', 't', 0, |
| /* 7227 */ 'c', 'f', 'i', 'n', 'v', 0, |
| }; |
| |
| static const uint32_t OpInfo0[] = { |
| 0U, // PHI |
| 0U, // INLINEASM |
| 0U, // INLINEASM_BR |
| 0U, // CFI_INSTRUCTION |
| 0U, // EH_LABEL |
| 0U, // GC_LABEL |
| 0U, // ANNOTATION_LABEL |
| 0U, // KILL |
| 0U, // EXTRACT_SUBREG |
| 0U, // INSERT_SUBREG |
| 0U, // IMPLICIT_DEF |
| 0U, // SUBREG_TO_REG |
| 0U, // COPY_TO_REGCLASS |
| 7123U, // DBG_VALUE |
| 7133U, // DBG_LABEL |
| 0U, // REG_SEQUENCE |
| 0U, // COPY |
| 7116U, // BUNDLE |
| 7143U, // LIFETIME_START |
| 7103U, // LIFETIME_END |
| 0U, // STACKMAP |
| 7189U, // FENTRY_CALL |
| 0U, // PATCHPOINT |
| 0U, // LOAD_STACK_GUARD |
| 0U, // STATEPOINT |
| 0U, // LOCAL_ESCAPE |
| 0U, // FAULTING_OP |
| 0U, // PATCHABLE_OP |
| 6920U, // PATCHABLE_FUNCTION_ENTER |
| 6837U, // PATCHABLE_RET |
| 6966U, // PATCHABLE_FUNCTION_EXIT |
| 6943U, // PATCHABLE_TAIL_CALL |
| 6895U, // PATCHABLE_EVENT_CALL |
| 6871U, // PATCHABLE_TYPED_EVENT_CALL |
| 0U, // ICALL_BRANCH_FUNNEL |
| 0U, // G_ADD |
| 0U, // G_SUB |
| 0U, // G_MUL |
| 0U, // G_SDIV |
| 0U, // G_UDIV |
| 0U, // G_SREM |
| 0U, // G_UREM |
| 0U, // G_AND |
| 0U, // G_OR |
| 0U, // G_XOR |
| 0U, // G_IMPLICIT_DEF |
| 0U, // G_PHI |
| 0U, // G_FRAME_INDEX |
| 0U, // G_GLOBAL_VALUE |
| 0U, // G_EXTRACT |
| 0U, // G_UNMERGE_VALUES |
| 0U, // G_INSERT |
| 0U, // G_MERGE_VALUES |
| 0U, // G_BUILD_VECTOR |
| 0U, // G_BUILD_VECTOR_TRUNC |
| 0U, // G_CONCAT_VECTORS |
| 0U, // G_PTRTOINT |
| 0U, // G_INTTOPTR |
| 0U, // G_BITCAST |
| 0U, // G_INTRINSIC_TRUNC |
| 0U, // G_INTRINSIC_ROUND |
| 0U, // G_READCYCLECOUNTER |
| 0U, // G_LOAD |
| 0U, // G_SEXTLOAD |
| 0U, // G_ZEXTLOAD |
| 0U, // G_INDEXED_LOAD |
| 0U, // G_INDEXED_SEXTLOAD |
| 0U, // G_INDEXED_ZEXTLOAD |
| 0U, // G_STORE |
| 0U, // G_INDEXED_STORE |
| 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 0U, // G_ATOMIC_CMPXCHG |
| 0U, // G_ATOMICRMW_XCHG |
| 0U, // G_ATOMICRMW_ADD |
| 0U, // G_ATOMICRMW_SUB |
| 0U, // G_ATOMICRMW_AND |
| 0U, // G_ATOMICRMW_NAND |
| 0U, // G_ATOMICRMW_OR |
| 0U, // G_ATOMICRMW_XOR |
| 0U, // G_ATOMICRMW_MAX |
| 0U, // G_ATOMICRMW_MIN |
| 0U, // G_ATOMICRMW_UMAX |
| 0U, // G_ATOMICRMW_UMIN |
| 0U, // G_ATOMICRMW_FADD |
| 0U, // G_ATOMICRMW_FSUB |
| 0U, // G_FENCE |
| 0U, // G_BRCOND |
| 0U, // G_BRINDIRECT |
| 0U, // G_INTRINSIC |
| 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 0U, // G_ANYEXT |
| 0U, // G_TRUNC |
| 0U, // G_CONSTANT |
| 0U, // G_FCONSTANT |
| 0U, // G_VASTART |
| 0U, // G_VAARG |
| 0U, // G_SEXT |
| 0U, // G_SEXT_INREG |
| 0U, // G_ZEXT |
| 0U, // G_SHL |
| 0U, // G_LSHR |
| 0U, // G_ASHR |
| 0U, // G_ICMP |
| 0U, // G_FCMP |
| 0U, // G_SELECT |
| 0U, // G_UADDO |
| 0U, // G_UADDE |
| 0U, // G_USUBO |
| 0U, // G_USUBE |
| 0U, // G_SADDO |
| 0U, // G_SADDE |
| 0U, // G_SSUBO |
| 0U, // G_SSUBE |
| 0U, // G_UMULO |
| 0U, // G_SMULO |
| 0U, // G_UMULH |
| 0U, // G_SMULH |
| 0U, // G_FADD |
| 0U, // G_FSUB |
| 0U, // G_FMUL |
| 0U, // G_FMA |
| 0U, // G_FMAD |
| 0U, // G_FDIV |
| 0U, // G_FREM |
| 0U, // G_FPOW |
| 0U, // G_FEXP |
| 0U, // G_FEXP2 |
| 0U, // G_FLOG |
| 0U, // G_FLOG2 |
| 0U, // G_FLOG10 |
| 0U, // G_FNEG |
| 0U, // G_FPEXT |
| 0U, // G_FPTRUNC |
| 0U, // G_FPTOSI |
| 0U, // G_FPTOUI |
| 0U, // G_SITOFP |
| 0U, // G_UITOFP |
| 0U, // G_FABS |
| 0U, // G_FCOPYSIGN |
| 0U, // G_FCANONICALIZE |
| 0U, // G_FMINNUM |
| 0U, // G_FMAXNUM |
| 0U, // G_FMINNUM_IEEE |
| 0U, // G_FMAXNUM_IEEE |
| 0U, // G_FMINIMUM |
| 0U, // G_FMAXIMUM |
| 0U, // G_PTR_ADD |
| 0U, // G_PTR_MASK |
| 0U, // G_SMIN |
| 0U, // G_SMAX |
| 0U, // G_UMIN |
| 0U, // G_UMAX |
| 0U, // G_BR |
| 0U, // G_BRJT |
| 0U, // G_INSERT_VECTOR_ELT |
| 0U, // G_EXTRACT_VECTOR_ELT |
| 0U, // G_SHUFFLE_VECTOR |
| 0U, // G_CTTZ |
| 0U, // G_CTTZ_ZERO_UNDEF |
| 0U, // G_CTLZ |
| 0U, // G_CTLZ_ZERO_UNDEF |
| 0U, // G_CTPOP |
| 0U, // G_BSWAP |
| 0U, // G_BITREVERSE |
| 0U, // G_FCEIL |
| 0U, // G_FCOS |
| 0U, // G_FSIN |
| 0U, // G_FSQRT |
| 0U, // G_FFLOOR |
| 0U, // G_FRINT |
| 0U, // G_FNEARBYINT |
| 0U, // G_ADDRSPACE_CAST |
| 0U, // G_BLOCK_ADDR |
| 0U, // G_JUMP_TABLE |
| 0U, // G_DYN_STACKALLOC |
| 0U, // G_READ_REGISTER |
| 0U, // G_WRITE_REGISTER |
| 0U, // CATCHRET |
| 0U, // CLEANUPRET |
| 0U, // SEH_AddFP |
| 0U, // SEH_EpilogEnd |
| 0U, // SEH_EpilogStart |
| 0U, // SEH_Nop |
| 0U, // SEH_PrologEnd |
| 0U, // SEH_SaveFPLR |
| 0U, // SEH_SaveFPLR_X |
| 0U, // SEH_SaveFReg |
| 0U, // SEH_SaveFRegP |
| 0U, // SEH_SaveFRegP_X |
| 0U, // SEH_SaveFReg_X |
| 0U, // SEH_SaveReg |
| 0U, // SEH_SaveRegP |
| 0U, // SEH_SaveRegP_X |
| 0U, // SEH_SaveReg_X |
| 0U, // SEH_SetFP |
| 0U, // SEH_StackAlloc |
| 13452U, // ABS_ZPmZ_B |
| 2147505292U, // ABS_ZPmZ_D |
| 34108556U, // ABS_ZPmZ_H |
| 38028U, // ABS_ZPmZ_S |
| 2215687308U, // ABSv16i8 |
| 100717708U, // ABSv1i64 |
| 2216211596U, // ABSv2i32 |
| 69252236U, // ABSv2i64 |
| 2217260172U, // ABSv4i16 |
| 70300812U, // ABSv4i32 |
| 2218308748U, // ABSv8i16 |
| 71349388U, // ABSv8i8 |
| 2281719137U, // ADCLB_ZZZ_D |
| 2315289953U, // ADCLB_ZZZ_S |
| 2281723444U, // ADCLT_ZZZ_D |
| 2315294260U, // ADCLT_ZZZ_S |
| 2248201395U, // ADCSWr |
| 2248201395U, // ADCSXr |
| 2248198288U, // ADCWr |
| 2248198288U, // ADCXr |
| 2248198838U, // ADDG |
| 2348820037U, // ADDHNB_ZZZ_B |
| 239625797U, // ADDHNB_ZZZ_H |
| 2415953477U, // ADDHNB_ZZZ_S |
| 2449487590U, // ADDHNT_ZZZ_B |
| 240154342U, // ADDHNT_ZZZ_H |
| 2281740006U, // ADDHNT_ZZZ_S |
| 2216210699U, // ADDHNv2i64_v2i32 |
| 2486231395U, // ADDHNv2i64_v4i32 |
| 69775627U, // ADDHNv4i32_v4i16 |
| 339272035U, // ADDHNv4i32_v8i16 |
| 2484134243U, // ADDHNv8i16_v16i8 |
| 2218832139U, // ADDHNv8i16_v8i8 |
| 2248200198U, // ADDPL_XXI |
| 369111558U, // ADDP_ZPmZ_B |
| 369119750U, // ADDP_ZPmZ_D |
| 2555933190U, // ADDP_ZPmZ_H |
| 369136134U, // ADDP_ZPmZ_S |
| 68203014U, // ADDPv16i8 |
| 2216210950U, // ADDPv2i32 |
| 2216735238U, // ADDPv2i64 |
| 67162630U, // ADDPv2i64p |
| 69775878U, // ADDPv4i16 |
| 70300166U, // ADDPv4i32 |
| 2218308102U, // ADDPv8i16 |
| 2218832390U, // ADDPv8i8 |
| 2248201407U, // ADDSWri |
| 0U, // ADDSWrr |
| 2248201407U, // ADDSWrs |
| 2248201407U, // ADDSWrx |
| 2248201407U, // ADDSXri |
| 0U, // ADDSXrr |
| 2248201407U, // ADDSXrs |
| 2248201407U, // ADDSXrx |
| 2248201407U, // ADDSXrx64 |
| 2248200324U, // ADDVL_XXI |
| 2214647809U, // ADDVv16i8v |
| 2214647809U, // ADDVv4i16v |
| 67164161U, // ADDVv4i32v |
| 2214647809U, // ADDVv8i16v |
| 67164161U, // ADDVv8i8v |
| 2248198489U, // ADDWri |
| 0U, // ADDWrr |
| 2248198489U, // ADDWrs |
| 2248198489U, // ADDWrx |
| 2248198489U, // ADDXri |
| 0U, // ADDXrr |
| 2248198489U, // ADDXrs |
| 2248198489U, // ADDXrx |
| 2248198489U, // ADDXrx64 |
| 2583701849U, // ADD_ZI_B |
| 2415937881U, // ADD_ZI_D |
| 241199449U, // ADD_ZI_H |
| 2617280857U, // ADD_ZI_S |
| 369109337U, // ADD_ZPmZ_B |
| 369117529U, // ADD_ZPmZ_D |
| 2555930969U, // ADD_ZPmZ_H |
| 369133913U, // ADD_ZPmZ_S |
| 2583701849U, // ADD_ZZZ_B |
| 2415937881U, // ADD_ZZZ_D |
| 2388683097U, // ADD_ZZZ_H |
| 2617280857U, // ADD_ZZZ_S |
| 0U, // ADDlowTLS |
| 68200793U, // ADDv16i8 |
| 2248198489U, // ADDv1i64 |
| 2216208729U, // ADDv2i32 |
| 2216733017U, // ADDv2i64 |
| 69773657U, // ADDv4i16 |
| 70297945U, // ADDv4i32 |
| 2218305881U, // ADDv8i16 |
| 2218830169U, // ADDv8i8 |
| 0U, // ADJCALLSTACKDOWN |
| 0U, // ADJCALLSTACKUP |
| 100717380U, // ADR |
| 503370365U, // ADRP |
| 2422756164U, // ADR_LSL_ZZZ_D_0 |
| 2422756164U, // ADR_LSL_ZZZ_D_1 |
| 2422756164U, // ADR_LSL_ZZZ_D_2 |
| 2422756164U, // ADR_LSL_ZZZ_D_3 |
| 2624099140U, // ADR_LSL_ZZZ_S_0 |
| 2624099140U, // ADR_LSL_ZZZ_S_1 |
| 2624099140U, // ADR_LSL_ZZZ_S_2 |
| 2624099140U, // ADR_LSL_ZZZ_S_3 |
| 2422756164U, // ADR_SXTW_ZZZ_D_0 |
| 2422756164U, // ADR_SXTW_ZZZ_D_1 |
| 2422756164U, // ADR_SXTW_ZZZ_D_2 |
| 2422756164U, // ADR_SXTW_ZZZ_D_3 |
| 2422756164U, // ADR_UXTW_ZZZ_D_0 |
| 2422756164U, // ADR_UXTW_ZZZ_D_1 |
| 2422756164U, // ADR_UXTW_ZZZ_D_2 |
| 2422756164U, // ADR_UXTW_ZZZ_D_3 |
| 2583701969U, // AESD_ZZZ_B |
| 2484136401U, // AESDrr |
| 2583702110U, // AESE_ZZZ_B |
| 2484136542U, // AESErr |
| 436218010U, // AESIMC_ZZ_B |
| 2215684250U, // AESIMCrr |
| 0U, // AESIMCrrTied |
| 436218018U, // AESMC_ZZ_B |
| 2215684258U, // AESMCrr |
| 0U, // AESMCrrTied |
| 2248201414U, // ANDSWri |
| 0U, // ANDSWrr |
| 2248201414U, // ANDSWrs |
| 2248201414U, // ANDSXri |
| 0U, // ANDSXrr |
| 2248201414U, // ANDSXrs |
| 2516595910U, // ANDS_PPzPP |
| 2516637717U, // ANDV_VPZ_B |
| 2516637717U, // ANDV_VPZ_D |
| 2516637717U, // ANDV_VPZ_H |
| 2516637717U, // ANDV_VPZ_S |
| 2248198583U, // ANDWri |
| 0U, // ANDWrr |
| 2248198583U, // ANDWrs |
| 2248198583U, // ANDXri |
| 0U, // ANDXrr |
| 2248198583U, // ANDXrs |
| 2516593079U, // AND_PPzPP |
| 2415937975U, // AND_ZI |
| 369109431U, // AND_ZPmZ_B |
| 369117623U, // AND_ZPmZ_D |
| 2555931063U, // AND_ZPmZ_H |
| 369134007U, // AND_ZPmZ_S |
| 2415937975U, // AND_ZZZ |
| 68200887U, // ANDv16i8 |
| 2218830263U, // ANDv8i8 |
| 369109451U, // ASRD_ZPmI_B |
| 369117643U, // ASRD_ZPmI_D |
| 2555931083U, // ASRD_ZPmI_H |
| 369134027U, // ASRD_ZPmI_S |
| 369112036U, // ASRR_ZPmZ_B |
| 369120228U, // ASRR_ZPmZ_D |
| 2555933668U, // ASRR_ZPmZ_H |
| 369136612U, // ASRR_ZPmZ_S |
| 2248201200U, // ASRVWr |
| 2248201200U, // ASRVXr |
| 369112048U, // ASR_WIDE_ZPmZ_B |
| 2555933680U, // ASR_WIDE_ZPmZ_H |
| 369136624U, // ASR_WIDE_ZPmZ_S |
| 2583704560U, // ASR_WIDE_ZZZ_B |
| 241202160U, // ASR_WIDE_ZZZ_H |
| 2617283568U, // ASR_WIDE_ZZZ_S |
| 369112048U, // ASR_ZPmI_B |
| 369120240U, // ASR_ZPmI_D |
| 2555933680U, // ASR_ZPmI_H |
| 369136624U, // ASR_ZPmI_S |
| 369112048U, // ASR_ZPmZ_B |
| 369120240U, // ASR_ZPmZ_D |
| 2555933680U, // ASR_ZPmZ_H |
| 369136624U, // ASR_ZPmZ_S |
| 2583704560U, // ASR_ZZI_B |
| 2415940592U, // ASR_ZZI_D |
| 2388685808U, // ASR_ZZI_H |
| 2617283568U, // ASR_ZZI_S |
| 100713119U, // AUTDA |
| 100713612U, // AUTDB |
| 7390052U, // AUTDZA |
| 7391340U, // AUTDZB |
| 100713140U, // AUTIA |
| 7015U, // AUTIA1716 |
| 7094U, // AUTIASP |
| 7085U, // AUTIAZ |
| 100713639U, // AUTIB |
| 7024U, // AUTIB1716 |
| 7006U, // AUTIBSP |
| 6997U, // AUTIBZ |
| 7390068U, // AUTIZA |
| 7391356U, // AUTIZB |
| 7182U, // AXFLAG |
| 66431U, // B |
| 68205022U, // BCAX |
| 2415942110U, // BCAX_ZZZZ_D |
| 2583704081U, // BDEP_ZZZ_B |
| 2415940113U, // BDEP_ZZZ_D |
| 2388685329U, // BDEP_ZZZ_H |
| 2617283089U, // BDEP_ZZZ_S |
| 2583705539U, // BEXT_ZZZ_B |
| 2415941571U, // BEXT_ZZZ_D |
| 2388686787U, // BEXT_ZZZ_H |
| 2617284547U, // BEXT_ZZZ_S |
| 2684407979U, // BFMWri |
| 2684407979U, // BFMXri |
| 2583704195U, // BGRP_ZZZ_B |
| 2415940227U, // BGRP_ZZZ_D |
| 2388685443U, // BGRP_ZZZ_H |
| 2617283203U, // BGRP_ZZZ_S |
| 0U, // BICSWrr |
| 2248201401U, // BICSWrs |
| 0U, // BICSXrr |
| 2248201401U, // BICSXrs |
| 2516595897U, // BICS_PPzPP |
| 0U, // BICWrr |
| 2248198293U, // BICWrs |
| 0U, // BICXrr |
| 2248198293U, // BICXrs |
| 2516592789U, // BIC_PPzPP |
| 369109141U, // BIC_ZPmZ_B |
| 369117333U, // BIC_ZPmZ_D |
| 2555930773U, // BIC_ZPmZ_H |
| 369133717U, // BIC_ZPmZ_S |
| 2415937685U, // BIC_ZZZ |
| 68200597U, // BICv16i8 |
| 572057749U, // BICv2i32 |
| 573106325U, // BICv4i16 |
| 573630613U, // BICv4i32 |
| 574154901U, // BICv8i16 |
| 2218829973U, // BICv8i8 |
| 68201098U, // BIFv16i8 |
| 2218830474U, // BIFv8i8 |
| 336655846U, // BITv16i8 |
| 2487285222U, // BITv8i8 |
| 69410U, // BL |
| 7394166U, // BLR |
| 100713078U, // BLRAA |
| 7395943U, // BLRAAZ |
| 100713495U, // BLRAB |
| 7395958U, // BLRABZ |
| 7394080U, // BR |
| 100713065U, // BRAA |
| 7395936U, // BRAAZ |
| 100713482U, // BRAB |
| 7395951U, // BRABZ |
| 77448U, // BRK |
| 2516595828U, // BRKAS_PPzP |
| 8891U, // BRKA_PPmP |
| 2516591291U, // BRKA_PPzP |
| 2516595864U, // BRKBS_PPzP |
| 9390U, // BRKB_PPmP |
| 2516591790U, // BRKB_PPzP |
| 2516595993U, // BRKNS_PPzP |
| 2516594984U, // BRKN_PPzP |
| 2516595835U, // BRKPAS_PPzPP |
| 2516591335U, // BRKPA_PPzPP |
| 2516595871U, // BRKPBS_PPzPP |
| 2516592307U, // BRKPB_PPzPP |
| 2415939828U, // BSL1N_ZZZZ_D |
| 2415939835U, // BSL2N_ZZZZ_D |
| 2415939633U, // BSL_ZZZZ_D |
| 336654385U, // BSLv16i8 |
| 2487283761U, // BSLv8i8 |
| 88788U, // Bcc |
| 2583701848U, // CADD_ZZI_B |
| 2415937880U, // CADD_ZZI_D |
| 2388683096U, // CADD_ZZI_H |
| 2617280856U, // CADD_ZZI_S |
| 536962096U, // CASAB |
| 536964010U, // CASAH |
| 536962338U, // CASALB |
| 536964169U, // CASALH |
| 536964861U, // CASALW |
| 536964861U, // CASALX |
| 536961836U, // CASAW |
| 536961836U, // CASAX |
| 536962942U, // CASB |
| 536964546U, // CASH |
| 536962544U, // CASLB |
| 536964263U, // CASLH |
| 536965162U, // CASLW |
| 536965162U, // CASLX |
| 102108U, // CASPALW |
| 110300U, // CASPALX |
| 99054U, // CASPAW |
| 107246U, // CASPAX |
| 102413U, // CASPLW |
| 110605U, // CASPLX |
| 103049U, // CASPW |
| 111241U, // CASPX |
| 536966255U, // CASW |
| 536966255U, // CASX |
| 0U, // CATCHPAD |
| 604035725U, // CBNZW |
| 604035725U, // CBNZX |
| 604035710U, // CBZW |
| 604035710U, // CBZX |
| 2248200494U, // CCMNWi |
| 2248200494U, // CCMNWr |
| 2248200494U, // CCMNXi |
| 2248200494U, // CCMNXr |
| 2248200766U, // CCMPWi |
| 2248200766U, // CCMPWr |
| 2248200766U, // CCMPXi |
| 2248200766U, // CCMPXr |
| 2449495897U, // CDOT_ZZZI_D |
| 637572953U, // CDOT_ZZZI_S |
| 2449495897U, // CDOT_ZZZ_D |
| 637572953U, // CDOT_ZZZ_S |
| 7228U, // CFINV |
| 2516632386U, // CLASTA_RPZ_B |
| 2516632386U, // CLASTA_RPZ_D |
| 2516632386U, // CLASTA_RPZ_H |
| 2516632386U, // CLASTA_RPZ_S |
| 2516632386U, // CLASTA_VPZ_B |
| 2516632386U, // CLASTA_VPZ_D |
| 2516632386U, // CLASTA_VPZ_H |
| 2516632386U, // CLASTA_VPZ_S |
| 2516591426U, // CLASTA_ZPZ_B |
| 2516599618U, // CLASTA_ZPZ_D |
| 2388157250U, // CLASTA_ZPZ_H |
| 2516616002U, // CLASTA_ZPZ_S |
| 2516633575U, // CLASTB_RPZ_B |
| 2516633575U, // CLASTB_RPZ_D |
| 2516633575U, // CLASTB_RPZ_H |
| 2516633575U, // CLASTB_RPZ_S |
| 2516633575U, // CLASTB_VPZ_B |
| 2516633575U, // CLASTB_VPZ_D |
| 2516633575U, // CLASTB_VPZ_H |
| 2516633575U, // CLASTB_VPZ_S |
| 2516592615U, // CLASTB_ZPZ_B |
| 2516600807U, // CLASTB_ZPZ_D |
| 2388158439U, // CLASTB_ZPZ_H |
| 2516617191U, // CLASTB_ZPZ_S |
| 7395855U, // CLREX |
| 100717802U, // CLSWr |
| 100717802U, // CLSXr |
| 13546U, // CLS_ZPmZ_B |
| 2147505386U, // CLS_ZPmZ_D |
| 34108650U, // CLS_ZPmZ_H |
| 38122U, // CLS_ZPmZ_S |
| 2215687402U, // CLSv16i8 |
| 2216211690U, // CLSv2i32 |
| 2217260266U, // CLSv4i16 |
| 70300906U, // CLSv4i32 |
| 2218308842U, // CLSv8i16 |
| 71349482U, // CLSv8i8 |
| 100719240U, // CLZWr |
| 100719240U, // CLZXr |
| 14984U, // CLZ_ZPmZ_B |
| 2147506824U, // CLZ_ZPmZ_D |
| 34110088U, // CLZ_ZPmZ_H |
| 39560U, // CLZ_ZPmZ_S |
| 2215688840U, // CLZv16i8 |
| 2216213128U, // CLZv2i32 |
| 2217261704U, // CLZv4i16 |
| 70302344U, // CLZv4i32 |
| 2218310280U, // CLZv8i16 |
| 71350920U, // CLZv8i8 |
| 68203229U, // CMEQv16i8 |
| 2215686877U, // CMEQv16i8rz |
| 2248200925U, // CMEQv1i64 |
| 100717277U, // CMEQv1i64rz |
| 2216211165U, // CMEQv2i32 |
| 2216211165U, // CMEQv2i32rz |
| 2216735453U, // CMEQv2i64 |
| 69251805U, // CMEQv2i64rz |
| 69776093U, // CMEQv4i16 |
| 2217259741U, // CMEQv4i16rz |
| 70300381U, // CMEQv4i32 |
| 70300381U, // CMEQv4i32rz |
| 2218308317U, // CMEQv8i16 |
| 2218308317U, // CMEQv8i16rz |
| 2218832605U, // CMEQv8i8 |
| 71348957U, // CMEQv8i8rz |
| 68200956U, // CMGEv16i8 |
| 2215684604U, // CMGEv16i8rz |
| 2248198652U, // CMGEv1i64 |
| 100715004U, // CMGEv1i64rz |
| 2216208892U, // CMGEv2i32 |
| 2216208892U, // CMGEv2i32rz |
| 2216733180U, // CMGEv2i64 |
| 69249532U, // CMGEv2i64rz |
| 69773820U, // CMGEv4i16 |
| 2217257468U, // CMGEv4i16rz |
| 70298108U, // CMGEv4i32 |
| 70298108U, // CMGEv4i32rz |
| 2218306044U, // CMGEv8i16 |
| 2218306044U, // CMGEv8i16rz |
| 2218830332U, // CMGEv8i8 |
| 71346684U, // CMGEv8i8rz |
| 68203992U, // CMGTv16i8 |
| 2215687640U, // CMGTv16i8rz |
| 2248201688U, // CMGTv1i64 |
| 100718040U, // CMGTv1i64rz |
| 2216211928U, // CMGTv2i32 |
| 2216211928U, // CMGTv2i32rz |
| 2216736216U, // CMGTv2i64 |
| 69252568U, // CMGTv2i64rz |
| 69776856U, // CMGTv4i16 |
| 2217260504U, // CMGTv4i16rz |
| 70301144U, // CMGTv4i32 |
| 70301144U, // CMGTv4i32rz |
| 2218309080U, // CMGTv8i16 |
| 2218309080U, // CMGTv8i16rz |
| 2218833368U, // CMGTv8i8 |
| 71349720U, // CMGTv8i8rz |
| 68202072U, // CMHIv16i8 |
| 2248199768U, // CMHIv1i64 |
| 2216210008U, // CMHIv2i32 |
| 2216734296U, // CMHIv2i64 |
| 69774936U, // CMHIv4i16 |
| 70299224U, // CMHIv4i32 |
| 2218307160U, // CMHIv8i16 |
| 2218831448U, // CMHIv8i8 |
| 68203741U, // CMHSv16i8 |
| 2248201437U, // CMHSv1i64 |
| 2216211677U, // CMHSv2i32 |
| 2216735965U, // CMHSv2i64 |
| 69776605U, // CMHSv4i16 |
| 70300893U, // CMHSv4i32 |
| 2218308829U, // CMHSv8i16 |
| 2218833117U, // CMHSv8i8 |
| 2390254274U, // CMLA_ZZZI_H |
| 2315289282U, // CMLA_ZZZI_S |
| 637543106U, // CMLA_ZZZ_B |
| 2281718466U, // CMLA_ZZZ_D |
| 2390254274U, // CMLA_ZZZ_H |
| 2315289282U, // CMLA_ZZZ_S |
| 2215684635U, // CMLEv16i8rz |
| 100715035U, // CMLEv1i64rz |
| 2216208923U, // CMLEv2i32rz |
| 69249563U, // CMLEv2i64rz |
| 2217257499U, // CMLEv4i16rz |
| 70298139U, // CMLEv4i32rz |
| 2218306075U, // CMLEv8i16rz |
| 71346715U, // CMLEv8i8rz |
| 2215687836U, // CMLTv16i8rz |
| 100718236U, // CMLTv1i64rz |
| 2216212124U, // CMLTv2i32rz |
| 69252764U, // CMLTv2i64rz |
| 2217260700U, // CMLTv4i16rz |
| 70301340U, // CMLTv4i32rz |
| 2218309276U, // CMLTv8i16rz |
| 71349916U, // CMLTv8i8rz |
| 2516595436U, // CMPEQ_PPzZI_B |
| 2516603628U, // CMPEQ_PPzZI_D |
| 2824368876U, // CMPEQ_PPzZI_H |
| 2516620012U, // CMPEQ_PPzZI_S |
| 2516595436U, // CMPEQ_PPzZZ_B |
| 2516603628U, // CMPEQ_PPzZZ_D |
| 2824368876U, // CMPEQ_PPzZZ_H |
| 2516620012U, // CMPEQ_PPzZZ_S |
| 2516595436U, // CMPEQ_WIDE_PPzZZ_B |
| 2824368876U, // CMPEQ_WIDE_PPzZZ_H |
| 2516620012U, // CMPEQ_WIDE_PPzZZ_S |
| 2516593154U, // CMPGE_PPzZI_B |
| 2516601346U, // CMPGE_PPzZI_D |
| 2824366594U, // CMPGE_PPzZI_H |
| 2516617730U, // CMPGE_PPzZI_S |
| 2516593154U, // CMPGE_PPzZZ_B |
| 2516601346U, // CMPGE_PPzZZ_D |
| 2824366594U, // CMPGE_PPzZZ_H |
| 2516617730U, // CMPGE_PPzZZ_S |
| 2516593154U, // CMPGE_WIDE_PPzZZ_B |
| 2824366594U, // CMPGE_WIDE_PPzZZ_H |
| 2516617730U, // CMPGE_WIDE_PPzZZ_S |
| 2516596190U, // CMPGT_PPzZI_B |
| 2516604382U, // CMPGT_PPzZI_D |
| 2824369630U, // CMPGT_PPzZI_H |
| 2516620766U, // CMPGT_PPzZI_S |
| 2516596190U, // CMPGT_PPzZZ_B |
| 2516604382U, // CMPGT_PPzZZ_D |
| 2824369630U, // CMPGT_PPzZZ_H |
| 2516620766U, // CMPGT_PPzZZ_S |
| 2516596190U, // CMPGT_WIDE_PPzZZ_B |
| 2824369630U, // CMPGT_WIDE_PPzZZ_H |
| 2516620766U, // CMPGT_WIDE_PPzZZ_S |
| 2516594270U, // CMPHI_PPzZI_B |
| 2516602462U, // CMPHI_PPzZI_D |
| 2824367710U, // CMPHI_PPzZI_H |
| 2516618846U, // CMPHI_PPzZI_S |
| 2516594270U, // CMPHI_PPzZZ_B |
| 2516602462U, // CMPHI_PPzZZ_D |
| 2824367710U, // CMPHI_PPzZZ_H |
| 2516618846U, // CMPHI_PPzZZ_S |
| 2516594270U, // CMPHI_WIDE_PPzZZ_B |
| 2824367710U, // CMPHI_WIDE_PPzZZ_H |
| 2516618846U, // CMPHI_WIDE_PPzZZ_S |
| 2516595939U, // CMPHS_PPzZI_B |
| 2516604131U, // CMPHS_PPzZI_D |
| 2824369379U, // CMPHS_PPzZI_H |
| 2516620515U, // CMPHS_PPzZI_S |
| 2516595939U, // CMPHS_PPzZZ_B |
| 2516604131U, // CMPHS_PPzZZ_D |
| 2824369379U, // CMPHS_PPzZZ_H |
| 2516620515U, // CMPHS_PPzZZ_S |
| 2516595939U, // CMPHS_WIDE_PPzZZ_B |
| 2824369379U, // CMPHS_WIDE_PPzZZ_H |
| 2516620515U, // CMPHS_WIDE_PPzZZ_S |
| 2516593185U, // CMPLE_PPzZI_B |
| 2516601377U, // CMPLE_PPzZI_D |
| 2824366625U, // CMPLE_PPzZI_H |
| 2516617761U, // CMPLE_PPzZI_S |
| 2516593185U, // CMPLE_WIDE_PPzZZ_B |
| 2824366625U, // CMPLE_WIDE_PPzZZ_H |
| 2516617761U, // CMPLE_WIDE_PPzZZ_S |
| 2516595146U, // CMPLO_PPzZI_B |
| 2516603338U, // CMPLO_PPzZI_D |
| 2824368586U, // CMPLO_PPzZI_H |
| 2516619722U, // CMPLO_PPzZI_S |
| 2516595146U, // CMPLO_WIDE_PPzZZ_B |
| 2824368586U, // CMPLO_WIDE_PPzZZ_H |
| 2516619722U, // CMPLO_WIDE_PPzZZ_S |
| 2516595973U, // CMPLS_PPzZI_B |
| 2516604165U, // CMPLS_PPzZI_D |
| 2824369413U, // CMPLS_PPzZI_H |
| 2516620549U, // CMPLS_PPzZI_S |
| 2516595973U, // CMPLS_WIDE_PPzZZ_B |
| 2824369413U, // CMPLS_WIDE_PPzZZ_H |
| 2516620549U, // CMPLS_WIDE_PPzZZ_S |
| 2516596386U, // CMPLT_PPzZI_B |
| 2516604578U, // CMPLT_PPzZI_D |
| 2824369826U, // CMPLT_PPzZI_H |
| 2516620962U, // CMPLT_PPzZI_S |
| 2516596386U, // CMPLT_WIDE_PPzZZ_B |
| 2824369826U, // CMPLT_WIDE_PPzZZ_H |
| 2516620962U, // CMPLT_WIDE_PPzZZ_S |
| 2516593208U, // CMPNE_PPzZI_B |
| 2516601400U, // CMPNE_PPzZI_D |
| 2824366648U, // CMPNE_PPzZI_H |
| 2516617784U, // CMPNE_PPzZI_S |
| 2516593208U, // CMPNE_PPzZZ_B |
| 2516601400U, // CMPNE_PPzZZ_D |
| 2824366648U, // CMPNE_PPzZZ_H |
| 2516617784U, // CMPNE_PPzZZ_S |
| 2516593208U, // CMPNE_WIDE_PPzZZ_B |
| 2824366648U, // CMPNE_WIDE_PPzZZ_H |
| 2516617784U, // CMPNE_WIDE_PPzZZ_S |
| 0U, // CMP_SWAP_128 |
| 0U, // CMP_SWAP_16 |
| 0U, // CMP_SWAP_32 |
| 0U, // CMP_SWAP_64 |
| 0U, // CMP_SWAP_8 |
| 68204438U, // CMTSTv16i8 |
| 2248202134U, // CMTSTv1i64 |
| 2216212374U, // CMTSTv2i32 |
| 2216736662U, // CMTSTv2i64 |
| 69777302U, // CMTSTv4i16 |
| 70301590U, // CMTSTv4i32 |
| 2218309526U, // CMTSTv8i16 |
| 2218833814U, // CMTSTv8i8 |
| 14187U, // CNOT_ZPmZ_B |
| 2147506027U, // CNOT_ZPmZ_D |
| 34109291U, // CNOT_ZPmZ_H |
| 38763U, // CNOT_ZPmZ_S |
| 704694234U, // CNTB_XPiI |
| 704694743U, // CNTD_XPiI |
| 704695811U, // CNTH_XPiI |
| 2516636303U, // CNTP_XPP_B |
| 2516636303U, // CNTP_XPP_D |
| 2516636303U, // CNTP_XPP_H |
| 2516636303U, // CNTP_XPP_S |
| 704698794U, // CNTW_XPiI |
| 14039U, // CNT_ZPmZ_B |
| 2147505879U, // CNT_ZPmZ_D |
| 34109143U, // CNT_ZPmZ_H |
| 38615U, // CNT_ZPmZ_S |
| 2215687895U, // CNTv16i8 |
| 71349975U, // CNTv8i8 |
| 2516604338U, // COMPACT_ZPZ_D |
| 2516620722U, // COMPACT_ZPZ_S |
| 2147498567U, // CPY_ZPmI_B |
| 23111U, // CPY_ZPmI_D |
| 738753095U, // CPY_ZPmI_H |
| 2147523143U, // CPY_ZPmI_S |
| 14919U, // CPY_ZPmR_B |
| 23111U, // CPY_ZPmR_D |
| 772307527U, // CPY_ZPmR_H |
| 39495U, // CPY_ZPmR_S |
| 14919U, // CPY_ZPmV_B |
| 23111U, // CPY_ZPmV_D |
| 772307527U, // CPY_ZPmV_H |
| 39495U, // CPY_ZPmV_S |
| 2516597319U, // CPY_ZPzI_B |
| 2516605511U, // CPY_ZPzI_D |
| 2824370759U, // CPY_ZPzI_H |
| 2516621895U, // CPY_ZPzI_S |
| 67164273U, // CPYi16 |
| 2214647921U, // CPYi32 |
| 67164273U, // CPYi64 |
| 2214647921U, // CPYi8 |
| 2248197041U, // CRC32Brr |
| 2248197204U, // CRC32CBrr |
| 2248199118U, // CRC32CHrr |
| 2248202499U, // CRC32CWrr |
| 2248202751U, // CRC32CXrr |
| 2248198954U, // CRC32Hrr |
| 2248202441U, // CRC32Wrr |
| 2248202690U, // CRC32Xrr |
| 2248200066U, // CSELWr |
| 2248200066U, // CSELXr |
| 2248198313U, // CSINCWr |
| 2248198313U, // CSINCXr |
| 2248202345U, // CSINVWr |
| 2248202345U, // CSINVXr |
| 2248198862U, // CSNEGWr |
| 2248198862U, // CSNEGXr |
| 100717283U, // CTERMEQ_WW |
| 100717283U, // CTERMEQ_XX |
| 100715055U, // CTERMNE_WW |
| 100715055U, // CTERMNE_XX |
| 0U, // CompilerBarrier |
| 73783U, // DCPS1 |
| 74210U, // DCPS2 |
| 74276U, // DCPS3 |
| 805356639U, // DECB_XPiI |
| 805357881U, // DECD_XPiI |
| 805325113U, // DECD_ZPiI |
| 805358553U, // DECH_XPiI |
| 8416217U, // DECH_ZPiI |
| 436261351U, // DECP_XP_B |
| 268489191U, // DECP_XP_D |
| 201380327U, // DECP_XP_H |
| 469815783U, // DECP_XP_S |
| 134238695U, // DECP_ZP_D |
| 846754279U, // DECP_ZP_H |
| 167809511U, // DECP_ZP_S |
| 805361934U, // DECW_XPiI |
| 805345550U, // DECW_ZPiI |
| 116278U, // DMB |
| 7210U, // DRPS |
| 116612U, // DSB |
| 872435935U, // DUPM_ZI |
| 905982627U, // DUP_ZI_B |
| 939545251U, // DUP_ZI_D |
| 8942243U, // DUP_ZI_H |
| 973116067U, // DUP_ZI_S |
| 100676259U, // DUP_ZR_B |
| 100684451U, // DUP_ZR_D |
| 848327331U, // DUP_ZR_H |
| 100700835U, // DUP_ZR_S |
| 436220579U, // DUP_ZZI_B |
| 268456611U, // DUP_ZZI_D |
| 1012953763U, // DUP_ZZI_H |
| 10089123U, // DUP_ZZI_Q |
| 469799587U, // DUP_ZZI_S |
| 101757603U, // DUPv16i8gpr |
| 2215686819U, // DUPv16i8lane |
| 102281891U, // DUPv2i32gpr |
| 2216211107U, // DUPv2i32lane |
| 102806179U, // DUPv2i64gpr |
| 69251747U, // DUPv2i64lane |
| 103330467U, // DUPv4i16gpr |
| 69776035U, // DUPv4i16lane |
| 103854755U, // DUPv4i32gpr |
| 2217783971U, // DUPv4i32lane |
| 104379043U, // DUPv8i16gpr |
| 70824611U, // DUPv8i16lane |
| 104903331U, // DUPv8i8gpr |
| 2218832547U, // DUPv8i8lane |
| 0U, // EMITBKEY |
| 0U, // EONWrr |
| 2248200500U, // EONWrs |
| 0U, // EONXrr |
| 2248200500U, // EONXrs |
| 68198942U, // EOR3 |
| 2415936030U, // EOR3_ZZZZ_D |
| 637547947U, // EORBT_ZZZ_B |
| 2281723307U, // EORBT_ZZZ_D |
| 2390259115U, // EORBT_ZZZ_H |
| 2315294123U, // EORBT_ZZZ_S |
| 2516596050U, // EORS_PPzPP |
| 637544416U, // EORTB_ZZZ_B |
| 2281719776U, // EORTB_ZZZ_D |
| 2390255584U, // EORTB_ZZZ_H |
| 2315290592U, // EORTB_ZZZ_S |
| 2516637826U, // EORV_VPZ_B |
| 2516637826U, // EORV_VPZ_D |
| 2516637826U, // EORV_VPZ_H |
| 2516637826U, // EORV_VPZ_S |
| 2248201161U, // EORWri |
| 0U, // EORWrr |
| 2248201161U, // EORWrs |
| 2248201161U, // EORXri |
| 0U, // EORXrr |
| 2248201161U, // EORXrs |
| 2516595657U, // EOR_PPzPP |
| 2415940553U, // EOR_ZI |
| 369112009U, // EOR_ZPmZ_B |
| 369120201U, // EOR_ZPmZ_D |
| 2555933641U, // EOR_ZPmZ_H |
| 369136585U, // EOR_ZPmZ_S |
| 2415940553U, // EOR_ZZZ |
| 68203465U, // EORv16i8 |
| 2218832841U, // EORv8i8 |
| 7215U, // ERET |
| 7158U, // ERETAA |
| 7165U, // ERETAB |
| 2248201238U, // EXTRWrri |
| 2248201238U, // EXTRXrri |
| 2583705540U, // EXT_ZZI |
| 3187685316U, // EXT_ZZI_B |
| 68204484U, // EXTv16i8 |
| 2218833860U, // EXTv8i8 |
| 0U, // F128CSEL |
| 2248198430U, // FABD16 |
| 2248198430U, // FABD32 |
| 2248198430U, // FABD64 |
| 369117470U, // FABD_ZPmZ_D |
| 2555930910U, // FABD_ZPmZ_H |
| 369133854U, // FABD_ZPmZ_S |
| 2216208670U, // FABDv2f32 |
| 2216732958U, // FABDv2f64 |
| 69773598U, // FABDv4f16 |
| 70297886U, // FABDv4f32 |
| 2218305822U, // FABDv8f16 |
| 100717707U, // FABSDr |
| 100717707U, // FABSHr |
| 100717707U, // FABSSr |
| 2147505291U, // FABS_ZPmZ_D |
| 34108555U, // FABS_ZPmZ_H |
| 38027U, // FABS_ZPmZ_S |
| 2216211595U, // FABSv2f32 |
| 69252235U, // FABSv2f64 |
| 2217260171U, // FABSv4f16 |
| 70300811U, // FABSv4f32 |
| 2218308747U, // FABSv8f16 |
| 2248198635U, // FACGE16 |
| 2248198635U, // FACGE32 |
| 2248198635U, // FACGE64 |
| 2516601323U, // FACGE_PPzZZ_D |
| 2824366571U, // FACGE_PPzZZ_H |
| 2516617707U, // FACGE_PPzZZ_S |
| 2216208875U, // FACGEv2f32 |
| 2216733163U, // FACGEv2f64 |
| 69773803U, // FACGEv4f16 |
| 70298091U, // FACGEv4f32 |
| 2218306027U, // FACGEv8f16 |
| 2248201671U, // FACGT16 |
| 2248201671U, // FACGT32 |
| 2248201671U, // FACGT64 |
| 2516604359U, // FACGT_PPzZZ_D |
| 2824369607U, // FACGT_PPzZZ_H |
| 2516620743U, // FACGT_PPzZZ_S |
| 2216211911U, // FACGTv2f32 |
| 2216736199U, // FACGTv2f64 |
| 69776839U, // FACGTv4f16 |
| 70301127U, // FACGTv4f32 |
| 2218309063U, // FACGTv8f16 |
| 2516632216U, // FADDA_VPZ_D |
| 2516632216U, // FADDA_VPZ_H |
| 2516632216U, // FADDA_VPZ_S |
| 2248198509U, // FADDDrr |
| 2248198509U, // FADDHrr |
| 369119749U, // FADDP_ZPmZZ_D |
| 2555933189U, // FADDP_ZPmZZ_H |
| 369136133U, // FADDP_ZPmZZ_S |
| 2216210949U, // FADDPv2f32 |
| 2216735237U, // FADDPv2f64 |
| 67162629U, // FADDPv2i16p |
| 2214646277U, // FADDPv2i32p |
| 67162629U, // FADDPv2i64p |
| 69775877U, // FADDPv4f16 |
| 70300165U, // FADDPv4f32 |
| 2218308101U, // FADDPv8f16 |
| 2248198509U, // FADDSrr |
| 2516637696U, // FADDV_VPZ_D |
| 2516637696U, // FADDV_VPZ_H |
| 2516637696U, // FADDV_VPZ_S |
| 369117549U, // FADD_ZPmI_D |
| 2555930989U, // FADD_ZPmI_H |
| 369133933U, // FADD_ZPmI_S |
| 369117549U, // FADD_ZPmZ_D |
| 2555930989U, // FADD_ZPmZ_H |
| 369133933U, // FADD_ZPmZ_S |
| 2415937901U, // FADD_ZZZ_D |
| 2388683117U, // FADD_ZZZ_H |
| 2617280877U, // FADD_ZZZ_S |
| 2216208749U, // FADDv2f32 |
| 2216733037U, // FADDv2f64 |
| 69773677U, // FADDv4f16 |
| 70297965U, // FADDv4f32 |
| 2218305901U, // FADDv8f16 |
| 369117527U, // FCADD_ZPmZ_D |
| 2555930967U, // FCADD_ZPmZ_H |
| 369133911U, // FCADD_ZPmZ_S |
| 2216208727U, // FCADDv2f32 |
| 2216733015U, // FCADDv2f64 |
| 69773655U, // FCADDv4f16 |
| 70297943U, // FCADDv4f32 |
| 2218305879U, // FCADDv8f16 |
| 2248200765U, // FCCMPDrr |
| 2248198735U, // FCCMPEDrr |
| 2248198735U, // FCCMPEHrr |
| 2248198735U, // FCCMPESrr |
| 2248200765U, // FCCMPHrr |
| 2248200765U, // FCCMPSrr |
| 2248200924U, // FCMEQ16 |
| 2248200924U, // FCMEQ32 |
| 2248200924U, // FCMEQ64 |
| 2516603612U, // FCMEQ_PPzZ0_D |
| 2824368860U, // FCMEQ_PPzZ0_H |
| 2516619996U, // FCMEQ_PPzZ0_S |
| 2516603612U, // FCMEQ_PPzZZ_D |
| 2824368860U, // FCMEQ_PPzZZ_H |
| 2516619996U, // FCMEQ_PPzZZ_S |
| 2248200924U, // FCMEQv1i16rz |
| 2248200924U, // FCMEQv1i32rz |
| 2248200924U, // FCMEQv1i64rz |
| 2216211164U, // FCMEQv2f32 |
| 2216735452U, // FCMEQv2f64 |
| 68727516U, // FCMEQv2i32rz |
| 2216735452U, // FCMEQv2i64rz |
| 69776092U, // FCMEQv4f16 |
| 70300380U, // FCMEQv4f32 |
| 69776092U, // FCMEQv4i16rz |
| 2217784028U, // FCMEQv4i32rz |
| 2218308316U, // FCMEQv8f16 |
| 70824668U, // FCMEQv8i16rz |
| 2248198651U, // FCMGE16 |
| 2248198651U, // FCMGE32 |
| 2248198651U, // FCMGE64 |
| 2516601339U, // FCMGE_PPzZ0_D |
| 2824366587U, // FCMGE_PPzZ0_H |
| 2516617723U, // FCMGE_PPzZ0_S |
| 2516601339U, // FCMGE_PPzZZ_D |
| 2824366587U, // FCMGE_PPzZZ_H |
| 2516617723U, // FCMGE_PPzZZ_S |
| 2248198651U, // FCMGEv1i16rz |
| 2248198651U, // FCMGEv1i32rz |
| 2248198651U, // FCMGEv1i64rz |
| 2216208891U, // FCMGEv2f32 |
| 2216733179U, // FCMGEv2f64 |
| 68725243U, // FCMGEv2i32rz |
| 2216733179U, // FCMGEv2i64rz |
| 69773819U, // FCMGEv4f16 |
| 70298107U, // FCMGEv4f32 |
| 69773819U, // FCMGEv4i16rz |
| 2217781755U, // FCMGEv4i32rz |
| 2218306043U, // FCMGEv8f16 |
| 70822395U, // FCMGEv8i16rz |
| 2248201687U, // FCMGT16 |
| 2248201687U, // FCMGT32 |
| 2248201687U, // FCMGT64 |
| 2516604375U, // FCMGT_PPzZ0_D |
| 2824369623U, // FCMGT_PPzZ0_H |
| 2516620759U, // FCMGT_PPzZ0_S |
| 2516604375U, // FCMGT_PPzZZ_D |
| 2824369623U, // FCMGT_PPzZZ_H |
| 2516620759U, // FCMGT_PPzZZ_S |
| 2248201687U, // FCMGTv1i16rz |
| 2248201687U, // FCMGTv1i32rz |
| 2248201687U, // FCMGTv1i64rz |
| 2216211927U, // FCMGTv2f32 |
| 2216736215U, // FCMGTv2f64 |
| 68728279U, // FCMGTv2i32rz |
| 2216736215U, // FCMGTv2i64rz |
| 69776855U, // FCMGTv4f16 |
| 70301143U, // FCMGTv4f32 |
| 69776855U, // FCMGTv4i16rz |
| 2217784791U, // FCMGTv4i32rz |
| 2218309079U, // FCMGTv8f16 |
| 70825431U, // FCMGTv8i16rz |
| 369115841U, // FCMLA_ZPmZZ_D |
| 2555929281U, // FCMLA_ZPmZZ_H |
| 369132225U, // FCMLA_ZPmZZ_S |
| 2390254273U, // FCMLA_ZZZI_H |
| 2315289281U, // FCMLA_ZZZI_S |
| 2484658881U, // FCMLAv2f32 |
| 2485183169U, // FCMLAv2f64 |
| 338223809U, // FCMLAv4f16 |
| 338223809U, // FCMLAv4f16_indexed |
| 338748097U, // FCMLAv4f32 |
| 338748097U, // FCMLAv4f32_indexed |
| 2486756033U, // FCMLAv8f16 |
| 2486756033U, // FCMLAv8f16_indexed |
| 2516601370U, // FCMLE_PPzZ0_D |
| 2824366618U, // FCMLE_PPzZ0_H |
| 2516617754U, // FCMLE_PPzZ0_S |
| 2248198682U, // FCMLEv1i16rz |
| 2248198682U, // FCMLEv1i32rz |
| 2248198682U, // FCMLEv1i64rz |
| 68725274U, // FCMLEv2i32rz |
| 2216733210U, // FCMLEv2i64rz |
| 69773850U, // FCMLEv4i16rz |
| 2217781786U, // FCMLEv4i32rz |
| 70822426U, // FCMLEv8i16rz |
| 2516604571U, // FCMLT_PPzZ0_D |
| 2824369819U, // FCMLT_PPzZ0_H |
| 2516620955U, // FCMLT_PPzZ0_S |
| 2248201883U, // FCMLTv1i16rz |
| 2248201883U, // FCMLTv1i32rz |
| 2248201883U, // FCMLTv1i64rz |
| 68728475U, // FCMLTv2i32rz |
| 2216736411U, // FCMLTv2i64rz |
| 69777051U, // FCMLTv4i16rz |
| 2217784987U, // FCMLTv4i32rz |
| 70825627U, // FCMLTv8i16rz |
| 2516601384U, // FCMNE_PPzZ0_D |
| 2824366632U, // FCMNE_PPzZ0_H |
| 2516617768U, // FCMNE_PPzZ0_S |
| 2516601384U, // FCMNE_PPzZZ_D |
| 2824366632U, // FCMNE_PPzZZ_H |
| 2516617768U, // FCMNE_PPzZZ_S |
| 10539588U, // FCMPDri |
| 100717124U, // FCMPDrr |
| 10537559U, // FCMPEDri |
| 100715095U, // FCMPEDrr |
| 10537559U, // FCMPEHri |
| 100715095U, // FCMPEHrr |
| 10537559U, // FCMPESri |
| 100715095U, // FCMPESrr |
| 10539588U, // FCMPHri |
| 100717124U, // FCMPHrr |
| 10539588U, // FCMPSri |
| 100717124U, // FCMPSrr |
| 2516603345U, // FCMUO_PPzZZ_D |
| 2824368593U, // FCMUO_PPzZZ_H |
| 2516619729U, // FCMUO_PPzZZ_S |
| 2147506758U, // FCPY_ZPmI_D |
| 1074297414U, // FCPY_ZPmI_H |
| 2147523142U, // FCPY_ZPmI_S |
| 2248200065U, // FCSELDrrr |
| 2248200065U, // FCSELHrrr |
| 2248200065U, // FCSELSrrr |
| 100717699U, // FCVTASUWDr |
| 100717699U, // FCVTASUWHr |
| 100717699U, // FCVTASUWSr |
| 100717699U, // FCVTASUXDr |
| 100717699U, // FCVTASUXHr |
| 100717699U, // FCVTASUXSr |
| 100717699U, // FCVTASv1f16 |
| 100717699U, // FCVTASv1i32 |
| 100717699U, // FCVTASv1i64 |
| 2216211587U, // FCVTASv2f32 |
| 69252227U, // FCVTASv2f64 |
| 2217260163U, // FCVTASv4f16 |
| 70300803U, // FCVTASv4f32 |
| 2218308739U, // FCVTASv8f16 |
| 100718544U, // FCVTAUUWDr |
| 100718544U, // FCVTAUUWHr |
| 100718544U, // FCVTAUUWSr |
| 100718544U, // FCVTAUUXDr |
| 100718544U, // FCVTAUUXHr |
| 100718544U, // FCVTAUUXSr |
| 100718544U, // FCVTAUv1f16 |
| 100718544U, // FCVTAUv1i32 |
| 100718544U, // FCVTAUv1i64 |
| 2216212432U, // FCVTAUv2f32 |
| 69253072U, // FCVTAUv2f64 |
| 2217261008U, // FCVTAUv4f16 |
| 70301648U, // FCVTAUv4f32 |
| 2218309584U, // FCVTAUv8f16 |
| 100718493U, // FCVTDHr |
| 100718493U, // FCVTDSr |
| 100718493U, // FCVTHDr |
| 100718493U, // FCVTHSr |
| 2147522251U, // FCVTLT_ZPmZ_HtoS |
| 22219U, // FCVTLT_ZPmZ_StoD |
| 2216734818U, // FCVTLv2i32 |
| 2217783394U, // FCVTLv4i16 |
| 69247313U, // FCVTLv4i32 |
| 2217779537U, // FCVTLv8i16 |
| 100717836U, // FCVTMSUWDr |
| 100717836U, // FCVTMSUWHr |
| 100717836U, // FCVTMSUWSr |
| 100717836U, // FCVTMSUXDr |
| 100717836U, // FCVTMSUXHr |
| 100717836U, // FCVTMSUXSr |
| 100717836U, // FCVTMSv1f16 |
| 100717836U, // FCVTMSv1i32 |
| 100717836U, // FCVTMSv1i64 |
| 2216211724U, // FCVTMSv2f32 |
| 69252364U, // FCVTMSv2f64 |
| 2217260300U, // FCVTMSv4f16 |
| 70300940U, // FCVTMSv4f32 |
| 2218308876U, // FCVTMSv8f16 |
| 100718560U, // FCVTMUUWDr |
| 100718560U, // FCVTMUUWHr |
| 100718560U, // FCVTMUUWSr |
| 100718560U, // FCVTMUUXDr |
| 100718560U, // FCVTMUUXHr |
| 100718560U, // FCVTMUUXSr |
| 100718560U, // FCVTMUv1f16 |
| 100718560U, // FCVTMUv1i32 |
| 100718560U, // FCVTMUv1i64 |
| 2216212448U, // FCVTMUv2f32 |
| 69253088U, // FCVTMUv2f64 |
| 2217261024U, // FCVTMUv4f16 |
| 70301664U, // FCVTMUv4f32 |
| 2218309600U, // FCVTMUv8f16 |
| 100717862U, // FCVTNSUWDr |
| 100717862U, // FCVTNSUWHr |
| 100717862U, // FCVTNSUWSr |
| 100717862U, // FCVTNSUXDr |
| 100717862U, // FCVTNSUXHr |
| 100717862U, // FCVTNSUXSr |
| 100717862U, // FCVTNSv1f16 |
| 100717862U, // FCVTNSv1i32 |
| 100717862U, // FCVTNSv1i64 |
| 2216211750U, // FCVTNSv2f32 |
| 69252390U, // FCVTNSv2f64 |
| 2217260326U, // FCVTNSv4f16 |
| 70300966U, // FCVTNSv4f32 |
| 2218308902U, // FCVTNSv8f16 |
| 2147522330U, // FCVTNT_ZPmZ_DtoS |
| 1107851034U, // FCVTNT_ZPmZ_StoH |
| 100718568U, // FCVTNUUWDr |
| 100718568U, // FCVTNUUWHr |
| 100718568U, // FCVTNUUWSr |
| 100718568U, // FCVTNUUXDr |
| 100718568U, // FCVTNUUXHr |
| 100718568U, // FCVTNUUXSr |
| 100718568U, // FCVTNUv1f16 |
| 100718568U, // FCVTNUv1i32 |
| 100718568U, // FCVTNUv1i64 |
| 2216212456U, // FCVTNUv2f32 |
| 69253096U, // FCVTNUv2f64 |
| 2217261032U, // FCVTNUv4f16 |
| 70301672U, // FCVTNUv4f32 |
| 2218309608U, // FCVTNUv8f16 |
| 68727144U, // FCVTNv2i32 |
| 69775720U, // FCVTNv4i16 |
| 338747799U, // FCVTNv4i32 |
| 339272087U, // FCVTNv8i16 |
| 100717885U, // FCVTPSUWDr |
| 100717885U, // FCVTPSUWHr |
| 100717885U, // FCVTPSUWSr |
| 100717885U, // FCVTPSUXDr |
| 100717885U, // FCVTPSUXHr |
| 100717885U, // FCVTPSUXSr |
| 100717885U, // FCVTPSv1f16 |
| 100717885U, // FCVTPSv1i32 |
| 100717885U, // FCVTPSv1i64 |
| 2216211773U, // FCVTPSv2f32 |
| 69252413U, // FCVTPSv2f64 |
| 2217260349U, // FCVTPSv4f16 |
| 70300989U, // FCVTPSv4f32 |
| 2218308925U, // FCVTPSv8f16 |
| 100718576U, // FCVTPUUWDr |
| 100718576U, // FCVTPUUWHr |
| 100718576U, // FCVTPUUWSr |
| 100718576U, // FCVTPUUXDr |
| 100718576U, // FCVTPUUXHr |
| 100718576U, // FCVTPUUXSr |
| 100718576U, // FCVTPUv1f16 |
| 100718576U, // FCVTPUv1i32 |
| 100718576U, // FCVTPUv1i64 |
| 2216212464U, // FCVTPUv2f32 |
| 69253104U, // FCVTPUv2f64 |
| 2217261040U, // FCVTPUv4f16 |
| 70301680U, // FCVTPUv4f32 |
| 2218309616U, // FCVTPUv8f16 |
| 100718493U, // FCVTSDr |
| 100718493U, // FCVTSHr |
| 2147522384U, // FCVTXNT_ZPmZ_DtoS |
| 100716958U, // FCVTXNv1i64 |
| 68727198U, // FCVTXNv2f32 |
| 338747853U, // FCVTXNv4f32 |
| 2147523126U, // FCVTX_ZPmZ_DtoS |
| 2248201586U, // FCVTZSSWDri |
| 2248201586U, // FCVTZSSWHri |
| 2248201586U, // FCVTZSSWSri |
| 2248201586U, // FCVTZSSXDri |
| 2248201586U, // FCVTZSSXHri |
| 2248201586U, // FCVTZSSXSri |
| 100717938U, // FCVTZSUWDr |
| 100717938U, // FCVTZSUWHr |
| 100717938U, // FCVTZSUWSr |
| 100717938U, // FCVTZSUXDr |
| 100717938U, // FCVTZSUXHr |
| 100717938U, // FCVTZSUXSr |
| 2147505522U, // FCVTZS_ZPmZ_DtoD |
| 2147521906U, // FCVTZS_ZPmZ_DtoS |
| 2147505522U, // FCVTZS_ZPmZ_HtoD |
| 34108786U, // FCVTZS_ZPmZ_HtoH |
| 2147521906U, // FCVTZS_ZPmZ_HtoS |
| 21874U, // FCVTZS_ZPmZ_StoD |
| 38258U, // FCVTZS_ZPmZ_StoS |
| 2248201586U, // FCVTZSd |
| 2248201586U, // FCVTZSh |
| 2248201586U, // FCVTZSs |
| 100717938U, // FCVTZSv1f16 |
| 100717938U, // FCVTZSv1i32 |
| 100717938U, // FCVTZSv1i64 |
| 2216211826U, // FCVTZSv2f32 |
| 69252466U, // FCVTZSv2f64 |
| 2216211826U, // FCVTZSv2i32_shift |
| 2216736114U, // FCVTZSv2i64_shift |
| 2217260402U, // FCVTZSv4f16 |
| 70301042U, // FCVTZSv4f32 |
| 69776754U, // FCVTZSv4i16_shift |
| 70301042U, // FCVTZSv4i32_shift |
| 2218308978U, // FCVTZSv8f16 |
| 2218308978U, // FCVTZSv8i16_shift |
| 2248202232U, // FCVTZUSWDri |
| 2248202232U, // FCVTZUSWHri |
| 2248202232U, // FCVTZUSWSri |
| 2248202232U, // FCVTZUSXDri |
| 2248202232U, // FCVTZUSXHri |
| 2248202232U, // FCVTZUSXSri |
| 100718584U, // FCVTZUUWDr |
| 100718584U, // FCVTZUUWHr |
| 100718584U, // FCVTZUUWSr |
| 100718584U, // FCVTZUUXDr |
| 100718584U, // FCVTZUUXHr |
| 100718584U, // FCVTZUUXSr |
| 2147506168U, // FCVTZU_ZPmZ_DtoD |
| 2147522552U, // FCVTZU_ZPmZ_DtoS |
| 2147506168U, // FCVTZU_ZPmZ_HtoD |
| 34109432U, // FCVTZU_ZPmZ_HtoH |
| 2147522552U, // FCVTZU_ZPmZ_HtoS |
| 22520U, // FCVTZU_ZPmZ_StoD |
| 38904U, // FCVTZU_ZPmZ_StoS |
| 2248202232U, // FCVTZUd |
| 2248202232U, // FCVTZUh |
| 2248202232U, // FCVTZUs |
| 100718584U, // FCVTZUv1f16 |
| 100718584U, // FCVTZUv1i32 |
| 100718584U, // FCVTZUv1i64 |
| 2216212472U, // FCVTZUv2f32 |
| 69253112U, // FCVTZUv2f64 |
| 2216212472U, // FCVTZUv2i32_shift |
| 2216736760U, // FCVTZUv2i64_shift |
| 2217261048U, // FCVTZUv4f16 |
| 70301688U, // FCVTZUv4f32 |
| 69777400U, // FCVTZUv4i16_shift |
| 70301688U, // FCVTZUv4i32_shift |
| 2218309624U, // FCVTZUv8f16 |
| 2218309624U, // FCVTZUv8i16_shift |
| 1141405597U, // FCVT_ZPmZ_DtoH |
| 2147522461U, // FCVT_ZPmZ_DtoS |
| 2147506077U, // FCVT_ZPmZ_HtoD |
| 2147522461U, // FCVT_ZPmZ_HtoS |
| 22429U, // FCVT_ZPmZ_StoD |
| 1107851165U, // FCVT_ZPmZ_StoH |
| 2248202272U, // FDIVDrr |
| 2248202272U, // FDIVHrr |
| 369120311U, // FDIVR_ZPmZ_D |
| 2555933751U, // FDIVR_ZPmZ_H |
| 369136695U, // FDIVR_ZPmZ_S |
| 2248202272U, // FDIVSrr |
| 369121312U, // FDIV_ZPmZ_D |
| 2555934752U, // FDIV_ZPmZ_H |
| 369137696U, // FDIV_ZPmZ_S |
| 2216212512U, // FDIVv2f32 |
| 2216736800U, // FDIVv2f64 |
| 69777440U, // FDIVv4f16 |
| 70301728U, // FDIVv4f32 |
| 2218309664U, // FDIVv8f16 |
| 1174426274U, // FDUP_ZI_D |
| 11039394U, // FDUP_ZI_H |
| 1174442658U, // FDUP_ZI_S |
| 268452603U, // FEXPA_ZZ_D |
| 845177595U, // FEXPA_ZZ_H |
| 469795579U, // FEXPA_ZZ_S |
| 100717946U, // FJCVTZS |
| 2147501209U, // FLOGB_ZPmZ_D |
| 34104473U, // FLOGB_ZPmZ_H |
| 33945U, // FLOGB_ZPmZ_S |
| 2248198545U, // FMADDDrrr |
| 2248198545U, // FMADDHrrr |
| 2248198545U, // FMADDSrrr |
| 369117450U, // FMAD_ZPmZZ_D |
| 2555930890U, // FMAD_ZPmZZ_H |
| 369133834U, // FMAD_ZPmZZ_S |
| 2248202724U, // FMAXDrr |
| 2248202724U, // FMAXHrr |
| 2248200407U, // FMAXNMDrr |
| 2248200407U, // FMAXNMHrr |
| 369119827U, // FMAXNMP_ZPmZZ_D |
| 2555933267U, // FMAXNMP_ZPmZZ_H |
| 369136211U, // FMAXNMP_ZPmZZ_S |
| 2216211027U, // FMAXNMPv2f32 |
| 2216735315U, // FMAXNMPv2f64 |
| 67162707U, // FMAXNMPv2i16p |
| 2214646355U, // FMAXNMPv2i32p |
| 67162707U, // FMAXNMPv2i64p |
| 69775955U, // FMAXNMPv4f16 |
| 70300243U, // FMAXNMPv4f32 |
| 2218308179U, // FMAXNMPv8f16 |
| 2248200407U, // FMAXNMSrr |
| 2516637771U, // FMAXNMV_VPZ_D |
| 2516637771U, // FMAXNMV_VPZ_H |
| 2516637771U, // FMAXNMV_VPZ_S |
| 2214647883U, // FMAXNMVv4i16v |
| 67164235U, // FMAXNMVv4i32v |
| 2214647883U, // FMAXNMVv8i16v |
| 369119447U, // FMAXNM_ZPmI_D |
| 2555932887U, // FMAXNM_ZPmI_H |
| 369135831U, // FMAXNM_ZPmI_S |
| 369119447U, // FMAXNM_ZPmZ_D |
| 2555932887U, // FMAXNM_ZPmZ_H |
| 369135831U, // FMAXNM_ZPmZ_S |
| 2216210647U, // FMAXNMv2f32 |
| 2216734935U, // FMAXNMv2f64 |
| 69775575U, // FMAXNMv4f16 |
| 70299863U, // FMAXNMv4f32 |
| 2218307799U, // FMAXNMv8f16 |
| 369119924U, // FMAXP_ZPmZZ_D |
| 2555933364U, // FMAXP_ZPmZZ_H |
| 369136308U, // FMAXP_ZPmZZ_S |
| 2216211124U, // FMAXPv2f32 |
| 2216735412U, // FMAXPv2f64 |
| 67162804U, // FMAXPv2i16p |
| 2214646452U, // FMAXPv2i32p |
| 67162804U, // FMAXPv2i64p |
| 69776052U, // FMAXPv4f16 |
| 70300340U, // FMAXPv4f32 |
| 2218308276U, // FMAXPv8f16 |
| 2248202724U, // FMAXSrr |
| 2516637832U, // FMAXV_VPZ_D |
| 2516637832U, // FMAXV_VPZ_H |
| 2516637832U, // FMAXV_VPZ_S |
| 2214647944U, // FMAXVv4i16v |
| 67164296U, // FMAXVv4i32v |
| 2214647944U, // FMAXVv8i16v |
| 369121764U, // FMAX_ZPmI_D |
| 2555935204U, // FMAX_ZPmI_H |
| 369138148U, // FMAX_ZPmI_S |
| 369121764U, // FMAX_ZPmZ_D |
| 2555935204U, // FMAX_ZPmZ_H |
| 369138148U, // FMAX_ZPmZ_S |
| 2216212964U, // FMAXv2f32 |
| 2216737252U, // FMAXv2f64 |
| 69777892U, // FMAXv4f16 |
| 70302180U, // FMAXv4f32 |
| 2218310116U, // FMAXv8f16 |
| 2248200466U, // FMINDrr |
| 2248200466U, // FMINHrr |
| 2248200399U, // FMINNMDrr |
| 2248200399U, // FMINNMHrr |
| 369119818U, // FMINNMP_ZPmZZ_D |
| 2555933258U, // FMINNMP_ZPmZZ_H |
| 369136202U, // FMINNMP_ZPmZZ_S |
| 2216211018U, // FMINNMPv2f32 |
| 2216735306U, // FMINNMPv2f64 |
| 67162698U, // FMINNMPv2i16p |
| 2214646346U, // FMINNMPv2i32p |
| 67162698U, // FMINNMPv2i64p |
| 69775946U, // FMINNMPv4f16 |
| 70300234U, // FMINNMPv4f32 |
| 2218308170U, // FMINNMPv8f16 |
| 2248200399U, // FMINNMSrr |
| 2516637762U, // FMINNMV_VPZ_D |
| 2516637762U, // FMINNMV_VPZ_H |
| 2516637762U, // FMINNMV_VPZ_S |
| 2214647874U, // FMINNMVv4i16v |
| 67164226U, // FMINNMVv4i32v |
| 2214647874U, // FMINNMVv8i16v |
| 369119439U, // FMINNM_ZPmI_D |
| 2555932879U, // FMINNM_ZPmI_H |
| 369135823U, // FMINNM_ZPmI_S |
| 369119439U, // FMINNM_ZPmZ_D |
| 2555932879U, // FMINNM_ZPmZ_H |
| 369135823U, // FMINNM_ZPmZ_S |
| 2216210639U, // FMINNMv2f32 |
| 2216734927U, // FMINNMv2f64 |
| 69775567U, // FMINNMv4f16 |
| 70299855U, // FMINNMv4f32 |
| 2218307791U, // FMINNMv8f16 |
| 369119842U, // FMINP_ZPmZZ_D |
| 2555933282U, // FMINP_ZPmZZ_H |
| 369136226U, // FMINP_ZPmZZ_S |
| 2216211042U, // FMINPv2f32 |
| 2216735330U, // FMINPv2f64 |
| 67162722U, // FMINPv2i16p |
| 2214646370U, // FMINPv2i32p |
| 67162722U, // FMINPv2i64p |
| 69775970U, // FMINPv4f16 |
| 70300258U, // FMINPv4f32 |
| 2218308194U, // FMINPv8f16 |
| 2248200466U, // FMINSrr |
| 2516637780U, // FMINV_VPZ_D |
| 2516637780U, // FMINV_VPZ_H |
| 2516637780U, // FMINV_VPZ_S |
| 2214647892U, // FMINVv4i16v |
| 67164244U, // FMINVv4i32v |
| 2214647892U, // FMINVv8i16v |
| 369119506U, // FMIN_ZPmI_D |
| 2555932946U, // FMIN_ZPmI_H |
| 369135890U, // FMIN_ZPmI_S |
| 369119506U, // FMIN_ZPmZ_D |
| 2555932946U, // FMIN_ZPmZ_H |
| 369135890U, // FMIN_ZPmZ_S |
| 2216210706U, // FMINv2f32 |
| 2216734994U, // FMINv2f64 |
| 69775634U, // FMINv4f16 |
| 70299922U, // FMINv4f32 |
| 2218307858U, // FMINv8f16 |
| 337174709U, // FMLAL2lanev4f16 |
| 338747573U, // FMLAL2lanev8f16 |
| 337174709U, // FMLAL2v4f16 |
| 338747573U, // FMLAL2v8f16 |
| 2449507544U, // FMLALB_ZZZI_SHH |
| 2449507544U, // FMLALB_ZZZ_SHH |
| 2449511941U, // FMLALT_ZZZI_SHH |
| 2449511941U, // FMLALT_ZZZ_SHH |
| 337178291U, // FMLALlanev4f16 |
| 338751155U, // FMLALlanev8f16 |
| 337178291U, // FMLALv4f16 |
| 338751155U, // FMLALv8f16 |
| 369115848U, // FMLA_ZPmZZ_D |
| 2555929288U, // FMLA_ZPmZZ_H |
| 369132232U, // FMLA_ZPmZZ_S |
| 2281718472U, // FMLA_ZZZI_D |
| 2390254280U, // FMLA_ZZZI_H |
| 2315289288U, // FMLA_ZZZI_S |
| 2684445384U, // FMLAv1i16_indexed |
| 2684445384U, // FMLAv1i32_indexed |
| 2684445384U, // FMLAv1i64_indexed |
| 2484658888U, // FMLAv2f32 |
| 2485183176U, // FMLAv2f64 |
| 2484658888U, // FMLAv2i32_indexed |
| 2485183176U, // FMLAv2i64_indexed |
| 338223816U, // FMLAv4f16 |
| 338748104U, // FMLAv4f32 |
| 338223816U, // FMLAv4i16_indexed |
| 338748104U, // FMLAv4i32_indexed |
| 2486756040U, // FMLAv8f16 |
| 2486756040U, // FMLAv8i16_indexed |
| 337174841U, // FMLSL2lanev4f16 |
| 338747705U, // FMLSL2lanev8f16 |
| 337174841U, // FMLSL2v4f16 |
| 338747705U, // FMLSL2v8f16 |
| 2449507841U, // FMLSLB_ZZZI_SHH |
| 2449507841U, // FMLSLB_ZZZ_SHH |
| 2449512115U, // FMLSLT_ZZZI_SHH |
| 2449512115U, // FMLSLT_ZZZ_SHH |
| 337178687U, // FMLSLlanev4f16 |
| 338751551U, // FMLSLlanev8f16 |
| 337178687U, // FMLSLv4f16 |
| 338751551U, // FMLSLv8f16 |
| 369120504U, // FMLS_ZPmZZ_D |
| 2555933944U, // FMLS_ZPmZZ_H |
| 369136888U, // FMLS_ZPmZZ_S |
| 2281723128U, // FMLS_ZZZI_D |
| 2390258936U, // FMLS_ZZZI_H |
| 2315293944U, // FMLS_ZZZI_S |
| 2684450040U, // FMLSv1i16_indexed |
| 2684450040U, // FMLSv1i32_indexed |
| 2684450040U, // FMLSv1i64_indexed |
| 2484663544U, // FMLSv2f32 |
| 2485187832U, // FMLSv2f64 |
| 2484663544U, // FMLSv2i32_indexed |
| 2485187832U, // FMLSv2i64_indexed |
| 338228472U, // FMLSv4f16 |
| 338752760U, // FMLSv4f32 |
| 338228472U, // FMLSv4i16_indexed |
| 338752760U, // FMLSv4i32_indexed |
| 2486760696U, // FMLSv8f16 |
| 2486760696U, // FMLSv8i16_indexed |
| 0U, // FMOVD0 |
| 67164272U, // FMOVDXHighr |
| 100718704U, // FMOVDXr |
| 1174460528U, // FMOVDi |
| 100718704U, // FMOVDr |
| 0U, // FMOVH0 |
| 100718704U, // FMOVHWr |
| 100718704U, // FMOVHXr |
| 1174460528U, // FMOVHi |
| 100718704U, // FMOVHr |
| 0U, // FMOVS0 |
| 100718704U, // FMOVSWr |
| 1174460528U, // FMOVSi |
| 100718704U, // FMOVSr |
| 100718704U, // FMOVWHr |
| 100718704U, // FMOVWSr |
| 112244848U, // FMOVXDHighr |
| 100718704U, // FMOVXDr |
| 100718704U, // FMOVXHr |
| 1176025200U, // FMOVv2f32_ns |
| 1176549488U, // FMOVv2f64_ns |
| 1177073776U, // FMOVv4f16_ns |
| 1177598064U, // FMOVv4f32_ns |
| 1178122352U, // FMOVv8f16_ns |
| 369117070U, // FMSB_ZPmZZ_D |
| 2555930510U, // FMSB_ZPmZZ_H |
| 369133454U, // FMSB_ZPmZZ_S |
| 2248198159U, // FMSUBDrrr |
| 2248198159U, // FMSUBHrrr |
| 2248198159U, // FMSUBSrrr |
| 2248200297U, // FMULDrr |
| 2248200297U, // FMULHrr |
| 2248200297U, // FMULSrr |
| 2248202783U, // FMULX16 |
| 2248202783U, // FMULX32 |
| 2248202783U, // FMULX64 |
| 369121823U, // FMULX_ZPmZ_D |
| 2555935263U, // FMULX_ZPmZ_H |
| 369138207U, // FMULX_ZPmZ_S |
| 2248202783U, // FMULXv1i16_indexed |
| 2248202783U, // FMULXv1i32_indexed |
| 2248202783U, // FMULXv1i64_indexed |
| 2216213023U, // FMULXv2f32 |
| 2216737311U, // FMULXv2f64 |
| 2216213023U, // FMULXv2i32_indexed |
| 2216737311U, // FMULXv2i64_indexed |
| 69777951U, // FMULXv4f16 |
| 70302239U, // FMULXv4f32 |
| 69777951U, // FMULXv4i16_indexed |
| 70302239U, // FMULXv4i32_indexed |
| 2218310175U, // FMULXv8f16 |
| 2218310175U, // FMULXv8i16_indexed |
| 369119337U, // FMUL_ZPmI_D |
| 2555932777U, // FMUL_ZPmI_H |
| 369135721U, // FMUL_ZPmI_S |
| 369119337U, // FMUL_ZPmZ_D |
| 2555932777U, // FMUL_ZPmZ_H |
| 369135721U, // FMUL_ZPmZ_S |
| 2415939689U, // FMUL_ZZZI_D |
| 2388684905U, // FMUL_ZZZI_H |
| 2617282665U, // FMUL_ZZZI_S |
| 2415939689U, // FMUL_ZZZ_D |
| 2388684905U, // FMUL_ZZZ_H |
| 2617282665U, // FMUL_ZZZ_S |
| 2248200297U, // FMULv1i16_indexed |
| 2248200297U, // FMULv1i32_indexed |
| 2248200297U, // FMULv1i64_indexed |
| 2216210537U, // FMULv2f32 |
| 2216734825U, // FMULv2f64 |
| 2216210537U, // FMULv2i32_indexed |
| 2216734825U, // FMULv2i64_indexed |
| 69775465U, // FMULv4f16 |
| 70299753U, // FMULv4f32 |
| 69775465U, // FMULv4i16_indexed |
| 70299753U, // FMULv4i32_indexed |
| 2218307689U, // FMULv8f16 |
| 2218307689U, // FMULv8i16_indexed |
| 100715201U, // FNEGDr |
| 100715201U, // FNEGHr |
| 100715201U, // FNEGSr |
| 2147502785U, // FNEG_ZPmZ_D |
| 34106049U, // FNEG_ZPmZ_H |
| 35521U, // FNEG_ZPmZ_S |
| 2216209089U, // FNEGv2f32 |
| 69249729U, // FNEGv2f64 |
| 2217257665U, // FNEGv4f16 |
| 70298305U, // FNEGv4f32 |
| 2218306241U, // FNEGv8f16 |
| 2248198552U, // FNMADDDrrr |
| 2248198552U, // FNMADDHrrr |
| 2248198552U, // FNMADDSrrr |
| 369117456U, // FNMAD_ZPmZZ_D |
| 2555930896U, // FNMAD_ZPmZZ_H |
| 369133840U, // FNMAD_ZPmZZ_S |
| 369115854U, // FNMLA_ZPmZZ_D |
| 2555929294U, // FNMLA_ZPmZZ_H |
| 369132238U, // FNMLA_ZPmZZ_S |
| 369120510U, // FNMLS_ZPmZZ_D |
| 2555933950U, // FNMLS_ZPmZZ_H |
| 369136894U, // FNMLS_ZPmZZ_S |
| 369117076U, // FNMSB_ZPmZZ_D |
| 2555930516U, // FNMSB_ZPmZZ_H |
| 369133460U, // FNMSB_ZPmZZ_S |
| 2248198166U, // FNMSUBDrrr |
| 2248198166U, // FNMSUBHrrr |
| 2248198166U, // FNMSUBSrrr |
| 2248200303U, // FNMULDrr |
| 2248200303U, // FNMULHrr |
| 2248200303U, // FNMULSrr |
| 268454463U, // FRECPE_ZZ_D |
| 845179455U, // FRECPE_ZZ_H |
| 469797439U, // FRECPE_ZZ_S |
| 100715071U, // FRECPEv1f16 |
| 100715071U, // FRECPEv1i32 |
| 100715071U, // FRECPEv1i64 |
| 2216208959U, // FRECPEv2f32 |
| 69249599U, // FRECPEv2f64 |
| 2217257535U, // FRECPEv4f16 |
| 70298175U, // FRECPEv4f32 |
| 2218306111U, // FRECPEv8f16 |
| 2248201525U, // FRECPS16 |
| 2248201525U, // FRECPS32 |
| 2248201525U, // FRECPS64 |
| 2415940917U, // FRECPS_ZZZ_D |
| 2388686133U, // FRECPS_ZZZ_H |
| 2617283893U, // FRECPS_ZZZ_S |
| 2216211765U, // FRECPSv2f32 |
| 2216736053U, // FRECPSv2f64 |
| 69776693U, // FRECPSv4f16 |
| 70300981U, // FRECPSv4f32 |
| 2218308917U, // FRECPSv8f16 |
| 2147506726U, // FRECPX_ZPmZ_D |
| 34109990U, // FRECPX_ZPmZ_H |
| 39462U, // FRECPX_ZPmZ_S |
| 100719142U, // FRECPXv1f16 |
| 100719142U, // FRECPXv1i32 |
| 100719142U, // FRECPXv1i64 |
| 100719050U, // FRINT32XDr |
| 100719050U, // FRINT32XSr |
| 2216212938U, // FRINT32Xv2f32 |
| 69253578U, // FRINT32Xv2f64 |
| 70302154U, // FRINT32Xv4f32 |
| 100719180U, // FRINT32ZDr |
| 100719180U, // FRINT32ZSr |
| 2216213068U, // FRINT32Zv2f32 |
| 69253708U, // FRINT32Zv2f64 |
| 70302284U, // FRINT32Zv4f32 |
| 100719060U, // FRINT64XDr |
| 100719060U, // FRINT64XSr |
| 2216212948U, // FRINT64Xv2f32 |
| 69253588U, // FRINT64Xv2f64 |
| 70302164U, // FRINT64Xv4f32 |
| 100719190U, // FRINT64ZDr |
| 100719190U, // FRINT64ZSr |
| 2216213078U, // FRINT64Zv2f32 |
| 69253718U, // FRINT64Zv2f64 |
| 70302294U, // FRINT64Zv4f32 |
| 100713274U, // FRINTADr |
| 100713274U, // FRINTAHr |
| 100713274U, // FRINTASr |
| 2147500858U, // FRINTA_ZPmZ_D |
| 34104122U, // FRINTA_ZPmZ_H |
| 33594U, // FRINTA_ZPmZ_S |
| 2216207162U, // FRINTAv2f32 |
| 69247802U, // FRINTAv2f64 |
| 2217255738U, // FRINTAv4f16 |
| 70296378U, // FRINTAv4f32 |
| 2218304314U, // FRINTAv8f16 |
| 100716154U, // FRINTIDr |
| 100716154U, // FRINTIHr |
| 100716154U, // FRINTISr |
| 2147503738U, // FRINTI_ZPmZ_D |
| 34107002U, // FRINTI_ZPmZ_H |
| 36474U, // FRINTI_ZPmZ_S |
| 2216210042U, // FRINTIv2f32 |
| 69250682U, // FRINTIv2f64 |
| 2217258618U, // FRINTIv4f16 |
| 70299258U, // FRINTIv4f32 |
| 2218307194U, // FRINTIv8f16 |
| 100716773U, // FRINTMDr |
| 100716773U, // FRINTMHr |
| 100716773U, // FRINTMSr |
| 2147504357U, // FRINTM_ZPmZ_D |
| 34107621U, // FRINTM_ZPmZ_H |
| 37093U, // FRINTM_ZPmZ_S |
| 2216210661U, // FRINTMv2f32 |
| 69251301U, // FRINTMv2f64 |
| 2217259237U, // FRINTMv4f16 |
| 70299877U, // FRINTMv4f32 |
| 2218307813U, // FRINTMv8f16 |
| 100716896U, // FRINTNDr |
| 100716896U, // FRINTNHr |
| 100716896U, // FRINTNSr |
| 2147504480U, // FRINTN_ZPmZ_D |
| 34107744U, // FRINTN_ZPmZ_H |
| 37216U, // FRINTN_ZPmZ_S |
| 2216210784U, // FRINTNv2f32 |
| 69251424U, // FRINTNv2f64 |
| 2217259360U, // FRINTNv4f16 |
| 70300000U, // FRINTNv4f32 |
| 2218307936U, // FRINTNv8f16 |
| 100717205U, // FRINTPDr |
| 100717205U, // FRINTPHr |
| 100717205U, // FRINTPSr |
| 2147504789U, // FRINTP_ZPmZ_D |
| 34108053U, // FRINTP_ZPmZ_H |
| 37525U, // FRINTP_ZPmZ_S |
| 2216211093U, // FRINTPv2f32 |
| 69251733U, // FRINTPv2f64 |
| 2217259669U, // FRINTPv4f16 |
| 70300309U, // FRINTPv4f32 |
| 2218308245U, // FRINTPv8f16 |
| 100719150U, // FRINTXDr |
| 100719150U, // FRINTXHr |
| 100719150U, // FRINTXSr |
| 2147506734U, // FRINTX_ZPmZ_D |
| 34109998U, // FRINTX_ZPmZ_H |
| 39470U, // FRINTX_ZPmZ_S |
| 2216213038U, // FRINTXv2f32 |
| 69253678U, // FRINTXv2f64 |
| 2217261614U, // FRINTXv4f16 |
| 70302254U, // FRINTXv4f32 |
| 2218310190U, // FRINTXv8f16 |
| 100719257U, // FRINTZDr |
| 100719257U, // FRINTZHr |
| 100719257U, // FRINTZSr |
| 2147506841U, // FRINTZ_ZPmZ_D |
| 34110105U, // FRINTZ_ZPmZ_H |
| 39577U, // FRINTZ_ZPmZ_S |
| 2216213145U, // FRINTZv2f32 |
| 69253785U, // FRINTZv2f64 |
| 2217261721U, // FRINTZv4f16 |
| 70302361U, // FRINTZv4f32 |
| 2218310297U, // FRINTZv8f16 |
| 268454508U, // FRSQRTE_ZZ_D |
| 845179500U, // FRSQRTE_ZZ_H |
| 469797484U, // FRSQRTE_ZZ_S |
| 100715116U, // FRSQRTEv1f16 |
| 100715116U, // FRSQRTEv1i32 |
| 100715116U, // FRSQRTEv1i64 |
| 2216209004U, // FRSQRTEv2f32 |
| 69249644U, // FRSQRTEv2f64 |
| 2217257580U, // FRSQRTEv4f16 |
| 70298220U, // FRSQRTEv4f32 |
| 2218306156U, // FRSQRTEv8f16 |
| 2248201572U, // FRSQRTS16 |
| 2248201572U, // FRSQRTS32 |
| 2248201572U, // FRSQRTS64 |
| 2415940964U, // FRSQRTS_ZZZ_D |
| 2388686180U, // FRSQRTS_ZZZ_H |
| 2617283940U, // FRSQRTS_ZZZ_S |
| 2216211812U, // FRSQRTSv2f32 |
| 2216736100U, // FRSQRTSv2f64 |
| 69776740U, // FRSQRTSv4f16 |
| 70301028U, // FRSQRTSv4f32 |
| 2218308964U, // FRSQRTSv8f16 |
| 369117705U, // FSCALE_ZPmZ_D |
| 2555931145U, // FSCALE_ZPmZ_H |
| 369134089U, // FSCALE_ZPmZ_S |
| 100718457U, // FSQRTDr |
| 100718457U, // FSQRTHr |
| 100718457U, // FSQRTSr |
| 2147506041U, // FSQRT_ZPmZ_D |
| 34109305U, // FSQRT_ZPmZ_H |
| 38777U, // FSQRT_ZPmZ_S |
| 2216212345U, // FSQRTv2f32 |
| 69252985U, // FSQRTv2f64 |
| 2217260921U, // FSQRTv4f16 |
| 70301561U, // FSQRTv4f32 |
| 2218309497U, // FSQRTv8f16 |
| 2248198139U, // FSUBDrr |
| 2248198139U, // FSUBHrr |
| 369120029U, // FSUBR_ZPmI_D |
| 2555933469U, // FSUBR_ZPmI_H |
| 369136413U, // FSUBR_ZPmI_S |
| 369120029U, // FSUBR_ZPmZ_D |
| 2555933469U, // FSUBR_ZPmZ_H |
| 369136413U, // FSUBR_ZPmZ_S |
| 2248198139U, // FSUBSrr |
| 369117179U, // FSUB_ZPmI_D |
| 2555930619U, // FSUB_ZPmI_H |
| 369133563U, // FSUB_ZPmI_S |
| 369117179U, // FSUB_ZPmZ_D |
| 2555930619U, // FSUB_ZPmZ_H |
| 369133563U, // FSUB_ZPmZ_S |
| 2415937531U, // FSUB_ZZZ_D |
| 2388682747U, // FSUB_ZZZ_H |
| 2617280507U, // FSUB_ZZZ_S |
| 2216208379U, // FSUBv2f32 |
| 2216732667U, // FSUBv2f64 |
| 69773307U, // FSUBv4f16 |
| 70297595U, // FSUBv4f32 |
| 2218305531U, // FSUBv8f16 |
| 2415937815U, // FTMAD_ZZI_D |
| 2388683031U, // FTMAD_ZZI_H |
| 2617280791U, // FTMAD_ZZI_S |
| 2415939708U, // FTSMUL_ZZZ_D |
| 2388684924U, // FTSMUL_ZZZ_H |
| 2617282684U, // FTSMUL_ZZZ_S |
| 2415939464U, // FTSSEL_ZZZ_D |
| 2388684680U, // FTSSEL_ZZZ_H |
| 2617282440U, // FTSSEL_ZZZ_S |
| 2293891964U, // GLD1B_D_IMM_REAL |
| 2696545148U, // GLD1B_D_REAL |
| 2696545148U, // GLD1B_D_SXTW_REAL |
| 2696545148U, // GLD1B_D_UXTW_REAL |
| 2327454588U, // GLD1B_S_IMM_REAL |
| 2696553340U, // GLD1B_S_SXTW_REAL |
| 2696553340U, // GLD1B_S_UXTW_REAL |
| 2293893306U, // GLD1D_IMM_REAL |
| 2696546490U, // GLD1D_REAL |
| 2696546490U, // GLD1D_SCALED_REAL |
| 2696546490U, // GLD1D_SXTW_REAL |
| 2696546490U, // GLD1D_SXTW_SCALED_REAL |
| 2696546490U, // GLD1D_UXTW_REAL |
| 2696546490U, // GLD1D_UXTW_SCALED_REAL |
| 2293893877U, // GLD1H_D_IMM_REAL |
| 2696547061U, // GLD1H_D_REAL |
| 2696547061U, // GLD1H_D_SCALED_REAL |
| 2696547061U, // GLD1H_D_SXTW_REAL |
| 2696547061U, // GLD1H_D_SXTW_SCALED_REAL |
| 2696547061U, // GLD1H_D_UXTW_REAL |
| 2696547061U, // GLD1H_D_UXTW_SCALED_REAL |
| 2327456501U, // GLD1H_S_IMM_REAL |
| 2696555253U, // GLD1H_S_SXTW_REAL |
| 2696555253U, // GLD1H_S_SXTW_SCALED_REAL |
| 2696555253U, // GLD1H_S_UXTW_REAL |
| 2696555253U, // GLD1H_S_UXTW_SCALED_REAL |
| 2293892956U, // GLD1SB_D_IMM_REAL |
| 2696546140U, // GLD1SB_D_REAL |
| 2696546140U, // GLD1SB_D_SXTW_REAL |
| 2696546140U, // GLD1SB_D_UXTW_REAL |
| 2327455580U, // GLD1SB_S_IMM_REAL |
| 2696554332U, // GLD1SB_S_SXTW_REAL |
| 2696554332U, // GLD1SB_S_UXTW_REAL |
| 2293894560U, // GLD1SH_D_IMM_REAL |
| 2696547744U, // GLD1SH_D_REAL |
| 2696547744U, // GLD1SH_D_SCALED_REAL |
| 2696547744U, // GLD1SH_D_SXTW_REAL |
| 2696547744U, // GLD1SH_D_SXTW_SCALED_REAL |
| 2696547744U, // GLD1SH_D_UXTW_REAL |
| 2696547744U, // GLD1SH_D_UXTW_SCALED_REAL |
| 2327457184U, // GLD1SH_S_IMM_REAL |
| 2696555936U, // GLD1SH_S_SXTW_REAL |
| 2696555936U, // GLD1SH_S_SXTW_SCALED_REAL |
| 2696555936U, // GLD1SH_S_UXTW_REAL |
| 2696555936U, // GLD1SH_S_UXTW_SCALED_REAL |
| 2293897560U, // GLD1SW_D_IMM_REAL |
| 2696550744U, // GLD1SW_D_REAL |
| 2696550744U, // GLD1SW_D_SCALED_REAL |
| 2696550744U, // GLD1SW_D_SXTW_REAL |
| 2696550744U, // GLD1SW_D_SXTW_SCALED_REAL |
| 2696550744U, // GLD1SW_D_UXTW_REAL |
| 2696550744U, // GLD1SW_D_UXTW_SCALED_REAL |
| 2293897373U, // GLD1W_D_IMM_REAL |
| 2696550557U, // GLD1W_D_REAL |
| 2696550557U, // GLD1W_D_SCALED_REAL |
| 2696550557U, // GLD1W_D_SXTW_REAL |
| 2696550557U, // GLD1W_D_SXTW_SCALED_REAL |
| 2696550557U, // GLD1W_D_UXTW_REAL |
| 2696550557U, // GLD1W_D_UXTW_SCALED_REAL |
| 2327459997U, // GLD1W_IMM_REAL |
| 2696558749U, // GLD1W_SXTW_REAL |
| 2696558749U, // GLD1W_SXTW_SCALED_REAL |
| 2696558749U, // GLD1W_UXTW_REAL |
| 2696558749U, // GLD1W_UXTW_SCALED_REAL |
| 2293891970U, // GLDFF1B_D_IMM_REAL |
| 2696545154U, // GLDFF1B_D_REAL |
| 2696545154U, // GLDFF1B_D_SXTW_REAL |
| 2696545154U, // GLDFF1B_D_UXTW_REAL |
| 2327454594U, // GLDFF1B_S_IMM_REAL |
| 2696553346U, // GLDFF1B_S_SXTW_REAL |
| 2696553346U, // GLDFF1B_S_UXTW_REAL |
| 2293893312U, // GLDFF1D_IMM_REAL |
| 2696546496U, // GLDFF1D_REAL |
| 2696546496U, // GLDFF1D_SCALED_REAL |
| 2696546496U, // GLDFF1D_SXTW_REAL |
| 2696546496U, // GLDFF1D_SXTW_SCALED_REAL |
| 2696546496U, // GLDFF1D_UXTW_REAL |
| 2696546496U, // GLDFF1D_UXTW_SCALED_REAL |
| 2293893883U, // GLDFF1H_D_IMM_REAL |
| 2696547067U, // GLDFF1H_D_REAL |
| 2696547067U, // GLDFF1H_D_SCALED_REAL |
| 2696547067U, // GLDFF1H_D_SXTW_REAL |
| 2696547067U, // GLDFF1H_D_SXTW_SCALED_REAL |
| 2696547067U, // GLDFF1H_D_UXTW_REAL |
| 2696547067U, // GLDFF1H_D_UXTW_SCALED_REAL |
| 2327456507U, // GLDFF1H_S_IMM_REAL |
| 2696555259U, // GLDFF1H_S_SXTW_REAL |
| 2696555259U, // GLDFF1H_S_SXTW_SCALED_REAL |
| 2696555259U, // GLDFF1H_S_UXTW_REAL |
| 2696555259U, // GLDFF1H_S_UXTW_SCALED_REAL |
| 2293892963U, // GLDFF1SB_D_IMM_REAL |
| 2696546147U, // GLDFF1SB_D_REAL |
| 2696546147U, // GLDFF1SB_D_SXTW_REAL |
| 2696546147U, // GLDFF1SB_D_UXTW_REAL |
| 2327455587U, // GLDFF1SB_S_IMM_REAL |
| 2696554339U, // GLDFF1SB_S_SXTW_REAL |
| 2696554339U, // GLDFF1SB_S_UXTW_REAL |
| 2293894567U, // GLDFF1SH_D_IMM_REAL |
| 2696547751U, // GLDFF1SH_D_REAL |
| 2696547751U, // GLDFF1SH_D_SCALED_REAL |
| 2696547751U, // GLDFF1SH_D_SXTW_REAL |
| 2696547751U, // GLDFF1SH_D_SXTW_SCALED_REAL |
| 2696547751U, // GLDFF1SH_D_UXTW_REAL |
| 2696547751U, // GLDFF1SH_D_UXTW_SCALED_REAL |
| 2327457191U, // GLDFF1SH_S_IMM_REAL |
| 2696555943U, // GLDFF1SH_S_SXTW_REAL |
| 2696555943U, // GLDFF1SH_S_SXTW_SCALED_REAL |
| 2696555943U, // GLDFF1SH_S_UXTW_REAL |
| 2696555943U, // GLDFF1SH_S_UXTW_SCALED_REAL |
| 2293897567U, // GLDFF1SW_D_IMM_REAL |
| 2696550751U, // GLDFF1SW_D_REAL |
| 2696550751U, // GLDFF1SW_D_SCALED_REAL |
| 2696550751U, // GLDFF1SW_D_SXTW_REAL |
| 2696550751U, // GLDFF1SW_D_SXTW_SCALED_REAL |
| 2696550751U, // GLDFF1SW_D_UXTW_REAL |
| 2696550751U, // GLDFF1SW_D_UXTW_SCALED_REAL |
| 2293897379U, // GLDFF1W_D_IMM_REAL |
| 2696550563U, // GLDFF1W_D_REAL |
| 2696550563U, // GLDFF1W_D_SCALED_REAL |
| 2696550563U, // GLDFF1W_D_SXTW_REAL |
| 2696550563U, // GLDFF1W_D_SXTW_SCALED_REAL |
| 2696550563U, // GLDFF1W_D_UXTW_REAL |
| 2696550563U, // GLDFF1W_D_UXTW_SCALED_REAL |
| 2327460003U, // GLDFF1W_IMM_REAL |
| 2696558755U, // GLDFF1W_SXTW_REAL |
| 2696558755U, // GLDFF1W_SXTW_SCALED_REAL |
| 2696558755U, // GLDFF1W_UXTW_REAL |
| 2696558755U, // GLDFF1W_UXTW_SCALED_REAL |
| 2248199786U, // GMI |
| 153326U, // HINT |
| 2516604627U, // HISTCNT_ZPzZZ_D |
| 2516621011U, // HISTCNT_ZPzZZ_S |
| 2583702229U, // HISTSEG_ZZZ |
| 79460U, // HLT |
| 75952U, // HVC |
| 0U, // HWASAN_CHECK_MEMACCESS |
| 0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES |
| 805356655U, // INCB_XPiI |
| 805357897U, // INCD_XPiI |
| 805325129U, // INCD_ZPiI |
| 805358569U, // INCH_XPiI |
| 8416233U, // INCH_ZPiI |
| 436261367U, // INCP_XP_B |
| 268489207U, // INCP_XP_D |
| 201380343U, // INCP_XP_H |
| 469815799U, // INCP_XP_S |
| 134238711U, // INCP_ZP_D |
| 846754295U, // INCP_ZP_H |
| 167809527U, // INCP_ZP_S |
| 805361950U, // INCW_XPiI |
| 805345566U, // INCW_ZPiI |
| 2248161800U, // INDEX_II_B |
| 2248169992U, // INDEX_II_D |
| 2391833096U, // INDEX_II_H |
| 2248186376U, // INDEX_II_S |
| 2248161800U, // INDEX_IR_B |
| 2248169992U, // INDEX_IR_D |
| 2391833096U, // INDEX_IR_H |
| 2248186376U, // INDEX_IR_S |
| 2248161800U, // INDEX_RI_B |
| 2248169992U, // INDEX_RI_D |
| 2391833096U, // INDEX_RI_H |
| 2248186376U, // INDEX_RI_S |
| 2248161800U, // INDEX_RR_B |
| 2248169992U, // INDEX_RR_D |
| 2391833096U, // INDEX_RR_H |
| 2248186376U, // INDEX_RR_S |
| 536884223U, // INSR_ZR_B |
| 536892415U, // INSR_ZR_D |
| 851473407U, // INSR_ZR_H |
| 536908799U, // INSR_ZR_S |
| 536884223U, // INSR_ZV_B |
| 536892415U, // INSR_ZV_D |
| 851473407U, // INSR_ZV_H |
| 536908799U, // INSR_ZV_S |
| 784921876U, // INSvi16gpr |
| 1221129492U, // INSvi16lane |
| 785446164U, // INSvi32gpr |
| 3369137428U, // INSvi32lane |
| 783349012U, // INSvi64gpr |
| 1219556628U, // INSvi64lane |
| 785970452U, // INSvi8gpr |
| 3369661716U, // INSvi8lane |
| 2248198878U, // IRG |
| 0U, // IRGstack |
| 116617U, // ISB |
| 0U, // JumpTableDest16 |
| 0U, // JumpTableDest32 |
| 0U, // JumpTableDest8 |
| 2516632387U, // LASTA_RPZ_B |
| 2516632387U, // LASTA_RPZ_D |
| 2516632387U, // LASTA_RPZ_H |
| 2516632387U, // LASTA_RPZ_S |
| 2516632387U, // LASTA_VPZ_B |
| 2516632387U, // LASTA_VPZ_D |
| 2516632387U, // LASTA_VPZ_H |
| 2516632387U, // LASTA_VPZ_S |
| 2516633576U, // LASTB_RPZ_B |
| 2516633576U, // LASTB_RPZ_D |
| 2516633576U, // LASTB_RPZ_H |
| 2516633576U, // LASTB_RPZ_S |
| 2516633576U, // LASTB_VPZ_B |
| 2516633576U, // LASTB_VPZ_D |
| 2516633576U, // LASTB_VPZ_H |
| 2516633576U, // LASTB_VPZ_S |
| 2696569724U, // LD1B |
| 2696545148U, // LD1B_D |
| 2696545148U, // LD1B_D_IMM |
| 2696577916U, // LD1B_H |
| 2696577916U, // LD1B_H_IMM |
| 2696569724U, // LD1B_IMM |
| 2696553340U, // LD1B_S |
| 2696553340U, // LD1B_S_IMM |
| 2696546490U, // LD1D |
| 2696546490U, // LD1D_IMM |
| 172064U, // LD1Fourv16b |
| 14860320U, // LD1Fourv16b_POST |
| 188448U, // LD1Fourv1d |
| 15400992U, // LD1Fourv1d_POST |
| 204832U, // LD1Fourv2d |
| 14893088U, // LD1Fourv2d_POST |
| 221216U, // LD1Fourv2s |
| 15433760U, // LD1Fourv2s_POST |
| 237600U, // LD1Fourv4h |
| 15450144U, // LD1Fourv4h_POST |
| 253984U, // LD1Fourv4s |
| 14942240U, // LD1Fourv4s_POST |
| 270368U, // LD1Fourv8b |
| 15482912U, // LD1Fourv8b_POST |
| 286752U, // LD1Fourv8h |
| 14975008U, // LD1Fourv8h_POST |
| 2696579829U, // LD1H |
| 2696547061U, // LD1H_D |
| 2696547061U, // LD1H_D_IMM |
| 2696579829U, // LD1H_IMM |
| 2696555253U, // LD1H_S |
| 2696555253U, // LD1H_S_IMM |
| 172064U, // LD1Onev16b |
| 15908896U, // LD1Onev16b_POST |
| 188448U, // LD1Onev1d |
| 16449568U, // LD1Onev1d_POST |
| 204832U, // LD1Onev2d |
| 15941664U, // LD1Onev2d_POST |
| 221216U, // LD1Onev2s |
| 16482336U, // LD1Onev2s_POST |
| 237600U, // LD1Onev4h |
| 16498720U, // LD1Onev4h_POST |
| 253984U, // LD1Onev4s |
| 15990816U, // LD1Onev4s_POST |
| 270368U, // LD1Onev8b |
| 16531488U, // LD1Onev8b_POST |
| 286752U, // LD1Onev8h |
| 16023584U, // LD1Onev8h_POST |
| 2696545992U, // LD1RB_D_IMM |
| 2696578760U, // LD1RB_H_IMM |
| 2696570568U, // LD1RB_IMM |
| 2696554184U, // LD1RB_S_IMM |
| 2696546756U, // LD1RD_IMM |
| 2696547596U, // LD1RH_D_IMM |
| 2696580364U, // LD1RH_IMM |
| 2696555788U, // LD1RH_S_IMM |
| 2696570560U, // LD1RQ_B |
| 2696570560U, // LD1RQ_B_IMM |
| 2696546748U, // LD1RQ_D |
| 2696546748U, // LD1RQ_D_IMM |
| 2696580356U, // LD1RQ_H |
| 2696580356U, // LD1RQ_H_IMM |
| 2696558912U, // LD1RQ_W |
| 2696558912U, // LD1RQ_W_IMM |
| 2696546203U, // LD1RSB_D_IMM |
| 2696578971U, // LD1RSB_H_IMM |
| 2696554395U, // LD1RSB_S_IMM |
| 2696547794U, // LD1RSH_D_IMM |
| 2696555986U, // LD1RSH_S_IMM |
| 2696550785U, // LD1RSW_IMM |
| 2696550728U, // LD1RW_D_IMM |
| 2696558920U, // LD1RW_IMM |
| 176883U, // LD1Rv16b |
| 16962291U, // LD1Rv16b_POST |
| 193267U, // LD1Rv1d |
| 16454387U, // LD1Rv1d_POST |
| 209651U, // LD1Rv2d |
| 16470771U, // LD1Rv2d_POST |
| 226035U, // LD1Rv2s |
| 17535731U, // LD1Rv2s_POST |
| 242419U, // LD1Rv4h |
| 18076403U, // LD1Rv4h_POST |
| 258803U, // LD1Rv4s |
| 17568499U, // LD1Rv4s_POST |
| 275187U, // LD1Rv8b |
| 17060595U, // LD1Rv8b_POST |
| 291571U, // LD1Rv8h |
| 18125555U, // LD1Rv8h_POST |
| 2696546140U, // LD1SB_D |
| 2696546140U, // LD1SB_D_IMM |
| 2696578908U, // LD1SB_H |
| 2696578908U, // LD1SB_H_IMM |
| 2696554332U, // LD1SB_S |
| 2696554332U, // LD1SB_S_IMM |
| 2696547744U, // LD1SH_D |
| 2696547744U, // LD1SH_D_IMM |
| 2696555936U, // LD1SH_S |
| 2696555936U, // LD1SH_S_IMM |
| 2696550744U, // LD1SW_D |
| 2696550744U, // LD1SW_D_IMM |
| 172064U, // LD1Threev16b |
| 18530336U, // LD1Threev16b_POST |
| 188448U, // LD1Threev1d |
| 19071008U, // LD1Threev1d_POST |
| 204832U, // LD1Threev2d |
| 18563104U, // LD1Threev2d_POST |
| 221216U, // LD1Threev2s |
| 19103776U, // LD1Threev2s_POST |
| 237600U, // LD1Threev4h |
| 19120160U, // LD1Threev4h_POST |
| 253984U, // LD1Threev4s |
| 18612256U, // LD1Threev4s_POST |
| 270368U, // LD1Threev8b |
| 19152928U, // LD1Threev8b_POST |
| 286752U, // LD1Threev8h |
| 18645024U, // LD1Threev8h_POST |
| 172064U, // LD1Twov16b |
| 15384608U, // LD1Twov16b_POST |
| 188448U, // LD1Twov1d |
| 15925280U, // LD1Twov1d_POST |
| 204832U, // LD1Twov2d |
| 15417376U, // LD1Twov2d_POST |
| 221216U, // LD1Twov2s |
| 15958048U, // LD1Twov2s_POST |
| 237600U, // LD1Twov4h |
| 15974432U, // LD1Twov4h_POST |
| 253984U, // LD1Twov4s |
| 15466528U, // LD1Twov4s_POST |
| 270368U, // LD1Twov8b |
| 16007200U, // LD1Twov8b_POST |
| 286752U, // LD1Twov8h |
| 15499296U, // LD1Twov8h_POST |
| 2696558749U, // LD1W |
| 2696550557U, // LD1W_D |
| 2696550557U, // LD1W_D_IMM |
| 2696558749U, // LD1W_IMM |
| 19701792U, // LD1i16 |
| 20234272U, // LD1i16_POST |
| 19718176U, // LD1i32 |
| 20774944U, // LD1i32_POST |
| 19734560U, // LD1i64 |
| 21315616U, // LD1i64_POST |
| 19750944U, // LD1i8 |
| 21856288U, // LD1i8_POST |
| 2696569785U, // LD2B |
| 2696569785U, // LD2B_IMM |
| 2696546534U, // LD2D |
| 2696546534U, // LD2D_IMM |
| 2696579890U, // LD2H |
| 2696579890U, // LD2H_IMM |
| 176889U, // LD2Rv16b |
| 18010873U, // LD2Rv16b_POST |
| 193273U, // LD2Rv1d |
| 15930105U, // LD2Rv1d_POST |
| 209657U, // LD2Rv2d |
| 15946489U, // LD2Rv2d_POST |
| 226041U, // LD2Rv2s |
| 16487161U, // LD2Rv2s_POST |
| 242425U, // LD2Rv4h |
| 17552121U, // LD2Rv4h_POST |
| 258809U, // LD2Rv4s |
| 16519929U, // LD2Rv4s_POST |
| 275193U, // LD2Rv8b |
| 18109177U, // LD2Rv8b_POST |
| 291577U, // LD2Rv8h |
| 17601273U, // LD2Rv8h_POST |
| 172162U, // LD2Twov16b |
| 15384706U, // LD2Twov16b_POST |
| 204930U, // LD2Twov2d |
| 15417474U, // LD2Twov2d_POST |
| 221314U, // LD2Twov2s |
| 15958146U, // LD2Twov2s_POST |
| 237698U, // LD2Twov4h |
| 15974530U, // LD2Twov4h_POST |
| 254082U, // LD2Twov4s |
| 15466626U, // LD2Twov4s_POST |
| 270466U, // LD2Twov8b |
| 16007298U, // LD2Twov8b_POST |
| 286850U, // LD2Twov8h |
| 15499394U, // LD2Twov8h_POST |
| 2696558801U, // LD2W |
| 2696558801U, // LD2W_IMM |
| 19701890U, // LD2i16 |
| 20758658U, // LD2i16_POST |
| 19718274U, // LD2i32 |
| 21299330U, // LD2i32_POST |
| 19734658U, // LD2i64 |
| 22364290U, // LD2i64_POST |
| 19751042U, // LD2i8 |
| 20283522U, // LD2i8_POST |
| 2696569806U, // LD3B |
| 2696569806U, // LD3B_IMM |
| 2696546546U, // LD3D |
| 2696546546U, // LD3D_IMM |
| 2696579902U, // LD3H |
| 2696579902U, // LD3H_IMM |
| 176895U, // LD3Rv16b |
| 22729471U, // LD3Rv16b_POST |
| 193279U, // LD3Rv1d |
| 19075839U, // LD3Rv1d_POST |
| 209663U, // LD3Rv2d |
| 19092223U, // LD3Rv2d_POST |
| 226047U, // LD3Rv2s |
| 23302911U, // LD3Rv2s_POST |
| 242431U, // LD3Rv4h |
| 23843583U, // LD3Rv4h_POST |
| 258815U, // LD3Rv4s |
| 23335679U, // LD3Rv4s_POST |
| 275199U, // LD3Rv8b |
| 22827775U, // LD3Rv8b_POST |
| 291583U, // LD3Rv8h |
| 23892735U, // LD3Rv8h_POST |
| 172569U, // LD3Threev16b |
| 18530841U, // LD3Threev16b_POST |
| 205337U, // LD3Threev2d |
| 18563609U, // LD3Threev2d_POST |
| 221721U, // LD3Threev2s |
| 19104281U, // LD3Threev2s_POST |
| 238105U, // LD3Threev4h |
| 19120665U, // LD3Threev4h_POST |
| 254489U, // LD3Threev4s |
| 18612761U, // LD3Threev4s_POST |
| 270873U, // LD3Threev8b |
| 19153433U, // LD3Threev8b_POST |
| 287257U, // LD3Threev8h |
| 18645529U, // LD3Threev8h_POST |
| 2696558813U, // LD3W |
| 2696558813U, // LD3W_IMM |
| 19702297U, // LD3i16 |
| 24429081U, // LD3i16_POST |
| 19718681U, // LD3i32 |
| 24969753U, // LD3i32_POST |
| 19735065U, // LD3i64 |
| 25510425U, // LD3i64_POST |
| 19751449U, // LD3i8 |
| 26051097U, // LD3i8_POST |
| 2696569818U, // LD4B |
| 2696569818U, // LD4B_IMM |
| 2696546558U, // LD4D |
| 2696546558U, // LD4D_IMM |
| 172599U, // LD4Fourv16b |
| 14860855U, // LD4Fourv16b_POST |
| 205367U, // LD4Fourv2d |
| 14893623U, // LD4Fourv2d_POST |
| 221751U, // LD4Fourv2s |
| 15434295U, // LD4Fourv2s_POST |
| 238135U, // LD4Fourv4h |
| 15450679U, // LD4Fourv4h_POST |
| 254519U, // LD4Fourv4s |
| 14942775U, // LD4Fourv4s_POST |
| 270903U, // LD4Fourv8b |
| 15483447U, // LD4Fourv8b_POST |
| 287287U, // LD4Fourv8h |
| 14975543U, // LD4Fourv8h_POST |
| 2696579914U, // LD4H |
| 2696579914U, // LD4H_IMM |
| 176901U, // LD4Rv16b |
| 17486597U, // LD4Rv16b_POST |
| 193285U, // LD4Rv1d |
| 15405829U, // LD4Rv1d_POST |
| 209669U, // LD4Rv2d |
| 15422213U, // LD4Rv2d_POST |
| 226053U, // LD4Rv2s |
| 15962885U, // LD4Rv2s_POST |
| 242437U, // LD4Rv4h |
| 16503557U, // LD4Rv4h_POST |
| 258821U, // LD4Rv4s |
| 15995653U, // LD4Rv4s_POST |
| 275205U, // LD4Rv8b |
| 17584901U, // LD4Rv8b_POST |
| 291589U, // LD4Rv8h |
| 16552709U, // LD4Rv8h_POST |
| 2696558825U, // LD4W |
| 2696558825U, // LD4W_IMM |
| 19702327U, // LD4i16 |
| 21283383U, // LD4i16_POST |
| 19718711U, // LD4i32 |
| 22348343U, // LD4i32_POST |
| 19735095U, // LD4i64 |
| 26559031U, // LD4i64_POST |
| 19751479U, // LD4i8 |
| 20808247U, // LD4i8_POST |
| 1241605094U, // LDADDAB |
| 1241607007U, // LDADDAH |
| 1241605316U, // LDADDALB |
| 1241607181U, // LDADDALH |
| 1241607841U, // LDADDALW |
| 1241607841U, // LDADDALX |
| 1241604752U, // LDADDAW |
| 1241604752U, // LDADDAX |
| 1241605252U, // LDADDB |
| 1241607167U, // LDADDH |
| 1241605496U, // LDADDLB |
| 1241607281U, // LDADDLH |
| 1241608018U, // LDADDLW |
| 1241608018U, // LDADDLX |
| 1241606502U, // LDADDW |
| 1241606502U, // LDADDX |
| 2255013635U, // LDAPRB |
| 2255015239U, // LDAPRH |
| 2255016920U, // LDAPRW |
| 2255016920U, // LDAPRX |
| 2255013678U, // LDAPURBi |
| 2255015282U, // LDAPURHi |
| 2255013818U, // LDAPURSBWi |
| 2255013818U, // LDAPURSBXi |
| 2255015409U, // LDAPURSHWi |
| 2255015409U, // LDAPURSHXi |
| 2255018400U, // LDAPURSWi |
| 2255017001U, // LDAPURXi |
| 2255017001U, // LDAPURi |
| 2255013583U, // LDARB |
| 2255015187U, // LDARH |
| 2255016715U, // LDARW |
| 2255016715U, // LDARX |
| 100717229U, // LDAXPW |
| 100717229U, // LDAXPX |
| 2255013694U, // LDAXRB |
| 2255015298U, // LDAXRH |
| 2255017045U, // LDAXRW |
| 2255017045U, // LDAXRX |
| 1241605150U, // LDCLRAB |
| 1241607064U, // LDCLRAH |
| 1241605390U, // LDCLRALB |
| 1241607221U, // LDCLRALH |
| 1241607915U, // LDCLRALW |
| 1241607915U, // LDCLRALX |
| 1241604866U, // LDCLRAW |
| 1241604866U, // LDCLRAX |
| 1241605860U, // LDCLRB |
| 1241607464U, // LDCLRH |
| 1241605598U, // LDCLRLB |
| 1241607317U, // LDCLRLH |
| 1241608218U, // LDCLRLW |
| 1241608218U, // LDCLRLX |
| 1241609083U, // LDCLRW |
| 1241609083U, // LDCLRX |
| 1241605159U, // LDEORAB |
| 1241607073U, // LDEORAH |
| 1241605400U, // LDEORALB |
| 1241607231U, // LDEORALH |
| 1241607924U, // LDEORALW |
| 1241607924U, // LDEORALX |
| 1241604874U, // LDEORAW |
| 1241604874U, // LDEORAX |
| 1241605883U, // LDEORB |
| 1241607487U, // LDEORH |
| 1241605607U, // LDEORLB |
| 1241607326U, // LDEORLH |
| 1241608226U, // LDEORLW |
| 1241608226U, // LDEORLX |
| 1241609159U, // LDEORW |
| 1241609159U, // LDEORX |
| 2696545154U, // LDFF1B_D_REAL |
| 2696577922U, // LDFF1B_H_REAL |
| 2696569730U, // LDFF1B_REAL |
| 2696553346U, // LDFF1B_S_REAL |
| 2696546496U, // LDFF1D_REAL |
| 2696547067U, // LDFF1H_D_REAL |
| 2696579835U, // LDFF1H_REAL |
| 2696555259U, // LDFF1H_S_REAL |
| 2696546147U, // LDFF1SB_D_REAL |
| 2696578915U, // LDFF1SB_H_REAL |
| 2696554339U, // LDFF1SB_S_REAL |
| 2696547751U, // LDFF1SH_D_REAL |
| 2696555943U, // LDFF1SH_S_REAL |
| 2696550751U, // LDFF1SW_D_REAL |
| 2696550563U, // LDFF1W_D_REAL |
| 2696558755U, // LDFF1W_REAL |
| 2691263164U, // LDG |
| 2255016124U, // LDGM |
| 2255013590U, // LDLARB |
| 2255015194U, // LDLARH |
| 2255016721U, // LDLARW |
| 2255016721U, // LDLARX |
| 2696545162U, // LDNF1B_D_IMM |
| 2696577930U, // LDNF1B_H_IMM |
| 2696569738U, // LDNF1B_IMM |
| 2696553354U, // LDNF1B_S_IMM |
| 2696546504U, // LDNF1D_IMM |
| 2696547075U, // LDNF1H_D_IMM |
| 2696579843U, // LDNF1H_IMM |
| 2696555267U, // LDNF1H_S_IMM |
| 2696546156U, // LDNF1SB_D_IMM |
| 2696578924U, // LDNF1SB_H_IMM |
| 2696554348U, // LDNF1SB_S_IMM |
| 2696547760U, // LDNF1SH_D_IMM |
| 2696555952U, // LDNF1SH_S_IMM |
| 2696550760U, // LDNF1SW_D_IMM |
| 2696550571U, // LDNF1W_D_IMM |
| 2696558763U, // LDNF1W_IMM |
| 100717148U, // LDNPDi |
| 100717148U, // LDNPQi |
| 100717148U, // LDNPSi |
| 100717148U, // LDNPWi |
| 100717148U, // LDNPXi |
| 2696569746U, // LDNT1B_ZRI |
| 2696569746U, // LDNT1B_ZRR |
| 2293891986U, // LDNT1B_ZZR_D_REAL |
| 2327454610U, // LDNT1B_ZZR_S_REAL |
| 2696546512U, // LDNT1D_ZRI |
| 2696546512U, // LDNT1D_ZRR |
| 2293893328U, // LDNT1D_ZZR_D_REAL |
| 2696579851U, // LDNT1H_ZRI |
| 2696579851U, // LDNT1H_ZRR |
| 2293893899U, // LDNT1H_ZZR_D_REAL |
| 2327456523U, // LDNT1H_ZZR_S_REAL |
| 2293892981U, // LDNT1SB_ZZR_D_REAL |
| 2327455605U, // LDNT1SB_ZZR_S_REAL |
| 2293894585U, // LDNT1SH_ZZR_D_REAL |
| 2327457209U, // LDNT1SH_ZZR_S_REAL |
| 2293897585U, // LDNT1SW_ZZR_D_REAL |
| 2696558771U, // LDNT1W_ZRI |
| 2696558771U, // LDNT1W_ZRR |
| 2293897395U, // LDNT1W_ZZR_D_REAL |
| 2327460019U, // LDNT1W_ZZR_S_REAL |
| 100717068U, // LDPDi |
| 536965644U, // LDPDpost |
| 536965644U, // LDPDpre |
| 100717068U, // LDPQi |
| 536965644U, // LDPQpost |
| 536965644U, // LDPQpre |
| 100718970U, // LDPSWi |
| 536967546U, // LDPSWpost |
| 536967546U, // LDPSWpre |
| 100717068U, // LDPSi |
| 536965644U, // LDPSpost |
| 536965644U, // LDPSpre |
| 100717068U, // LDPWi |
| 536965644U, // LDPWpost |
| 536965644U, // LDPWpre |
| 100717068U, // LDPXi |
| 536965644U, // LDPXpost |
| 536965644U, // LDPXpre |
| 2255012463U, // LDRAAindexed |
| 2691261039U, // LDRAAwriteback |
| 2255012880U, // LDRABindexed |
| 2691261456U, // LDRABwriteback |
| 543778526U, // LDRBBpost |
| 2691262174U, // LDRBBpre |
| 2255013598U, // LDRBBroW |
| 2255013598U, // LDRBBroX |
| 2255013598U, // LDRBBui |
| 543781705U, // LDRBpost |
| 2691265353U, // LDRBpre |
| 2255016777U, // LDRBroW |
| 2255016777U, // LDRBroX |
| 2255016777U, // LDRBui |
| 604033865U, // LDRDl |
| 543781705U, // LDRDpost |
| 2691265353U, // LDRDpre |
| 2255016777U, // LDRDroW |
| 2255016777U, // LDRDroX |
| 2255016777U, // LDRDui |
| 543780130U, // LDRHHpost |
| 2691263778U, // LDRHHpre |
| 2255015202U, // LDRHHroW |
| 2255015202U, // LDRHHroX |
| 2255015202U, // LDRHHui |
| 543781705U, // LDRHpost |
| 2691265353U, // LDRHpre |
| 2255016777U, // LDRHroW |
| 2255016777U, // LDRHroX |
| 2255016777U, // LDRHui |
| 604033865U, // LDRQl |
| 543781705U, // LDRQpost |
| 2691265353U, // LDRQpre |
| 2255016777U, // LDRQroW |
| 2255016777U, // LDRQroX |
| 2255016777U, // LDRQui |
| 543778723U, // LDRSBWpost |
| 2691262371U, // LDRSBWpre |
| 2255013795U, // LDRSBWroW |
| 2255013795U, // LDRSBWroX |
| 2255013795U, // LDRSBWui |
| 543778723U, // LDRSBXpost |
| 2691262371U, // LDRSBXpre |
| 2255013795U, // LDRSBXroW |
| 2255013795U, // LDRSBXroX |
| 2255013795U, // LDRSBXui |
| 543780314U, // LDRSHWpost |
| 2691263962U, // LDRSHWpre |
| 2255015386U, // LDRSHWroW |
| 2255015386U, // LDRSHWroX |
| 2255015386U, // LDRSHWui |
| 543780314U, // LDRSHXpost |
| 2691263962U, // LDRSHXpre |
| 2255015386U, // LDRSHXroW |
| 2255015386U, // LDRSHXroX |
| 2255015386U, // LDRSHXui |
| 604035465U, // LDRSWl |
| 543783305U, // LDRSWpost |
| 2691266953U, // LDRSWpre |
| 2255018377U, // LDRSWroW |
| 2255018377U, // LDRSWroX |
| 2255018377U, // LDRSWui |
| 604033865U, // LDRSl |
| 543781705U, // LDRSpost |
| 2691265353U, // LDRSpre |
| 2255016777U, // LDRSroW |
| 2255016777U, // LDRSroX |
| 2255016777U, // LDRSui |
| 604033865U, // LDRWl |
| 543781705U, // LDRWpost |
| 2691265353U, // LDRWpre |
| 2255016777U, // LDRWroW |
| 2255016777U, // LDRWroX |
| 2255016777U, // LDRWui |
| 604033865U, // LDRXl |
| 543781705U, // LDRXpost |
| 2691265353U, // LDRXpre |
| 2255016777U, // LDRXroW |
| 2255016777U, // LDRXroX |
| 2255016777U, // LDRXui |
| 2255336265U, // LDR_PXI |
| 2255336265U, // LDR_ZXI |
| 1241605175U, // LDSETAB |
| 1241607089U, // LDSETAH |
| 1241605418U, // LDSETALB |
| 1241607249U, // LDSETALH |
| 1241607940U, // LDSETALW |
| 1241607940U, // LDSETALX |
| 1241604914U, // LDSETAW |
| 1241604914U, // LDSETAX |
| 1241606089U, // LDSETB |
| 1241607675U, // LDSETH |
| 1241605657U, // LDSETLB |
| 1241607342U, // LDSETLH |
| 1241608282U, // LDSETLW |
| 1241608282U, // LDSETLX |
| 1241609664U, // LDSETW |
| 1241609664U, // LDSETX |
| 1241605184U, // LDSMAXAB |
| 1241607098U, // LDSMAXAH |
| 1241605428U, // LDSMAXALB |
| 1241607259U, // LDSMAXALH |
| 1241607949U, // LDSMAXALW |
| 1241607949U, // LDSMAXALX |
| 1241604938U, // LDSMAXAW |
| 1241604938U, // LDSMAXAX |
| 1241606226U, // LDSMAXB |
| 1241607707U, // LDSMAXH |
| 1241605666U, // LDSMAXLB |
| 1241607384U, // LDSMAXLH |
| 1241608337U, // LDSMAXLW |
| 1241608337U, // LDSMAXLX |
| 1241610730U, // LDSMAXW |
| 1241610730U, // LDSMAXX |
| 1241605103U, // LDSMINAB |
| 1241607037U, // LDSMINAH |
| 1241605360U, // LDSMINALB |
| 1241607191U, // LDSMINALH |
| 1241607880U, // LDSMINALW |
| 1241607880U, // LDSMINALX |
| 1241604821U, // LDSMINAW |
| 1241604821U, // LDSMINAX |
| 1241605709U, // LDSMINB |
| 1241607404U, // LDSMINH |
| 1241605571U, // LDSMINLB |
| 1241607290U, // LDSMINLH |
| 1241608180U, // LDSMINLW |
| 1241608180U, // LDSMINLX |
| 1241608472U, // LDSMINW |
| 1241608472U, // LDSMINX |
| 2255013643U, // LDTRBi |
| 2255015247U, // LDTRHi |
| 2255013802U, // LDTRSBWi |
| 2255013802U, // LDTRSBXi |
| 2255015393U, // LDTRSHWi |
| 2255015393U, // LDTRSHXi |
| 2255018384U, // LDTRSWi |
| 2255016965U, // LDTRWi |
| 2255016965U, // LDTRXi |
| 1241605194U, // LDUMAXAB |
| 1241607108U, // LDUMAXAH |
| 1241605439U, // LDUMAXALB |
| 1241607270U, // LDUMAXALH |
| 1241607959U, // LDUMAXALW |
| 1241607959U, // LDUMAXALX |
| 1241604947U, // LDUMAXAW |
| 1241604947U, // LDUMAXAX |
| 1241606235U, // LDUMAXB |
| 1241607716U, // LDUMAXH |
| 1241605676U, // LDUMAXLB |
| 1241607394U, // LDUMAXLH |
| 1241608346U, // LDUMAXLW |
| 1241608346U, // LDUMAXLX |
| 1241610738U, // LDUMAXW |
| 1241610738U, // LDUMAXX |
| 1241605113U, // LDUMINAB |
| 1241607047U, // LDUMINAH |
| 1241605371U, // LDUMINALB |
| 1241607202U, // LDUMINALH |
| 1241607890U, // LDUMINALW |
| 1241607890U, // LDUMINALX |
| 1241604830U, // LDUMINAW |
| 1241604830U, // LDUMINAX |
| 1241605718U, // LDUMINB |
| 1241607413U, // LDUMINH |
| 1241605581U, // LDUMINLB |
| 1241607300U, // LDUMINLH |
| 1241608189U, // LDUMINLW |
| 1241608189U, // LDUMINLX |
| 1241608480U, // LDUMINW |
| 1241608480U, // LDUMINX |
| 2255013663U, // LDURBBi |
| 2255016988U, // LDURBi |
| 2255016988U, // LDURDi |
| 2255015267U, // LDURHHi |
| 2255016988U, // LDURHi |
| 2255016988U, // LDURQi |
| 2255013810U, // LDURSBWi |
| 2255013810U, // LDURSBXi |
| 2255015401U, // LDURSHWi |
| 2255015401U, // LDURSHXi |
| 2255018392U, // LDURSWi |
| 2255016988U, // LDURSi |
| 2255016988U, // LDURWi |
| 2255016988U, // LDURXi |
| 100717257U, // LDXPW |
| 100717257U, // LDXPX |
| 2255013702U, // LDXRB |
| 2255015306U, // LDXRH |
| 2255017052U, // LDXRW |
| 2255017052U, // LDXRX |
| 0U, // LOADgot |
| 369111995U, // LSLR_ZPmZ_B |
| 369120187U, // LSLR_ZPmZ_D |
| 2555933627U, // LSLR_ZPmZ_H |
| 369136571U, // LSLR_ZPmZ_S |
| 2248200250U, // LSLVWr |
| 2248200250U, // LSLVXr |
| 369111098U, // LSL_WIDE_ZPmZ_B |
| 2555932730U, // LSL_WIDE_ZPmZ_H |
| 369135674U, // LSL_WIDE_ZPmZ_S |
| 2583703610U, // LSL_WIDE_ZZZ_B |
| 241201210U, // LSL_WIDE_ZZZ_H |
| 2617282618U, // LSL_WIDE_ZZZ_S |
| 369111098U, // LSL_ZPmI_B |
| 369119290U, // LSL_ZPmI_D |
| 2555932730U, // LSL_ZPmI_H |
| 369135674U, // LSL_ZPmI_S |
| 369111098U, // LSL_ZPmZ_B |
| 369119290U, // LSL_ZPmZ_D |
| 2555932730U, // LSL_ZPmZ_H |
| 369135674U, // LSL_ZPmZ_S |
| 2583703610U, // LSL_ZZI_B |
| 2415939642U, // LSL_ZZI_D |
| 2388684858U, // LSL_ZZI_H |
| 2617282618U, // LSL_ZZI_S |
| 369112042U, // LSRR_ZPmZ_B |
| 369120234U, // LSRR_ZPmZ_D |
| 2555933674U, // LSRR_ZPmZ_H |
| 369136618U, // LSRR_ZPmZ_S |
| 2248201205U, // LSRVWr |
| 2248201205U, // LSRVXr |
| 369112053U, // LSR_WIDE_ZPmZ_B |
| 2555933685U, // LSR_WIDE_ZPmZ_H |
| 369136629U, // LSR_WIDE_ZPmZ_S |
| 2583704565U, // LSR_WIDE_ZZZ_B |
| 241202165U, // LSR_WIDE_ZZZ_H |
| 2617283573U, // LSR_WIDE_ZZZ_S |
| 369112053U, // LSR_ZPmI_B |
| 369120245U, // LSR_ZPmI_D |
| 2555933685U, // LSR_ZPmI_H |
| 369136629U, // LSR_ZPmI_S |
| 369112053U, // LSR_ZPmZ_B |
| 369120245U, // LSR_ZPmZ_D |
| 2555933685U, // LSR_ZPmZ_H |
| 369136629U, // LSR_ZPmZ_S |
| 2583704565U, // LSR_ZZI_B |
| 2415940597U, // LSR_ZZI_D |
| 2388685813U, // LSR_ZZI_H |
| 2617283573U, // LSR_ZZI_S |
| 2248198546U, // MADDWrrr |
| 2248198546U, // MADDXrrr |
| 369109259U, // MAD_ZPmZZ_B |
| 369117451U, // MAD_ZPmZZ_D |
| 2555930891U, // MAD_ZPmZZ_H |
| 369133835U, // MAD_ZPmZZ_S |
| 2516593656U, // MATCH_PPzZZ_B |
| 2824367096U, // MATCH_PPzZZ_H |
| 369107651U, // MLA_ZPmZZ_B |
| 369115843U, // MLA_ZPmZZ_D |
| 2555929283U, // MLA_ZPmZZ_H |
| 369132227U, // MLA_ZPmZZ_S |
| 2281718467U, // MLA_ZZZI_D |
| 2390254275U, // MLA_ZZZI_H |
| 2315289283U, // MLA_ZZZI_S |
| 336650947U, // MLAv16i8 |
| 2484658883U, // MLAv2i32 |
| 2484658883U, // MLAv2i32_indexed |
| 338223811U, // MLAv4i16 |
| 338223811U, // MLAv4i16_indexed |
| 338748099U, // MLAv4i32 |
| 338748099U, // MLAv4i32_indexed |
| 2486756035U, // MLAv8i16 |
| 2486756035U, // MLAv8i16_indexed |
| 2487280323U, // MLAv8i8 |
| 369112313U, // MLS_ZPmZZ_B |
| 369120505U, // MLS_ZPmZZ_D |
| 2555933945U, // MLS_ZPmZZ_H |
| 369136889U, // MLS_ZPmZZ_S |
| 2281723129U, // MLS_ZZZI_D |
| 2390258937U, // MLS_ZZZI_H |
| 2315293945U, // MLS_ZZZI_S |
| 336655609U, // MLSv16i8 |
| 2484663545U, // MLSv2i32 |
| 2484663545U, // MLSv2i32_indexed |
| 338228473U, // MLSv4i16 |
| 338228473U, // MLSv4i16_indexed |
| 338752761U, // MLSv4i32 |
| 338752761U, // MLSv4i32_indexed |
| 2486760697U, // MLSv8i16 |
| 2486760697U, // MLSv8i16_indexed |
| 2487284985U, // MLSv8i8 |
| 1275121282U, // MOVID |
| 1309716098U, // MOVIv16b_ns |
| 1277210242U, // MOVIv2d_ns |
| 3457724034U, // MOVIv2i32 |
| 3457724034U, // MOVIv2s_msl |
| 3458772610U, // MOVIv4i16 |
| 3459296898U, // MOVIv4i32 |
| 3459296898U, // MOVIv4s_msl |
| 1312861826U, // MOVIv8b_ns |
| 3459821186U, // MOVIv8i16 |
| 570478221U, // MOVKWi |
| 570478221U, // MOVKXi |
| 0U, // MOVMCSym |
| 3456160152U, // MOVNWi |
| 3456160152U, // MOVNXi |
| 14870U, // MOVPRFX_ZPmZ_B |
| 2147506710U, // MOVPRFX_ZPmZ_D |
| 34109974U, // MOVPRFX_ZPmZ_H |
| 39446U, // MOVPRFX_ZPmZ_S |
| 2516597270U, // MOVPRFX_ZPzZ_B |
| 2516605462U, // MOVPRFX_ZPzZ_D |
| 2824370710U, // MOVPRFX_ZPzZ_H |
| 2516621846U, // MOVPRFX_ZPzZ_S |
| 369474070U, // MOVPRFX_ZZ |
| 3456162465U, // MOVZWi |
| 3456162465U, // MOVZXi |
| 0U, // MOVaddr |
| 0U, // MOVaddrBA |
| 0U, // MOVaddrCP |
| 0U, // MOVaddrEXT |
| 0U, // MOVaddrJT |
| 0U, // MOVaddrTLS |
| 0U, // MOVbaseTLS |
| 0U, // MOVi32imm |
| 0U, // MOVi64imm |
| 1342231885U, // MRS |
| 369108879U, // MSB_ZPmZZ_B |
| 369117071U, // MSB_ZPmZZ_D |
| 2555930511U, // MSB_ZPmZZ_H |
| 369133455U, // MSB_ZPmZZ_S |
| 381946U, // MSR |
| 390138U, // MSRpstateImm1 |
| 390138U, // MSRpstateImm4 |
| 2248198160U, // MSUBWrrr |
| 2248198160U, // MSUBXrrr |
| 2583703658U, // MUL_ZI_B |
| 2415939690U, // MUL_ZI_D |
| 2388684906U, // MUL_ZI_H |
| 2617282666U, // MUL_ZI_S |
| 369111146U, // MUL_ZPmZ_B |
| 369119338U, // MUL_ZPmZ_D |
| 2555932778U, // MUL_ZPmZ_H |
| 369135722U, // MUL_ZPmZ_S |
| 2415939690U, // MUL_ZZZI_D |
| 2388684906U, // MUL_ZZZI_H |
| 2617282666U, // MUL_ZZZI_S |
| 2583703658U, // MUL_ZZZ_B |
| 2415939690U, // MUL_ZZZ_D |
| 2388684906U, // MUL_ZZZ_H |
| 2617282666U, // MUL_ZZZ_S |
| 68202602U, // MULv16i8 |
| 2216210538U, // MULv2i32 |
| 2216210538U, // MULv2i32_indexed |
| 69775466U, // MULv4i16 |
| 69775466U, // MULv4i16_indexed |
| 70299754U, // MULv4i32 |
| 70299754U, // MULv4i32_indexed |
| 2218307690U, // MULv8i16 |
| 2218307690U, // MULv8i16_indexed |
| 2218831978U, // MULv8i8 |
| 3457724015U, // MVNIv2i32 |
| 3457724015U, // MVNIv2s_msl |
| 3458772591U, // MVNIv4i16 |
| 3459296879U, // MVNIv4i32 |
| 3459296879U, // MVNIv4s_msl |
| 3459821167U, // MVNIv8i16 |
| 2516595909U, // NANDS_PPzPP |
| 2516593078U, // NAND_PPzPP |
| 2415939632U, // NBSL_ZZZZ_D |
| 10946U, // NEG_ZPmZ_B |
| 2147502786U, // NEG_ZPmZ_D |
| 34106050U, // NEG_ZPmZ_H |
| 35522U, // NEG_ZPmZ_S |
| 2215684802U, // NEGv16i8 |
| 100715202U, // NEGv1i64 |
| 2216209090U, // NEGv2i32 |
| 69249730U, // NEGv2i64 |
| 2217257666U, // NEGv4i16 |
| 70298306U, // NEGv4i32 |
| 2218306242U, // NEGv8i16 |
| 71346882U, // NEGv8i8 |
| 2516593655U, // NMATCH_PPzZZ_B |
| 2824367095U, // NMATCH_PPzZZ_H |
| 2516596056U, // NORS_PPzPP |
| 2516595662U, // NOR_PPzPP |
| 14188U, // NOT_ZPmZ_B |
| 2147506028U, // NOT_ZPmZ_D |
| 34109292U, // NOT_ZPmZ_H |
| 38764U, // NOT_ZPmZ_S |
| 2215688044U, // NOTv16i8 |
| 71350124U, // NOTv8i8 |
| 2516596000U, // ORNS_PPzPP |
| 0U, // ORNWrr |
| 2248200539U, // ORNWrs |
| 0U, // ORNXrr |
| 2248200539U, // ORNXrs |
| 2516595035U, // ORN_PPzPP |
| 68202843U, // ORNv16i8 |
| 2218832219U, // ORNv8i8 |
| 2516596062U, // ORRS_PPzPP |
| 2248201183U, // ORRWri |
| 0U, // ORRWrr |
| 2248201183U, // ORRWrs |
| 2248201183U, // ORRXri |
| 0U, // ORRXrr |
| 2248201183U, // ORRXrs |
| 2516595679U, // ORR_PPzPP |
| 2415940575U, // ORR_ZI |
| 369112031U, // ORR_ZPmZ_B |
| 369120223U, // ORR_ZPmZ_D |
| 2555933663U, // ORR_ZPmZ_H |
| 369136607U, // ORR_ZPmZ_S |
| 2415940575U, // ORR_ZZZ |
| 68203487U, // ORRv16i8 |
| 572060639U, // ORRv2i32 |
| 573109215U, // ORRv4i16 |
| 573633503U, // ORRv4i32 |
| 574157791U, // ORRv8i16 |
| 2218832863U, // ORRv8i8 |
| 2516637827U, // ORV_VPZ_B |
| 2516637827U, // ORV_VPZ_D |
| 2516637827U, // ORV_VPZ_H |
| 2516637827U, // ORV_VPZ_S |
| 100713097U, // PACDA |
| 100713597U, // PACDB |
| 7390044U, // PACDZA |
| 7391332U, // PACDZB |
| 2248196774U, // PACGA |
| 100713133U, // PACIA |
| 7077U, // PACIA1716 |
| 7042U, // PACIASP |
| 7033U, // PACIAZ |
| 100713632U, // PACIB |
| 6988U, // PACIB1716 |
| 7068U, // PACIBSP |
| 7051U, // PACIBZ |
| 7390060U, // PACIZA |
| 7391348U, // PACIZB |
| 7350884U, // PFALSE |
| 2516596622U, // PFIRST_B |
| 2617263531U, // PMULLB_ZZZ_D |
| 261645739U, // PMULLB_ZZZ_H |
| 27387307U, // PMULLB_ZZZ_Q |
| 2617267843U, // PMULLT_ZZZ_D |
| 261650051U, // PMULLT_ZZZ_H |
| 27391619U, // PMULLT_ZZZ_Q |
| 70820119U, // PMULLv16i8 |
| 1403563999U, // PMULLv1i64 |
| 1437114647U, // PMULLv2i64 |
| 2218307551U, // PMULLv8i8 |
| 2583703670U, // PMUL_ZZZ_B |
| 68202614U, // PMULv16i8 |
| 2218831990U, // PMULv8i8 |
| 2516596681U, // PNEXT_B |
| 2516604873U, // PNEXT_D |
| 2388162505U, // PNEXT_H |
| 2516621257U, // PNEXT_S |
| 2947941523U, // PRFB_D_PZI |
| 2395341971U, // PRFB_D_SCALED |
| 247858323U, // PRFB_D_SXTW_SCALED |
| 2395341971U, // PRFB_D_UXTW_SCALED |
| 247858323U, // PRFB_PRI |
| 247858323U, // PRFB_PRR |
| 240518291U, // PRFB_S_PZI |
| 2395341971U, // PRFB_S_SXTW_SCALED |
| 247858323U, // PRFB_S_UXTW_SCALED |
| 1471547824U, // PRFD_D_PZI |
| 2395343280U, // PRFD_D_SCALED |
| 247859632U, // PRFD_D_SXTW_SCALED |
| 2395343280U, // PRFD_D_UXTW_SCALED |
| 247859632U, // PRFD_PRI |
| 247859632U, // PRFD_PRR |
| 2388003248U, // PRFD_S_PZI |
| 247859632U, // PRFD_S_SXTW_SCALED |
| 2395343280U, // PRFD_S_UXTW_SCALED |
| 1505102855U, // PRFH_D_PZI |
| 247860231U, // PRFH_D_SCALED |
| 2395343879U, // PRFH_D_SXTW_SCALED |
| 247860231U, // PRFH_D_UXTW_SCALED |
| 247860231U, // PRFH_PRI |
| 2395343879U, // PRFH_PRR |
| 240520199U, // PRFH_S_PZI |
| 2395343879U, // PRFH_S_SXTW_SCALED |
| 247860231U, // PRFH_S_UXTW_SCALED |
| 604385462U, // PRFMl |
| 2255368374U, // PRFMroW |
| 2255368374U, // PRFMroX |
| 2255368374U, // PRFMui |
| 2395347258U, // PRFS_PRR |
| 2255368429U, // PRFUMi |
| 1538660666U, // PRFW_D_PZI |
| 247863610U, // PRFW_D_SCALED |
| 2395347258U, // PRFW_D_SXTW_SCALED |
| 247863610U, // PRFW_D_UXTW_SCALED |
| 247863610U, // PRFW_PRI |
| 2388007226U, // PRFW_S_PZI |
| 247863610U, // PRFW_S_SXTW_SCALED |
| 2395347258U, // PRFW_S_UXTW_SCALED |
| 436582272U, // PTEST_PP |
| 704656588U, // PTRUES_B |
| 704664780U, // PTRUES_D |
| 28865740U, // PTRUES_H |
| 704681164U, // PTRUES_S |
| 704653950U, // PTRUE_B |
| 704662142U, // PTRUE_D |
| 28863102U, // PTRUE_H |
| 704678526U, // PTRUE_S |
| 865627709U, // PUNPKHI_PP |
| 865628591U, // PUNPKLO_PP |
| 2348820036U, // RADDHNB_ZZZ_B |
| 239625796U, // RADDHNB_ZZZ_H |
| 2415953476U, // RADDHNB_ZZZ_S |
| 2449487589U, // RADDHNT_ZZZ_B |
| 240154341U, // RADDHNT_ZZZ_H |
| 2281740005U, // RADDHNT_ZZZ_S |
| 2216210698U, // RADDHNv2i64_v2i32 |
| 2486231394U, // RADDHNv2i64_v4i32 |
| 69775626U, // RADDHNv4i32_v4i16 |
| 339272034U, // RADDHNv4i32_v8i16 |
| 2484134242U, // RADDHNv8i16_v16i8 |
| 2218832138U, // RADDHNv8i16_v8i8 |
| 2216730741U, // RAX1 |
| 2415935605U, // RAX1_ZZZ_D |
| 100718053U, // RBITWr |
| 100718053U, // RBITXr |
| 13797U, // RBIT_ZPmZ_B |
| 2147505637U, // RBIT_ZPmZ_D |
| 34108901U, // RBIT_ZPmZ_H |
| 38373U, // RBIT_ZPmZ_S |
| 2215687653U, // RBITv16i8 |
| 71349733U, // RBITv8i8 |
| 369112389U, // RDFFRS_PPz |
| 7353166U, // RDFFR_P |
| 369111886U, // RDFFR_PPz |
| 100716683U, // RDVLI_XI |
| 7394747U, // RET |
| 7159U, // RETAA |
| 7166U, // RETAB |
| 0U, // RET_ReallyLR |
| 100713033U, // REV16Wr |
| 100713033U, // REV16Xr |
| 2215682633U, // REV16v16i8 |
| 71344713U, // REV16v8i8 |
| 100712571U, // REV32Xr |
| 2215682171U, // REV32v16i8 |
| 2217255035U, // REV32v4i16 |
| 2218303611U, // REV32v8i16 |
| 71344251U, // REV32v8i8 |
| 2215682608U, // REV64v16i8 |
| 2216206896U, // REV64v2i32 |
| 2217255472U, // REV64v4i16 |
| 70296112U, // REV64v4i32 |
| 2218304048U, // REV64v8i16 |
| 71344688U, // REV64v8i8 |
| 2147502124U, // REVB_ZPmZ_D |
| 34105388U, // REVB_ZPmZ_H |
| 34860U, // REVB_ZPmZ_S |
| 2147503637U, // REVH_ZPmZ_D |
| 36373U, // REVH_ZPmZ_S |
| 2147506620U, // REVW_ZPmZ_D |
| 100718619U, // REVWr |
| 100718619U, // REVXr |
| 436221979U, // REV_PP_B |
| 268458011U, // REV_PP_D |
| 845183003U, // REV_PP_H |
| 469800987U, // REV_PP_S |
| 436221979U, // REV_ZZ_B |
| 268458011U, // REV_ZZ_D |
| 845183003U, // REV_ZZ_H |
| 469800987U, // REV_ZZ_S |
| 2248198799U, // RMIF |
| 2248201171U, // RORVWr |
| 2248201171U, // RORVXr |
| 2348820083U, // RSHRNB_ZZI_B |
| 2387109491U, // RSHRNB_ZZI_H |
| 2415953523U, // RSHRNB_ZZI_S |
| 2449487624U, // RSHRNT_ZZI_B |
| 240154376U, // RSHRNT_ZZI_H |
| 2281740040U, // RSHRNT_ZZI_S |
| 2484134271U, // RSHRNv16i8_shift |
| 2216210763U, // RSHRNv2i32_shift |
| 69775691U, // RSHRNv4i16_shift |
| 2486231423U, // RSHRNv4i32_shift |
| 339272063U, // RSHRNv8i16_shift |
| 2218832203U, // RSHRNv8i8_shift |
| 2348820027U, // RSUBHNB_ZZZ_B |
| 239625787U, // RSUBHNB_ZZZ_H |
| 2415953467U, // RSUBHNB_ZZZ_S |
| 2449487580U, // RSUBHNT_ZZZ_B |
| 240154332U, // RSUBHNT_ZZZ_H |
| 2281739996U, // RSUBHNT_ZZZ_S |
| 2216210690U, // RSUBHNv2i64_v2i32 |
| 2486231385U, // RSUBHNv2i64_v4i32 |
| 69775618U, // RSUBHNv4i32_v4i16 |
| 339272025U, // RSUBHNv4i32_v8i16 |
| 2484134233U, // RSUBHNv8i16_v16i8 |
| 2218832130U, // RSUBHNv8i16_v8i8 |
| 2315273396U, // SABALB_ZZZ_D |
| 29385908U, // SABALB_ZZZ_H |
| 2449507508U, // SABALB_ZZZ_S |
| 2315277803U, // SABALT_ZZZ_D |
| 29390315U, // SABALT_ZZZ_H |
| 2449511915U, // SABALT_ZZZ_S |
| 339271835U, // SABALv16i8_v8i16 |
| 2485186195U, // SABALv2i32_v2i64 |
| 338751123U, // SABALv4i16_v4i32 |
| 337698971U, // SABALv4i32_v2i64 |
| 2486231195U, // SABALv8i16_v4i32 |
| 2486759059U, // SABALv8i8_v8i16 |
| 637543037U, // SABA_ZZZ_B |
| 2281718397U, // SABA_ZZZ_D |
| 2390254205U, // SABA_ZZZ_H |
| 2315289213U, // SABA_ZZZ_S |
| 336650877U, // SABAv16i8 |
| 2484658813U, // SABAv2i32 |
| 338223741U, // SABAv4i16 |
| 338748029U, // SABAv4i32 |
| 2486755965U, // SABAv8i16 |
| 2487280253U, // SABAv8i8 |
| 2617263464U, // SABDLB_ZZZ_D |
| 261645672U, // SABDLB_ZZZ_H |
| 2348844392U, // SABDLB_ZZZ_S |
| 2617267771U, // SABDLT_ZZZ_D |
| 261649979U, // SABDLT_ZZZ_H |
| 2348848699U, // SABDLT_ZZZ_S |
| 70820061U, // SABDLv16i8_v8i16 |
| 2216734532U, // SABDLv2i32_v2i64 |
| 70299460U, // SABDLv4i16_v4i32 |
| 69247197U, // SABDLv4i32_v2i64 |
| 2217779421U, // SABDLv8i16_v4i32 |
| 2218307396U, // SABDLv8i8_v8i16 |
| 369109284U, // SABD_ZPmZ_B |
| 369117476U, // SABD_ZPmZ_D |
| 2555930916U, // SABD_ZPmZ_H |
| 369133860U, // SABD_ZPmZ_S |
| 68200740U, // SABDv16i8 |
| 2216208676U, // SABDv2i32 |
| 69773604U, // SABDv4i16 |
| 70297892U, // SABDv4i32 |
| 2218305828U, // SABDv8i16 |
| 2218830116U, // SABDv8i8 |
| 369119773U, // SADALP_ZPmZ_D |
| 408449565U, // SADALP_ZPmZ_H |
| 369136157U, // SADALP_ZPmZ_S |
| 2486759965U, // SADALPv16i8_v8i16 |
| 2512974365U, // SADALPv2i32_v1i64 |
| 2484662813U, // SADALPv4i16_v2i32 |
| 337703453U, // SADALPv4i32_v2i64 |
| 2486235677U, // SADALPv8i16_v4i32 |
| 338227741U, // SADALPv8i8_v4i16 |
| 2617267607U, // SADDLBT_ZZZ_D |
| 261649815U, // SADDLBT_ZZZ_H |
| 2348848535U, // SADDLBT_ZZZ_S |
| 2617263489U, // SADDLB_ZZZ_D |
| 261645697U, // SADDLB_ZZZ_H |
| 2348844417U, // SADDLB_ZZZ_S |
| 2218308141U, // SADDLPv16i8_v8i16 |
| 2244522541U, // SADDLPv2i32_v1i64 |
| 2216210989U, // SADDLPv4i16_v2i32 |
| 69251629U, // SADDLPv4i32_v2i64 |
| 2217783853U, // SADDLPv8i16_v4i32 |
| 69775917U, // SADDLPv8i8_v4i16 |
| 2617267787U, // SADDLT_ZZZ_D |
| 261649995U, // SADDLT_ZZZ_H |
| 2348848715U, // SADDLT_ZZZ_S |
| 2214647858U, // SADDLVv16i8v |
| 2214647858U, // SADDLVv4i16v |
| 67164210U, // SADDLVv4i32v |
| 2214647858U, // SADDLVv8i16v |
| 67164210U, // SADDLVv8i8v |
| 70820077U, // SADDLv16i8_v8i16 |
| 2216734570U, // SADDLv2i32_v2i64 |
| 70299498U, // SADDLv4i16_v4i32 |
| 69247213U, // SADDLv4i32_v2i64 |
| 2217779437U, // SADDLv8i16_v4i32 |
| 2218307434U, // SADDLv8i8_v8i16 |
| 2516637703U, // SADDV_VPZ_B |
| 2516637703U, // SADDV_VPZ_H |
| 2516637703U, // SADDV_VPZ_S |
| 2415937602U, // SADDWB_ZZZ_D |
| 241199170U, // SADDWB_ZZZ_H |
| 2617280578U, // SADDWB_ZZZ_S |
| 2415941555U, // SADDWT_ZZZ_D |
| 241203123U, // SADDWT_ZZZ_H |
| 2617284531U, // SADDWT_ZZZ_S |
| 2218303998U, // SADDWv16i8_v8i16 |
| 2216737068U, // SADDWv2i32_v2i64 |
| 70301996U, // SADDWv4i16_v4i32 |
| 2216731134U, // SADDWv4i32_v2i64 |
| 70296062U, // SADDWv8i16_v4i32 |
| 2218309932U, // SADDWv8i8_v8i16 |
| 7172U, // SB |
| 2281719130U, // SBCLB_ZZZ_D |
| 2315289946U, // SBCLB_ZZZ_S |
| 2281723437U, // SBCLT_ZZZ_D |
| 2315294253U, // SBCLT_ZZZ_S |
| 2248201389U, // SBCSWr |
| 2248201389U, // SBCSXr |
| 2248198283U, // SBCWr |
| 2248198283U, // SBCXr |
| 2248200362U, // SBFMWri |
| 2248200362U, // SBFMXri |
| 2248198805U, // SCVTFSWDri |
| 2248198805U, // SCVTFSWHri |
| 2248198805U, // SCVTFSWSri |
| 2248198805U, // SCVTFSXDri |
| 2248198805U, // SCVTFSXHri |
| 2248198805U, // SCVTFSXSri |
| 100715157U, // SCVTFUWDri |
| 100715157U, // SCVTFUWHri |
| 100715157U, // SCVTFUWSri |
| 100715157U, // SCVTFUXDri |
| 100715157U, // SCVTFUXHri |
| 100715157U, // SCVTFUXSri |
| 2147502741U, // SCVTF_ZPmZ_DtoD |
| 1141402261U, // SCVTF_ZPmZ_DtoH |
| 2147519125U, // SCVTF_ZPmZ_DtoS |
| 34106005U, // SCVTF_ZPmZ_HtoH |
| 19093U, // SCVTF_ZPmZ_StoD |
| 1107847829U, // SCVTF_ZPmZ_StoH |
| 35477U, // SCVTF_ZPmZ_StoS |
| 2248198805U, // SCVTFd |
| 2248198805U, // SCVTFh |
| 2248198805U, // SCVTFs |
| 100715157U, // SCVTFv1i16 |
| 100715157U, // SCVTFv1i32 |
| 100715157U, // SCVTFv1i64 |
| 2216209045U, // SCVTFv2f32 |
| 69249685U, // SCVTFv2f64 |
| 2216209045U, // SCVTFv2i32_shift |
| 2216733333U, // SCVTFv2i64_shift |
| 2217257621U, // SCVTFv4f16 |
| 70298261U, // SCVTFv4f32 |
| 69773973U, // SCVTFv4i16_shift |
| 70298261U, // SCVTFv4i32_shift |
| 2218306197U, // SCVTFv8f16 |
| 2218306197U, // SCVTFv8i16_shift |
| 369120318U, // SDIVR_ZPmZ_D |
| 369136702U, // SDIVR_ZPmZ_S |
| 2248202278U, // SDIVWr |
| 2248202278U, // SDIVXr |
| 369121318U, // SDIV_ZPmZ_D |
| 369137702U, // SDIV_ZPmZ_S |
| 2449495903U, // SDOT_ZZZI_D |
| 637572959U, // SDOT_ZZZI_S |
| 2449495903U, // SDOT_ZZZ_D |
| 637572959U, // SDOT_ZZZ_S |
| 338753375U, // SDOTlanev16i8 |
| 2484664159U, // SDOTlanev8i8 |
| 338753375U, // SDOTv16i8 |
| 2484664159U, // SDOTv8i8 |
| 2516594563U, // SEL_PPPP |
| 2516594563U, // SEL_ZPZZ_B |
| 2516602755U, // SEL_ZPZZ_D |
| 2388160387U, // SEL_ZPZZ_H |
| 2516619139U, // SEL_ZPZZ_S |
| 7389761U, // SETF16 |
| 7389776U, // SETF8 |
| 7203U, // SETFFR |
| 2684446852U, // SHA1Crrr |
| 100715246U, // SHA1Hrr |
| 2684448931U, // SHA1Mrrr |
| 2684449240U, // SHA1Prrr |
| 338747393U, // SHA1SU0rrr |
| 338747467U, // SHA1SU1rr |
| 2684444817U, // SHA256H2rrr |
| 2684447574U, // SHA256Hrrr |
| 338747413U, // SHA256SU0rr |
| 338747487U, // SHA256SU1rrr |
| 2684447521U, // SHA512H |
| 2684444807U, // SHA512H2 |
| 69246986U, // SHA512SU0 |
| 2485182548U, // SHA512SU1 |
| 369109379U, // SHADD_ZPmZ_B |
| 369117571U, // SHADD_ZPmZ_D |
| 2555931011U, // SHADD_ZPmZ_H |
| 369133955U, // SHADD_ZPmZ_S |
| 68200835U, // SHADDv16i8 |
| 2216208771U, // SHADDv2i32 |
| 69773699U, // SHADDv4i16 |
| 70297987U, // SHADDv4i32 |
| 2218305923U, // SHADDv8i16 |
| 2218830211U, // SHADDv8i8 |
| 2218303742U, // SHLLv16i8 |
| 69251017U, // SHLLv2i32 |
| 2217783241U, // SHLLv4i16 |
| 69247230U, // SHLLv4i32 |
| 2217779454U, // SHLLv8i16 |
| 70823881U, // SHLLv8i8 |
| 2248200082U, // SHLd |
| 68202386U, // SHLv16i8_shift |
| 2216210322U, // SHLv2i32_shift |
| 2216734610U, // SHLv2i64_shift |
| 69775250U, // SHLv4i16_shift |
| 70299538U, // SHLv4i32_shift |
| 2218307474U, // SHLv8i16_shift |
| 2218831762U, // SHLv8i8_shift |
| 2348820065U, // SHRNB_ZZI_B |
| 2387109473U, // SHRNB_ZZI_H |
| 2415953505U, // SHRNB_ZZI_S |
| 2449487606U, // SHRNT_ZZI_B |
| 240154358U, // SHRNT_ZZI_H |
| 2281740022U, // SHRNT_ZZI_S |
| 2484134253U, // SHRNv16i8_shift |
| 2216210747U, // SHRNv2i32_shift |
| 69775675U, // SHRNv4i16_shift |
| 2486231405U, // SHRNv4i32_shift |
| 339272045U, // SHRNv8i16_shift |
| 2218832187U, // SHRNv8i8_shift |
| 369111844U, // SHSUBR_ZPmZ_B |
| 369120036U, // SHSUBR_ZPmZ_D |
| 2555933476U, // SHSUBR_ZPmZ_H |
| 369136420U, // SHSUBR_ZPmZ_S |
| 369108993U, // SHSUB_ZPmZ_B |
| 369117185U, // SHSUB_ZPmZ_D |
| 2555930625U, // SHSUB_ZPmZ_H |
| 369133569U, // SHSUB_ZPmZ_S |
| 68200449U, // SHSUBv16i8 |
| 2216208385U, // SHSUBv2i32 |
| 69773313U, // SHSUBv4i16 |
| 70297601U, // SHSUBv4i32 |
| 2218305537U, // SHSUBv8i16 |
| 2218829825U, // SHSUBv8i8 |
| 637546085U, // SLI_ZZI_B |
| 2281721445U, // SLI_ZZI_D |
| 242773605U, // SLI_ZZI_H |
| 2315292261U, // SLI_ZZI_S |
| 2684448357U, // SLId |
| 336653925U, // SLIv16i8_shift |
| 2484661861U, // SLIv2i32_shift |
| 2485186149U, // SLIv2i64_shift |
| 338226789U, // SLIv4i16_shift |
| 338751077U, // SLIv4i32_shift |
| 2486759013U, // SLIv8i16_shift |
| 2487283301U, // SLIv8i8_shift |
| 338747498U, // SM3PARTW1 |
| 338747918U, // SM3PARTW2 |
| 70295614U, // SM3SS1 |
| 338747991U, // SM3TT1A |
| 338748328U, // SM3TT1B |
| 338748000U, // SM3TT2A |
| 338748357U, // SM3TT2B |
| 70298077U, // SM4E |
| 2617285181U, // SM4EKEY_ZZZ_S |
| 70302269U, // SM4ENCKEY |
| 2617280989U, // SM4E_ZZZ_S |
| 2248200026U, // SMADDLrrr |
| 369111739U, // SMAXP_ZPmZ_B |
| 369119931U, // SMAXP_ZPmZ_D |
| 2555933371U, // SMAXP_ZPmZ_H |
| 369136315U, // SMAXP_ZPmZ_S |
| 68203195U, // SMAXPv16i8 |
| 2216211131U, // SMAXPv2i32 |
| 69776059U, // SMAXPv4i16 |
| 70300347U, // SMAXPv4i32 |
| 2218308283U, // SMAXPv8i16 |
| 2218832571U, // SMAXPv8i8 |
| 2516637839U, // SMAXV_VPZ_B |
| 2516637839U, // SMAXV_VPZ_D |
| 2516637839U, // SMAXV_VPZ_H |
| 2516637839U, // SMAXV_VPZ_S |
| 2214647951U, // SMAXVv16i8v |
| 2214647951U, // SMAXVv4i16v |
| 67164303U, // SMAXVv4i32v |
| 2214647951U, // SMAXVv8i16v |
| 67164303U, // SMAXVv8i8v |
| 2583706092U, // SMAX_ZI_B |
| 2415942124U, // SMAX_ZI_D |
| 2388687340U, // SMAX_ZI_H |
| 2617285100U, // SMAX_ZI_S |
| 369113580U, // SMAX_ZPmZ_B |
| 369121772U, // SMAX_ZPmZ_D |
| 2555935212U, // SMAX_ZPmZ_H |
| 369138156U, // SMAX_ZPmZ_S |
| 68205036U, // SMAXv16i8 |
| 2216212972U, // SMAXv2i32 |
| 69777900U, // SMAXv4i16 |
| 70302188U, // SMAXv4i32 |
| 2218310124U, // SMAXv8i16 |
| 2218834412U, // SMAXv8i8 |
| 75940U, // SMC |
| 369111657U, // SMINP_ZPmZ_B |
| 369119849U, // SMINP_ZPmZ_D |
| 2555933289U, // SMINP_ZPmZ_H |
| 369136233U, // SMINP_ZPmZ_S |
| 68203113U, // SMINPv16i8 |
| 2216211049U, // SMINPv2i32 |
| 69775977U, // SMINPv4i16 |
| 70300265U, // SMINPv4i32 |
| 2218308201U, // SMINPv8i16 |
| 2218832489U, // SMINPv8i8 |
| 2516637787U, // SMINV_VPZ_B |
| 2516637787U, // SMINV_VPZ_D |
| 2516637787U, // SMINV_VPZ_H |
| 2516637787U, // SMINV_VPZ_S |
| 2214647899U, // SMINVv16i8v |
| 2214647899U, // SMINVv4i16v |
| 67164251U, // SMINVv4i32v |
| 2214647899U, // SMINVv8i16v |
| 67164251U, // SMINVv8i8v |
| 2583703834U, // SMIN_ZI_B |
| 2415939866U, // SMIN_ZI_D |
| 2388685082U, // SMIN_ZI_H |
| 2617282842U, // SMIN_ZI_S |
| 369111322U, // SMIN_ZPmZ_B |
| 369119514U, // SMIN_ZPmZ_D |
| 2555932954U, // SMIN_ZPmZ_H |
| 369135898U, // SMIN_ZPmZ_S |
| 68202778U, // SMINv16i8 |
| 2216210714U, // SMINv2i32 |
| 69775642U, // SMINv4i16 |
| 70299930U, // SMINv4i32 |
| 2218307866U, // SMINv8i16 |
| 2218832154U, // SMINv8i8 |
| 2315273440U, // SMLALB_ZZZI_D |
| 2449507552U, // SMLALB_ZZZI_S |
| 2315273440U, // SMLALB_ZZZ_D |
| 29385952U, // SMLALB_ZZZ_H |
| 2449507552U, // SMLALB_ZZZ_S |
| 2315277837U, // SMLALT_ZZZI_D |
| 2449511949U, // SMLALT_ZZZI_S |
| 2315277837U, // SMLALT_ZZZ_D |
| 29390349U, // SMLALT_ZZZ_H |
| 2449511949U, // SMLALT_ZZZ_S |
| 339271869U, // SMLALv16i8_v8i16 |
| 2485186234U, // SMLALv2i32_indexed |
| 2485186234U, // SMLALv2i32_v2i64 |
| 338751162U, // SMLALv4i16_indexed |
| 338751162U, // SMLALv4i16_v4i32 |
| 337699005U, // SMLALv4i32_indexed |
| 337699005U, // SMLALv4i32_v2i64 |
| 2486231229U, // SMLALv8i16_indexed |
| 2486231229U, // SMLALv8i16_v4i32 |
| 2486759098U, // SMLALv8i8_v8i16 |
| 2315273737U, // SMLSLB_ZZZI_D |
| 2449507849U, // SMLSLB_ZZZI_S |
| 2315273737U, // SMLSLB_ZZZ_D |
| 29386249U, // SMLSLB_ZZZ_H |
| 2449507849U, // SMLSLB_ZZZ_S |
| 2315278011U, // SMLSLT_ZZZI_D |
| 2449512123U, // SMLSLT_ZZZI_S |
| 2315278011U, // SMLSLT_ZZZ_D |
| 29390523U, // SMLSLT_ZZZ_H |
| 2449512123U, // SMLSLT_ZZZ_S |
| 339272001U, // SMLSLv16i8_v8i16 |
| 2485186630U, // SMLSLv2i32_indexed |
| 2485186630U, // SMLSLv2i32_v2i64 |
| 338751558U, // SMLSLv4i16_indexed |
| 338751558U, // SMLSLv4i16_v4i32 |
| 337699137U, // SMLSLv4i32_indexed |
| 337699137U, // SMLSLv4i32_v2i64 |
| 2486231361U, // SMLSLv8i16_indexed |
| 2486231361U, // SMLSLv8i16_v4i32 |
| 2486759494U, // SMLSLv8i8_v8i16 |
| 67164278U, // SMOVvi16to32 |
| 67164278U, // SMOVvi16to64 |
| 2214647926U, // SMOVvi32to64 |
| 2214647926U, // SMOVvi8to32 |
| 2214647926U, // SMOVvi8to64 |
| 2248199974U, // SMSUBLrrr |
| 369110218U, // SMULH_ZPmZ_B |
| 369118410U, // SMULH_ZPmZ_D |
| 2555931850U, // SMULH_ZPmZ_H |
| 369134794U, // SMULH_ZPmZ_S |
| 2583702730U, // SMULH_ZZZ_B |
| 2415938762U, // SMULH_ZZZ_D |
| 2388683978U, // SMULH_ZZZ_H |
| 2617281738U, // SMULH_ZZZ_S |
| 2248199370U, // SMULHrr |
| 2617263539U, // SMULLB_ZZZI_D |
| 2348844467U, // SMULLB_ZZZI_S |
| 2617263539U, // SMULLB_ZZZ_D |
| 261645747U, // SMULLB_ZZZ_H |
| 2348844467U, // SMULLB_ZZZ_S |
| 2617267851U, // SMULLT_ZZZI_D |
| 2348848779U, // SMULLT_ZZZI_S |
| 2617267851U, // SMULLT_ZZZ_D |
| 261650059U, // SMULLT_ZZZ_H |
| 2348848779U, // SMULLT_ZZZ_S |
| 70820127U, // SMULLv16i8_v8i16 |
| 2216734694U, // SMULLv2i32_indexed |
| 2216734694U, // SMULLv2i32_v2i64 |
| 70299622U, // SMULLv4i16_indexed |
| 70299622U, // SMULLv4i16_v4i32 |
| 69247263U, // SMULLv4i32_indexed |
| 69247263U, // SMULLv4i32_v2i64 |
| 2217779487U, // SMULLv8i16_indexed |
| 2217779487U, // SMULLv8i16_v4i32 |
| 2218307558U, // SMULLv8i8_v8i16 |
| 0U, // SPACE |
| 2516593123U, // SPLICE_ZPZZ_B |
| 2516601315U, // SPLICE_ZPZZ_D |
| 2388158947U, // SPLICE_ZPZZ_H |
| 2516617699U, // SPLICE_ZPZZ_S |
| 2516593123U, // SPLICE_ZPZ_B |
| 2516601315U, // SPLICE_ZPZ_D |
| 2388158947U, // SPLICE_ZPZ_H |
| 2516617699U, // SPLICE_ZPZ_S |
| 13457U, // SQABS_ZPmZ_B |
| 2147505297U, // SQABS_ZPmZ_D |
| 34108561U, // SQABS_ZPmZ_H |
| 38033U, // SQABS_ZPmZ_S |
| 2215687313U, // SQABSv16i8 |
| 100717713U, // SQABSv1i16 |
| 100717713U, // SQABSv1i32 |
| 100717713U, // SQABSv1i64 |
| 100717713U, // SQABSv1i8 |
| 2216211601U, // SQABSv2i32 |
| 69252241U, // SQABSv2i64 |
| 2217260177U, // SQABSv4i16 |
| 70300817U, // SQABSv4i32 |
| 2218308753U, // SQABSv8i16 |
| 71349393U, // SQABSv8i8 |
| 2583701921U, // SQADD_ZI_B |
| 2415937953U, // SQADD_ZI_D |
| 241199521U, // SQADD_ZI_H |
| 2617280929U, // SQADD_ZI_S |
| 369109409U, // SQADD_ZPmZ_B |
| 369117601U, // SQADD_ZPmZ_D |
| 2555931041U, // SQADD_ZPmZ_H |
| 369133985U, // SQADD_ZPmZ_S |
| 2583701921U, // SQADD_ZZZ_B |
| 2415937953U, // SQADD_ZZZ_D |
| 2388683169U, // SQADD_ZZZ_H |
| 2617280929U, // SQADD_ZZZ_S |
| 68200865U, // SQADDv16i8 |
| 2248198561U, // SQADDv1i16 |
| 2248198561U, // SQADDv1i32 |
| 2248198561U, // SQADDv1i64 |
| 2248198561U, // SQADDv1i8 |
| 2216208801U, // SQADDv2i32 |
| 2216733089U, // SQADDv2i64 |
| 69773729U, // SQADDv4i16 |
| 70298017U, // SQADDv4i32 |
| 2218305953U, // SQADDv8i16 |
| 2218830241U, // SQADDv8i8 |
| 2583701854U, // SQCADD_ZZI_B |
| 2415937886U, // SQCADD_ZZI_D |
| 2388683102U, // SQCADD_ZZI_H |
| 2617280862U, // SQCADD_ZZI_S |
| 805356637U, // SQDECB_XPiI |
| 1543554141U, // SQDECB_XPiWdI |
| 805357879U, // SQDECD_XPiI |
| 1543555383U, // SQDECD_XPiWdI |
| 805325111U, // SQDECD_ZPiI |
| 805358551U, // SQDECH_XPiI |
| 1543556055U, // SQDECH_XPiWdI |
| 8416215U, // SQDECH_ZPiI |
| 2583744997U, // SQDECP_XPWd_B |
| 2415972837U, // SQDECP_XPWd_D |
| 2348863973U, // SQDECP_XPWd_H |
| 2617299429U, // SQDECP_XPWd_S |
| 436261349U, // SQDECP_XP_B |
| 268489189U, // SQDECP_XP_D |
| 201380325U, // SQDECP_XP_H |
| 469815781U, // SQDECP_XP_S |
| 134238693U, // SQDECP_ZP_D |
| 846754277U, // SQDECP_ZP_H |
| 167809509U, // SQDECP_ZP_S |
| 805361932U, // SQDECW_XPiI |
| 1543559436U, // SQDECW_XPiWdI |
| 805345548U, // SQDECW_ZPiI |
| 2315277699U, // SQDMLALBT_ZZZ_D |
| 29390211U, // SQDMLALBT_ZZZ_H |
| 2449511811U, // SQDMLALBT_ZZZ_S |
| 2315273422U, // SQDMLALB_ZZZI_D |
| 2449507534U, // SQDMLALB_ZZZI_S |
| 2315273422U, // SQDMLALB_ZZZ_D |
| 29385934U, // SQDMLALB_ZZZ_H |
| 2449507534U, // SQDMLALB_ZZZ_S |
| 2315277819U, // SQDMLALT_ZZZI_D |
| 2449511931U, // SQDMLALT_ZZZI_S |
| 2315277819U, // SQDMLALT_ZZZ_D |
| 29390331U, // SQDMLALT_ZZZ_H |
| 2449511931U, // SQDMLALT_ZZZ_S |
| 2684448426U, // SQDMLALi16 |
| 2684448426U, // SQDMLALi32 |
| 2684448426U, // SQDMLALv1i32_indexed |
| 2684448426U, // SQDMLALv1i64_indexed |
| 2485186218U, // SQDMLALv2i32_indexed |
| 2485186218U, // SQDMLALv2i32_v2i64 |
| 338751146U, // SQDMLALv4i16_indexed |
| 338751146U, // SQDMLALv4i16_v4i32 |
| 337698987U, // SQDMLALv4i32_indexed |
| 337698987U, // SQDMLALv4i32_v2i64 |
| 2486231211U, // SQDMLALv8i16_indexed |
| 2486231211U, // SQDMLALv8i16_v4i32 |
| 2315277728U, // SQDMLSLBT_ZZZ_D |
| 29390240U, // SQDMLSLBT_ZZZ_H |
| 2449511840U, // SQDMLSLBT_ZZZ_S |
| 2315273719U, // SQDMLSLB_ZZZI_D |
| 2449507831U, // SQDMLSLB_ZZZI_S |
| 2315273719U, // SQDMLSLB_ZZZ_D |
| 29386231U, // SQDMLSLB_ZZZ_H |
| 2449507831U, // SQDMLSLB_ZZZ_S |
| 2315277993U, // SQDMLSLT_ZZZI_D |
| 2449512105U, // SQDMLSLT_ZZZI_S |
| 2315277993U, // SQDMLSLT_ZZZ_D |
| 29390505U, // SQDMLSLT_ZZZ_H |
| 2449512105U, // SQDMLSLT_ZZZ_S |
| 2684448822U, // SQDMLSLi16 |
| 2684448822U, // SQDMLSLi32 |
| 2684448822U, // SQDMLSLv1i32_indexed |
| 2684448822U, // SQDMLSLv1i64_indexed |
| 2485186614U, // SQDMLSLv2i32_indexed |
| 2485186614U, // SQDMLSLv2i32_v2i64 |
| 338751542U, // SQDMLSLv4i16_indexed |
| 338751542U, // SQDMLSLv4i16_v4i32 |
| 337699119U, // SQDMLSLv4i32_indexed |
| 337699119U, // SQDMLSLv4i32_v2i64 |
| 2486231343U, // SQDMLSLv8i16_indexed |
| 2486231343U, // SQDMLSLv8i16_v4i32 |
| 2415938743U, // SQDMULH_ZZZI_D |
| 2388683959U, // SQDMULH_ZZZI_H |
| 2617281719U, // SQDMULH_ZZZI_S |
| 2583702711U, // SQDMULH_ZZZ_B |
| 2415938743U, // SQDMULH_ZZZ_D |
| 2388683959U, // SQDMULH_ZZZ_H |
| 2617281719U, // SQDMULH_ZZZ_S |
| 2248199351U, // SQDMULHv1i16 |
| 2248199351U, // SQDMULHv1i16_indexed |
| 2248199351U, // SQDMULHv1i32 |
| 2248199351U, // SQDMULHv1i32_indexed |
| 2216209591U, // SQDMULHv2i32 |
| 2216209591U, // SQDMULHv2i32_indexed |
| 69774519U, // SQDMULHv4i16 |
| 69774519U, // SQDMULHv4i16_indexed |
| 70298807U, // SQDMULHv4i32 |
| 70298807U, // SQDMULHv4i32_indexed |
| 2218306743U, // SQDMULHv8i16 |
| 2218306743U, // SQDMULHv8i16_indexed |
| 2617263521U, // SQDMULLB_ZZZI_D |
| 2348844449U, // SQDMULLB_ZZZI_S |
| 2617263521U, // SQDMULLB_ZZZ_D |
| 261645729U, // SQDMULLB_ZZZ_H |
| 2348844449U, // SQDMULLB_ZZZ_S |
| 2617267833U, // SQDMULLT_ZZZI_D |
| 2348848761U, // SQDMULLT_ZZZI_S |
| 2617267833U, // SQDMULLT_ZZZ_D |
| 261650041U, // SQDMULLT_ZZZ_H |
| 2348848761U, // SQDMULLT_ZZZ_S |
| 2248200150U, // SQDMULLi16 |
| 2248200150U, // SQDMULLi32 |
| 2248200150U, // SQDMULLv1i32_indexed |
| 2248200150U, // SQDMULLv1i64_indexed |
| 2216734678U, // SQDMULLv2i32_indexed |
| 2216734678U, // SQDMULLv2i32_v2i64 |
| 70299606U, // SQDMULLv4i16_indexed |
| 70299606U, // SQDMULLv4i16_v4i32 |
| 69247245U, // SQDMULLv4i32_indexed |
| 69247245U, // SQDMULLv4i32_v2i64 |
| 2217779469U, // SQDMULLv8i16_indexed |
| 2217779469U, // SQDMULLv8i16_v4i32 |
| 805356653U, // SQINCB_XPiI |
| 1543554157U, // SQINCB_XPiWdI |
| 805357895U, // SQINCD_XPiI |
| 1543555399U, // SQINCD_XPiWdI |
| 805325127U, // SQINCD_ZPiI |
| 805358567U, // SQINCH_XPiI |
| 1543556071U, // SQINCH_XPiWdI |
| 8416231U, // SQINCH_ZPiI |
| 2583745013U, // SQINCP_XPWd_B |
| 2415972853U, // SQINCP_XPWd_D |
| 2348863989U, // SQINCP_XPWd_H |
| 2617299445U, // SQINCP_XPWd_S |
| 436261365U, // SQINCP_XP_B |
| 268489205U, // SQINCP_XP_D |
| 201380341U, // SQINCP_XP_H |
| 469815797U, // SQINCP_XP_S |
| 134238709U, // SQINCP_ZP_D |
| 846754293U, // SQINCP_ZP_H |
| 167809525U, // SQINCP_ZP_S |
| 805361948U, // SQINCW_XPiI |
| 1543559452U, // SQINCW_XPiWdI |
| 805345564U, // SQINCW_ZPiI |
| 10951U, // SQNEG_ZPmZ_B |
| 2147502791U, // SQNEG_ZPmZ_D |
| 34106055U, // SQNEG_ZPmZ_H |
| 35527U, // SQNEG_ZPmZ_S |
| 2215684807U, // SQNEGv16i8 |
| 100715207U, // SQNEGv1i16 |
| 100715207U, // SQNEGv1i32 |
| 100715207U, // SQNEGv1i64 |
| 100715207U, // SQNEGv1i8 |
| 2216209095U, // SQNEGv2i32 |
| 69249735U, // SQNEGv2i64 |
| 2217257671U, // SQNEGv4i16 |
| 70298311U, // SQNEGv4i32 |
| 2218306247U, // SQNEGv8i16 |
| 71346887U, // SQNEGv8i8 |
| 2390256488U, // SQRDCMLAH_ZZZI_H |
| 2315291496U, // SQRDCMLAH_ZZZI_S |
| 637545320U, // SQRDCMLAH_ZZZ_B |
| 2281720680U, // SQRDCMLAH_ZZZ_D |
| 2390256488U, // SQRDCMLAH_ZZZ_H |
| 2315291496U, // SQRDCMLAH_ZZZ_S |
| 2281720691U, // SQRDMLAH_ZZZI_D |
| 2390256499U, // SQRDMLAH_ZZZI_H |
| 2315291507U, // SQRDMLAH_ZZZI_S |
| 637545331U, // SQRDMLAH_ZZZ_B |
| 2281720691U, // SQRDMLAH_ZZZ_D |
| 2390256499U, // SQRDMLAH_ZZZ_H |
| 2315291507U, // SQRDMLAH_ZZZ_S |
| 2684447603U, // SQRDMLAHi16_indexed |
| 2684447603U, // SQRDMLAHi32_indexed |
| 2684447603U, // SQRDMLAHv1i16 |
| 2684447603U, // SQRDMLAHv1i32 |
| 2484661107U, // SQRDMLAHv2i32 |
| 2484661107U, // SQRDMLAHv2i32_indexed |
| 338226035U, // SQRDMLAHv4i16 |
| 338226035U, // SQRDMLAHv4i16_indexed |
| 338750323U, // SQRDMLAHv4i32 |
| 338750323U, // SQRDMLAHv4i32_indexed |
| 2486758259U, // SQRDMLAHv8i16 |
| 2486758259U, // SQRDMLAHv8i16_indexed |
| 2281721288U, // SQRDMLSH_ZZZI_D |
| 2390257096U, // SQRDMLSH_ZZZI_H |
| 2315292104U, // SQRDMLSH_ZZZI_S |
| 637545928U, // SQRDMLSH_ZZZ_B |
| 2281721288U, // SQRDMLSH_ZZZ_D |
| 2390257096U, // SQRDMLSH_ZZZ_H |
| 2315292104U, // SQRDMLSH_ZZZ_S |
| 2684448200U, // SQRDMLSHi16_indexed |
| 2684448200U, // SQRDMLSHi32_indexed |
| 2684448200U, // SQRDMLSHv1i16 |
| 2684448200U, // SQRDMLSHv1i32 |
| 2484661704U, // SQRDMLSHv2i32 |
| 2484661704U, // SQRDMLSHv2i32_indexed |
| 338226632U, // SQRDMLSHv4i16 |
| 338226632U, // SQRDMLSHv4i16_indexed |
| 338750920U, // SQRDMLSHv4i32 |
| 338750920U, // SQRDMLSHv4i32_indexed |
| 2486758856U, // SQRDMLSHv8i16 |
| 2486758856U, // SQRDMLSHv8i16_indexed |
| 2415938752U, // SQRDMULH_ZZZI_D |
| 2388683968U, // SQRDMULH_ZZZI_H |
| 2617281728U, // SQRDMULH_ZZZI_S |
| 2583702720U, // SQRDMULH_ZZZ_B |
| 2415938752U, // SQRDMULH_ZZZ_D |
| 2388683968U, // SQRDMULH_ZZZ_H |
| 2617281728U, // SQRDMULH_ZZZ_S |
| 2248199360U, // SQRDMULHv1i16 |
| 2248199360U, // SQRDMULHv1i16_indexed |
| 2248199360U, // SQRDMULHv1i32 |
| 2248199360U, // SQRDMULHv1i32_indexed |
| 2216209600U, // SQRDMULHv2i32 |
| 2216209600U, // SQRDMULHv2i32_indexed |
| 69774528U, // SQRDMULHv4i16 |
| 69774528U, // SQRDMULHv4i16_indexed |
| 70298816U, // SQRDMULHv4i32 |
| 70298816U, // SQRDMULHv4i32_indexed |
| 2218306752U, // SQRDMULHv8i16 |
| 2218306752U, // SQRDMULHv8i16_indexed |
| 369111954U, // SQRSHLR_ZPmZ_B |
| 369120146U, // SQRSHLR_ZPmZ_D |
| 2555933586U, // SQRSHLR_ZPmZ_H |
| 369136530U, // SQRSHLR_ZPmZ_S |
| 369110942U, // SQRSHL_ZPmZ_B |
| 369119134U, // SQRSHL_ZPmZ_D |
| 2555932574U, // SQRSHL_ZPmZ_H |
| 369135518U, // SQRSHL_ZPmZ_S |
| 68202398U, // SQRSHLv16i8 |
| 2248200094U, // SQRSHLv1i16 |
| 2248200094U, // SQRSHLv1i32 |
| 2248200094U, // SQRSHLv1i64 |
| 2248200094U, // SQRSHLv1i8 |
| 2216210334U, // SQRSHLv2i32 |
| 2216734622U, // SQRSHLv2i64 |
| 69775262U, // SQRSHLv4i16 |
| 70299550U, // SQRSHLv4i32 |
| 2218307486U, // SQRSHLv8i16 |
| 2218831774U, // SQRSHLv8i8 |
| 2348820081U, // SQRSHRNB_ZZI_B |
| 2387109489U, // SQRSHRNB_ZZI_H |
| 2415953521U, // SQRSHRNB_ZZI_S |
| 2449487622U, // SQRSHRNT_ZZI_B |
| 240154374U, // SQRSHRNT_ZZI_H |
| 2281740038U, // SQRSHRNT_ZZI_S |
| 2248200521U, // SQRSHRNb |
| 2248200521U, // SQRSHRNh |
| 2248200521U, // SQRSHRNs |
| 2484134269U, // SQRSHRNv16i8_shift |
| 2216210761U, // SQRSHRNv2i32_shift |
| 69775689U, // SQRSHRNv4i16_shift |
| 2486231421U, // SQRSHRNv4i32_shift |
| 339272061U, // SQRSHRNv8i16_shift |
| 2218832201U, // SQRSHRNv8i8_shift |
| 2348820127U, // SQRSHRUNB_ZZI_B |
| 2387109535U, // SQRSHRUNB_ZZI_H |
| 2415953567U, // SQRSHRUNB_ZZI_S |
| 2449487676U, // SQRSHRUNT_ZZI_B |
| 240154428U, // SQRSHRUNT_ZZI_H |
| 2281740092U, // SQRSHRUNT_ZZI_S |
| 2248200582U, // SQRSHRUNb |
| 2248200582U, // SQRSHRUNh |
| 2248200582U, // SQRSHRUNs |
| 2484134329U, // SQRSHRUNv16i8_shift |
| 2216210822U, // SQRSHRUNv2i32_shift |
| 69775750U, // SQRSHRUNv4i16_shift |
| 2486231481U, // SQRSHRUNv4i32_shift |
| 339272121U, // SQRSHRUNv8i16_shift |
| 2218832262U, // SQRSHRUNv8i8_shift |
| 369111938U, // SQSHLR_ZPmZ_B |
| 369120130U, // SQSHLR_ZPmZ_D |
| 2555933570U, // SQSHLR_ZPmZ_H |
| 369136514U, // SQSHLR_ZPmZ_S |
| 369113048U, // SQSHLU_ZPmI_B |
| 369121240U, // SQSHLU_ZPmI_D |
| 2555934680U, // SQSHLU_ZPmI_H |
| 369137624U, // SQSHLU_ZPmI_S |
| 2248202200U, // SQSHLUb |
| 2248202200U, // SQSHLUd |
| 2248202200U, // SQSHLUh |
| 2248202200U, // SQSHLUs |
| 68204504U, // SQSHLUv16i8_shift |
| 2216212440U, // SQSHLUv2i32_shift |
| 2216736728U, // SQSHLUv2i64_shift |
| 69777368U, // SQSHLUv4i16_shift |
| 70301656U, // SQSHLUv4i32_shift |
| 2218309592U, // SQSHLUv8i16_shift |
| 2218833880U, // SQSHLUv8i8_shift |
| 369110928U, // SQSHL_ZPmI_B |
| 369119120U, // SQSHL_ZPmI_D |
| 2555932560U, // SQSHL_ZPmI_H |
| 369135504U, // SQSHL_ZPmI_S |
| 369110928U, // SQSHL_ZPmZ_B |
| 369119120U, // SQSHL_ZPmZ_D |
| 2555932560U, // SQSHL_ZPmZ_H |
| 369135504U, // SQSHL_ZPmZ_S |
| 2248200080U, // SQSHLb |
| 2248200080U, // SQSHLd |
| 2248200080U, // SQSHLh |
| 2248200080U, // SQSHLs |
| 68202384U, // SQSHLv16i8 |
| 68202384U, // SQSHLv16i8_shift |
| 2248200080U, // SQSHLv1i16 |
| 2248200080U, // SQSHLv1i32 |
| 2248200080U, // SQSHLv1i64 |
| 2248200080U, // SQSHLv1i8 |
| 2216210320U, // SQSHLv2i32 |
| 2216210320U, // SQSHLv2i32_shift |
| 2216734608U, // SQSHLv2i64 |
| 2216734608U, // SQSHLv2i64_shift |
| 69775248U, // SQSHLv4i16 |
| 69775248U, // SQSHLv4i16_shift |
| 70299536U, // SQSHLv4i32 |
| 70299536U, // SQSHLv4i32_shift |
| 2218307472U, // SQSHLv8i16 |
| 2218307472U, // SQSHLv8i16_shift |
| 2218831760U, // SQSHLv8i8 |
| 2218831760U, // SQSHLv8i8_shift |
| 2348820063U, // SQSHRNB_ZZI_B |
| 2387109471U, // SQSHRNB_ZZI_H |
| 2415953503U, // SQSHRNB_ZZI_S |
| 2449487604U, // SQSHRNT_ZZI_B |
| 240154356U, // SQSHRNT_ZZI_H |
| 2281740020U, // SQSHRNT_ZZI_S |
| 2248200505U, // SQSHRNb |
| 2248200505U, // SQSHRNh |
| 2248200505U, // SQSHRNs |
| 2484134251U, // SQSHRNv16i8_shift |
| 2216210745U, // SQSHRNv2i32_shift |
| 69775673U, // SQSHRNv4i16_shift |
| 2486231403U, // SQSHRNv4i32_shift |
| 339272043U, // SQSHRNv8i16_shift |
| 2218832185U, // SQSHRNv8i8_shift |
| 2348820117U, // SQSHRUNB_ZZI_B |
| 2387109525U, // SQSHRUNB_ZZI_H |
| 2415953557U, // SQSHRUNB_ZZI_S |
| 2449487666U, // SQSHRUNT_ZZI_B |
| 240154418U, // SQSHRUNT_ZZI_H |
| 2281740082U, // SQSHRUNT_ZZI_S |
| 2248200573U, // SQSHRUNb |
| 2248200573U, // SQSHRUNh |
| 2248200573U, // SQSHRUNs |
| 2484134319U, // SQSHRUNv16i8_shift |
| 2216210813U, // SQSHRUNv2i32_shift |
| 69775741U, // SQSHRUNv4i16_shift |
| 2486231471U, // SQSHRUNv4i32_shift |
| 339272111U, // SQSHRUNv8i16_shift |
| 2218832253U, // SQSHRUNv8i8_shift |
| 369111860U, // SQSUBR_ZPmZ_B |
| 369120052U, // SQSUBR_ZPmZ_D |
| 2555933492U, // SQSUBR_ZPmZ_H |
| 369136436U, // SQSUBR_ZPmZ_S |
| 2583701534U, // SQSUB_ZI_B |
| 2415937566U, // SQSUB_ZI_D |
| 241199134U, // SQSUB_ZI_H |
| 2617280542U, // SQSUB_ZI_S |
| 369109022U, // SQSUB_ZPmZ_B |
| 369117214U, // SQSUB_ZPmZ_D |
| 2555930654U, // SQSUB_ZPmZ_H |
| 369133598U, // SQSUB_ZPmZ_S |
| 2583701534U, // SQSUB_ZZZ_B |
| 2415937566U, // SQSUB_ZZZ_D |
| 2388682782U, // SQSUB_ZZZ_H |
| 2617280542U, // SQSUB_ZZZ_S |
| 68200478U, // SQSUBv16i8 |
| 2248198174U, // SQSUBv1i16 |
| 2248198174U, // SQSUBv1i32 |
| 2248198174U, // SQSUBv1i64 |
| 2248198174U, // SQSUBv1i8 |
| 2216208414U, // SQSUBv2i32 |
| 2216732702U, // SQSUBv2i64 |
| 69773342U, // SQSUBv4i16 |
| 70297630U, // SQSUBv4i32 |
| 2218305566U, // SQSUBv8i16 |
| 2218829854U, // SQSUBv8i8 |
| 201336453U, // SQXTNB_ZZ_B |
| 843605637U, // SQXTNB_ZZ_H |
| 268469893U, // SQXTNB_ZZ_S |
| 302004002U, // SQXTNT_ZZ_B |
| 844134178U, // SQXTNT_ZZ_H |
| 134256418U, // SQXTNT_ZZ_S |
| 2484134303U, // SQXTNv16i8 |
| 100716911U, // SQXTNv1i16 |
| 100716911U, // SQXTNv1i32 |
| 100716911U, // SQXTNv1i8 |
| 68727151U, // SQXTNv2i32 |
| 69775727U, // SQXTNv4i16 |
| 338747807U, // SQXTNv4i32 |
| 339272095U, // SQXTNv8i16 |
| 2218832239U, // SQXTNv8i8 |
| 201336490U, // SQXTUNB_ZZ_B |
| 843605674U, // SQXTUNB_ZZ_H |
| 268469930U, // SQXTUNB_ZZ_S |
| 302004039U, // SQXTUNT_ZZ_B |
| 844134215U, // SQXTUNT_ZZ_H |
| 134256455U, // SQXTUNT_ZZ_S |
| 2484134340U, // SQXTUNv16i8 |
| 100716944U, // SQXTUNv1i16 |
| 100716944U, // SQXTUNv1i32 |
| 100716944U, // SQXTUNv1i8 |
| 68727184U, // SQXTUNv2i32 |
| 69775760U, // SQXTUNv4i16 |
| 338747844U, // SQXTUNv4i32 |
| 339272132U, // SQXTUNv8i16 |
| 2218832272U, // SQXTUNv8i8 |
| 369109363U, // SRHADD_ZPmZ_B |
| 369117555U, // SRHADD_ZPmZ_D |
| 2555930995U, // SRHADD_ZPmZ_H |
| 369133939U, // SRHADD_ZPmZ_S |
| 68200819U, // SRHADDv16i8 |
| 2216208755U, // SRHADDv2i32 |
| 69773683U, // SRHADDv4i16 |
| 70297971U, // SRHADDv4i32 |
| 2218305907U, // SRHADDv8i16 |
| 2218830195U, // SRHADDv8i8 |
| 637546101U, // SRI_ZZI_B |
| 2281721461U, // SRI_ZZI_D |
| 242773621U, // SRI_ZZI_H |
| 2315292277U, // SRI_ZZI_S |
| 2684448373U, // SRId |
| 336653941U, // SRIv16i8_shift |
| 2484661877U, // SRIv2i32_shift |
| 2485186165U, // SRIv2i64_shift |
| 338226805U, // SRIv4i16_shift |
| 338751093U, // SRIv4i32_shift |
| 2486759029U, // SRIv8i16_shift |
| 2487283317U, // SRIv8i8_shift |
| 369111972U, // SRSHLR_ZPmZ_B |
| 369120164U, // SRSHLR_ZPmZ_D |
| 2555933604U, // SRSHLR_ZPmZ_H |
| 369136548U, // SRSHLR_ZPmZ_S |
| 369110958U, // SRSHL_ZPmZ_B |
| 369119150U, // SRSHL_ZPmZ_D |
| 2555932590U, // SRSHL_ZPmZ_H |
| 369135534U, // SRSHL_ZPmZ_S |
| 68202414U, // SRSHLv16i8 |
| 2248200110U, // SRSHLv1i64 |
| 2216210350U, // SRSHLv2i32 |
| 2216734638U, // SRSHLv2i64 |
| 69775278U, // SRSHLv4i16 |
| 70299566U, // SRSHLv4i32 |
| 2218307502U, // SRSHLv8i16 |
| 2218831790U, // SRSHLv8i8 |
| 369111900U, // SRSHR_ZPmI_B |
| 369120092U, // SRSHR_ZPmI_D |
| 2555933532U, // SRSHR_ZPmI_H |
| 369136476U, // SRSHR_ZPmI_S |
| 2248201052U, // SRSHRd |
| 68203356U, // SRSHRv16i8_shift |
| 2216211292U, // SRSHRv2i32_shift |
| 2216735580U, // SRSHRv2i64_shift |
| 69776220U, // SRSHRv4i16_shift |
| 70300508U, // SRSHRv4i32_shift |
| 2218308444U, // SRSHRv8i16_shift |
| 2218832732U, // SRSHRv8i8_shift |
| 637543186U, // SRSRA_ZZI_B |
| 2281718546U, // SRSRA_ZZI_D |
| 242770706U, // SRSRA_ZZI_H |
| 2315289362U, // SRSRA_ZZI_S |
| 2684445458U, // SRSRAd |
| 336651026U, // SRSRAv16i8_shift |
| 2484658962U, // SRSRAv2i32_shift |
| 2485183250U, // SRSRAv2i64_shift |
| 338223890U, // SRSRAv4i16_shift |
| 338748178U, // SRSRAv4i32_shift |
| 2486756114U, // SRSRAv8i16_shift |
| 2487280402U, // SRSRAv8i8_shift |
| 2617263505U, // SSHLLB_ZZI_D |
| 2409129361U, // SSHLLB_ZZI_H |
| 2348844433U, // SSHLLB_ZZI_S |
| 2617267817U, // SSHLLT_ZZI_D |
| 2409133673U, // SSHLLT_ZZI_H |
| 2348848745U, // SSHLLT_ZZI_S |
| 70820093U, // SSHLLv16i8_shift |
| 2216734664U, // SSHLLv2i32_shift |
| 70299592U, // SSHLLv4i16_shift |
| 69247229U, // SSHLLv4i32_shift |
| 2217779453U, // SSHLLv8i16_shift |
| 2218307528U, // SSHLLv8i8_shift |
| 68202428U, // SSHLv16i8 |
| 2248200124U, // SSHLv1i64 |
| 2216210364U, // SSHLv2i32 |
| 2216734652U, // SSHLv2i64 |
| 69775292U, // SSHLv4i16 |
| 70299580U, // SSHLv4i32 |
| 2218307516U, // SSHLv8i16 |
| 2218831804U, // SSHLv8i8 |
| 2248201066U, // SSHRd |
| 68203370U, // SSHRv16i8_shift |
| 2216211306U, // SSHRv2i32_shift |
| 2216735594U, // SSHRv2i64_shift |
| 69776234U, // SSHRv4i16_shift |
| 70300522U, // SSHRv4i32_shift |
| 2218308458U, // SSHRv8i16_shift |
| 2218832746U, // SSHRv8i8_shift |
| 637543200U, // SSRA_ZZI_B |
| 2281718560U, // SSRA_ZZI_D |
| 242770720U, // SSRA_ZZI_H |
| 2315289376U, // SSRA_ZZI_S |
| 2684445472U, // SSRAd |
| 336651040U, // SSRAv16i8_shift |
| 2484658976U, // SSRAv2i32_shift |
| 2485183264U, // SSRAv2i64_shift |
| 338223904U, // SSRAv4i16_shift |
| 338748192U, // SSRAv4i32_shift |
| 2486756128U, // SSRAv8i16_shift |
| 2487280416U, // SSRAv8i8_shift |
| 2288649122U, // SST1B_D_IMM |
| 2691302306U, // SST1B_D_REAL |
| 2691302306U, // SST1B_D_SXTW |
| 2691302306U, // SST1B_D_UXTW |
| 2322211746U, // SST1B_S_IMM |
| 2691310498U, // SST1B_S_SXTW |
| 2691310498U, // SST1B_S_UXTW |
| 2288650464U, // SST1D_IMM |
| 2691303648U, // SST1D_REAL |
| 2691303648U, // SST1D_SCALED_SCALED_REAL |
| 2691303648U, // SST1D_SXTW |
| 2691303648U, // SST1D_SXTW_SCALED |
| 2691303648U, // SST1D_UXTW |
| 2691303648U, // SST1D_UXTW_SCALED |
| 2288651035U, // SST1H_D_IMM |
| 2691304219U, // SST1H_D_REAL |
| 2691304219U, // SST1H_D_SCALED_SCALED_REAL |
| 2691304219U, // SST1H_D_SXTW |
| 2691304219U, // SST1H_D_SXTW_SCALED |
| 2691304219U, // SST1H_D_UXTW |
| 2691304219U, // SST1H_D_UXTW_SCALED |
| 2322213659U, // SST1H_S_IMM |
| 2691312411U, // SST1H_S_SXTW |
| 2691312411U, // SST1H_S_SXTW_SCALED |
| 2691312411U, // SST1H_S_UXTW |
| 2691312411U, // SST1H_S_UXTW_SCALED |
| 2288654531U, // SST1W_D_IMM |
| 2691307715U, // SST1W_D_REAL |
| 2691307715U, // SST1W_D_SCALED_SCALED_REAL |
| 2691307715U, // SST1W_D_SXTW |
| 2691307715U, // SST1W_D_SXTW_SCALED |
| 2691307715U, // SST1W_D_UXTW |
| 2691307715U, // SST1W_D_UXTW_SCALED |
| 2322217155U, // SST1W_IMM |
| 2691315907U, // SST1W_SXTW |
| 2691315907U, // SST1W_SXTW_SCALED |
| 2691315907U, // SST1W_UXTW |
| 2691315907U, // SST1W_UXTW_SCALED |
| 2617267598U, // SSUBLBT_ZZZ_D |
| 261649806U, // SSUBLBT_ZZZ_H |
| 2348848526U, // SSUBLBT_ZZZ_S |
| 2617263434U, // SSUBLB_ZZZ_D |
| 261645642U, // SSUBLB_ZZZ_H |
| 2348844362U, // SSUBLB_ZZZ_S |
| 2617264081U, // SSUBLTB_ZZZ_D |
| 261646289U, // SSUBLTB_ZZZ_H |
| 2348845009U, // SSUBLTB_ZZZ_S |
| 2617267741U, // SSUBLT_ZZZ_D |
| 261649949U, // SSUBLT_ZZZ_H |
| 2348848669U, // SSUBLT_ZZZ_S |
| 70820045U, // SSUBLv16i8_v8i16 |
| 2216734518U, // SSUBLv2i32_v2i64 |
| 70299446U, // SSUBLv4i16_v4i32 |
| 69247181U, // SSUBLv4i32_v2i64 |
| 2217779405U, // SSUBLv8i16_v4i32 |
| 2218307382U, // SSUBLv8i8_v8i16 |
| 2415937586U, // SSUBWB_ZZZ_D |
| 241199154U, // SSUBWB_ZZZ_H |
| 2617280562U, // SSUBWB_ZZZ_S |
| 2415941539U, // SSUBWT_ZZZ_D |
| 241203107U, // SSUBWT_ZZZ_H |
| 2617284515U, // SSUBWT_ZZZ_S |
| 2218303982U, // SSUBWv16i8_v8i16 |
| 2216737013U, // SSUBWv2i32_v2i64 |
| 70301941U, // SSUBWv4i16_v4i32 |
| 2216731118U, // SSUBWv4i32_v2i64 |
| 70296046U, // SSUBWv8i16_v4i32 |
| 2218309877U, // SSUBWv8i8_v8i16 |
| 2691326882U, // ST1B |
| 2691302306U, // ST1B_D |
| 2691302306U, // ST1B_D_IMM |
| 2691335074U, // ST1B_H |
| 2691335074U, // ST1B_H_IMM |
| 2691326882U, // ST1B_IMM |
| 2691310498U, // ST1B_S |
| 2691310498U, // ST1B_S_IMM |
| 2691303648U, // ST1D |
| 2691303648U, // ST1D_IMM |
| 172102U, // ST1Fourv16b |
| 14860358U, // ST1Fourv16b_POST |
| 188486U, // ST1Fourv1d |
| 15401030U, // ST1Fourv1d_POST |
| 204870U, // ST1Fourv2d |
| 14893126U, // ST1Fourv2d_POST |
| 221254U, // ST1Fourv2s |
| 15433798U, // ST1Fourv2s_POST |
| 237638U, // ST1Fourv4h |
| 15450182U, // ST1Fourv4h_POST |
| 254022U, // ST1Fourv4s |
| 14942278U, // ST1Fourv4s_POST |
| 270406U, // ST1Fourv8b |
| 15482950U, // ST1Fourv8b_POST |
| 286790U, // ST1Fourv8h |
| 14975046U, // ST1Fourv8h_POST |
| 2691336987U, // ST1H |
| 2691304219U, // ST1H_D |
| 2691304219U, // ST1H_D_IMM |
| 2691336987U, // ST1H_IMM |
| 2691312411U, // ST1H_S |
| 2691312411U, // ST1H_S_IMM |
| 172102U, // ST1Onev16b |
| 15908934U, // ST1Onev16b_POST |
| 188486U, // ST1Onev1d |
| 16449606U, // ST1Onev1d_POST |
| 204870U, // ST1Onev2d |
| 15941702U, // ST1Onev2d_POST |
| 221254U, // ST1Onev2s |
| 16482374U, // ST1Onev2s_POST |
| 237638U, // ST1Onev4h |
| 16498758U, // ST1Onev4h_POST |
| 254022U, // ST1Onev4s |
| 15990854U, // ST1Onev4s_POST |
| 270406U, // ST1Onev8b |
| 16531526U, // ST1Onev8b_POST |
| 286790U, // ST1Onev8h |
| 16023622U, // ST1Onev8h_POST |
| 172102U, // ST1Threev16b |
| 18530374U, // ST1Threev16b_POST |
| 188486U, // ST1Threev1d |
| 19071046U, // ST1Threev1d_POST |
| 204870U, // ST1Threev2d |
| 18563142U, // ST1Threev2d_POST |
| 221254U, // ST1Threev2s |
| 19103814U, // ST1Threev2s_POST |
| 237638U, // ST1Threev4h |
| 19120198U, // ST1Threev4h_POST |
| 254022U, // ST1Threev4s |
| 18612294U, // ST1Threev4s_POST |
| 270406U, // ST1Threev8b |
| 19152966U, // ST1Threev8b_POST |
| 286790U, // ST1Threev8h |
| 18645062U, // ST1Threev8h_POST |
| 172102U, // ST1Twov16b |
| 15384646U, // ST1Twov16b_POST |
| 188486U, // ST1Twov1d |
| 15925318U, // ST1Twov1d_POST |
| 204870U, // ST1Twov2d |
| 15417414U, // ST1Twov2d_POST |
| 221254U, // ST1Twov2s |
| 15958086U, // ST1Twov2s_POST |
| 237638U, // ST1Twov4h |
| 15974470U, // ST1Twov4h_POST |
| 254022U, // ST1Twov4s |
| 15466566U, // ST1Twov4s_POST |
| 270406U, // ST1Twov8b |
| 16007238U, // ST1Twov8b_POST |
| 286790U, // ST1Twov8h |
| 15499334U, // ST1Twov8h_POST |
| 2691315907U, // ST1W |
| 2691307715U, // ST1W_D |
| 2691307715U, // ST1W_D_IMM |
| 2691315907U, // ST1W_IMM |
| 409670U, // ST1i16 |
| 1607770182U, // ST1i16_POST |
| 417862U, // ST1i32 |
| 1641340998U, // ST1i32_POST |
| 426054U, // ST1i64 |
| 1674911814U, // ST1i64_POST |
| 434246U, // ST1i8 |
| 1708482630U, // ST1i8_POST |
| 2691326911U, // ST2B |
| 2691326911U, // ST2B_IMM |
| 2691303660U, // ST2D |
| 2691303660U, // ST2D_IMM |
| 2255014563U, // ST2GOffset |
| 543779491U, // ST2GPostIndex |
| 2691263139U, // ST2GPreIndex |
| 2691337016U, // ST2H |
| 2691337016U, // ST2H_IMM |
| 172521U, // ST2Twov16b |
| 15385065U, // ST2Twov16b_POST |
| 205289U, // ST2Twov2d |
| 15417833U, // ST2Twov2d_POST |
| 221673U, // ST2Twov2s |
| 15958505U, // ST2Twov2s_POST |
| 238057U, // ST2Twov4h |
| 15974889U, // ST2Twov4h_POST |
| 254441U, // ST2Twov4s |
| 15466985U, // ST2Twov4s_POST |
| 270825U, // ST2Twov8b |
| 16007657U, // ST2Twov8b_POST |
| 287209U, // ST2Twov8h |
| 15499753U, // ST2Twov8h_POST |
| 2691315927U, // ST2W |
| 2691315927U, // ST2W_IMM |
| 410089U, // ST2i16 |
| 1641325033U, // ST2i16_POST |
| 418281U, // ST2i32 |
| 1674895849U, // ST2i32_POST |
| 426473U, // ST2i64 |
| 1742021097U, // ST2i64_POST |
| 434665U, // ST2i8 |
| 1607819753U, // ST2i8_POST |
| 2691326932U, // ST3B |
| 2691326932U, // ST3B_IMM |
| 2691303672U, // ST3D |
| 2691303672U, // ST3D_IMM |
| 2691337028U, // ST3H |
| 2691337028U, // ST3H_IMM |
| 172587U, // ST3Threev16b |
| 18530859U, // ST3Threev16b_POST |
| 205355U, // ST3Threev2d |
| 18563627U, // ST3Threev2d_POST |
| 221739U, // ST3Threev2s |
| 19104299U, // ST3Threev2s_POST |
| 238123U, // ST3Threev4h |
| 19120683U, // ST3Threev4h_POST |
| 254507U, // ST3Threev4s |
| 18612779U, // ST3Threev4s_POST |
| 270891U, // ST3Threev8b |
| 19153451U, // ST3Threev8b_POST |
| 287275U, // ST3Threev8h |
| 18645547U, // ST3Threev8h_POST |
| 2691315939U, // ST3W |
| 2691315939U, // ST3W_IMM |
| 410155U, // ST3i16 |
| 1775542827U, // ST3i16_POST |
| 418347U, // ST3i32 |
| 1809113643U, // ST3i32_POST |
| 426539U, // ST3i64 |
| 1842684459U, // ST3i64_POST |
| 434731U, // ST3i8 |
| 1876255275U, // ST3i8_POST |
| 2691326944U, // ST4B |
| 2691326944U, // ST4B_IMM |
| 2691303684U, // ST4D |
| 2691303684U, // ST4D_IMM |
| 172604U, // ST4Fourv16b |
| 14860860U, // ST4Fourv16b_POST |
| 205372U, // ST4Fourv2d |
| 14893628U, // ST4Fourv2d_POST |
| 221756U, // ST4Fourv2s |
| 15434300U, // ST4Fourv2s_POST |
| 238140U, // ST4Fourv4h |
| 15450684U, // ST4Fourv4h_POST |
| 254524U, // ST4Fourv4s |
| 14942780U, // ST4Fourv4s_POST |
| 270908U, // ST4Fourv8b |
| 15483452U, // ST4Fourv8b_POST |
| 287292U, // ST4Fourv8h |
| 14975548U, // ST4Fourv8h_POST |
| 2691337040U, // ST4H |
| 2691337040U, // ST4H_IMM |
| 2691315951U, // ST4W |
| 2691315951U, // ST4W_IMM |
| 410172U, // ST4i16 |
| 1674879548U, // ST4i16_POST |
| 418364U, // ST4i32 |
| 1742004796U, // ST4i32_POST |
| 426556U, // ST4i64 |
| 1909793340U, // ST4i64_POST |
| 434748U, // ST4i8 |
| 1641374268U, // ST4i8_POST |
| 2255016130U, // STGM |
| 2255014627U, // STGOffset |
| 100717079U, // STGPi |
| 543779555U, // STGPostIndex |
| 536965655U, // STGPpost |
| 536965655U, // STGPpre |
| 2691263203U, // STGPreIndex |
| 0U, // STGloop |
| 2255013612U, // STLLRB |
| 2255015216U, // STLLRH |
| 2255016884U, // STLLRW |
| 2255016884U, // STLLRX |
| 2255013620U, // STLRB |
| 2255015224U, // STLRH |
| 2255016897U, // STLRW |
| 2255016897U, // STLRX |
| 2255013670U, // STLURBi |
| 2255015274U, // STLURHi |
| 2255016994U, // STLURWi |
| 2255016994U, // STLURXi |
| 2248200911U, // STLXPW |
| 2248200911U, // STLXPX |
| 100714317U, // STLXRB |
| 100715921U, // STLXRH |
| 100717666U, // STLXRW |
| 100717666U, // STLXRX |
| 100717175U, // STNPDi |
| 100717175U, // STNPQi |
| 100717175U, // STNPSi |
| 100717175U, // STNPWi |
| 100717175U, // STNPXi |
| 2691326874U, // STNT1B_ZRI |
| 2691326874U, // STNT1B_ZRR |
| 2288649114U, // STNT1B_ZZR_D_REAL |
| 2322211738U, // STNT1B_ZZR_S_REAL |
| 2691303640U, // STNT1D_ZRI |
| 2691303640U, // STNT1D_ZRR |
| 2288650456U, // STNT1D_ZZR_D_REAL |
| 2691336979U, // STNT1H_ZRI |
| 2691336979U, // STNT1H_ZRR |
| 2288651027U, // STNT1H_ZZR_D_REAL |
| 2322213651U, // STNT1H_ZZR_S_REAL |
| 2691315899U, // STNT1W_ZRI |
| 2691315899U, // STNT1W_ZRR |
| 2288654523U, // STNT1W_ZZR_D_REAL |
| 2322217147U, // STNT1W_ZZR_S_REAL |
| 100717213U, // STPDi |
| 536965789U, // STPDpost |
| 536965789U, // STPDpre |
| 100717213U, // STPQi |
| 536965789U, // STPQpost |
| 536965789U, // STPQpre |
| 100717213U, // STPSi |
| 536965789U, // STPSpost |
| 536965789U, // STPSpre |
| 100717213U, // STPWi |
| 536965789U, // STPWpost |
| 536965789U, // STPWpre |
| 100717213U, // STPXi |
| 536965789U, // STPXpost |
| 536965789U, // STPXpre |
| 543778578U, // STRBBpost |
| 2691262226U, // STRBBpre |
| 2255013650U, // STRBBroW |
| 2255013650U, // STRBBroX |
| 2255013650U, // STRBBui |
| 543781899U, // STRBpost |
| 2691265547U, // STRBpre |
| 2255016971U, // STRBroW |
| 2255016971U, // STRBroX |
| 2255016971U, // STRBui |
| 543781899U, // STRDpost |
| 2691265547U, // STRDpre |
| 2255016971U, // STRDroW |
| 2255016971U, // STRDroX |
| 2255016971U, // STRDui |
| 543780182U, // STRHHpost |
| 2691263830U, // STRHHpre |
| 2255015254U, // STRHHroW |
| 2255015254U, // STRHHroX |
| 2255015254U, // STRHHui |
| 543781899U, // STRHpost |
| 2691265547U, // STRHpre |
| 2255016971U, // STRHroW |
| 2255016971U, // STRHroX |
| 2255016971U, // STRHui |
| 543781899U, // STRQpost |
| 2691265547U, // STRQpre |
| 2255016971U, // STRQroW |
| 2255016971U, // STRQroX |
| 2255016971U, // STRQui |
| 543781899U, // STRSpost |
| 2691265547U, // STRSpre |
| 2255016971U, // STRSroW |
| 2255016971U, // STRSroX |
| 2255016971U, // STRSui |
| 543781899U, // STRWpost |
| 2691265547U, // STRWpre |
| 2255016971U, // STRWroW |
| 2255016971U, // STRWroX |
| 2255016971U, // STRWui |
| 543781899U, // STRXpost |
| 2691265547U, // STRXpre |
| 2255016971U, // STRXroW |
| 2255016971U, // STRXroX |
| 2255016971U, // STRXui |
| 2255336459U, // STR_PXI |
| 2255336459U, // STR_ZXI |
| 2255013656U, // STTRBi |
| 2255015260U, // STTRHi |
| 2255016976U, // STTRWi |
| 2255016976U, // STTRXi |
| 2255013687U, // STURBBi |
| 2255017009U, // STURBi |
| 2255017009U, // STURDi |
| 2255015291U, // STURHHi |
| 2255017009U, // STURHi |
| 2255017009U, // STURQi |
| 2255017009U, // STURSi |
| 2255017009U, // STURWi |
| 2255017009U, // STURXi |
| 2248200918U, // STXPW |
| 2248200918U, // STXPX |
| 100714325U, // STXRB |
| 100715929U, // STXRH |
| 100717673U, // STXRW |
| 100717673U, // STXRX |
| 2255014569U, // STZ2GOffset |
| 543779497U, // STZ2GPostIndex |
| 2691263145U, // STZ2GPreIndex |
| 2255016136U, // STZGM |
| 2255014632U, // STZGOffset |
| 543779560U, // STZGPostIndex |
| 2691263208U, // STZGPreIndex |
| 0U, // STZGloop |
| 2248198832U, // SUBG |
| 2348820028U, // SUBHNB_ZZZ_B |
| 239625788U, // SUBHNB_ZZZ_H |
| 2415953468U, // SUBHNB_ZZZ_S |
| 2449487581U, // SUBHNT_ZZZ_B |
| 240154333U, // SUBHNT_ZZZ_H |
| 2281739997U, // SUBHNT_ZZZ_S |
| 2216210691U, // SUBHNv2i64_v2i32 |
| 2486231386U, // SUBHNv2i64_v4i32 |
| 69775619U, // SUBHNv4i32_v4i16 |
| 339272026U, // SUBHNv4i32_v8i16 |
| 2484134234U, // SUBHNv8i16_v16i8 |
| 2218832131U, // SUBHNv8i16_v8i8 |
| 2248200671U, // SUBP |
| 2248201518U, // SUBPS |
| 2583704350U, // SUBR_ZI_B |
| 2415940382U, // SUBR_ZI_D |
| 241201950U, // SUBR_ZI_H |
| 2617283358U, // SUBR_ZI_S |
| 369111838U, // SUBR_ZPmZ_B |
| 369120030U, // SUBR_ZPmZ_D |
| 2555933470U, // SUBR_ZPmZ_H |
| 369136414U, // SUBR_ZPmZ_S |
| 2248201383U, // SUBSWri |
| 0U, // SUBSWrr |
| 2248201383U, // SUBSWrs |
| 2248201383U, // SUBSWrx |
| 2248201383U, // SUBSXri |
| 0U, // SUBSXrr |
| 2248201383U, // SUBSXrs |
| 2248201383U, // SUBSXrx |
| 2248201383U, // SUBSXrx64 |
| 2248198140U, // SUBWri |
| 0U, // SUBWrr |
| 2248198140U, // SUBWrs |
| 2248198140U, // SUBWrx |
| 2248198140U, // SUBXri |
| 0U, // SUBXrr |
| 2248198140U, // SUBXrs |
| 2248198140U, // SUBXrx |
| 2248198140U, // SUBXrx64 |
| 2583701500U, // SUB_ZI_B |
| 2415937532U, // SUB_ZI_D |
| 241199100U, // SUB_ZI_H |
| 2617280508U, // SUB_ZI_S |
| 369108988U, // SUB_ZPmZ_B |
| 369117180U, // SUB_ZPmZ_D |
| 2555930620U, // SUB_ZPmZ_H |
| 369133564U, // SUB_ZPmZ_S |
| 2583701500U, // SUB_ZZZ_B |
| 2415937532U, // SUB_ZZZ_D |
| 2388682748U, // SUB_ZZZ_H |
| 2617280508U, // SUB_ZZZ_S |
| 68200444U, // SUBv16i8 |
| 2248198140U, // SUBv1i64 |
| 2216208380U, // SUBv2i32 |
| 2216732668U, // SUBv2i64 |
| 69773308U, // SUBv4i16 |
| 70297596U, // SUBv4i32 |
| 2218305532U, // SUBv8i16 |
| 2218829820U, // SUBv8i8 |
| 469782086U, // SUNPKHI_ZZ_D |
| 865627718U, // SUNPKHI_ZZ_H |
| 201363014U, // SUNPKHI_ZZ_S |
| 469782968U, // SUNPKLO_ZZ_D |
| 865628600U, // SUNPKLO_ZZ_H |
| 201363896U, // SUNPKLO_ZZ_S |
| 369109416U, // SUQADD_ZPmZ_B |
| 369117608U, // SUQADD_ZPmZ_D |
| 2555931048U, // SUQADD_ZPmZ_H |
| 369133992U, // SUQADD_ZPmZ_S |
| 2484136360U, // SUQADDv16i8 |
| 536963496U, // SUQADDv1i16 |
| 536963496U, // SUQADDv1i32 |
| 536963496U, // SUQADDv1i64 |
| 536963496U, // SUQADDv1i8 |
| 2484660648U, // SUQADDv2i32 |
| 337701288U, // SUQADDv2i64 |
| 2485709224U, // SUQADDv4i16 |
| 338749864U, // SUQADDv4i32 |
| 2486757800U, // SUQADDv8i16 |
| 339798440U, // SUQADDv8i8 |
| 75957U, // SVC |
| 1241605123U, // SWPAB |
| 1241607057U, // SWPAH |
| 1241605382U, // SWPALB |
| 1241607213U, // SWPALH |
| 1241607908U, // SWPALW |
| 1241607908U, // SWPALX |
| 1241604853U, // SWPAW |
| 1241604853U, // SWPAX |
| 1241605818U, // SWPB |
| 1241607422U, // SWPH |
| 1241605591U, // SWPLB |
| 1241607310U, // SWPLH |
| 1241608212U, // SWPLW |
| 1241608212U, // SWPLX |
| 1241608872U, // SWPW |
| 1241608872U, // SWPX |
| 2147502063U, // SXTB_ZPmZ_D |
| 34105327U, // SXTB_ZPmZ_H |
| 34799U, // SXTB_ZPmZ_S |
| 2147503625U, // SXTH_ZPmZ_D |
| 36361U, // SXTH_ZPmZ_S |
| 2147506608U, // SXTW_ZPmZ_D |
| 2248200276U, // SYSLxt |
| 1912657261U, // SYSxt |
| 0U, // SpeculationSafeValueW |
| 0U, // SpeculationSafeValueX |
| 0U, // TAGPstack |
| 1040199457U, // TBL_ZZZZ_B |
| 1946177313U, // TBL_ZZZZ_D |
| 30961441U, // TBL_ZZZZ_H |
| 1979748129U, // TBL_ZZZZ_S |
| 1040199457U, // TBL_ZZZ_B |
| 1946177313U, // TBL_ZZZ_D |
| 30961441U, // TBL_ZZZ_H |
| 1979748129U, // TBL_ZZZ_S |
| 4161842977U, // TBLv16i8Four |
| 4161842977U, // TBLv16i8One |
| 4161842977U, // TBLv16i8Three |
| 4161842977U, // TBLv16i8Two |
| 2017505057U, // TBLv8i8Four |
| 2017505057U, // TBLv8i8One |
| 2017505057U, // TBLv8i8Three |
| 2017505057U, // TBLv8i8Two |
| 2248202899U, // TBNZW |
| 2248202899U, // TBNZX |
| 637549050U, // TBX_ZZZ_B |
| 2281724410U, // TBX_ZZZ_D |
| 2390260218U, // TBX_ZZZ_H |
| 2315295226U, // TBX_ZZZ_S |
| 4195416570U, // TBXv16i8Four |
| 4195416570U, // TBXv16i8One |
| 4195416570U, // TBXv16i8Three |
| 4195416570U, // TBXv16i8Two |
| 2051078650U, // TBXv8i8Four |
| 2051078650U, // TBXv8i8One |
| 2051078650U, // TBXv8i8Three |
| 2051078650U, // TBXv8i8Two |
| 2248202883U, // TBZW |
| 2248202883U, // TBZX |
| 77688U, // TCANCEL |
| 7220U, // TCOMMIT |
| 0U, // TCRETURNdi |
| 0U, // TCRETURNri |
| 0U, // TCRETURNriALL |
| 0U, // TCRETURNriBTI |
| 7396007U, // TLSDESCCALL |
| 0U, // TLSDESC_CALLSEQ |
| 2583699493U, // TRN1_PPP_B |
| 2415935525U, // TRN1_PPP_D |
| 2388680741U, // TRN1_PPP_H |
| 2617278501U, // TRN1_PPP_S |
| 2583699493U, // TRN1_ZZZ_B |
| 2415935525U, // TRN1_ZZZ_D |
| 2388680741U, // TRN1_ZZZ_H |
| 2617278501U, // TRN1_ZZZ_S |
| 68198437U, // TRN1v16i8 |
| 2216206373U, // TRN1v2i32 |
| 2216730661U, // TRN1v2i64 |
| 69771301U, // TRN1v4i16 |
| 70295589U, // TRN1v4i32 |
| 2218303525U, // TRN1v8i16 |
| 2218827813U, // TRN1v8i8 |
| 2583699857U, // TRN2_PPP_B |
| 2415935889U, // TRN2_PPP_D |
| 2388681105U, // TRN2_PPP_H |
| 2617278865U, // TRN2_PPP_S |
| 2583699857U, // TRN2_ZZZ_B |
| 2415935889U, // TRN2_ZZZ_D |
| 2388681105U, // TRN2_ZZZ_H |
| 2617278865U, // TRN2_ZZZ_S |
| 68198801U, // TRN2v16i8 |
| 2216206737U, // TRN2v2i32 |
| 2216731025U, // TRN2v2i64 |
| 69771665U, // TRN2v4i16 |
| 70295953U, // TRN2v4i32 |
| 2218303889U, // TRN2v8i16 |
| 2218828177U, // TRN2v8i8 |
| 116676U, // TSB |
| 7395185U, // TSTART |
| 7395207U, // TTEST |
| 2315273404U, // UABALB_ZZZ_D |
| 29385916U, // UABALB_ZZZ_H |
| 2449507516U, // UABALB_ZZZ_S |
| 2315277811U, // UABALT_ZZZ_D |
| 29390323U, // UABALT_ZZZ_H |
| 2449511923U, // UABALT_ZZZ_S |
| 339271843U, // UABALv16i8_v8i16 |
| 2485186202U, // UABALv2i32_v2i64 |
| 338751130U, // UABALv4i16_v4i32 |
| 337698979U, // UABALv4i32_v2i64 |
| 2486231203U, // UABALv8i16_v4i32 |
| 2486759066U, // UABALv8i8_v8i16 |
| 637543043U, // UABA_ZZZ_B |
| 2281718403U, // UABA_ZZZ_D |
| 2390254211U, // UABA_ZZZ_H |
| 2315289219U, // UABA_ZZZ_S |
| 336650883U, // UABAv16i8 |
| 2484658819U, // UABAv2i32 |
| 338223747U, // UABAv4i16 |
| 338748035U, // UABAv4i32 |
| 2486755971U, // UABAv8i16 |
| 2487280259U, // UABAv8i8 |
| 2617263472U, // UABDLB_ZZZ_D |
| 261645680U, // UABDLB_ZZZ_H |
| 2348844400U, // UABDLB_ZZZ_S |
| 2617267779U, // UABDLT_ZZZ_D |
| 261649987U, // UABDLT_ZZZ_H |
| 2348848707U, // UABDLT_ZZZ_S |
| 70820069U, // UABDLv16i8_v8i16 |
| 2216734539U, // UABDLv2i32_v2i64 |
| 70299467U, // UABDLv4i16_v4i32 |
| 69247205U, // UABDLv4i32_v2i64 |
| 2217779429U, // UABDLv8i16_v4i32 |
| 2218307403U, // UABDLv8i8_v8i16 |
| 369109290U, // UABD_ZPmZ_B |
| 369117482U, // UABD_ZPmZ_D |
| 2555930922U, // UABD_ZPmZ_H |
| 369133866U, // UABD_ZPmZ_S |
| 68200746U, // UABDv16i8 |
| 2216208682U, // UABDv2i32 |
| 69773610U, // UABDv4i16 |
| 70297898U, // UABDv4i32 |
| 2218305834U, // UABDv8i16 |
| 2218830122U, // UABDv8i8 |
| 369119781U, // UADALP_ZPmZ_D |
| 408449573U, // UADALP_ZPmZ_H |
| 369136165U, // UADALP_ZPmZ_S |
| 2486759973U, // UADALPv16i8_v8i16 |
| 2512974373U, // UADALPv2i32_v1i64 |
| 2484662821U, // UADALPv4i16_v2i32 |
| 337703461U, // UADALPv4i32_v2i64 |
| 2486235685U, // UADALPv8i16_v4i32 |
| 338227749U, // UADALPv8i8_v4i16 |
| 2617263497U, // UADDLB_ZZZ_D |
| 261645705U, // UADDLB_ZZZ_H |
| 2348844425U, // UADDLB_ZZZ_S |
| 2218308149U, // UADDLPv16i8_v8i16 |
| 2244522549U, // UADDLPv2i32_v1i64 |
| 2216210997U, // UADDLPv4i16_v2i32 |
| 69251637U, // UADDLPv4i32_v2i64 |
| 2217783861U, // UADDLPv8i16_v4i32 |
| 69775925U, // UADDLPv8i8_v4i16 |
| 2617267795U, // UADDLT_ZZZ_D |
| 261650003U, // UADDLT_ZZZ_H |
| 2348848723U, // UADDLT_ZZZ_S |
| 2214647866U, // UADDLVv16i8v |
| 2214647866U, // UADDLVv4i16v |
| 67164218U, // UADDLVv4i32v |
| 2214647866U, // UADDLVv8i16v |
| 67164218U, // UADDLVv8i8v |
| 70820085U, // UADDLv16i8_v8i16 |
| 2216734577U, // UADDLv2i32_v2i64 |
| 70299505U, // UADDLv4i16_v4i32 |
| 69247221U, // UADDLv4i32_v2i64 |
| 2217779445U, // UADDLv8i16_v4i32 |
| 2218307441U, // UADDLv8i8_v8i16 |
| 2516637710U, // UADDV_VPZ_B |
| 2516637710U, // UADDV_VPZ_D |
| 2516637710U, // UADDV_VPZ_H |
| 2516637710U, // UADDV_VPZ_S |
| 2415937610U, // UADDWB_ZZZ_D |
| 241199178U, // UADDWB_ZZZ_H |
| 2617280586U, // UADDWB_ZZZ_S |
| 2415941563U, // UADDWT_ZZZ_D |
| 241203131U, // UADDWT_ZZZ_H |
| 2617284539U, // UADDWT_ZZZ_S |
| 2218304006U, // UADDWv16i8_v8i16 |
| 2216737075U, // UADDWv2i32_v2i64 |
| 70302003U, // UADDWv4i16_v4i32 |
| 2216731142U, // UADDWv4i32_v2i64 |
| 70296070U, // UADDWv8i16_v4i32 |
| 2218309939U, // UADDWv8i8_v8i16 |
| 2248200368U, // UBFMWri |
| 2248200368U, // UBFMXri |
| 2248198812U, // UCVTFSWDri |
| 2248198812U, // UCVTFSWHri |
| 2248198812U, // UCVTFSWSri |
| 2248198812U, // UCVTFSXDri |
| 2248198812U, // UCVTFSXHri |
| 2248198812U, // UCVTFSXSri |
| 100715164U, // UCVTFUWDri |
| 100715164U, // UCVTFUWHri |
| 100715164U, // UCVTFUWSri |
| 100715164U, // UCVTFUXDri |
| 100715164U, // UCVTFUXHri |
| 100715164U, // UCVTFUXSri |
| 2147502748U, // UCVTF_ZPmZ_DtoD |
| 1141402268U, // UCVTF_ZPmZ_DtoH |
| 2147519132U, // UCVTF_ZPmZ_DtoS |
| 34106012U, // UCVTF_ZPmZ_HtoH |
| 19100U, // UCVTF_ZPmZ_StoD |
| 1107847836U, // UCVTF_ZPmZ_StoH |
| 35484U, // UCVTF_ZPmZ_StoS |
| 2248198812U, // UCVTFd |
| 2248198812U, // UCVTFh |
| 2248198812U, // UCVTFs |
| 100715164U, // UCVTFv1i16 |
| 100715164U, // UCVTFv1i32 |
| 100715164U, // UCVTFv1i64 |
| 2216209052U, // UCVTFv2f32 |
| 69249692U, // UCVTFv2f64 |
| 2216209052U, // UCVTFv2i32_shift |
| 2216733340U, // UCVTFv2i64_shift |
| 2217257628U, // UCVTFv4f16 |
| 70298268U, // UCVTFv4f32 |
| 69773980U, // UCVTFv4i16_shift |
| 70298268U, // UCVTFv4i32_shift |
| 2218306204U, // UCVTFv8f16 |
| 2218306204U, // UCVTFv8i16_shift |
| 7391877U, // UDF |
| 369120325U, // UDIVR_ZPmZ_D |
| 369136709U, // UDIVR_ZPmZ_S |
| 2248202284U, // UDIVWr |
| 2248202284U, // UDIVXr |
| 369121324U, // UDIV_ZPmZ_D |
| 369137708U, // UDIV_ZPmZ_S |
| 2449495909U, // UDOT_ZZZI_D |
| 637572965U, // UDOT_ZZZI_S |
| 2449495909U, // UDOT_ZZZ_D |
| 637572965U, // UDOT_ZZZ_S |
| 338753381U, // UDOTlanev16i8 |
| 2484664165U, // UDOTlanev8i8 |
| 338753381U, // UDOTv16i8 |
| 2484664165U, // UDOTv8i8 |
| 369109386U, // UHADD_ZPmZ_B |
| 369117578U, // UHADD_ZPmZ_D |
| 2555931018U, // UHADD_ZPmZ_H |
| 369133962U, // UHADD_ZPmZ_S |
| 68200842U, // UHADDv16i8 |
| 2216208778U, // UHADDv2i32 |
| 69773706U, // UHADDv4i16 |
| 70297994U, // UHADDv4i32 |
| 2218305930U, // UHADDv8i16 |
| 2218830218U, // UHADDv8i8 |
| 369111852U, // UHSUBR_ZPmZ_B |
| 369120044U, // UHSUBR_ZPmZ_D |
| 2555933484U, // UHSUBR_ZPmZ_H |
| 369136428U, // UHSUBR_ZPmZ_S |
| 369109000U, // UHSUB_ZPmZ_B |
| 369117192U, // UHSUB_ZPmZ_D |
| 2555930632U, // UHSUB_ZPmZ_H |
| 369133576U, // UHSUB_ZPmZ_S |
| 68200456U, // UHSUBv16i8 |
| 2216208392U, // UHSUBv2i32 |
| 69773320U, // UHSUBv4i16 |
| 70297608U, // UHSUBv4i32 |
| 2218305544U, // UHSUBv8i16 |
| 2218829832U, // UHSUBv8i8 |
| 2248200034U, // UMADDLrrr |
| 369111746U, // UMAXP_ZPmZ_B |
| 369119938U, // UMAXP_ZPmZ_D |
| 2555933378U, // UMAXP_ZPmZ_H |
| 369136322U, // UMAXP_ZPmZ_S |
| 68203202U, // UMAXPv16i8 |
| 2216211138U, // UMAXPv2i32 |
| 69776066U, // UMAXPv4i16 |
| 70300354U, // UMAXPv4i32 |
| 2218308290U, // UMAXPv8i16 |
| 2218832578U, // UMAXPv8i8 |
| 2516637846U, // UMAXV_VPZ_B |
| 2516637846U, // UMAXV_VPZ_D |
| 2516637846U, // UMAXV_VPZ_H |
| 2516637846U, // UMAXV_VPZ_S |
| 2214647958U, // UMAXVv16i8v |
| 2214647958U, // UMAXVv4i16v |
| 67164310U, // UMAXVv4i32v |
| 2214647958U, // UMAXVv8i16v |
| 67164310U, // UMAXVv8i8v |
| 2583706100U, // UMAX_ZI_B |
| 2415942132U, // UMAX_ZI_D |
| 2388687348U, // UMAX_ZI_H |
| 2617285108U, // UMAX_ZI_S |
| 369113588U, // UMAX_ZPmZ_B |
| 369121780U, // UMAX_ZPmZ_D |
| 2555935220U, // UMAX_ZPmZ_H |
| 369138164U, // UMAX_ZPmZ_S |
| 68205044U, // UMAXv16i8 |
| 2216212980U, // UMAXv2i32 |
| 69777908U, // UMAXv4i16 |
| 70302196U, // UMAXv4i32 |
| 2218310132U, // UMAXv8i16 |
| 2218834420U, // UMAXv8i8 |
| 369111664U, // UMINP_ZPmZ_B |
| 369119856U, // UMINP_ZPmZ_D |
| 2555933296U, // UMINP_ZPmZ_H |
| 369136240U, // UMINP_ZPmZ_S |
| 68203120U, // UMINPv16i8 |
| 2216211056U, // UMINPv2i32 |
| 69775984U, // UMINPv4i16 |
| 70300272U, // UMINPv4i32 |
| 2218308208U, // UMINPv8i16 |
| 2218832496U, // UMINPv8i8 |
| 2516637794U, // UMINV_VPZ_B |
| 2516637794U, // UMINV_VPZ_D |
| 2516637794U, // UMINV_VPZ_H |
| 2516637794U, // UMINV_VPZ_S |
| 2214647906U, // UMINVv16i8v |
| 2214647906U, // UMINVv4i16v |
| 67164258U, // UMINVv4i32v |
| 2214647906U, // UMINVv8i16v |
| 67164258U, // UMINVv8i8v |
| 2583703842U, // UMIN_ZI_B |
| 2415939874U, // UMIN_ZI_D |
| 2388685090U, // UMIN_ZI_H |
| 2617282850U, // UMIN_ZI_S |
| 369111330U, // UMIN_ZPmZ_B |
| 369119522U, // UMIN_ZPmZ_D |
| 2555932962U, // UMIN_ZPmZ_H |
| 369135906U, // UMIN_ZPmZ_S |
| 68202786U, // UMINv16i8 |
| 2216210722U, // UMINv2i32 |
| 69775650U, // UMINv4i16 |
| 70299938U, // UMINv4i32 |
| 2218307874U, // UMINv8i16 |
| 2218832162U, // UMINv8i8 |
| 2315273448U, // UMLALB_ZZZI_D |
| 2449507560U, // UMLALB_ZZZI_S |
| 2315273448U, // UMLALB_ZZZ_D |
| 29385960U, // UMLALB_ZZZ_H |
| 2449507560U, // UMLALB_ZZZ_S |
| 2315277845U, // UMLALT_ZZZI_D |
| 2449511957U, // UMLALT_ZZZI_S |
| 2315277845U, // UMLALT_ZZZ_D |
| 29390357U, // UMLALT_ZZZ_H |
| 2449511957U, // UMLALT_ZZZ_S |
| 339271877U, // UMLALv16i8_v8i16 |
| 2485186241U, // UMLALv2i32_indexed |
| 2485186241U, // UMLALv2i32_v2i64 |
| 338751169U, // UMLALv4i16_indexed |
| 338751169U, // UMLALv4i16_v4i32 |
| 337699013U, // UMLALv4i32_indexed |
| 337699013U, // UMLALv4i32_v2i64 |
| 2486231237U, // UMLALv8i16_indexed |
| 2486231237U, // UMLALv8i16_v4i32 |
| 2486759105U, // UMLALv8i8_v8i16 |
| 2315273745U, // UMLSLB_ZZZI_D |
| 2449507857U, // UMLSLB_ZZZI_S |
| 2315273745U, // UMLSLB_ZZZ_D |
| 29386257U, // UMLSLB_ZZZ_H |
| 2449507857U, // UMLSLB_ZZZ_S |
| 2315278019U, // UMLSLT_ZZZI_D |
| 2449512131U, // UMLSLT_ZZZI_S |
| 2315278019U, // UMLSLT_ZZZ_D |
| 29390531U, // UMLSLT_ZZZ_H |
| 2449512131U, // UMLSLT_ZZZ_S |
| 339272009U, // UMLSLv16i8_v8i16 |
| 2485186637U, // UMLSLv2i32_indexed |
| 2485186637U, // UMLSLv2i32_v2i64 |
| 338751565U, // UMLSLv4i16_indexed |
| 338751565U, // UMLSLv4i16_v4i32 |
| 337699145U, // UMLSLv4i32_indexed |
| 337699145U, // UMLSLv4i32_v2i64 |
| 2486231369U, // UMLSLv8i16_indexed |
| 2486231369U, // UMLSLv8i16_v4i32 |
| 2486759501U, // UMLSLv8i8_v8i16 |
| 67164284U, // UMOVvi16 |
| 2214647932U, // UMOVvi32 |
| 67164284U, // UMOVvi64 |
| 2214647932U, // UMOVvi8 |
| 2248199982U, // UMSUBLrrr |
| 369110225U, // UMULH_ZPmZ_B |
| 369118417U, // UMULH_ZPmZ_D |
| 2555931857U, // UMULH_ZPmZ_H |
| 369134801U, // UMULH_ZPmZ_S |
| 2583702737U, // UMULH_ZZZ_B |
| 2415938769U, // UMULH_ZZZ_D |
| 2388683985U, // UMULH_ZZZ_H |
| 2617281745U, // UMULH_ZZZ_S |
| 2248199377U, // UMULHrr |
| 2617263547U, // UMULLB_ZZZI_D |
| 2348844475U, // UMULLB_ZZZI_S |
| 2617263547U, // UMULLB_ZZZ_D |
| 261645755U, // UMULLB_ZZZ_H |
| 2348844475U, // UMULLB_ZZZ_S |
| 2617267859U, // UMULLT_ZZZI_D |
| 2348848787U, // UMULLT_ZZZI_S |
| 2617267859U, // UMULLT_ZZZ_D |
| 261650067U, // UMULLT_ZZZ_H |
| 2348848787U, // UMULLT_ZZZ_S |
| 70820135U, // UMULLv16i8_v8i16 |
| 2216734701U, // UMULLv2i32_indexed |
| 2216734701U, // UMULLv2i32_v2i64 |
| 70299629U, // UMULLv4i16_indexed |
| 70299629U, // UMULLv4i16_v4i32 |
| 69247271U, // UMULLv4i32_indexed |
| 69247271U, // UMULLv4i32_v2i64 |
| 2217779495U, // UMULLv8i16_indexed |
| 2217779495U, // UMULLv8i16_v4i32 |
| 2218307565U, // UMULLv8i8_v8i16 |
| 2583701929U, // UQADD_ZI_B |
| 2415937961U, // UQADD_ZI_D |
| 241199529U, // UQADD_ZI_H |
| 2617280937U, // UQADD_ZI_S |
| 369109417U, // UQADD_ZPmZ_B |
| 369117609U, // UQADD_ZPmZ_D |
| 2555931049U, // UQADD_ZPmZ_H |
| 369133993U, // UQADD_ZPmZ_S |
| 2583701929U, // UQADD_ZZZ_B |
| 2415937961U, // UQADD_ZZZ_D |
| 2388683177U, // UQADD_ZZZ_H |
| 2617280937U, // UQADD_ZZZ_S |
| 68200873U, // UQADDv16i8 |
| 2248198569U, // UQADDv1i16 |
| 2248198569U, // UQADDv1i32 |
| 2248198569U, // UQADDv1i64 |
| 2248198569U, // UQADDv1i8 |
| 2216208809U, // UQADDv2i32 |
| 2216733097U, // UQADDv2i64 |
| 69773737U, // UQADDv4i16 |
| 70298025U, // UQADDv4i32 |
| 2218305961U, // UQADDv8i16 |
| 2218830249U, // UQADDv8i8 |
| 805356645U, // UQDECB_WPiI |
| 805356645U, // UQDECB_XPiI |
| 805357887U, // UQDECD_WPiI |
| 805357887U, // UQDECD_XPiI |
| 805325119U, // UQDECD_ZPiI |
| 805358559U, // UQDECH_WPiI |
| 805358559U, // UQDECH_XPiI |
| 8416223U, // UQDECH_ZPiI |
| 436261357U, // UQDECP_WP_B |
| 268489197U, // UQDECP_WP_D |
| 201380333U, // UQDECP_WP_H |
| 469815789U, // UQDECP_WP_S |
| 436261357U, // UQDECP_XP_B |
| 268489197U, // UQDECP_XP_D |
| 201380333U, // UQDECP_XP_H |
| 469815789U, // UQDECP_XP_S |
| 134238701U, // UQDECP_ZP_D |
| 846754285U, // UQDECP_ZP_H |
| 167809517U, // UQDECP_ZP_S |
| 805361940U, // UQDECW_WPiI |
| 805361940U, // UQDECW_XPiI |
| 805345556U, // UQDECW_ZPiI |
| 805356661U, // UQINCB_WPiI |
| 805356661U, // UQINCB_XPiI |
| 805357903U, // UQINCD_WPiI |
| 805357903U, // UQINCD_XPiI |
| 805325135U, // UQINCD_ZPiI |
| 805358575U, // UQINCH_WPiI |
| 805358575U, // UQINCH_XPiI |
| 8416239U, // UQINCH_ZPiI |
| 436261373U, // UQINCP_WP_B |
| 268489213U, // UQINCP_WP_D |
| 201380349U, // UQINCP_WP_H |
| 469815805U, // UQINCP_WP_S |
| 436261373U, // UQINCP_XP_B |
| 268489213U, // UQINCP_XP_D |
| 201380349U, // UQINCP_XP_H |
| 469815805U, // UQINCP_XP_S |
| 134238717U, // UQINCP_ZP_D |
| 846754301U, // UQINCP_ZP_H |
| 167809533U, // UQINCP_ZP_S |
| 805361956U, // UQINCW_WPiI |
| 805361956U, // UQINCW_XPiI |
| 805345572U, // UQINCW_ZPiI |
| 369111963U, // UQRSHLR_ZPmZ_B |
| 369120155U, // UQRSHLR_ZPmZ_D |
| 2555933595U, // UQRSHLR_ZPmZ_H |
| 369136539U, // UQRSHLR_ZPmZ_S |
| 369110950U, // UQRSHL_ZPmZ_B |
| 369119142U, // UQRSHL_ZPmZ_D |
| 2555932582U, // UQRSHL_ZPmZ_H |
| 369135526U, // UQRSHL_ZPmZ_S |
| 68202406U, // UQRSHLv16i8 |
| 2248200102U, // UQRSHLv1i16 |
| 2248200102U, // UQRSHLv1i32 |
| 2248200102U, // UQRSHLv1i64 |
| 2248200102U, // UQRSHLv1i8 |
| 2216210342U, // UQRSHLv2i32 |
| 2216734630U, // UQRSHLv2i64 |
| 69775270U, // UQRSHLv4i16 |
| 70299558U, // UQRSHLv4i32 |
| 2218307494U, // UQRSHLv8i16 |
| 2218831782U, // UQRSHLv8i8 |
| 2348820091U, // UQRSHRNB_ZZI_B |
| 2387109499U, // UQRSHRNB_ZZI_H |
| 2415953531U, // UQRSHRNB_ZZI_S |
| 2449487632U, // UQRSHRNT_ZZI_B |
| 240154384U, // UQRSHRNT_ZZI_H |
| 2281740048U, // UQRSHRNT_ZZI_S |
| 2248200530U, // UQRSHRNb |
| 2248200530U, // UQRSHRNh |
| 2248200530U, // UQRSHRNs |
| 2484134279U, // UQRSHRNv16i8_shift |
| 2216210770U, // UQRSHRNv2i32_shift |
| 69775698U, // UQRSHRNv4i16_shift |
| 2486231431U, // UQRSHRNv4i32_shift |
| 339272071U, // UQRSHRNv8i16_shift |
| 2218832210U, // UQRSHRNv8i8_shift |
| 369111946U, // UQSHLR_ZPmZ_B |
| 369120138U, // UQSHLR_ZPmZ_D |
| 2555933578U, // UQSHLR_ZPmZ_H |
| 369136522U, // UQSHLR_ZPmZ_S |
| 369110935U, // UQSHL_ZPmI_B |
| 369119127U, // UQSHL_ZPmI_D |
| 2555932567U, // UQSHL_ZPmI_H |
| 369135511U, // UQSHL_ZPmI_S |
| 369110935U, // UQSHL_ZPmZ_B |
| 369119127U, // UQSHL_ZPmZ_D |
| 2555932567U, // UQSHL_ZPmZ_H |
| 369135511U, // UQSHL_ZPmZ_S |
| 2248200087U, // UQSHLb |
| 2248200087U, // UQSHLd |
| 2248200087U, // UQSHLh |
| 2248200087U, // UQSHLs |
| 68202391U, // UQSHLv16i8 |
| 68202391U, // UQSHLv16i8_shift |
| 2248200087U, // UQSHLv1i16 |
| 2248200087U, // UQSHLv1i32 |
| 2248200087U, // UQSHLv1i64 |
| 2248200087U, // UQSHLv1i8 |
| 2216210327U, // UQSHLv2i32 |
| 2216210327U, // UQSHLv2i32_shift |
| 2216734615U, // UQSHLv2i64 |
| 2216734615U, // UQSHLv2i64_shift |
| 69775255U, // UQSHLv4i16 |
| 69775255U, // UQSHLv4i16_shift |
| 70299543U, // UQSHLv4i32 |
| 70299543U, // UQSHLv4i32_shift |
| 2218307479U, // UQSHLv8i16 |
| 2218307479U, // UQSHLv8i16_shift |
| 2218831767U, // UQSHLv8i8 |
| 2218831767U, // UQSHLv8i8_shift |
| 2348820072U, // UQSHRNB_ZZI_B |
| 2387109480U, // UQSHRNB_ZZI_H |
| 2415953512U, // UQSHRNB_ZZI_S |
| 2449487613U, // UQSHRNT_ZZI_B |
| 240154365U, // UQSHRNT_ZZI_H |
| 2281740029U, // UQSHRNT_ZZI_S |
| 2248200513U, // UQSHRNb |
| 2248200513U, // UQSHRNh |
| 2248200513U, // UQSHRNs |
| 2484134260U, // UQSHRNv16i8_shift |
| 2216210753U, // UQSHRNv2i32_shift |
| 69775681U, // UQSHRNv4i16_shift |
| 2486231412U, // UQSHRNv4i32_shift |
| 339272052U, // UQSHRNv8i16_shift |
| 2218832193U, // UQSHRNv8i8_shift |
| 369111868U, // UQSUBR_ZPmZ_B |
| 369120060U, // UQSUBR_ZPmZ_D |
| 2555933500U, // UQSUBR_ZPmZ_H |
| 369136444U, // UQSUBR_ZPmZ_S |
| 2583701541U, // UQSUB_ZI_B |
| 2415937573U, // UQSUB_ZI_D |
| 241199141U, // UQSUB_ZI_H |
| 2617280549U, // UQSUB_ZI_S |
| 369109029U, // UQSUB_ZPmZ_B |
| 369117221U, // UQSUB_ZPmZ_D |
| 2555930661U, // UQSUB_ZPmZ_H |
| 369133605U, // UQSUB_ZPmZ_S |
| 2583701541U, // UQSUB_ZZZ_B |
| 2415937573U, // UQSUB_ZZZ_D |
| 2388682789U, // UQSUB_ZZZ_H |
| 2617280549U, // UQSUB_ZZZ_S |
| 68200485U, // UQSUBv16i8 |
| 2248198181U, // UQSUBv1i16 |
| 2248198181U, // UQSUBv1i32 |
| 2248198181U, // UQSUBv1i64 |
| 2248198181U, // UQSUBv1i8 |
| 2216208421U, // UQSUBv2i32 |
| 2216732709U, // UQSUBv2i64 |
| 69773349U, // UQSUBv4i16 |
| 70297637U, // UQSUBv4i32 |
| 2218305573U, // UQSUBv8i16 |
| 2218829861U, // UQSUBv8i8 |
| 201336461U, // UQXTNB_ZZ_B |
| 843605645U, // UQXTNB_ZZ_H |
| 268469901U, // UQXTNB_ZZ_S |
| 302004010U, // UQXTNT_ZZ_B |
| 844134186U, // UQXTNT_ZZ_H |
| 134256426U, // UQXTNT_ZZ_S |
| 2484134311U, // UQXTNv16i8 |
| 100716918U, // UQXTNv1i16 |
| 100716918U, // UQXTNv1i32 |
| 100716918U, // UQXTNv1i8 |
| 68727158U, // UQXTNv2i32 |
| 69775734U, // UQXTNv4i16 |
| 338747815U, // UQXTNv4i32 |
| 339272103U, // UQXTNv8i16 |
| 2218832246U, // UQXTNv8i8 |
| 35399U, // URECPE_ZPmZ_S |
| 2216208967U, // URECPEv2i32 |
| 70298183U, // URECPEv4i32 |
| 369109371U, // URHADD_ZPmZ_B |
| 369117563U, // URHADD_ZPmZ_D |
| 2555931003U, // URHADD_ZPmZ_H |
| 369133947U, // URHADD_ZPmZ_S |
| 68200827U, // URHADDv16i8 |
| 2216208763U, // URHADDv2i32 |
| 69773691U, // URHADDv4i16 |
| 70297979U, // URHADDv4i32 |
| 2218305915U, // URHADDv8i16 |
| 2218830203U, // URHADDv8i8 |
| 369111980U, // URSHLR_ZPmZ_B |
| 369120172U, // URSHLR_ZPmZ_D |
| 2555933612U, // URSHLR_ZPmZ_H |
| 369136556U, // URSHLR_ZPmZ_S |
| 369110965U, // URSHL_ZPmZ_B |
| 369119157U, // URSHL_ZPmZ_D |
| 2555932597U, // URSHL_ZPmZ_H |
| 369135541U, // URSHL_ZPmZ_S |
| 68202421U, // URSHLv16i8 |
| 2248200117U, // URSHLv1i64 |
| 2216210357U, // URSHLv2i32 |
| 2216734645U, // URSHLv2i64 |
| 69775285U, // URSHLv4i16 |
| 70299573U, // URSHLv4i32 |
| 2218307509U, // URSHLv8i16 |
| 2218831797U, // URSHLv8i8 |
| 369111907U, // URSHR_ZPmI_B |
| 369120099U, // URSHR_ZPmI_D |
| 2555933539U, // URSHR_ZPmI_H |
| 369136483U, // URSHR_ZPmI_S |
| 2248201059U, // URSHRd |
| 68203363U, // URSHRv16i8_shift |
| 2216211299U, // URSHRv2i32_shift |
| 2216735587U, // URSHRv2i64_shift |
| 69776227U, // URSHRv4i16_shift |
| 70300515U, // URSHRv4i32_shift |
| 2218308451U, // URSHRv8i16_shift |
| 2218832739U, // URSHRv8i8_shift |
| 35445U, // URSQRTE_ZPmZ_S |
| 2216209013U, // URSQRTEv2i32 |
| 70298229U, // URSQRTEv4i32 |
| 637543193U, // URSRA_ZZI_B |
| 2281718553U, // URSRA_ZZI_D |
| 242770713U, // URSRA_ZZI_H |
| 2315289369U, // URSRA_ZZI_S |
| 2684445465U, // URSRAd |
| 336651033U, // URSRAv16i8_shift |
| 2484658969U, // URSRAv2i32_shift |
| 2485183257U, // URSRAv2i64_shift |
| 338223897U, // URSRAv4i16_shift |
| 338748185U, // URSRAv4i32_shift |
| 2486756121U, // URSRAv8i16_shift |
| 2487280409U, // URSRAv8i8_shift |
| 2617263513U, // USHLLB_ZZI_D |
| 2409129369U, // USHLLB_ZZI_H |
| 2348844441U, // USHLLB_ZZI_S |
| 2617267825U, // USHLLT_ZZI_D |
| 2409133681U, // USHLLT_ZZI_H |
| 2348848753U, // USHLLT_ZZI_S |
| 70820101U, // USHLLv16i8_shift |
| 2216734671U, // USHLLv2i32_shift |
| 70299599U, // USHLLv4i16_shift |
| 69247237U, // USHLLv4i32_shift |
| 2217779461U, // USHLLv8i16_shift |
| 2218307535U, // USHLLv8i8_shift |
| 68202434U, // USHLv16i8 |
| 2248200130U, // USHLv1i64 |
| 2216210370U, // USHLv2i32 |
| 2216734658U, // USHLv2i64 |
| 69775298U, // USHLv4i16 |
| 70299586U, // USHLv4i32 |
| 2218307522U, // USHLv8i16 |
| 2218831810U, // USHLv8i8 |
| 2248201072U, // USHRd |
| 68203376U, // USHRv16i8_shift |
| 2216211312U, // USHRv2i32_shift |
| 2216735600U, // USHRv2i64_shift |
| 69776240U, // USHRv4i16_shift |
| 70300528U, // USHRv4i32_shift |
| 2218308464U, // USHRv8i16_shift |
| 2218832752U, // USHRv8i8_shift |
| 369109408U, // USQADD_ZPmZ_B |
| 369117600U, // USQADD_ZPmZ_D |
| 2555931040U, // USQADD_ZPmZ_H |
| 369133984U, // USQADD_ZPmZ_S |
| 2484136352U, // USQADDv16i8 |
| 536963488U, // USQADDv1i16 |
| 536963488U, // USQADDv1i32 |
| 536963488U, // USQADDv1i64 |
| 536963488U, // USQADDv1i8 |
| 2484660640U, // USQADDv2i32 |
| 337701280U, // USQADDv2i64 |
| 2485709216U, // USQADDv4i16 |
| 338749856U, // USQADDv4i32 |
| 2486757792U, // USQADDv8i16 |
| 339798432U, // USQADDv8i8 |
| 637543206U, // USRA_ZZI_B |
| 2281718566U, // USRA_ZZI_D |
| 242770726U, // USRA_ZZI_H |
| 2315289382U, // USRA_ZZI_S |
| 2684445478U, // USRAd |
| 336651046U, // USRAv16i8_shift |
| 2484658982U, // USRAv2i32_shift |
| 2485183270U, // USRAv2i64_shift |
| 338223910U, // USRAv4i16_shift |
| 338748198U, // USRAv4i32_shift |
| 2486756134U, // USRAv8i16_shift |
| 2487280422U, // USRAv8i8_shift |
| 2617263442U, // USUBLB_ZZZ_D |
| 261645650U, // USUBLB_ZZZ_H |
| 2348844370U, // USUBLB_ZZZ_S |
| 2617267749U, // USUBLT_ZZZ_D |
| 261649957U, // USUBLT_ZZZ_H |
| 2348848677U, // USUBLT_ZZZ_S |
| 70820053U, // USUBLv16i8_v8i16 |
| 2216734525U, // USUBLv2i32_v2i64 |
| 70299453U, // USUBLv4i16_v4i32 |
| 69247189U, // USUBLv4i32_v2i64 |
| 2217779413U, // USUBLv8i16_v4i32 |
| 2218307389U, // USUBLv8i8_v8i16 |
| 2415937594U, // USUBWB_ZZZ_D |
| 241199162U, // USUBWB_ZZZ_H |
| 2617280570U, // USUBWB_ZZZ_S |
| 2415941547U, // USUBWT_ZZZ_D |
| 241203115U, // USUBWT_ZZZ_H |
| 2617284523U, // USUBWT_ZZZ_S |
| 2218303990U, // USUBWv16i8_v8i16 |
| 2216737020U, // USUBWv2i32_v2i64 |
| 70301948U, // USUBWv4i16_v4i32 |
| 2216731126U, // USUBWv4i32_v2i64 |
| 70296054U, // USUBWv8i16_v4i32 |
| 2218309884U, // USUBWv8i8_v8i16 |
| 469782095U, // UUNPKHI_ZZ_D |
| 865627727U, // UUNPKHI_ZZ_H |
| 201363023U, // UUNPKHI_ZZ_S |
| 469782977U, // UUNPKLO_ZZ_D |
| 865628609U, // UUNPKLO_ZZ_H |
| 201363905U, // UUNPKLO_ZZ_S |
| 2147502069U, // UXTB_ZPmZ_D |
| 34105333U, // UXTB_ZPmZ_H |
| 34805U, // UXTB_ZPmZ_S |
| 2147503631U, // UXTH_ZPmZ_D |
| 36367U, // UXTH_ZPmZ_S |
| 2147506614U, // UXTW_ZPmZ_D |
| 2583699505U, // UZP1_PPP_B |
| 2415935537U, // UZP1_PPP_D |
| 2388680753U, // UZP1_PPP_H |
| 2617278513U, // UZP1_PPP_S |
| 2583699505U, // UZP1_ZZZ_B |
| 2415935537U, // UZP1_ZZZ_D |
| 2388680753U, // UZP1_ZZZ_H |
| 2617278513U, // UZP1_ZZZ_S |
| 68198449U, // UZP1v16i8 |
| 2216206385U, // UZP1v2i32 |
| 2216730673U, // UZP1v2i64 |
| 69771313U, // UZP1v4i16 |
| 70295601U, // UZP1v4i32 |
| 2218303537U, // UZP1v8i16 |
| 2218827825U, // UZP1v8i8 |
| 2583699932U, // UZP2_PPP_B |
| 2415935964U, // UZP2_PPP_D |
| 2388681180U, // UZP2_PPP_H |
| 2617278940U, // UZP2_PPP_S |
| 2583699932U, // UZP2_ZZZ_B |
| 2415935964U, // UZP2_ZZZ_D |
| 2388681180U, // UZP2_ZZZ_H |
| 2617278940U, // UZP2_ZZZ_S |
| 68198876U, // UZP2v16i8 |
| 2216206812U, // UZP2v2i32 |
| 2216731100U, // UZP2v2i64 |
| 69771740U, // UZP2v4i16 |
| 70296028U, // UZP2v4i32 |
| 2218303964U, // UZP2v8i16 |
| 2218828252U, // UZP2v8i8 |
| 2248157682U, // WHILEGE_PWW_B |
| 2248165874U, // WHILEGE_PWW_D |
| 2391828978U, // WHILEGE_PWW_H |
| 2248182258U, // WHILEGE_PWW_S |
| 2248157682U, // WHILEGE_PXX_B |
| 2248165874U, // WHILEGE_PXX_D |
| 2391828978U, // WHILEGE_PXX_H |
| 2248182258U, // WHILEGE_PXX_S |
| 2248160718U, // WHILEGT_PWW_B |
| 2248168910U, // WHILEGT_PWW_D |
| 2391832014U, // WHILEGT_PWW_H |
| 2248185294U, // WHILEGT_PWW_S |
| 2248160718U, // WHILEGT_PXX_B |
| 2248168910U, // WHILEGT_PXX_D |
| 2391832014U, // WHILEGT_PXX_H |
| 2248185294U, // WHILEGT_PXX_S |
| 2248158772U, // WHILEHI_PWW_B |
| 2248166964U, // WHILEHI_PWW_D |
| 2391830068U, // WHILEHI_PWW_H |
| 2248183348U, // WHILEHI_PWW_S |
| 2248158772U, // WHILEHI_PXX_B |
| 2248166964U, // WHILEHI_PXX_D |
| 2391830068U, // WHILEHI_PXX_H |
| 2248183348U, // WHILEHI_PXX_S |
| 2248160468U, // WHILEHS_PWW_B |
| 2248168660U, // WHILEHS_PWW_D |
| 2391831764U, // WHILEHS_PWW_H |
| 2248185044U, // WHILEHS_PWW_S |
| 2248160468U, // WHILEHS_PXX_B |
| 2248168660U, // WHILEHS_PXX_D |
| 2391831764U, // WHILEHS_PXX_H |
| 2248185044U, // WHILEHS_PXX_S |
| 2248157713U, // WHILELE_PWW_B |
| 2248165905U, // WHILELE_PWW_D |
| 2391829009U, // WHILELE_PWW_H |
| 2248182289U, // WHILELE_PWW_S |
| 2248157713U, // WHILELE_PXX_B |
| 2248165905U, // WHILELE_PXX_D |
| 2391829009U, // WHILELE_PXX_H |
| 2248182289U, // WHILELE_PXX_S |
| 2248159654U, // WHILELO_PWW_B |
| 2248167846U, // WHILELO_PWW_D |
| 2391830950U, // WHILELO_PWW_H |
| 2248184230U, // WHILELO_PWW_S |
| 2248159654U, // WHILELO_PXX_B |
| 2248167846U, // WHILELO_PXX_D |
| 2391830950U, // WHILELO_PXX_H |
| 2248184230U, // WHILELO_PXX_S |
| 2248160495U, // WHILELS_PWW_B |
| 2248168687U, // WHILELS_PWW_D |
| 2391831791U, // WHILELS_PWW_H |
| 2248185071U, // WHILELS_PWW_S |
| 2248160495U, // WHILELS_PXX_B |
| 2248168687U, // WHILELS_PXX_D |
| 2391831791U, // WHILELS_PXX_H |
| 2248185071U, // WHILELS_PXX_S |
| 2248160859U, // WHILELT_PWW_B |
| 2248169051U, // WHILELT_PWW_D |
| 2391832155U, // WHILELT_PWW_H |
| 2248185435U, // WHILELT_PWW_S |
| 2248160859U, // WHILELT_PXX_B |
| 2248169051U, // WHILELT_PXX_D |
| 2391832155U, // WHILELT_PXX_H |
| 2248185435U, // WHILELT_PXX_S |
| 2248161615U, // WHILERW_PXX_B |
| 2248169807U, // WHILERW_PXX_D |
| 2391832911U, // WHILERW_PXX_H |
| 2248186191U, // WHILERW_PXX_S |
| 2248160332U, // WHILEWR_PXX_B |
| 2248168524U, // WHILEWR_PXX_D |
| 2391831628U, // WHILEWR_PXX_H |
| 2248184908U, // WHILEWR_PXX_S |
| 7353173U, // WRFFR |
| 7175U, // XAFLAG |
| 2216735512U, // XAR |
| 2583704344U, // XAR_ZZZI_B |
| 2415940376U, // XAR_ZZZI_D |
| 2388685592U, // XAR_ZZZI_H |
| 2617283352U, // XAR_ZZZI_S |
| 7391536U, // XPACD |
| 7392813U, // XPACI |
| 7060U, // XPACLRI |
| 2484134305U, // XTNv16i8 |
| 68727153U, // XTNv2i32 |
| 69775729U, // XTNv4i16 |
| 338747809U, // XTNv4i32 |
| 339272097U, // XTNv8i16 |
| 2218832241U, // XTNv8i8 |
| 2583699499U, // ZIP1_PPP_B |
| 2415935531U, // ZIP1_PPP_D |
| 2388680747U, // ZIP1_PPP_H |
| 2617278507U, // ZIP1_PPP_S |
| 2583699499U, // ZIP1_ZZZ_B |
| 2415935531U, // ZIP1_ZZZ_D |
| 2388680747U, // ZIP1_ZZZ_H |
| 2617278507U, // ZIP1_ZZZ_S |
| 68198443U, // ZIP1v16i8 |
| 2216206379U, // ZIP1v2i32 |
| 2216730667U, // ZIP1v2i64 |
| 69771307U, // ZIP1v4i16 |
| 70295595U, // ZIP1v4i32 |
| 2218303531U, // ZIP1v8i16 |
| 2218827819U, // ZIP1v8i8 |
| 2583699926U, // ZIP2_PPP_B |
| 2415935958U, // ZIP2_PPP_D |
| 2388681174U, // ZIP2_PPP_H |
| 2617278934U, // ZIP2_PPP_S |
| 2583699926U, // ZIP2_ZZZ_B |
| 2415935958U, // ZIP2_ZZZ_D |
| 2388681174U, // ZIP2_ZZZ_H |
| 2617278934U, // ZIP2_ZZZ_S |
| 68198870U, // ZIP2v16i8 |
| 2216206806U, // ZIP2v2i32 |
| 2216731094U, // ZIP2v2i64 |
| 69771734U, // ZIP2v4i16 |
| 70296022U, // ZIP2v4i32 |
| 2218303958U, // ZIP2v8i16 |
| 2218828246U, // ZIP2v8i8 |
| }; |
| |
| static const uint32_t OpInfo1[] = { |
| 0U, // PHI |
| 0U, // INLINEASM |
| 0U, // INLINEASM_BR |
| 0U, // CFI_INSTRUCTION |
| 0U, // EH_LABEL |
| 0U, // GC_LABEL |
| 0U, // ANNOTATION_LABEL |
| 0U, // KILL |
| 0U, // EXTRACT_SUBREG |
| 0U, // INSERT_SUBREG |
| 0U, // IMPLICIT_DEF |
| 0U, // SUBREG_TO_REG |
| 0U, // COPY_TO_REGCLASS |
| 0U, // DBG_VALUE |
| 0U, // DBG_LABEL |
| 0U, // REG_SEQUENCE |
| 0U, // COPY |
| 0U, // BUNDLE |
| 0U, // LIFETIME_START |
| 0U, // LIFETIME_END |
| 0U, // STACKMAP |
| 0U, // FENTRY_CALL |
| 0U, // PATCHPOINT |
| 0U, // LOAD_STACK_GUARD |
| 0U, // STATEPOINT |
| 0U, // LOCAL_ESCAPE |
| 0U, // FAULTING_OP |
| 0U, // PATCHABLE_OP |
| 0U, // PATCHABLE_FUNCTION_ENTER |
| 0U, // PATCHABLE_RET |
| 0U, // PATCHABLE_FUNCTION_EXIT |
| 0U, // PATCHABLE_TAIL_CALL |
| 0U, // PATCHABLE_EVENT_CALL |
| 0U, // PATCHABLE_TYPED_EVENT_CALL |
| 0U, // ICALL_BRANCH_FUNNEL |
| 0U, // G_ADD |
| 0U, // G_SUB |
| 0U, // G_MUL |
| 0U, // G_SDIV |
| 0U, // G_UDIV |
| 0U, // G_SREM |
| 0U, // G_UREM |
| 0U, // G_AND |
| 0U, // G_OR |
| 0U, // G_XOR |
| 0U, // G_IMPLICIT_DEF |
| 0U, // G_PHI |
| 0U, // G_FRAME_INDEX |
| 0U, // G_GLOBAL_VALUE |
| 0U, // G_EXTRACT |
| 0U, // G_UNMERGE_VALUES |
| 0U, // G_INSERT |
| 0U, // G_MERGE_VALUES |
| 0U, // G_BUILD_VECTOR |
| 0U, // G_BUILD_VECTOR_TRUNC |
| 0U, // G_CONCAT_VECTORS |
| 0U, // G_PTRTOINT |
| 0U, // G_INTTOPTR |
| 0U, // G_BITCAST |
| 0U, // G_INTRINSIC_TRUNC |
| 0U, // G_INTRINSIC_ROUND |
| 0U, // G_READCYCLECOUNTER |
| 0U, // G_LOAD |
| 0U, // G_SEXTLOAD |
| 0U, // G_ZEXTLOAD |
| 0U, // G_INDEXED_LOAD |
| 0U, // G_INDEXED_SEXTLOAD |
| 0U, // G_INDEXED_ZEXTLOAD |
| 0U, // G_STORE |
| 0U, // G_INDEXED_STORE |
| 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 0U, // G_ATOMIC_CMPXCHG |
| 0U, // G_ATOMICRMW_XCHG |
| 0U, // G_ATOMICRMW_ADD |
| 0U, // G_ATOMICRMW_SUB |
| 0U, // G_ATOMICRMW_AND |
| 0U, // G_ATOMICRMW_NAND |
| 0U, // G_ATOMICRMW_OR |
| 0U, // G_ATOMICRMW_XOR |
| 0U, // G_ATOMICRMW_MAX |
| 0U, // G_ATOMICRMW_MIN |
| 0U, // G_ATOMICRMW_UMAX |
| 0U, // G_ATOMICRMW_UMIN |
| 0U, // G_ATOMICRMW_FADD |
| 0U, // G_ATOMICRMW_FSUB |
| 0U, // G_FENCE |
| 0U, // G_BRCOND |
| 0U, // G_BRINDIRECT |
| 0U, // G_INTRINSIC |
| 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 0U, // G_ANYEXT |
| 0U, // G_TRUNC |
| 0U, // G_CONSTANT |
| 0U, // G_FCONSTANT |
| 0U, // G_VASTART |
| 0U, // G_VAARG |
| 0U, // G_SEXT |
| 0U, // G_SEXT_INREG |
| 0U, // G_ZEXT |
| 0U, // G_SHL |
| 0U, // G_LSHR |
| 0U, // G_ASHR |
| 0U, // G_ICMP |
| 0U, // G_FCMP |
| 0U, // G_SELECT |
| 0U, // G_UADDO |
| 0U, // G_UADDE |
| 0U, // G_USUBO |
| 0U, // G_USUBE |
| 0U, // G_SADDO |
| 0U, // G_SADDE |
| 0U, // G_SSUBO |
| 0U, // G_SSUBE |
| 0U, // G_UMULO |
| 0U, // G_SMULO |
| 0U, // G_UMULH |
| 0U, // G_SMULH |
| 0U, // G_FADD |
| 0U, // G_FSUB |
| 0U, // G_FMUL |
| 0U, // G_FMA |
| 0U, // G_FMAD |
| 0U, // G_FDIV |
| 0U, // G_FREM |
| 0U, // G_FPOW |
| 0U, // G_FEXP |
| 0U, // G_FEXP2 |
| 0U, // G_FLOG |
| 0U, // G_FLOG2 |
| 0U, // G_FLOG10 |
| 0U, // G_FNEG |
| 0U, // G_FPEXT |
| 0U, // G_FPTRUNC |
| 0U, // G_FPTOSI |
| 0U, // G_FPTOUI |
| 0U, // G_SITOFP |
| 0U, // G_UITOFP |
| 0U, // G_FABS |
| 0U, // G_FCOPYSIGN |
| 0U, // G_FCANONICALIZE |
| 0U, // G_FMINNUM |
| 0U, // G_FMAXNUM |
| 0U, // G_FMINNUM_IEEE |
| 0U, // G_FMAXNUM_IEEE |
| 0U, // G_FMINIMUM |
| 0U, // G_FMAXIMUM |
| 0U, // G_PTR_ADD |
| 0U, // G_PTR_MASK |
| 0U, // G_SMIN |
| 0U, // G_SMAX |
| 0U, // G_UMIN |
| 0U, // G_UMAX |
| 0U, // G_BR |
| 0U, // G_BRJT |
| 0U, // G_INSERT_VECTOR_ELT |
| 0U, // G_EXTRACT_VECTOR_ELT |
| 0U, // G_SHUFFLE_VECTOR |
| 0U, // G_CTTZ |
| 0U, // G_CTTZ_ZERO_UNDEF |
| 0U, // G_CTLZ |
| 0U, // G_CTLZ_ZERO_UNDEF |
| 0U, // G_CTPOP |
| 0U, // G_BSWAP |
| 0U, // G_BITREVERSE |
| 0U, // G_FCEIL |
| 0U, // G_FCOS |
| 0U, // G_FSIN |
| 0U, // G_FSQRT |
| 0U, // G_FFLOOR |
| 0U, // G_FRINT |
| 0U, // G_FNEARBYINT |
| 0U, // G_ADDRSPACE_CAST |
| 0U, // G_BLOCK_ADDR |
| 0U, // G_JUMP_TABLE |
| 0U, // G_DYN_STACKALLOC |
| 0U, // G_READ_REGISTER |
| 0U, // G_WRITE_REGISTER |
| 0U, // CATCHRET |
| 0U, // CLEANUPRET |
| 0U, // SEH_AddFP |
| 0U, // SEH_EpilogEnd |
| 0U, // SEH_EpilogStart |
| 0U, // SEH_Nop |
| 0U, // SEH_PrologEnd |
| 0U, // SEH_SaveFPLR |
| 0U, // SEH_SaveFPLR_X |
| 0U, // SEH_SaveFReg |
| 0U, // SEH_SaveFRegP |
| 0U, // SEH_SaveFRegP_X |
| 0U, // SEH_SaveFReg_X |
| 0U, // SEH_SaveReg |
| 0U, // SEH_SaveRegP |
| 0U, // SEH_SaveRegP_X |
| 0U, // SEH_SaveReg_X |
| 0U, // SEH_SetFP |
| 0U, // SEH_StackAlloc |
| 0U, // ABS_ZPmZ_B |
| 0U, // ABS_ZPmZ_D |
| 0U, // ABS_ZPmZ_H |
| 1U, // ABS_ZPmZ_S |
| 1U, // ABSv16i8 |
| 2U, // ABSv1i64 |
| 2U, // ABSv2i32 |
| 3U, // ABSv2i64 |
| 3U, // ABSv4i16 |
| 4U, // ABSv4i32 |
| 4U, // ABSv8i16 |
| 5U, // ABSv8i8 |
| 69U, // ADCLB_ZZZ_D |
| 133U, // ADCLB_ZZZ_S |
| 69U, // ADCLT_ZZZ_D |
| 133U, // ADCLT_ZZZ_S |
| 197U, // ADCSWr |
| 197U, // ADCSXr |
| 197U, // ADCWr |
| 197U, // ADCXr |
| 8453U, // ADDG |
| 325U, // ADDHNB_ZZZ_B |
| 6U, // ADDHNB_ZZZ_H |
| 389U, // ADDHNB_ZZZ_S |
| 453U, // ADDHNT_ZZZ_B |
| 1U, // ADDHNT_ZZZ_H |
| 69U, // ADDHNT_ZZZ_S |
| 16902U, // ADDHNv2i64_v2i32 |
| 16966U, // ADDHNv2i64_v4i32 |
| 25095U, // ADDHNv4i32_v4i16 |
| 25159U, // ADDHNv4i32_v8i16 |
| 33351U, // ADDHNv8i16_v16i8 |
| 33287U, // ADDHNv8i16_v8i8 |
| 197U, // ADDPL_XXI |
| 533128U, // ADDP_ZPmZ_B |
| 1057160U, // ADDP_ZPmZ_D |
| 1614536U, // ADDP_ZPmZ_H |
| 2106120U, // ADDP_ZPmZ_S |
| 49673U, // ADDPv16i8 |
| 57865U, // ADDPv2i32 |
| 16902U, // ADDPv2i64 |
| 3U, // ADDPv2i64p |
| 66058U, // ADDPv4i16 |
| 25095U, // ADDPv4i32 |
| 33287U, // ADDPv8i16 |
| 74250U, // ADDPv8i8 |
| 837U, // ADDSWri |
| 0U, // ADDSWrr |
| 901U, // ADDSWrs |
| 965U, // ADDSWrx |
| 837U, // ADDSXri |
| 0U, // ADDSXrr |
| 901U, // ADDSXrs |
| 965U, // ADDSXrx |
| 82117U, // ADDSXrx64 |
| 197U, // ADDVL_XXI |
| 1U, // ADDVv16i8v |
| 3U, // ADDVv4i16v |
| 4U, // ADDVv4i32v |
| 4U, // ADDVv8i16v |
| 5U, // ADDVv8i8v |
| 837U, // ADDWri |
| 0U, // ADDWrr |
| 901U, // ADDWrs |
| 965U, // ADDWrx |
| 837U, // ADDXri |
| 0U, // ADDXrr |
| 901U, // ADDXrs |
| 965U, // ADDXrx |
| 82117U, // ADDXrx64 |
| 1029U, // ADD_ZI_B |
| 1093U, // ADD_ZI_D |
| 11U, // ADD_ZI_H |
| 1157U, // ADD_ZI_S |
| 533128U, // ADD_ZPmZ_B |
| 1057160U, // ADD_ZPmZ_D |
| 1614536U, // ADD_ZPmZ_H |
| 2106120U, // ADD_ZPmZ_S |
| 645U, // ADD_ZZZ_B |
| 389U, // ADD_ZZZ_D |
| 8U, // ADD_ZZZ_H |
| 773U, // ADD_ZZZ_S |
| 0U, // ADDlowTLS |
| 49673U, // ADDv16i8 |
| 197U, // ADDv1i64 |
| 57865U, // ADDv2i32 |
| 16902U, // ADDv2i64 |
| 66058U, // ADDv4i16 |
| 25095U, // ADDv4i32 |
| 33287U, // ADDv8i16 |
| 74250U, // ADDv8i8 |
| 0U, // ADJCALLSTACKDOWN |
| 0U, // ADJCALLSTACKUP |
| 2U, // ADR |
| 0U, // ADRP |
| 1221U, // ADR_LSL_ZZZ_D_0 |
| 1285U, // ADR_LSL_ZZZ_D_1 |
| 1349U, // ADR_LSL_ZZZ_D_2 |
| 1413U, // ADR_LSL_ZZZ_D_3 |
| 1477U, // ADR_LSL_ZZZ_S_0 |
| 1541U, // ADR_LSL_ZZZ_S_1 |
| 1605U, // ADR_LSL_ZZZ_S_2 |
| 1669U, // ADR_LSL_ZZZ_S_3 |
| 1733U, // ADR_SXTW_ZZZ_D_0 |
| 1797U, // ADR_SXTW_ZZZ_D_1 |
| 1861U, // ADR_SXTW_ZZZ_D_2 |
| 1925U, // ADR_SXTW_ZZZ_D_3 |
| 1989U, // ADR_UXTW_ZZZ_D_0 |
| 2053U, // ADR_UXTW_ZZZ_D_1 |
| 2117U, // ADR_UXTW_ZZZ_D_2 |
| 2181U, // ADR_UXTW_ZZZ_D_3 |
| 645U, // AESD_ZZZ_B |
| 1U, // AESDrr |
| 645U, // AESE_ZZZ_B |
| 1U, // AESErr |
| 2U, // AESIMC_ZZ_B |
| 1U, // AESIMCrr |
| 0U, // AESIMCrrTied |
| 2U, // AESMC_ZZ_B |
| 1U, // AESMCrr |
| 0U, // AESMCrrTied |
| 2245U, // ANDSWri |
| 0U, // ANDSWrr |
| 901U, // ANDSWrs |
| 2309U, // ANDSXri |
| 0U, // ANDSXrr |
| 901U, // ANDSXrs |
| 533131U, // ANDS_PPzPP |
| 645U, // ANDV_VPZ_B |
| 389U, // ANDV_VPZ_D |
| 325U, // ANDV_VPZ_H |
| 773U, // ANDV_VPZ_S |
| 2245U, // ANDWri |
| 0U, // ANDWrr |
| 901U, // ANDWrs |
| 2309U, // ANDXri |
| 0U, // ANDXrr |
| 901U, // ANDXrs |
| 533131U, // AND_PPzPP |
| 2309U, // AND_ZI |
| 533128U, // AND_ZPmZ_B |
| 1057160U, // AND_ZPmZ_D |
| 1614536U, // AND_ZPmZ_H |
| 2106120U, // AND_ZPmZ_S |
| 389U, // AND_ZZZ |
| 49673U, // ANDv16i8 |
| 74250U, // ANDv8i8 |
| 8840U, // ASRD_ZPmI_B |
| 8584U, // ASRD_ZPmI_D |
| 90824U, // ASRD_ZPmI_H |
| 8968U, // ASRD_ZPmI_S |
| 533128U, // ASRR_ZPmZ_B |
| 1057160U, // ASRR_ZPmZ_D |
| 1614536U, // ASRR_ZPmZ_H |
| 2106120U, // ASRR_ZPmZ_S |
| 197U, // ASRVWr |
| 197U, // ASRVXr |
| 1057416U, // ASR_WIDE_ZPmZ_B |
| 99016U, // ASR_WIDE_ZPmZ_H |
| 1057544U, // ASR_WIDE_ZPmZ_S |
| 389U, // ASR_WIDE_ZZZ_B |
| 12U, // ASR_WIDE_ZZZ_H |
| 389U, // ASR_WIDE_ZZZ_S |
| 8840U, // ASR_ZPmI_B |
| 8584U, // ASR_ZPmI_D |
| 90824U, // ASR_ZPmI_H |
| 8968U, // ASR_ZPmI_S |
| 533128U, // ASR_ZPmZ_B |
| 1057160U, // ASR_ZPmZ_D |
| 1614536U, // ASR_ZPmZ_H |
| 2106120U, // ASR_ZPmZ_S |
| 197U, // ASR_ZZI_B |
| 197U, // ASR_ZZI_D |
| 12U, // ASR_ZZI_H |
| 197U, // ASR_ZZI_S |
| 2U, // AUTDA |
| 2U, // AUTDB |
| 0U, // AUTDZA |
| 0U, // AUTDZB |
| 2U, // AUTIA |
| 0U, // AUTIA1716 |
| 0U, // AUTIASP |
| 0U, // AUTIAZ |
| 2U, // AUTIB |
| 0U, // AUTIB1716 |
| 0U, // AUTIBSP |
| 0U, // AUTIBZ |
| 0U, // AUTIZA |
| 0U, // AUTIZB |
| 0U, // AXFLAG |
| 0U, // B |
| 36282889U, // BCAX |
| 1057157U, // BCAX_ZZZZ_D |
| 645U, // BDEP_ZZZ_B |
| 389U, // BDEP_ZZZ_D |
| 8U, // BDEP_ZZZ_H |
| 773U, // BDEP_ZZZ_S |
| 645U, // BEXT_ZZZ_B |
| 389U, // BEXT_ZZZ_D |
| 8U, // BEXT_ZZZ_H |
| 773U, // BEXT_ZZZ_S |
| 3156293U, // BFMWri |
| 3156293U, // BFMXri |
| 645U, // BGRP_ZZZ_B |
| 389U, // BGRP_ZZZ_D |
| 8U, // BGRP_ZZZ_H |
| 773U, // BGRP_ZZZ_S |
| 0U, // BICSWrr |
| 901U, // BICSWrs |
| 0U, // BICSXrr |
| 901U, // BICSXrs |
| 533131U, // BICS_PPzPP |
| 0U, // BICWrr |
| 901U, // BICWrs |
| 0U, // BICXrr |
| 901U, // BICXrs |
| 533131U, // BIC_PPzPP |
| 533128U, // BIC_ZPmZ_B |
| 1057160U, // BIC_ZPmZ_D |
| 1614536U, // BIC_ZPmZ_H |
| 2106120U, // BIC_ZPmZ_S |
| 389U, // BIC_ZZZ |
| 49673U, // BICv16i8 |
| 0U, // BICv2i32 |
| 0U, // BICv4i16 |
| 0U, // BICv4i32 |
| 0U, // BICv8i16 |
| 74250U, // BICv8i8 |
| 49673U, // BIFv16i8 |
| 74250U, // BIFv8i8 |
| 49737U, // BITv16i8 |
| 74314U, // BITv8i8 |
| 0U, // BL |
| 0U, // BLR |
| 2U, // BLRAA |
| 0U, // BLRAAZ |
| 2U, // BLRAB |
| 0U, // BLRABZ |
| 0U, // BR |
| 2U, // BRAA |
| 0U, // BRAAZ |
| 2U, // BRAB |
| 0U, // BRABZ |
| 0U, // BRK |
| 651U, // BRKAS_PPzP |
| 0U, // BRKA_PPmP |
| 651U, // BRKA_PPzP |
| 651U, // BRKBS_PPzP |
| 0U, // BRKB_PPmP |
| 651U, // BRKB_PPzP |
| 533131U, // BRKNS_PPzP |
| 533131U, // BRKN_PPzP |
| 533131U, // BRKPAS_PPzPP |
| 533131U, // BRKPA_PPzPP |
| 533131U, // BRKPBS_PPzPP |
| 533131U, // BRKPB_PPzPP |
| 1057157U, // BSL1N_ZZZZ_D |
| 1057157U, // BSL2N_ZZZZ_D |
| 1057157U, // BSL_ZZZZ_D |
| 49737U, // BSLv16i8 |
| 74314U, // BSLv8i8 |
| 0U, // Bcc |
| 3678853U, // CADD_ZZI_B |
| 3678597U, // CADD_ZZI_D |
| 115400U, // CADD_ZZI_H |
| 3678981U, // CADD_ZZI_S |
| 125261U, // CASAB |
| 125261U, // CASAH |
| 125261U, // CASALB |
| 125261U, // CASALH |
| 125261U, // CASALW |
| 125261U, // CASALX |
| 125261U, // CASAW |
| 125261U, // CASAX |
| 125261U, // CASB |
| 125261U, // CASH |
| 125261U, // CASLB |
| 125261U, // CASLH |
| 125261U, // CASLW |
| 125261U, // CASLX |
| 0U, // CASPALW |
| 0U, // CASPALX |
| 0U, // CASPAW |
| 0U, // CASPAX |
| 0U, // CASPLW |
| 0U, // CASPLX |
| 0U, // CASPW |
| 0U, // CASPX |
| 125261U, // CASW |
| 125261U, // CASX |
| 0U, // CATCHPAD |
| 0U, // CBNZW |
| 0U, // CBNZX |
| 0U, // CBZW |
| 0U, // CBZX |
| 4202693U, // CCMNWi |
| 4202693U, // CCMNWr |
| 4202693U, // CCMNXi |
| 4202693U, // CCMNXr |
| 4202693U, // CCMPWi |
| 4202693U, // CCMPWr |
| 4202693U, // CCMPXi |
| 4202693U, // CCMPXr |
| 71958981U, // CDOT_ZZZI_D |
| 5253504U, // CDOT_ZZZI_S |
| 5775813U, // CDOT_ZZZ_D |
| 139968U, // CDOT_ZZZ_S |
| 0U, // CFINV |
| 532677U, // CLASTA_RPZ_B |
| 1056965U, // CLASTA_RPZ_D |
| 6299845U, // CLASTA_RPZ_H |
| 2105541U, // CLASTA_RPZ_S |
| 532677U, // CLASTA_VPZ_B |
| 1056965U, // CLASTA_VPZ_D |
| 6299845U, // CLASTA_VPZ_H |
| 2105541U, // CLASTA_VPZ_S |
| 533125U, // CLASTA_ZPZ_B |
| 1057157U, // CLASTA_ZPZ_D |
| 1614536U, // CLASTA_ZPZ_H |
| 2106117U, // CLASTA_ZPZ_S |
| 532677U, // CLASTB_RPZ_B |
| 1056965U, // CLASTB_RPZ_D |
| 6299845U, // CLASTB_RPZ_H |
| 2105541U, // CLASTB_RPZ_S |
| 532677U, // CLASTB_VPZ_B |
| 1056965U, // CLASTB_VPZ_D |
| 6299845U, // CLASTB_VPZ_H |
| 2105541U, // CLASTB_VPZ_S |
| 533125U, // CLASTB_ZPZ_B |
| 1057157U, // CLASTB_ZPZ_D |
| 1614536U, // CLASTB_ZPZ_H |
| 2106117U, // CLASTB_ZPZ_S |
| 0U, // CLREX |
| 2U, // CLSWr |
| 2U, // CLSXr |
| 0U, // CLS_ZPmZ_B |
| 0U, // CLS_ZPmZ_D |
| 0U, // CLS_ZPmZ_H |
| 1U, // CLS_ZPmZ_S |
| 1U, // CLSv16i8 |
| 2U, // CLSv2i32 |
| 3U, // CLSv4i16 |
| 4U, // CLSv4i32 |
| 4U, // CLSv8i16 |
| 5U, // CLSv8i8 |
| 2U, // CLZWr |
| 2U, // CLZXr |
| 0U, // CLZ_ZPmZ_B |
| 0U, // CLZ_ZPmZ_D |
| 0U, // CLZ_ZPmZ_H |
| 1U, // CLZ_ZPmZ_S |
| 1U, // CLZv16i8 |
| 2U, // CLZv2i32 |
| 3U, // CLZv4i16 |
| 4U, // CLZv4i32 |
| 4U, // CLZv8i16 |
| 5U, // CLZv8i8 |
| 49673U, // CMEQv16i8 |
| 13U, // CMEQv16i8rz |
| 197U, // CMEQv1i64 |
| 14U, // CMEQv1i64rz |
| 57865U, // CMEQv2i32 |
| 14U, // CMEQv2i32rz |
| 16902U, // CMEQv2i64 |
| 15U, // CMEQv2i64rz |
| 66058U, // CMEQv4i16 |
| 15U, // CMEQv4i16rz |
| 25095U, // CMEQv4i32 |
| 16U, // CMEQv4i32rz |
| 33287U, // CMEQv8i16 |
| 16U, // CMEQv8i16rz |
| 74250U, // CMEQv8i8 |
| 17U, // CMEQv8i8rz |
| 49673U, // CMGEv16i8 |
| 13U, // CMGEv16i8rz |
| 197U, // CMGEv1i64 |
| 14U, // CMGEv1i64rz |
| 57865U, // CMGEv2i32 |
| 14U, // CMGEv2i32rz |
| 16902U, // CMGEv2i64 |
| 15U, // CMGEv2i64rz |
| 66058U, // CMGEv4i16 |
| 15U, // CMGEv4i16rz |
| 25095U, // CMGEv4i32 |
| 16U, // CMGEv4i32rz |
| 33287U, // CMGEv8i16 |
| 16U, // CMGEv8i16rz |
| 74250U, // CMGEv8i8 |
| 17U, // CMGEv8i8rz |
| 49673U, // CMGTv16i8 |
| 13U, // CMGTv16i8rz |
| 197U, // CMGTv1i64 |
| 14U, // CMGTv1i64rz |
| 57865U, // CMGTv2i32 |
| 14U, // CMGTv2i32rz |
| 16902U, // CMGTv2i64 |
| 15U, // CMGTv2i64rz |
| 66058U, // CMGTv4i16 |
| 15U, // CMGTv4i16rz |
| 25095U, // CMGTv4i32 |
| 16U, // CMGTv4i32rz |
| 33287U, // CMGTv8i16 |
| 16U, // CMGTv8i16rz |
| 74250U, // CMGTv8i8 |
| 17U, // CMGTv8i8rz |
| 49673U, // CMHIv16i8 |
| 197U, // CMHIv1i64 |
| 57865U, // CMHIv2i32 |
| 16902U, // CMHIv2i64 |
| 66058U, // CMHIv4i16 |
| 25095U, // CMHIv4i32 |
| 33287U, // CMHIv8i16 |
| 74250U, // CMHIv8i8 |
| 49673U, // CMHSv16i8 |
| 197U, // CMHSv1i64 |
| 57865U, // CMHSv2i32 |
| 16902U, // CMHSv2i64 |
| 66058U, // CMHSv4i16 |
| 25095U, // CMHSv4i32 |
| 33287U, // CMHSv8i16 |
| 74250U, // CMHSv8i8 |
| 5253521U, // CMLA_ZZZI_H |
| 71958661U, // CMLA_ZZZI_S |
| 139968U, // CMLA_ZZZ_B |
| 5775429U, // CMLA_ZZZ_D |
| 139985U, // CMLA_ZZZ_H |
| 5775493U, // CMLA_ZZZ_S |
| 13U, // CMLEv16i8rz |
| 14U, // CMLEv1i64rz |
| 14U, // CMLEv2i32rz |
| 15U, // CMLEv2i64rz |
| 15U, // CMLEv4i16rz |
| 16U, // CMLEv4i32rz |
| 16U, // CMLEv8i16rz |
| 17U, // CMLEv8i8rz |
| 13U, // CMLTv16i8rz |
| 14U, // CMLTv1i64rz |
| 14U, // CMLTv2i32rz |
| 15U, // CMLTv2i64rz |
| 15U, // CMLTv4i16rz |
| 16U, // CMLTv4i32rz |
| 16U, // CMLTv8i16rz |
| 17U, // CMLTv8i8rz |
| 8843U, // CMPEQ_PPzZI_B |
| 8587U, // CMPEQ_PPzZI_D |
| 90824U, // CMPEQ_PPzZI_H |
| 8971U, // CMPEQ_PPzZI_S |
| 533131U, // CMPEQ_PPzZZ_B |
| 1057163U, // CMPEQ_PPzZZ_D |
| 1614536U, // CMPEQ_PPzZZ_H |
| 2106123U, // CMPEQ_PPzZZ_S |
| 1057419U, // CMPEQ_WIDE_PPzZZ_B |
| 99016U, // CMPEQ_WIDE_PPzZZ_H |
| 1057547U, // CMPEQ_WIDE_PPzZZ_S |
| 8843U, // CMPGE_PPzZI_B |
| 8587U, // CMPGE_PPzZI_D |
| 90824U, // CMPGE_PPzZI_H |
| 8971U, // CMPGE_PPzZI_S |
| 533131U, // CMPGE_PPzZZ_B |
| 1057163U, // CMPGE_PPzZZ_D |
| 1614536U, // CMPGE_PPzZZ_H |
| 2106123U, // CMPGE_PPzZZ_S |
| 1057419U, // CMPGE_WIDE_PPzZZ_B |
| 99016U, // CMPGE_WIDE_PPzZZ_H |
| 1057547U, // CMPGE_WIDE_PPzZZ_S |
| 8843U, // CMPGT_PPzZI_B |
| 8587U, // CMPGT_PPzZI_D |
| 90824U, // CMPGT_PPzZI_H |
| 8971U, // CMPGT_PPzZI_S |
| 533131U, // CMPGT_PPzZZ_B |
| 1057163U, // CMPGT_PPzZZ_D |
| 1614536U, // CMPGT_PPzZZ_H |
| 2106123U, // CMPGT_PPzZZ_S |
| 1057419U, // CMPGT_WIDE_PPzZZ_B |
| 99016U, // CMPGT_WIDE_PPzZZ_H |
| 1057547U, // CMPGT_WIDE_PPzZZ_S |
| 6824587U, // CMPHI_PPzZI_B |
| 6824331U, // CMPHI_PPzZI_D |
| 148168U, // CMPHI_PPzZI_H |
| 6824715U, // CMPHI_PPzZI_S |
| 533131U, // CMPHI_PPzZZ_B |
| 1057163U, // CMPHI_PPzZZ_D |
| 1614536U, // CMPHI_PPzZZ_H |
| 2106123U, // CMPHI_PPzZZ_S |
| 1057419U, // CMPHI_WIDE_PPzZZ_B |
| 99016U, // CMPHI_WIDE_PPzZZ_H |
| 1057547U, // CMPHI_WIDE_PPzZZ_S |
| 6824587U, // CMPHS_PPzZI_B |
| 6824331U, // CMPHS_PPzZI_D |
| 148168U, // CMPHS_PPzZI_H |
| 6824715U, // CMPHS_PPzZI_S |
| 533131U, // CMPHS_PPzZZ_B |
| 1057163U, // CMPHS_PPzZZ_D |
| 1614536U, // CMPHS_PPzZZ_H |
| 2106123U, // CMPHS_PPzZZ_S |
| 1057419U, // CMPHS_WIDE_PPzZZ_B |
| 99016U, // CMPHS_WIDE_PPzZZ_H |
| 1057547U, // CMPHS_WIDE_PPzZZ_S |
| 8843U, // CMPLE_PPzZI_B |
| 8587U, // CMPLE_PPzZI_D |
| 90824U, // CMPLE_PPzZI_H |
| 8971U, // CMPLE_PPzZI_S |
| 1057419U, // CMPLE_WIDE_PPzZZ_B |
| 99016U, // CMPLE_WIDE_PPzZZ_H |
| 1057547U, // CMPLE_WIDE_PPzZZ_S |
| 6824587U, // CMPLO_PPzZI_B |
| 6824331U, // CMPLO_PPzZI_D |
| 148168U, // CMPLO_PPzZI_H |
| 6824715U, // CMPLO_PPzZI_S |
| 1057419U, // CMPLO_WIDE_PPzZZ_B |
| 99016U, // CMPLO_WIDE_PPzZZ_H |
| 1057547U, // CMPLO_WIDE_PPzZZ_S |
| 6824587U, // CMPLS_PPzZI_B |
| 6824331U, // CMPLS_PPzZI_D |
| 148168U, // CMPLS_PPzZI_H |
| 6824715U, // CMPLS_PPzZI_S |
| 1057419U, // CMPLS_WIDE_PPzZZ_B |
| 99016U, // CMPLS_WIDE_PPzZZ_H |
| 1057547U, // CMPLS_WIDE_PPzZZ_S |
| 8843U, // CMPLT_PPzZI_B |
| 8587U, // CMPLT_PPzZI_D |
| 90824U, // CMPLT_PPzZI_H |
| 8971U, // CMPLT_PPzZI_S |
| 1057419U, // CMPLT_WIDE_PPzZZ_B |
| 99016U, // CMPLT_WIDE_PPzZZ_H |
| 1057547U, // CMPLT_WIDE_PPzZZ_S |
| 8843U, // CMPNE_PPzZI_B |
| 8587U, // CMPNE_PPzZI_D |
| 90824U, // CMPNE_PPzZI_H |
| 8971U, // CMPNE_PPzZI_S |
| 533131U, // CMPNE_PPzZZ_B |
| 1057163U, // CMPNE_PPzZZ_D |
| 1614536U, // CMPNE_PPzZZ_H |
| 2106123U, // CMPNE_PPzZZ_S |
| 1057419U, // CMPNE_WIDE_PPzZZ_B |
| 99016U, // CMPNE_WIDE_PPzZZ_H |
| 1057547U, // CMPNE_WIDE_PPzZZ_S |
| 0U, // CMP_SWAP_128 |
| 0U, // CMP_SWAP_16 |
| 0U, // CMP_SWAP_32 |
| 0U, // CMP_SWAP_64 |
| 0U, // CMP_SWAP_8 |
| 49673U, // CMTSTv16i8 |
| 197U, // CMTSTv1i64 |
| 57865U, // CMTSTv2i32 |
| 16902U, // CMTSTv2i64 |
| 66058U, // CMTSTv4i16 |
| 25095U, // CMTSTv4i32 |
| 33287U, // CMTSTv8i16 |
| 74250U, // CMTSTv8i8 |
| 0U, // CNOT_ZPmZ_B |
| 0U, // CNOT_ZPmZ_D |
| 0U, // CNOT_ZPmZ_H |
| 1U, // CNOT_ZPmZ_S |
| 18U, // CNTB_XPiI |
| 18U, // CNTD_XPiI |
| 18U, // CNTH_XPiI |
| 645U, // CNTP_XPP_B |
| 389U, // CNTP_XPP_D |
| 325U, // CNTP_XPP_H |
| 773U, // CNTP_XPP_S |
| 18U, // CNTW_XPiI |
| 0U, // CNT_ZPmZ_B |
| 0U, // CNT_ZPmZ_D |
| 0U, // CNT_ZPmZ_H |
| 1U, // CNT_ZPmZ_S |
| 1U, // CNTv16i8 |
| 5U, // CNTv8i8 |
| 389U, // COMPACT_ZPZ_D |
| 773U, // COMPACT_ZPZ_S |
| 18U, // CPY_ZPmI_B |
| 19U, // CPY_ZPmI_D |
| 0U, // CPY_ZPmI_H |
| 19U, // CPY_ZPmI_S |
| 20U, // CPY_ZPmR_B |
| 20U, // CPY_ZPmR_D |
| 2U, // CPY_ZPmR_H |
| 20U, // CPY_ZPmR_S |
| 20U, // CPY_ZPmV_B |
| 20U, // CPY_ZPmV_D |
| 2U, // CPY_ZPmV_H |
| 20U, // CPY_ZPmV_S |
| 2507U, // CPY_ZPzI_B |
| 2571U, // CPY_ZPzI_D |
| 20U, // CPY_ZPzI_H |
| 2635U, // CPY_ZPzI_S |
| 2709U, // CPYi16 |
| 2709U, // CPYi32 |
| 2710U, // CPYi64 |
| 2710U, // CPYi8 |
| 197U, // CRC32Brr |
| 197U, // CRC32CBrr |
| 197U, // CRC32CHrr |
| 197U, // CRC32CWrr |
| 197U, // CRC32CXrr |
| 197U, // CRC32Hrr |
| 197U, // CRC32Wrr |
| 197U, // CRC32Xrr |
| 4202693U, // CSELWr |
| 4202693U, // CSELXr |
| 4202693U, // CSINCWr |
| 4202693U, // CSINCXr |
| 4202693U, // CSINVWr |
| 4202693U, // CSINVXr |
| 4202693U, // CSNEGWr |
| 4202693U, // CSNEGXr |
| 2U, // CTERMEQ_WW |
| 2U, // CTERMEQ_XX |
| 2U, // CTERMNE_WW |
| 2U, // CTERMNE_XX |
| 0U, // CompilerBarrier |
| 0U, // DCPS1 |
| 0U, // DCPS2 |
| 0U, // DCPS3 |
| 0U, // DECB_XPiI |
| 0U, // DECD_XPiI |
| 0U, // DECD_ZPiI |
| 0U, // DECH_XPiI |
| 0U, // DECH_ZPiI |
| 2U, // DECP_XP_B |
| 2U, // DECP_XP_D |
| 2U, // DECP_XP_H |
| 2U, // DECP_XP_S |
| 2U, // DECP_ZP_D |
| 0U, // DECP_ZP_H |
| 2U, // DECP_ZP_S |
| 0U, // DECW_XPiI |
| 0U, // DECW_ZPiI |
| 0U, // DMB |
| 0U, // DRPS |
| 0U, // DSB |
| 0U, // DUPM_ZI |
| 0U, // DUP_ZI_B |
| 0U, // DUP_ZI_D |
| 0U, // DUP_ZI_H |
| 0U, // DUP_ZI_S |
| 2U, // DUP_ZR_B |
| 2U, // DUP_ZR_D |
| 0U, // DUP_ZR_H |
| 2U, // DUP_ZR_S |
| 23U, // DUP_ZZI_B |
| 23U, // DUP_ZZI_D |
| 0U, // DUP_ZZI_H |
| 0U, // DUP_ZZI_Q |
| 23U, // DUP_ZZI_S |
| 2U, // DUPv16i8gpr |
| 2710U, // DUPv16i8lane |
| 2U, // DUPv2i32gpr |
| 2709U, // DUPv2i32lane |
| 2U, // DUPv2i64gpr |
| 2710U, // DUPv2i64lane |
| 2U, // DUPv4i16gpr |
| 2709U, // DUPv4i16lane |
| 2U, // DUPv4i32gpr |
| 2709U, // DUPv4i32lane |
| 2U, // DUPv8i16gpr |
| 2709U, // DUPv8i16lane |
| 2U, // DUPv8i8gpr |
| 2710U, // DUPv8i8lane |
| 0U, // EMITBKEY |
| 0U, // EONWrr |
| 901U, // EONWrs |
| 0U, // EONXrr |
| 901U, // EONXrs |
| 36282889U, // EOR3 |
| 1057157U, // EOR3_ZZZZ_D |
| 0U, // EORBT_ZZZ_B |
| 69U, // EORBT_ZZZ_D |
| 17U, // EORBT_ZZZ_H |
| 133U, // EORBT_ZZZ_S |
| 533131U, // EORS_PPzPP |
| 0U, // EORTB_ZZZ_B |
| 69U, // EORTB_ZZZ_D |
| 17U, // EORTB_ZZZ_H |
| 133U, // EORTB_ZZZ_S |
| 645U, // EORV_VPZ_B |
| 389U, // EORV_VPZ_D |
| 325U, // EORV_VPZ_H |
| 773U, // EORV_VPZ_S |
| 2245U, // EORWri |
| 0U, // EORWrr |
| 901U, // EORWrs |
| 2309U, // EORXri |
| 0U, // EORXrr |
| 901U, // EORXrs |
| 533131U, // EOR_PPzPP |
| 2309U, // EOR_ZI |
| 533128U, // EOR_ZPmZ_B |
| 1057160U, // EOR_ZPmZ_D |
| 1614536U, // EOR_ZPmZ_H |
| 2106120U, // EOR_ZPmZ_S |
| 389U, // EOR_ZZZ |
| 49673U, // EORv16i8 |
| 74250U, // EORv8i8 |
| 0U, // ERET |
| 0U, // ERETAA |
| 0U, // ERETAB |
| 8389U, // EXTRWrri |
| 8389U, // EXTRXrri |
| 6824581U, // EXT_ZZI |
| 23U, // EXT_ZZI_B |
| 107017U, // EXTv16i8 |
| 156170U, // EXTv8i8 |
| 0U, // F128CSEL |
| 197U, // FABD16 |
| 197U, // FABD32 |
| 197U, // FABD64 |
| 1057160U, // FABD_ZPmZ_D |
| 1614536U, // FABD_ZPmZ_H |
| 2106120U, // FABD_ZPmZ_S |
| 57865U, // FABDv2f32 |
| 16902U, // FABDv2f64 |
| 66058U, // FABDv4f16 |
| 25095U, // FABDv4f32 |
| 33287U, // FABDv8f16 |
| 2U, // FABSDr |
| 2U, // FABSHr |
| 2U, // FABSSr |
| 0U, // FABS_ZPmZ_D |
| 0U, // FABS_ZPmZ_H |
| 1U, // FABS_ZPmZ_S |
| 2U, // FABSv2f32 |
| 3U, // FABSv2f64 |
| 3U, // FABSv4f16 |
| 4U, // FABSv4f32 |
| 4U, // FABSv8f16 |
| 197U, // FACGE16 |
| 197U, // FACGE32 |
| 197U, // FACGE64 |
| 1057163U, // FACGE_PPzZZ_D |
| 1614536U, // FACGE_PPzZZ_H |
| 2106123U, // FACGE_PPzZZ_S |
| 57865U, // FACGEv2f32 |
| 16902U, // FACGEv2f64 |
| 66058U, // FACGEv4f16 |
| 25095U, // FACGEv4f32 |
| 33287U, // FACGEv8f16 |
| 197U, // FACGT16 |
| 197U, // FACGT32 |
| 197U, // FACGT64 |
| 1057163U, // FACGT_PPzZZ_D |
| 1614536U, // FACGT_PPzZZ_H |
| 2106123U, // FACGT_PPzZZ_S |
| 57865U, // FACGTv2f32 |
| 16902U, // FACGTv2f64 |
| 66058U, // FACGTv4f16 |
| 25095U, // FACGTv4f32 |
| 33287U, // FACGTv8f16 |
| 1056965U, // FADDA_VPZ_D |
| 6299845U, // FADDA_VPZ_H |
| 2105541U, // FADDA_VPZ_S |
| 197U, // FADDDrr |
| 197U, // FADDHrr |
| 1057160U, // FADDP_ZPmZZ_D |
| 1614536U, // FADDP_ZPmZZ_H |
| 2106120U, // FADDP_ZPmZZ_S |
| 57865U, // FADDPv2f32 |
| 16902U, // FADDPv2f64 |
| 24U, // FADDPv2i16p |
| 2U, // FADDPv2i32p |
| 3U, // FADDPv2i64p |
| 66058U, // FADDPv4f16 |
| 25095U, // FADDPv4f32 |
| 33287U, // FADDPv8f16 |
| 197U, // FADDSrr |
| 389U, // FADDV_VPZ_D |
| 325U, // FADDV_VPZ_H |
| 773U, // FADDV_VPZ_S |
| 7348616U, // FADD_ZPmI_D |
| 164552U, // FADD_ZPmI_H |
| 7349000U, // FADD_ZPmI_S |
| 1057160U, // FADD_ZPmZ_D |
| 1614536U, // FADD_ZPmZ_H |
| 2106120U, // FADD_ZPmZ_S |
| 389U, // FADD_ZZZ_D |
| 8U, // FADD_ZZZ_H |
| 773U, // FADD_ZZZ_S |
| 57865U, // FADDv2f32 |
| 16902U, // FADDv2f64 |
| 66058U, // FADDv4f16 |
| 25095U, // FADDv4f32 |
| 33287U, // FADDv8f16 |
| 101720456U, // FCADD_ZPmZ_D |
| 138977992U, // FCADD_ZPmZ_H |
| 102769416U, // FCADD_ZPmZ_S |
| 3842569U, // FCADDv2f32 |
| 3850758U, // FCADDv2f64 |
| 3858954U, // FCADDv4f16 |
| 3867143U, // FCADDv4f32 |
| 3875335U, // FCADDv8f16 |
| 4202693U, // FCCMPDrr |
| 4202693U, // FCCMPEDrr |
| 4202693U, // FCCMPEHrr |
| 4202693U, // FCCMPESrr |
| 4202693U, // FCCMPHrr |
| 4202693U, // FCCMPSrr |
| 197U, // FCMEQ16 |
| 197U, // FCMEQ32 |
| 197U, // FCMEQ64 |
| 213387U, // FCMEQ_PPzZ0_D |
| 2760U, // FCMEQ_PPzZ0_H |
| 213771U, // FCMEQ_PPzZ0_S |
| 1057163U, // FCMEQ_PPzZZ_D |
| 1614536U, // FCMEQ_PPzZZ_H |
| 2106123U, // FCMEQ_PPzZZ_S |
| 24U, // FCMEQv1i16rz |
| 24U, // FCMEQv1i32rz |
| 24U, // FCMEQv1i64rz |
| 57865U, // FCMEQv2f32 |
| 16902U, // FCMEQv2f64 |
| 25U, // FCMEQv2i32rz |
| 25U, // FCMEQv2i64rz |
| 66058U, // FCMEQv4f16 |
| 25095U, // FCMEQv4f32 |
| 26U, // FCMEQv4i16rz |
| 26U, // FCMEQv4i32rz |
| 33287U, // FCMEQv8f16 |
| 27U, // FCMEQv8i16rz |
| 197U, // FCMGE16 |
| 197U, // FCMGE32 |
| 197U, // FCMGE64 |
| 213387U, // FCMGE_PPzZ0_D |
| 2760U, // FCMGE_PPzZ0_H |
| 213771U, // FCMGE_PPzZ0_S |
| 1057163U, // FCMGE_PPzZZ_D |
| 1614536U, // FCMGE_PPzZZ_H |
| 2106123U, // FCMGE_PPzZZ_S |
| 24U, // FCMGEv1i16rz |
| 24U, // FCMGEv1i32rz |
| 24U, // FCMGEv1i64rz |
| 57865U, // FCMGEv2f32 |
| 16902U, // FCMGEv2f64 |
| 25U, // FCMGEv2i32rz |
| 25U, // FCMGEv2i64rz |
| 66058U, // FCMGEv4f16 |
| 25095U, // FCMGEv4f32 |
| 26U, // FCMGEv4i16rz |
| 26U, // FCMGEv4i32rz |
| 33287U, // FCMGEv8f16 |
| 27U, // FCMGEv8i16rz |
| 197U, // FCMGT16 |
| 197U, // FCMGT32 |
| 197U, // FCMGT64 |
| 213387U, // FCMGT_PPzZ0_D |
| 2760U, // FCMGT_PPzZ0_H |
| 213771U, // FCMGT_PPzZ0_S |
| 1057163U, // FCMGT_PPzZZ_D |
| 1614536U, // FCMGT_PPzZZ_H |
| 2106123U, // FCMGT_PPzZZ_S |
| 24U, // FCMGTv1i16rz |
| 24U, // FCMGTv1i32rz |
| 24U, // FCMGTv1i64rz |
| 57865U, // FCMGTv2f32 |
| 16902U, // FCMGTv2f64 |
| 25U, // FCMGTv2i32rz |
| 25U, // FCMGTv2i64rz |
| 66058U, // FCMGTv4f16 |
| 25095U, // FCMGTv4f32 |
| 26U, // FCMGTv4i16rz |
| 26U, // FCMGTv4i32rz |
| 33287U, // FCMGTv8f16 |
| 27U, // FCMGTv8i16rz |
| 376971336U, // FCMLA_ZPmZZ_D |
| 72049361U, // FCMLA_ZPmZZ_H |
| 377495688U, // FCMLA_ZPmZZ_S |
| 5253521U, // FCMLA_ZZZI_H |
| 71958661U, // FCMLA_ZZZI_S |
| 5939785U, // FCMLAv2f32 |
| 5947974U, // FCMLAv2f64 |
| 5956170U, // FCMLAv4f16 |
| 378241610U, // FCMLAv4f16_indexed |
| 5964359U, // FCMLAv4f32 |
| 378249799U, // FCMLAv4f32_indexed |
| 5972551U, // FCMLAv8f16 |
| 378241607U, // FCMLAv8f16_indexed |
| 213387U, // FCMLE_PPzZ0_D |
| 2760U, // FCMLE_PPzZ0_H |
| 213771U, // FCMLE_PPzZ0_S |
| 24U, // FCMLEv1i16rz |
| 24U, // FCMLEv1i32rz |
| 24U, // FCMLEv1i64rz |
| 25U, // FCMLEv2i32rz |
| 25U, // FCMLEv2i64rz |
| 26U, // FCMLEv4i16rz |
| 26U, // FCMLEv4i32rz |
| 27U, // FCMLEv8i16rz |
| 213387U, // FCMLT_PPzZ0_D |
| 2760U, // FCMLT_PPzZ0_H |
| 213771U, // FCMLT_PPzZ0_S |
| 24U, // FCMLTv1i16rz |
| 24U, // FCMLTv1i32rz |
| 24U, // FCMLTv1i64rz |
| 25U, // FCMLTv2i32rz |
| 25U, // FCMLTv2i64rz |
| 26U, // FCMLTv4i16rz |
| 26U, // FCMLTv4i32rz |
| 27U, // FCMLTv8i16rz |
| 213387U, // FCMNE_PPzZ0_D |
| 2760U, // FCMNE_PPzZ0_H |
| 213771U, // FCMNE_PPzZ0_S |
| 1057163U, // FCMNE_PPzZZ_D |
| 1614536U, // FCMNE_PPzZZ_H |
| 2106123U, // FCMNE_PPzZZ_S |
| 0U, // FCMPDri |
| 2U, // FCMPDrr |
| 0U, // FCMPEDri |
| 2U, // FCMPEDrr |
| 0U, // FCMPEHri |
| 2U, // FCMPEHrr |
| 0U, // FCMPESri |
| 2U, // FCMPESrr |
| 0U, // FCMPHri |
| 2U, // FCMPHrr |
| 0U, // FCMPSri |
| 2U, // FCMPSrr |
| 1057163U, // FCMUO_PPzZZ_D |
| 1614536U, // FCMUO_PPzZZ_H |
| 2106123U, // FCMUO_PPzZZ_S |
| 27U, // FCPY_ZPmI_D |
| 0U, // FCPY_ZPmI_H |
| 27U, // FCPY_ZPmI_S |
| 4202693U, // FCSELDrrr |
| 4202693U, // FCSELHrrr |
| 4202693U, // FCSELSrrr |
| 2U, // FCVTASUWDr |
| 2U, // FCVTASUWHr |
| 2U, // FCVTASUWSr |
| 2U, // FCVTASUXDr |
| 2U, // FCVTASUXHr |
| 2U, // FCVTASUXSr |
| 2U, // FCVTASv1f16 |
| 2U, // FCVTASv1i32 |
| 2U, // FCVTASv1i64 |
| 2U, // FCVTASv2f32 |
| 3U, // FCVTASv2f64 |
| 3U, // FCVTASv4f16 |
| 4U, // FCVTASv4f32 |
| 4U, // FCVTASv8f16 |
| 2U, // FCVTAUUWDr |
| 2U, // FCVTAUUWHr |
| 2U, // FCVTAUUWSr |
| 2U, // FCVTAUUXDr |
| 2U, // FCVTAUUXHr |
| 2U, // FCVTAUUXSr |
| 2U, // FCVTAUv1f16 |
| 2U, // FCVTAUv1i32 |
| 2U, // FCVTAUv1i64 |
| 2U, // FCVTAUv2f32 |
| 3U, // FCVTAUv2f64 |
| 3U, // FCVTAUv4f16 |
| 4U, // FCVTAUv4f32 |
| 4U, // FCVTAUv8f16 |
| 2U, // FCVTDHr |
| 2U, // FCVTDSr |
| 2U, // FCVTHDr |
| 2U, // FCVTHSr |
| 17U, // FCVTLT_ZPmZ_HtoS |
| 1U, // FCVTLT_ZPmZ_StoD |
| 2U, // FCVTLv2i32 |
| 3U, // FCVTLv4i16 |
| 4U, // FCVTLv4i32 |
| 4U, // FCVTLv8i16 |
| 2U, // FCVTMSUWDr |
| 2U, // FCVTMSUWHr |
| 2U, // FCVTMSUWSr |
| 2U, // FCVTMSUXDr |
| 2U, // FCVTMSUXHr |
| 2U, // FCVTMSUXSr |
| 2U, // FCVTMSv1f16 |
| 2U, // FCVTMSv1i32 |
| 2U, // FCVTMSv1i64 |
| 2U, // FCVTMSv2f32 |
| 3U, // FCVTMSv2f64 |
| 3U, // FCVTMSv4f16 |
| 4U, // FCVTMSv4f32 |
| 4U, // FCVTMSv8f16 |
| 2U, // FCVTMUUWDr |
| 2U, // FCVTMUUWHr |
| 2U, // FCVTMUUWSr |
| 2U, // FCVTMUUXDr |
| 2U, // FCVTMUUXHr |
| 2U, // FCVTMUUXSr |
| 2U, // FCVTMUv1f16 |
| 2U, // FCVTMUv1i32 |
| 2U, // FCVTMUv1i64 |
| 2U, // FCVTMUv2f32 |
| 3U, // FCVTMUv2f64 |
| 3U, // FCVTMUv4f16 |
| 4U, // FCVTMUv4f32 |
| 4U, // FCVTMUv8f16 |
| 2U, // FCVTNSUWDr |
| 2U, // FCVTNSUWHr |
| 2U, // FCVTNSUWSr |
| 2U, // FCVTNSUXDr |
| 2U, // FCVTNSUXHr |
| 2U, // FCVTNSUXSr |
| 2U, // FCVTNSv1f16 |
| 2U, // FCVTNSv1i32 |
| 2U, // FCVTNSv1i64 |
| 2U, // FCVTNSv2f32 |
| 3U, // FCVTNSv2f64 |
| 3U, // FCVTNSv4f16 |
| 4U, // FCVTNSv4f32 |
| 4U, // FCVTNSv8f16 |
| 0U, // FCVTNT_ZPmZ_DtoS |
| 0U, // FCVTNT_ZPmZ_StoH |
| 2U, // FCVTNUUWDr |
| 2U, // FCVTNUUWHr |
| 2U, // FCVTNUUWSr |
| 2U, // FCVTNUUXDr |
| 2U, // FCVTNUUXHr |
| 2U, // FCVTNUUXSr |
| 2U, // FCVTNUv1f16 |
| 2U, // FCVTNUv1i32 |
| 2U, // FCVTNUv1i64 |
| 2U, // FCVTNUv2f32 |
| 3U, // FCVTNUv2f64 |
| 3U, // FCVTNUv4f16 |
| 4U, // FCVTNUv4f32 |
| 4U, // FCVTNUv8f16 |
| 3U, // FCVTNv2i32 |
| 4U, // FCVTNv4i16 |
| 3U, // FCVTNv4i32 |
| 4U, // FCVTNv8i16 |
| 2U, // FCVTPSUWDr |
| 2U, // FCVTPSUWHr |
| 2U, // FCVTPSUWSr |
| 2U, // FCVTPSUXDr |
| 2U, // FCVTPSUXHr |
| 2U, // FCVTPSUXSr |
| 2U, // FCVTPSv1f16 |
| 2U, // FCVTPSv1i32 |
| 2U, // FCVTPSv1i64 |
| 2U, // FCVTPSv2f32 |
| 3U, // FCVTPSv2f64 |
| 3U, // FCVTPSv4f16 |
| 4U, // FCVTPSv4f32 |
| 4U, // FCVTPSv8f16 |
| 2U, // FCVTPUUWDr |
| 2U, // FCVTPUUWHr |
| 2U, // FCVTPUUWSr |
| 2U, // FCVTPUUXDr |
| 2U, // FCVTPUUXHr |
| 2U, // FCVTPUUXSr |
| 2U, // FCVTPUv1f16 |
| 2U, // FCVTPUv1i32 |
| 2U, // FCVTPUv1i64 |
| 2U, // FCVTPUv2f32 |
| 3U, // FCVTPUv2f64 |
| 3U, // FCVTPUv4f16 |
| 4U, // FCVTPUv4f32 |
| 4U, // FCVTPUv8f16 |
| 2U, // FCVTSDr |
| 2U, // FCVTSHr |
| 0U, // FCVTXNT_ZPmZ_DtoS |
| 2U, // FCVTXNv1i64 |
| 3U, // FCVTXNv2f32 |
| 3U, // FCVTXNv4f32 |
| 0U, // FCVTX_ZPmZ_DtoS |
| 197U, // FCVTZSSWDri |
| 197U, // FCVTZSSWHri |
| 197U, // FCVTZSSWSri |
| 197U, // FCVTZSSXDri |
| 197U, // FCVTZSSXHri |
| 197U, // FCVTZSSXSri |
| 2U, // FCVTZSUWDr |
| 2U, // FCVTZSUWHr |
| 2U, // FCVTZSUWSr |
| 2U, // FCVTZSUXDr |
| 2U, // FCVTZSUXHr |
| 2U, // FCVTZSUXSr |
| 0U, // FCVTZS_ZPmZ_DtoD |
| 0U, // FCVTZS_ZPmZ_DtoS |
| 17U, // FCVTZS_ZPmZ_HtoD |
| 0U, // FCVTZS_ZPmZ_HtoH |
| 17U, // FCVTZS_ZPmZ_HtoS |
| 1U, // FCVTZS_ZPmZ_StoD |
| 1U, // FCVTZS_ZPmZ_StoS |
| 197U, // FCVTZSd |
| 197U, // FCVTZSh |
| 197U, // FCVTZSs |
| 2U, // FCVTZSv1f16 |
| 2U, // FCVTZSv1i32 |
| 2U, // FCVTZSv1i64 |
| 2U, // FCVTZSv2f32 |
| 3U, // FCVTZSv2f64 |
| 201U, // FCVTZSv2i32_shift |
| 198U, // FCVTZSv2i64_shift |
| 3U, // FCVTZSv4f16 |
| 4U, // FCVTZSv4f32 |
| 202U, // FCVTZSv4i16_shift |
| 199U, // FCVTZSv4i32_shift |
| 4U, // FCVTZSv8f16 |
| 199U, // FCVTZSv8i16_shift |
| 197U, // FCVTZUSWDri |
| 197U, // FCVTZUSWHri |
| 197U, // FCVTZUSWSri |
| 197U, // FCVTZUSXDri |
| 197U, // FCVTZUSXHri |
| 197U, // FCVTZUSXSri |
| 2U, // FCVTZUUWDr |
| 2U, // FCVTZUUWHr |
| 2U, // FCVTZUUWSr |
| 2U, // FCVTZUUXDr |
| 2U, // FCVTZUUXHr |
| 2U, // FCVTZUUXSr |
| 0U, // FCVTZU_ZPmZ_DtoD |
| 0U, // FCVTZU_ZPmZ_DtoS |
| 17U, // FCVTZU_ZPmZ_HtoD |
| 0U, // FCVTZU_ZPmZ_HtoH |
| 17U, // FCVTZU_ZPmZ_HtoS |
| 1U, // FCVTZU_ZPmZ_StoD |
| 1U, // FCVTZU_ZPmZ_StoS |
| 197U, // FCVTZUd |
| 197U, // FCVTZUh |
| 197U, // FCVTZUs |
| 2U, // FCVTZUv1f16 |
| 2U, // FCVTZUv1i32 |
| 2U, // FCVTZUv1i64 |
| 2U, // FCVTZUv2f32 |
| 3U, // FCVTZUv2f64 |
| 201U, // FCVTZUv2i32_shift |
| 198U, // FCVTZUv2i64_shift |
| 3U, // FCVTZUv4f16 |
| 4U, // FCVTZUv4f32 |
| 202U, // FCVTZUv4i16_shift |
| 199U, // FCVTZUv4i32_shift |
| 4U, // FCVTZUv8f16 |
| 199U, // FCVTZUv8i16_shift |
| 0U, // FCVT_ZPmZ_DtoH |
| 0U, // FCVT_ZPmZ_DtoS |
| 17U, // FCVT_ZPmZ_HtoD |
| 17U, // FCVT_ZPmZ_HtoS |
| 1U, // FCVT_ZPmZ_StoD |
| 0U, // FCVT_ZPmZ_StoH |
| 197U, // FDIVDrr |
| 197U, // FDIVHrr |
| 1057160U, // FDIVR_ZPmZ_D |
| 1614536U, // FDIVR_ZPmZ_H |
| 2106120U, // FDIVR_ZPmZ_S |
| 197U, // FDIVSrr |
| 1057160U, // FDIV_ZPmZ_D |
| 1614536U, // FDIV_ZPmZ_H |
| 2106120U, // FDIV_ZPmZ_S |
| 57865U, // FDIVv2f32 |
| 16902U, // FDIVv2f64 |
| 66058U, // FDIVv4f16 |
| 25095U, // FDIVv4f32 |
| 33287U, // FDIVv8f16 |
| 0U, // FDUP_ZI_D |
| 0U, // FDUP_ZI_H |
| 0U, // FDUP_ZI_S |
| 2U, // FEXPA_ZZ_D |
| 0U, // FEXPA_ZZ_H |
| 2U, // FEXPA_ZZ_S |
| 2U, // FJCVTZS |
| 0U, // FLOGB_ZPmZ_D |
| 0U, // FLOGB_ZPmZ_H |
| 1U, // FLOGB_ZPmZ_S |
| 8389U, // FMADDDrrr |
| 8389U, // FMADDHrrr |
| 8389U, // FMADDSrrr |
| 7872584U, // FMAD_ZPmZZ_D |
| 1794769U, // FMAD_ZPmZZ_H |
| 8396936U, // FMAD_ZPmZZ_S |
| 197U, // FMAXDrr |
| 197U, // FMAXHrr |
| 197U, // FMAXNMDrr |
| 197U, // FMAXNMHrr |
| 1057160U, // FMAXNMP_ZPmZZ_D |
| 1614536U, // FMAXNMP_ZPmZZ_H |
| 2106120U, // FMAXNMP_ZPmZZ_S |
| 57865U, // FMAXNMPv2f32 |
| 16902U, // FMAXNMPv2f64 |
| 24U, // FMAXNMPv2i16p |
| 2U, // FMAXNMPv2i32p |
| 3U, // FMAXNMPv2i64p |
| 66058U, // FMAXNMPv4f16 |
| 25095U, // FMAXNMPv4f32 |
| 33287U, // FMAXNMPv8f16 |
| 197U, // FMAXNMSrr |
| 389U, // FMAXNMV_VPZ_D |
| 325U, // FMAXNMV_VPZ_H |
| 773U, // FMAXNMV_VPZ_S |
| 3U, // FMAXNMVv4i16v |
| 4U, // FMAXNMVv4i32v |
| 4U, // FMAXNMVv8i16v |
| 9445768U, // FMAXNM_ZPmI_D |
| 246472U, // FMAXNM_ZPmI_H |
| 9446152U, // FMAXNM_ZPmI_S |
| 1057160U, // FMAXNM_ZPmZ_D |
| 1614536U, // FMAXNM_ZPmZ_H |
| 2106120U, // FMAXNM_ZPmZ_S |
| 57865U, // FMAXNMv2f32 |
| 16902U, // FMAXNMv2f64 |
| 66058U, // FMAXNMv4f16 |
| 25095U, // FMAXNMv4f32 |
| 33287U, // FMAXNMv8f16 |
| 1057160U, // FMAXP_ZPmZZ_D |
| 1614536U, // FMAXP_ZPmZZ_H |
| 2106120U, // FMAXP_ZPmZZ_S |
| 57865U, // FMAXPv2f32 |
| 16902U, // FMAXPv2f64 |
| 24U, // FMAXPv2i16p |
| 2U, // FMAXPv2i32p |
| 3U, // FMAXPv2i64p |
| 66058U, // FMAXPv4f16 |
| 25095U, // FMAXPv4f32 |
| 33287U, // FMAXPv8f16 |
| 197U, // FMAXSrr |
| 389U, // FMAXV_VPZ_D |
| 325U, // FMAXV_VPZ_H |
| 773U, // FMAXV_VPZ_S |
| 3U, // FMAXVv4i16v |
| 4U, // FMAXVv4i32v |
| 4U, // FMAXVv8i16v |
| 9445768U, // FMAX_ZPmI_D |
| 246472U, // FMAX_ZPmI_H |
| 9446152U, // FMAX_ZPmI_S |
| 1057160U, // FMAX_ZPmZ_D |
| 1614536U, // FMAX_ZPmZ_H |
| 2106120U, // FMAX_ZPmZ_S |
| 57865U, // FMAXv2f32 |
| 16902U, // FMAXv2f64 |
| 66058U, // FMAXv4f16 |
| 25095U, // FMAXv4f32 |
| 33287U, // FMAXv8f16 |
| 197U, // FMINDrr |
| 197U, // FMINHrr |
| 197U, // FMINNMDrr |
| 197U, // FMINNMHrr |
| 1057160U, // FMINNMP_ZPmZZ_D |
| 1614536U, // FMINNMP_ZPmZZ_H |
| 2106120U, // FMINNMP_ZPmZZ_S |
| 57865U, // FMINNMPv2f32 |
| 16902U, // FMINNMPv2f64 |
| 24U, // FMINNMPv2i16p |
| 2U, // FMINNMPv2i32p |
| 3U, // FMINNMPv2i64p |
| 66058U, // FMINNMPv4f16 |
| 25095U, // FMINNMPv4f32 |
| 33287U, // FMINNMPv8f16 |
| 197U, // FMINNMSrr |
| 389U, // FMINNMV_VPZ_D |
| 325U, // FMINNMV_VPZ_H |
| 773U, // FMINNMV_VPZ_S |
| 3U, // FMINNMVv4i16v |
| 4U, // FMINNMVv4i32v |
| 4U, // FMINNMVv8i16v |
| 9445768U, // FMINNM_ZPmI_D |
| 246472U, // FMINNM_ZPmI_H |
| 9446152U, // FMINNM_ZPmI_S |
| 1057160U, // FMINNM_ZPmZ_D |
| 1614536U, // FMINNM_ZPmZ_H |
| 2106120U, // FMINNM_ZPmZ_S |
| 57865U, // FMINNMv2f32 |
| 16902U, // FMINNMv2f64 |
| 66058U, // FMINNMv4f16 |
| 25095U, // FMINNMv4f32 |
| 33287U, // FMINNMv8f16 |
| 1057160U, // FMINP_ZPmZZ_D |
| 1614536U, // FMINP_ZPmZZ_H |
| 2106120U, // FMINP_ZPmZZ_S |
| 57865U, // FMINPv2f32 |
| 16902U, // FMINPv2f64 |
| 24U, // FMINPv2i16p |
| 2U, // FMINPv2i32p |
| 3U, // FMINPv2i64p |
| 66058U, // FMINPv4f16 |
| 25095U, // FMINPv4f32 |
| 33287U, // FMINPv8f16 |
| 197U, // FMINSrr |
| 389U, // FMINV_VPZ_D |
| 325U, // FMINV_VPZ_H |
| 773U, // FMINV_VPZ_S |
| 3U, // FMINVv4i16v |
| 4U, // FMINVv4i32v |
| 4U, // FMINVv8i16v |
| 9445768U, // FMIN_ZPmI_D |
| 246472U, // FMIN_ZPmI_H |
| 9446152U, // FMIN_ZPmI_S |
| 1057160U, // FMIN_ZPmZ_D |
| 1614536U, // FMIN_ZPmZ_H |
| 2106120U, // FMIN_ZPmZ_S |
| 57865U, // FMINv2f32 |
| 16902U, // FMINv2f64 |
| 66058U, // FMINv4f16 |
| 25095U, // FMINv4f32 |
| 33287U, // FMINv8f16 |
| 2844U, // FMLAL2lanev4f16 |
| 9142858U, // FMLAL2lanev8f16 |
| 2908U, // FMLAL2v4f16 |
| 66122U, // FMLAL2v8f16 |
| 1704389U, // FMLALB_ZZZI_SHH |
| 453U, // FMLALB_ZZZ_SHH |
| 1704389U, // FMLALT_ZZZI_SHH |
| 453U, // FMLALT_ZZZ_SHH |
| 2844U, // FMLALlanev4f16 |
| 9142858U, // FMLALlanev8f16 |
| 2908U, // FMLALv4f16 |
| 66122U, // FMLALv8f16 |
| 7872584U, // FMLA_ZPmZZ_D |
| 1794769U, // FMLA_ZPmZZ_H |
| 8396936U, // FMLA_ZPmZZ_S |
| 1704005U, // FMLA_ZZZI_D |
| 2449U, // FMLA_ZZZI_H |
| 1704069U, // FMLA_ZZZI_S |
| 9142853U, // FMLAv1i16_indexed |
| 9151045U, // FMLAv1i32_indexed |
| 9167429U, // FMLAv1i64_indexed |
| 57929U, // FMLAv2f32 |
| 16966U, // FMLAv2f64 |
| 9151049U, // FMLAv2i32_indexed |
| 9167430U, // FMLAv2i64_indexed |
| 66122U, // FMLAv4f16 |
| 25159U, // FMLAv4f32 |
| 9142858U, // FMLAv4i16_indexed |
| 9151047U, // FMLAv4i32_indexed |
| 33351U, // FMLAv8f16 |
| 9142855U, // FMLAv8i16_indexed |
| 2844U, // FMLSL2lanev4f16 |
| 9142858U, // FMLSL2lanev8f16 |
| 2908U, // FMLSL2v4f16 |
| 66122U, // FMLSL2v8f16 |
| 1704389U, // FMLSLB_ZZZI_SHH |
| 453U, // FMLSLB_ZZZ_SHH |
| 1704389U, // FMLSLT_ZZZI_SHH |
| 453U, // FMLSLT_ZZZ_SHH |
| 2844U, // FMLSLlanev4f16 |
| 9142858U, // FMLSLlanev8f16 |
| 2908U, // FMLSLv4f16 |
| 66122U, // FMLSLv8f16 |
| 7872584U, // FMLS_ZPmZZ_D |
| 1794769U, // FMLS_ZPmZZ_H |
| 8396936U, // FMLS_ZPmZZ_S |
| 1704005U, // FMLS_ZZZI_D |
| 2449U, // FMLS_ZZZI_H |
| 1704069U, // FMLS_ZZZI_S |
| 9142853U, // FMLSv1i16_indexed |
| 9151045U, // FMLSv1i32_indexed |
| 9167429U, // FMLSv1i64_indexed |
| 57929U, // FMLSv2f32 |
| 16966U, // FMLSv2f64 |
| 9151049U, // FMLSv2i32_indexed |
| 9167430U, // FMLSv2i64_indexed |
| 66122U, // FMLSv4f16 |
| 25159U, // FMLSv4f32 |
| 9142858U, // FMLSv4i16_indexed |
| 9151047U, // FMLSv4i32_indexed |
| 33351U, // FMLSv8f16 |
| 9142855U, // FMLSv8i16_indexed |
| 0U, // FMOVD0 |
| 2710U, // FMOVDXHighr |
| 2U, // FMOVDXr |
| 0U, // FMOVDi |
| 2U, // FMOVDr |
| 0U, // FMOVH0 |
| 2U, // FMOVHWr |
| 2U, // FMOVHXr |
| 0U, // FMOVHi |
| 2U, // FMOVHr |
| 0U, // FMOVS0 |
| 2U, // FMOVSWr |
| 0U, // FMOVSi |
| 2U, // FMOVSr |
| 2U, // FMOVWHr |
| 2U, // FMOVWSr |
| 2U, // FMOVXDHighr |
| 2U, // FMOVXDr |
| 2U, // FMOVXHr |
| 0U, // FMOVv2f32_ns |
| 0U, // FMOVv2f64_ns |
| 0U, // FMOVv4f16_ns |
| 0U, // FMOVv4f32_ns |
| 0U, // FMOVv8f16_ns |
| 7872584U, // FMSB_ZPmZZ_D |
| 1794769U, // FMSB_ZPmZZ_H |
| 8396936U, // FMSB_ZPmZZ_S |
| 8389U, // FMSUBDrrr |
| 8389U, // FMSUBHrrr |
| 8389U, // FMSUBSrrr |
| 197U, // FMULDrr |
| 197U, // FMULHrr |
| 197U, // FMULSrr |
| 197U, // FMULX16 |
| 197U, // FMULX32 |
| 197U, // FMULX64 |
| 1057160U, // FMULX_ZPmZ_D |
| 1614536U, // FMULX_ZPmZ_H |
| 2106120U, // FMULX_ZPmZ_S |
| 10191365U, // FMULXv1i16_indexed |
| 10199557U, // FMULXv1i32_indexed |
| 10215941U, // FMULXv1i64_indexed |
| 57865U, // FMULXv2f32 |
| 16902U, // FMULXv2f64 |
| 10199561U, // FMULXv2i32_indexed |
| 10215942U, // FMULXv2i64_indexed |
| 66058U, // FMULXv4f16 |
| 25095U, // FMULXv4f32 |
| 10191370U, // FMULXv4i16_indexed |
| 10199559U, // FMULXv4i32_indexed |
| 33287U, // FMULXv8f16 |
| 10191367U, // FMULXv8i16_indexed |
| 10494344U, // FMUL_ZPmI_D |
| 262856U, // FMUL_ZPmI_H |
| 10494728U, // FMUL_ZPmI_S |
| 1057160U, // FMUL_ZPmZ_D |
| 1614536U, // FMUL_ZPmZ_H |
| 2106120U, // FMUL_ZPmZ_S |
| 270725U, // FMUL_ZZZI_D |
| 2952U, // FMUL_ZZZI_H |
| 271109U, // FMUL_ZZZI_S |
| 389U, // FMUL_ZZZ_D |
| 8U, // FMUL_ZZZ_H |
| 773U, // FMUL_ZZZ_S |
| 10191365U, // FMULv1i16_indexed |
| 10199557U, // FMULv1i32_indexed |
| 10215941U, // FMULv1i64_indexed |
| 57865U, // FMULv2f32 |
| 16902U, // FMULv2f64 |
| 10199561U, // FMULv2i32_indexed |
| 10215942U, // FMULv2i64_indexed |
| 66058U, // FMULv4f16 |
| 25095U, // FMULv4f32 |
| 10191370U, // FMULv4i16_indexed |
| 10199559U, // FMULv4i32_indexed |
| 33287U, // FMULv8f16 |
| 10191367U, // FMULv8i16_indexed |
| 2U, // FNEGDr |
| 2U, // FNEGHr |
| 2U, // FNEGSr |
| 0U, // FNEG_ZPmZ_D |
| 0U, // FNEG_ZPmZ_H |
| 1U, // FNEG_ZPmZ_S |
| 2U, // FNEGv2f32 |
| 3U, // FNEGv2f64 |
| 3U, // FNEGv4f16 |
| 4U, // FNEGv4f32 |
| 4U, // FNEGv8f16 |
| 8389U, // FNMADDDrrr |
| 8389U, // FNMADDHrrr |
| 8389U, // FNMADDSrrr |
| 7872584U, // FNMAD_ZPmZZ_D |
| 1794769U, // FNMAD_ZPmZZ_H |
| 8396936U, // FNMAD_ZPmZZ_S |
| 7872584U, // FNMLA_ZPmZZ_D |
| 1794769U, // FNMLA_ZPmZZ_H |
| 8396936U, // FNMLA_ZPmZZ_S |
| 7872584U, // FNMLS_ZPmZZ_D |
| 1794769U, // FNMLS_ZPmZZ_H |
| 8396936U, // FNMLS_ZPmZZ_S |
| 7872584U, // FNMSB_ZPmZZ_D |
| 1794769U, // FNMSB_ZPmZZ_H |
| 8396936U, // FNMSB_ZPmZZ_S |
| 8389U, // FNMSUBDrrr |
| 8389U, // FNMSUBHrrr |
| 8389U, // FNMSUBSrrr |
| 197U, // FNMULDrr |
| 197U, // FNMULHrr |
| 197U, // FNMULSrr |
| 2U, // FRECPE_ZZ_D |
| 0U, // FRECPE_ZZ_H |
| 2U, // FRECPE_ZZ_S |
| 2U, // FRECPEv1f16 |
| 2U, // FRECPEv1i32 |
| 2U, // FRECPEv1i64 |
| 2U, // FRECPEv2f32 |
| 3U, // FRECPEv2f64 |
| 3U, // FRECPEv4f16 |
| 4U, // FRECPEv4f32 |
| 4U, // FRECPEv8f16 |
| 197U, // FRECPS16 |
| 197U, // FRECPS32 |
| 197U, // FRECPS64 |
| 389U, // FRECPS_ZZZ_D |
| 8U, // FRECPS_ZZZ_H |
| 773U, // FRECPS_ZZZ_S |
| 57865U, // FRECPSv2f32 |
| 16902U, // FRECPSv2f64 |
| 66058U, // FRECPSv4f16 |
| 25095U, // FRECPSv4f32 |
| 33287U, // FRECPSv8f16 |
| 0U, // FRECPX_ZPmZ_D |
| 0U, // FRECPX_ZPmZ_H |
| 1U, // FRECPX_ZPmZ_S |
| 2U, // FRECPXv1f16 |
| 2U, // FRECPXv1i32 |
| 2U, // FRECPXv1i64 |
| 2U, // FRINT32XDr |
| 2U, // FRINT32XSr |
| 2U, // FRINT32Xv2f32 |
| 3U, // FRINT32Xv2f64 |
| 4U, // FRINT32Xv4f32 |
| 2U, // FRINT32ZDr |
| 2U, // FRINT32ZSr |
| 2U, // FRINT32Zv2f32 |
| 3U, // FRINT32Zv2f64 |
| 4U, // FRINT32Zv4f32 |
| 2U, // FRINT64XDr |
| 2U, // FRINT64XSr |
| 2U, // FRINT64Xv2f32 |
| 3U, // FRINT64Xv2f64 |
| 4U, // FRINT64Xv4f32 |
| 2U, // FRINT64ZDr |
| 2U, // FRINT64ZSr |
| 2U, // FRINT64Zv2f32 |
| 3U, // FRINT64Zv2f64 |
| 4U, // FRINT64Zv4f32 |
| 2U, // FRINTADr |
| 2U, // FRINTAHr |
| 2U, // FRINTASr |
| 0U, // FRINTA_ZPmZ_D |
| 0U, // FRINTA_ZPmZ_H |
| 1U, // FRINTA_ZPmZ_S |
| 2U, // FRINTAv2f32 |
| 3U, // FRINTAv2f64 |
| 3U, // FRINTAv4f16 |
| 4U, // FRINTAv4f32 |
| 4U, // FRINTAv8f16 |
| 2U, // FRINTIDr |
| 2U, // FRINTIHr |
| 2U, // FRINTISr |
| 0U, // FRINTI_ZPmZ_D |
| 0U, // FRINTI_ZPmZ_H |
| 1U, // FRINTI_ZPmZ_S |
| 2U, // FRINTIv2f32 |
| 3U, // FRINTIv2f64 |
| 3U, // FRINTIv4f16 |
| 4U, // FRINTIv4f32 |
| 4U, // FRINTIv8f16 |
| 2U, // FRINTMDr |
| 2U, // FRINTMHr |
| 2U, // FRINTMSr |
| 0U, // FRINTM_ZPmZ_D |
| 0U, // FRINTM_ZPmZ_H |
| 1U, // FRINTM_ZPmZ_S |
| 2U, // FRINTMv2f32 |
| 3U, // FRINTMv2f64 |
| 3U, // FRINTMv4f16 |
| 4U, // FRINTMv4f32 |
| 4U, // FRINTMv8f16 |
| 2U, // FRINTNDr |
| 2U, // FRINTNHr |
| 2U, // FRINTNSr |
| 0U, // FRINTN_ZPmZ_D |
| 0U, // FRINTN_ZPmZ_H |
| 1U, // FRINTN_ZPmZ_S |
| 2U, // FRINTNv2f32 |
| 3U, // FRINTNv2f64 |
| 3U, // FRINTNv4f16 |
| 4U, // FRINTNv4f32 |
| 4U, // FRINTNv8f16 |
| 2U, // FRINTPDr |
| 2U, // FRINTPHr |
| 2U, // FRINTPSr |
| 0U, // FRINTP_ZPmZ_D |
| 0U, // FRINTP_ZPmZ_H |
| 1U, // FRINTP_ZPmZ_S |
| 2U, // FRINTPv2f32 |
| 3U, // FRINTPv2f64 |
| 3U, // FRINTPv4f16 |
| 4U, // FRINTPv4f32 |
| 4U, // FRINTPv8f16 |
| 2U, // FRINTXDr |
| 2U, // FRINTXHr |
| 2U, // FRINTXSr |
| 0U, // FRINTX_ZPmZ_D |
| 0U, // FRINTX_ZPmZ_H |
| 1U, // FRINTX_ZPmZ_S |
| 2U, // FRINTXv2f32 |
| 3U, // FRINTXv2f64 |
| 3U, // FRINTXv4f16 |
| 4U, // FRINTXv4f32 |
| 4U, // FRINTXv8f16 |
| 2U, // FRINTZDr |
| 2U, // FRINTZHr |
| 2U, // FRINTZSr |
| 0U, // FRINTZ_ZPmZ_D |
| 0U, // FRINTZ_ZPmZ_H |
| 1U, // FRINTZ_ZPmZ_S |
| 2U, // FRINTZv2f32 |
| 3U, // FRINTZv2f64 |
| 3U, // FRINTZv4f16 |
| 4U, // FRINTZv4f32 |
| 4U, // FRINTZv8f16 |
| 2U, // FRSQRTE_ZZ_D |
| 0U, // FRSQRTE_ZZ_H |
| 2U, // FRSQRTE_ZZ_S |
| 2U, // FRSQRTEv1f16 |
| 2U, // FRSQRTEv1i32 |
| 2U, // FRSQRTEv1i64 |
| 2U, // FRSQRTEv2f32 |
| 3U, // FRSQRTEv2f64 |
| 3U, // FRSQRTEv4f16 |
| 4U, // FRSQRTEv4f32 |
| 4U, // FRSQRTEv8f16 |
| 197U, // FRSQRTS16 |
| 197U, // FRSQRTS32 |
| 197U, // FRSQRTS64 |
| 389U, // FRSQRTS_ZZZ_D |
| 8U, // FRSQRTS_ZZZ_H |
| 773U, // FRSQRTS_ZZZ_S |
| 57865U, // FRSQRTSv2f32 |
| 16902U, // FRSQRTSv2f64 |
| 66058U, // FRSQRTSv4f16 |
| 25095U, // FRSQRTSv4f32 |
| 33287U, // FRSQRTSv8f16 |
| 1057160U, // FSCALE_ZPmZ_D |
| 1614536U, // FSCALE_ZPmZ_H |
| 2106120U, // FSCALE_ZPmZ_S |
| 2U, // FSQRTDr |
| 2U, // FSQRTHr |
| 2U, // FSQRTSr |
| 0U, // FSQRT_ZPmZ_D |
| 0U, // FSQRT_ZPmZ_H |
| 1U, // FSQRT_ZPmZ_S |
| 2U, // FSQRTv2f32 |
| 3U, // FSQRTv2f64 |
| 3U, // FSQRTv4f16 |
| 4U, // FSQRTv4f32 |
| 4U, // FSQRTv8f16 |
| 197U, // FSUBDrr |
| 197U, // FSUBHrr |
| 7348616U, // FSUBR_ZPmI_D |
| 164552U, // FSUBR_ZPmI_H |
| 7349000U, // FSUBR_ZPmI_S |
| 1057160U, // FSUBR_ZPmZ_D |
| 1614536U, // FSUBR_ZPmZ_H |
| 2106120U, // FSUBR_ZPmZ_S |
| 197U, // FSUBSrr |
| 7348616U, // FSUB_ZPmI_D |
| 164552U, // FSUB_ZPmI_H |
| 7349000U, // FSUB_ZPmI_S |
| 1057160U, // FSUB_ZPmZ_D |
| 1614536U, // FSUB_ZPmZ_H |
| 2106120U, // FSUB_ZPmZ_S |
| 389U, // FSUB_ZZZ_D |
| 8U, // FSUB_ZZZ_H |
| 773U, // FSUB_ZZZ_S |
| 57865U, // FSUBv2f32 |
| 16902U, // FSUBv2f64 |
| 66058U, // FSUBv4f16 |
| 25095U, // FSUBv4f32 |
| 33287U, // FSUBv8f16 |
| 8581U, // FTMAD_ZZI_D |
| 90824U, // FTMAD_ZZI_H |
| 8965U, // FTMAD_ZZI_S |
| 389U, // FTSMUL_ZZZ_D |
| 8U, // FTSMUL_ZZZ_H |
| 773U, // FTSMUL_ZZZ_S |
| 389U, // FTSSEL_ZZZ_D |
| 8U, // FTSSEL_ZZZ_H |
| 773U, // FTSSEL_ZZZ_S |
| 125253U, // GLD1B_D_IMM_REAL |
| 3013U, // GLD1B_D_REAL |
| 3077U, // GLD1B_D_SXTW_REAL |
| 3141U, // GLD1B_D_UXTW_REAL |
| 125253U, // GLD1B_S_IMM_REAL |
| 3205U, // GLD1B_S_SXTW_REAL |
| 3269U, // GLD1B_S_UXTW_REAL |
| 126213U, // GLD1D_IMM_REAL |
| 3013U, // GLD1D_REAL |
| 3397U, // GLD1D_SCALED_REAL |
| 3077U, // GLD1D_SXTW_REAL |
| 3461U, // GLD1D_SXTW_SCALED_REAL |
| 3141U, // GLD1D_UXTW_REAL |
| 3525U, // GLD1D_UXTW_SCALED_REAL |
| 126469U, // GLD1H_D_IMM_REAL |
| 3013U, // GLD1H_D_REAL |
| 3653U, // GLD1H_D_SCALED_REAL |
| 3077U, // GLD1H_D_SXTW_REAL |
| 3717U, // GLD1H_D_SXTW_SCALED_REAL |
| 3141U, // GLD1H_D_UXTW_REAL |
| 3781U, // GLD1H_D_UXTW_SCALED_REAL |
| 126469U, // GLD1H_S_IMM_REAL |
| 3205U, // GLD1H_S_SXTW_REAL |
| 3845U, // GLD1H_S_SXTW_SCALED_REAL |
| 3269U, // GLD1H_S_UXTW_REAL |
| 3909U, // GLD1H_S_UXTW_SCALED_REAL |
| 125253U, // GLD1SB_D_IMM_REAL |
| 3013U, // GLD1SB_D_REAL |
| 3077U, // GLD1SB_D_SXTW_REAL |
| 3141U, // GLD1SB_D_UXTW_REAL |
| 125253U, // GLD1SB_S_IMM_REAL |
| 3205U, // GLD1SB_S_SXTW_REAL |
| 3269U, // GLD1SB_S_UXTW_REAL |
| 126469U, // GLD1SH_D_IMM_REAL |
| 3013U, // GLD1SH_D_REAL |
| 3653U, // GLD1SH_D_SCALED_REAL |
| 3077U, // GLD1SH_D_SXTW_REAL |
| 3717U, // GLD1SH_D_SXTW_SCALED_REAL |
| 3141U, // GLD1SH_D_UXTW_REAL |
| 3781U, // GLD1SH_D_UXTW_SCALED_REAL |
| 126469U, // GLD1SH_S_IMM_REAL |
| 3205U, // GLD1SH_S_SXTW_REAL |
| 3845U, // GLD1SH_S_SXTW_SCALED_REAL |
| 3269U, // GLD1SH_S_UXTW_REAL |
| 3909U, // GLD1SH_S_UXTW_SCALED_REAL |
| 126853U, // GLD1SW_D_IMM_REAL |
| 3013U, // GLD1SW_D_REAL |
| 4037U, // GLD1SW_D_SCALED_REAL |
| 3077U, // GLD1SW_D_SXTW_REAL |
| 4101U, // GLD1SW_D_SXTW_SCALED_REAL |
| 3141U, // GLD1SW_D_UXTW_REAL |
| 4165U, // GLD1SW_D_UXTW_SCALED_REAL |
| 126853U, // GLD1W_D_IMM_REAL |
| 3013U, // GLD1W_D_REAL |
| 4037U, // GLD1W_D_SCALED_REAL |
| 3077U, // GLD1W_D_SXTW_REAL |
| 4101U, // GLD1W_D_SXTW_SCALED_REAL |
| 3141U, // GLD1W_D_UXTW_REAL |
| 4165U, // GLD1W_D_UXTW_SCALED_REAL |
| 126853U, // GLD1W_IMM_REAL |
| 3205U, // GLD1W_SXTW_REAL |
| 4229U, // GLD1W_SXTW_SCALED_REAL |
| 3269U, // GLD1W_UXTW_REAL |
| 4293U, // GLD1W_UXTW_SCALED_REAL |
| 125253U, // GLDFF1B_D_IMM_REAL |
| 3013U, // GLDFF1B_D_REAL |
| 3077U, // GLDFF1B_D_SXTW_REAL |
| 3141U, // GLDFF1B_D_UXTW_REAL |
| 125253U, // GLDFF1B_S_IMM_REAL |
| 3205U, // GLDFF1B_S_SXTW_REAL |
| 3269U, // GLDFF1B_S_UXTW_REAL |
| 126213U, // GLDFF1D_IMM_REAL |
| 3013U, // GLDFF1D_REAL |
| 3397U, // GLDFF1D_SCALED_REAL |
| 3077U, // GLDFF1D_SXTW_REAL |
| 3461U, // GLDFF1D_SXTW_SCALED_REAL |
| 3141U, // GLDFF1D_UXTW_REAL |
| 3525U, // GLDFF1D_UXTW_SCALED_REAL |
| 126469U, // GLDFF1H_D_IMM_REAL |
| 3013U, // GLDFF1H_D_REAL |
| 3653U, // GLDFF1H_D_SCALED_REAL |
| 3077U, // GLDFF1H_D_SXTW_REAL |
| 3717U, // GLDFF1H_D_SXTW_SCALED_REAL |
| 3141U, // GLDFF1H_D_UXTW_REAL |
| 3781U, // GLDFF1H_D_UXTW_SCALED_REAL |
| 126469U, // GLDFF1H_S_IMM_REAL |
| 3205U, // GLDFF1H_S_SXTW_REAL |
| 3845U, // GLDFF1H_S_SXTW_SCALED_REAL |
| 3269U, // GLDFF1H_S_UXTW_REAL |
| 3909U, // GLDFF1H_S_UXTW_SCALED_REAL |
| 125253U, // GLDFF1SB_D_IMM_REAL |
| 3013U, // GLDFF1SB_D_REAL |
| 3077U, // GLDFF1SB_D_SXTW_REAL |
| 3141U, // GLDFF1SB_D_UXTW_REAL |
| 125253U, // GLDFF1SB_S_IMM_REAL |
| 3205U, // GLDFF1SB_S_SXTW_REAL |
| 3269U, // GLDFF1SB_S_UXTW_REAL |
| 126469U, // GLDFF1SH_D_IMM_REAL |
| 3013U, // GLDFF1SH_D_REAL |
| 3653U, // GLDFF1SH_D_SCALED_REAL |
| 3077U, // GLDFF1SH_D_SXTW_REAL |
| 3717U, // GLDFF1SH_D_SXTW_SCALED_REAL |
| 3141U, // GLDFF1SH_D_UXTW_REAL |
| 3781U, // GLDFF1SH_D_UXTW_SCALED_REAL |
| 126469U, // GLDFF1SH_S_IMM_REAL |
| 3205U, // GLDFF1SH_S_SXTW_REAL |
| 3845U, // GLDFF1SH_S_SXTW_SCALED_REAL |
| 3269U, // GLDFF1SH_S_UXTW_REAL |
| 3909U, // GLDFF1SH_S_UXTW_SCALED_REAL |
| 126853U, // GLDFF1SW_D_IMM_REAL |
| 3013U, // GLDFF1SW_D_REAL |
| 4037U, // GLDFF1SW_D_SCALED_REAL |
| 3077U, // GLDFF1SW_D_SXTW_REAL |
| 4101U, // GLDFF1SW_D_SXTW_SCALED_REAL |
| 3141U, // GLDFF1SW_D_UXTW_REAL |
| 4165U, // GLDFF1SW_D_UXTW_SCALED_REAL |
| 126853U, // GLDFF1W_D_IMM_REAL |
| 3013U, // GLDFF1W_D_REAL |
| 4037U, // GLDFF1W_D_SCALED_REAL |
| 3077U, // GLDFF1W_D_SXTW_REAL |
| 4101U, // GLDFF1W_D_SXTW_SCALED_REAL |
| 3141U, // GLDFF1W_D_UXTW_REAL |
| 4165U, // GLDFF1W_D_UXTW_SCALED_REAL |
| 126853U, // GLDFF1W_IMM_REAL |
| 3205U, // GLDFF1W_SXTW_REAL |
| 4229U, // GLDFF1W_SXTW_SCALED_REAL |
| 3269U, // GLDFF1W_UXTW_REAL |
| 4293U, // GLDFF1W_UXTW_SCALED_REAL |
| 197U, // GMI |
| 0U, // HINT |
| 1057163U, // HISTCNT_ZPzZZ_D |
| 2106123U, // HISTCNT_ZPzZZ_S |
| 645U, // HISTSEG_ZZZ |
| 0U, // HLT |
| 0U, // HVC |
| 0U, // HWASAN_CHECK_MEMACCESS |
| 0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES |
| 0U, // INCB_XPiI |
| 0U, // INCD_XPiI |
| 0U, // INCD_ZPiI |
| 0U, // INCH_XPiI |
| 0U, // INCH_ZPiI |
| 2U, // INCP_XP_B |
| 2U, // INCP_XP_D |
| 2U, // INCP_XP_H |
| 2U, // INCP_XP_S |
| 2U, // INCP_ZP_D |
| 0U, // INCP_ZP_H |
| 2U, // INCP_ZP_S |
| 0U, // INCW_XPiI |
| 0U, // INCW_ZPiI |
| 197U, // INDEX_II_B |
| 197U, // INDEX_II_D |
| 12U, // INDEX_II_H |
| 197U, // INDEX_II_S |
| 197U, // INDEX_IR_B |
| 197U, // INDEX_IR_D |
| 12U, // INDEX_IR_H |
| 197U, // INDEX_IR_S |
| 197U, // INDEX_RI_B |
| 197U, // INDEX_RI_D |
| 12U, // INDEX_RI_H |
| 197U, // INDEX_RI_S |
| 197U, // INDEX_RR_B |
| 197U, // INDEX_RR_D |
| 12U, // INDEX_RR_H |
| 197U, // INDEX_RR_S |
| 2U, // INSR_ZR_B |
| 2U, // INSR_ZR_D |
| 0U, // INSR_ZR_H |
| 2U, // INSR_ZR_S |
| 2U, // INSR_ZV_B |
| 2U, // INSR_ZV_D |
| 0U, // INSR_ZV_H |
| 2U, // INSR_ZV_S |
| 2U, // INSvi16gpr |
| 2453U, // INSvi16lane |
| 2U, // INSvi32gpr |
| 2453U, // INSvi32lane |
| 2U, // INSvi64gpr |
| 2454U, // INSvi64lane |
| 2U, // INSvi8gpr |
| 2454U, // INSvi8lane |
| 197U, // IRG |
| 0U, // IRGstack |
| 0U, // ISB |
| 0U, // JumpTableDest16 |
| 0U, // JumpTableDest32 |
| 0U, // JumpTableDest8 |
| 645U, // LASTA_RPZ_B |
| 389U, // LASTA_RPZ_D |
| 325U, // LASTA_RPZ_H |
| 773U, // LASTA_RPZ_S |
| 645U, // LASTA_VPZ_B |
| 389U, // LASTA_VPZ_D |
| 325U, // LASTA_VPZ_H |
| 773U, // LASTA_VPZ_S |
| 645U, // LASTB_RPZ_B |
| 389U, // LASTB_RPZ_D |
| 325U, // LASTB_RPZ_H |
| 773U, // LASTB_RPZ_S |
| 645U, // LASTB_VPZ_B |
| 389U, // LASTB_VPZ_D |
| 325U, // LASTB_VPZ_H |
| 773U, // LASTB_VPZ_S |
| 4357U, // LD1B |
| 4357U, // LD1B_D |
| 280901U, // LD1B_D_IMM |
| 4357U, // LD1B_H |
| 280901U, // LD1B_H_IMM |
| 280901U, // LD1B_IMM |
| 4357U, // LD1B_S |
| 280901U, // LD1B_S_IMM |
| 4421U, // LD1D |
| 280901U, // LD1D_IMM |
| 0U, // LD1Fourv16b |
| 0U, // LD1Fourv16b_POST |
| 0U, // LD1Fourv1d |
| 0U, // LD1Fourv1d_POST |
| 0U, // LD1Fourv2d |
| 0U, // LD1Fourv2d_POST |
| 0U, // LD1Fourv2s |
| 0U, // LD1Fourv2s_POST |
| 0U, // LD1Fourv4h |
| 0U, // LD1Fourv4h_POST |
| 0U, // LD1Fourv4s |
| 0U, // LD1Fourv4s_POST |
| 0U, // LD1Fourv8b |
| 0U, // LD1Fourv8b_POST |
| 0U, // LD1Fourv8h |
| 0U, // LD1Fourv8h_POST |
| 4485U, // LD1H |
| 4485U, // LD1H_D |
| 280901U, // LD1H_D_IMM |
| 280901U, // LD1H_IMM |
| 4485U, // LD1H_S |
| 280901U, // LD1H_S_IMM |
| 0U, // LD1Onev16b |
| 0U, // LD1Onev16b_POST |
| 0U, // LD1Onev1d |
| 0U, // LD1Onev1d_POST |
| 0U, // LD1Onev2d |
| 0U, // LD1Onev2d_POST |
| 0U, // LD1Onev2s |
| 0U, // LD1Onev2s_POST |
| 0U, // LD1Onev4h |
| 0U, // LD1Onev4h_POST |
| 0U, // LD1Onev4s |
| 0U, // LD1Onev4s_POST |
| 0U, // LD1Onev8b |
| 0U, // LD1Onev8b_POST |
| 0U, // LD1Onev8h |
| 0U, // LD1Onev8h_POST |
| 125253U, // LD1RB_D_IMM |
| 125253U, // LD1RB_H_IMM |
| 125253U, // LD1RB_IMM |
| 125253U, // LD1RB_S_IMM |
| 126213U, // LD1RD_IMM |
| 126469U, // LD1RH_D_IMM |
| 126469U, // LD1RH_IMM |
| 126469U, // LD1RH_S_IMM |
| 4357U, // LD1RQ_B |
| 127429U, // LD1RQ_B_IMM |
| 4421U, // LD1RQ_D |
| 127429U, // LD1RQ_D_IMM |
| 4485U, // LD1RQ_H |
| 127429U, // LD1RQ_H_IMM |
| 4613U, // LD1RQ_W |
| 127429U, // LD1RQ_W_IMM |
| 125253U, // LD1RSB_D_IMM |
| 125253U, // LD1RSB_H_IMM |
| 125253U, // LD1RSB_S_IMM |
| 126469U, // LD1RSH_D_IMM |
| 126469U, // LD1RSH_S_IMM |
| 126853U, // LD1RSW_IMM |
| 126853U, // LD1RW_D_IMM |
| 126853U, // LD1RW_IMM |
| 0U, // LD1Rv16b |
| 0U, // LD1Rv16b_POST |
| 0U, // LD1Rv1d |
| 0U, // LD1Rv1d_POST |
| 0U, // LD1Rv2d |
| 0U, // LD1Rv2d_POST |
| 0U, // LD1Rv2s |
| 0U, // LD1Rv2s_POST |
| 0U, // LD1Rv4h |
| 0U, // LD1Rv4h_POST |
| 0U, // LD1Rv4s |
| 0U, // LD1Rv4s_POST |
| 0U, // LD1Rv8b |
| 0U, // LD1Rv8b_POST |
| 0U, // LD1Rv8h |
| 0U, // LD1Rv8h_POST |
| 4357U, // LD1SB_D |
| 280901U, // LD1SB_D_IMM |
| 4357U, // LD1SB_H |
| 280901U, // LD1SB_H_IMM |
| 4357U, // LD1SB_S |
| 280901U, // LD1SB_S_IMM |
| 4485U, // LD1SH_D |
| 280901U, // LD1SH_D_IMM |
| 4485U, // LD1SH_S |
| 280901U, // LD1SH_S_IMM |
| 4613U, // LD1SW_D |
| 280901U, // LD1SW_D_IMM |
| 0U, // LD1Threev16b |
| 0U, // LD1Threev16b_POST |
| 0U, // LD1Threev1d |
| 0U, // LD1Threev1d_POST |
| 0U, // LD1Threev2d |
| 0U, // LD1Threev2d_POST |
| 0U, // LD1Threev2s |
| 0U, // LD1Threev2s_POST |
| 0U, // LD1Threev4h |
| 0U, // LD1Threev4h_POST |
| 0U, // LD1Threev4s |
| 0U, // LD1Threev4s_POST |
| 0U, // LD1Threev8b |
| 0U, // LD1Threev8b_POST |
| 0U, // LD1Threev8h |
| 0U, // LD1Threev8h_POST |
| 0U, // LD1Twov16b |
| 0U, // LD1Twov16b_POST |
| 0U, // LD1Twov1d |
| 0U, // LD1Twov1d_POST |
| 0U, // LD1Twov2d |
| 0U, // LD1Twov2d_POST |
| 0U, // LD1Twov2s |
| 0U, // LD1Twov2s_POST |
| 0U, // LD1Twov4h |
| 0U, // LD1Twov4h_POST |
| 0U, // LD1Twov4s |
| 0U, // LD1Twov4s_POST |
| 0U, // LD1Twov8b |
| 0U, // LD1Twov8b_POST |
| 0U, // LD1Twov8h |
| 0U, // LD1Twov8h_POST |
| 4613U, // LD1W |
| 4613U, // LD1W_D |
| 280901U, // LD1W_D_IMM |
| 280901U, // LD1W_IMM |
| 0U, // LD1i16 |
| 0U, // LD1i16_POST |
| 0U, // LD1i32 |
| 0U, // LD1i32_POST |
| 0U, // LD1i64 |
| 0U, // LD1i64_POST |
| 0U, // LD1i8 |
| 0U, // LD1i8_POST |
| 4357U, // LD2B |
| 282117U, // LD2B_IMM |
| 4421U, // LD2D |
| 282117U, // LD2D_IMM |
| 4485U, // LD2H |
| 282117U, // LD2H_IMM |
| 0U, // LD2Rv16b |
| 0U, // LD2Rv16b_POST |
| 0U, // LD2Rv1d |
| 0U, // LD2Rv1d_POST |
| 0U, // LD2Rv2d |
| 0U, // LD2Rv2d_POST |
| 0U, // LD2Rv2s |
| 0U, // LD2Rv2s_POST |
| 0U, // LD2Rv4h |
| 0U, // LD2Rv4h_POST |
| 0U, // LD2Rv4s |
| 0U, // LD2Rv4s_POST |
| 0U, // LD2Rv8b |
| 0U, // LD2Rv8b_POST |
| 0U, // LD2Rv8h |
| 0U, // LD2Rv8h_POST |
| 0U, // LD2Twov16b |
| 0U, // LD2Twov16b_POST |
| 0U, // LD2Twov2d |
| 0U, // LD2Twov2d_POST |
| 0U, // LD2Twov2s |
| 0U, // LD2Twov2s_POST |
| 0U, // LD2Twov4h |
| 0U, // LD2Twov4h_POST |
| 0U, // LD2Twov4s |
| 0U, // LD2Twov4s_POST |
| 0U, // LD2Twov8b |
| 0U, // LD2Twov8b_POST |
| 0U, // LD2Twov8h |
| 0U, // LD2Twov8h_POST |
| 4613U, // LD2W |
| 282117U, // LD2W_IMM |
| 0U, // LD2i16 |
| 0U, // LD2i16_POST |
| 0U, // LD2i32 |
| 0U, // LD2i32_POST |
| 0U, // LD2i64 |
| 0U, // LD2i64_POST |
| 0U, // LD2i8 |
| 0U, // LD2i8_POST |
| 4357U, // LD3B |
| 4677U, // LD3B_IMM |
| 4421U, // LD3D |
| 4677U, // LD3D_IMM |
| 4485U, // LD3H |
| 4677U, // LD3H_IMM |
| 0U, // LD3Rv16b |
| 0U, // LD3Rv16b_POST |
| 0U, // LD3Rv1d |
| 0U, // LD3Rv1d_POST |
| 0U, // LD3Rv2d |
| 0U, // LD3Rv2d_POST |
| 0U, // LD3Rv2s |
| 0U, // LD3Rv2s_POST |
| 0U, // LD3Rv4h |
| 0U, // LD3Rv4h_POST |
| 0U, // LD3Rv4s |
| 0U, // LD3Rv4s_POST |
| 0U, // LD3Rv8b |
| 0U, // LD3Rv8b_POST |
| 0U, // LD3Rv8h |
| 0U, // LD3Rv8h_POST |
| 0U, // LD3Threev16b |
| 0U, // LD3Threev16b_POST |
| 0U, // LD3Threev2d |
| 0U, // LD3Threev2d_POST |
| 0U, // LD3Threev2s |
| 0U, // LD3Threev2s_POST |
| 0U, // LD3Threev4h |
| 0U, // LD3Threev4h_POST |
| 0U, // LD3Threev4s |
| 0U, // LD3Threev4s_POST |
| 0U, // LD3Threev8b |
| 0U, // LD3Threev8b_POST |
| 0U, // LD3Threev8h |
| 0U, // LD3Threev8h_POST |
| 4613U, // LD3W |
| 4677U, // LD3W_IMM |
| 0U, // LD3i16 |
| 0U, // LD3i16_POST |
| 0U, // LD3i32 |
| 0U, // LD3i32_POST |
| 0U, // LD3i64 |
| 0U, // LD3i64_POST |
| 0U, // LD3i8 |
| 0U, // LD3i8_POST |
| 4357U, // LD4B |
| 282501U, // LD4B_IMM |
| 4421U, // LD4D |
| 282501U, // LD4D_IMM |
| 0U, // LD4Fourv16b |
| 0U, // LD4Fourv16b_POST |
| 0U, // LD4Fourv2d |
| 0U, // LD4Fourv2d_POST |
| 0U, // LD4Fourv2s |
| 0U, // LD4Fourv2s_POST |
| 0U, // LD4Fourv4h |
| 0U, // LD4Fourv4h_POST |
| 0U, // LD4Fourv4s |
| 0U, // LD4Fourv4s_POST |
| 0U, // LD4Fourv8b |
| 0U, // LD4Fourv8b_POST |
| 0U, // LD4Fourv8h |
| 0U, // LD4Fourv8h_POST |
| 4485U, // LD4H |
| 282501U, // LD4H_IMM |
| 0U, // LD4Rv16b |
| 0U, // LD4Rv16b_POST |
| 0U, // LD4Rv1d |
| 0U, // LD4Rv1d_POST |
| 0U, // LD4Rv2d |
| 0U, // LD4Rv2d_POST |
| 0U, // LD4Rv2s |
| 0U, // LD4Rv2s_POST |
| 0U, // LD4Rv4h |
| 0U, // LD4Rv4h_POST |
| 0U, // LD4Rv4s |
| 0U, // LD4Rv4s_POST |
| 0U, // LD4Rv8b |
| 0U, // LD4Rv8b_POST |
| 0U, // LD4Rv8h |
| 0U, // LD4Rv8h_POST |
| 4613U, // LD4W |
| 282501U, // LD4W_IMM |
| 0U, // LD4i16 |
| 0U, // LD4i16_POST |
| 0U, // LD4i32 |
| 0U, // LD4i32_POST |
| 0U, // LD4i64 |
| 0U, // LD4i64_POST |
| 0U, // LD4i8 |
| 0U, // LD4i8_POST |
| 0U, // LDADDAB |
| 0U, // LDADDAH |
| 0U, // LDADDALB |
| 0U, // LDADDALH |
| 0U, // LDADDALW |
| 0U, // LDADDALX |
| 0U, // LDADDAW |
| 0U, // LDADDAX |
| 0U, // LDADDB |
| 0U, // LDADDH |
| 0U, // LDADDLB |
| 0U, // LDADDLH |
| 0U, // LDADDLW |
| 0U, // LDADDLX |
| 0U, // LDADDW |
| 0U, // LDADDX |
| 28U, // LDAPRB |
| 28U, // LDAPRH |
| 28U, // LDAPRW |
| 28U, // LDAPRX |
| 123077U, // LDAPURBi |
| 123077U, // LDAPURHi |
| 123077U, // LDAPURSBWi |
| 123077U, // LDAPURSBXi |
| 123077U, // LDAPURSHWi |
| 123077U, // LDAPURSHXi |
| 123077U, // LDAPURSWi |
| 123077U, // LDAPURXi |
| 123077U, // LDAPURi |
| 28U, // LDARB |
| 28U, // LDARH |
| 28U, // LDARW |
| 28U, // LDARX |
| 123085U, // LDAXPW |
| 123085U, // LDAXPX |
| 28U, // LDAXRB |
| 28U, // LDAXRH |
| 28U, // LDAXRW |
| 28U, // LDAXRX |
| 0U, // LDCLRAB |
| 0U, // LDCLRAH |
| 0U, // LDCLRALB |
| 0U, // LDCLRALH |
| 0U, // LDCLRALW |
| 0U, // LDCLRALX |
| 0U, // LDCLRAW |
| 0U, // LDCLRAX |
| 0U, // LDCLRB |
| 0U, // LDCLRH |
| 0U, // LDCLRLB |
| 0U, // LDCLRLH |
| 0U, // LDCLRLW |
| 0U, // LDCLRLX |
| 0U, // LDCLRW |
| 0U, // LDCLRX |
| 0U, // LDEORAB |
| 0U, // LDEORAH |
| 0U, // LDEORALB |
| 0U, // LDEORALH |
| 0U, // LDEORALW |
| 0U, // LDEORALX |
| 0U, // LDEORAW |
| 0U, // LDEORAX |
| 0U, // LDEORB |
| 0U, // LDEORH |
| 0U, // LDEORLB |
| 0U, // LDEORLH |
| 0U, // LDEORLW |
| 0U, // LDEORLX |
| 0U, // LDEORW |
| 0U, // LDEORX |
| 4357U, // LDFF1B_D_REAL |
| 4357U, // LDFF1B_H_REAL |
| 4357U, // LDFF1B_REAL |
| 4357U, // LDFF1B_S_REAL |
| 4421U, // LDFF1D_REAL |
| 4485U, // LDFF1H_D_REAL |
| 4485U, // LDFF1H_REAL |
| 4485U, // LDFF1H_S_REAL |
| 4357U, // LDFF1SB_D_REAL |
| 4357U, // LDFF1SB_H_REAL |
| 4357U, // LDFF1SB_S_REAL |
| 4485U, // LDFF1SH_D_REAL |
| 4485U, // LDFF1SH_S_REAL |
| 4613U, // LDFF1SW_D_REAL |
| 4613U, // LDFF1W_D_REAL |
| 4613U, // LDFF1W_REAL |
| 127429U, // LDG |
| 28U, // LDGM |
| 28U, // LDLARB |
| 28U, // LDLARH |
| 28U, // LDLARW |
| 28U, // LDLARX |
| 280901U, // LDNF1B_D_IMM |
| 280901U, // LDNF1B_H_IMM |
| 280901U, // LDNF1B_IMM |
| 280901U, // LDNF1B_S_IMM |
| 280901U, // LDNF1D_IMM |
| 280901U, // LDNF1H_D_IMM |
| 280901U, // LDNF1H_IMM |
| 280901U, // LDNF1H_S_IMM |
| 280901U, // LDNF1SB_D_IMM |
| 280901U, // LDNF1SB_H_IMM |
| 280901U, // LDNF1SB_S_IMM |
| 280901U, // LDNF1SH_D_IMM |
| 280901U, // LDNF1SH_S_IMM |
| 280901U, // LDNF1SW_D_IMM |
| 280901U, // LDNF1W_D_IMM |
| 280901U, // LDNF1W_IMM |
| 11018445U, // LDNPDi |
| 11542733U, // LDNPQi |
| 12067021U, // LDNPSi |
| 12067021U, // LDNPWi |
| 11018445U, // LDNPXi |
| 280901U, // LDNT1B_ZRI |
| 4357U, // LDNT1B_ZRR |
| 125253U, // LDNT1B_ZZR_D_REAL |
| 125253U, // LDNT1B_ZZR_S_REAL |
| 280901U, // LDNT1D_ZRI |
| 4421U, // LDNT1D_ZRR |
| 125253U, // LDNT1D_ZZR_D_REAL |
| 280901U, // LDNT1H_ZRI |
| 4485U, // LDNT1H_ZRR |
| 125253U, // LDNT1H_ZZR_D_REAL |
| 125253U, // LDNT1H_ZZR_S_REAL |
| 125253U, // LDNT1SB_ZZR_D_REAL |
| 125253U, // LDNT1SB_ZZR_S_REAL |
| 125253U, // LDNT1SH_ZZR_D_REAL |
| 125253U, // LDNT1SH_ZZR_S_REAL |
| 125253U, // LDNT1SW_ZZR_D_REAL |
| 280901U, // LDNT1W_ZRI |
| 4613U, // LDNT1W_ZRR |
| 125253U, // LDNT1W_ZZR_D_REAL |
| 125253U, // LDNT1W_ZZR_S_REAL |
| 11018445U, // LDPDi |
| 12872013U, // LDPDpost |
| 180365645U, // LDPDpre |
| 11542733U, // LDPQi |
| 13396301U, // LDPQpost |
| 180889933U, // LDPQpre |
| 12067021U, // LDPSWi |
| 13920589U, // LDPSWpost |
| 181414221U, // LDPSWpre |
| 12067021U, // LDPSi |
| 13920589U, // LDPSpost |
| 181414221U, // LDPSpre |
| 12067021U, // LDPWi |
| 13920589U, // LDPWpost |
| 181414221U, // LDPWpre |
| 11018445U, // LDPXi |
| 12872013U, // LDPXpost |
| 180365645U, // LDPXpre |
| 4741U, // LDRAAindexed |
| 298245U, // LDRAAwriteback |
| 4741U, // LDRABindexed |
| 298245U, // LDRABwriteback |
| 2397U, // LDRBBpost |
| 297285U, // LDRBBpre |
| 14164165U, // LDRBBroW |
| 14688453U, // LDRBBroX |
| 4805U, // LDRBBui |
| 2397U, // LDRBpost |
| 297285U, // LDRBpre |
| 14164165U, // LDRBroW |
| 14688453U, // LDRBroX |
| 4805U, // LDRBui |
| 0U, // LDRDl |
| 2397U, // LDRDpost |
| 297285U, // LDRDpre |
| 15212741U, // LDRDroW |
| 15737029U, // LDRDroX |
| 4869U, // LDRDui |
| 2397U, // LDRHHpost |
| 297285U, // LDRHHpre |
| 16261317U, // LDRHHroW |
| 16785605U, // LDRHHroX |
| 4933U, // LDRHHui |
| 2397U, // LDRHpost |
| 297285U, // LDRHpre |
| 16261317U, // LDRHroW |
| 16785605U, // LDRHroX |
| 4933U, // LDRHui |
| 0U, // LDRQl |
| 2397U, // LDRQpost |
| 297285U, // LDRQpre |
| 17309893U, // LDRQroW |
| 17834181U, // LDRQroX |
| 4997U, // LDRQui |
| 2397U, // LDRSBWpost |
| 297285U, // LDRSBWpre |
| 14164165U, // LDRSBWroW |
| 14688453U, // LDRSBWroX |
| 4805U, // LDRSBWui |
| 2397U, // LDRSBXpost |
| 297285U, // LDRSBXpre |
| 14164165U, // LDRSBXroW |
| 14688453U, // LDRSBXroX |
| 4805U, // LDRSBXui |
| 2397U, // LDRSHWpost |
| 297285U, // LDRSHWpre |
| 16261317U, // LDRSHWroW |
| 16785605U, // LDRSHWroX |
| 4933U, // LDRSHWui |
| 2397U, // LDRSHXpost |
| 297285U, // LDRSHXpre |
| 16261317U, // LDRSHXroW |
| 16785605U, // LDRSHXroX |
| 4933U, // LDRSHXui |
| 0U, // LDRSWl |
| 2397U, // LDRSWpost |
| 297285U, // LDRSWpre |
| 18358469U, // LDRSWroW |
| 18882757U, // LDRSWroX |
| 5061U, // LDRSWui |
| 0U, // LDRSl |
| 2397U, // LDRSpost |
| 297285U, // LDRSpre |
| 18358469U, // LDRSroW |
| 18882757U, // LDRSroX |
| 5061U, // LDRSui |
| 0U, // LDRWl |
| 2397U, // LDRWpost |
| 297285U, // LDRWpre |
| 18358469U, // LDRWroW |
| 18882757U, // LDRWroX |
| 5061U, // LDRWui |
| 0U, // LDRXl |
| 2397U, // LDRXpost |
| 297285U, // LDRXpre |
| 15212741U, // LDRXroW |
| 15737029U, // LDRXroX |
| 4869U, // LDRXui |
| 278725U, // LDR_PXI |
| 278725U, // LDR_ZXI |
| 0U, // LDSETAB |
| 0U, // LDSETAH |
| 0U, // LDSETALB |
| 0U, // LDSETALH |
| 0U, // LDSETALW |
| 0U, // LDSETALX |
| 0U, // LDSETAW |
| 0U, // LDSETAX |
| 0U, // LDSETB |
| 0U, // LDSETH |
| 0U, // LDSETLB |
| 0U, // LDSETLH |
| 0U, // LDSETLW |
| 0U, // LDSETLX |
| 0U, // LDSETW |
| 0U, // LDSETX |
| 0U, // LDSMAXAB |
| 0U, // LDSMAXAH |
| 0U, // LDSMAXALB |
| 0U, // LDSMAXALH |
| 0U, // LDSMAXALW |
| 0U, // LDSMAXALX |
| 0U, // LDSMAXAW |
| 0U, // LDSMAXAX |
| 0U, // LDSMAXB |
| 0U, // LDSMAXH |
| 0U, // LDSMAXLB |
| 0U, // LDSMAXLH |
| 0U, // LDSMAXLW |
| 0U, // LDSMAXLX |
| 0U, // LDSMAXW |
| 0U, // LDSMAXX |
| 0U, // LDSMINAB |
| 0U, // LDSMINAH |
| 0U, // LDSMINALB |
| 0U, // LDSMINALH |
| 0U, // LDSMINALW |
| 0U, // LDSMINALX |
| 0U, // LDSMINAW |
| 0U, // LDSMINAX |
| 0U, // LDSMINB |
| 0U, // LDSMINH |
| 0U, // LDSMINLB |
| 0U, // LDSMINLH |
| 0U, // LDSMINLW |
| 0U, // LDSMINLX |
| 0U, // LDSMINW |
| 0U, // LDSMINX |
| 123077U, // LDTRBi |
| 123077U, // LDTRHi |
| 123077U, // LDTRSBWi |
| 123077U, // LDTRSBXi |
| 123077U, // LDTRSHWi |
| 123077U, // LDTRSHXi |
| 123077U, // LDTRSWi |
| 123077U, // LDTRWi |
| 123077U, // LDTRXi |
| 0U, // LDUMAXAB |
| 0U, // LDUMAXAH |
| 0U, // LDUMAXALB |
| 0U, // LDUMAXALH |
| 0U, // LDUMAXALW |
| 0U, // LDUMAXALX |
| 0U, // LDUMAXAW |
| 0U, // LDUMAXAX |
| 0U, // LDUMAXB |
| 0U, // LDUMAXH |
| 0U, // LDUMAXLB |
| 0U, // LDUMAXLH |
| 0U, // LDUMAXLW |
| 0U, // LDUMAXLX |
| 0U, // LDUMAXW |
| 0U, // LDUMAXX |
| 0U, // LDUMINAB |
| 0U, // LDUMINAH |
| 0U, // LDUMINALB |
| 0U, // LDUMINALH |
| 0U, // LDUMINALW |
| 0U, // LDUMINALX |
| 0U, // LDUMINAW |
| 0U, // LDUMINAX |
| 0U, // LDUMINB |
| 0U, // LDUMINH |
| 0U, // LDUMINLB |
| 0U, // LDUMINLH |
| 0U, // LDUMINLW |
| 0U, // LDUMINLX |
| 0U, // LDUMINW |
| 0U, // LDUMINX |
| 123077U, // LDURBBi |
| 123077U, // LDURBi |
| 123077U, // LDURDi |
| 123077U, // LDURHHi |
| 123077U, // LDURHi |
| 123077U, // LDURQi |
| 123077U, // LDURSBWi |
| 123077U, // LDURSBXi |
| 123077U, // LDURSHWi |
| 123077U, // LDURSHXi |
| 123077U, // LDURSWi |
| 123077U, // LDURSi |
| 123077U, // LDURWi |
| 123077U, // LDURXi |
| 123085U, // LDXPW |
| 123085U, // LDXPX |
| 28U, // LDXRB |
| 28U, // LDXRH |
| 28U, // LDXRW |
| 28U, // LDXRX |
| 0U, // LOADgot |
| 533128U, // LSLR_ZPmZ_B |
| 1057160U, // LSLR_ZPmZ_D |
| 1614536U, // LSLR_ZPmZ_H |
| 2106120U, // LSLR_ZPmZ_S |
| 197U, // LSLVWr |
| 197U, // LSLVXr |
| 1057416U, // LSL_WIDE_ZPmZ_B |
| 99016U, // LSL_WIDE_ZPmZ_H |
| 1057544U, // LSL_WIDE_ZPmZ_S |
| 389U, // LSL_WIDE_ZZZ_B |
| 12U, // LSL_WIDE_ZZZ_H |
| 389U, // LSL_WIDE_ZZZ_S |
| 8840U, // LSL_ZPmI_B |
| 8584U, // LSL_ZPmI_D |
| 90824U, // LSL_ZPmI_H |
| 8968U, // LSL_ZPmI_S |
| 533128U, // LSL_ZPmZ_B |
| 1057160U, // LSL_ZPmZ_D |
| 1614536U, // LSL_ZPmZ_H |
| 2106120U, // LSL_ZPmZ_S |
| 197U, // LSL_ZZI_B |
| 197U, // LSL_ZZI_D |
| 12U, // LSL_ZZI_H |
| 197U, // LSL_ZZI_S |
| 533128U, // LSRR_ZPmZ_B |
| 1057160U, // LSRR_ZPmZ_D |
| 1614536U, // LSRR_ZPmZ_H |
| 2106120U, // LSRR_ZPmZ_S |
| 197U, // LSRVWr |
| 197U, // LSRVXr |
| 1057416U, // LSR_WIDE_ZPmZ_B |
| 99016U, // LSR_WIDE_ZPmZ_H |
| 1057544U, // LSR_WIDE_ZPmZ_S |
| 389U, // LSR_WIDE_ZZZ_B |
| 12U, // LSR_WIDE_ZZZ_H |
| 389U, // LSR_WIDE_ZZZ_S |
| 8840U, // LSR_ZPmI_B |
| 8584U, // LSR_ZPmI_D |
| 90824U, // LSR_ZPmI_H |
| 8968U, // LSR_ZPmI_S |
| 533128U, // LSR_ZPmZ_B |
| 1057160U, // LSR_ZPmZ_D |
| 1614536U, // LSR_ZPmZ_H |
| 2106120U, // LSR_ZPmZ_S |
| 197U, // LSR_ZZI_B |
| 197U, // LSR_ZZI_D |
| 12U, // LSR_ZZI_H |
| 197U, // LSR_ZZI_S |
| 8389U, // MADDWrrr |
| 8389U, // MADDXrrr |
| 5128U, // MAD_ZPmZZ_B |
| 7872584U, // MAD_ZPmZZ_D |
| 1794769U, // MAD_ZPmZZ_H |
| 8396936U, // MAD_ZPmZZ_S |
| 533131U, // MATCH_PPzZZ_B |
| 1614536U, // MATCH_PPzZZ_H |
| 5128U, // MLA_ZPmZZ_B |
| 7872584U, // MLA_ZPmZZ_D |
| 1794769U, // MLA_ZPmZZ_H |
| 8396936U, // MLA_ZPmZZ_S |
| 1704005U, // MLA_ZZZI_D |
| 2449U, // MLA_ZZZI_H |
| 1704069U, // MLA_ZZZI_S |
| 49737U, // MLAv16i8 |
| 57929U, // MLAv2i32 |
| 9151049U, // MLAv2i32_indexed |
| 66122U, // MLAv4i16 |
| 9142858U, // MLAv4i16_indexed |
| 25159U, // MLAv4i32 |
| 9151047U, // MLAv4i32_indexed |
| 33351U, // MLAv8i16 |
| 9142855U, // MLAv8i16_indexed |
| 74314U, // MLAv8i8 |
| 5128U, // MLS_ZPmZZ_B |
| 7872584U, // MLS_ZPmZZ_D |
| 1794769U, // MLS_ZPmZZ_H |
| 8396936U, // MLS_ZPmZZ_S |
| 1704005U, // MLS_ZZZI_D |
| 2449U, // MLS_ZZZI_H |
| 1704069U, // MLS_ZZZI_S |
| 49737U, // MLSv16i8 |
| 57929U, // MLSv2i32 |
| 9151049U, // MLSv2i32_indexed |
| 66122U, // MLSv4i16 |
| 9142858U, // MLSv4i16_indexed |
| 25159U, // MLSv4i32 |
| 9151047U, // MLSv4i32_indexed |
| 33351U, // MLSv8i16 |
| 9142855U, // MLSv8i16_indexed |
| 74314U, // MLSv8i8 |
| 0U, // MOVID |
| 2U, // MOVIv16b_ns |
| 0U, // MOVIv2d_ns |
| 29U, // MOVIv2i32 |
| 29U, // MOVIv2s_msl |
| 29U, // MOVIv4i16 |
| 29U, // MOVIv4i32 |
| 29U, // MOVIv4s_msl |
| 2U, // MOVIv8b_ns |
| 29U, // MOVIv8i16 |
| 0U, // MOVKWi |
| 0U, // MOVKXi |
| 0U, // MOVMCSym |
| 29U, // MOVNWi |
| 29U, // MOVNXi |
| 0U, // MOVPRFX_ZPmZ_B |
| 0U, // MOVPRFX_ZPmZ_D |
| 0U, // MOVPRFX_ZPmZ_H |
| 1U, // MOVPRFX_ZPmZ_S |
| 651U, // MOVPRFX_ZPzZ_B |
| 395U, // MOVPRFX_ZPzZ_D |
| 8U, // MOVPRFX_ZPzZ_H |
| 779U, // MOVPRFX_ZPzZ_S |
| 2U, // MOVPRFX_ZZ |
| 29U, // MOVZWi |
| 29U, // MOVZXi |
| 0U, // MOVaddr |
| 0U, // MOVaddrBA |
| 0U, // MOVaddrCP |
| 0U, // MOVaddrEXT |
| 0U, // MOVaddrJT |
| 0U, // MOVaddrTLS |
| 0U, // MOVbaseTLS |
| 0U, // MOVi32imm |
| 0U, // MOVi64imm |
| 0U, // MRS |
| 5128U, // MSB_ZPmZZ_B |
| 7872584U, // MSB_ZPmZZ_D |
| 1794769U, // MSB_ZPmZZ_H |
| 8396936U, // MSB_ZPmZZ_S |
| 0U, // MSR |
| 0U, // MSRpstateImm1 |
| 0U, // MSRpstateImm4 |
| 8389U, // MSUBWrrr |
| 8389U, // MSUBXrrr |
| 197U, // MUL_ZI_B |
| 197U, // MUL_ZI_D |
| 12U, // MUL_ZI_H |
| 197U, // MUL_ZI_S |
| 533128U, // MUL_ZPmZ_B |
| 1057160U, // MUL_ZPmZ_D |
| 1614536U, // MUL_ZPmZ_H |
| 2106120U, // MUL_ZPmZ_S |
| 270725U, // MUL_ZZZI_D |
| 2952U, // MUL_ZZZI_H |
| 271109U, // MUL_ZZZI_S |
| 645U, // MUL_ZZZ_B |
| 389U, // MUL_ZZZ_D |
| 8U, // MUL_ZZZ_H |
| 773U, // MUL_ZZZ_S |
| 49673U, // MULv16i8 |
| 57865U, // MULv2i32 |
| 10199561U, // MULv2i32_indexed |
| 66058U, // MULv4i16 |
| 10191370U, // MULv4i16_indexed |
| 25095U, // MULv4i32 |
| 10199559U, // MULv4i32_indexed |
| 33287U, // MULv8i16 |
| 10191367U, // MULv8i16_indexed |
| 74250U, // MULv8i8 |
| 29U, // MVNIv2i32 |
| 29U, // MVNIv2s_msl |
| 29U, // MVNIv4i16 |
| 29U, // MVNIv4i32 |
| 29U, // MVNIv4s_msl |
| 29U, // MVNIv8i16 |
| 533131U, // NANDS_PPzPP |
| 533131U, // NAND_PPzPP |
| 1057157U, // NBSL_ZZZZ_D |
| 0U, // NEG_ZPmZ_B |
| 0U, // NEG_ZPmZ_D |
| 0U, // NEG_ZPmZ_H |
| 1U, // NEG_ZPmZ_S |
| 1U, // NEGv16i8 |
| 2U, // NEGv1i64 |
| 2U, // NEGv2i32 |
| 3U, // NEGv2i64 |
| 3U, // NEGv4i16 |
| 4U, // NEGv4i32 |
| 4U, // NEGv8i16 |
| 5U, // NEGv8i8 |
| 533131U, // NMATCH_PPzZZ_B |
| 1614536U, // NMATCH_PPzZZ_H |
| 533131U, // NORS_PPzPP |
| 533131U, // NOR_PPzPP |
| 0U, // NOT_ZPmZ_B |
| 0U, // NOT_ZPmZ_D |
| 0U, // NOT_ZPmZ_H |
| 1U, // NOT_ZPmZ_S |
| 1U, // NOTv16i8 |
| 5U, // NOTv8i8 |
| 533131U, // ORNS_PPzPP |
| 0U, // ORNWrr |
| 901U, // ORNWrs |
| 0U, // ORNXrr |
| 901U, // ORNXrs |
| 533131U, // ORN_PPzPP |
| 49673U, // ORNv16i8 |
| 74250U, // ORNv8i8 |
| 533131U, // ORRS_PPzPP |
| 2245U, // ORRWri |
| 0U, // ORRWrr |
| 901U, // ORRWrs |
| 2309U, // ORRXri |
| 0U, // ORRXrr |
| 901U, // ORRXrs |
| 533131U, // ORR_PPzPP |
| 2309U, // ORR_ZI |
| 533128U, // ORR_ZPmZ_B |
| 1057160U, // ORR_ZPmZ_D |
| 1614536U, // ORR_ZPmZ_H |
| 2106120U, // ORR_ZPmZ_S |
| 389U, // ORR_ZZZ |
| 49673U, // ORRv16i8 |
| 0U, // ORRv2i32 |
| 0U, // ORRv4i16 |
| 0U, // ORRv4i32 |
| 0U, // ORRv8i16 |
| 74250U, // ORRv8i8 |
| 645U, // ORV_VPZ_B |
| 389U, // ORV_VPZ_D |
| 325U, // ORV_VPZ_H |
| 773U, // ORV_VPZ_S |
| 2U, // PACDA |
| 2U, // PACDB |
| 0U, // PACDZA |
| 0U, // PACDZB |
| 197U, // PACGA |
| 2U, // PACIA |
| 0U, // PACIA1716 |
| 0U, // PACIASP |
| 0U, // PACIAZ |
| 2U, // PACIB |
| 0U, // PACIB1716 |
| 0U, // PACIBSP |
| 0U, // PACIBZ |
| 0U, // PACIZA |
| 0U, // PACIZB |
| 0U, // PFALSE |
| 645U, // PFIRST_B |
| 773U, // PMULLB_ZZZ_D |
| 30U, // PMULLB_ZZZ_H |
| 0U, // PMULLB_ZZZ_Q |
| 773U, // PMULLT_ZZZ_D |
| 30U, // PMULLT_ZZZ_H |
| 0U, // PMULLT_ZZZ_Q |
| 49673U, // PMULLv16i8 |
| 0U, // PMULLv1i64 |
| 0U, // PMULLv2i64 |
| 74250U, // PMULLv8i8 |
| 645U, // PMUL_ZZZ_B |
| 49673U, // PMULv16i8 |
| 74250U, // PMULv8i8 |
| 645U, // PNEXT_B |
| 389U, // PNEXT_D |
| 8U, // PNEXT_H |
| 773U, // PNEXT_S |
| 28U, // PRFB_D_PZI |
| 30U, // PRFB_D_SCALED |
| 31U, // PRFB_D_SXTW_SCALED |
| 31U, // PRFB_D_UXTW_SCALED |
| 5204U, // PRFB_PRI |
| 32U, // PRFB_PRR |
| 5268U, // PRFB_S_PZI |
| 32U, // PRFB_S_SXTW_SCALED |
| 33U, // PRFB_S_UXTW_SCALED |
| 0U, // PRFD_D_PZI |
| 33U, // PRFD_D_SCALED |
| 34U, // PRFD_D_SXTW_SCALED |
| 34U, // PRFD_D_UXTW_SCALED |
| 5204U, // PRFD_PRI |
| 35U, // PRFD_PRR |
| 35U, // PRFD_S_PZI |
| 36U, // PRFD_S_SXTW_SCALED |
| 36U, // PRFD_S_UXTW_SCALED |
| 0U, // PRFH_D_PZI |
| 37U, // PRFH_D_SCALED |
| 37U, // PRFH_D_SXTW_SCALED |
| 38U, // PRFH_D_UXTW_SCALED |
| 5204U, // PRFH_PRI |
| 38U, // PRFH_PRR |
| 39U, // PRFH_S_PZI |
| 39U, // PRFH_S_SXTW_SCALED |
| 40U, // PRFH_S_UXTW_SCALED |
| 0U, // PRFMl |
| 15212741U, // PRFMroW |
| 15737029U, // PRFMroX |
| 4869U, // PRFMui |
| 40U, // PRFS_PRR |
| 123077U, // PRFUMi |
| 0U, // PRFW_D_PZI |
| 41U, // PRFW_D_SCALED |
| 41U, // PRFW_D_SXTW_SCALED |
| 42U, // PRFW_D_UXTW_SCALED |
| 5204U, // PRFW_PRI |
| 42U, // PRFW_S_PZI |
| 43U, // PRFW_S_SXTW_SCALED |
| 43U, // PRFW_S_UXTW_SCALED |
| 2U, // PTEST_PP |
| 2U, // PTRUES_B |
| 2U, // PTRUES_D |
| 0U, // PTRUES_H |
| 2U, // PTRUES_S |
| 2U, // PTRUE_B |
| 2U, // PTRUE_D |
| 0U, // PTRUE_H |
| 2U, // PTRUE_S |
| 0U, // PUNPKHI_PP |
| 0U, // PUNPKLO_PP |
| 325U, // RADDHNB_ZZZ_B |
| 6U, // RADDHNB_ZZZ_H |
| 389U, // RADDHNB_ZZZ_S |
| 453U, // RADDHNT_ZZZ_B |
| 1U, // RADDHNT_ZZZ_H |
| 69U, // RADDHNT_ZZZ_S |
| 16902U, // RADDHNv2i64_v2i32 |
| 16966U, // RADDHNv2i64_v4i32 |
| 25095U, // RADDHNv4i32_v4i16 |
| 25159U, // RADDHNv4i32_v8i16 |
| 33351U, // RADDHNv8i16_v16i8 |
| 33287U, // RADDHNv8i16_v8i8 |
| 16902U, // RAX1 |
| 389U, // RAX1_ZZZ_D |
| 2U, // RBITWr |
| 2U, // RBITXr |
| 0U, // RBIT_ZPmZ_B |
| 0U, // RBIT_ZPmZ_D |
| 0U, // RBIT_ZPmZ_H |
| 1U, // RBIT_ZPmZ_S |
| 1U, // RBITv16i8 |
| 5U, // RBITv8i8 |
| 44U, // RDFFRS_PPz |
| 0U, // RDFFR_P |
| 44U, // RDFFR_PPz |
| 2U, // RDVLI_XI |
| 0U, // RET |
| 0U, // RETAA |
| 0U, // RETAB |
| 0U, // RET_ReallyLR |
| 2U, // REV16Wr |
| 2U, // REV16Xr |
| 1U, // REV16v16i8 |
| 5U, // REV16v8i8 |
| 2U, // REV32Xr |
| 1U, // REV32v16i8 |
| 3U, // REV32v4i16 |
| 4U, // REV32v8i16 |
| 5U, // REV32v8i8 |
| 1U, // REV64v16i8 |
| 2U, // REV64v2i32 |
| 3U, // REV64v4i16 |
| 4U, // REV64v4i32 |
| 4U, // REV64v8i16 |
| 5U, // REV64v8i8 |
| 0U, // REVB_ZPmZ_D |
| 0U, // REVB_ZPmZ_H |
| 1U, // REVB_ZPmZ_S |
| 0U, // REVH_ZPmZ_D |
| 1U, // REVH_ZPmZ_S |
| 0U, // REVW_ZPmZ_D |
| 2U, // REVWr |
| 2U, // REVXr |
| 2U, // REV_PP_B |
| 2U, // REV_PP_D |
| 0U, // REV_PP_H |
| 2U, // REV_PP_S |
| 2U, // REV_ZZ_B |
| 2U, // REV_ZZ_D |
| 0U, // REV_ZZ_H |
| 2U, // REV_ZZ_S |
| 197U, // RMIF |
| 197U, // RORVWr |
| 197U, // RORVXr |
| 197U, // RSHRNB_ZZI_B |
| 12U, // RSHRNB_ZZI_H |
| 197U, // RSHRNB_ZZI_S |
| 2373U, // RSHRNT_ZZI_B |
| 20U, // RSHRNT_ZZI_H |
| 2373U, // RSHRNT_ZZI_S |
| 2375U, // RSHRNv16i8_shift |
| 198U, // RSHRNv2i32_shift |
| 199U, // RSHRNv4i16_shift |
| 2374U, // RSHRNv4i32_shift |
| 2375U, // RSHRNv8i16_shift |
| 199U, // RSHRNv8i8_shift |
| 325U, // RSUBHNB_ZZZ_B |
| 6U, // RSUBHNB_ZZZ_H |
| 389U, // RSUBHNB_ZZZ_S |
| 453U, // RSUBHNT_ZZZ_B |
| 1U, // RSUBHNT_ZZZ_H |
| 69U, // RSUBHNT_ZZZ_S |
| 16902U, // RSUBHNv2i64_v2i32 |
| 16966U, // RSUBHNv2i64_v4i32 |
| 25095U, // RSUBHNv4i32_v4i16 |
| 25159U, // RSUBHNv4i32_v8i16 |
| 33351U, // RSUBHNv8i16_v16i8 |
| 33287U, // RSUBHNv8i16_v8i8 |
| 133U, // SABALB_ZZZ_D |
| 0U, // SABALB_ZZZ_H |
| 453U, // SABALB_ZZZ_S |
| 133U, // SABALT_ZZZ_D |
| 0U, // SABALT_ZZZ_H |
| 453U, // SABALT_ZZZ_S |
| 49737U, // SABALv16i8_v8i16 |
| 57929U, // SABALv2i32_v2i64 |
| 66122U, // SABALv4i16_v4i32 |
| 25159U, // SABALv4i32_v2i64 |
| 33351U, // SABALv8i16_v4i32 |
| 74314U, // SABALv8i8_v8i16 |
| 0U, // SABA_ZZZ_B |
| 69U, // SABA_ZZZ_D |
| 17U, // SABA_ZZZ_H |
| 133U, // SABA_ZZZ_S |
| 49737U, // SABAv16i8 |
| 57929U, // SABAv2i32 |
| 66122U, // SABAv4i16 |
| 25159U, // SABAv4i32 |
| 33351U, // SABAv8i16 |
| 74314U, // SABAv8i8 |
| 773U, // SABDLB_ZZZ_D |
| 30U, // SABDLB_ZZZ_H |
| 325U, // SABDLB_ZZZ_S |
| 773U, // SABDLT_ZZZ_D |
| 30U, // SABDLT_ZZZ_H |
| 325U, // SABDLT_ZZZ_S |
| 49673U, // SABDLv16i8_v8i16 |
| 57865U, // SABDLv2i32_v2i64 |
| 66058U, // SABDLv4i16_v4i32 |
| 25095U, // SABDLv4i32_v2i64 |
| 33287U, // SABDLv8i16_v4i32 |
| 74250U, // SABDLv8i8_v8i16 |
| 533128U, // SABD_ZPmZ_B |
| 1057160U, // SABD_ZPmZ_D |
| 1614536U, // SABD_ZPmZ_H |
| 2106120U, // SABD_ZPmZ_S |
| 49673U, // SABDv16i8 |
| 57865U, // SABDv2i32 |
| 66058U, // SABDv4i16 |
| 25095U, // SABDv4i32 |
| 33287U, // SABDv8i16 |
| 74250U, // SABDv8i8 |
| 136U, // SADALP_ZPmZ_D |
| 0U, // SADALP_ZPmZ_H |
| 456U, // SADALP_ZPmZ_S |
| 1U, // SADALPv16i8_v8i16 |
| 2U, // SADALPv2i32_v1i64 |
| 3U, // SADALPv4i16_v2i32 |
| 4U, // SADALPv4i32_v2i64 |
| 4U, // SADALPv8i16_v4i32 |
| 5U, // SADALPv8i8_v4i16 |
| 773U, // SADDLBT_ZZZ_D |
| 30U, // SADDLBT_ZZZ_H |
| 325U, // SADDLBT_ZZZ_S |
| 773U, // SADDLB_ZZZ_D |
| 30U, // SADDLB_ZZZ_H |
| 325U, // SADDLB_ZZZ_S |
| 1U, // SADDLPv16i8_v8i16 |
| 2U, // SADDLPv2i32_v1i64 |
| 3U, // SADDLPv4i16_v2i32 |
| 4U, // SADDLPv4i32_v2i64 |
| 4U, // SADDLPv8i16_v4i32 |
| 5U, // SADDLPv8i8_v4i16 |
| 773U, // SADDLT_ZZZ_D |
| 30U, // SADDLT_ZZZ_H |
| 325U, // SADDLT_ZZZ_S |
| 1U, // SADDLVv16i8v |
| 3U, // SADDLVv4i16v |
| 4U, // SADDLVv4i32v |
| 4U, // SADDLVv8i16v |
| 5U, // SADDLVv8i8v |
| 49673U, // SADDLv16i8_v8i16 |
| 57865U, // SADDLv2i32_v2i64 |
| 66058U, // SADDLv4i16_v4i32 |
| 25095U, // SADDLv4i32_v2i64 |
| 33287U, // SADDLv8i16_v4i32 |
| 74250U, // SADDLv8i8_v8i16 |
| 645U, // SADDV_VPZ_B |
| 325U, // SADDV_VPZ_H |
| 773U, // SADDV_VPZ_S |
| 773U, // SADDWB_ZZZ_D |
| 30U, // SADDWB_ZZZ_H |
| 325U, // SADDWB_ZZZ_S |
| 773U, // SADDWT_ZZZ_D |
| 30U, // SADDWT_ZZZ_H |
| 325U, // SADDWT_ZZZ_S |
| 49671U, // SADDWv16i8_v8i16 |
| 57862U, // SADDWv2i32_v2i64 |
| 66055U, // SADDWv4i16_v4i32 |
| 25094U, // SADDWv4i32_v2i64 |
| 33287U, // SADDWv8i16_v4i32 |
| 74247U, // SADDWv8i8_v8i16 |
| 0U, // SB |
| 69U, // SBCLB_ZZZ_D |
| 133U, // SBCLB_ZZZ_S |
| 69U, // SBCLT_ZZZ_D |
| 133U, // SBCLT_ZZZ_S |
| 197U, // SBCSWr |
| 197U, // SBCSXr |
| 197U, // SBCWr |
| 197U, // SBCXr |
| 8389U, // SBFMWri |
| 8389U, // SBFMXri |
| 197U, // SCVTFSWDri |
| 197U, // SCVTFSWHri |
| 197U, // SCVTFSWSri |
| 197U, // SCVTFSXDri |
| 197U, // SCVTFSXHri |
| 197U, // SCVTFSXSri |
| 2U, // SCVTFUWDri |
| 2U, // SCVTFUWHri |
| 2U, // SCVTFUWSri |
| 2U, // SCVTFUXDri |
| 2U, // SCVTFUXHri |
| 2U, // SCVTFUXSri |
| 0U, // SCVTF_ZPmZ_DtoD |
| 0U, // SCVTF_ZPmZ_DtoH |
| 0U, // SCVTF_ZPmZ_DtoS |
| 0U, // SCVTF_ZPmZ_HtoH |
| 1U, // SCVTF_ZPmZ_StoD |
| 0U, // SCVTF_ZPmZ_StoH |
| 1U, // SCVTF_ZPmZ_StoS |
| 197U, // SCVTFd |
| 197U, // SCVTFh |
| 197U, // SCVTFs |
| 2U, // SCVTFv1i16 |
| 2U, // SCVTFv1i32 |
| 2U, // SCVTFv1i64 |
| 2U, // SCVTFv2f32 |
| 3U, // SCVTFv2f64 |
| 201U, // SCVTFv2i32_shift |
| 198U, // SCVTFv2i64_shift |
| 3U, // SCVTFv4f16 |
| 4U, // SCVTFv4f32 |
| 202U, // SCVTFv4i16_shift |
| 199U, // SCVTFv4i32_shift |
| 4U, // SCVTFv8f16 |
| 199U, // SCVTFv8i16_shift |
| 1057160U, // SDIVR_ZPmZ_D |
| 2106120U, // SDIVR_ZPmZ_S |
| 197U, // SDIVWr |
| 197U, // SDIVXr |
| 1057160U, // SDIV_ZPmZ_D |
| 2106120U, // SDIV_ZPmZ_S |
| 1704389U, // SDOT_ZZZI_D |
| 2432U, // SDOT_ZZZI_S |
| 453U, // SDOT_ZZZ_D |
| 0U, // SDOT_ZZZ_S |
| 303689U, // SDOTlanev16i8 |
| 303690U, // SDOTlanev8i8 |
| 49737U, // SDOTv16i8 |
| 74314U, // SDOTv8i8 |
| 533125U, // SEL_PPPP |
| 533125U, // SEL_ZPZZ_B |
| 1057157U, // SEL_ZPZZ_D |
| 1614536U, // SEL_ZPZZ_H |
| 2106117U, // SEL_ZPZZ_S |
| 0U, // SETF16 |
| 0U, // SETF8 |
| 0U, // SETFFR |
| 25157U, // SHA1Crrr |
| 2U, // SHA1Hrr |
| 25157U, // SHA1Mrrr |
| 25157U, // SHA1Prrr |
| 25159U, // SHA1SU0rrr |
| 4U, // SHA1SU1rr |
| 25157U, // SHA256H2rrr |
| 25157U, // SHA256Hrrr |
| 4U, // SHA256SU0rr |
| 25159U, // SHA256SU1rrr |
| 16965U, // SHA512H |
| 16965U, // SHA512H2 |
| 3U, // SHA512SU0 |
| 16966U, // SHA512SU1 |
| 533128U, // SHADD_ZPmZ_B |
| 1057160U, // SHADD_ZPmZ_D |
| 1614536U, // SHADD_ZPmZ_H |
| 2106120U, // SHADD_ZPmZ_S |
| 49673U, // SHADDv16i8 |
| 57865U, // SHADDv2i32 |
| 66058U, // SHADDv4i16 |
| 25095U, // SHADDv4i32 |
| 33287U, // SHADDv8i16 |
| 74250U, // SHADDv8i8 |
| 44U, // SHLLv16i8 |
| 45U, // SHLLv2i32 |
| 45U, // SHLLv4i16 |
| 46U, // SHLLv4i32 |
| 46U, // SHLLv8i16 |
| 47U, // SHLLv8i8 |
| 197U, // SHLd |
| 201U, // SHLv16i8_shift |
| 201U, // SHLv2i32_shift |
| 198U, // SHLv2i64_shift |
| 202U, // SHLv4i16_shift |
| 199U, // SHLv4i32_shift |
| 199U, // SHLv8i16_shift |
| 202U, // SHLv8i8_shift |
| 197U, // SHRNB_ZZI_B |
| 12U, // SHRNB_ZZI_H |
| 197U, // SHRNB_ZZI_S |
| 2373U, // SHRNT_ZZI_B |
| 20U, // SHRNT_ZZI_H |
| 2373U, // SHRNT_ZZI_S |
| 2375U, // SHRNv16i8_shift |
| 198U, // SHRNv2i32_shift |
| 199U, // SHRNv4i16_shift |
| 2374U, // SHRNv4i32_shift |
| 2375U, // SHRNv8i16_shift |
| 199U, // SHRNv8i8_shift |
| 533128U, // SHSUBR_ZPmZ_B |
| 1057160U, // SHSUBR_ZPmZ_D |
| 1614536U, // SHSUBR_ZPmZ_H |
| 2106120U, // SHSUBR_ZPmZ_S |
| 533128U, // SHSUB_ZPmZ_B |
| 1057160U, // SHSUB_ZPmZ_D |
| 1614536U, // SHSUB_ZPmZ_H |
| 2106120U, // SHSUB_ZPmZ_S |
| 49673U, // SHSUBv16i8 |
| 57865U, // SHSUBv2i32 |
| 66058U, // SHSUBv4i16 |
| 25095U, // SHSUBv4i32 |
| 33287U, // SHSUBv8i16 |
| 74250U, // SHSUBv8i8 |
| 20U, // SLI_ZZI_B |
| 2373U, // SLI_ZZI_D |
| 20U, // SLI_ZZI_H |
| 2373U, // SLI_ZZI_S |
| 2373U, // SLId |
| 2377U, // SLIv16i8_shift |
| 2377U, // SLIv2i32_shift |
| 2374U, // SLIv2i64_shift |
| 2378U, // SLIv4i16_shift |
| 2375U, // SLIv4i32_shift |
| 2375U, // SLIv8i16_shift |
| 2378U, // SLIv8i8_shift |
| 25159U, // SM3PARTW1 |
| 25159U, // SM3PARTW2 |
| 204145159U, // SM3SS1 |
| 9151047U, // SM3TT1A |
| 9151047U, // SM3TT1B |
| 9151047U, // SM3TT2A |
| 9151047U, // SM3TT2B |
| 4U, // SM4E |
| 773U, // SM4EKEY_ZZZ_S |
| 25095U, // SM4ENCKEY |
| 773U, // SM4E_ZZZ_S |
| 8389U, // SMADDLrrr |
| 533128U, // SMAXP_ZPmZ_B |
| 1057160U, // SMAXP_ZPmZ_D |
| 1614536U, // SMAXP_ZPmZ_H |
| 2106120U, // SMAXP_ZPmZ_S |
| 49673U, // SMAXPv16i8 |
| 57865U, // SMAXPv2i32 |
| 66058U, // SMAXPv4i16 |
| 25095U, // SMAXPv4i32 |
| 33287U, // SMAXPv8i16 |
| 74250U, // SMAXPv8i8 |
| 645U, // SMAXV_VPZ_B |
| 389U, // SMAXV_VPZ_D |
| 325U, // SMAXV_VPZ_H |
| 773U, // SMAXV_VPZ_S |
| 1U, // SMAXVv16i8v |
| 3U, // SMAXVv4i16v |
| 4U, // SMAXVv4i32v |
| 4U, // SMAXVv8i16v |
| 5U, // SMAXVv8i8v |
| 197U, // SMAX_ZI_B |
| 197U, // SMAX_ZI_D |
| 12U, // SMAX_ZI_H |
| 197U, // SMAX_ZI_S |
| 533128U, // SMAX_ZPmZ_B |
| 1057160U, // SMAX_ZPmZ_D |
| 1614536U, // SMAX_ZPmZ_H |
| 2106120U, // SMAX_ZPmZ_S |
| 49673U, // SMAXv16i8 |
| 57865U, // SMAXv2i32 |
| 66058U, // SMAXv4i16 |
| 25095U, // SMAXv4i32 |
| 33287U, // SMAXv8i16 |
| 74250U, // SMAXv8i8 |
| 0U, // SMC |
| 533128U, // SMINP_ZPmZ_B |
| 1057160U, // SMINP_ZPmZ_D |
| 1614536U, // SMINP_ZPmZ_H |
| 2106120U, // SMINP_ZPmZ_S |
| 49673U, // SMINPv16i8 |
| 57865U, // SMINPv2i32 |
| 66058U, // SMINPv4i16 |
| 25095U, // SMINPv4i32 |
| 33287U, // SMINPv8i16 |
| 74250U, // SMINPv8i8 |
| 645U, // SMINV_VPZ_B |
| 389U, // SMINV_VPZ_D |
| 325U, // SMINV_VPZ_H |
| 773U, // SMINV_VPZ_S |
| 1U, // SMINVv16i8v |
| 3U, // SMINVv4i16v |
| 4U, // SMINVv4i32v |
| 4U, // SMINVv8i16v |
| 5U, // SMINVv8i8v |
| 197U, // SMIN_ZI_B |
| 197U, // SMIN_ZI_D |
| 12U, // SMIN_ZI_H |
| 197U, // SMIN_ZI_S |
| 533128U, // SMIN_ZPmZ_B |
| 1057160U, // SMIN_ZPmZ_D |
| 1614536U, // SMIN_ZPmZ_H |
| 2106120U, // SMIN_ZPmZ_S |
| 49673U, // SMINv16i8 |
| 57865U, // SMINv2i32 |
| 66058U, // SMINv4i16 |
| 25095U, // SMINv4i32 |
| 33287U, // SMINv8i16 |
| 74250U, // SMINv8i8 |
| 1704069U, // SMLALB_ZZZI_D |
| 1704389U, // SMLALB_ZZZI_S |
| 133U, // SMLALB_ZZZ_D |
| 0U, // SMLALB_ZZZ_H |
| 453U, // SMLALB_ZZZ_S |
| 1704069U, // SMLALT_ZZZI_D |
| 1704389U, // SMLALT_ZZZI_S |
| 133U, // SMLALT_ZZZ_D |
| 0U, // SMLALT_ZZZ_H |
| 453U, // SMLALT_ZZZ_S |
| 49737U, // SMLALv16i8_v8i16 |
| 9151049U, // SMLALv2i32_indexed |
| 57929U, // SMLALv2i32_v2i64 |
| 9142858U, // SMLALv4i16_indexed |
| 66122U, // SMLALv4i16_v4i32 |
| 9151047U, // SMLALv4i32_indexed |
| 25159U, // SMLALv4i32_v2i64 |
| 9142855U, // SMLALv8i16_indexed |
| 33351U, // SMLALv8i16_v4i32 |
| 74314U, // SMLALv8i8_v8i16 |
| 1704069U, // SMLSLB_ZZZI_D |
| 1704389U, // SMLSLB_ZZZI_S |
| 133U, // SMLSLB_ZZZ_D |
| 0U, // SMLSLB_ZZZ_H |
| 453U, // SMLSLB_ZZZ_S |
| 1704069U, // SMLSLT_ZZZI_D |
| 1704389U, // SMLSLT_ZZZI_S |
| 133U, // SMLSLT_ZZZ_D |
| 0U, // SMLSLT_ZZZ_H |
| 453U, // SMLSLT_ZZZ_S |
| 49737U, // SMLSLv16i8_v8i16 |
| 9151049U, // SMLSLv2i32_indexed |
| 57929U, // SMLSLv2i32_v2i64 |
| 9142858U, // SMLSLv4i16_indexed |
| 66122U, // SMLSLv4i16_v4i32 |
| 9151047U, // SMLSLv4i32_indexed |
| 25159U, // SMLSLv4i32_v2i64 |
| 9142855U, // SMLSLv8i16_indexed |
| 33351U, // SMLSLv8i16_v4i32 |
| 74314U, // SMLSLv8i8_v8i16 |
| 2709U, // SMOVvi16to32 |
| 2709U, // SMOVvi16to64 |
| 2709U, // SMOVvi32to64 |
| 2710U, // SMOVvi8to32 |
| 2710U, // SMOVvi8to64 |
| 8389U, // SMSUBLrrr |
| 533128U, // SMULH_ZPmZ_B |
| 1057160U, // SMULH_ZPmZ_D |
| 1614536U, // SMULH_ZPmZ_H |
| 2106120U, // SMULH_ZPmZ_S |
| 645U, // SMULH_ZZZ_B |
| 389U, // SMULH_ZZZ_D |
| 8U, // SMULH_ZZZ_H |
| 773U, // SMULH_ZZZ_S |
| 197U, // SMULHrr |
| 271109U, // SMULLB_ZZZI_D |
| 270661U, // SMULLB_ZZZI_S |
| 773U, // SMULLB_ZZZ_D |
| 30U, // SMULLB_ZZZ_H |
| 325U, // SMULLB_ZZZ_S |
| 271109U, // SMULLT_ZZZI_D |
| 270661U, // SMULLT_ZZZI_S |
| 773U, // SMULLT_ZZZ_D |
| 30U, // SMULLT_ZZZ_H |
| 325U, // SMULLT_ZZZ_S |
| 49673U, // SMULLv16i8_v8i16 |
| 10199561U, // SMULLv2i32_indexed |
| 57865U, // SMULLv2i32_v2i64 |
| 10191370U, // SMULLv4i16_indexed |
| 66058U, // SMULLv4i16_v4i32 |
| 10199559U, // SMULLv4i32_indexed |
| 25095U, // SMULLv4i32_v2i64 |
| 10191367U, // SMULLv8i16_indexed |
| 33287U, // SMULLv8i16_v4i32 |
| 74250U, // SMULLv8i8_v8i16 |
| 0U, // SPACE |
| 5317U, // SPLICE_ZPZZ_B |
| 5381U, // SPLICE_ZPZZ_D |
| 47U, // SPLICE_ZPZZ_H |
| 5445U, // SPLICE_ZPZZ_S |
| 533125U, // SPLICE_ZPZ_B |
| 1057157U, // SPLICE_ZPZ_D |
| 1614536U, // SPLICE_ZPZ_H |
| 2106117U, // SPLICE_ZPZ_S |
| 0U, // SQABS_ZPmZ_B |
| 0U, // SQABS_ZPmZ_D |
| 0U, // SQABS_ZPmZ_H |
| 1U, // SQABS_ZPmZ_S |
| 1U, // SQABSv16i8 |
| 2U, // SQABSv1i16 |
| 2U, // SQABSv1i32 |
| 2U, // SQABSv1i64 |
| 2U, // SQABSv1i8 |
| 2U, // SQABSv2i32 |
| 3U, // SQABSv2i64 |
| 3U, // SQABSv4i16 |
| 4U, // SQABSv4i32 |
| 4U, // SQABSv8i16 |
| 5U, // SQABSv8i8 |
| 1029U, // SQADD_ZI_B |
| 1093U, // SQADD_ZI_D |
| 11U, // SQADD_ZI_H |
| 1157U, // SQADD_ZI_S |
| 533128U, // SQADD_ZPmZ_B |
| 1057160U, // SQADD_ZPmZ_D |
| 1614536U, // SQADD_ZPmZ_H |
| 2106120U, // SQADD_ZPmZ_S |
| 645U, // SQADD_ZZZ_B |
| 389U, // SQADD_ZZZ_D |
| 8U, // SQADD_ZZZ_H |
| 773U, // SQADD_ZZZ_S |
| 49673U, // SQADDv16i8 |
| 197U, // SQADDv1i16 |
| 197U, // SQADDv1i32 |
| 197U, // SQADDv1i64 |
| 197U, // SQADDv1i8 |
| 57865U, // SQADDv2i32 |
| 16902U, // SQADDv2i64 |
| 66058U, // SQADDv4i16 |
| 25095U, // SQADDv4i32 |
| 33287U, // SQADDv8i16 |
| 74250U, // SQADDv8i8 |
| 3678853U, // SQCADD_ZZI_B |
| 3678597U, // SQCADD_ZZI_D |
| 115400U, // SQCADD_ZZI_H |
| 3678981U, // SQCADD_ZZI_S |
| 0U, // SQDECB_XPiI |
| 0U, // SQDECB_XPiWdI |
| 0U, // SQDECD_XPiI |
| 0U, // SQDECD_XPiWdI |
| 0U, // SQDECD_ZPiI |
| 0U, // SQDECH_XPiI |
| 0U, // SQDECH_XPiWdI |
| 0U, // SQDECH_ZPiI |
| 5509U, // SQDECP_XPWd_B |
| 5509U, // SQDECP_XPWd_D |
| 5509U, // SQDECP_XPWd_H |
| 5509U, // SQDECP_XPWd_S |
| 2U, // SQDECP_XP_B |
| 2U, // SQDECP_XP_D |
| 2U, // SQDECP_XP_H |
| 2U, // SQDECP_XP_S |
| 2U, // SQDECP_ZP_D |
| 0U, // SQDECP_ZP_H |
| 2U, // SQDECP_ZP_S |
| 0U, // SQDECW_XPiI |
| 0U, // SQDECW_XPiWdI |
| 0U, // SQDECW_ZPiI |
| 133U, // SQDMLALBT_ZZZ_D |
| 0U, // SQDMLALBT_ZZZ_H |
| 453U, // SQDMLALBT_ZZZ_S |
| 1704069U, // SQDMLALB_ZZZI_D |
| 1704389U, // SQDMLALB_ZZZI_S |
| 133U, // SQDMLALB_ZZZ_D |
| 0U, // SQDMLALB_ZZZ_H |
| 453U, // SQDMLALB_ZZZ_S |
| 1704069U, // SQDMLALT_ZZZI_D |
| 1704389U, // SQDMLALT_ZZZI_S |
| 133U, // SQDMLALT_ZZZ_D |
| 0U, // SQDMLALT_ZZZ_H |
| 453U, // SQDMLALT_ZZZ_S |
| 2373U, // SQDMLALi16 |
| 2373U, // SQDMLALi32 |
| 9142853U, // SQDMLALv1i32_indexed |
| 9151045U, // SQDMLALv1i64_indexed |
| 9151049U, // SQDMLALv2i32_indexed |
| 57929U, // SQDMLALv2i32_v2i64 |
| 9142858U, // SQDMLALv4i16_indexed |
| 66122U, // SQDMLALv4i16_v4i32 |
| 9151047U, // SQDMLALv4i32_indexed |
| 25159U, // SQDMLALv4i32_v2i64 |
| 9142855U, // SQDMLALv8i16_indexed |
| 33351U, // SQDMLALv8i16_v4i32 |
| 133U, // SQDMLSLBT_ZZZ_D |
| 0U, // SQDMLSLBT_ZZZ_H |
| 453U, // SQDMLSLBT_ZZZ_S |
| 1704069U, // SQDMLSLB_ZZZI_D |
| 1704389U, // SQDMLSLB_ZZZI_S |
| 133U, // SQDMLSLB_ZZZ_D |
| 0U, // SQDMLSLB_ZZZ_H |
| 453U, // SQDMLSLB_ZZZ_S |
| 1704069U, // SQDMLSLT_ZZZI_D |
| 1704389U, // SQDMLSLT_ZZZI_S |
| 133U, // SQDMLSLT_ZZZ_D |
| 0U, // SQDMLSLT_ZZZ_H |
| 453U, // SQDMLSLT_ZZZ_S |
| 2373U, // SQDMLSLi16 |
| 2373U, // SQDMLSLi32 |
| 9142853U, // SQDMLSLv1i32_indexed |
| 9151045U, // SQDMLSLv1i64_indexed |
| 9151049U, // SQDMLSLv2i32_indexed |
| 57929U, // SQDMLSLv2i32_v2i64 |
| 9142858U, // SQDMLSLv4i16_indexed |
| 66122U, // SQDMLSLv4i16_v4i32 |
| 9151047U, // SQDMLSLv4i32_indexed |
| 25159U, // SQDMLSLv4i32_v2i64 |
| 9142855U, // SQDMLSLv8i16_indexed |
| 33351U, // SQDMLSLv8i16_v4i32 |
| 270725U, // SQDMULH_ZZZI_D |
| 2952U, // SQDMULH_ZZZI_H |
| 271109U, // SQDMULH_ZZZI_S |
| 645U, // SQDMULH_ZZZ_B |
| 389U, // SQDMULH_ZZZ_D |
| 8U, // SQDMULH_ZZZ_H |
| 773U, // SQDMULH_ZZZ_S |
| 197U, // SQDMULHv1i16 |
| 10191365U, // SQDMULHv1i16_indexed |
| 197U, // SQDMULHv1i32 |
| 10199557U, // SQDMULHv1i32_indexed |
| 57865U, // SQDMULHv2i32 |
| 10199561U, // SQDMULHv2i32_indexed |
| 66058U, // SQDMULHv4i16 |
| 10191370U, // SQDMULHv4i16_indexed |
| 25095U, // SQDMULHv4i32 |
| 10199559U, // SQDMULHv4i32_indexed |
| 33287U, // SQDMULHv8i16 |
| 10191367U, // SQDMULHv8i16_indexed |
| 271109U, // SQDMULLB_ZZZI_D |
| 270661U, // SQDMULLB_ZZZI_S |
| 773U, // SQDMULLB_ZZZ_D |
| 30U, // SQDMULLB_ZZZ_H |
| 325U, // SQDMULLB_ZZZ_S |
| 271109U, // SQDMULLT_ZZZI_D |
| 270661U, // SQDMULLT_ZZZI_S |
| 773U, // SQDMULLT_ZZZ_D |
| 30U, // SQDMULLT_ZZZ_H |
| 325U, // SQDMULLT_ZZZ_S |
| 197U, // SQDMULLi16 |
| 197U, // SQDMULLi32 |
| 10191365U, // SQDMULLv1i32_indexed |
| 10199557U, // SQDMULLv1i64_indexed |
| 10199561U, // SQDMULLv2i32_indexed |
| 57865U, // SQDMULLv2i32_v2i64 |
| 10191370U, // SQDMULLv4i16_indexed |
| 66058U, // SQDMULLv4i16_v4i32 |
| 10199559U, // SQDMULLv4i32_indexed |
| 25095U, // SQDMULLv4i32_v2i64 |
| 10191367U, // SQDMULLv8i16_indexed |
| 33287U, // SQDMULLv8i16_v4i32 |
| 0U, // SQINCB_XPiI |
| 0U, // SQINCB_XPiWdI |
| 0U, // SQINCD_XPiI |
| 0U, // SQINCD_XPiWdI |
| 0U, // SQINCD_ZPiI |
| 0U, // SQINCH_XPiI |
| 0U, // SQINCH_XPiWdI |
| 0U, // SQINCH_ZPiI |
| 5509U, // SQINCP_XPWd_B |
| 5509U, // SQINCP_XPWd_D |
| 5509U, // SQINCP_XPWd_H |
| 5509U, // SQINCP_XPWd_S |
| 2U, // SQINCP_XP_B |
| 2U, // SQINCP_XP_D |
| 2U, // SQINCP_XP_H |
| 2U, // SQINCP_XP_S |
| 2U, // SQINCP_ZP_D |
| 0U, // SQINCP_ZP_H |
| 2U, // SQINCP_ZP_S |
| 0U, // SQINCW_XPiI |
| 0U, // SQINCW_XPiWdI |
| 0U, // SQINCW_ZPiI |
| 0U, // SQNEG_ZPmZ_B |
| 0U, // SQNEG_ZPmZ_D |
| 0U, // SQNEG_ZPmZ_H |
| 1U, // SQNEG_ZPmZ_S |
| 1U, // SQNEGv16i8 |
| 2U, // SQNEGv1i16 |
| 2U, // SQNEGv1i32 |
| 2U, // SQNEGv1i64 |
| 2U, // SQNEGv1i8 |
| 2U, // SQNEGv2i32 |
| 3U, // SQNEGv2i64 |
| 3U, // SQNEGv4i16 |
| 4U, // SQNEGv4i32 |
| 4U, // SQNEGv8i16 |
| 5U, // SQNEGv8i8 |
| 5253521U, // SQRDCMLAH_ZZZI_H |
| 71958661U, // SQRDCMLAH_ZZZI_S |
| 139968U, // SQRDCMLAH_ZZZ_B |
| 5775429U, // SQRDCMLAH_ZZZ_D |
| 139985U, // SQRDCMLAH_ZZZ_H |
| 5775493U, // SQRDCMLAH_ZZZ_S |
| 1704005U, // SQRDMLAH_ZZZI_D |
| 2449U, // SQRDMLAH_ZZZI_H |
| 1704069U, // SQRDMLAH_ZZZI_S |
| 0U, // SQRDMLAH_ZZZ_B |
| 69U, // SQRDMLAH_ZZZ_D |
| 17U, // SQRDMLAH_ZZZ_H |
| 133U, // SQRDMLAH_ZZZ_S |
| 9142853U, // SQRDMLAHi16_indexed |
| 9151045U, // SQRDMLAHi32_indexed |
| 2373U, // SQRDMLAHv1i16 |
| 2373U, // SQRDMLAHv1i32 |
| 57929U, // SQRDMLAHv2i32 |
| 9151049U, // SQRDMLAHv2i32_indexed |
| 66122U, // SQRDMLAHv4i16 |
| 9142858U, // SQRDMLAHv4i16_indexed |
| 25159U, // SQRDMLAHv4i32 |
| 9151047U, // SQRDMLAHv4i32_indexed |
| 33351U, // SQRDMLAHv8i16 |
| 9142855U, // SQRDMLAHv8i16_indexed |
| 1704005U, // SQRDMLSH_ZZZI_D |
| 2449U, // SQRDMLSH_ZZZI_H |
| 1704069U, // SQRDMLSH_ZZZI_S |
| 0U, // SQRDMLSH_ZZZ_B |
| 69U, // SQRDMLSH_ZZZ_D |
| 17U, // SQRDMLSH_ZZZ_H |
| 133U, // SQRDMLSH_ZZZ_S |
| 9142853U, // SQRDMLSHi16_indexed |
| 9151045U, // SQRDMLSHi32_indexed |
| 2373U, // SQRDMLSHv1i16 |
| 2373U, // SQRDMLSHv1i32 |
| 57929U, // SQRDMLSHv2i32 |
| 9151049U, // SQRDMLSHv2i32_indexed |
| 66122U, // SQRDMLSHv4i16 |
| 9142858U, // SQRDMLSHv4i16_indexed |
| 25159U, // SQRDMLSHv4i32 |
| 9151047U, // SQRDMLSHv4i32_indexed |
| 33351U, // SQRDMLSHv8i16 |
| 9142855U, // SQRDMLSHv8i16_indexed |
| 270725U, // SQRDMULH_ZZZI_D |
| 2952U, // SQRDMULH_ZZZI_H |
| 271109U, // SQRDMULH_ZZZI_S |
| 645U, // SQRDMULH_ZZZ_B |
| 389U, // SQRDMULH_ZZZ_D |
| 8U, // SQRDMULH_ZZZ_H |
| 773U, // SQRDMULH_ZZZ_S |
| 197U, // SQRDMULHv1i16 |
| 10191365U, // SQRDMULHv1i16_indexed |
| 197U, // SQRDMULHv1i32 |
| 10199557U, // SQRDMULHv1i32_indexed |
| 57865U, // SQRDMULHv2i32 |
| 10199561U, // SQRDMULHv2i32_indexed |
| 66058U, // SQRDMULHv4i16 |
| 10191370U, // SQRDMULHv4i16_indexed |
| 25095U, // SQRDMULHv4i32 |
| 10199559U, // SQRDMULHv4i32_indexed |
| 33287U, // SQRDMULHv8i16 |
| 10191367U, // SQRDMULHv8i16_indexed |
| 533128U, // SQRSHLR_ZPmZ_B |
| 1057160U, // SQRSHLR_ZPmZ_D |
| 1614536U, // SQRSHLR_ZPmZ_H |
| 2106120U, // SQRSHLR_ZPmZ_S |
| 533128U, // SQRSHL_ZPmZ_B |
| 1057160U, // SQRSHL_ZPmZ_D |
| 1614536U, // SQRSHL_ZPmZ_H |
| 2106120U, // SQRSHL_ZPmZ_S |
| 49673U, // SQRSHLv16i8 |
| 197U, // SQRSHLv1i16 |
| 197U, // SQRSHLv1i32 |
| 197U, // SQRSHLv1i64 |
| 197U, // SQRSHLv1i8 |
| 57865U, // SQRSHLv2i32 |
| 16902U, // SQRSHLv2i64 |
| 66058U, // SQRSHLv4i16 |
| 25095U, // SQRSHLv4i32 |
| 33287U, // SQRSHLv8i16 |
| 74250U, // SQRSHLv8i8 |
| 197U, // SQRSHRNB_ZZI_B |
| 12U, // SQRSHRNB_ZZI_H |
| 197U, // SQRSHRNB_ZZI_S |
| 2373U, // SQRSHRNT_ZZI_B |
| 20U, // SQRSHRNT_ZZI_H |
| 2373U, // SQRSHRNT_ZZI_S |
| 197U, // SQRSHRNb |
| 197U, // SQRSHRNh |
| 197U, // SQRSHRNs |
| 2375U, // SQRSHRNv16i8_shift |
| 198U, // SQRSHRNv2i32_shift |
| 199U, // SQRSHRNv4i16_shift |
| 2374U, // SQRSHRNv4i32_shift |
| 2375U, // SQRSHRNv8i16_shift |
| 199U, // SQRSHRNv8i8_shift |
| 197U, // SQRSHRUNB_ZZI_B |
| 12U, // SQRSHRUNB_ZZI_H |
| 197U, // SQRSHRUNB_ZZI_S |
| 2373U, // SQRSHRUNT_ZZI_B |
| 20U, // SQRSHRUNT_ZZI_H |
| 2373U, // SQRSHRUNT_ZZI_S |
| 197U, // SQRSHRUNb |
| 197U, // SQRSHRUNh |
| 197U, // SQRSHRUNs |
| 2375U, // SQRSHRUNv16i8_shift |
| 198U, // SQRSHRUNv2i32_shift |
| 199U, // SQRSHRUNv4i16_shift |
| 2374U, // SQRSHRUNv4i32_shift |
| 2375U, // SQRSHRUNv8i16_shift |
| 199U, // SQRSHRUNv8i8_shift |
| 533128U, // SQSHLR_ZPmZ_B |
| 1057160U, // SQSHLR_ZPmZ_D |
| 1614536U, // SQSHLR_ZPmZ_H |
| 2106120U, // SQSHLR_ZPmZ_S |
| 8840U, // SQSHLU_ZPmI_B |
| 8584U, // SQSHLU_ZPmI_D |
| 90824U, // SQSHLU_ZPmI_H |
| 8968U, // SQSHLU_ZPmI_S |
| 197U, // SQSHLUb |
| 197U, // SQSHLUd |
| 197U, // SQSHLUh |
| 197U, // SQSHLUs |
| 201U, // SQSHLUv16i8_shift |
| 201U, // SQSHLUv2i32_shift |
| 198U, // SQSHLUv2i64_shift |
| 202U, // SQSHLUv4i16_shift |
| 199U, // SQSHLUv4i32_shift |
| 199U, // SQSHLUv8i16_shift |
| 202U, // SQSHLUv8i8_shift |
| 8840U, // SQSHL_ZPmI_B |
| 8584U, // SQSHL_ZPmI_D |
| 90824U, // SQSHL_ZPmI_H |
| 8968U, // SQSHL_ZPmI_S |
| 533128U, // SQSHL_ZPmZ_B |
| 1057160U, // SQSHL_ZPmZ_D |
| 1614536U, // SQSHL_ZPmZ_H |
| 2106120U, // SQSHL_ZPmZ_S |
| 197U, // SQSHLb |
| 197U, // SQSHLd |
| 197U, // SQSHLh |
| 197U, // SQSHLs |
| 49673U, // SQSHLv16i8 |
| 201U, // SQSHLv16i8_shift |
| 197U, // SQSHLv1i16 |
| 197U, // SQSHLv1i32 |
| 197U, // SQSHLv1i64 |
| 197U, // SQSHLv1i8 |
| 57865U, // SQSHLv2i32 |
| 201U, // SQSHLv2i32_shift |
| 16902U, // SQSHLv2i64 |
| 198U, // SQSHLv2i64_shift |
| 66058U, // SQSHLv4i16 |
| 202U, // SQSHLv4i16_shift |
| 25095U, // SQSHLv4i32 |
| 199U, // SQSHLv4i32_shift |
| 33287U, // SQSHLv8i16 |
| 199U, // SQSHLv8i16_shift |
| 74250U, // SQSHLv8i8 |
| 202U, // SQSHLv8i8_shift |
| 197U, // SQSHRNB_ZZI_B |
| 12U, // SQSHRNB_ZZI_H |
| 197U, // SQSHRNB_ZZI_S |
| 2373U, // SQSHRNT_ZZI_B |
| 20U, // SQSHRNT_ZZI_H |
| 2373U, // SQSHRNT_ZZI_S |
| 197U, // SQSHRNb |
| 197U, // SQSHRNh |
| 197U, // SQSHRNs |
| 2375U, // SQSHRNv16i8_shift |
| 198U, // SQSHRNv2i32_shift |
| 199U, // SQSHRNv4i16_shift |
| 2374U, // SQSHRNv4i32_shift |
| 2375U, // SQSHRNv8i16_shift |
| 199U, // SQSHRNv8i8_shift |
| 197U, // SQSHRUNB_ZZI_B |
| 12U, // SQSHRUNB_ZZI_H |
| 197U, // SQSHRUNB_ZZI_S |
| 2373U, // SQSHRUNT_ZZI_B |
| 20U, // SQSHRUNT_ZZI_H |
| 2373U, // SQSHRUNT_ZZI_S |
| 197U, // SQSHRUNb |
| 197U, // SQSHRUNh |
| 197U, // SQSHRUNs |
| 2375U, // SQSHRUNv16i8_shift |
| 198U, // SQSHRUNv2i32_shift |
| 199U, // SQSHRUNv4i16_shift |
| 2374U, // SQSHRUNv4i32_shift |
| 2375U, // SQSHRUNv8i16_shift |
| 199U, // SQSHRUNv8i8_shift |
| 533128U, // SQSUBR_ZPmZ_B |
| 1057160U, // SQSUBR_ZPmZ_D |
| 1614536U, // SQSUBR_ZPmZ_H |
| 2106120U, // SQSUBR_ZPmZ_S |
| 1029U, // SQSUB_ZI_B |
| 1093U, // SQSUB_ZI_D |
| 11U, // SQSUB_ZI_H |
| 1157U, // SQSUB_ZI_S |
| 533128U, // SQSUB_ZPmZ_B |
| 1057160U, // SQSUB_ZPmZ_D |
| 1614536U, // SQSUB_ZPmZ_H |
| 2106120U, // SQSUB_ZPmZ_S |
| 645U, // SQSUB_ZZZ_B |
| 389U, // SQSUB_ZZZ_D |
| 8U, // SQSUB_ZZZ_H |
| 773U, // SQSUB_ZZZ_S |
| 49673U, // SQSUBv16i8 |
| 197U, // SQSUBv1i16 |
| 197U, // SQSUBv1i32 |
| 197U, // SQSUBv1i64 |
| 197U, // SQSUBv1i8 |
| 57865U, // SQSUBv2i32 |
| 16902U, // SQSUBv2i64 |
| 66058U, // SQSUBv4i16 |
| 25095U, // SQSUBv4i32 |
| 33287U, // SQSUBv8i16 |
| 74250U, // SQSUBv8i8 |
| 2U, // SQXTNB_ZZ_B |
| 0U, // SQXTNB_ZZ_H |
| 2U, // SQXTNB_ZZ_S |
| 2U, // SQXTNT_ZZ_B |
| 0U, // SQXTNT_ZZ_H |
| 2U, // SQXTNT_ZZ_S |
| 4U, // SQXTNv16i8 |
| 2U, // SQXTNv1i16 |
| 2U, // SQXTNv1i32 |
| 2U, // SQXTNv1i8 |
| 3U, // SQXTNv2i32 |
| 4U, // SQXTNv4i16 |
| 3U, // SQXTNv4i32 |
| 4U, // SQXTNv8i16 |
| 4U, // SQXTNv8i8 |
| 2U, // SQXTUNB_ZZ_B |
| 0U, // SQXTUNB_ZZ_H |
| 2U, // SQXTUNB_ZZ_S |
| 2U, // SQXTUNT_ZZ_B |
| 0U, // SQXTUNT_ZZ_H |
| 2U, // SQXTUNT_ZZ_S |
| 4U, // SQXTUNv16i8 |
| 2U, // SQXTUNv1i16 |
| 2U, // SQXTUNv1i32 |
| 2U, // SQXTUNv1i8 |
| 3U, // SQXTUNv2i32 |
| 4U, // SQXTUNv4i16 |
| 3U, // SQXTUNv4i32 |
| 4U, // SQXTUNv8i16 |
| 4U, // SQXTUNv8i8 |
| 533128U, // SRHADD_ZPmZ_B |
| 1057160U, // SRHADD_ZPmZ_D |
| 1614536U, // SRHADD_ZPmZ_H |
| 2106120U, // SRHADD_ZPmZ_S |
| 49673U, // SRHADDv16i8 |
| 57865U, // SRHADDv2i32 |
| 66058U, // SRHADDv4i16 |
| 25095U, // SRHADDv4i32 |
| 33287U, // SRHADDv8i16 |
| 74250U, // SRHADDv8i8 |
| 20U, // SRI_ZZI_B |
| 2373U, // SRI_ZZI_D |
| 20U, // SRI_ZZI_H |
| 2373U, // SRI_ZZI_S |
| 2373U, // SRId |
| 2377U, // SRIv16i8_shift |
| 2377U, // SRIv2i32_shift |
| 2374U, // SRIv2i64_shift |
| 2378U, // SRIv4i16_shift |
| 2375U, // SRIv4i32_shift |
| 2375U, // SRIv8i16_shift |
| 2378U, // SRIv8i8_shift |
| 533128U, // SRSHLR_ZPmZ_B |
| 1057160U, // SRSHLR_ZPmZ_D |
| 1614536U, // SRSHLR_ZPmZ_H |
| 2106120U, // SRSHLR_ZPmZ_S |
| 533128U, // SRSHL_ZPmZ_B |
| 1057160U, // SRSHL_ZPmZ_D |
| 1614536U, // SRSHL_ZPmZ_H |
| 2106120U, // SRSHL_ZPmZ_S |
| 49673U, // SRSHLv16i8 |
| 197U, // SRSHLv1i64 |
| 57865U, // SRSHLv2i32 |
| 16902U, // SRSHLv2i64 |
| 66058U, // SRSHLv4i16 |
| 25095U, // SRSHLv4i32 |
| 33287U, // SRSHLv8i16 |
| 74250U, // SRSHLv8i8 |
| 8840U, // SRSHR_ZPmI_B |
| 8584U, // SRSHR_ZPmI_D |
| 90824U, // SRSHR_ZPmI_H |
| 8968U, // SRSHR_ZPmI_S |
| 197U, // SRSHRd |
| 201U, // SRSHRv16i8_shift |
| 201U, // SRSHRv2i32_shift |
| 198U, // SRSHRv2i64_shift |
| 202U, // SRSHRv4i16_shift |
| 199U, // SRSHRv4i32_shift |
| 199U, // SRSHRv8i16_shift |
| 202U, // SRSHRv8i8_shift |
| 20U, // SRSRA_ZZI_B |
| 2373U, // SRSRA_ZZI_D |
| 20U, // SRSRA_ZZI_H |
| 2373U, // SRSRA_ZZI_S |
| 2373U, // SRSRAd |
| 2377U, // SRSRAv16i8_shift |
| 2377U, // SRSRAv2i32_shift |
| 2374U, // SRSRAv2i64_shift |
| 2378U, // SRSRAv4i16_shift |
| 2375U, // SRSRAv4i32_shift |
| 2375U, // SRSRAv8i16_shift |
| 2378U, // SRSRAv8i8_shift |
| 197U, // SSHLLB_ZZI_D |
| 12U, // SSHLLB_ZZI_H |
| 197U, // SSHLLB_ZZI_S |
| 197U, // SSHLLT_ZZI_D |
| 12U, // SSHLLT_ZZI_H |
| 197U, // SSHLLT_ZZI_S |
| 201U, // SSHLLv16i8_shift |
| 201U, // SSHLLv2i32_shift |
| 202U, // SSHLLv4i16_shift |
| 199U, // SSHLLv4i32_shift |
| 199U, // SSHLLv8i16_shift |
| 202U, // SSHLLv8i8_shift |
| 49673U, // SSHLv16i8 |
| 197U, // SSHLv1i64 |
| 57865U, // SSHLv2i32 |
| 16902U, // SSHLv2i64 |
| 66058U, // SSHLv4i16 |
| 25095U, // SSHLv4i32 |
| 33287U, // SSHLv8i16 |
| 74250U, // SSHLv8i8 |
| 197U, // SSHRd |
| 201U, // SSHRv16i8_shift |
| 201U, // SSHRv2i32_shift |
| 198U, // SSHRv2i64_shift |
| 202U, // SSHRv4i16_shift |
| 199U, // SSHRv4i32_shift |
| 199U, // SSHRv8i16_shift |
| 202U, // SSHRv8i8_shift |
| 20U, // SSRA_ZZI_B |
| 2373U, // SSRA_ZZI_D |
| 20U, // SSRA_ZZI_H |
| 2373U, // SSRA_ZZI_S |
| 2373U, // SSRAd |
| 2377U, // SSRAv16i8_shift |
| 2377U, // SSRAv2i32_shift |
| 2374U, // SSRAv2i64_shift |
| 2378U, // SSRAv4i16_shift |
| 2375U, // SSRAv4i32_shift |
| 2375U, // SSRAv8i16_shift |
| 2378U, // SSRAv8i8_shift |
| 125253U, // SST1B_D_IMM |
| 3013U, // SST1B_D_REAL |
| 3077U, // SST1B_D_SXTW |
| 3141U, // SST1B_D_UXTW |
| 125253U, // SST1B_S_IMM |
| 3205U, // SST1B_S_SXTW |
| 3269U, // SST1B_S_UXTW |
| 126213U, // SST1D_IMM |
| 3013U, // SST1D_REAL |
| 3397U, // SST1D_SCALED_SCALED_REAL |
| 3077U, // SST1D_SXTW |
| 3461U, // SST1D_SXTW_SCALED |
| 3141U, // SST1D_UXTW |
| 3525U, // SST1D_UXTW_SCALED |
| 126469U, // SST1H_D_IMM |
| 3013U, // SST1H_D_REAL |
| 3653U, // SST1H_D_SCALED_SCALED_REAL |
| 3077U, // SST1H_D_SXTW |
| 3717U, // SST1H_D_SXTW_SCALED |
| 3141U, // SST1H_D_UXTW |
| 3781U, // SST1H_D_UXTW_SCALED |
| 126469U, // SST1H_S_IMM |
| 3205U, // SST1H_S_SXTW |
| 3845U, // SST1H_S_SXTW_SCALED |
| 3269U, // SST1H_S_UXTW |
| 3909U, // SST1H_S_UXTW_SCALED |
| 126853U, // SST1W_D_IMM |
| 3013U, // SST1W_D_REAL |
| 4037U, // SST1W_D_SCALED_SCALED_REAL |
| 3077U, // SST1W_D_SXTW |
| 4101U, // SST1W_D_SXTW_SCALED |
| 3141U, // SST1W_D_UXTW |
| 4165U, // SST1W_D_UXTW_SCALED |
| 126853U, // SST1W_IMM |
| 3205U, // SST1W_SXTW |
| 4229U, // SST1W_SXTW_SCALED |
| 3269U, // SST1W_UXTW |
| 4293U, // SST1W_UXTW_SCALED |
| 773U, // SSUBLBT_ZZZ_D |
| 30U, // SSUBLBT_ZZZ_H |
| 325U, // SSUBLBT_ZZZ_S |
| 773U, // SSUBLB_ZZZ_D |
| 30U, // SSUBLB_ZZZ_H |
| 325U, // SSUBLB_ZZZ_S |
| 773U, // SSUBLTB_ZZZ_D |
| 30U, // SSUBLTB_ZZZ_H |
| 325U, // SSUBLTB_ZZZ_S |
| 773U, // SSUBLT_ZZZ_D |
| 30U, // SSUBLT_ZZZ_H |
| 325U, // SSUBLT_ZZZ_S |
| 49673U, // SSUBLv16i8_v8i16 |
| 57865U, // SSUBLv2i32_v2i64 |
| 66058U, // SSUBLv4i16_v4i32 |
| 25095U, // SSUBLv4i32_v2i64 |
| 33287U, // SSUBLv8i16_v4i32 |
| 74250U, // SSUBLv8i8_v8i16 |
| 773U, // SSUBWB_ZZZ_D |
| 30U, // SSUBWB_ZZZ_H |
| 325U, // SSUBWB_ZZZ_S |
| 773U, // SSUBWT_ZZZ_D |
| 30U, // SSUBWT_ZZZ_H |
| 325U, // SSUBWT_ZZZ_S |
| 49671U, // SSUBWv16i8_v8i16 |
| 57862U, // SSUBWv2i32_v2i64 |
| 66055U, // SSUBWv4i16_v4i32 |
| 25094U, // SSUBWv4i32_v2i64 |
| 33287U, // SSUBWv8i16_v4i32 |
| 74247U, // SSUBWv8i8_v8i16 |
| 4357U, // ST1B |
| 4357U, // ST1B_D |
| 280901U, // ST1B_D_IMM |
| 4357U, // ST1B_H |
| 280901U, // ST1B_H_IMM |
| 280901U, // ST1B_IMM |
| 4357U, // ST1B_S |
| 280901U, // ST1B_S_IMM |
| 4421U, // ST1D |
| 280901U, // ST1D_IMM |
| 0U, // ST1Fourv16b |
| 0U, // ST1Fourv16b_POST |
| 0U, // ST1Fourv1d |
| 0U, // ST1Fourv1d_POST |
| 0U, // ST1Fourv2d |
| 0U, // ST1Fourv2d_POST |
| 0U, // ST1Fourv2s |
| 0U, // ST1Fourv2s_POST |
| 0U, // ST1Fourv4h |
| 0U, // ST1Fourv4h_POST |
| 0U, // ST1Fourv4s |
| 0U, // ST1Fourv4s_POST |
| 0U, // ST1Fourv8b |
| 0U, // ST1Fourv8b_POST |
| 0U, // ST1Fourv8h |
| 0U, // ST1Fourv8h_POST |
| 4485U, // ST1H |
| 4485U, // ST1H_D |
| 280901U, // ST1H_D_IMM |
| 280901U, // ST1H_IMM |
| 4485U, // ST1H_S |
| 280901U, // ST1H_S_IMM |
| 0U, // ST1Onev16b |
| 0U, // ST1Onev16b_POST |
| 0U, // ST1Onev1d |
| 0U, // ST1Onev1d_POST |
| 0U, // ST1Onev2d |
| 0U, // ST1Onev2d_POST |
| 0U, // ST1Onev2s |
| 0U, // ST1Onev2s_POST |
| 0U, // ST1Onev4h |
| 0U, // ST1Onev4h_POST |
| 0U, // ST1Onev4s |
| 0U, // ST1Onev4s_POST |
| 0U, // ST1Onev8b |
| 0U, // ST1Onev8b_POST |
| 0U, // ST1Onev8h |
| 0U, // ST1Onev8h_POST |
| 0U, // ST1Threev16b |
| 0U, // ST1Threev16b_POST |
| 0U, // ST1Threev1d |
| 0U, // ST1Threev1d_POST |
| 0U, // ST1Threev2d |
| 0U, // ST1Threev2d_POST |
| 0U, // ST1Threev2s |
| 0U, // ST1Threev2s_POST |
| 0U, // ST1Threev4h |
| 0U, // ST1Threev4h_POST |
| 0U, // ST1Threev4s |
| 0U, // ST1Threev4s_POST |
| 0U, // ST1Threev8b |
| 0U, // ST1Threev8b_POST |
| 0U, // ST1Threev8h |
| 0U, // ST1Threev8h_POST |
| 0U, // ST1Twov16b |
| 0U, // ST1Twov16b_POST |
| 0U, // ST1Twov1d |
| 0U, // ST1Twov1d_POST |
| 0U, // ST1Twov2d |
| 0U, // ST1Twov2d_POST |
| 0U, // ST1Twov2s |
| 0U, // ST1Twov2s_POST |
| 0U, // ST1Twov4h |
| 0U, // ST1Twov4h_POST |
| 0U, // ST1Twov4s |
| 0U, // ST1Twov4s_POST |
| 0U, // ST1Twov8b |
| 0U, // ST1Twov8b_POST |
| 0U, // ST1Twov8h |
| 0U, // ST1Twov8h_POST |
| 4613U, // ST1W |
| 4613U, // ST1W_D |
| 280901U, // ST1W_D_IMM |
| 280901U, // ST1W_IMM |
| 0U, // ST1i16 |
| 0U, // ST1i16_POST |
| 0U, // ST1i32 |
| 0U, // ST1i32_POST |
| 0U, // ST1i64 |
| 0U, // ST1i64_POST |
| 0U, // ST1i8 |
| 0U, // ST1i8_POST |
| 4357U, // ST2B |
| 282117U, // ST2B_IMM |
| 4421U, // ST2D |
| 282117U, // ST2D_IMM |
| 123141U, // ST2GOffset |
| 4573U, // ST2GPostIndex |
| 299461U, // ST2GPreIndex |
| 4485U, // ST2H |
| 282117U, // ST2H_IMM |
| 0U, // ST2Twov16b |
| 0U, // ST2Twov16b_POST |
| 0U, // ST2Twov2d |
| 0U, // ST2Twov2d_POST |
| 0U, // ST2Twov2s |
| 0U, // ST2Twov2s_POST |
| 0U, // ST2Twov4h |
| 0U, // ST2Twov4h_POST |
| 0U, // ST2Twov4s |
| 0U, // ST2Twov4s_POST |
| 0U, // ST2Twov8b |
| 0U, // ST2Twov8b_POST |
| 0U, // ST2Twov8h |
| 0U, // ST2Twov8h_POST |
| 4613U, // ST2W |
| 282117U, // ST2W_IMM |
| 0U, // ST2i16 |
| 0U, // ST2i16_POST |
| 0U, // ST2i32 |
| 0U, // ST2i32_POST |
| 0U, // ST2i64 |
| 0U, // ST2i64_POST |
| 0U, // ST2i8 |
| 0U, // ST2i8_POST |
| 4357U, // ST3B |
| 4677U, // ST3B_IMM |
| 4421U, // ST3D |
| 4677U, // ST3D_IMM |
| 4485U, // ST3H |
| 4677U, // ST3H_IMM |
| 0U, // ST3Threev16b |
| 0U, // ST3Threev16b_POST |
| 0U, // ST3Threev2d |
| 0U, // ST3Threev2d_POST |
| 0U, // ST3Threev2s |
| 0U, // ST3Threev2s_POST |
| 0U, // ST3Threev4h |
| 0U, // ST3Threev4h_POST |
| 0U, // ST3Threev4s |
| 0U, // ST3Threev4s_POST |
| 0U, // ST3Threev8b |
| 0U, // ST3Threev8b_POST |
| 0U, // ST3Threev8h |
| 0U, // ST3Threev8h_POST |
| 4613U, // ST3W |
| 4677U, // ST3W_IMM |
| 0U, // ST3i16 |
| 0U, // ST3i16_POST |
| 0U, // ST3i32 |
| 0U, // ST3i32_POST |
| 0U, // ST3i64 |
| 0U, // ST3i64_POST |
| 0U, // ST3i8 |
| 0U, // ST3i8_POST |
| 4357U, // ST4B |
| 282501U, // ST4B_IMM |
| 4421U, // ST4D |
| 282501U, // ST4D_IMM |
| 0U, // ST4Fourv16b |
| 0U, // ST4Fourv16b_POST |
| 0U, // ST4Fourv2d |
| 0U, // ST4Fourv2d_POST |
| 0U, // ST4Fourv2s |
| 0U, // ST4Fourv2s_POST |
| 0U, // ST4Fourv4h |
| 0U, // ST4Fourv4h_POST |
| 0U, // ST4Fourv4s |
| 0U, // ST4Fourv4s_POST |
| 0U, // ST4Fourv8b |
| 0U, // ST4Fourv8b_POST |
| 0U, // ST4Fourv8h |
| 0U, // ST4Fourv8h_POST |
| 4485U, // ST4H |
| 282501U, // ST4H_IMM |
| 4613U, // ST4W |
| 282501U, // ST4W_IMM |
| 0U, // ST4i16 |
| 0U, // ST4i16_POST |
| 0U, // ST4i32 |
| 0U, // ST4i32_POST |
| 0U, // ST4i64 |
| 0U, // ST4i64_POST |
| 0U, // ST4i8 |
| 0U, // ST4i8_POST |
| 28U, // STGM |
| 123141U, // STGOffset |
| 11542733U, // STGPi |
| 4573U, // STGPostIndex |
| 13396301U, // STGPpost |
| 180889933U, // STGPpre |
| 299461U, // STGPreIndex |
| 0U, // STGloop |
| 28U, // STLLRB |
| 28U, // STLLRH |
| 28U, // STLLRW |
| 28U, // STLLRX |
| 28U, // STLRB |
| 28U, // STLRH |
| 28U, // STLRW |
| 28U, // STLRX |
| 123077U, // STLURBi |
| 123077U, // STLURHi |
| 123077U, // STLURWi |
| 123077U, // STLURXi |
| 311493U, // STLXPW |
| 311493U, // STLXPX |
| 123085U, // STLXRB |
| 123085U, // STLXRH |
| 123085U, // STLXRW |
| 123085U, // STLXRX |
| 11018445U, // STNPDi |
| 11542733U, // STNPQi |
| 12067021U, // STNPSi |
| 12067021U, // STNPWi |
| 11018445U, // STNPXi |
| 280901U, // STNT1B_ZRI |
| 4357U, // STNT1B_ZRR |
| 125253U, // STNT1B_ZZR_D_REAL |
| 125253U, // STNT1B_ZZR_S_REAL |
| 280901U, // STNT1D_ZRI |
| 4421U, // STNT1D_ZRR |
| 125253U, // STNT1D_ZZR_D_REAL |
| 280901U, // STNT1H_ZRI |
| 4485U, // STNT1H_ZRR |
| 125253U, // STNT1H_ZZR_D_REAL |
| 125253U, // STNT1H_ZZR_S_REAL |
| 280901U, // STNT1W_ZRI |
| 4613U, // STNT1W_ZRR |
| 125253U, // STNT1W_ZZR_D_REAL |
| 125253U, // STNT1W_ZZR_S_REAL |
| 11018445U, // STPDi |
| 12872013U, // STPDpost |
| 180365645U, // STPDpre |
| 11542733U, // STPQi |
| 13396301U, // STPQpost |
| 180889933U, // STPQpre |
| 12067021U, // STPSi |
| 13920589U, // STPSpost |
| 181414221U, // STPSpre |
| 12067021U, // STPWi |
| 13920589U, // STPWpost |
| 181414221U, // STPWpre |
| 11018445U, // STPXi |
| 12872013U, // STPXpost |
| 180365645U, // STPXpre |
| 2397U, // STRBBpost |
| 297285U, // STRBBpre |
| 14164165U, // STRBBroW |
| 14688453U, // STRBBroX |
| 4805U, // STRBBui |
| 2397U, // STRBpost |
| 297285U, // STRBpre |
| 14164165U, // STRBroW |
| 14688453U, // STRBroX |
| 4805U, // STRBui |
| 2397U, // STRDpost |
| 297285U, // STRDpre |
| 15212741U, // STRDroW |
| 15737029U, // STRDroX |
| 4869U, // STRDui |
| 2397U, // STRHHpost |
| 297285U, // STRHHpre |
| 16261317U, // STRHHroW |
| 16785605U, // STRHHroX |
| 4933U, // STRHHui |
| 2397U, // STRHpost |
| 297285U, // STRHpre |
| 16261317U, // STRHroW |
| 16785605U, // STRHroX |
| 4933U, // STRHui |
| 2397U, // STRQpost |
| 297285U, // STRQpre |
| 17309893U, // STRQroW |
| 17834181U, // STRQroX |
| 4997U, // STRQui |
| 2397U, // STRSpost |
| 297285U, // STRSpre |
| 18358469U, // STRSroW |
| 18882757U, // STRSroX |
| 5061U, // STRSui |
| 2397U, // STRWpost |
| 297285U, // STRWpre |
| 18358469U, // STRWroW |
| 18882757U, // STRWroX |
| 5061U, // STRWui |
| 2397U, // STRXpost |
| 297285U, // STRXpre |
| 15212741U, // STRXroW |
| 15737029U, // STRXroX |
| 4869U, // STRXui |
| 278725U, // STR_PXI |
| 278725U, // STR_ZXI |
| 123077U, // STTRBi |
| 123077U, // STTRHi |
| 123077U, // STTRWi |
| 123077U, // STTRXi |
| 123077U, // STURBBi |
| 123077U, // STURBi |
| 123077U, // STURDi |
| 123077U, // STURHHi |
| 123077U, // STURHi |
| 123077U, // STURQi |
| 123077U, // STURSi |
| 123077U, // STURWi |
| 123077U, // STURXi |
| 311493U, // STXPW |
| 311493U, // STXPX |
| 123085U, // STXRB |
| 123085U, // STXRH |
| 123085U, // STXRW |
| 123085U, // STXRX |
| 123141U, // STZ2GOffset |
| 4573U, // STZ2GPostIndex |
| 299461U, // STZ2GPreIndex |
| 28U, // STZGM |
| 123141U, // STZGOffset |
| 4573U, // STZGPostIndex |
| 299461U, // STZGPreIndex |
| 0U, // STZGloop |
| 8453U, // SUBG |
| 325U, // SUBHNB_ZZZ_B |
| 6U, // SUBHNB_ZZZ_H |
| 389U, // SUBHNB_ZZZ_S |
| 453U, // SUBHNT_ZZZ_B |
| 1U, // SUBHNT_ZZZ_H |
| 69U, // SUBHNT_ZZZ_S |
| 16902U, // SUBHNv2i64_v2i32 |
| 16966U, // SUBHNv2i64_v4i32 |
| 25095U, // SUBHNv4i32_v4i16 |
| 25159U, // SUBHNv4i32_v8i16 |
| 33351U, // SUBHNv8i16_v16i8 |
| 33287U, // SUBHNv8i16_v8i8 |
| 197U, // SUBP |
| 197U, // SUBPS |
| 1029U, // SUBR_ZI_B |
| 1093U, // SUBR_ZI_D |
| 11U, // SUBR_ZI_H |
| 1157U, // SUBR_ZI_S |
| 533128U, // SUBR_ZPmZ_B |
| 1057160U, // SUBR_ZPmZ_D |
| 1614536U, // SUBR_ZPmZ_H |
| 2106120U, // SUBR_ZPmZ_S |
| 837U, // SUBSWri |
| 0U, // SUBSWrr |
| 901U, // SUBSWrs |
| 965U, // SUBSWrx |
| 837U, // SUBSXri |
| 0U, // SUBSXrr |
| 901U, // SUBSXrs |
| 965U, // SUBSXrx |
| 82117U, // SUBSXrx64 |
| 837U, // SUBWri |
| 0U, // SUBWrr |
| 901U, // SUBWrs |
| 965U, // SUBWrx |
| 837U, // SUBXri |
| 0U, // SUBXrr |
| 901U, // SUBXrs |
| 965U, // SUBXrx |
| 82117U, // SUBXrx64 |
| 1029U, // SUB_ZI_B |
| 1093U, // SUB_ZI_D |
| 11U, // SUB_ZI_H |
| 1157U, // SUB_ZI_S |
| 533128U, // SUB_ZPmZ_B |
| 1057160U, // SUB_ZPmZ_D |
| 1614536U, // SUB_ZPmZ_H |
| 2106120U, // SUB_ZPmZ_S |
| 645U, // SUB_ZZZ_B |
| 389U, // SUB_ZZZ_D |
| 8U, // SUB_ZZZ_H |
| 773U, // SUB_ZZZ_S |
| 49673U, // SUBv16i8 |
| 197U, // SUBv1i64 |
| 57865U, // SUBv2i32 |
| 16902U, // SUBv2i64 |
| 66058U, // SUBv4i16 |
| 25095U, // SUBv4i32 |
| 33287U, // SUBv8i16 |
| 74250U, // SUBv8i8 |
| 2U, // SUNPKHI_ZZ_D |
| 0U, // SUNPKHI_ZZ_H |
| 2U, // SUNPKHI_ZZ_S |
| 2U, // SUNPKLO_ZZ_D |
| 0U, // SUNPKLO_ZZ_H |
| 2U, // SUNPKLO_ZZ_S |
| 533128U, // SUQADD_ZPmZ_B |
| 1057160U, // SUQADD_ZPmZ_D |
| 1614536U, // SUQADD_ZPmZ_H |
| 2106120U, // SUQADD_ZPmZ_S |
| 1U, // SUQADDv16i8 |
| 2U, // SUQADDv1i16 |
| 2U, // SUQADDv1i32 |
| 2U, // SUQADDv1i64 |
| 2U, // SUQADDv1i8 |
| 2U, // SUQADDv2i32 |
| 3U, // SUQADDv2i64 |
| 3U, // SUQADDv4i16 |
| 4U, // SUQADDv4i32 |
| 4U, // SUQADDv8i16 |
| 5U, // SUQADDv8i8 |
| 0U, // SVC |
| 0U, // SWPAB |
| 0U, // SWPAH |
| 0U, // SWPALB |
| 0U, // SWPALH |
| 0U, // SWPALW |
| 0U, // SWPALX |
| 0U, // SWPAW |
| 0U, // SWPAX |
| 0U, // SWPB |
| 0U, // SWPH |
| 0U, // SWPLB |
| 0U, // SWPLH |
| 0U, // SWPLW |
| 0U, // SWPLX |
| 0U, // SWPW |
| 0U, // SWPX |
| 0U, // SXTB_ZPmZ_D |
| 0U, // SXTB_ZPmZ_H |
| 1U, // SXTB_ZPmZ_S |
| 0U, // SXTH_ZPmZ_D |
| 1U, // SXTH_ZPmZ_S |
| 0U, // SXTW_ZPmZ_D |
| 5573U, // SYSLxt |
| 0U, // SYSxt |
| 0U, // SpeculationSafeValueW |
| 0U, // SpeculationSafeValueX |
| 0U, // TAGPstack |
| 30U, // TBL_ZZZZ_B |
| 0U, // TBL_ZZZZ_D |
| 0U, // TBL_ZZZZ_H |
| 0U, // TBL_ZZZZ_S |
| 30U, // TBL_ZZZ_B |
| 0U, // TBL_ZZZ_D |
| 0U, // TBL_ZZZ_H |
| 0U, // TBL_ZZZ_S |
| 1U, // TBLv16i8Four |
| 1U, // TBLv16i8One |
| 1U, // TBLv16i8Three |
| 1U, // TBLv16i8Two |
| 5U, // TBLv8i8Four |
| 5U, // TBLv8i8One |
| 5U, // TBLv8i8Three |
| 5U, // TBLv8i8Two |
| 5637U, // TBNZW |
| 5637U, // TBNZX |
| 0U, // TBX_ZZZ_B |
| 69U, // TBX_ZZZ_D |
| 17U, // TBX_ZZZ_H |
| 133U, // TBX_ZZZ_S |
| 1U, // TBXv16i8Four |
| 1U, // TBXv16i8One |
| 1U, // TBXv16i8Three |
| 1U, // TBXv16i8Two |
| 5U, // TBXv8i8Four |
| 5U, // TBXv8i8One |
| 5U, // TBXv8i8Three |
| 5U, // TBXv8i8Two |
| 5637U, // TBZW |
| 5637U, // TBZX |
| 0U, // TCANCEL |
| 0U, // TCOMMIT |
| 0U, // TCRETURNdi |
| 0U, // TCRETURNri |
| 0U, // TCRETURNriALL |
| 0U, // TCRETURNriBTI |
| 0U, // TLSDESCCALL |
| 0U, // TLSDESC_CALLSEQ |
| 645U, // TRN1_PPP_B |
| 389U, // TRN1_PPP_D |
| 8U, // TRN1_PPP_H |
| 773U, // TRN1_PPP_S |
| 645U, // TRN1_ZZZ_B |
| 389U, // TRN1_ZZZ_D |
| 8U, // TRN1_ZZZ_H |
| 773U, // TRN1_ZZZ_S |
| 49673U, // TRN1v16i8 |
| 57865U, // TRN1v2i32 |
| 16902U, // TRN1v2i64 |
| 66058U, // TRN1v4i16 |
| 25095U, // TRN1v4i32 |
| 33287U, // TRN1v8i16 |
| 74250U, // TRN1v8i8 |
| 645U, // TRN2_PPP_B |
| 389U, // TRN2_PPP_D |
| 8U, // TRN2_PPP_H |
| 773U, // TRN2_PPP_S |
| 645U, // TRN2_ZZZ_B |
| 389U, // TRN2_ZZZ_D |
| 8U, // TRN2_ZZZ_H |
| 773U, // TRN2_ZZZ_S |
| 49673U, // TRN2v16i8 |
| 57865U, // TRN2v2i32 |
| 16902U, // TRN2v2i64 |
| 66058U, // TRN2v4i16 |
| 25095U, // TRN2v4i32 |
| 33287U, // TRN2v8i16 |
| 74250U, // TRN2v8i8 |
| 0U, // TSB |
| 0U, // TSTART |
| 0U, // TTEST |
| 133U, // UABALB_ZZZ_D |
| 0U, // UABALB_ZZZ_H |
| 453U, // UABALB_ZZZ_S |
| 133U, // UABALT_ZZZ_D |
| 0U, // UABALT_ZZZ_H |
| 453U, // UABALT_ZZZ_S |
| 49737U, // UABALv16i8_v8i16 |
| 57929U, // UABALv2i32_v2i64 |
| 66122U, // UABALv4i16_v4i32 |
| 25159U, // UABALv4i32_v2i64 |
| 33351U, // UABALv8i16_v4i32 |
| 74314U, // UABALv8i8_v8i16 |
| 0U, // UABA_ZZZ_B |
| 69U, // UABA_ZZZ_D |
| 17U, // UABA_ZZZ_H |
| 133U, // UABA_ZZZ_S |
| 49737U, // UABAv16i8 |
| 57929U, // UABAv2i32 |
| 66122U, // UABAv4i16 |
| 25159U, // UABAv4i32 |
| 33351U, // UABAv8i16 |
| 74314U, // UABAv8i8 |
| 773U, // UABDLB_ZZZ_D |
| 30U, // UABDLB_ZZZ_H |
| 325U, // UABDLB_ZZZ_S |
| 773U, // UABDLT_ZZZ_D |
| 30U, // UABDLT_ZZZ_H |
| 325U, // UABDLT_ZZZ_S |
| 49673U, // UABDLv16i8_v8i16 |
| 57865U, // UABDLv2i32_v2i64 |
| 66058U, // UABDLv4i16_v4i32 |
| 25095U, // UABDLv4i32_v2i64 |
| 33287U, // UABDLv8i16_v4i32 |
| 74250U, // UABDLv8i8_v8i16 |
| 533128U, // UABD_ZPmZ_B |
| 1057160U, // UABD_ZPmZ_D |
| 1614536U, // UABD_ZPmZ_H |
| 2106120U, // UABD_ZPmZ_S |
| 49673U, // UABDv16i8 |
| 57865U, // UABDv2i32 |
| 66058U, // UABDv4i16 |
| 25095U, // UABDv4i32 |
| 33287U, // UABDv8i16 |
| 74250U, // UABDv8i8 |
| 136U, // UADALP_ZPmZ_D |
| 0U, // UADALP_ZPmZ_H |
| 456U, // UADALP_ZPmZ_S |
| 1U, // UADALPv16i8_v8i16 |
| 2U, // UADALPv2i32_v1i64 |
| 3U, // UADALPv4i16_v2i32 |
| 4U, // UADALPv4i32_v2i64 |
| 4U, // UADALPv8i16_v4i32 |
| 5U, // UADALPv8i8_v4i16 |
| 773U, // UADDLB_ZZZ_D |
| 30U, // UADDLB_ZZZ_H |
| 325U, // UADDLB_ZZZ_S |
| 1U, // UADDLPv16i8_v8i16 |
| 2U, // UADDLPv2i32_v1i64 |
| 3U, // UADDLPv4i16_v2i32 |
| 4U, // UADDLPv4i32_v2i64 |
| 4U, // UADDLPv8i16_v4i32 |
| 5U, // UADDLPv8i8_v4i16 |
| 773U, // UADDLT_ZZZ_D |
| 30U, // UADDLT_ZZZ_H |
| 325U, // UADDLT_ZZZ_S |
| 1U, // UADDLVv16i8v |
| 3U, // UADDLVv4i16v |
| 4U, // UADDLVv4i32v |
| 4U, // UADDLVv8i16v |
| 5U, // UADDLVv8i8v |
| 49673U, // UADDLv16i8_v8i16 |
| 57865U, // UADDLv2i32_v2i64 |
| 66058U, // UADDLv4i16_v4i32 |
| 25095U, // UADDLv4i32_v2i64 |
| 33287U, // UADDLv8i16_v4i32 |
| 74250U, // UADDLv8i8_v8i16 |
| 645U, // UADDV_VPZ_B |
| 389U, // UADDV_VPZ_D |
| 325U, // UADDV_VPZ_H |
| 773U, // UADDV_VPZ_S |
| 773U, // UADDWB_ZZZ_D |
| 30U, // UADDWB_ZZZ_H |
| 325U, // UADDWB_ZZZ_S |
| 773U, // UADDWT_ZZZ_D |
| 30U, // UADDWT_ZZZ_H |
| 325U, // UADDWT_ZZZ_S |
| 49671U, // UADDWv16i8_v8i16 |
| 57862U, // UADDWv2i32_v2i64 |
| 66055U, // UADDWv4i16_v4i32 |
| 25094U, // UADDWv4i32_v2i64 |
| 33287U, // UADDWv8i16_v4i32 |
| 74247U, // UADDWv8i8_v8i16 |
| 8389U, // UBFMWri |
| 8389U, // UBFMXri |
| 197U, // UCVTFSWDri |
| 197U, // UCVTFSWHri |
| 197U, // UCVTFSWSri |
| 197U, // UCVTFSXDri |
| 197U, // UCVTFSXHri |
| 197U, // UCVTFSXSri |
| 2U, // UCVTFUWDri |
| 2U, // UCVTFUWHri |
| 2U, // UCVTFUWSri |
| 2U, // UCVTFUXDri |
| 2U, // UCVTFUXHri |
| 2U, // UCVTFUXSri |
| 0U, // UCVTF_ZPmZ_DtoD |
| 0U, // UCVTF_ZPmZ_DtoH |
| 0U, // UCVTF_ZPmZ_DtoS |
| 0U, // UCVTF_ZPmZ_HtoH |
| 1U, // UCVTF_ZPmZ_StoD |
| 0U, // UCVTF_ZPmZ_StoH |
| 1U, // UCVTF_ZPmZ_StoS |
| 197U, // UCVTFd |
| 197U, // UCVTFh |
| 197U, // UCVTFs |
| 2U, // UCVTFv1i16 |
| 2U, // UCVTFv1i32 |
| 2U, // UCVTFv1i64 |
| 2U, // UCVTFv2f32 |
| 3U, // UCVTFv2f64 |
| 201U, // UCVTFv2i32_shift |
| 198U, // UCVTFv2i64_shift |
| 3U, // UCVTFv4f16 |
| 4U, // UCVTFv4f32 |
| 202U, // UCVTFv4i16_shift |
| 199U, // UCVTFv4i32_shift |
| 4U, // UCVTFv8f16 |
| 199U, // UCVTFv8i16_shift |
| 0U, // UDF |
| 1057160U, // UDIVR_ZPmZ_D |
| 2106120U, // UDIVR_ZPmZ_S |
| 197U, // UDIVWr |
| 197U, // UDIVXr |
| 1057160U, // UDIV_ZPmZ_D |
| 2106120U, // UDIV_ZPmZ_S |
| 1704389U, // UDOT_ZZZI_D |
| 2432U, // UDOT_ZZZI_S |
| 453U, // UDOT_ZZZ_D |
| 0U, // UDOT_ZZZ_S |
| 303689U, // UDOTlanev16i8 |
| 303690U, // UDOTlanev8i8 |
| 49737U, // UDOTv16i8 |
| 74314U, // UDOTv8i8 |
| 533128U, // UHADD_ZPmZ_B |
| 1057160U, // UHADD_ZPmZ_D |
| 1614536U, // UHADD_ZPmZ_H |
| 2106120U, // UHADD_ZPmZ_S |
| 49673U, // UHADDv16i8 |
| 57865U, // UHADDv2i32 |
| 66058U, // UHADDv4i16 |
| 25095U, // UHADDv4i32 |
| 33287U, // UHADDv8i16 |
| 74250U, // UHADDv8i8 |
| 533128U, // UHSUBR_ZPmZ_B |
| 1057160U, // UHSUBR_ZPmZ_D |
| 1614536U, // UHSUBR_ZPmZ_H |
| 2106120U, // UHSUBR_ZPmZ_S |
| 533128U, // UHSUB_ZPmZ_B |
| 1057160U, // UHSUB_ZPmZ_D |
| 1614536U, // UHSUB_ZPmZ_H |
| 2106120U, // UHSUB_ZPmZ_S |
| 49673U, // UHSUBv16i8 |
| 57865U, // UHSUBv2i32 |
| 66058U, // UHSUBv4i16 |
| 25095U, // UHSUBv4i32 |
| 33287U, // UHSUBv8i16 |
| 74250U, // UHSUBv8i8 |
| 8389U, // UMADDLrrr |
| 533128U, // UMAXP_ZPmZ_B |
| 1057160U, // UMAXP_ZPmZ_D |
| 1614536U, // UMAXP_ZPmZ_H |
| 2106120U, // UMAXP_ZPmZ_S |
| 49673U, // UMAXPv16i8 |
| 57865U, // UMAXPv2i32 |
| 66058U, // UMAXPv4i16 |
| 25095U, // UMAXPv4i32 |
| 33287U, // UMAXPv8i16 |
| 74250U, // UMAXPv8i8 |
| 645U, // UMAXV_VPZ_B |
| 389U, // UMAXV_VPZ_D |
| 325U, // UMAXV_VPZ_H |
| 773U, // UMAXV_VPZ_S |
| 1U, // UMAXVv16i8v |
| 3U, // UMAXVv4i16v |
| 4U, // UMAXVv4i32v |
| 4U, // UMAXVv8i16v |
| 5U, // UMAXVv8i8v |
| 5701U, // UMAX_ZI_B |
| 5701U, // UMAX_ZI_D |
| 23U, // UMAX_ZI_H |
| 5701U, // UMAX_ZI_S |
| 533128U, // UMAX_ZPmZ_B |
| 1057160U, // UMAX_ZPmZ_D |
| 1614536U, // UMAX_ZPmZ_H |
| 2106120U, // UMAX_ZPmZ_S |
| 49673U, // UMAXv16i8 |
| 57865U, // UMAXv2i32 |
| 66058U, // UMAXv4i16 |
| 25095U, // UMAXv4i32 |
| 33287U, // UMAXv8i16 |
| 74250U, // UMAXv8i8 |
| 533128U, // UMINP_ZPmZ_B |
| 1057160U, // UMINP_ZPmZ_D |
| 1614536U, // UMINP_ZPmZ_H |
| 2106120U, // UMINP_ZPmZ_S |
| 49673U, // UMINPv16i8 |
| 57865U, // UMINPv2i32 |
| 66058U, // UMINPv4i16 |
| 25095U, // UMINPv4i32 |
| 33287U, // UMINPv8i16 |
| 74250U, // UMINPv8i8 |
| 645U, // UMINV_VPZ_B |
| 389U, // UMINV_VPZ_D |
| 325U, // UMINV_VPZ_H |
| 773U, // UMINV_VPZ_S |
| 1U, // UMINVv16i8v |
| 3U, // UMINVv4i16v |
| 4U, // UMINVv4i32v |
| 4U, // UMINVv8i16v |
| 5U, // UMINVv8i8v |
| 5701U, // UMIN_ZI_B |
| 5701U, // UMIN_ZI_D |
| 23U, // UMIN_ZI_H |
| 5701U, // UMIN_ZI_S |
| 533128U, // UMIN_ZPmZ_B |
| 1057160U, // UMIN_ZPmZ_D |
| 1614536U, // UMIN_ZPmZ_H |
| 2106120U, // UMIN_ZPmZ_S |
| 49673U, // UMINv16i8 |
| 57865U, // UMINv2i32 |
| 66058U, // UMINv4i16 |
| 25095U, // UMINv4i32 |
| 33287U, // UMINv8i16 |
| 74250U, // UMINv8i8 |
| 1704069U, // UMLALB_ZZZI_D |
| 1704389U, // UMLALB_ZZZI_S |
| 133U, // UMLALB_ZZZ_D |
| 0U, // UMLALB_ZZZ_H |
| 453U, // UMLALB_ZZZ_S |
| 1704069U, // UMLALT_ZZZI_D |
| 1704389U, // UMLALT_ZZZI_S |
| 133U, // UMLALT_ZZZ_D |
| 0U, // UMLALT_ZZZ_H |
| 453U, // UMLALT_ZZZ_S |
| 49737U, // UMLALv16i8_v8i16 |
| 9151049U, // UMLALv2i32_indexed |
| 57929U, // UMLALv2i32_v2i64 |
| 9142858U, // UMLALv4i16_indexed |
| 66122U, // UMLALv4i16_v4i32 |
| 9151047U, // UMLALv4i32_indexed |
| 25159U, // UMLALv4i32_v2i64 |
| 9142855U, // UMLALv8i16_indexed |
| 33351U, // UMLALv8i16_v4i32 |
| 74314U, // UMLALv8i8_v8i16 |
| 1704069U, // UMLSLB_ZZZI_D |
| 1704389U, // UMLSLB_ZZZI_S |
| 133U, // UMLSLB_ZZZ_D |
| 0U, // UMLSLB_ZZZ_H |
| 453U, // UMLSLB_ZZZ_S |
| 1704069U, // UMLSLT_ZZZI_D |
| 1704389U, // UMLSLT_ZZZI_S |
| 133U, // UMLSLT_ZZZ_D |
| 0U, // UMLSLT_ZZZ_H |
| 453U, // UMLSLT_ZZZ_S |
| 49737U, // UMLSLv16i8_v8i16 |
| 9151049U, // UMLSLv2i32_indexed |
| 57929U, // UMLSLv2i32_v2i64 |
| 9142858U, // UMLSLv4i16_indexed |
| 66122U, // UMLSLv4i16_v4i32 |
| 9151047U, // UMLSLv4i32_indexed |
| 25159U, // UMLSLv4i32_v2i64 |
| 9142855U, // UMLSLv8i16_indexed |
| 33351U, // UMLSLv8i16_v4i32 |
| 74314U, // UMLSLv8i8_v8i16 |
| 2709U, // UMOVvi16 |
| 2709U, // UMOVvi32 |
| 2710U, // UMOVvi64 |
| 2710U, // UMOVvi8 |
| 8389U, // UMSUBLrrr |
| 533128U, // UMULH_ZPmZ_B |
| 1057160U, // UMULH_ZPmZ_D |
| 1614536U, // UMULH_ZPmZ_H |
| 2106120U, // UMULH_ZPmZ_S |
| 645U, // UMULH_ZZZ_B |
| 389U, // UMULH_ZZZ_D |
| 8U, // UMULH_ZZZ_H |
| 773U, // UMULH_ZZZ_S |
| 197U, // UMULHrr |
| 271109U, // UMULLB_ZZZI_D |
| 270661U, // UMULLB_ZZZI_S |
| 773U, // UMULLB_ZZZ_D |
| 30U, // UMULLB_ZZZ_H |
| 325U, // UMULLB_ZZZ_S |
| 271109U, // UMULLT_ZZZI_D |
| 270661U, // UMULLT_ZZZI_S |
| 773U, // UMULLT_ZZZ_D |
| 30U, // UMULLT_ZZZ_H |
| 325U, // UMULLT_ZZZ_S |
| 49673U, // UMULLv16i8_v8i16 |
| 10199561U, // UMULLv2i32_indexed |
| 57865U, // UMULLv2i32_v2i64 |
| 10191370U, // UMULLv4i16_indexed |
| 66058U, // UMULLv4i16_v4i32 |
| 10199559U, // UMULLv4i32_indexed |
| 25095U, // UMULLv4i32_v2i64 |
| 10191367U, // UMULLv8i16_indexed |
| 33287U, // UMULLv8i16_v4i32 |
| 74250U, // UMULLv8i8_v8i16 |
| 1029U, // UQADD_ZI_B |
| 1093U, // UQADD_ZI_D |
| 11U, // UQADD_ZI_H |
| 1157U, // UQADD_ZI_S |
| 533128U, // UQADD_ZPmZ_B |
| 1057160U, // UQADD_ZPmZ_D |
| 1614536U, // UQADD_ZPmZ_H |
| 2106120U, // UQADD_ZPmZ_S |
| 645U, // UQADD_ZZZ_B |
| 389U, // UQADD_ZZZ_D |
| 8U, // UQADD_ZZZ_H |
| 773U, // UQADD_ZZZ_S |
| 49673U, // UQADDv16i8 |
| 197U, // UQADDv1i16 |
| 197U, // UQADDv1i32 |
| 197U, // UQADDv1i64 |
| 197U, // UQADDv1i8 |
| 57865U, // UQADDv2i32 |
| 16902U, // UQADDv2i64 |
| 66058U, // UQADDv4i16 |
| 25095U, // UQADDv4i32 |
| 33287U, // UQADDv8i16 |
| 74250U, // UQADDv8i8 |
| 0U, // UQDECB_WPiI |
| 0U, // UQDECB_XPiI |
| 0U, // UQDECD_WPiI |
| 0U, // UQDECD_XPiI |
| 0U, // UQDECD_ZPiI |
| 0U, // UQDECH_WPiI |
| 0U, // UQDECH_XPiI |
| 0U, // UQDECH_ZPiI |
| 2U, // UQDECP_WP_B |
| 2U, // UQDECP_WP_D |
| 2U, // UQDECP_WP_H |
| 2U, // UQDECP_WP_S |
| 2U, // UQDECP_XP_B |
| 2U, // UQDECP_XP_D |
| 2U, // UQDECP_XP_H |
| 2U, // UQDECP_XP_S |
| 2U, // UQDECP_ZP_D |
| 0U, // UQDECP_ZP_H |
| 2U, // UQDECP_ZP_S |
| 0U, // UQDECW_WPiI |
| 0U, // UQDECW_XPiI |
| 0U, // UQDECW_ZPiI |
| 0U, // UQINCB_WPiI |
| 0U, // UQINCB_XPiI |
| 0U, // UQINCD_WPiI |
| 0U, // UQINCD_XPiI |
| 0U, // UQINCD_ZPiI |
| 0U, // UQINCH_WPiI |
| 0U, // UQINCH_XPiI |
| 0U, // UQINCH_ZPiI |
| 2U, // UQINCP_WP_B |
| 2U, // UQINCP_WP_D |
| 2U, // UQINCP_WP_H |
| 2U, // UQINCP_WP_S |
| 2U, // UQINCP_XP_B |
| 2U, // UQINCP_XP_D |
| 2U, // UQINCP_XP_H |
| 2U, // UQINCP_XP_S |
| 2U, // UQINCP_ZP_D |
| 0U, // UQINCP_ZP_H |
| 2U, // UQINCP_ZP_S |
| 0U, // UQINCW_WPiI |
| 0U, // UQINCW_XPiI |
| 0U, // UQINCW_ZPiI |
| 533128U, // UQRSHLR_ZPmZ_B |
| 1057160U, // UQRSHLR_ZPmZ_D |
| 1614536U, // UQRSHLR_ZPmZ_H |
| 2106120U, // UQRSHLR_ZPmZ_S |
| 533128U, // UQRSHL_ZPmZ_B |
| 1057160U, // UQRSHL_ZPmZ_D |
| 1614536U, // UQRSHL_ZPmZ_H |
| 2106120U, // UQRSHL_ZPmZ_S |
| 49673U, // UQRSHLv16i8 |
| 197U, // UQRSHLv1i16 |
| 197U, // UQRSHLv1i32 |
| 197U, // UQRSHLv1i64 |
| 197U, // UQRSHLv1i8 |
| 57865U, // UQRSHLv2i32 |
| 16902U, // UQRSHLv2i64 |
| 66058U, // UQRSHLv4i16 |
| 25095U, // UQRSHLv4i32 |
| 33287U, // UQRSHLv8i16 |
| 74250U, // UQRSHLv8i8 |
| 197U, // UQRSHRNB_ZZI_B |
| 12U, // UQRSHRNB_ZZI_H |
| 197U, // UQRSHRNB_ZZI_S |
| 2373U, // UQRSHRNT_ZZI_B |
| 20U, // UQRSHRNT_ZZI_H |
| 2373U, // UQRSHRNT_ZZI_S |
| 197U, // UQRSHRNb |
| 197U, // UQRSHRNh |
| 197U, // UQRSHRNs |
| 2375U, // UQRSHRNv16i8_shift |
| 198U, // UQRSHRNv2i32_shift |
| 199U, // UQRSHRNv4i16_shift |
| 2374U, // UQRSHRNv4i32_shift |
| 2375U, // UQRSHRNv8i16_shift |
| 199U, // UQRSHRNv8i8_shift |
| 533128U, // UQSHLR_ZPmZ_B |
| 1057160U, // UQSHLR_ZPmZ_D |
| 1614536U, // UQSHLR_ZPmZ_H |
| 2106120U, // UQSHLR_ZPmZ_S |
| 8840U, // UQSHL_ZPmI_B |
| 8584U, // UQSHL_ZPmI_D |
| 90824U, // UQSHL_ZPmI_H |
| 8968U, // UQSHL_ZPmI_S |
| 533128U, // UQSHL_ZPmZ_B |
| 1057160U, // UQSHL_ZPmZ_D |
| 1614536U, // UQSHL_ZPmZ_H |
| 2106120U, // UQSHL_ZPmZ_S |
| 197U, // UQSHLb |
| 197U, // UQSHLd |
| 197U, // UQSHLh |
| 197U, // UQSHLs |
| 49673U, // UQSHLv16i8 |
| 201U, // UQSHLv16i8_shift |
| 197U, // UQSHLv1i16 |
| 197U, // UQSHLv1i32 |
| 197U, // UQSHLv1i64 |
| 197U, // UQSHLv1i8 |
| 57865U, // UQSHLv2i32 |
| 201U, // UQSHLv2i32_shift |
| 16902U, // UQSHLv2i64 |
| 198U, // UQSHLv2i64_shift |
| 66058U, // UQSHLv4i16 |
| 202U, // UQSHLv4i16_shift |
| 25095U, // UQSHLv4i32 |
| 199U, // UQSHLv4i32_shift |
| 33287U, // UQSHLv8i16 |
| 199U, // UQSHLv8i16_shift |
| 74250U, // UQSHLv8i8 |
| 202U, // UQSHLv8i8_shift |
| 197U, // UQSHRNB_ZZI_B |
| 12U, // UQSHRNB_ZZI_H |
| 197U, // UQSHRNB_ZZI_S |
| 2373U, // UQSHRNT_ZZI_B |
| 20U, // UQSHRNT_ZZI_H |
| 2373U, // UQSHRNT_ZZI_S |
| 197U, // UQSHRNb |
| 197U, // UQSHRNh |
| 197U, // UQSHRNs |
| 2375U, // UQSHRNv16i8_shift |
| 198U, // UQSHRNv2i32_shift |
| 199U, // UQSHRNv4i16_shift |
| 2374U, // UQSHRNv4i32_shift |
| 2375U, // UQSHRNv8i16_shift |
| 199U, // UQSHRNv8i8_shift |
| 533128U, // UQSUBR_ZPmZ_B |
| 1057160U, // UQSUBR_ZPmZ_D |
| 1614536U, // UQSUBR_ZPmZ_H |
| 2106120U, // UQSUBR_ZPmZ_S |
| 1029U, // UQSUB_ZI_B |
| 1093U, // UQSUB_ZI_D |
| 11U, // UQSUB_ZI_H |
| 1157U, // UQSUB_ZI_S |
| 533128U, // UQSUB_ZPmZ_B |
| 1057160U, // UQSUB_ZPmZ_D |
| 1614536U, // UQSUB_ZPmZ_H |
| 2106120U, // UQSUB_ZPmZ_S |
| 645U, // UQSUB_ZZZ_B |
| 389U, // UQSUB_ZZZ_D |
| 8U, // UQSUB_ZZZ_H |
| 773U, // UQSUB_ZZZ_S |
| 49673U, // UQSUBv16i8 |
| 197U, // UQSUBv1i16 |
| 197U, // UQSUBv1i32 |
| 197U, // UQSUBv1i64 |
| 197U, // UQSUBv1i8 |
| 57865U, // UQSUBv2i32 |
| 16902U, // UQSUBv2i64 |
| 66058U, // UQSUBv4i16 |
| 25095U, // UQSUBv4i32 |
| 33287U, // UQSUBv8i16 |
| 74250U, // UQSUBv8i8 |
| 2U, // UQXTNB_ZZ_B |
| 0U, // UQXTNB_ZZ_H |
| 2U, // UQXTNB_ZZ_S |
| 2U, // UQXTNT_ZZ_B |
| 0U, // UQXTNT_ZZ_H |
| 2U, // UQXTNT_ZZ_S |
| 4U, // UQXTNv16i8 |
| 2U, // UQXTNv1i16 |
| 2U, // UQXTNv1i32 |
| 2U, // UQXTNv1i8 |
| 3U, // UQXTNv2i32 |
| 4U, // UQXTNv4i16 |
| 3U, // UQXTNv4i32 |
| 4U, // UQXTNv8i16 |
| 4U, // UQXTNv8i8 |
| 1U, // URECPE_ZPmZ_S |
| 2U, // URECPEv2i32 |
| 4U, // URECPEv4i32 |
| 533128U, // URHADD_ZPmZ_B |
| 1057160U, // URHADD_ZPmZ_D |
| 1614536U, // URHADD_ZPmZ_H |
| 2106120U, // URHADD_ZPmZ_S |
| 49673U, // URHADDv16i8 |
| 57865U, // URHADDv2i32 |
| 66058U, // URHADDv4i16 |
| 25095U, // URHADDv4i32 |
| 33287U, // URHADDv8i16 |
| 74250U, // URHADDv8i8 |
| 533128U, // URSHLR_ZPmZ_B |
| 1057160U, // URSHLR_ZPmZ_D |
| 1614536U, // URSHLR_ZPmZ_H |
| 2106120U, // URSHLR_ZPmZ_S |
| 533128U, // URSHL_ZPmZ_B |
| 1057160U, // URSHL_ZPmZ_D |
| 1614536U, // URSHL_ZPmZ_H |
| 2106120U, // URSHL_ZPmZ_S |
| 49673U, // URSHLv16i8 |
| 197U, // URSHLv1i64 |
| 57865U, // URSHLv2i32 |
| 16902U, // URSHLv2i64 |
| 66058U, // URSHLv4i16 |
| 25095U, // URSHLv4i32 |
| 33287U, // URSHLv8i16 |
| 74250U, // URSHLv8i8 |
| 8840U, // URSHR_ZPmI_B |
| 8584U, // URSHR_ZPmI_D |
| 90824U, // URSHR_ZPmI_H |
| 8968U, // URSHR_ZPmI_S |
| 197U, // URSHRd |
| 201U, // URSHRv16i8_shift |
| 201U, // URSHRv2i32_shift |
| 198U, // URSHRv2i64_shift |
| 202U, // URSHRv4i16_shift |
| 199U, // URSHRv4i32_shift |
| 199U, // URSHRv8i16_shift |
| 202U, // URSHRv8i8_shift |
| 1U, // URSQRTE_ZPmZ_S |
| 2U, // URSQRTEv2i32 |
| 4U, // URSQRTEv4i32 |
| 20U, // URSRA_ZZI_B |
| 2373U, // URSRA_ZZI_D |
| 20U, // URSRA_ZZI_H |
| 2373U, // URSRA_ZZI_S |
| 2373U, // URSRAd |
| 2377U, // URSRAv16i8_shift |
| 2377U, // URSRAv2i32_shift |
| 2374U, // URSRAv2i64_shift |
| 2378U, // URSRAv4i16_shift |
| 2375U, // URSRAv4i32_shift |
| 2375U, // URSRAv8i16_shift |
| 2378U, // URSRAv8i8_shift |
| 197U, // USHLLB_ZZI_D |
| 12U, // USHLLB_ZZI_H |
| 197U, // USHLLB_ZZI_S |
| 197U, // USHLLT_ZZI_D |
| 12U, // USHLLT_ZZI_H |
| 197U, // USHLLT_ZZI_S |
| 201U, // USHLLv16i8_shift |
| 201U, // USHLLv2i32_shift |
| 202U, // USHLLv4i16_shift |
| 199U, // USHLLv4i32_shift |
| 199U, // USHLLv8i16_shift |
| 202U, // USHLLv8i8_shift |
| 49673U, // USHLv16i8 |
| 197U, // USHLv1i64 |
| 57865U, // USHLv2i32 |
| 16902U, // USHLv2i64 |
| 66058U, // USHLv4i16 |
| 25095U, // USHLv4i32 |
| 33287U, // USHLv8i16 |
| 74250U, // USHLv8i8 |
| 197U, // USHRd |
| 201U, // USHRv16i8_shift |
| 201U, // USHRv2i32_shift |
| 198U, // USHRv2i64_shift |
| 202U, // USHRv4i16_shift |
| 199U, // USHRv4i32_shift |
| 199U, // USHRv8i16_shift |
| 202U, // USHRv8i8_shift |
| 533128U, // USQADD_ZPmZ_B |
| 1057160U, // USQADD_ZPmZ_D |
| 1614536U, // USQADD_ZPmZ_H |
| 2106120U, // USQADD_ZPmZ_S |
| 1U, // USQADDv16i8 |
| 2U, // USQADDv1i16 |
| 2U, // USQADDv1i32 |
| 2U, // USQADDv1i64 |
| 2U, // USQADDv1i8 |
| 2U, // USQADDv2i32 |
| 3U, // USQADDv2i64 |
| 3U, // USQADDv4i16 |
| 4U, // USQADDv4i32 |
| 4U, // USQADDv8i16 |
| 5U, // USQADDv8i8 |
| 20U, // USRA_ZZI_B |
| 2373U, // USRA_ZZI_D |
| 20U, // USRA_ZZI_H |
| 2373U, // USRA_ZZI_S |
| 2373U, // USRAd |
| 2377U, // USRAv16i8_shift |
| 2377U, // USRAv2i32_shift |
| 2374U, // USRAv2i64_shift |
| 2378U, // USRAv4i16_shift |
| 2375U, // USRAv4i32_shift |
| 2375U, // USRAv8i16_shift |
| 2378U, // USRAv8i8_shift |
| 773U, // USUBLB_ZZZ_D |
| 30U, // USUBLB_ZZZ_H |
| 325U, // USUBLB_ZZZ_S |
| 773U, // USUBLT_ZZZ_D |
| 30U, // USUBLT_ZZZ_H |
| 325U, // USUBLT_ZZZ_S |
| 49673U, // USUBLv16i8_v8i16 |
| 57865U, // USUBLv2i32_v2i64 |
| 66058U, // USUBLv4i16_v4i32 |
| 25095U, // USUBLv4i32_v2i64 |
| 33287U, // USUBLv8i16_v4i32 |
| 74250U, // USUBLv8i8_v8i16 |
| 773U, // USUBWB_ZZZ_D |
| 30U, // USUBWB_ZZZ_H |
| 325U, // USUBWB_ZZZ_S |
| 773U, // USUBWT_ZZZ_D |
| 30U, // USUBWT_ZZZ_H |
| 325U, // USUBWT_ZZZ_S |
| 49671U, // USUBWv16i8_v8i16 |
| 57862U, // USUBWv2i32_v2i64 |
| 66055U, // USUBWv4i16_v4i32 |
| 25094U, // USUBWv4i32_v2i64 |
| 33287U, // USUBWv8i16_v4i32 |
| 74247U, // USUBWv8i8_v8i16 |
| 2U, // UUNPKHI_ZZ_D |
| 0U, // UUNPKHI_ZZ_H |
| 2U, // UUNPKHI_ZZ_S |
| 2U, // UUNPKLO_ZZ_D |
| 0U, // UUNPKLO_ZZ_H |
| 2U, // UUNPKLO_ZZ_S |
| 0U, // UXTB_ZPmZ_D |
| 0U, // UXTB_ZPmZ_H |
| 1U, // UXTB_ZPmZ_S |
| 0U, // UXTH_ZPmZ_D |
| 1U, // UXTH_ZPmZ_S |
| 0U, // UXTW_ZPmZ_D |
| 645U, // UZP1_PPP_B |
| 389U, // UZP1_PPP_D |
| 8U, // UZP1_PPP_H |
| 773U, // UZP1_PPP_S |
| 645U, // UZP1_ZZZ_B |
| 389U, // UZP1_ZZZ_D |
| 8U, // UZP1_ZZZ_H |
| 773U, // UZP1_ZZZ_S |
| 49673U, // UZP1v16i8 |
| 57865U, // UZP1v2i32 |
| 16902U, // UZP1v2i64 |
| 66058U, // UZP1v4i16 |
| 25095U, // UZP1v4i32 |
| 33287U, // UZP1v8i16 |
| 74250U, // UZP1v8i8 |
| 645U, // UZP2_PPP_B |
| 389U, // UZP2_PPP_D |
| 8U, // UZP2_PPP_H |
| 773U, // UZP2_PPP_S |
| 645U, // UZP2_ZZZ_B |
| 389U, // UZP2_ZZZ_D |
| 8U, // UZP2_ZZZ_H |
| 773U, // UZP2_ZZZ_S |
| 49673U, // UZP2v16i8 |
| 57865U, // UZP2v2i32 |
| 16902U, // UZP2v2i64 |
| 66058U, // UZP2v4i16 |
| 25095U, // UZP2v4i32 |
| 33287U, // UZP2v8i16 |
| 74250U, // UZP2v8i8 |
| 197U, // WHILEGE_PWW_B |
| 197U, // WHILEGE_PWW_D |
| 12U, // WHILEGE_PWW_H |
| 197U, // WHILEGE_PWW_S |
| 197U, // WHILEGE_PXX_B |
| 197U, // WHILEGE_PXX_D |
| 12U, // WHILEGE_PXX_H |
| 197U, // WHILEGE_PXX_S |
| 197U, // WHILEGT_PWW_B |
| 197U, // WHILEGT_PWW_D |
| 12U, // WHILEGT_PWW_H |
| 197U, // WHILEGT_PWW_S |
| 197U, // WHILEGT_PXX_B |
| 197U, // WHILEGT_PXX_D |
| 12U, // WHILEGT_PXX_H |
| 197U, // WHILEGT_PXX_S |
| 197U, // WHILEHI_PWW_B |
| 197U, // WHILEHI_PWW_D |
| 12U, // WHILEHI_PWW_H |
| 197U, // WHILEHI_PWW_S |
| 197U, // WHILEHI_PXX_B |
| 197U, // WHILEHI_PXX_D |
| 12U, // WHILEHI_PXX_H |
| 197U, // WHILEHI_PXX_S |
| 197U, // WHILEHS_PWW_B |
| 197U, // WHILEHS_PWW_D |
| 12U, // WHILEHS_PWW_H |
| 197U, // WHILEHS_PWW_S |
| 197U, // WHILEHS_PXX_B |
| 197U, // WHILEHS_PXX_D |
| 12U, // WHILEHS_PXX_H |
| 197U, // WHILEHS_PXX_S |
| 197U, // WHILELE_PWW_B |
| 197U, // WHILELE_PWW_D |
| 12U, // WHILELE_PWW_H |
| 197U, // WHILELE_PWW_S |
| 197U, // WHILELE_PXX_B |
| 197U, // WHILELE_PXX_D |
| 12U, // WHILELE_PXX_H |
| 197U, // WHILELE_PXX_S |
| 197U, // WHILELO_PWW_B |
| 197U, // WHILELO_PWW_D |
| 12U, // WHILELO_PWW_H |
| 197U, // WHILELO_PWW_S |
| 197U, // WHILELO_PXX_B |
| 197U, // WHILELO_PXX_D |
| 12U, // WHILELO_PXX_H |
| 197U, // WHILELO_PXX_S |
| 197U, // WHILELS_PWW_B |
| 197U, // WHILELS_PWW_D |
| 12U, // WHILELS_PWW_H |
| 197U, // WHILELS_PWW_S |
| 197U, // WHILELS_PXX_B |
| 197U, // WHILELS_PXX_D |
| 12U, // WHILELS_PXX_H |
| 197U, // WHILELS_PXX_S |
| 197U, // WHILELT_PWW_B |
| 197U, // WHILELT_PWW_D |
| 12U, // WHILELT_PWW_H |
| 197U, // WHILELT_PWW_S |
| 197U, // WHILELT_PXX_B |
| 197U, // WHILELT_PXX_D |
| 12U, // WHILELT_PXX_H |
| 197U, // WHILELT_PXX_S |
| 197U, // WHILERW_PXX_B |
| 197U, // WHILERW_PXX_D |
| 12U, // WHILERW_PXX_H |
| 197U, // WHILERW_PXX_S |
| 197U, // WHILEWR_PXX_B |
| 197U, // WHILEWR_PXX_D |
| 12U, // WHILEWR_PXX_H |
| 197U, // WHILEWR_PXX_S |
| 0U, // WRFFR |
| 0U, // XAFLAG |
| 180742U, // XAR |
| 8837U, // XAR_ZZZI_B |
| 8581U, // XAR_ZZZI_D |
| 90824U, // XAR_ZZZI_H |
| 8965U, // XAR_ZZZI_S |
| 0U, // XPACD |
| 0U, // XPACI |
| 0U, // XPACLRI |
| 4U, // XTNv16i8 |
| 3U, // XTNv2i32 |
| 4U, // XTNv4i16 |
| 3U, // XTNv4i32 |
| 4U, // XTNv8i16 |
| 4U, // XTNv8i8 |
| 645U, // ZIP1_PPP_B |
| 389U, // ZIP1_PPP_D |
| 8U, // ZIP1_PPP_H |
| 773U, // ZIP1_PPP_S |
| 645U, // ZIP1_ZZZ_B |
| 389U, // ZIP1_ZZZ_D |
| 8U, // ZIP1_ZZZ_H |
| 773U, // ZIP1_ZZZ_S |
| 49673U, // ZIP1v16i8 |
| 57865U, // ZIP1v2i32 |
| 16902U, // ZIP1v2i64 |
| 66058U, // ZIP1v4i16 |
| 25095U, // ZIP1v4i32 |
| 33287U, // ZIP1v8i16 |
| 74250U, // ZIP1v8i8 |
| 645U, // ZIP2_PPP_B |
| 389U, // ZIP2_PPP_D |
| 8U, // ZIP2_PPP_H |
| 773U, // ZIP2_PPP_S |
| 645U, // ZIP2_ZZZ_B |
| 389U, // ZIP2_ZZZ_D |
| 8U, // ZIP2_ZZZ_H |
| 773U, // ZIP2_ZZZ_S |
| 49673U, // ZIP2v16i8 |
| 57865U, // ZIP2v2i32 |
| 16902U, // ZIP2v2i64 |
| 66058U, // ZIP2v4i16 |
| 25095U, // ZIP2v4i32 |
| 33287U, // ZIP2v8i16 |
| 74250U, // ZIP2v8i8 |
| }; |
| |
| O << "\t"; |
| |
| // Emit the opcode for the instruction. |
| uint64_t Bits = 0; |
| Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0; |
| Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32; |
| assert(Bits != 0 && "Cannot print this instruction."); |
| O << AsmStrs+(Bits & 8191)-1; |
| |
| |
| // Fragment 0 encoded into 6 bits for 54 unique commands. |
| switch ((Bits >> 13) & 63) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... |
| return; |
| break; |
| case 1: |
| // ABS_ZPmZ_B, ADDHNB_ZZZ_B, ADDHNT_ZZZ_B, ADDP_ZPmZ_B, ADD_ZI_B, ADD_ZPm... |
| printSVERegOp<'b'>(MI, 0, STI, O); |
| break; |
| case 2: |
| // ABS_ZPmZ_D, ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDP_ZPmZ_D, ADD_ZI_D, ADD_ZPmZ_... |
| printSVERegOp<'d'>(MI, 0, STI, O); |
| break; |
| case 3: |
| // ABS_ZPmZ_H, ADDHNB_ZZZ_H, ADDHNT_ZZZ_H, ADDP_ZPmZ_H, ADD_ZI_H, ADD_ZPm... |
| printSVERegOp<'h'>(MI, 0, STI, O); |
| O << ", "; |
| break; |
| case 4: |
| // ABS_ZPmZ_S, ADCLB_ZZZ_S, ADCLT_ZZZ_S, ADDHNB_ZZZ_S, ADDHNT_ZZZ_S, ADDP... |
| printSVERegOp<'s'>(MI, 0, STI, O); |
| break; |
| case 5: |
| // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... |
| printVRegOperand(MI, 0, STI, O); |
| break; |
| case 6: |
| // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDG, ADDPL_XXI, ADDPv2i64p, A... |
| printOperand(MI, 0, STI, O); |
| break; |
| case 7: |
| // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... |
| printVRegOperand(MI, 1, STI, O); |
| break; |
| case 8: |
| // B, BL |
| printAlignedLabel(MI, 0, STI, O); |
| return; |
| break; |
| case 9: |
| // BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, SVC, TCANCEL |
| printImmHex(MI, 0, STI, O); |
| return; |
| break; |
| case 10: |
| // Bcc |
| printCondCode(MI, 0, STI, O); |
| O << "\t"; |
| printAlignedLabel(MI, 1, STI, O); |
| return; |
| break; |
| case 11: |
| // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... |
| printOperand(MI, 1, STI, O); |
| break; |
| case 12: |
| // CASPALW, CASPAW, CASPLW, CASPW |
| printGPRSeqPairsClassOperand<32>(MI, 1, STI, O); |
| O << ", "; |
| printGPRSeqPairsClassOperand<32>(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 13: |
| // CASPALX, CASPAX, CASPLX, CASPX |
| printGPRSeqPairsClassOperand<64>(MI, 1, STI, O); |
| O << ", "; |
| printGPRSeqPairsClassOperand<64>(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 14: |
| // DMB, DSB, ISB, TSB |
| printBarrierOption(MI, 0, STI, O); |
| return; |
| break; |
| case 15: |
| // DUP_ZZI_Q, PMULLB_ZZZ_Q, PMULLT_ZZZ_Q |
| printSVERegOp<'q'>(MI, 0, STI, O); |
| O << ", "; |
| break; |
| case 16: |
| // GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ... |
| printTypedVectorList<0,'d'>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 1, STI, O); |
| break; |
| case 17: |
| // GLD1B_S_IMM_REAL, GLD1B_S_SXTW_REAL, GLD1B_S_UXTW_REAL, GLD1H_S_IMM_RE... |
| printTypedVectorList<0,'s'>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 1, STI, O); |
| break; |
| case 18: |
| // HINT |
| printImm(MI, 0, STI, O); |
| return; |
| break; |
| case 19: |
| // LD1B, LD1B_IMM, LD1RB_IMM, LD1RQ_B, LD1RQ_B_IMM, LD2B, LD2B_IMM, LD3B,... |
| printTypedVectorList<0,'b'>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 1, STI, O); |
| break; |
| case 20: |
| // LD1B_H, LD1B_H_IMM, LD1H, LD1H_IMM, LD1RB_H_IMM, LD1RH_IMM, LD1RQ_H, L... |
| printTypedVectorList<0,'h'>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 1, STI, O); |
| break; |
| case 21: |
| // LD1Fourv16b, LD1Onev16b, LD1Rv16b, LD1Threev16b, LD1Twov16b, LD2Rv16b,... |
| printTypedVectorList<16, 'b'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 22: |
| // LD1Fourv16b_POST, LD1Onev16b_POST, LD1Rv16b_POST, LD1Threev16b_POST, L... |
| printTypedVectorList<16, 'b'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 23: |
| // LD1Fourv1d, LD1Onev1d, LD1Rv1d, LD1Threev1d, LD1Twov1d, LD2Rv1d, LD3Rv... |
| printTypedVectorList<1, 'd'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 24: |
| // LD1Fourv1d_POST, LD1Onev1d_POST, LD1Rv1d_POST, LD1Threev1d_POST, LD1Tw... |
| printTypedVectorList<1, 'd'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 25: |
| // LD1Fourv2d, LD1Onev2d, LD1Rv2d, LD1Threev2d, LD1Twov2d, LD2Rv2d, LD2Tw... |
| printTypedVectorList<2, 'd'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 26: |
| // LD1Fourv2d_POST, LD1Onev2d_POST, LD1Rv2d_POST, LD1Threev2d_POST, LD1Tw... |
| printTypedVectorList<2, 'd'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 27: |
| // LD1Fourv2s, LD1Onev2s, LD1Rv2s, LD1Threev2s, LD1Twov2s, LD2Rv2s, LD2Tw... |
| printTypedVectorList<2, 's'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 28: |
| // LD1Fourv2s_POST, LD1Onev2s_POST, LD1Rv2s_POST, LD1Threev2s_POST, LD1Tw... |
| printTypedVectorList<2, 's'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 29: |
| // LD1Fourv4h, LD1Onev4h, LD1Rv4h, LD1Threev4h, LD1Twov4h, LD2Rv4h, LD2Tw... |
| printTypedVectorList<4, 'h'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 30: |
| // LD1Fourv4h_POST, LD1Onev4h_POST, LD1Rv4h_POST, LD1Threev4h_POST, LD1Tw... |
| printTypedVectorList<4, 'h'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 31: |
| // LD1Fourv4s, LD1Onev4s, LD1Rv4s, LD1Threev4s, LD1Twov4s, LD2Rv4s, LD2Tw... |
| printTypedVectorList<4, 's'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 32: |
| // LD1Fourv4s_POST, LD1Onev4s_POST, LD1Rv4s_POST, LD1Threev4s_POST, LD1Tw... |
| printTypedVectorList<4, 's'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 33: |
| // LD1Fourv8b, LD1Onev8b, LD1Rv8b, LD1Threev8b, LD1Twov8b, LD2Rv8b, LD2Tw... |
| printTypedVectorList<8, 'b'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 34: |
| // LD1Fourv8b_POST, LD1Onev8b_POST, LD1Rv8b_POST, LD1Threev8b_POST, LD1Tw... |
| printTypedVectorList<8, 'b'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 35: |
| // LD1Fourv8h, LD1Onev8h, LD1Rv8h, LD1Threev8h, LD1Twov8h, LD2Rv8h, LD2Tw... |
| printTypedVectorList<8, 'h'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 36: |
| // LD1Fourv8h_POST, LD1Onev8h_POST, LD1Rv8h_POST, LD1Threev8h_POST, LD1Tw... |
| printTypedVectorList<8, 'h'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 37: |
| // LD1i16, LD2i16, LD3i16, LD4i16, ST1i16_POST, ST2i16_POST, ST3i16_POST,... |
| printTypedVectorList<0, 'h'>(MI, 1, STI, O); |
| printVectorIndex(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| break; |
| case 38: |
| // LD1i16_POST, LD2i16_POST, LD3i16_POST, LD4i16_POST |
| printTypedVectorList<0, 'h'>(MI, 2, STI, O); |
| printVectorIndex(MI, 3, STI, O); |
| O << ", ["; |
| printOperand(MI, 4, STI, O); |
| O << "], "; |
| break; |
| case 39: |
| // LD1i32, LD2i32, LD3i32, LD4i32, ST1i32_POST, ST2i32_POST, ST3i32_POST,... |
| printTypedVectorList<0, 's'>(MI, 1, STI, O); |
| printVectorIndex(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| break; |
| case 40: |
| // LD1i32_POST, LD2i32_POST, LD3i32_POST, LD4i32_POST |
| printTypedVectorList<0, 's'>(MI, 2, STI, O); |
| printVectorIndex(MI, 3, STI, O); |
| O << ", ["; |
| printOperand(MI, 4, STI, O); |
| O << "], "; |
| break; |
| case 41: |
| // LD1i64, LD2i64, LD3i64, LD4i64, ST1i64_POST, ST2i64_POST, ST3i64_POST,... |
| printTypedVectorList<0, 'd'>(MI, 1, STI, O); |
| printVectorIndex(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| break; |
| case 42: |
| // LD1i64_POST, LD2i64_POST, LD3i64_POST, LD4i64_POST |
| printTypedVectorList<0, 'd'>(MI, 2, STI, O); |
| printVectorIndex(MI, 3, STI, O); |
| O << ", ["; |
| printOperand(MI, 4, STI, O); |
| O << "], "; |
| break; |
| case 43: |
| // LD1i8, LD2i8, LD3i8, LD4i8, ST1i8_POST, ST2i8_POST, ST3i8_POST, ST4i8_... |
| printTypedVectorList<0, 'b'>(MI, 1, STI, O); |
| printVectorIndex(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| break; |
| case 44: |
| // LD1i8_POST, LD2i8_POST, LD3i8_POST, LD4i8_POST |
| printTypedVectorList<0, 'b'>(MI, 2, STI, O); |
| printVectorIndex(MI, 3, STI, O); |
| O << ", ["; |
| printOperand(MI, 4, STI, O); |
| O << "], "; |
| break; |
| case 45: |
| // LDR_PXI, LDR_ZXI, MOVPRFX_ZZ, PTEST_PP, STR_PXI, STR_ZXI |
| printSVERegOp<>(MI, 0, STI, O); |
| break; |
| case 46: |
| // MSR |
| printMSRSystemRegister(MI, 0, STI, O); |
| O << ", "; |
| printOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 47: |
| // MSRpstateImm1, MSRpstateImm4 |
| printSystemPStateField(MI, 0, STI, O); |
| O << ", "; |
| printOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 48: |
| // PRFB_D_PZI, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_SCALED, PRF... |
| printPrefetchOp<true>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 1, STI, O); |
| O << ", ["; |
| break; |
| case 49: |
| // PRFMl, PRFMroW, PRFMroX, PRFMui, PRFUMi |
| printPrefetchOp(MI, 0, STI, O); |
| break; |
| case 50: |
| // ST1i16, ST2i16, ST3i16, ST4i16 |
| printTypedVectorList<0, 'h'>(MI, 0, STI, O); |
| printVectorIndex(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 51: |
| // ST1i32, ST2i32, ST3i32, ST4i32 |
| printTypedVectorList<0, 's'>(MI, 0, STI, O); |
| printVectorIndex(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 52: |
| // ST1i64, ST2i64, ST3i64, ST4i64 |
| printTypedVectorList<0, 'd'>(MI, 0, STI, O); |
| printVectorIndex(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 53: |
| // ST1i8, ST2i8, ST3i8, ST4i8 |
| printTypedVectorList<0, 'b'>(MI, 0, STI, O); |
| printVectorIndex(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| } |
| |
| |
| // Fragment 1 encoded into 6 bits for 60 unique commands. |
| switch ((Bits >> 19) & 63) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ABSv1i64, ADCLB_ZZZ_D, ADCLB_ZZZ_S... |
| O << ", "; |
| break; |
| case 1: |
| // ABS_ZPmZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H, CPY_ZPmI_... |
| printSVERegOp<>(MI, 2, STI, O); |
| O << "/m, "; |
| break; |
| case 2: |
| // ABSv16i8, ADDHNv8i16_v16i8, ADDPv16i8, ADDv16i8, AESDrr, AESErr, AESIM... |
| O << ".16b, "; |
| break; |
| case 3: |
| // ABSv2i32, ADDHNv2i64_v2i32, ADDPv2i32, ADDv2i32, BICv2i32, CLSv2i32, C... |
| O << ".2s, "; |
| break; |
| case 4: |
| // ABSv2i64, ADDPv2i64, ADDv2i64, CMEQv2i64, CMEQv2i64rz, CMGEv2i64, CMGE... |
| O << ".2d, "; |
| break; |
| case 5: |
| // ABSv4i16, ADDHNv4i32_v4i16, ADDPv4i16, ADDv4i16, BICv4i16, CLSv4i16, C... |
| O << ".4h, "; |
| break; |
| case 6: |
| // ABSv4i32, ADDHNv2i64_v4i32, ADDPv4i32, ADDv4i32, BICv4i32, CLSv4i32, C... |
| O << ".4s, "; |
| break; |
| case 7: |
| // ABSv8i16, ADDHNv4i32_v8i16, ADDPv8i16, ADDv8i16, BICv8i16, CLSv8i16, C... |
| O << ".8h, "; |
| break; |
| case 8: |
| // ABSv8i8, ADDHNv8i16_v8i8, ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8... |
| O << ".8b, "; |
| break; |
| case 9: |
| // ADDHNB_ZZZ_H, RADDHNB_ZZZ_H, RSHRNB_ZZI_H, RSUBHNB_ZZZ_H, SHRNB_ZZI_H,... |
| printSVERegOp<'s'>(MI, 1, STI, O); |
| break; |
| case 10: |
| // ADDHNT_ZZZ_H, PRFB_S_PZI, PRFD_S_PZI, PRFH_S_PZI, PRFW_S_PZI, RADDHNT_... |
| printSVERegOp<'s'>(MI, 2, STI, O); |
| break; |
| case 11: |
| // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID... |
| printSVERegOp<>(MI, 1, STI, O); |
| break; |
| case 12: |
| // ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_ZZI_H, BDEP_ZZZ_H, BEXT_ZZZ_H... |
| printSVERegOp<'h'>(MI, 1, STI, O); |
| break; |
| case 13: |
| // ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, ADR_LSL_ZZZ_D_2, ADR_LSL_ZZZ_D_3, AD... |
| O << ", ["; |
| break; |
| case 14: |
| // AUTDZA, AUTDZB, AUTIZA, AUTIZB, BLR, BLRAAZ, BLRABZ, BR, BRAAZ, BRABZ,... |
| return; |
| break; |
| case 15: |
| // CMLA_ZZZI_H, CMLA_ZZZ_H, DECP_ZP_H, EORBT_ZZZ_H, EORTB_ZZZ_H, FCMLA_ZZ... |
| printSVERegOp<'h'>(MI, 2, STI, O); |
| break; |
| case 16: |
| // DECH_ZPiI, INCH_ZPiI, SQDECH_ZPiI, SQINCH_ZPiI, UQDECH_ZPiI, UQINCH_ZP... |
| printSVEPattern(MI, 2, STI, O); |
| O << ", mul "; |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 17: |
| // DUP_ZI_H |
| printImm8OptLsl<int16_t>(MI, 1, STI, O); |
| return; |
| break; |
| case 18: |
| // DUP_ZR_H, INDEX_II_H, INDEX_IR_H, INDEX_RI_H, INDEX_RR_H, WHILEGE_PWW_... |
| printOperand(MI, 1, STI, O); |
| break; |
| case 19: |
| // DUP_ZZI_Q |
| printSVERegOp<'q'>(MI, 1, STI, O); |
| printVectorIndex(MI, 2, STI, O); |
| return; |
| break; |
| case 20: |
| // FCMPDri, FCMPEDri, FCMPEHri, FCMPESri, FCMPHri, FCMPSri |
| O << ", #0.0"; |
| return; |
| break; |
| case 21: |
| // FDUP_ZI_H |
| printFPImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 22: |
| // FMOVXDHighr, INSvi64gpr, INSvi64lane |
| O << ".d"; |
| printVectorIndex(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 23: |
| // GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ... |
| O << "/z, ["; |
| break; |
| case 24: |
| // INSR_ZR_H, INSR_ZV_H, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_S... |
| printOperand(MI, 2, STI, O); |
| break; |
| case 25: |
| // INSvi16gpr, INSvi16lane |
| O << ".h"; |
| printVectorIndex(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 26: |
| // INSvi32gpr, INSvi32lane |
| O << ".s"; |
| printVectorIndex(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 27: |
| // INSvi8gpr, INSvi8lane |
| O << ".b"; |
| printVectorIndex(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 28: |
| // LD1Fourv16b_POST, LD1Fourv2d_POST, LD1Fourv4s_POST, LD1Fourv8h_POST, L... |
| printPostIncOperand<64>(MI, 3, STI, O); |
| return; |
| break; |
| case 29: |
| // LD1Fourv1d_POST, LD1Fourv2s_POST, LD1Fourv4h_POST, LD1Fourv8b_POST, LD... |
| printPostIncOperand<32>(MI, 3, STI, O); |
| return; |
| break; |
| case 30: |
| // LD1Onev16b_POST, LD1Onev2d_POST, LD1Onev4s_POST, LD1Onev8h_POST, LD1Tw... |
| printPostIncOperand<16>(MI, 3, STI, O); |
| return; |
| break; |
| case 31: |
| // LD1Onev1d_POST, LD1Onev2s_POST, LD1Onev4h_POST, LD1Onev8b_POST, LD1Rv1... |
| printPostIncOperand<8>(MI, 3, STI, O); |
| return; |
| break; |
| case 32: |
| // LD1Rv16b_POST, LD1Rv8b_POST |
| printPostIncOperand<1>(MI, 3, STI, O); |
| return; |
| break; |
| case 33: |
| // LD1Rv2s_POST, LD1Rv4s_POST, LD2Rv4h_POST, LD2Rv8h_POST, LD4Rv16b_POST,... |
| printPostIncOperand<4>(MI, 3, STI, O); |
| return; |
| break; |
| case 34: |
| // LD1Rv4h_POST, LD1Rv8h_POST, LD2Rv16b_POST, LD2Rv8b_POST |
| printPostIncOperand<2>(MI, 3, STI, O); |
| return; |
| break; |
| case 35: |
| // LD1Threev16b_POST, LD1Threev2d_POST, LD1Threev4s_POST, LD1Threev8h_POS... |
| printPostIncOperand<48>(MI, 3, STI, O); |
| return; |
| break; |
| case 36: |
| // LD1Threev1d_POST, LD1Threev2s_POST, LD1Threev4h_POST, LD1Threev8b_POST... |
| printPostIncOperand<24>(MI, 3, STI, O); |
| return; |
| break; |
| case 37: |
| // LD1i16, LD1i32, LD1i64, LD1i8, LD2i16, LD2i32, LD2i64, LD2i8, LD3i16, ... |
| O << ']'; |
| return; |
| break; |
| case 38: |
| // LD1i16_POST, LD2i8_POST |
| printPostIncOperand<2>(MI, 5, STI, O); |
| return; |
| break; |
| case 39: |
| // LD1i32_POST, LD2i16_POST, LD4i8_POST |
| printPostIncOperand<4>(MI, 5, STI, O); |
| return; |
| break; |
| case 40: |
| // LD1i64_POST, LD2i32_POST, LD4i16_POST |
| printPostIncOperand<8>(MI, 5, STI, O); |
| return; |
| break; |
| case 41: |
| // LD1i8_POST |
| printPostIncOperand<1>(MI, 5, STI, O); |
| return; |
| break; |
| case 42: |
| // LD2i64_POST, LD4i32_POST |
| printPostIncOperand<16>(MI, 5, STI, O); |
| return; |
| break; |
| case 43: |
| // LD3Rv16b_POST, LD3Rv8b_POST |
| printPostIncOperand<3>(MI, 3, STI, O); |
| return; |
| break; |
| case 44: |
| // LD3Rv2s_POST, LD3Rv4s_POST |
| printPostIncOperand<12>(MI, 3, STI, O); |
| return; |
| break; |
| case 45: |
| // LD3Rv4h_POST, LD3Rv8h_POST |
| printPostIncOperand<6>(MI, 3, STI, O); |
| return; |
| break; |
| case 46: |
| // LD3i16_POST |
| printPostIncOperand<6>(MI, 5, STI, O); |
| return; |
| break; |
| case 47: |
| // LD3i32_POST |
| printPostIncOperand<12>(MI, 5, STI, O); |
| return; |
| break; |
| case 48: |
| // LD3i64_POST |
| printPostIncOperand<24>(MI, 5, STI, O); |
| return; |
| break; |
| case 49: |
| // LD3i8_POST |
| printPostIncOperand<3>(MI, 5, STI, O); |
| return; |
| break; |
| case 50: |
| // LD4i64_POST |
| printPostIncOperand<32>(MI, 5, STI, O); |
| return; |
| break; |
| case 51: |
| // PMULLB_ZZZ_H, PMULLT_ZZZ_H, PUNPKHI_PP, PUNPKLO_PP, SABDLB_ZZZ_H, SABD... |
| printSVERegOp<'b'>(MI, 1, STI, O); |
| break; |
| case 52: |
| // PMULLB_ZZZ_Q, PMULLT_ZZZ_Q |
| printSVERegOp<'d'>(MI, 1, STI, O); |
| O << ", "; |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| return; |
| break; |
| case 53: |
| // PMULLv1i64, PMULLv2i64 |
| O << ".1q, "; |
| printVRegOperand(MI, 1, STI, O); |
| break; |
| case 54: |
| // PRFB_D_PZI, PRFD_D_PZI, PRFH_D_PZI, PRFW_D_PZI |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 55: |
| // PTRUES_H, PTRUE_H |
| printSVEPattern(MI, 1, STI, O); |
| return; |
| break; |
| case 56: |
| // SABALB_ZZZ_H, SABALT_ZZZ_H, SMLALB_ZZZ_H, SMLALT_ZZZ_H, SMLSLB_ZZZ_H, ... |
| printSVERegOp<'b'>(MI, 2, STI, O); |
| O << ", "; |
| printSVERegOp<'b'>(MI, 3, STI, O); |
| return; |
| break; |
| case 57: |
| // SADALPv2i32_v1i64, SADDLPv2i32_v1i64, UADALPv2i32_v1i64, UADDLPv2i32_v... |
| O << ".1d, "; |
| break; |
| case 58: |
| // ST1i16_POST, ST1i32_POST, ST1i64_POST, ST1i8_POST, ST2i16_POST, ST2i32... |
| O << "], "; |
| break; |
| case 59: |
| // TBL_ZZZZ_H, TBL_ZZZ_H |
| printTypedVectorList<0,'h'>(MI, 1, STI, O); |
| O << ", "; |
| printSVERegOp<'h'>(MI, 2, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 2 encoded into 6 bits for 62 unique commands. |
| switch ((Bits >> 25) & 63) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, BRKA_PPmP, BRKB_PPmP, CLS_ZPmZ_B, ... |
| printSVERegOp<>(MI, 2, STI, O); |
| O << "/m, "; |
| break; |
| case 1: |
| // ABS_ZPmZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H, FABS_ZPmZ... |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| return; |
| break; |
| case 2: |
| // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... |
| printVRegOperand(MI, 1, STI, O); |
| break; |
| case 3: |
| // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDG, ADDPL_XXI, ADDSWri, ADDS... |
| printOperand(MI, 1, STI, O); |
| break; |
| case 4: |
| // ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDHNT_ZZZ_S, CMLA_ZZZ_D, DECP_ZP_D, EORBT_Z... |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| break; |
| case 5: |
| // ADCLB_ZZZ_S, ADCLT_ZZZ_S, CMLA_ZZZI_S, CMLA_ZZZ_S, DECP_ZP_S, EORBT_ZZ... |
| printSVERegOp<'s'>(MI, 2, STI, O); |
| break; |
| case 6: |
| // ADDHNB_ZZZ_B, DECP_XP_H, INCP_XP_H, RADDHNB_ZZZ_B, RSHRNB_ZZI_B, RSUBH... |
| printSVERegOp<'h'>(MI, 1, STI, O); |
| break; |
| case 7: |
| // ADDHNB_ZZZ_H, ADDHNT_ZZZ_H, ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_Z... |
| O << ", "; |
| break; |
| case 8: |
| // ADDHNB_ZZZ_S, ADD_ZI_D, ADD_ZZZ_D, ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, A... |
| printSVERegOp<'d'>(MI, 1, STI, O); |
| break; |
| case 9: |
| // ADDHNT_ZZZ_B, CDOT_ZZZI_D, CDOT_ZZZ_D, FMLALB_ZZZI_SHH, FMLALB_ZZZ_SHH... |
| printSVERegOp<'h'>(MI, 2, STI, O); |
| break; |
| case 10: |
| // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... |
| printVRegOperand(MI, 2, STI, O); |
| break; |
| case 11: |
| // ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPm... |
| printSVERegOp<>(MI, 1, STI, O); |
| break; |
| case 12: |
| // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID... |
| O << "/m, "; |
| break; |
| case 13: |
| // ADD_ZI_B, ADD_ZZZ_B, AESD_ZZZ_B, AESE_ZZZ_B, AESIMC_ZZ_B, AESMC_ZZ_B, ... |
| printSVERegOp<'b'>(MI, 1, STI, O); |
| break; |
| case 14: |
| // ADD_ZI_S, ADD_ZZZ_S, ADR_LSL_ZZZ_S_0, ADR_LSL_ZZZ_S_1, ADR_LSL_ZZZ_S_2... |
| printSVERegOp<'s'>(MI, 1, STI, O); |
| break; |
| case 15: |
| // ADRP |
| printAdrpLabel(MI, 1, STI, O); |
| return; |
| break; |
| case 16: |
| // BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, C... |
| printOperand(MI, 2, STI, O); |
| break; |
| case 17: |
| // BICv2i32, BICv4i16, BICv4i32, BICv8i16, MOVKWi, MOVKXi, ORRv2i32, ORRv... |
| printImm(MI, 2, STI, O); |
| printShifter(MI, 3, STI, O); |
| return; |
| break; |
| case 18: |
| // CBNZW, CBNZX, CBZW, CBZX, LDRDl, LDRQl, LDRSWl, LDRSl, LDRWl, LDRXl, P... |
| printAlignedLabel(MI, 1, STI, O); |
| return; |
| break; |
| case 19: |
| // CDOT_ZZZI_S, CDOT_ZZZ_S, CMLA_ZZZ_B, EORBT_ZZZ_B, EORTB_ZZZ_B, SABA_ZZ... |
| printSVERegOp<'b'>(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 20: |
| // CMPEQ_PPzZI_H, CMPEQ_PPzZZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_PPzZI_H, CMPGE... |
| O << "/z, "; |
| break; |
| case 21: |
| // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI, PTRUES_B, PTRUES_D, PTRUES... |
| printSVEPattern(MI, 1, STI, O); |
| break; |
| case 22: |
| // CPY_ZPmI_H |
| printImm8OptLsl<int16_t>(MI, 3, STI, O); |
| return; |
| break; |
| case 23: |
| // CPY_ZPmR_H, CPY_ZPmV_H, INSvi16gpr, INSvi32gpr, INSvi64gpr, INSvi8gpr,... |
| printOperand(MI, 3, STI, O); |
| break; |
| case 24: |
| // DECB_XPiI, DECD_XPiI, DECD_ZPiI, DECH_XPiI, DECW_XPiI, DECW_ZPiI, INCB... |
| printSVEPattern(MI, 2, STI, O); |
| O << ", mul "; |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 25: |
| // DECP_ZP_H, DUP_ZR_H, FEXPA_ZZ_H, FRECPE_ZZ_H, FRSQRTE_ZZ_H, INCP_ZP_H,... |
| return; |
| break; |
| case 26: |
| // DUPM_ZI |
| printLogicalImm<int64_t>(MI, 1, STI, O); |
| return; |
| break; |
| case 27: |
| // DUP_ZI_B |
| printImm8OptLsl<int8_t>(MI, 1, STI, O); |
| return; |
| break; |
| case 28: |
| // DUP_ZI_D |
| printImm8OptLsl<int64_t>(MI, 1, STI, O); |
| return; |
| break; |
| case 29: |
| // DUP_ZI_S |
| printImm8OptLsl<int32_t>(MI, 1, STI, O); |
| return; |
| break; |
| case 30: |
| // DUP_ZZI_H |
| printVectorIndex(MI, 2, STI, O); |
| return; |
| break; |
| case 31: |
| // EXT_ZZI_B, TBL_ZZZZ_B, TBL_ZZZ_B |
| printTypedVectorList<0,'b'>(MI, 1, STI, O); |
| O << ", "; |
| break; |
| case 32: |
| // FCPY_ZPmI_H |
| printFPImmOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 33: |
| // FCVTNT_ZPmZ_StoH, FCVT_ZPmZ_StoH, SCVTF_ZPmZ_StoH, UCVTF_ZPmZ_StoH |
| printSVERegOp<'s'>(MI, 3, STI, O); |
| return; |
| break; |
| case 34: |
| // FCVT_ZPmZ_DtoH, SCVTF_ZPmZ_DtoH, UCVTF_ZPmZ_DtoH |
| printSVERegOp<'d'>(MI, 3, STI, O); |
| return; |
| break; |
| case 35: |
| // FDUP_ZI_D, FDUP_ZI_S, FMOVDi, FMOVHi, FMOVSi, FMOVv2f32_ns, FMOVv2f64_... |
| printFPImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 36: |
| // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane |
| printVRegOperand(MI, 3, STI, O); |
| break; |
| case 37: |
| // LDADDAB, LDADDAH, LDADDALB, LDADDALH, LDADDALW, LDADDALX, LDADDAW, LDA... |
| printOperand(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 38: |
| // MOVID, MOVIv2d_ns |
| printSIMDType10Operand(MI, 1, STI, O); |
| return; |
| break; |
| case 39: |
| // MOVIv16b_ns, MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl... |
| printImm(MI, 1, STI, O); |
| break; |
| case 40: |
| // MRS |
| printMRSSystemRegister(MI, 1, STI, O); |
| return; |
| break; |
| case 41: |
| // PMULLv1i64 |
| O << ".1d, "; |
| printVRegOperand(MI, 2, STI, O); |
| O << ".1d"; |
| return; |
| break; |
| case 42: |
| // PMULLv2i64 |
| O << ".2d, "; |
| printVRegOperand(MI, 2, STI, O); |
| O << ".2d"; |
| return; |
| break; |
| case 43: |
| // PRFD_D_PZI |
| printImmScale<8>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 44: |
| // PRFH_D_PZI |
| printImmScale<2>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 45: |
| // PRFW_D_PZI |
| printImmScale<4>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 46: |
| // SQDECB_XPiWdI, SQDECD_XPiWdI, SQDECH_XPiWdI, SQDECW_XPiWdI, SQINCB_XPi... |
| printGPR64as32(MI, 1, STI, O); |
| O << ", "; |
| printSVEPattern(MI, 2, STI, O); |
| O << ", mul "; |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 47: |
| // ST1i16_POST, ST2i8_POST |
| printPostIncOperand<2>(MI, 4, STI, O); |
| return; |
| break; |
| case 48: |
| // ST1i32_POST, ST2i16_POST, ST4i8_POST |
| printPostIncOperand<4>(MI, 4, STI, O); |
| return; |
| break; |
| case 49: |
| // ST1i64_POST, ST2i32_POST, ST4i16_POST |
| printPostIncOperand<8>(MI, 4, STI, O); |
| return; |
| break; |
| case 50: |
| // ST1i8_POST |
| printPostIncOperand<1>(MI, 4, STI, O); |
| return; |
| break; |
| case 51: |
| // ST2i64_POST, ST4i32_POST |
| printPostIncOperand<16>(MI, 4, STI, O); |
| return; |
| break; |
| case 52: |
| // ST3i16_POST |
| printPostIncOperand<6>(MI, 4, STI, O); |
| return; |
| break; |
| case 53: |
| // ST3i32_POST |
| printPostIncOperand<12>(MI, 4, STI, O); |
| return; |
| break; |
| case 54: |
| // ST3i64_POST |
| printPostIncOperand<24>(MI, 4, STI, O); |
| return; |
| break; |
| case 55: |
| // ST3i8_POST |
| printPostIncOperand<3>(MI, 4, STI, O); |
| return; |
| break; |
| case 56: |
| // ST4i64_POST |
| printPostIncOperand<32>(MI, 4, STI, O); |
| return; |
| break; |
| case 57: |
| // SYSxt |
| printSysCROperand(MI, 1, STI, O); |
| O << ", "; |
| printSysCROperand(MI, 2, STI, O); |
| O << ", "; |
| printOperand(MI, 3, STI, O); |
| O << ", "; |
| printOperand(MI, 4, STI, O); |
| return; |
| break; |
| case 58: |
| // TBL_ZZZZ_D, TBL_ZZZ_D |
| printTypedVectorList<0,'d'>(MI, 1, STI, O); |
| O << ", "; |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| return; |
| break; |
| case 59: |
| // TBL_ZZZZ_S, TBL_ZZZ_S |
| printTypedVectorList<0,'s'>(MI, 1, STI, O); |
| O << ", "; |
| printSVERegOp<'s'>(MI, 2, STI, O); |
| return; |
| break; |
| case 60: |
| // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBLv8i8Four, TB... |
| printTypedVectorList<16, 'b'>(MI, 1, STI, O); |
| O << ", "; |
| printVRegOperand(MI, 2, STI, O); |
| break; |
| case 61: |
| // TBXv16i8Four, TBXv16i8One, TBXv16i8Three, TBXv16i8Two, TBXv8i8Four, TB... |
| printTypedVectorList<16, 'b'>(MI, 2, STI, O); |
| O << ", "; |
| printVRegOperand(MI, 3, STI, O); |
| break; |
| } |
| |
| |
| // Fragment 3 encoded into 7 bits for 96 unique commands. |
| switch ((Bits >> 31) & 127) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ABS_ZPmZ_B, BRKA_PPmP, BRKB_PPmP, CDOT_ZZZI_S, CDOT_ZZZ_S, CLS_ZPmZ_B,... |
| printSVERegOp<'b'>(MI, 3, STI, O); |
| break; |
| case 1: |
| // ABS_ZPmZ_D, CLS_ZPmZ_D, CLZ_ZPmZ_D, CNOT_ZPmZ_D, CNT_ZPmZ_D, FABS_ZPmZ... |
| printSVERegOp<'d'>(MI, 3, STI, O); |
| return; |
| break; |
| case 2: |
| // ABS_ZPmZ_S, ADDHNT_ZZZ_H, CLS_ZPmZ_S, CLZ_ZPmZ_S, CNOT_ZPmZ_S, CNT_ZPm... |
| printSVERegOp<'s'>(MI, 3, STI, O); |
| return; |
| break; |
| case 3: |
| // ABSv16i8, ADDVv16i8v, AESDrr, AESErr, AESIMCrr, AESMCrr, CLSv16i8, CLZ... |
| O << ".16b"; |
| return; |
| break; |
| case 4: |
| // ABSv1i64, ADR, AESIMC_ZZ_B, AESMC_ZZ_B, AUTDA, AUTDB, AUTIA, AUTIB, BL... |
| return; |
| break; |
| case 5: |
| // ABSv2i32, CLSv2i32, CLZv2i32, FABSv2f32, FADDPv2i32p, FCVTASv2f32, FCV... |
| O << ".2s"; |
| return; |
| break; |
| case 6: |
| // ABSv2i64, ADDPv2i64p, FABSv2f64, FADDPv2i64p, FCVTASv2f64, FCVTAUv2f64... |
| O << ".2d"; |
| return; |
| break; |
| case 7: |
| // ABSv4i16, ADDVv4i16v, CLSv4i16, CLZv4i16, FABSv4f16, FCVTASv4f16, FCVT... |
| O << ".4h"; |
| return; |
| break; |
| case 8: |
| // ABSv4i32, ADDVv4i32v, CLSv4i32, CLZv4i32, FABSv4f32, FCVTASv4f32, FCVT... |
| O << ".4s"; |
| return; |
| break; |
| case 9: |
| // ABSv8i16, ADDVv8i16v, CLSv8i16, CLZv8i16, FABSv8f16, FCVTASv8f16, FCVT... |
| O << ".8h"; |
| return; |
| break; |
| case 10: |
| // ABSv8i8, ADDVv8i8v, CLSv8i8, CLZv8i8, CNTv8i8, NEGv8i8, NOTv8i8, RBITv... |
| O << ".8b"; |
| return; |
| break; |
| case 11: |
| // ADCLB_ZZZ_D, ADCLB_ZZZ_S, ADCLT_ZZZ_D, ADCLT_ZZZ_S, ADCSWr, ADCSXr, AD... |
| O << ", "; |
| break; |
| case 12: |
| // ADDHNB_ZZZ_H, RADDHNB_ZZZ_H, RSUBHNB_ZZZ_H, SUBHNB_ZZZ_H |
| printSVERegOp<'s'>(MI, 2, STI, O); |
| return; |
| break; |
| case 13: |
| // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... |
| O << ".2d, "; |
| break; |
| case 14: |
| // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... |
| O << ".4s, "; |
| break; |
| case 15: |
| // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, CMEQv8i16, CMG... |
| O << ".8h, "; |
| break; |
| case 16: |
| // ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPm... |
| O << "/m, "; |
| break; |
| case 17: |
| // ADDP_ZPmZ_H, ADD_ZPmZ_H, ADD_ZZZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ... |
| printSVERegOp<'h'>(MI, 2, STI, O); |
| break; |
| case 18: |
| // ADDPv16i8, ADDv16i8, ANDv16i8, BCAX, BICv16i8, BIFv16i8, BITv16i8, BSL... |
| O << ".16b, "; |
| break; |
| case 19: |
| // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... |
| O << ".2s, "; |
| break; |
| case 20: |
| // ADDPv4i16, ADDv4i16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMHIv4i16, CMHSv... |
| O << ".4h, "; |
| break; |
| case 21: |
| // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... |
| O << ".8b, "; |
| break; |
| case 22: |
| // ADD_ZI_H, SQADD_ZI_H, SQSUB_ZI_H, SUBR_ZI_H, SUB_ZI_H, UQADD_ZI_H, UQS... |
| printImm8OptLsl<uint16_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 23: |
| // ANDS_PPzPP, AND_PPzPP, BICS_PPzPP, BIC_PPzPP, BRKAS_PPzP, BRKA_PPzP, B... |
| O << "/z, "; |
| break; |
| case 24: |
| // ASR_WIDE_ZZZ_H, LSL_WIDE_ZZZ_H, LSR_WIDE_ZZZ_H |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| return; |
| break; |
| case 25: |
| // ASR_ZZI_H, INDEX_II_H, INDEX_IR_H, INDEX_RI_H, INDEX_RR_H, LSL_ZZI_H, ... |
| printOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 26: |
| // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... |
| O << ", ["; |
| break; |
| case 27: |
| // CMEQv16i8rz, CMGEv16i8rz, CMGTv16i8rz, CMLEv16i8rz, CMLTv16i8rz |
| O << ".16b, #0"; |
| return; |
| break; |
| case 28: |
| // CMEQv1i64rz, CMGEv1i64rz, CMGTv1i64rz, CMLEv1i64rz, CMLTv1i64rz |
| O << ", #0"; |
| return; |
| break; |
| case 29: |
| // CMEQv2i32rz, CMGEv2i32rz, CMGTv2i32rz, CMLEv2i32rz, CMLTv2i32rz |
| O << ".2s, #0"; |
| return; |
| break; |
| case 30: |
| // CMEQv2i64rz, CMGEv2i64rz, CMGTv2i64rz, CMLEv2i64rz, CMLTv2i64rz |
| O << ".2d, #0"; |
| return; |
| break; |
| case 31: |
| // CMEQv4i16rz, CMGEv4i16rz, CMGTv4i16rz, CMLEv4i16rz, CMLTv4i16rz |
| O << ".4h, #0"; |
| return; |
| break; |
| case 32: |
| // CMEQv4i32rz, CMGEv4i32rz, CMGTv4i32rz, CMLEv4i32rz, CMLTv4i32rz |
| O << ".4s, #0"; |
| return; |
| break; |
| case 33: |
| // CMEQv8i16rz, CMGEv8i16rz, CMGTv8i16rz, CMLEv8i16rz, CMLTv8i16rz |
| O << ".8h, #0"; |
| return; |
| break; |
| case 34: |
| // CMEQv8i8rz, CMGEv8i8rz, CMGTv8i8rz, CMLEv8i8rz, CMLTv8i8rz |
| O << ".8b, #0"; |
| return; |
| break; |
| case 35: |
| // CMLA_ZZZI_H, CMLA_ZZZ_H, EORBT_ZZZ_H, EORTB_ZZZ_H, FCMLA_ZPmZZ_H, FCML... |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| break; |
| case 36: |
| // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI |
| O << ", mul "; |
| printOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 37: |
| // CPY_ZPmI_B |
| printImm8OptLsl<int8_t>(MI, 3, STI, O); |
| return; |
| break; |
| case 38: |
| // CPY_ZPmI_D |
| printImm8OptLsl<int64_t>(MI, 3, STI, O); |
| return; |
| break; |
| case 39: |
| // CPY_ZPmI_S |
| printImm8OptLsl<int32_t>(MI, 3, STI, O); |
| return; |
| break; |
| case 40: |
| // CPY_ZPmR_B, CPY_ZPmR_D, CPY_ZPmR_S, CPY_ZPmV_B, CPY_ZPmV_D, CPY_ZPmV_S... |
| printOperand(MI, 3, STI, O); |
| break; |
| case 41: |
| // CPY_ZPzI_H |
| printImm8OptLsl<int16_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 42: |
| // CPYi16, DUPv4i16lane, DUPv8i16lane, INSvi16lane, SMOVvi16to32, SMOVvi1... |
| O << ".h"; |
| break; |
| case 43: |
| // CPYi32, DUPv2i32lane, DUPv4i32lane, INSvi32lane, SMOVvi32to64, UMOVvi3... |
| O << ".s"; |
| break; |
| case 44: |
| // CPYi64, DUPv2i64lane, FMOVDXHighr, INSvi64lane, UMOVvi64 |
| O << ".d"; |
| break; |
| case 45: |
| // CPYi8, DUPv16i8lane, DUPv8i8lane, INSvi8lane, SMOVvi8to32, SMOVvi8to64... |
| O << ".b"; |
| break; |
| case 46: |
| // DUP_ZZI_B, DUP_ZZI_D, DUP_ZZI_S |
| printVectorIndex(MI, 2, STI, O); |
| return; |
| break; |
| case 47: |
| // EXT_ZZI_B, UMAX_ZI_H, UMIN_ZI_H |
| printImm(MI, 2, STI, O); |
| return; |
| break; |
| case 48: |
| // FADDPv2i16p, FMAXNMPv2i16p, FMAXPv2i16p, FMINNMPv2i16p, FMINPv2i16p |
| O << ".2h"; |
| return; |
| break; |
| case 49: |
| // FCMEQv1i16rz, FCMEQv1i32rz, FCMEQv1i64rz, FCMGEv1i16rz, FCMGEv1i32rz, ... |
| O << ", #0.0"; |
| return; |
| break; |
| case 50: |
| // FCMEQv2i32rz, FCMGEv2i32rz, FCMGTv2i32rz, FCMLEv2i32rz, FCMLTv2i32rz |
| O << ".2s, #0.0"; |
| return; |
| break; |
| case 51: |
| // FCMEQv2i64rz, FCMGEv2i64rz, FCMGTv2i64rz, FCMLEv2i64rz, FCMLTv2i64rz |
| O << ".2d, #0.0"; |
| return; |
| break; |
| case 52: |
| // FCMEQv4i16rz, FCMGEv4i16rz, FCMGTv4i16rz, FCMLEv4i16rz, FCMLTv4i16rz |
| O << ".4h, #0.0"; |
| return; |
| break; |
| case 53: |
| // FCMEQv4i32rz, FCMGEv4i32rz, FCMGTv4i32rz, FCMLEv4i32rz, FCMLTv4i32rz |
| O << ".4s, #0.0"; |
| return; |
| break; |
| case 54: |
| // FCMEQv8i16rz, FCMGEv8i16rz, FCMGTv8i16rz, FCMLEv8i16rz, FCMLTv8i16rz |
| O << ".8h, #0.0"; |
| return; |
| break; |
| case 55: |
| // FCPY_ZPmI_D, FCPY_ZPmI_S |
| printFPImmOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 56: |
| // FMLAL2lanev4f16, FMLAL2v4f16, FMLALlanev4f16, FMLALv4f16, FMLSL2lanev4... |
| O << ".2h, "; |
| printVRegOperand(MI, 3, STI, O); |
| break; |
| case 57: |
| // LDAPRB, LDAPRH, LDAPRW, LDAPRX, LDARB, LDARH, LDARW, LDARX, LDAXRB, LD... |
| O << ']'; |
| return; |
| break; |
| case 58: |
| // LDRBBpost, LDRBpost, LDRDpost, LDRHHpost, LDRHpost, LDRQpost, LDRSBWpo... |
| O << "], "; |
| break; |
| case 59: |
| // MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl, MOVIv8i16, ... |
| printShifter(MI, 2, STI, O); |
| return; |
| break; |
| case 60: |
| // PMULLB_ZZZ_H, PMULLT_ZZZ_H, SABDLB_ZZZ_H, SABDLT_ZZZ_H, SADDLBT_ZZZ_H,... |
| printSVERegOp<'b'>(MI, 2, STI, O); |
| return; |
| break; |
| case 61: |
| // PRFB_D_SCALED |
| printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 62: |
| // PRFB_D_SXTW_SCALED |
| printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 63: |
| // PRFB_D_UXTW_SCALED |
| printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 64: |
| // PRFB_PRR |
| printRegWithShiftExtend<false, 8, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 65: |
| // PRFB_S_SXTW_SCALED |
| printRegWithShiftExtend<true, 8, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 66: |
| // PRFB_S_UXTW_SCALED |
| printRegWithShiftExtend<false, 8, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 67: |
| // PRFD_D_SCALED |
| printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 68: |
| // PRFD_D_SXTW_SCALED |
| printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 69: |
| // PRFD_D_UXTW_SCALED |
| printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 70: |
| // PRFD_PRR |
| printRegWithShiftExtend<false, 64, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 71: |
| // PRFD_S_PZI |
| printImmScale<8>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 72: |
| // PRFD_S_SXTW_SCALED |
| printRegWithShiftExtend<true, 64, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 73: |
| // PRFD_S_UXTW_SCALED |
| printRegWithShiftExtend<false, 64, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 74: |
| // PRFH_D_SCALED |
| printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 75: |
| // PRFH_D_SXTW_SCALED |
| printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 76: |
| // PRFH_D_UXTW_SCALED |
| printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 77: |
| // PRFH_PRR |
| printRegWithShiftExtend<false, 16, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 78: |
| // PRFH_S_PZI |
| printImmScale<2>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 79: |
| // PRFH_S_SXTW_SCALED |
| printRegWithShiftExtend<true, 16, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 80: |
| // PRFH_S_UXTW_SCALED |
| printRegWithShiftExtend<false, 16, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 81: |
| // PRFS_PRR |
| printRegWithShiftExtend<false, 32, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 82: |
| // PRFW_D_SCALED |
| printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 83: |
| // PRFW_D_SXTW_SCALED |
| printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 84: |
| // PRFW_D_UXTW_SCALED |
| printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 85: |
| // PRFW_S_PZI |
| printImmScale<4>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 86: |
| // PRFW_S_SXTW_SCALED |
| printRegWithShiftExtend<true, 32, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 87: |
| // PRFW_S_UXTW_SCALED |
| printRegWithShiftExtend<false, 32, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 88: |
| // RDFFRS_PPz, RDFFR_PPz |
| O << "/z"; |
| return; |
| break; |
| case 89: |
| // SHLLv16i8 |
| O << ".16b, #8"; |
| return; |
| break; |
| case 90: |
| // SHLLv2i32 |
| O << ".2s, #32"; |
| return; |
| break; |
| case 91: |
| // SHLLv4i16 |
| O << ".4h, #16"; |
| return; |
| break; |
| case 92: |
| // SHLLv4i32 |
| O << ".4s, #32"; |
| return; |
| break; |
| case 93: |
| // SHLLv8i16 |
| O << ".8h, #16"; |
| return; |
| break; |
| case 94: |
| // SHLLv8i8 |
| O << ".8b, #8"; |
| return; |
| break; |
| case 95: |
| // SPLICE_ZPZZ_H |
| printTypedVectorList<0,'h'>(MI, 2, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 4 encoded into 7 bits for 90 unique commands. |
| switch ((Bits >> 38) & 127) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ABS_ZPmZ_B, ADD_ZZZ_H, BDEP_ZZZ_H, BEXT_ZZZ_H, BGRP_ZZZ_H, BRKA_PPmP, ... |
| return; |
| break; |
| case 1: |
| // ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDHNT_ZZZ_S, CMLA_ZZZ_D, EORBT_ZZZ_D, EORTB... |
| printSVERegOp<'d'>(MI, 3, STI, O); |
| break; |
| case 2: |
| // ADCLB_ZZZ_S, ADCLT_ZZZ_S, CMLA_ZZZI_S, CMLA_ZZZ_S, EORBT_ZZZ_S, EORTB_... |
| printSVERegOp<'s'>(MI, 3, STI, O); |
| break; |
| case 3: |
| // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDSXrx64, ADDVL_XXI, ADDXrx6... |
| printOperand(MI, 2, STI, O); |
| break; |
| case 4: |
| // ADDG, ST2GOffset, STGOffset, STZ2GOffset, STZGOffset, SUBG |
| printImmScale<16>(MI, 2, STI, O); |
| break; |
| case 5: |
| // ADDHNB_ZZZ_B, ANDV_VPZ_H, CNTP_XPP_H, EORV_VPZ_H, FADDV_VPZ_H, FMAXNMV... |
| printSVERegOp<'h'>(MI, 2, STI, O); |
| break; |
| case 6: |
| // ADDHNB_ZZZ_S, ADDP_ZPmZ_D, ADD_ZPmZ_D, ADD_ZZZ_D, ANDV_VPZ_D, AND_ZPmZ... |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| break; |
| case 7: |
| // ADDHNT_ZZZ_B, CDOT_ZZZI_D, CDOT_ZZZ_D, FMLALB_ZZZI_SHH, FMLALB_ZZZ_SHH... |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| break; |
| case 8: |
| // ADDHNv2i64_v2i32, ADDHNv4i32_v4i16, ADDHNv8i16_v8i8, ADDPv16i8, ADDPv2... |
| printVRegOperand(MI, 2, STI, O); |
| break; |
| case 9: |
| // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, BITv16i8, BITv8i... |
| printVRegOperand(MI, 3, STI, O); |
| break; |
| case 10: |
| // ADDP_ZPmZ_B, ADD_ZPmZ_B, ADD_ZZZ_B, AESD_ZZZ_B, AESE_ZZZ_B, ANDS_PPzPP... |
| printSVERegOp<'b'>(MI, 2, STI, O); |
| break; |
| case 11: |
| // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID... |
| O << ", "; |
| break; |
| case 12: |
| // ADDP_ZPmZ_S, ADD_ZPmZ_S, ADD_ZZZ_S, ANDV_VPZ_S, AND_ZPmZ_S, ASRD_ZPmI_... |
| printSVERegOp<'s'>(MI, 2, STI, O); |
| break; |
| case 13: |
| // ADDSWri, ADDSXri, ADDWri, ADDXri, SUBSWri, SUBSXri, SUBWri, SUBXri |
| printAddSubImm(MI, 2, STI, O); |
| return; |
| break; |
| case 14: |
| // ADDSWrs, ADDSXrs, ADDWrs, ADDXrs, ANDSWrs, ANDSXrs, ANDWrs, ANDXrs, BI... |
| printShiftedRegister(MI, 2, STI, O); |
| return; |
| break; |
| case 15: |
| // ADDSWrx, ADDSXrx, ADDWrx, ADDXrx, SUBSWrx, SUBSXrx, SUBWrx, SUBXrx |
| printExtendedRegister(MI, 2, STI, O); |
| return; |
| break; |
| case 16: |
| // ADD_ZI_B, SQADD_ZI_B, SQSUB_ZI_B, SUBR_ZI_B, SUB_ZI_B, UQADD_ZI_B, UQS... |
| printImm8OptLsl<uint8_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 17: |
| // ADD_ZI_D, SQADD_ZI_D, SQSUB_ZI_D, SUBR_ZI_D, SUB_ZI_D, UQADD_ZI_D, UQS... |
| printImm8OptLsl<uint64_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 18: |
| // ADD_ZI_S, SQADD_ZI_S, SQSUB_ZI_S, SUBR_ZI_S, SUB_ZI_S, UQADD_ZI_S, UQS... |
| printImm8OptLsl<uint32_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 19: |
| // ADR_LSL_ZZZ_D_0 |
| printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 20: |
| // ADR_LSL_ZZZ_D_1 |
| printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 21: |
| // ADR_LSL_ZZZ_D_2 |
| printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 22: |
| // ADR_LSL_ZZZ_D_3 |
| printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 23: |
| // ADR_LSL_ZZZ_S_0 |
| printRegWithShiftExtend<false, 8, 'x', 's'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 24: |
| // ADR_LSL_ZZZ_S_1 |
| printRegWithShiftExtend<false, 16, 'x', 's'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 25: |
| // ADR_LSL_ZZZ_S_2 |
| printRegWithShiftExtend<false, 32, 'x', 's'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 26: |
| // ADR_LSL_ZZZ_S_3 |
| printRegWithShiftExtend<false, 64, 'x', 's'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 27: |
| // ADR_SXTW_ZZZ_D_0 |
| printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 28: |
| // ADR_SXTW_ZZZ_D_1 |
| printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 29: |
| // ADR_SXTW_ZZZ_D_2 |
| printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 30: |
| // ADR_SXTW_ZZZ_D_3 |
| printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 31: |
| // ADR_UXTW_ZZZ_D_0 |
| printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 32: |
| // ADR_UXTW_ZZZ_D_1 |
| printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 33: |
| // ADR_UXTW_ZZZ_D_2 |
| printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 34: |
| // ADR_UXTW_ZZZ_D_3 |
| printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 35: |
| // ANDSWri, ANDWri, EORWri, ORRWri |
| printLogicalImm<int32_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 36: |
| // ANDSXri, ANDXri, AND_ZI, EORXri, EOR_ZI, ORRXri, ORR_ZI |
| printLogicalImm<int64_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 37: |
| // BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, C... |
| printOperand(MI, 3, STI, O); |
| break; |
| case 38: |
| // CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, FMLA_ZZZI_H, FMLS_ZZZI_H, INSv... |
| printVectorIndex(MI, 4, STI, O); |
| break; |
| case 39: |
| // CPY_ZPzI_B |
| printImm8OptLsl<int8_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 40: |
| // CPY_ZPzI_D |
| printImm8OptLsl<int64_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 41: |
| // CPY_ZPzI_S |
| printImm8OptLsl<int32_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 42: |
| // CPYi16, CPYi32, CPYi64, CPYi8, DUPv16i8lane, DUPv2i32lane, DUPv2i64lan... |
| printVectorIndex(MI, 2, STI, O); |
| return; |
| break; |
| case 43: |
| // FCMEQ_PPzZ0_H, FCMGE_PPzZ0_H, FCMGT_PPzZ0_H, FCMLE_PPzZ0_H, FCMLT_PPzZ... |
| O << ", #0.0"; |
| return; |
| break; |
| case 44: |
| // FMLAL2lanev4f16, FMLALlanev4f16, FMLSL2lanev4f16, FMLSLlanev4f16 |
| O << ".h"; |
| printVectorIndex(MI, 4, STI, O); |
| return; |
| break; |
| case 45: |
| // FMLAL2v4f16, FMLALv4f16, FMLSL2v4f16, FMLSLv4f16 |
| O << ".2h"; |
| return; |
| break; |
| case 46: |
| // FMUL_ZZZI_H, MUL_ZZZI_H, SQDMULH_ZZZI_H, SQRDMULH_ZZZI_H |
| printVectorIndex(MI, 3, STI, O); |
| return; |
| break; |
| case 47: |
| // GLD1B_D_REAL, GLD1D_REAL, GLD1H_D_REAL, GLD1SB_D_REAL, GLD1SH_D_REAL, ... |
| printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 48: |
| // GLD1B_D_SXTW_REAL, GLD1D_SXTW_REAL, GLD1H_D_SXTW_REAL, GLD1SB_D_SXTW_R... |
| printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 49: |
| // GLD1B_D_UXTW_REAL, GLD1D_UXTW_REAL, GLD1H_D_UXTW_REAL, GLD1SB_D_UXTW_R... |
| printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 50: |
| // GLD1B_S_SXTW_REAL, GLD1H_S_SXTW_REAL, GLD1SB_S_SXTW_REAL, GLD1SH_S_SXT... |
| printRegWithShiftExtend<true, 8, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 51: |
| // GLD1B_S_UXTW_REAL, GLD1H_S_UXTW_REAL, GLD1SB_S_UXTW_REAL, GLD1SH_S_UXT... |
| printRegWithShiftExtend<false, 8, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 52: |
| // GLD1D_IMM_REAL, GLDFF1D_IMM_REAL, LD1RD_IMM, LDRAAwriteback, LDRABwrit... |
| printImmScale<8>(MI, 3, STI, O); |
| break; |
| case 53: |
| // GLD1D_SCALED_REAL, GLDFF1D_SCALED_REAL, SST1D_SCALED_SCALED_REAL |
| printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 54: |
| // GLD1D_SXTW_SCALED_REAL, GLDFF1D_SXTW_SCALED_REAL, SST1D_SXTW_SCALED |
| printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 55: |
| // GLD1D_UXTW_SCALED_REAL, GLDFF1D_UXTW_SCALED_REAL, SST1D_UXTW_SCALED |
| printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 56: |
| // GLD1H_D_IMM_REAL, GLD1H_S_IMM_REAL, GLD1SH_D_IMM_REAL, GLD1SH_S_IMM_RE... |
| printImmScale<2>(MI, 3, STI, O); |
| break; |
| case 57: |
| // GLD1H_D_SCALED_REAL, GLD1SH_D_SCALED_REAL, GLDFF1H_D_SCALED_REAL, GLDF... |
| printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 58: |
| // GLD1H_D_SXTW_SCALED_REAL, GLD1SH_D_SXTW_SCALED_REAL, GLDFF1H_D_SXTW_SC... |
| printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 59: |
| // GLD1H_D_UXTW_SCALED_REAL, GLD1SH_D_UXTW_SCALED_REAL, GLDFF1H_D_UXTW_SC... |
| printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 60: |
| // GLD1H_S_SXTW_SCALED_REAL, GLD1SH_S_SXTW_SCALED_REAL, GLDFF1H_S_SXTW_SC... |
| printRegWithShiftExtend<true, 16, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 61: |
| // GLD1H_S_UXTW_SCALED_REAL, GLD1SH_S_UXTW_SCALED_REAL, GLDFF1H_S_UXTW_SC... |
| printRegWithShiftExtend<false, 16, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 62: |
| // GLD1SW_D_IMM_REAL, GLD1W_D_IMM_REAL, GLD1W_IMM_REAL, GLDFF1SW_D_IMM_RE... |
| printImmScale<4>(MI, 3, STI, O); |
| break; |
| case 63: |
| // GLD1SW_D_SCALED_REAL, GLD1W_D_SCALED_REAL, GLDFF1SW_D_SCALED_REAL, GLD... |
| printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 64: |
| // GLD1SW_D_SXTW_SCALED_REAL, GLD1W_D_SXTW_SCALED_REAL, GLDFF1SW_D_SXTW_S... |
| printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 65: |
| // GLD1SW_D_UXTW_SCALED_REAL, GLD1W_D_UXTW_SCALED_REAL, GLDFF1SW_D_UXTW_S... |
| printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 66: |
| // GLD1W_SXTW_SCALED_REAL, GLDFF1W_SXTW_SCALED_REAL, SST1W_SXTW_SCALED |
| printRegWithShiftExtend<true, 32, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 67: |
| // GLD1W_UXTW_SCALED_REAL, GLDFF1W_UXTW_SCALED_REAL, SST1W_UXTW_SCALED |
| printRegWithShiftExtend<false, 32, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 68: |
| // LD1B, LD1B_D, LD1B_H, LD1B_S, LD1RQ_B, LD1SB_D, LD1SB_H, LD1SB_S, LD2B... |
| printRegWithShiftExtend<false, 8, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 69: |
| // LD1D, LD1RQ_D, LD2D, LD3D, LD4D, LDFF1D_REAL, LDNT1D_ZRR, ST1D, ST2D, ... |
| printRegWithShiftExtend<false, 64, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 70: |
| // LD1H, LD1H_D, LD1H_S, LD1RQ_H, LD1SH_D, LD1SH_S, LD2H, LD3H, LD4H, LDF... |
| printRegWithShiftExtend<false, 16, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 71: |
| // LD1RQ_B_IMM, LD1RQ_D_IMM, LD1RQ_H_IMM, LD1RQ_W_IMM, LDG, ST2GPostIndex... |
| printImmScale<16>(MI, 3, STI, O); |
| break; |
| case 72: |
| // LD1RQ_W, LD1SW_D, LD1W, LD1W_D, LD2W, LD3W, LD4W, LDFF1SW_D_REAL, LDFF... |
| printRegWithShiftExtend<false, 32, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 73: |
| // LD3B_IMM, LD3D_IMM, LD3H_IMM, LD3W_IMM, ST3B_IMM, ST3D_IMM, ST3H_IMM, ... |
| printImmScale<3>(MI, 3, STI, O); |
| O << ", mul vl]"; |
| return; |
| break; |
| case 74: |
| // LDRAAindexed, LDRABindexed |
| printImmScale<8>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 75: |
| // LDRBBui, LDRBui, LDRSBWui, LDRSBXui, STRBBui, STRBui |
| printUImm12Offset<1>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 76: |
| // LDRDui, LDRXui, PRFMui, STRDui, STRXui |
| printUImm12Offset<8>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 77: |
| // LDRHHui, LDRHui, LDRSHWui, LDRSHXui, STRHHui, STRHui |
| printUImm12Offset<2>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 78: |
| // LDRQui, STRQui |
| printUImm12Offset<16>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 79: |
| // LDRSWui, LDRSui, LDRWui, STRSui, STRWui |
| printUImm12Offset<4>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 80: |
| // MAD_ZPmZZ_B, MLA_ZPmZZ_B, MLS_ZPmZZ_B, MSB_ZPmZZ_B |
| printSVERegOp<'b'>(MI, 3, STI, O); |
| O << ", "; |
| printSVERegOp<'b'>(MI, 4, STI, O); |
| return; |
| break; |
| case 81: |
| // PRFB_PRI, PRFD_PRI, PRFH_PRI, PRFW_PRI |
| O << ", mul vl]"; |
| return; |
| break; |
| case 82: |
| // PRFB_S_PZI |
| O << ']'; |
| return; |
| break; |
| case 83: |
| // SPLICE_ZPZZ_B |
| printTypedVectorList<0,'b'>(MI, 2, STI, O); |
| return; |
| break; |
| case 84: |
| // SPLICE_ZPZZ_D |
| printTypedVectorList<0,'d'>(MI, 2, STI, O); |
| return; |
| break; |
| case 85: |
| // SPLICE_ZPZZ_S |
| printTypedVectorList<0,'s'>(MI, 2, STI, O); |
| return; |
| break; |
| case 86: |
| // SQDECP_XPWd_B, SQDECP_XPWd_D, SQDECP_XPWd_H, SQDECP_XPWd_S, SQINCP_XPW... |
| printGPR64as32(MI, 2, STI, O); |
| return; |
| break; |
| case 87: |
| // SYSLxt |
| printSysCROperand(MI, 2, STI, O); |
| O << ", "; |
| printSysCROperand(MI, 3, STI, O); |
| O << ", "; |
| printOperand(MI, 4, STI, O); |
| return; |
| break; |
| case 88: |
| // TBNZW, TBNZX, TBZW, TBZX |
| printAlignedLabel(MI, 2, STI, O); |
| return; |
| break; |
| case 89: |
| // UMAX_ZI_B, UMAX_ZI_D, UMAX_ZI_S, UMIN_ZI_B, UMIN_ZI_D, UMIN_ZI_S |
| printImm(MI, 2, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 5 encoded into 6 bits for 39 unique commands. |
| switch ((Bits >> 45) & 63) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ADCLB_ZZZ_D, ADCLB_ZZZ_S, ADCLT_ZZZ_D, ADCLT_ZZZ_S, ADCSWr, ADCSXr, AD... |
| return; |
| break; |
| case 1: |
| // ADDG, ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, A... |
| O << ", "; |
| break; |
| case 2: |
| // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... |
| O << ".2d"; |
| return; |
| break; |
| case 3: |
| // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... |
| O << ".4s"; |
| return; |
| break; |
| case 4: |
| // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, CMEQv8i16, CMG... |
| O << ".8h"; |
| return; |
| break; |
| case 5: |
| // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BIC_ZPmZ... |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| break; |
| case 6: |
| // ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,... |
| O << ".16b"; |
| return; |
| break; |
| case 7: |
| // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... |
| O << ".2s"; |
| return; |
| break; |
| case 8: |
| // ADDPv4i16, ADDv4i16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMHIv4i16, CMHSv... |
| O << ".4h"; |
| return; |
| break; |
| case 9: |
| // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... |
| O << ".8b"; |
| return; |
| break; |
| case 10: |
| // ADDSXrx64, ADDXrx64, SUBSXrx64, SUBXrx64 |
| printArithExtend(MI, 3, STI, O); |
| return; |
| break; |
| case 11: |
| // ASRD_ZPmI_H, ASR_ZPmI_H, CMPEQ_PPzZI_H, CMPGE_PPzZI_H, CMPGT_PPzZI_H, ... |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 12: |
| // ASR_WIDE_ZPmZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_WIDE_PPzZZ_H, CMPGT_WIDE_PP... |
| printSVERegOp<'d'>(MI, 3, STI, O); |
| return; |
| break; |
| case 13: |
| // BCAX, EOR3, EXTv16i8 |
| O << ".16b, "; |
| break; |
| case 14: |
| // CADD_ZZI_H, SQCADD_ZZI_H |
| printComplexRotationOp<180, 90>(MI, 3, STI, O); |
| return; |
| break; |
| case 15: |
| // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... |
| O << ']'; |
| return; |
| break; |
| case 16: |
| // CDOT_ZZZI_D, CMLA_ZZZI_S, FCMLA_ZZZI_S, FMLALB_ZZZI_SHH, FMLALT_ZZZI_S... |
| printVectorIndex(MI, 4, STI, O); |
| break; |
| case 17: |
| // CDOT_ZZZ_S, CMLA_ZZZ_B, CMLA_ZZZ_H, SQRDCMLAH_ZZZ_B, SQRDCMLAH_ZZZ_H |
| printComplexRotationOp<90, 0>(MI, 4, STI, O); |
| return; |
| break; |
| case 18: |
| // CMPHI_PPzZI_H, CMPHS_PPzZI_H, CMPLO_PPzZI_H, CMPLS_PPzZI_H |
| printImm(MI, 3, STI, O); |
| return; |
| break; |
| case 19: |
| // EXTv8i8 |
| O << ".8b, "; |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 20: |
| // FADD_ZPmI_H, FSUBR_ZPmI_H, FSUB_ZPmI_H |
| printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::one>(MI, 3, STI, O); |
| return; |
| break; |
| case 21: |
| // FCADDv2f32, FCMLAv2f32 |
| O << ".2s, "; |
| break; |
| case 22: |
| // FCADDv2f64, FCMLAv2f64, XAR |
| O << ".2d, "; |
| break; |
| case 23: |
| // FCADDv4f16, FCMLAv4f16 |
| O << ".4h, "; |
| break; |
| case 24: |
| // FCADDv4f32, FCMLAv4f32, SM3SS1 |
| O << ".4s, "; |
| break; |
| case 25: |
| // FCADDv8f16, FCMLAv8f16 |
| O << ".8h, "; |
| break; |
| case 26: |
| // FCMEQ_PPzZ0_D, FCMEQ_PPzZ0_S, FCMGE_PPzZ0_D, FCMGE_PPzZ0_S, FCMGT_PPzZ... |
| O << ", #0.0"; |
| return; |
| break; |
| case 27: |
| // FCMLA_ZPmZZ_H, FMAD_ZPmZZ_H, FMLA_ZPmZZ_H, FMLS_ZPmZZ_H, FMSB_ZPmZZ_H,... |
| printSVERegOp<'h'>(MI, 4, STI, O); |
| break; |
| case 28: |
| // FCMLAv4f16_indexed, FCMLAv8f16_indexed, FMLAL2lanev8f16, FMLALlanev8f1... |
| O << ".h"; |
| break; |
| case 29: |
| // FCMLAv4f32_indexed, FMLAv1i32_indexed, FMLAv2i32_indexed, FMLAv4i32_in... |
| O << ".s"; |
| break; |
| case 30: |
| // FMAXNM_ZPmI_H, FMAX_ZPmI_H, FMINNM_ZPmI_H, FMIN_ZPmI_H |
| printExactFPImm<AArch64ExactFPImm::zero, AArch64ExactFPImm::one>(MI, 3, STI, O); |
| return; |
| break; |
| case 31: |
| // FMLAv1i64_indexed, FMLAv2i64_indexed, FMLSv1i64_indexed, FMLSv2i64_ind... |
| O << ".d"; |
| break; |
| case 32: |
| // FMUL_ZPmI_H |
| printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::two>(MI, 3, STI, O); |
| return; |
| break; |
| case 33: |
| // FMUL_ZZZI_D, FMUL_ZZZI_S, MUL_ZZZI_D, MUL_ZZZI_S, SMULLB_ZZZI_D, SMULL... |
| printVectorIndex(MI, 3, STI, O); |
| return; |
| break; |
| case 34: |
| // LD1B_D_IMM, LD1B_H_IMM, LD1B_IMM, LD1B_S_IMM, LD1D_IMM, LD1H_D_IMM, LD... |
| O << ", mul vl]"; |
| return; |
| break; |
| case 35: |
| // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STGPpost,... |
| O << "], "; |
| break; |
| case 36: |
| // LDRAAwriteback, LDRABwriteback, LDRBBpre, LDRBpre, LDRDpre, LDRHHpre, ... |
| O << "]!"; |
| return; |
| break; |
| case 37: |
| // SDOTlanev16i8, SDOTlanev8i8, UDOTlanev16i8, UDOTlanev8i8 |
| O << ".4b"; |
| printVectorIndex(MI, 4, STI, O); |
| return; |
| break; |
| case 38: |
| // STLXPW, STLXPX, STXPW, STXPX |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| } |
| |
| |
| // Fragment 6 encoded into 6 bits for 37 unique commands. |
| switch ((Bits >> 51) & 63) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ADDG, ASRD_ZPmI_B, ASRD_ZPmI_D, ASRD_ZPmI_S, ASR_ZPmI_B, ASR_ZPmI_D, A... |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 1: |
| // ADDP_ZPmZ_B, ADD_ZPmZ_B, ANDS_PPzPP, AND_PPzPP, AND_ZPmZ_B, ASRR_ZPmZ_... |
| printSVERegOp<'b'>(MI, 3, STI, O); |
| return; |
| break; |
| case 2: |
| // ADDP_ZPmZ_D, ADD_ZPmZ_D, AND_ZPmZ_D, ASRR_ZPmZ_D, ASR_WIDE_ZPmZ_B, ASR... |
| printSVERegOp<'d'>(MI, 3, STI, O); |
| break; |
| case 3: |
| // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BIC_ZPmZ... |
| return; |
| break; |
| case 4: |
| // ADDP_ZPmZ_S, ADD_ZPmZ_S, AND_ZPmZ_S, ASRR_ZPmZ_S, ASR_ZPmZ_S, BIC_ZPmZ... |
| printSVERegOp<'s'>(MI, 3, STI, O); |
| break; |
| case 5: |
| // BCAX, EOR3, SM3SS1 |
| printVRegOperand(MI, 3, STI, O); |
| break; |
| case 6: |
| // BFMWri, BFMXri |
| printOperand(MI, 4, STI, O); |
| return; |
| break; |
| case 7: |
| // CADD_ZZI_B, CADD_ZZI_D, CADD_ZZI_S, FCADDv2f32, FCADDv2f64, FCADDv4f16... |
| printComplexRotationOp<180, 90>(MI, 3, STI, O); |
| return; |
| break; |
| case 8: |
| // CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi, CCMPXr, CSELWr... |
| printCondCode(MI, 3, STI, O); |
| return; |
| break; |
| case 9: |
| // CDOT_ZZZI_D, CMLA_ZZZI_S, FCADD_ZPmZ_H, FCMLA_ZPmZZ_H, FCMLA_ZZZI_S, S... |
| O << ", "; |
| break; |
| case 10: |
| // CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, SQRDCMLAH_ZZZI_H |
| printComplexRotationOp<90, 0>(MI, 5, STI, O); |
| return; |
| break; |
| case 11: |
| // CDOT_ZZZ_D, CMLA_ZZZ_D, CMLA_ZZZ_S, FCMLAv2f32, FCMLAv2f64, FCMLAv4f16... |
| printComplexRotationOp<90, 0>(MI, 4, STI, O); |
| return; |
| break; |
| case 12: |
| // CLASTA_RPZ_H, CLASTA_VPZ_H, CLASTB_RPZ_H, CLASTB_VPZ_H, FADDA_VPZ_H |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| return; |
| break; |
| case 13: |
| // CMPHI_PPzZI_B, CMPHI_PPzZI_D, CMPHI_PPzZI_S, CMPHS_PPzZI_B, CMPHS_PPzZ... |
| printImm(MI, 3, STI, O); |
| return; |
| break; |
| case 14: |
| // FADD_ZPmI_D, FADD_ZPmI_S, FSUBR_ZPmI_D, FSUBR_ZPmI_S, FSUB_ZPmI_D, FSU... |
| printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::one>(MI, 3, STI, O); |
| return; |
| break; |
| case 15: |
| // FCMLA_ZPmZZ_D, FMAD_ZPmZZ_D, FMLA_ZPmZZ_D, FMLS_ZPmZZ_D, FMSB_ZPmZZ_D,... |
| printSVERegOp<'d'>(MI, 4, STI, O); |
| break; |
| case 16: |
| // FCMLA_ZPmZZ_S, FMAD_ZPmZZ_S, FMLA_ZPmZZ_S, FMLS_ZPmZZ_S, FMSB_ZPmZZ_S,... |
| printSVERegOp<'s'>(MI, 4, STI, O); |
| break; |
| case 17: |
| // FCMLAv4f16_indexed, FCMLAv4f32_indexed, FCMLAv8f16_indexed, FMLAL2lane... |
| printVectorIndex(MI, 4, STI, O); |
| break; |
| case 18: |
| // FMAXNM_ZPmI_D, FMAXNM_ZPmI_S, FMAX_ZPmI_D, FMAX_ZPmI_S, FMINNM_ZPmI_D,... |
| printExactFPImm<AArch64ExactFPImm::zero, AArch64ExactFPImm::one>(MI, 3, STI, O); |
| return; |
| break; |
| case 19: |
| // FMULXv1i16_indexed, FMULXv1i32_indexed, FMULXv1i64_indexed, FMULXv2i32... |
| printVectorIndex(MI, 3, STI, O); |
| return; |
| break; |
| case 20: |
| // FMUL_ZPmI_D, FMUL_ZPmI_S |
| printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::two>(MI, 3, STI, O); |
| return; |
| break; |
| case 21: |
| // LDNPDi, LDNPXi, LDPDi, LDPXi, STNPDi, STNPXi, STPDi, STPXi |
| printImmScale<8>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 22: |
| // LDNPQi, LDPQi, STGPi, STNPQi, STPQi |
| printImmScale<16>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 23: |
| // LDNPSi, LDNPWi, LDPSWi, LDPSi, LDPWi, STNPSi, STNPWi, STPSi, STPWi |
| printImmScale<4>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 24: |
| // LDPDpost, LDPDpre, LDPXpost, LDPXpre, STPDpost, STPDpre, STPXpost, STP... |
| printImmScale<8>(MI, 4, STI, O); |
| break; |
| case 25: |
| // LDPQpost, LDPQpre, STGPpost, STGPpre, STPQpost, STPQpre |
| printImmScale<16>(MI, 4, STI, O); |
| break; |
| case 26: |
| // LDPSWpost, LDPSWpre, LDPSpost, LDPSpre, LDPWpost, LDPWpre, STPSpost, S... |
| printImmScale<4>(MI, 4, STI, O); |
| break; |
| case 27: |
| // LDRBBroW, LDRBroW, LDRSBWroW, LDRSBXroW, STRBBroW, STRBroW |
| printMemExtend<'w', 8>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 28: |
| // LDRBBroX, LDRBroX, LDRSBWroX, LDRSBXroX, STRBBroX, STRBroX |
| printMemExtend<'x', 8>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 29: |
| // LDRDroW, LDRXroW, PRFMroW, STRDroW, STRXroW |
| printMemExtend<'w', 64>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 30: |
| // LDRDroX, LDRXroX, PRFMroX, STRDroX, STRXroX |
| printMemExtend<'x', 64>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 31: |
| // LDRHHroW, LDRHroW, LDRSHWroW, LDRSHXroW, STRHHroW, STRHroW |
| printMemExtend<'w', 16>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 32: |
| // LDRHHroX, LDRHroX, LDRSHWroX, LDRSHXroX, STRHHroX, STRHroX |
| printMemExtend<'x', 16>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 33: |
| // LDRQroW, STRQroW |
| printMemExtend<'w', 128>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 34: |
| // LDRQroX, STRQroX |
| printMemExtend<'x', 128>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 35: |
| // LDRSWroW, LDRSroW, LDRWroW, STRSroW, STRWroW |
| printMemExtend<'w', 32>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 36: |
| // LDRSWroX, LDRSroX, LDRWroX, STRSroX, STRWroX |
| printMemExtend<'x', 32>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| } |
| |
| |
| // Fragment 7 encoded into 3 bits for 7 unique commands. |
| switch ((Bits >> 57) & 7) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_D, ADD_ZPmZ_S, AND_ZPmZ_D, AND_ZPmZ... |
| return; |
| break; |
| case 1: |
| // BCAX, EOR3 |
| O << ".16b"; |
| return; |
| break; |
| case 2: |
| // CDOT_ZZZI_D, CMLA_ZZZI_S, FCMLA_ZPmZZ_H, FCMLA_ZZZI_S, SQRDCMLAH_ZZZI_... |
| printComplexRotationOp<90, 0>(MI, 5, STI, O); |
| return; |
| break; |
| case 3: |
| // FCADD_ZPmZ_D, FCADD_ZPmZ_S, FCMLA_ZPmZZ_D, FCMLA_ZPmZZ_S, FCMLAv4f16_i... |
| O << ", "; |
| break; |
| case 4: |
| // FCADD_ZPmZ_H |
| printComplexRotationOp<180, 90>(MI, 4, STI, O); |
| return; |
| break; |
| case 5: |
| // LDPDpre, LDPQpre, LDPSWpre, LDPSpre, LDPWpre, LDPXpre, STGPpre, STPDpr... |
| O << "]!"; |
| return; |
| break; |
| case 6: |
| // SM3SS1 |
| O << ".4s"; |
| return; |
| break; |
| } |
| |
| |
| // Fragment 8 encoded into 1 bits for 2 unique commands. |
| if ((Bits >> 60) & 1) { |
| // FCMLA_ZPmZZ_D, FCMLA_ZPmZZ_S, FCMLAv4f16_indexed, FCMLAv4f32_indexed, ... |
| printComplexRotationOp<90, 0>(MI, 5, STI, O); |
| return; |
| } else { |
| // FCADD_ZPmZ_D, FCADD_ZPmZ_S |
| printComplexRotationOp<180, 90>(MI, 4, STI, O); |
| return; |
| } |
| |
| } |
| |
| |
| /// getRegisterName - This method is automatically generated by tblgen |
| /// from the register set description. This returns the assembler name |
| /// for the specified register. |
| const char *AArch64InstPrinter:: |
| getRegisterName(unsigned RegNo, unsigned AltIdx) { |
| assert(RegNo && RegNo < 629 && "Invalid register number!"); |
| |
| static const char AsmStrsNoRegAltName[] = { |
| /* 0 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0, |
| /* 13 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0, |
| /* 26 */ 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', 0, |
| /* 39 */ 'b', '1', '0', 0, |
| /* 43 */ 'd', '1', '0', 0, |
| /* 47 */ 'h', '1', '0', 0, |
| /* 51 */ 'p', '1', '0', 0, |
| /* 55 */ 'q', '1', '0', 0, |
| /* 59 */ 's', '1', '0', 0, |
| /* 63 */ 'w', '1', '0', 0, |
| /* 67 */ 'x', '1', '0', 0, |
| /* 71 */ 'z', '1', '0', 0, |
| /* 75 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0, |
| /* 91 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0, |
| /* 107 */ 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', 0, |
| /* 123 */ 'b', '2', '0', 0, |
| /* 127 */ 'd', '2', '0', 0, |
| /* 131 */ 'h', '2', '0', 0, |
| /* 135 */ 'q', '2', '0', 0, |
| /* 139 */ 's', '2', '0', 0, |
| /* 143 */ 'w', '2', '0', 0, |
| /* 147 */ 'x', '2', '0', 0, |
| /* 151 */ 'z', '2', '0', 0, |
| /* 155 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0, |
| /* 171 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0, |
| /* 187 */ 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', 0, |
| /* 203 */ 'b', '3', '0', 0, |
| /* 207 */ 'd', '3', '0', 0, |
| /* 211 */ 'h', '3', '0', 0, |
| /* 215 */ 'q', '3', '0', 0, |
| /* 219 */ 's', '3', '0', 0, |
| /* 223 */ 'w', '3', '0', 0, |
| /* 227 */ 'x', '3', '0', 0, |
| /* 231 */ 'z', '3', '0', 0, |
| /* 235 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0, |
| /* 250 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0, |
| /* 265 */ 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', 0, |
| /* 280 */ 'b', '0', 0, |
| /* 283 */ 'd', '0', 0, |
| /* 286 */ 'h', '0', 0, |
| /* 289 */ 'p', '0', 0, |
| /* 292 */ 'q', '0', 0, |
| /* 295 */ 's', '0', 0, |
| /* 298 */ 'w', '0', 0, |
| /* 301 */ 'x', '0', 0, |
| /* 304 */ 'z', '0', 0, |
| /* 307 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0, |
| /* 321 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0, |
| /* 335 */ 'W', '1', '0', '_', 'W', '1', '1', 0, |
| /* 343 */ 'X', '1', '0', '_', 'X', '1', '1', 0, |
| /* 351 */ 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', 0, |
| /* 365 */ 'b', '1', '1', 0, |
| /* 369 */ 'd', '1', '1', 0, |
| /* 373 */ 'h', '1', '1', 0, |
| /* 377 */ 'p', '1', '1', 0, |
| /* 381 */ 'q', '1', '1', 0, |
| /* 385 */ 's', '1', '1', 0, |
| /* 389 */ 'w', '1', '1', 0, |
| /* 393 */ 'x', '1', '1', 0, |
| /* 397 */ 'z', '1', '1', 0, |
| /* 401 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0, |
| /* 417 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0, |
| /* 433 */ 'W', '2', '0', '_', 'W', '2', '1', 0, |
| /* 441 */ 'X', '2', '0', '_', 'X', '2', '1', 0, |
| /* 449 */ 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', 0, |
| /* 465 */ 'b', '2', '1', 0, |
| /* 469 */ 'd', '2', '1', 0, |
| /* 473 */ 'h', '2', '1', 0, |
| /* 477 */ 'q', '2', '1', 0, |
| /* 481 */ 's', '2', '1', 0, |
| /* 485 */ 'w', '2', '1', 0, |
| /* 489 */ 'x', '2', '1', 0, |
| /* 493 */ 'z', '2', '1', 0, |
| /* 497 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0, |
| /* 513 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0, |
| /* 529 */ 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', 0, |
| /* 545 */ 'b', '3', '1', 0, |
| /* 549 */ 'd', '3', '1', 0, |
| /* 553 */ 'h', '3', '1', 0, |
| /* 557 */ 'q', '3', '1', 0, |
| /* 561 */ 's', '3', '1', 0, |
| /* 565 */ 'z', '3', '1', 0, |
| /* 569 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0, |
| /* 583 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0, |
| /* 597 */ 'W', '0', '_', 'W', '1', 0, |
| /* 603 */ 'X', '0', '_', 'X', '1', 0, |
| /* 609 */ 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', 0, |
| /* 623 */ 'b', '1', 0, |
| /* 626 */ 'd', '1', 0, |
| /* 629 */ 'h', '1', 0, |
| /* 632 */ 'p', '1', 0, |
| /* 635 */ 'q', '1', 0, |
| /* 638 */ 's', '1', 0, |
| /* 641 */ 'w', '1', 0, |
| /* 644 */ 'x', '1', 0, |
| /* 647 */ 'z', '1', 0, |
| /* 650 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0, |
| /* 665 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0, |
| /* 680 */ 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', 0, |
| /* 695 */ 'b', '1', '2', 0, |
| /* 699 */ 'd', '1', '2', 0, |
| /* 703 */ 'h', '1', '2', 0, |
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| /* 711 */ 'q', '1', '2', 0, |
| /* 715 */ 's', '1', '2', 0, |
| /* 719 */ 'w', '1', '2', 0, |
| /* 723 */ 'x', '1', '2', 0, |
| /* 727 */ 'z', '1', '2', 0, |
| /* 731 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0, |
| /* 747 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0, |
| /* 763 */ 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', 0, |
| /* 779 */ 'b', '2', '2', 0, |
| /* 783 */ 'd', '2', '2', 0, |
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| /* 807 */ 'z', '2', '2', 0, |
| /* 811 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0, |
| /* 824 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0, |
| /* 837 */ 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', 0, |
| /* 850 */ 'b', '2', 0, |
| /* 853 */ 'd', '2', 0, |
| /* 856 */ 'h', '2', 0, |
| /* 859 */ 'p', '2', 0, |
| /* 862 */ 'q', '2', 0, |
| /* 865 */ 's', '2', 0, |
| /* 868 */ 'w', '2', 0, |
| /* 871 */ 'x', '2', 0, |
| /* 874 */ 'z', '2', 0, |
| /* 877 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0, |
| /* 893 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0, |
| /* 909 */ 'W', '1', '2', '_', 'W', '1', '3', 0, |
| /* 917 */ 'X', '1', '2', '_', 'X', '1', '3', 0, |
| /* 925 */ 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', 0, |
| /* 941 */ 'b', '1', '3', 0, |
| /* 945 */ 'd', '1', '3', 0, |
| /* 949 */ 'h', '1', '3', 0, |
| /* 953 */ 'p', '1', '3', 0, |
| /* 957 */ 'q', '1', '3', 0, |
| /* 961 */ 's', '1', '3', 0, |
| /* 965 */ 'w', '1', '3', 0, |
| /* 969 */ 'x', '1', '3', 0, |
| /* 973 */ 'z', '1', '3', 0, |
| /* 977 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0, |
| /* 993 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0, |
| /* 1009 */ 'W', '2', '2', '_', 'W', '2', '3', 0, |
| /* 1017 */ 'X', '2', '2', '_', 'X', '2', '3', 0, |
| /* 1025 */ 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', 0, |
| /* 1041 */ 'b', '2', '3', 0, |
| /* 1045 */ 'd', '2', '3', 0, |
| /* 1049 */ 'h', '2', '3', 0, |
| /* 1053 */ 'q', '2', '3', 0, |
| /* 1057 */ 's', '2', '3', 0, |
| /* 1061 */ 'w', '2', '3', 0, |
| /* 1065 */ 'x', '2', '3', 0, |
| /* 1069 */ 'z', '2', '3', 0, |
| /* 1073 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0, |
| /* 1085 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0, |
| /* 1097 */ 'W', '2', '_', 'W', '3', 0, |
| /* 1103 */ 'X', '2', '_', 'X', '3', 0, |
| /* 1109 */ 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', 0, |
| /* 1121 */ 'b', '3', 0, |
| /* 1124 */ 'd', '3', 0, |
| /* 1127 */ 'h', '3', 0, |
| /* 1130 */ 'p', '3', 0, |
| /* 1133 */ 'q', '3', 0, |
| /* 1136 */ 's', '3', 0, |
| /* 1139 */ 'w', '3', 0, |
| /* 1142 */ 'x', '3', 0, |
| /* 1145 */ 'z', '3', 0, |
| /* 1148 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0, |
| /* 1164 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0, |
| /* 1180 */ 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', 0, |
| /* 1196 */ 'b', '1', '4', 0, |
| /* 1200 */ 'd', '1', '4', 0, |
| /* 1204 */ 'h', '1', '4', 0, |
| /* 1208 */ 'p', '1', '4', 0, |
| /* 1212 */ 'q', '1', '4', 0, |
| /* 1216 */ 's', '1', '4', 0, |
| /* 1220 */ 'w', '1', '4', 0, |
| /* 1224 */ 'x', '1', '4', 0, |
| /* 1228 */ 'z', '1', '4', 0, |
| /* 1232 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0, |
| /* 1248 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0, |
| /* 1264 */ 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', 0, |
| /* 1280 */ 'b', '2', '4', 0, |
| /* 1284 */ 'd', '2', '4', 0, |
| /* 1288 */ 'h', '2', '4', 0, |
| /* 1292 */ 'q', '2', '4', 0, |
| /* 1296 */ 's', '2', '4', 0, |
| /* 1300 */ 'w', '2', '4', 0, |
| /* 1304 */ 'x', '2', '4', 0, |
| /* 1308 */ 'z', '2', '4', 0, |
| /* 1312 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0, |
| /* 1324 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0, |
| /* 1336 */ 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', 0, |
| /* 1348 */ 'b', '4', 0, |
| /* 1351 */ 'd', '4', 0, |
| /* 1354 */ 'h', '4', 0, |
| /* 1357 */ 'p', '4', 0, |
| /* 1360 */ 'q', '4', 0, |
| /* 1363 */ 's', '4', 0, |
| /* 1366 */ 'w', '4', 0, |
| /* 1369 */ 'x', '4', 0, |
| /* 1372 */ 'z', '4', 0, |
| /* 1375 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0, |
| /* 1391 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0, |
| /* 1407 */ 'W', '1', '4', '_', 'W', '1', '5', 0, |
| /* 1415 */ 'X', '1', '4', '_', 'X', '1', '5', 0, |
| /* 1423 */ 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', 0, |
| /* 1439 */ 'b', '1', '5', 0, |
| /* 1443 */ 'd', '1', '5', 0, |
| /* 1447 */ 'h', '1', '5', 0, |
| /* 1451 */ 'p', '1', '5', 0, |
| /* 1455 */ 'q', '1', '5', 0, |
| /* 1459 */ 's', '1', '5', 0, |
| /* 1463 */ 'w', '1', '5', 0, |
| /* 1467 */ 'x', '1', '5', 0, |
| /* 1471 */ 'z', '1', '5', 0, |
| /* 1475 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0, |
| /* 1491 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0, |
| /* 1507 */ 'W', '2', '4', '_', 'W', '2', '5', 0, |
| /* 1515 */ 'X', '2', '4', '_', 'X', '2', '5', 0, |
| /* 1523 */ 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', 0, |
| /* 1539 */ 'b', '2', '5', 0, |
| /* 1543 */ 'd', '2', '5', 0, |
| /* 1547 */ 'h', '2', '5', 0, |
| /* 1551 */ 'q', '2', '5', 0, |
| /* 1555 */ 's', '2', '5', 0, |
| /* 1559 */ 'w', '2', '5', 0, |
| /* 1563 */ 'x', '2', '5', 0, |
| /* 1567 */ 'z', '2', '5', 0, |
| /* 1571 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0, |
| /* 1583 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0, |
| /* 1595 */ 'W', '4', '_', 'W', '5', 0, |
| /* 1601 */ 'X', '4', '_', 'X', '5', 0, |
| /* 1607 */ 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', 0, |
| /* 1619 */ 'b', '5', 0, |
| /* 1622 */ 'd', '5', 0, |
| /* 1625 */ 'h', '5', 0, |
| /* 1628 */ 'p', '5', 0, |
| /* 1631 */ 'q', '5', 0, |
| /* 1634 */ 's', '5', 0, |
| /* 1637 */ 'w', '5', 0, |
| /* 1640 */ 'x', '5', 0, |
| /* 1643 */ 'z', '5', 0, |
| /* 1646 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0, |
| /* 1662 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0, |
| /* 1678 */ 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', 0, |
| /* 1694 */ 'b', '1', '6', 0, |
| /* 1698 */ 'd', '1', '6', 0, |
| /* 1702 */ 'h', '1', '6', 0, |
| /* 1706 */ 'q', '1', '6', 0, |
| /* 1710 */ 's', '1', '6', 0, |
| /* 1714 */ 'w', '1', '6', 0, |
| /* 1718 */ 'x', '1', '6', 0, |
| /* 1722 */ 'z', '1', '6', 0, |
| /* 1726 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0, |
| /* 1742 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0, |
| /* 1758 */ 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', 0, |
| /* 1774 */ 'b', '2', '6', 0, |
| /* 1778 */ 'd', '2', '6', 0, |
| /* 1782 */ 'h', '2', '6', 0, |
| /* 1786 */ 'q', '2', '6', 0, |
| /* 1790 */ 's', '2', '6', 0, |
| /* 1794 */ 'w', '2', '6', 0, |
| /* 1798 */ 'x', '2', '6', 0, |
| /* 1802 */ 'z', '2', '6', 0, |
| /* 1806 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0, |
| /* 1818 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0, |
| /* 1830 */ 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', 0, |
| /* 1842 */ 'b', '6', 0, |
| /* 1845 */ 'd', '6', 0, |
| /* 1848 */ 'h', '6', 0, |
| /* 1851 */ 'p', '6', 0, |
| /* 1854 */ 'q', '6', 0, |
| /* 1857 */ 's', '6', 0, |
| /* 1860 */ 'w', '6', 0, |
| /* 1863 */ 'x', '6', 0, |
| /* 1866 */ 'z', '6', 0, |
| /* 1869 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0, |
| /* 1885 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0, |
| /* 1901 */ 'W', '1', '6', '_', 'W', '1', '7', 0, |
| /* 1909 */ 'X', '1', '6', '_', 'X', '1', '7', 0, |
| /* 1917 */ 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', 0, |
| /* 1933 */ 'b', '1', '7', 0, |
| /* 1937 */ 'd', '1', '7', 0, |
| /* 1941 */ 'h', '1', '7', 0, |
| /* 1945 */ 'q', '1', '7', 0, |
| /* 1949 */ 's', '1', '7', 0, |
| /* 1953 */ 'w', '1', '7', 0, |
| /* 1957 */ 'x', '1', '7', 0, |
| /* 1961 */ 'z', '1', '7', 0, |
| /* 1965 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0, |
| /* 1981 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0, |
| /* 1997 */ 'W', '2', '6', '_', 'W', '2', '7', 0, |
| /* 2005 */ 'X', '2', '6', '_', 'X', '2', '7', 0, |
| /* 2013 */ 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', 0, |
| /* 2029 */ 'b', '2', '7', 0, |
| /* 2033 */ 'd', '2', '7', 0, |
| /* 2037 */ 'h', '2', '7', 0, |
| /* 2041 */ 'q', '2', '7', 0, |
| /* 2045 */ 's', '2', '7', 0, |
| /* 2049 */ 'w', '2', '7', 0, |
| /* 2053 */ 'x', '2', '7', 0, |
| /* 2057 */ 'z', '2', '7', 0, |
| /* 2061 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0, |
| /* 2073 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0, |
| /* 2085 */ 'W', '6', '_', 'W', '7', 0, |
| /* 2091 */ 'X', '6', '_', 'X', '7', 0, |
| /* 2097 */ 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', 0, |
| /* 2109 */ 'b', '7', 0, |
| /* 2112 */ 'd', '7', 0, |
| /* 2115 */ 'h', '7', 0, |
| /* 2118 */ 'p', '7', 0, |
| /* 2121 */ 'q', '7', 0, |
| /* 2124 */ 's', '7', 0, |
| /* 2127 */ 'w', '7', 0, |
| /* 2130 */ 'x', '7', 0, |
| /* 2133 */ 'z', '7', 0, |
| /* 2136 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0, |
| /* 2152 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0, |
| /* 2168 */ 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', 0, |
| /* 2184 */ 'b', '1', '8', 0, |
| /* 2188 */ 'd', '1', '8', 0, |
| /* 2192 */ 'h', '1', '8', 0, |
| /* 2196 */ 'q', '1', '8', 0, |
| /* 2200 */ 's', '1', '8', 0, |
| /* 2204 */ 'w', '1', '8', 0, |
| /* 2208 */ 'x', '1', '8', 0, |
| /* 2212 */ 'z', '1', '8', 0, |
| /* 2216 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0, |
| /* 2232 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0, |
| /* 2248 */ 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', 0, |
| /* 2264 */ 'b', '2', '8', 0, |
| /* 2268 */ 'd', '2', '8', 0, |
| /* 2272 */ 'h', '2', '8', 0, |
| /* 2276 */ 'q', '2', '8', 0, |
| /* 2280 */ 's', '2', '8', 0, |
| /* 2284 */ 'w', '2', '8', 0, |
| /* 2288 */ 'x', '2', '8', 0, |
| /* 2292 */ 'z', '2', '8', 0, |
| /* 2296 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0, |
| /* 2308 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0, |
| /* 2320 */ 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', 0, |
| /* 2332 */ 'b', '8', 0, |
| /* 2335 */ 'd', '8', 0, |
| /* 2338 */ 'h', '8', 0, |
| /* 2341 */ 'p', '8', 0, |
| /* 2344 */ 'q', '8', 0, |
| /* 2347 */ 's', '8', 0, |
| /* 2350 */ 'w', '8', 0, |
| /* 2353 */ 'x', '8', 0, |
| /* 2356 */ 'z', '8', 0, |
| /* 2359 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0, |
| /* 2375 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0, |
| /* 2391 */ 'W', '1', '8', '_', 'W', '1', '9', 0, |
| /* 2399 */ 'X', '1', '8', '_', 'X', '1', '9', 0, |
| /* 2407 */ 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', 0, |
| /* 2423 */ 'b', '1', '9', 0, |
| /* 2427 */ 'd', '1', '9', 0, |
| /* 2431 */ 'h', '1', '9', 0, |
| /* 2435 */ 'q', '1', '9', 0, |
| /* 2439 */ 's', '1', '9', 0, |
| /* 2443 */ 'w', '1', '9', 0, |
| /* 2447 */ 'x', '1', '9', 0, |
| /* 2451 */ 'z', '1', '9', 0, |
| /* 2455 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0, |
| /* 2471 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0, |
| /* 2487 */ 'W', '2', '8', '_', 'W', '2', '9', 0, |
| /* 2495 */ 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', 0, |
| /* 2511 */ 'b', '2', '9', 0, |
| /* 2515 */ 'd', '2', '9', 0, |
| /* 2519 */ 'h', '2', '9', 0, |
| /* 2523 */ 'q', '2', '9', 0, |
| /* 2527 */ 's', '2', '9', 0, |
| /* 2531 */ 'w', '2', '9', 0, |
| /* 2535 */ 'x', '2', '9', 0, |
| /* 2539 */ 'z', '2', '9', 0, |
| /* 2543 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0, |
| /* 2555 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0, |
| /* 2567 */ 'W', '8', '_', 'W', '9', 0, |
| /* 2573 */ 'X', '8', '_', 'X', '9', 0, |
| /* 2579 */ 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', 0, |
| /* 2591 */ 'b', '9', 0, |
| /* 2594 */ 'd', '9', 0, |
| /* 2597 */ 'h', '9', 0, |
| /* 2600 */ 'p', '9', 0, |
| /* 2603 */ 'q', '9', 0, |
| /* 2606 */ 's', '9', 0, |
| /* 2609 */ 'w', '9', 0, |
| /* 2612 */ 'x', '9', 0, |
| /* 2615 */ 'z', '9', 0, |
| /* 2618 */ 'X', '2', '8', '_', 'F', 'P', 0, |
| /* 2625 */ 'W', '3', '0', '_', 'W', 'Z', 'R', 0, |
| /* 2633 */ 'L', 'R', '_', 'X', 'Z', 'R', 0, |
| /* 2640 */ 'z', '1', '0', '_', 'h', 'i', 0, |
| /* 2647 */ 'z', '2', '0', '_', 'h', 'i', 0, |
| /* 2654 */ 'z', '3', '0', '_', 'h', 'i', 0, |
| /* 2661 */ 'z', '0', '_', 'h', 'i', 0, |
| /* 2667 */ 'z', '1', '1', '_', 'h', 'i', 0, |
| /* 2674 */ 'z', '2', '1', '_', 'h', 'i', 0, |
| /* 2681 */ 'z', '3', '1', '_', 'h', 'i', 0, |
| /* 2688 */ 'z', '1', '_', 'h', 'i', 0, |
| /* 2694 */ 'z', '1', '2', '_', 'h', 'i', 0, |
| /* 2701 */ 'z', '2', '2', '_', 'h', 'i', 0, |
| /* 2708 */ 'z', '2', '_', 'h', 'i', 0, |
| /* 2714 */ 'z', '1', '3', '_', 'h', 'i', 0, |
| /* 2721 */ 'z', '2', '3', '_', 'h', 'i', 0, |
| /* 2728 */ 'z', '3', '_', 'h', 'i', 0, |
| /* 2734 */ 'z', '1', '4', '_', 'h', 'i', 0, |
| /* 2741 */ 'z', '2', '4', '_', 'h', 'i', 0, |
| /* 2748 */ 'z', '4', '_', 'h', 'i', 0, |
| /* 2754 */ 'z', '1', '5', '_', 'h', 'i', 0, |
| /* 2761 */ 'z', '2', '5', '_', 'h', 'i', 0, |
| /* 2768 */ 'z', '5', '_', 'h', 'i', 0, |
| /* 2774 */ 'z', '1', '6', '_', 'h', 'i', 0, |
| /* 2781 */ 'z', '2', '6', '_', 'h', 'i', 0, |
| /* 2788 */ 'z', '6', '_', 'h', 'i', 0, |
| /* 2794 */ 'z', '1', '7', '_', 'h', 'i', 0, |
| /* 2801 */ 'z', '2', '7', '_', 'h', 'i', 0, |
| /* 2808 */ 'z', '7', '_', 'h', 'i', 0, |
| /* 2814 */ 'z', '1', '8', '_', 'h', 'i', 0, |
| /* 2821 */ 'z', '2', '8', '_', 'h', 'i', 0, |
| /* 2828 */ 'z', '8', '_', 'h', 'i', 0, |
| /* 2834 */ 'z', '1', '9', '_', 'h', 'i', 0, |
| /* 2841 */ 'z', '2', '9', '_', 'h', 'i', 0, |
| /* 2848 */ 'z', '9', '_', 'h', 'i', 0, |
| /* 2854 */ 'w', 's', 'p', 0, |
| /* 2858 */ 'f', 'f', 'r', 0, |
| /* 2862 */ 'w', 'z', 'r', 0, |
| /* 2866 */ 'x', 'z', 'r', 0, |
| /* 2870 */ 'n', 'z', 'c', 'v', 0, |
| }; |
| |
| static const uint16_t RegAsmOffsetNoRegAltName[] = { |
| 2858, 2535, 227, 2870, 2855, 2854, 2862, 2866, 280, 623, 850, 1121, 1348, 1619, |
| 1842, 2109, 2332, 2591, 39, 365, 695, 941, 1196, 1439, 1694, 1933, 2184, 2423, |
| 123, 465, 779, 1041, 1280, 1539, 1774, 2029, 2264, 2511, 203, 545, 283, 626, |
| 853, 1124, 1351, 1622, 1845, 2112, 2335, 2594, 43, 369, 699, 945, 1200, 1443, |
| 1698, 1937, 2188, 2427, 127, 469, 783, 1045, 1284, 1543, 1778, 2033, 2268, 2515, |
| 207, 549, 286, 629, 856, 1127, 1354, 1625, 1848, 2115, 2338, 2597, 47, 373, |
| 703, 949, 1204, 1447, 1702, 1941, 2192, 2431, 131, 473, 787, 1049, 1288, 1547, |
| 1782, 2037, 2272, 2519, 211, 553, 289, 632, 859, 1130, 1357, 1628, 1851, 2118, |
| 2341, 2600, 51, 377, 707, 953, 1208, 1451, 292, 635, 862, 1133, 1360, 1631, |
| 1854, 2121, 2344, 2603, 55, 381, 711, 957, 1212, 1455, 1706, 1945, 2196, 2435, |
| 135, 477, 791, 1053, 1292, 1551, 1786, 2041, 2276, 2523, 215, 557, 295, 638, |
| 865, 1136, 1363, 1634, 1857, 2124, 2347, 2606, 59, 385, 715, 961, 1216, 1459, |
| 1710, 1949, 2200, 2439, 139, 481, 795, 1057, 1296, 1555, 1790, 2045, 2280, 2527, |
| 219, 561, 298, 641, 868, 1139, 1366, 1637, 1860, 2127, 2350, 2609, 63, 389, |
| 719, 965, 1220, 1463, 1714, 1953, 2204, 2443, 143, 485, 799, 1061, 1300, 1559, |
| 1794, 2049, 2284, 2531, 223, 301, 644, 871, 1142, 1369, 1640, 1863, 2130, 2353, |
| 2612, 67, 393, 723, 969, 1224, 1467, 1718, 1957, 2208, 2447, 147, 489, 803, |
| 1065, 1304, 1563, 1798, 2053, 2288, 304, 647, 874, 1145, 1372, 1643, 1866, 2133, |
| 2356, 2615, 71, 397, 727, 973, 1228, 1471, 1722, 1961, 2212, 2451, 151, 493, |
| 807, 1069, 1308, 1567, 1802, 2057, 2292, 2539, 231, 565, 2661, 2688, 2708, 2728, |
| 2748, 2768, 2788, 2808, 2828, 2848, 2640, 2667, 2694, 2714, 2734, 2754, 2774, 2794, |
| 2814, 2834, 2647, 2674, 2701, 2721, 2741, 2761, 2781, 2801, 2821, 2841, 2654, 2681, |
| 577, 818, 1079, 1318, 1577, 1812, 2067, 2302, 2549, 6, 313, 657, 885, 1156, |
| 1383, 1654, 1877, 2144, 2367, 83, 409, 739, 985, 1240, 1483, 1734, 1973, 2224, |
| 2463, 163, 505, 243, 1073, 1312, 1571, 1806, 2061, 2296, 2543, 0, 307, 650, |
| 877, 1148, 1375, 1646, 1869, 2136, 2359, 75, 401, 731, 977, 1232, 1475, 1726, |
| 1965, 2216, 2455, 155, 497, 235, 569, 811, 815, 1076, 1315, 1574, 1809, 2064, |
| 2299, 2546, 3, 310, 653, 881, 1152, 1379, 1650, 1873, 2140, 2363, 79, 405, |
| 735, 981, 1236, 1479, 1730, 1969, 2220, 2459, 159, 501, 239, 573, 591, 831, |
| 1091, 1330, 1589, 1824, 2079, 2314, 2561, 19, 327, 672, 901, 1172, 1399, 1670, |
| 1893, 2160, 2383, 99, 425, 755, 1001, 1256, 1499, 1750, 1989, 2240, 2479, 179, |
| 521, 258, 1085, 1324, 1583, 1818, 2073, 2308, 2555, 13, 321, 665, 893, 1164, |
| 1391, 1662, 1885, 2152, 2375, 91, 417, 747, 993, 1248, 1491, 1742, 1981, 2232, |
| 2471, 171, 513, 250, 583, 824, 828, 1088, 1327, 1586, 1821, 2076, 2311, 2558, |
| 16, 324, 668, 897, 1168, 1395, 1666, 1889, 2156, 2379, 95, 421, 751, 997, |
| 1252, 1495, 1746, 1985, 2236, 2475, 175, 517, 254, 587, 2625, 597, 1097, 1595, |
| 2085, 2567, 335, 909, 1407, 1901, 2391, 433, 1009, 1507, 1997, 2487, 2633, 2618, |
| 603, 1103, 1601, 2091, 2573, 343, 917, 1415, 1909, 2399, 441, 1017, 1515, 2005, |
| 617, 844, 1115, 1342, 1613, 1836, 2103, 2326, 2585, 32, 357, 687, 933, 1188, |
| 1431, 1686, 1925, 2176, 2415, 115, 457, 771, 1033, 1272, 1531, 1766, 2021, 2256, |
| 2503, 195, 537, 273, 1109, 1336, 1607, 1830, 2097, 2320, 2579, 26, 351, 680, |
| 925, 1180, 1423, 1678, 1917, 2168, 2407, 107, 449, 763, 1025, 1264, 1523, 1758, |
| 2013, 2248, 2495, 187, 529, 265, 609, 837, 841, 1112, 1339, 1610, 1833, 2100, |
| 2323, 2582, 29, 354, 683, 929, 1184, 1427, 1682, 1921, 2172, 2411, 111, 453, |
| 767, 1029, 1268, 1527, 1762, 2017, 2252, 2499, 191, 533, 269, 613, |
| }; |
| |
| static const char AsmStrsvlist1[] = { |
| /* 0 */ 0, |
| }; |
| |
| static const uint8_t RegAsmOffsetvlist1[] = { |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| }; |
| |
| static const char AsmStrsvreg[] = { |
| /* 0 */ 'v', '1', '0', 0, |
| /* 4 */ 'v', '2', '0', 0, |
| /* 8 */ 'v', '3', '0', 0, |
| /* 12 */ 'v', '0', 0, |
| /* 15 */ 'v', '1', '1', 0, |
| /* 19 */ 'v', '2', '1', 0, |
| /* 23 */ 'v', '3', '1', 0, |
| /* 27 */ 'v', '1', 0, |
| /* 30 */ 'v', '1', '2', 0, |
| /* 34 */ 'v', '2', '2', 0, |
| /* 38 */ 'v', '2', 0, |
| /* 41 */ 'v', '1', '3', 0, |
| /* 45 */ 'v', '2', '3', 0, |
| /* 49 */ 'v', '3', 0, |
| /* 52 */ 'v', '1', '4', 0, |
| /* 56 */ 'v', '2', '4', 0, |
| /* 60 */ 'v', '4', 0, |
| /* 63 */ 'v', '1', '5', 0, |
| /* 67 */ 'v', '2', '5', 0, |
| /* 71 */ 'v', '5', 0, |
| /* 74 */ 'v', '1', '6', 0, |
| /* 78 */ 'v', '2', '6', 0, |
| /* 82 */ 'v', '6', 0, |
| /* 85 */ 'v', '1', '7', 0, |
| /* 89 */ 'v', '2', '7', 0, |
| /* 93 */ 'v', '7', 0, |
| /* 96 */ 'v', '1', '8', 0, |
| /* 100 */ 'v', '2', '8', 0, |
| /* 104 */ 'v', '8', 0, |
| /* 107 */ 'v', '1', '9', 0, |
| /* 111 */ 'v', '2', '9', 0, |
| /* 115 */ 'v', '9', 0, |
| }; |
| |
| static const uint8_t RegAsmOffsetvreg[] = { |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, |
| 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, |
| 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, |
| 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, |
| 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, |
| 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, |
| 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, |
| 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, |
| 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, |
| 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, |
| 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, |
| 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, |
| 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, |
| 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, |
| 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, |
| 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, |
| 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, |
| 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, |
| 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| }; |
| |
| switch(AltIdx) { |
| default: llvm_unreachable("Invalid register alt name index!"); |
| case AArch64::NoRegAltName: |
| assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) && |
| "Invalid alt name index for register!"); |
| return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]; |
| case AArch64::vlist1: |
| assert(*(AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1]) && |
| "Invalid alt name index for register!"); |
| return AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1]; |
| case AArch64::vreg: |
| assert(*(AsmStrsvreg+RegAsmOffsetvreg[RegNo-1]) && |
| "Invalid alt name index for register!"); |
| return AsmStrsvreg+RegAsmOffsetvreg[RegNo-1]; |
| } |
| } |
| |
| #ifdef PRINT_ALIAS_INSTR |
| #undef PRINT_ALIAS_INSTR |
| |
| static bool AArch64InstPrinterValidateMCOperand(const MCOperand &MCOp, |
| const MCSubtargetInfo &STI, |
| unsigned PredicateIndex); |
| bool AArch64InstPrinter::printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &OS) { |
| static const PatternsForOpcode OpToPatterns[] = { |
| {AArch64::ADDSWri, 0, 1 }, |
| {AArch64::ADDSWrs, 1, 3 }, |
| {AArch64::ADDSWrx, 4, 3 }, |
| {AArch64::ADDSXri, 7, 1 }, |
| {AArch64::ADDSXrs, 8, 3 }, |
| {AArch64::ADDSXrx, 11, 1 }, |
| {AArch64::ADDSXrx64, 12, 3 }, |
| {AArch64::ADDWri, 15, 2 }, |
| {AArch64::ADDWrs, 17, 1 }, |
| {AArch64::ADDWrx, 18, 2 }, |
| {AArch64::ADDXri, 20, 2 }, |
| {AArch64::ADDXrs, 22, 1 }, |
| {AArch64::ADDXrx64, 23, 2 }, |
| {AArch64::ANDSWri, 25, 1 }, |
| {AArch64::ANDSWrs, 26, 3 }, |
| {AArch64::ANDSXri, 29, 1 }, |
| {AArch64::ANDSXrs, 30, 3 }, |
| {AArch64::ANDS_PPzPP, 33, 1 }, |
| {AArch64::ANDWrs, 34, 1 }, |
| {AArch64::ANDXrs, 35, 1 }, |
| {AArch64::AND_PPzPP, 36, 1 }, |
| {AArch64::AND_ZI, 37, 3 }, |
| {AArch64::AUTIA1716, 40, 1 }, |
| {AArch64::AUTIASP, 41, 1 }, |
| {AArch64::AUTIAZ, 42, 1 }, |
| {AArch64::AUTIB1716, 43, 1 }, |
| {AArch64::AUTIBSP, 44, 1 }, |
| {AArch64::AUTIBZ, 45, 1 }, |
| {AArch64::BICSWrs, 46, 1 }, |
| {AArch64::BICSXrs, 47, 1 }, |
| {AArch64::BICWrs, 48, 1 }, |
| {AArch64::BICXrs, 49, 1 }, |
| {AArch64::CLREX, 50, 1 }, |
| {AArch64::CNTB_XPiI, 51, 2 }, |
| {AArch64::CNTD_XPiI, 53, 2 }, |
| {AArch64::CNTH_XPiI, 55, 2 }, |
| {AArch64::CNTW_XPiI, 57, 2 }, |
| {AArch64::CPY_ZPmI_B, 59, 1 }, |
| {AArch64::CPY_ZPmI_D, 60, 1 }, |
| {AArch64::CPY_ZPmI_H, 61, 1 }, |
| {AArch64::CPY_ZPmI_S, 62, 1 }, |
| {AArch64::CPY_ZPmR_B, 63, 1 }, |
| {AArch64::CPY_ZPmR_D, 64, 1 }, |
| {AArch64::CPY_ZPmR_H, 65, 1 }, |
| {AArch64::CPY_ZPmR_S, 66, 1 }, |
| {AArch64::CPY_ZPmV_B, 67, 1 }, |
| {AArch64::CPY_ZPmV_D, 68, 1 }, |
| {AArch64::CPY_ZPmV_H, 69, 1 }, |
| {AArch64::CPY_ZPmV_S, 70, 1 }, |
| {AArch64::CPY_ZPzI_B, 71, 1 }, |
| {AArch64::CPY_ZPzI_D, 72, 1 }, |
| {AArch64::CPY_ZPzI_H, 73, 1 }, |
| {AArch64::CPY_ZPzI_S, 74, 1 }, |
| {AArch64::CSINCWr, 75, 2 }, |
| {AArch64::CSINCXr, 77, 2 }, |
| {AArch64::CSINVWr, 79, 2 }, |
| {AArch64::CSINVXr, 81, 2 }, |
| {AArch64::CSNEGWr, 83, 1 }, |
| {AArch64::CSNEGXr, 84, 1 }, |
| {AArch64::DCPS1, 85, 1 }, |
| {AArch64::DCPS2, 86, 1 }, |
| {AArch64::DCPS3, 87, 1 }, |
| {AArch64::DECB_XPiI, 88, 2 }, |
| {AArch64::DECD_XPiI, 90, 2 }, |
| {AArch64::DECD_ZPiI, 92, 2 }, |
| {AArch64::DECH_XPiI, 94, 2 }, |
| {AArch64::DECH_ZPiI, 96, 2 }, |
| {AArch64::DECW_XPiI, 98, 2 }, |
| {AArch64::DECW_ZPiI, 100, 2 }, |
| {AArch64::DSB, 102, 2 }, |
| {AArch64::DUPM_ZI, 104, 6 }, |
| {AArch64::DUP_ZI_B, 110, 1 }, |
| {AArch64::DUP_ZI_D, 111, 2 }, |
| {AArch64::DUP_ZI_H, 113, 2 }, |
| {AArch64::DUP_ZI_S, 115, 2 }, |
| {AArch64::DUP_ZR_B, 117, 1 }, |
| {AArch64::DUP_ZR_D, 118, 1 }, |
| {AArch64::DUP_ZR_H, 119, 1 }, |
| {AArch64::DUP_ZR_S, 120, 1 }, |
| {AArch64::DUP_ZZI_B, 121, 2 }, |
| {AArch64::DUP_ZZI_D, 123, 2 }, |
| {AArch64::DUP_ZZI_H, 125, 2 }, |
| {AArch64::DUP_ZZI_Q, 127, 2 }, |
| {AArch64::DUP_ZZI_S, 129, 2 }, |
| {AArch64::EONWrs, 131, 1 }, |
| {AArch64::EONXrs, 132, 1 }, |
| {AArch64::EORS_PPzPP, 133, 1 }, |
| {AArch64::EORWrs, 134, 1 }, |
| {AArch64::EORXrs, 135, 1 }, |
| {AArch64::EOR_PPzPP, 136, 1 }, |
| {AArch64::EOR_ZI, 137, 3 }, |
| {AArch64::EXTRWrri, 140, 1 }, |
| {AArch64::EXTRXrri, 141, 1 }, |
| {AArch64::FCPY_ZPmI_D, 142, 1 }, |
| {AArch64::FCPY_ZPmI_H, 143, 1 }, |
| {AArch64::FCPY_ZPmI_S, 144, 1 }, |
| {AArch64::FDUP_ZI_D, 145, 1 }, |
| {AArch64::FDUP_ZI_H, 146, 1 }, |
| {AArch64::FDUP_ZI_S, 147, 1 }, |
| {AArch64::GLD1B_D_IMM_REAL, 148, 1 }, |
| {AArch64::GLD1B_S_IMM_REAL, 149, 1 }, |
| {AArch64::GLD1D_IMM_REAL, 150, 1 }, |
| {AArch64::GLD1H_D_IMM_REAL, 151, 1 }, |
| {AArch64::GLD1H_S_IMM_REAL, 152, 1 }, |
| {AArch64::GLD1SB_D_IMM_REAL, 153, 1 }, |
| {AArch64::GLD1SB_S_IMM_REAL, 154, 1 }, |
| {AArch64::GLD1SH_D_IMM_REAL, 155, 1 }, |
| {AArch64::GLD1SH_S_IMM_REAL, 156, 1 }, |
| {AArch64::GLD1SW_D_IMM_REAL, 157, 1 }, |
| {AArch64::GLD1W_D_IMM_REAL, 158, 1 }, |
| {AArch64::GLD1W_IMM_REAL, 159, 1 }, |
| {AArch64::GLDFF1B_D_IMM_REAL, 160, 1 }, |
| {AArch64::GLDFF1B_S_IMM_REAL, 161, 1 }, |
| {AArch64::GLDFF1D_IMM_REAL, 162, 1 }, |
| {AArch64::GLDFF1H_D_IMM_REAL, 163, 1 }, |
| {AArch64::GLDFF1H_S_IMM_REAL, 164, 1 }, |
| {AArch64::GLDFF1SB_D_IMM_REAL, 165, 1 }, |
| {AArch64::GLDFF1SB_S_IMM_REAL, 166, 1 }, |
| {AArch64::GLDFF1SH_D_IMM_REAL, 167, 1 }, |
| {AArch64::GLDFF1SH_S_IMM_REAL, 168, 1 }, |
| {AArch64::GLDFF1SW_D_IMM_REAL, 169, 1 }, |
| {AArch64::GLDFF1W_D_IMM_REAL, 170, 1 }, |
| {AArch64::GLDFF1W_IMM_REAL, 171, 1 }, |
| {AArch64::HINT, 172, 11 }, |
| {AArch64::INCB_XPiI, 183, 2 }, |
| {AArch64::INCD_XPiI, 185, 2 }, |
| {AArch64::INCD_ZPiI, 187, 2 }, |
| {AArch64::INCH_XPiI, 189, 2 }, |
| {AArch64::INCH_ZPiI, 191, 2 }, |
| {AArch64::INCW_XPiI, 193, 2 }, |
| {AArch64::INCW_ZPiI, 195, 2 }, |
| {AArch64::INSvi16gpr, 197, 1 }, |
| {AArch64::INSvi16lane, 198, 1 }, |
| {AArch64::INSvi32gpr, 199, 1 }, |
| {AArch64::INSvi32lane, 200, 1 }, |
| {AArch64::INSvi64gpr, 201, 1 }, |
| {AArch64::INSvi64lane, 202, 1 }, |
| {AArch64::INSvi8gpr, 203, 1 }, |
| {AArch64::INSvi8lane, 204, 1 }, |
| {AArch64::IRG, 205, 1 }, |
| {AArch64::ISB, 206, 1 }, |
| {AArch64::LD1B_D_IMM, 207, 1 }, |
| {AArch64::LD1B_H_IMM, 208, 1 }, |
| {AArch64::LD1B_IMM, 209, 1 }, |
| {AArch64::LD1B_S_IMM, 210, 1 }, |
| {AArch64::LD1D_IMM, 211, 1 }, |
| {AArch64::LD1Fourv16b_POST, 212, 1 }, |
| {AArch64::LD1Fourv1d_POST, 213, 1 }, |
| {AArch64::LD1Fourv2d_POST, 214, 1 }, |
| {AArch64::LD1Fourv2s_POST, 215, 1 }, |
| {AArch64::LD1Fourv4h_POST, 216, 1 }, |
| {AArch64::LD1Fourv4s_POST, 217, 1 }, |
| {AArch64::LD1Fourv8b_POST, 218, 1 }, |
| {AArch64::LD1Fourv8h_POST, 219, 1 }, |
| {AArch64::LD1H_D_IMM, 220, 1 }, |
| {AArch64::LD1H_IMM, 221, 1 }, |
| {AArch64::LD1H_S_IMM, 222, 1 }, |
| {AArch64::LD1Onev16b_POST, 223, 1 }, |
| {AArch64::LD1Onev1d_POST, 224, 1 }, |
| {AArch64::LD1Onev2d_POST, 225, 1 }, |
| {AArch64::LD1Onev2s_POST, 226, 1 }, |
| {AArch64::LD1Onev4h_POST, 227, 1 }, |
| {AArch64::LD1Onev4s_POST, 228, 1 }, |
| {AArch64::LD1Onev8b_POST, 229, 1 }, |
| {AArch64::LD1Onev8h_POST, 230, 1 }, |
| {AArch64::LD1RB_D_IMM, 231, 1 }, |
| {AArch64::LD1RB_H_IMM, 232, 1 }, |
| {AArch64::LD1RB_IMM, 233, 1 }, |
| {AArch64::LD1RB_S_IMM, 234, 1 }, |
| {AArch64::LD1RD_IMM, 235, 1 }, |
| {AArch64::LD1RH_D_IMM, 236, 1 }, |
| {AArch64::LD1RH_IMM, 237, 1 }, |
| {AArch64::LD1RH_S_IMM, 238, 1 }, |
| {AArch64::LD1RQ_B_IMM, 239, 1 }, |
| {AArch64::LD1RQ_D_IMM, 240, 1 }, |
| {AArch64::LD1RQ_H_IMM, 241, 1 }, |
| {AArch64::LD1RQ_W_IMM, 242, 1 }, |
| {AArch64::LD1RSB_D_IMM, 243, 1 }, |
| {AArch64::LD1RSB_H_IMM, 244, 1 }, |
| {AArch64::LD1RSB_S_IMM, 245, 1 }, |
| {AArch64::LD1RSH_D_IMM, 246, 1 }, |
| {AArch64::LD1RSH_S_IMM, 247, 1 }, |
| {AArch64::LD1RSW_IMM, 248, 1 }, |
| {AArch64::LD1RW_D_IMM, 249, 1 }, |
| {AArch64::LD1RW_IMM, 250, 1 }, |
| {AArch64::LD1Rv16b_POST, 251, 1 }, |
| {AArch64::LD1Rv1d_POST, 252, 1 }, |
| {AArch64::LD1Rv2d_POST, 253, 1 }, |
| {AArch64::LD1Rv2s_POST, 254, 1 }, |
| {AArch64::LD1Rv4h_POST, 255, 1 }, |
| {AArch64::LD1Rv4s_POST, 256, 1 }, |
| {AArch64::LD1Rv8b_POST, 257, 1 }, |
| {AArch64::LD1Rv8h_POST, 258, 1 }, |
| {AArch64::LD1SB_D_IMM, 259, 1 }, |
| {AArch64::LD1SB_H_IMM, 260, 1 }, |
| {AArch64::LD1SB_S_IMM, 261, 1 }, |
| {AArch64::LD1SH_D_IMM, 262, 1 }, |
| {AArch64::LD1SH_S_IMM, 263, 1 }, |
| {AArch64::LD1SW_D_IMM, 264, 1 }, |
| {AArch64::LD1Threev16b_POST, 265, 1 }, |
| {AArch64::LD1Threev1d_POST, 266, 1 }, |
| {AArch64::LD1Threev2d_POST, 267, 1 }, |
| {AArch64::LD1Threev2s_POST, 268, 1 }, |
| {AArch64::LD1Threev4h_POST, 269, 1 }, |
| {AArch64::LD1Threev4s_POST, 270, 1 }, |
| {AArch64::LD1Threev8b_POST, 271, 1 }, |
| {AArch64::LD1Threev8h_POST, 272, 1 }, |
| {AArch64::LD1Twov16b_POST, 273, 1 }, |
| {AArch64::LD1Twov1d_POST, 274, 1 }, |
| {AArch64::LD1Twov2d_POST, 275, 1 }, |
| {AArch64::LD1Twov2s_POST, 276, 1 }, |
| {AArch64::LD1Twov4h_POST, 277, 1 }, |
| {AArch64::LD1Twov4s_POST, 278, 1 }, |
| {AArch64::LD1Twov8b_POST, 279, 1 }, |
| {AArch64::LD1Twov8h_POST, 280, 1 }, |
| {AArch64::LD1W_D_IMM, 281, 1 }, |
| {AArch64::LD1W_IMM, 282, 1 }, |
| {AArch64::LD1i16_POST, 283, 1 }, |
| {AArch64::LD1i32_POST, 284, 1 }, |
| {AArch64::LD1i64_POST, 285, 1 }, |
| {AArch64::LD1i8_POST, 286, 1 }, |
| {AArch64::LD2B_IMM, 287, 1 }, |
| {AArch64::LD2D_IMM, 288, 1 }, |
| {AArch64::LD2H_IMM, 289, 1 }, |
| {AArch64::LD2Rv16b_POST, 290, 1 }, |
| {AArch64::LD2Rv1d_POST, 291, 1 }, |
| {AArch64::LD2Rv2d_POST, 292, 1 }, |
| {AArch64::LD2Rv2s_POST, 293, 1 }, |
| {AArch64::LD2Rv4h_POST, 294, 1 }, |
| {AArch64::LD2Rv4s_POST, 295, 1 }, |
| {AArch64::LD2Rv8b_POST, 296, 1 }, |
| {AArch64::LD2Rv8h_POST, 297, 1 }, |
| {AArch64::LD2Twov16b_POST, 298, 1 }, |
| {AArch64::LD2Twov2d_POST, 299, 1 }, |
| {AArch64::LD2Twov2s_POST, 300, 1 }, |
| {AArch64::LD2Twov4h_POST, 301, 1 }, |
| {AArch64::LD2Twov4s_POST, 302, 1 }, |
| {AArch64::LD2Twov8b_POST, 303, 1 }, |
| {AArch64::LD2Twov8h_POST, 304, 1 }, |
| {AArch64::LD2W_IMM, 305, 1 }, |
| {AArch64::LD2i16_POST, 306, 1 }, |
| {AArch64::LD2i32_POST, 307, 1 }, |
| {AArch64::LD2i64_POST, 308, 1 }, |
| {AArch64::LD2i8_POST, 309, 1 }, |
| {AArch64::LD3B_IMM, 310, 1 }, |
| {AArch64::LD3D_IMM, 311, 1 }, |
| {AArch64::LD3H_IMM, 312, 1 }, |
| {AArch64::LD3Rv16b_POST, 313, 1 }, |
| {AArch64::LD3Rv1d_POST, 314, 1 }, |
| {AArch64::LD3Rv2d_POST, 315, 1 }, |
| {AArch64::LD3Rv2s_POST, 316, 1 }, |
| {AArch64::LD3Rv4h_POST, 317, 1 }, |
| {AArch64::LD3Rv4s_POST, 318, 1 }, |
| {AArch64::LD3Rv8b_POST, 319, 1 }, |
| {AArch64::LD3Rv8h_POST, 320, 1 }, |
| {AArch64::LD3Threev16b_POST, 321, 1 }, |
| {AArch64::LD3Threev2d_POST, 322, 1 }, |
| {AArch64::LD3Threev2s_POST, 323, 1 }, |
| {AArch64::LD3Threev4h_POST, 324, 1 }, |
| {AArch64::LD3Threev4s_POST, 325, 1 }, |
| {AArch64::LD3Threev8b_POST, 326, 1 }, |
| {AArch64::LD3Threev8h_POST, 327, 1 }, |
| {AArch64::LD3W_IMM, 328, 1 }, |
| {AArch64::LD3i16_POST, 329, 1 }, |
| {AArch64::LD3i32_POST, 330, 1 }, |
| {AArch64::LD3i64_POST, 331, 1 }, |
| {AArch64::LD3i8_POST, 332, 1 }, |
| {AArch64::LD4B_IMM, 333, 1 }, |
| {AArch64::LD4D_IMM, 334, 1 }, |
| {AArch64::LD4Fourv16b_POST, 335, 1 }, |
| {AArch64::LD4Fourv2d_POST, 336, 1 }, |
| {AArch64::LD4Fourv2s_POST, 337, 1 }, |
| {AArch64::LD4Fourv4h_POST, 338, 1 }, |
| {AArch64::LD4Fourv4s_POST, 339, 1 }, |
| {AArch64::LD4Fourv8b_POST, 340, 1 }, |
| {AArch64::LD4Fourv8h_POST, 341, 1 }, |
| {AArch64::LD4H_IMM, 342, 1 }, |
| {AArch64::LD4Rv16b_POST, 343, 1 }, |
| {AArch64::LD4Rv1d_POST, 344, 1 }, |
| {AArch64::LD4Rv2d_POST, 345, 1 }, |
| {AArch64::LD4Rv2s_POST, 346, 1 }, |
| {AArch64::LD4Rv4h_POST, 347, 1 }, |
| {AArch64::LD4Rv4s_POST, 348, 1 }, |
| {AArch64::LD4Rv8b_POST, 349, 1 }, |
| {AArch64::LD4Rv8h_POST, 350, 1 }, |
| {AArch64::LD4W_IMM, 351, 1 }, |
| {AArch64::LD4i16_POST, 352, 1 }, |
| {AArch64::LD4i32_POST, 353, 1 }, |
| {AArch64::LD4i64_POST, 354, 1 }, |
| {AArch64::LD4i8_POST, 355, 1 }, |
| {AArch64::LDADDB, 356, 1 }, |
| {AArch64::LDADDH, 357, 1 }, |
| {AArch64::LDADDLB, 358, 1 }, |
| {AArch64::LDADDLH, 359, 1 }, |
| {AArch64::LDADDLW, 360, 1 }, |
| {AArch64::LDADDLX, 361, 1 }, |
| {AArch64::LDADDW, 362, 1 }, |
| {AArch64::LDADDX, 363, 1 }, |
| {AArch64::LDAPURBi, 364, 1 }, |
| {AArch64::LDAPURHi, 365, 1 }, |
| {AArch64::LDAPURSBWi, 366, 1 }, |
| {AArch64::LDAPURSBXi, 367, 1 }, |
| {AArch64::LDAPURSHWi, 368, 1 }, |
| {AArch64::LDAPURSHXi, 369, 1 }, |
| {AArch64::LDAPURSWi, 370, 1 }, |
| {AArch64::LDAPURXi, 371, 1 }, |
| {AArch64::LDAPURi, 372, 1 }, |
| {AArch64::LDCLRB, 373, 1 }, |
| {AArch64::LDCLRH, 374, 1 }, |
| {AArch64::LDCLRLB, 375, 1 }, |
| {AArch64::LDCLRLH, 376, 1 }, |
| {AArch64::LDCLRLW, 377, 1 }, |
| {AArch64::LDCLRLX, 378, 1 }, |
| {AArch64::LDCLRW, 379, 1 }, |
| {AArch64::LDCLRX, 380, 1 }, |
| {AArch64::LDEORB, 381, 1 }, |
| {AArch64::LDEORH, 382, 1 }, |
| {AArch64::LDEORLB, 383, 1 }, |
| {AArch64::LDEORLH, 384, 1 }, |
| {AArch64::LDEORLW, 385, 1 }, |
| {AArch64::LDEORLX, 386, 1 }, |
| {AArch64::LDEORW, 387, 1 }, |
| {AArch64::LDEORX, 388, 1 }, |
| {AArch64::LDFF1B_D_REAL, 389, 1 }, |
| {AArch64::LDFF1B_H_REAL, 390, 1 }, |
| {AArch64::LDFF1B_REAL, 391, 1 }, |
| {AArch64::LDFF1B_S_REAL, 392, 1 }, |
| {AArch64::LDFF1D_REAL, 393, 1 }, |
| {AArch64::LDFF1H_D_REAL, 394, 1 }, |
| {AArch64::LDFF1H_REAL, 395, 1 }, |
| {AArch64::LDFF1H_S_REAL, 396, 1 }, |
| {AArch64::LDFF1SB_D_REAL, 397, 1 }, |
| {AArch64::LDFF1SB_H_REAL, 398, 1 }, |
| {AArch64::LDFF1SB_S_REAL, 399, 1 }, |
| {AArch64::LDFF1SH_D_REAL, 400, 1 }, |
| {AArch64::LDFF1SH_S_REAL, 401, 1 }, |
| {AArch64::LDFF1SW_D_REAL, 402, 1 }, |
| {AArch64::LDFF1W_D_REAL, 403, 1 }, |
| {AArch64::LDFF1W_REAL, 404, 1 }, |
| {AArch64::LDG, 405, 1 }, |
| {AArch64::LDNF1B_D_IMM, 406, 1 }, |
| {AArch64::LDNF1B_H_IMM, 407, 1 }, |
| {AArch64::LDNF1B_IMM, 408, 1 }, |
| {AArch64::LDNF1B_S_IMM, 409, 1 }, |
| {AArch64::LDNF1D_IMM, 410, 1 }, |
| {AArch64::LDNF1H_D_IMM, 411, 1 }, |
| {AArch64::LDNF1H_IMM, 412, 1 }, |
| {AArch64::LDNF1H_S_IMM, 413, 1 }, |
| {AArch64::LDNF1SB_D_IMM, 414, 1 }, |
| {AArch64::LDNF1SB_H_IMM, 415, 1 }, |
| {AArch64::LDNF1SB_S_IMM, 416, 1 }, |
| {AArch64::LDNF1SH_D_IMM, 417, 1 }, |
| {AArch64::LDNF1SH_S_IMM, 418, 1 }, |
| {AArch64::LDNF1SW_D_IMM, 419, 1 }, |
| {AArch64::LDNF1W_D_IMM, 420, 1 }, |
| {AArch64::LDNF1W_IMM, 421, 1 }, |
| {AArch64::LDNPDi, 422, 1 }, |
| {AArch64::LDNPQi, 423, 1 }, |
| {AArch64::LDNPSi, 424, 1 }, |
| {AArch64::LDNPWi, 425, 1 }, |
| {AArch64::LDNPXi, 426, 1 }, |
| {AArch64::LDNT1B_ZRI, 427, 1 }, |
| {AArch64::LDNT1B_ZZR_D_REAL, 428, 1 }, |
| {AArch64::LDNT1B_ZZR_S_REAL, 429, 1 }, |
| {AArch64::LDNT1D_ZRI, 430, 1 }, |
| {AArch64::LDNT1D_ZZR_D_REAL, 431, 1 }, |
| {AArch64::LDNT1H_ZRI, 432, 1 }, |
| {AArch64::LDNT1H_ZZR_D_REAL, 433, 1 }, |
| {AArch64::LDNT1H_ZZR_S_REAL, 434, 1 }, |
| {AArch64::LDNT1SB_ZZR_D_REAL, 435, 1 }, |
| {AArch64::LDNT1SB_ZZR_S_REAL, 436, 1 }, |
| {AArch64::LDNT1SH_ZZR_D_REAL, 437, 1 }, |
| {AArch64::LDNT1SH_ZZR_S_REAL, 438, 1 }, |
| {AArch64::LDNT1SW_ZZR_D_REAL, 439, 1 }, |
| {AArch64::LDNT1W_ZRI, 440, 1 }, |
| {AArch64::LDNT1W_ZZR_D_REAL, 441, 1 }, |
| {AArch64::LDNT1W_ZZR_S_REAL, 442, 1 }, |
| {AArch64::LDPDi, 443, 1 }, |
| {AArch64::LDPQi, 444, 1 }, |
| {AArch64::LDPSWi, 445, 1 }, |
| {AArch64::LDPSi, 446, 1 }, |
| {AArch64::LDPWi, 447, 1 }, |
| {AArch64::LDPXi, 448, 1 }, |
| {AArch64::LDRAAindexed, 449, 1 }, |
| {AArch64::LDRABindexed, 450, 1 }, |
| {AArch64::LDRBBroX, 451, 1 }, |
| {AArch64::LDRBBui, 452, 1 }, |
| {AArch64::LDRBroX, 453, 1 }, |
| {AArch64::LDRBui, 454, 1 }, |
| {AArch64::LDRDroX, 455, 1 }, |
| {AArch64::LDRDui, 456, 1 }, |
| {AArch64::LDRHHroX, 457, 1 }, |
| {AArch64::LDRHHui, 458, 1 }, |
| {AArch64::LDRHroX, 459, 1 }, |
| {AArch64::LDRHui, 460, 1 }, |
| {AArch64::LDRQroX, 461, 1 }, |
| {AArch64::LDRQui, 462, 1 }, |
| {AArch64::LDRSBWroX, 463, 1 }, |
| {AArch64::LDRSBWui, 464, 1 }, |
| {AArch64::LDRSBXroX, 465, 1 }, |
| {AArch64::LDRSBXui, 466, 1 }, |
| {AArch64::LDRSHWroX, 467, 1 }, |
| {AArch64::LDRSHWui, 468, 1 }, |
| {AArch64::LDRSHXroX, 469, 1 }, |
| {AArch64::LDRSHXui, 470, 1 }, |
| {AArch64::LDRSWroX, 471, 1 }, |
| {AArch64::LDRSWui, 472, 1 }, |
| {AArch64::LDRSroX, 473, 1 }, |
| {AArch64::LDRSui, 474, 1 }, |
| {AArch64::LDRWroX, 475, 1 }, |
| {AArch64::LDRWui, 476, 1 }, |
| {AArch64::LDRXroX, 477, 1 }, |
| {AArch64::LDRXui, 478, 1 }, |
| {AArch64::LDR_PXI, 479, 1 }, |
| {AArch64::LDR_ZXI, 480, 1 }, |
| {AArch64::LDSETB, 481, 1 }, |
| {AArch64::LDSETH, 482, 1 }, |
| {AArch64::LDSETLB, 483, 1 }, |
| {AArch64::LDSETLH, 484, 1 }, |
| {AArch64::LDSETLW, 485, 1 }, |
| {AArch64::LDSETLX, 486, 1 }, |
| {AArch64::LDSETW, 487, 1 }, |
| {AArch64::LDSETX, 488, 1 }, |
| {AArch64::LDSMAXB, 489, 1 }, |
| {AArch64::LDSMAXH, 490, 1 }, |
| {AArch64::LDSMAXLB, 491, 1 }, |
| {AArch64::LDSMAXLH, 492, 1 }, |
| {AArch64::LDSMAXLW, 493, 1 }, |
| {AArch64::LDSMAXLX, 494, 1 }, |
| {AArch64::LDSMAXW, 495, 1 }, |
| {AArch64::LDSMAXX, 496, 1 }, |
| {AArch64::LDSMINB, 497, 1 }, |
| {AArch64::LDSMINH, 498, 1 }, |
| {AArch64::LDSMINLB, 499, 1 }, |
| {AArch64::LDSMINLH, 500, 1 }, |
| {AArch64::LDSMINLW, 501, 1 }, |
| {AArch64::LDSMINLX, 502, 1 }, |
| {AArch64::LDSMINW, 503, 1 }, |
| {AArch64::LDSMINX, 504, 1 }, |
| {AArch64::LDTRBi, 505, 1 }, |
| {AArch64::LDTRHi, 506, 1 }, |
| {AArch64::LDTRSBWi, 507, 1 }, |
| {AArch64::LDTRSBXi, 508, 1 }, |
| {AArch64::LDTRSHWi, 509, 1 }, |
| {AArch64::LDTRSHXi, 510, 1 }, |
| {AArch64::LDTRSWi, 511, 1 }, |
| {AArch64::LDTRWi, 512, 1 }, |
| {AArch64::LDTRXi, 513, 1 }, |
| {AArch64::LDUMAXB, 514, 1 }, |
| {AArch64::LDUMAXH, 515, 1 }, |
| {AArch64::LDUMAXLB, 516, 1 }, |
| {AArch64::LDUMAXLH, 517, 1 }, |
| {AArch64::LDUMAXLW, 518, 1 }, |
| {AArch64::LDUMAXLX, 519, 1 }, |
| {AArch64::LDUMAXW, 520, 1 }, |
| {AArch64::LDUMAXX, 521, 1 }, |
| {AArch64::LDUMINB, 522, 1 }, |
| {AArch64::LDUMINH, 523, 1 }, |
| {AArch64::LDUMINLB, 524, 1 }, |
| {AArch64::LDUMINLH, 525, 1 }, |
| {AArch64::LDUMINLW, 526, 1 }, |
| {AArch64::LDUMINLX, 527, 1 }, |
| {AArch64::LDUMINW, 528, 1 }, |
| {AArch64::LDUMINX, 529, 1 }, |
| {AArch64::LDURBBi, 530, 1 }, |
| {AArch64::LDURBi, 531, 1 }, |
| {AArch64::LDURDi, 532, 1 }, |
| {AArch64::LDURHHi, 533, 1 }, |
| {AArch64::LDURHi, 534, 1 }, |
| {AArch64::LDURQi, 535, 1 }, |
| {AArch64::LDURSBWi, 536, 1 }, |
| {AArch64::LDURSBXi, 537, 1 }, |
| {AArch64::LDURSHWi, 538, 1 }, |
| {AArch64::LDURSHXi, 539, 1 }, |
| {AArch64::LDURSWi, 540, 1 }, |
| {AArch64::LDURSi, 541, 1 }, |
| {AArch64::LDURWi, 542, 1 }, |
| {AArch64::LDURXi, 543, 1 }, |
| {AArch64::MADDWrrr, 544, 1 }, |
| {AArch64::MADDXrrr, 545, 1 }, |
| {AArch64::MSUBWrrr, 546, 1 }, |
| {AArch64::MSUBXrrr, 547, 1 }, |
| {AArch64::NOTv16i8, 548, 1 }, |
| {AArch64::NOTv8i8, 549, 1 }, |
| {AArch64::ORNWrs, 550, 3 }, |
| {AArch64::ORNXrs, 553, 3 }, |
| {AArch64::ORRS_PPzPP, 556, 1 }, |
| {AArch64::ORRWrs, 557, 2 }, |
| {AArch64::ORRXrs, 559, 2 }, |
| {AArch64::ORR_PPzPP, 561, 1 }, |
| {AArch64::ORR_ZI, 562, 3 }, |
| {AArch64::ORR_ZZZ, 565, 1 }, |
| {AArch64::ORRv16i8, 566, 1 }, |
| {AArch64::ORRv8i8, 567, 1 }, |
| {AArch64::PACIA1716, 568, 1 }, |
| {AArch64::PACIASP, 569, 1 }, |
| {AArch64::PACIAZ, 570, 1 }, |
| {AArch64::PACIB1716, 571, 1 }, |
| {AArch64::PACIBSP, 572, 1 }, |
| {AArch64::PACIBZ, 573, 1 }, |
| {AArch64::PRFB_D_PZI, 574, 1 }, |
| {AArch64::PRFB_PRI, 575, 1 }, |
| {AArch64::PRFB_S_PZI, 576, 1 }, |
| {AArch64::PRFD_D_PZI, 577, 1 }, |
| {AArch64::PRFD_PRI, 578, 1 }, |
| {AArch64::PRFD_S_PZI, 579, 1 }, |
| {AArch64::PRFH_D_PZI, 580, 1 }, |
| {AArch64::PRFH_PRI, 581, 1 }, |
| {AArch64::PRFH_S_PZI, 582, 1 }, |
| {AArch64::PRFMroX, 583, 1 }, |
| {AArch64::PRFMui, 584, 1 }, |
| {AArch64::PRFUMi, 585, 1 }, |
| {AArch64::PRFW_D_PZI, 586, 1 }, |
| {AArch64::PRFW_PRI, 587, 1 }, |
| {AArch64::PRFW_S_PZI, 588, 1 }, |
| {AArch64::PTRUES_B, 589, 1 }, |
| {AArch64::PTRUES_D, 590, 1 }, |
| {AArch64::PTRUES_H, 591, 1 }, |
| {AArch64::PTRUES_S, 592, 1 }, |
| {AArch64::PTRUE_B, 593, 1 }, |
| {AArch64::PTRUE_D, 594, 1 }, |
| {AArch64::PTRUE_H, 595, 1 }, |
| {AArch64::PTRUE_S, 596, 1 }, |
| {AArch64::RET, 597, 1 }, |
| {AArch64::SBCSWr, 598, 1 }, |
| {AArch64::SBCSXr, 599, 1 }, |
| {AArch64::SBCWr, 600, 1 }, |
| {AArch64::SBCXr, 601, 1 }, |
| {AArch64::SBFMWri, 602, 3 }, |
| {AArch64::SBFMXri, 605, 4 }, |
| {AArch64::SEL_PPPP, 609, 1 }, |
| {AArch64::SEL_ZPZZ_B, 610, 1 }, |
| {AArch64::SEL_ZPZZ_D, 611, 1 }, |
| {AArch64::SEL_ZPZZ_H, 612, 1 }, |
| {AArch64::SEL_ZPZZ_S, 613, 1 }, |
| {AArch64::SMADDLrrr, 614, 1 }, |
| {AArch64::SMSUBLrrr, 615, 1 }, |
| {AArch64::SQDECB_XPiI, 616, 2 }, |
| {AArch64::SQDECB_XPiWdI, 618, 2 }, |
| {AArch64::SQDECD_XPiI, 620, 2 }, |
| {AArch64::SQDECD_XPiWdI, 622, 2 }, |
| {AArch64::SQDECD_ZPiI, 624, 2 }, |
| {AArch64::SQDECH_XPiI, 626, 2 }, |
| {AArch64::SQDECH_XPiWdI, 628, 2 }, |
| {AArch64::SQDECH_ZPiI, 630, 2 }, |
| {AArch64::SQDECW_XPiI, 632, 2 }, |
| {AArch64::SQDECW_XPiWdI, 634, 2 }, |
| {AArch64::SQDECW_ZPiI, 636, 2 }, |
| {AArch64::SQINCB_XPiI, 638, 2 }, |
| {AArch64::SQINCB_XPiWdI, 640, 2 }, |
| {AArch64::SQINCD_XPiI, 642, 2 }, |
| {AArch64::SQINCD_XPiWdI, 644, 2 }, |
| {AArch64::SQINCD_ZPiI, 646, 2 }, |
| {AArch64::SQINCH_XPiI, 648, 2 }, |
| {AArch64::SQINCH_XPiWdI, 650, 2 }, |
| {AArch64::SQINCH_ZPiI, 652, 2 }, |
| {AArch64::SQINCW_XPiI, 654, 2 }, |
| {AArch64::SQINCW_XPiWdI, 656, 2 }, |
| {AArch64::SQINCW_ZPiI, 658, 2 }, |
| {AArch64::SST1B_D_IMM, 660, 1 }, |
| {AArch64::SST1B_S_IMM, 661, 1 }, |
| {AArch64::SST1D_IMM, 662, 1 }, |
| {AArch64::SST1H_D_IMM, 663, 1 }, |
| {AArch64::SST1H_S_IMM, 664, 1 }, |
| {AArch64::SST1W_D_IMM, 665, 1 }, |
| {AArch64::SST1W_IMM, 666, 1 }, |
| {AArch64::ST1B_D_IMM, 667, 1 }, |
| {AArch64::ST1B_H_IMM, 668, 1 }, |
| {AArch64::ST1B_IMM, 669, 1 }, |
| {AArch64::ST1B_S_IMM, 670, 1 }, |
| {AArch64::ST1D_IMM, 671, 1 }, |
| {AArch64::ST1Fourv16b_POST, 672, 1 }, |
| {AArch64::ST1Fourv1d_POST, 673, 1 }, |
| {AArch64::ST1Fourv2d_POST, 674, 1 }, |
| {AArch64::ST1Fourv2s_POST, 675, 1 }, |
| {AArch64::ST1Fourv4h_POST, 676, 1 }, |
| {AArch64::ST1Fourv4s_POST, 677, 1 }, |
| {AArch64::ST1Fourv8b_POST, 678, 1 }, |
| {AArch64::ST1Fourv8h_POST, 679, 1 }, |
| {AArch64::ST1H_D_IMM, 680, 1 }, |
| {AArch64::ST1H_IMM, 681, 1 }, |
| {AArch64::ST1H_S_IMM, 682, 1 }, |
| {AArch64::ST1Onev16b_POST, 683, 1 }, |
| {AArch64::ST1Onev1d_POST, 684, 1 }, |
| {AArch64::ST1Onev2d_POST, 685, 1 }, |
| {AArch64::ST1Onev2s_POST, 686, 1 }, |
| {AArch64::ST1Onev4h_POST, 687, 1 }, |
| {AArch64::ST1Onev4s_POST, 688, 1 }, |
| {AArch64::ST1Onev8b_POST, 689, 1 }, |
| {AArch64::ST1Onev8h_POST, 690, 1 }, |
| {AArch64::ST1Threev16b_POST, 691, 1 }, |
| {AArch64::ST1Threev1d_POST, 692, 1 }, |
| {AArch64::ST1Threev2d_POST, 693, 1 }, |
| {AArch64::ST1Threev2s_POST, 694, 1 }, |
| {AArch64::ST1Threev4h_POST, 695, 1 }, |
| {AArch64::ST1Threev4s_POST, 696, 1 }, |
| {AArch64::ST1Threev8b_POST, 697, 1 }, |
| {AArch64::ST1Threev8h_POST, 698, 1 }, |
| {AArch64::ST1Twov16b_POST, 699, 1 }, |
| {AArch64::ST1Twov1d_POST, 700, 1 }, |
| {AArch64::ST1Twov2d_POST, 701, 1 }, |
| {AArch64::ST1Twov2s_POST, 702, 1 }, |
| {AArch64::ST1Twov4h_POST, 703, 1 }, |
| {AArch64::ST1Twov4s_POST, 704, 1 }, |
| {AArch64::ST1Twov8b_POST, 705, 1 }, |
| {AArch64::ST1Twov8h_POST, 706, 1 }, |
| {AArch64::ST1W_D_IMM, 707, 1 }, |
| {AArch64::ST1W_IMM, 708, 1 }, |
| {AArch64::ST1i16_POST, 709, 1 }, |
| {AArch64::ST1i32_POST, 710, 1 }, |
| {AArch64::ST1i64_POST, 711, 1 }, |
| {AArch64::ST1i8_POST, 712, 1 }, |
| {AArch64::ST2B_IMM, 713, 1 }, |
| {AArch64::ST2D_IMM, 714, 1 }, |
| {AArch64::ST2GOffset, 715, 1 }, |
| {AArch64::ST2H_IMM, 716, 1 }, |
| {AArch64::ST2Twov16b_POST, 717, 1 }, |
| {AArch64::ST2Twov2d_POST, 718, 1 }, |
| {AArch64::ST2Twov2s_POST, 719, 1 }, |
| {AArch64::ST2Twov4h_POST, 720, 1 }, |
| {AArch64::ST2Twov4s_POST, 721, 1 }, |
| {AArch64::ST2Twov8b_POST, 722, 1 }, |
| {AArch64::ST2Twov8h_POST, 723, 1 }, |
| {AArch64::ST2W_IMM, 724, 1 }, |
| {AArch64::ST2i16_POST, 725, 1 }, |
| {AArch64::ST2i32_POST, 726, 1 }, |
| {AArch64::ST2i64_POST, 727, 1 }, |
| {AArch64::ST2i8_POST, 728, 1 }, |
| {AArch64::ST3B_IMM, 729, 1 }, |
| {AArch64::ST3D_IMM, 730, 1 }, |
| {AArch64::ST3H_IMM, 731, 1 }, |
| {AArch64::ST3Threev16b_POST, 732, 1 }, |
| {AArch64::ST3Threev2d_POST, 733, 1 }, |
| {AArch64::ST3Threev2s_POST, 734, 1 }, |
| {AArch64::ST3Threev4h_POST, 735, 1 }, |
| {AArch64::ST3Threev4s_POST, 736, 1 }, |
| {AArch64::ST3Threev8b_POST, 737, 1 }, |
| {AArch64::ST3Threev8h_POST, 738, 1 }, |
| {AArch64::ST3W_IMM, 739, 1 }, |
| {AArch64::ST3i16_POST, 740, 1 }, |
| {AArch64::ST3i32_POST, 741, 1 }, |
| {AArch64::ST3i64_POST, 742, 1 }, |
| {AArch64::ST3i8_POST, 743, 1 }, |
| {AArch64::ST4B_IMM, 744, 1 }, |
| {AArch64::ST4D_IMM, 745, 1 }, |
| {AArch64::ST4Fourv16b_POST, 746, 1 }, |
| {AArch64::ST4Fourv2d_POST, 747, 1 }, |
| {AArch64::ST4Fourv2s_POST, 748, 1 }, |
| {AArch64::ST4Fourv4h_POST, 749, 1 }, |
| {AArch64::ST4Fourv4s_POST, 750, 1 }, |
| {AArch64::ST4Fourv8b_POST, 751, 1 }, |
| {AArch64::ST4Fourv8h_POST, 752, 1 }, |
| {AArch64::ST4H_IMM, 753, 1 }, |
| {AArch64::ST4W_IMM, 754, 1 }, |
| {AArch64::ST4i16_POST, 755, 1 }, |
| {AArch64::ST4i32_POST, 756, 1 }, |
| {AArch64::ST4i64_POST, 757, 1 }, |
| {AArch64::ST4i8_POST, 758, 1 }, |
| {AArch64::STGOffset, 759, 1 }, |
| {AArch64::STGPi, 760, 1 }, |
| {AArch64::STLURBi, 761, 1 }, |
| {AArch64::STLURHi, 762, 1 }, |
| {AArch64::STLURWi, 763, 1 }, |
| {AArch64::STLURXi, 764, 1 }, |
| {AArch64::STNPDi, 765, 1 }, |
| {AArch64::STNPQi, 766, 1 }, |
| {AArch64::STNPSi, 767, 1 }, |
| {AArch64::STNPWi, 768, 1 }, |
| {AArch64::STNPXi, 769, 1 }, |
| {AArch64::STNT1B_ZRI, 770, 1 }, |
| {AArch64::STNT1B_ZZR_D_REAL, 771, 1 }, |
| {AArch64::STNT1B_ZZR_S_REAL, 772, 1 }, |
| {AArch64::STNT1D_ZRI, 773, 1 }, |
| {AArch64::STNT1D_ZZR_D_REAL, 774, 1 }, |
| {AArch64::STNT1H_ZRI, 775, 1 }, |
| {AArch64::STNT1H_ZZR_D_REAL, 776, 1 }, |
| {AArch64::STNT1H_ZZR_S_REAL, 777, 1 }, |
| {AArch64::STNT1W_ZRI, 778, 1 }, |
| {AArch64::STNT1W_ZZR_D_REAL, 779, 1 }, |
| {AArch64::STNT1W_ZZR_S_REAL, 780, 1 }, |
| {AArch64::STPDi, 781, 1 }, |
| {AArch64::STPQi, 782, 1 }, |
| {AArch64::STPSi, 783, 1 }, |
| {AArch64::STPWi, 784, 1 }, |
| {AArch64::STPXi, 785, 1 }, |
| {AArch64::STRBBroX, 786, 1 }, |
| {AArch64::STRBBui, 787, 1 }, |
| {AArch64::STRBroX, 788, 1 }, |
| {AArch64::STRBui, 789, 1 }, |
| {AArch64::STRDroX, 790, 1 }, |
| {AArch64::STRDui, 791, 1 }, |
| {AArch64::STRHHroX, 792, 1 }, |
| {AArch64::STRHHui, 793, 1 }, |
| {AArch64::STRHroX, 794, 1 }, |
| {AArch64::STRHui, 795, 1 }, |
| {AArch64::STRQroX, 796, 1 }, |
| {AArch64::STRQui, 797, 1 }, |
| {AArch64::STRSroX, 798, 1 }, |
| {AArch64::STRSui, 799, 1 }, |
| {AArch64::STRWroX, 800, 1 }, |
| {AArch64::STRWui, 801, 1 }, |
| {AArch64::STRXroX, 802, 1 }, |
| {AArch64::STRXui, 803, 1 }, |
| {AArch64::STR_PXI, 804, 1 }, |
| {AArch64::STR_ZXI, 805, 1 }, |
| {AArch64::STTRBi, 806, 1 }, |
| {AArch64::STTRHi, 807, 1 }, |
| {AArch64::STTRWi, 808, 1 }, |
| {AArch64::STTRXi, 809, 1 }, |
| {AArch64::STURBBi, 810, 1 }, |
| {AArch64::STURBi, 811, 1 }, |
| {AArch64::STURDi, 812, 1 }, |
| {AArch64::STURHHi, 813, 1 }, |
| {AArch64::STURHi, 814, 1 }, |
| {AArch64::STURQi, 815, 1 }, |
| {AArch64::STURSi, 816, 1 }, |
| {AArch64::STURWi, 817, 1 }, |
| {AArch64::STURXi, 818, 1 }, |
| {AArch64::STZ2GOffset, 819, 1 }, |
| {AArch64::STZGOffset, 820, 1 }, |
| {AArch64::SUBSWri, 821, 1 }, |
| {AArch64::SUBSWrs, 822, 5 }, |
| {AArch64::SUBSWrx, 827, 3 }, |
| {AArch64::SUBSXri, 830, 1 }, |
| {AArch64::SUBSXrs, 831, 5 }, |
| {AArch64::SUBSXrx, 836, 1 }, |
| {AArch64::SUBSXrx64, 837, 3 }, |
| {AArch64::SUBWrs, 840, 3 }, |
| {AArch64::SUBWrx, 843, 2 }, |
| {AArch64::SUBXrs, 845, 3 }, |
| {AArch64::SUBXrx64, 848, 2 }, |
| {AArch64::SYSxt, 850, 1 }, |
| {AArch64::UBFMWri, 851, 3 }, |
| {AArch64::UBFMXri, 854, 4 }, |
| {AArch64::UMADDLrrr, 858, 1 }, |
| {AArch64::UMOVvi32, 859, 1 }, |
| {AArch64::UMOVvi64, 860, 1 }, |
| {AArch64::UMSUBLrrr, 861, 1 }, |
| {AArch64::UQDECB_WPiI, 862, 2 }, |
| {AArch64::UQDECB_XPiI, 864, 2 }, |
| {AArch64::UQDECD_WPiI, 866, 2 }, |
| {AArch64::UQDECD_XPiI, 868, 2 }, |
| {AArch64::UQDECD_ZPiI, 870, 2 }, |
| {AArch64::UQDECH_WPiI, 872, 2 }, |
| {AArch64::UQDECH_XPiI, 874, 2 }, |
| {AArch64::UQDECH_ZPiI, 876, 2 }, |
| {AArch64::UQDECW_WPiI, 878, 2 }, |
| {AArch64::UQDECW_XPiI, 880, 2 }, |
| {AArch64::UQDECW_ZPiI, 882, 2 }, |
| {AArch64::UQINCB_WPiI, 884, 2 }, |
| {AArch64::UQINCB_XPiI, 886, 2 }, |
| {AArch64::UQINCD_WPiI, 888, 2 }, |
| {AArch64::UQINCD_XPiI, 890, 2 }, |
| {AArch64::UQINCD_ZPiI, 892, 2 }, |
| {AArch64::UQINCH_WPiI, 894, 2 }, |
| {AArch64::UQINCH_XPiI, 896, 2 }, |
| {AArch64::UQINCH_ZPiI, 898, 2 }, |
| {AArch64::UQINCW_WPiI, 900, 2 }, |
| {AArch64::UQINCW_XPiI, 902, 2 }, |
| {AArch64::UQINCW_ZPiI, 904, 2 }, |
| {AArch64::XPACLRI, 906, 1 }, |
| }; |
| |
| static const AliasPattern Patterns[] = { |
| // AArch64::ADDSWri - 0 |
| {0, 0, 4, 2 }, |
| // AArch64::ADDSWrs - 1 |
| {13, 2, 4, 4 }, |
| {24, 6, 4, 3 }, |
| {39, 9, 4, 4 }, |
| // AArch64::ADDSWrx - 4 |
| {13, 13, 4, 4 }, |
| {55, 17, 4, 3 }, |
| {39, 20, 4, 4 }, |
| // AArch64::ADDSXri - 7 |
| {0, 24, 4, 2 }, |
| // AArch64::ADDSXrs - 8 |
| {13, 26, 4, 4 }, |
| {24, 30, 4, 3 }, |
| {39, 33, 4, 4 }, |
| // AArch64::ADDSXrx - 11 |
| {55, 37, 4, 3 }, |
| // AArch64::ADDSXrx64 - 12 |
| {13, 40, 4, 4 }, |
| {55, 44, 4, 3 }, |
| {39, 47, 4, 4 }, |
| // AArch64::ADDWri - 15 |
| {70, 51, 4, 4 }, |
| {70, 55, 4, 4 }, |
| // AArch64::ADDWrs - 17 |
| {81, 59, 4, 4 }, |
| // AArch64::ADDWrx - 18 |
| {81, 63, 4, 4 }, |
| {81, 67, 4, 4 }, |
| // AArch64::ADDXri - 20 |
| {70, 71, 4, 4 }, |
| {70, 75, 4, 4 }, |
| // AArch64::ADDXrs - 22 |
| {81, 79, 4, 4 }, |
| // AArch64::ADDXrx64 - 23 |
| {81, 83, 4, 4 }, |
| {81, 87, 4, 4 }, |
| // AArch64::ANDSWri - 25 |
| {96, 91, 3, 2 }, |
| // AArch64::ANDSWrs - 26 |
| {109, 93, 4, 4 }, |
| {120, 97, 4, 3 }, |
| {135, 100, 4, 4 }, |
| // AArch64::ANDSXri - 29 |
| {151, 104, 3, 2 }, |
| // AArch64::ANDSXrs - 30 |
| {109, 106, 4, 4 }, |
| {120, 110, 4, 3 }, |
| {135, 113, 4, 4 }, |
| // AArch64::ANDS_PPzPP - 33 |
| {164, 117, 4, 5 }, |
| // AArch64::ANDWrs - 34 |
| {188, 122, 4, 4 }, |
| // AArch64::ANDXrs - 35 |
| {188, 126, 4, 4 }, |
| // AArch64::AND_PPzPP - 36 |
| {203, 130, 4, 5 }, |
| // AArch64::AND_ZI - 37 |
| {226, 135, 3, 4 }, |
| {247, 139, 3, 4 }, |
| {268, 143, 3, 4 }, |
| // AArch64::AUTIA1716 - 40 |
| {289, 147, 0, 1 }, |
| // AArch64::AUTIASP - 41 |
| {299, 148, 0, 1 }, |
| // AArch64::AUTIAZ - 42 |
| {307, 149, 0, 1 }, |
| // AArch64::AUTIB1716 - 43 |
| {314, 150, 0, 1 }, |
| // AArch64::AUTIBSP - 44 |
| {324, 151, 0, 1 }, |
| // AArch64::AUTIBZ - 45 |
| {332, 152, 0, 1 }, |
| // AArch64::BICSWrs - 46 |
| {339, 153, 4, 4 }, |
| // AArch64::BICSXrs - 47 |
| {339, 157, 4, 4 }, |
| // AArch64::BICWrs - 48 |
| {355, 161, 4, 4 }, |
| // AArch64::BICXrs - 49 |
| {355, 165, 4, 4 }, |
| // AArch64::CLREX - 50 |
| {370, 169, 1, 1 }, |
| // AArch64::CNTB_XPiI - 51 |
| {376, 170, 3, 4 }, |
| {384, 174, 3, 4 }, |
| // AArch64::CNTD_XPiI - 53 |
| {398, 178, 3, 4 }, |
| {406, 182, 3, 4 }, |
| // AArch64::CNTH_XPiI - 55 |
| {420, 186, 3, 4 }, |
| {428, 190, 3, 4 }, |
| // AArch64::CNTW_XPiI - 57 |
| {442, 194, 3, 4 }, |
| {450, 198, 3, 4 }, |
| // AArch64::CPY_ZPmI_B - 59 |
| {464, 202, 5, 4 }, |
| // AArch64::CPY_ZPmI_D - 60 |
| {487, 206, 5, 4 }, |
| // AArch64::CPY_ZPmI_H - 61 |
| {510, 210, 5, 4 }, |
| // AArch64::CPY_ZPmI_S - 62 |
| {533, 214, 5, 4 }, |
| // AArch64::CPY_ZPmR_B - 63 |
| {556, 218, 4, 5 }, |
| // AArch64::CPY_ZPmR_D - 64 |
| {577, 223, 4, 5 }, |
| // AArch64::CPY_ZPmR_H - 65 |
| {598, 228, 4, 5 }, |
| // AArch64::CPY_ZPmR_S - 66 |
| {619, 233, 4, 5 }, |
| // AArch64::CPY_ZPmV_B - 67 |
| {556, 238, 4, 5 }, |
| // AArch64::CPY_ZPmV_D - 68 |
| {577, 243, 4, 5 }, |
| // AArch64::CPY_ZPmV_H - 69 |
| {598, 248, 4, 5 }, |
| // AArch64::CPY_ZPmV_S - 70 |
| {619, 253, 4, 5 }, |
| // AArch64::CPY_ZPzI_B - 71 |
| {640, 258, 4, 3 }, |
| // AArch64::CPY_ZPzI_D - 72 |
| {663, 261, 4, 3 }, |
| // AArch64::CPY_ZPzI_H - 73 |
| {686, 264, 4, 3 }, |
| // AArch64::CPY_ZPzI_S - 74 |
| {709, 267, 4, 3 }, |
| // AArch64::CSINCWr - 75 |
| {732, 270, 4, 4 }, |
| {746, 274, 4, 4 }, |
| // AArch64::CSINCXr - 77 |
| {732, 278, 4, 4 }, |
| {746, 282, 4, 4 }, |
| // AArch64::CSINVWr - 79 |
| {764, 286, 4, 4 }, |
| {779, 290, 4, 4 }, |
| // AArch64::CSINVXr - 81 |
| {764, 294, 4, 4 }, |
| {779, 298, 4, 4 }, |
| // AArch64::CSNEGWr - 83 |
| {797, 302, 4, 4 }, |
| // AArch64::CSNEGXr - 84 |
| {797, 306, 4, 4 }, |
| // AArch64::DCPS1 - 85 |
| {815, 310, 1, 1 }, |
| // AArch64::DCPS2 - 86 |
| {821, 311, 1, 1 }, |
| // AArch64::DCPS3 - 87 |
| {827, 312, 1, 1 }, |
| // AArch64::DECB_XPiI - 88 |
| {833, 313, 4, 5 }, |
| {841, 318, 4, 5 }, |
| // AArch64::DECD_XPiI - 90 |
| {855, 323, 4, 5 }, |
| {863, 328, 4, 5 }, |
| // AArch64::DECD_ZPiI - 92 |
| {877, 333, 4, 5 }, |
| {887, 338, 4, 5 }, |
| // AArch64::DECH_XPiI - 94 |
| {903, 343, 4, 5 }, |
| {911, 348, 4, 5 }, |
| // AArch64::DECH_ZPiI - 96 |
| {925, 353, 4, 5 }, |
| {935, 358, 4, 5 }, |
| // AArch64::DECW_XPiI - 98 |
| {951, 363, 4, 5 }, |
| {959, 368, 4, 5 }, |
| // AArch64::DECW_ZPiI - 100 |
| {973, 373, 4, 5 }, |
| {983, 378, 4, 5 }, |
| // AArch64::DSB - 102 |
| {999, 383, 1, 1 }, |
| {1004, 384, 1, 1 }, |
| // AArch64::DUPM_ZI - 104 |
| {1010, 385, 2, 3 }, |
| {1025, 388, 2, 3 }, |
| {1040, 391, 2, 3 }, |
| {1055, 394, 2, 3 }, |
| {1071, 397, 2, 3 }, |
| {1087, 400, 2, 3 }, |
| // AArch64::DUP_ZI_B - 110 |
| {1103, 403, 3, 2 }, |
| // AArch64::DUP_ZI_D - 111 |
| {1118, 405, 3, 2 }, |
| {1133, 407, 3, 4 }, |
| // AArch64::DUP_ZI_H - 113 |
| {1149, 411, 3, 2 }, |
| {1164, 413, 3, 4 }, |
| // AArch64::DUP_ZI_S - 115 |
| {1180, 417, 3, 2 }, |
| {1195, 419, 3, 4 }, |
| // AArch64::DUP_ZR_B - 117 |
| {1211, 423, 2, 3 }, |
| // AArch64::DUP_ZR_D - 118 |
| {1224, 426, 2, 3 }, |
| // AArch64::DUP_ZR_H - 119 |
| {1237, 429, 2, 3 }, |
| // AArch64::DUP_ZR_S - 120 |
| {1250, 432, 2, 3 }, |
| // AArch64::DUP_ZZI_B - 121 |
| {1263, 435, 3, 4 }, |
| {1278, 439, 3, 3 }, |
| // AArch64::DUP_ZZI_D - 123 |
| {1297, 442, 3, 4 }, |
| {1312, 446, 3, 3 }, |
| // AArch64::DUP_ZZI_H - 125 |
| {1331, 449, 3, 4 }, |
| {1346, 453, 3, 3 }, |
| // AArch64::DUP_ZZI_Q - 127 |
| {1365, 456, 3, 4 }, |
| {1380, 460, 3, 3 }, |
| // AArch64::DUP_ZZI_S - 129 |
| {1399, 463, 3, 4 }, |
| {1414, 467, 3, 3 }, |
| // AArch64::EONWrs - 131 |
| {1433, 470, 4, 4 }, |
| // AArch64::EONXrs - 132 |
| {1433, 474, 4, 4 }, |
| // AArch64::EORS_PPzPP - 133 |
| {1448, 478, 4, 5 }, |
| // AArch64::EORWrs - 134 |
| {1472, 483, 4, 4 }, |
| // AArch64::EORXrs - 135 |
| {1472, 487, 4, 4 }, |
| // AArch64::EOR_PPzPP - 136 |
| {1487, 491, 4, 5 }, |
| // AArch64::EOR_ZI - 137 |
| {1510, 496, 3, 4 }, |
| {1531, 500, 3, 4 }, |
| {1552, 504, 3, 4 }, |
| // AArch64::EXTRWrri - 140 |
| {1573, 508, 4, 3 }, |
| // AArch64::EXTRXrri - 141 |
| {1573, 511, 4, 3 }, |
| // AArch64::FCPY_ZPmI_D - 142 |
| {1588, 514, 4, 4 }, |
| // AArch64::FCPY_ZPmI_H - 143 |
| {1612, 518, 4, 4 }, |
| // AArch64::FCPY_ZPmI_S - 144 |
| {1636, 522, 4, 4 }, |
| // AArch64::FDUP_ZI_D - 145 |
| {1660, 526, 2, 2 }, |
| // AArch64::FDUP_ZI_H - 146 |
| {1676, 528, 2, 2 }, |
| // AArch64::FDUP_ZI_S - 147 |
| {1692, 530, 2, 2 }, |
| // AArch64::GLD1B_D_IMM_REAL - 148 |
| {1708, 532, 4, 5 }, |
| // AArch64::GLD1B_S_IMM_REAL - 149 |
| {1734, 537, 4, 5 }, |
| // AArch64::GLD1D_IMM_REAL - 150 |
| {1760, 542, 4, 5 }, |
| // AArch64::GLD1H_D_IMM_REAL - 151 |
| {1786, 547, 4, 5 }, |
| // AArch64::GLD1H_S_IMM_REAL - 152 |
| {1812, 552, 4, 5 }, |
| // AArch64::GLD1SB_D_IMM_REAL - 153 |
| {1838, 557, 4, 5 }, |
| // AArch64::GLD1SB_S_IMM_REAL - 154 |
| {1865, 562, 4, 5 }, |
| // AArch64::GLD1SH_D_IMM_REAL - 155 |
| {1892, 567, 4, 5 }, |
| // AArch64::GLD1SH_S_IMM_REAL - 156 |
| {1919, 572, 4, 5 }, |
| // AArch64::GLD1SW_D_IMM_REAL - 157 |
| {1946, 577, 4, 5 }, |
| // AArch64::GLD1W_D_IMM_REAL - 158 |
| {1973, 582, 4, 5 }, |
| // AArch64::GLD1W_IMM_REAL - 159 |
| {1999, 587, 4, 5 }, |
| // AArch64::GLDFF1B_D_IMM_REAL - 160 |
| {2025, 592, 4, 5 }, |
| // AArch64::GLDFF1B_S_IMM_REAL - 161 |
| {2053, 597, 4, 5 }, |
| // AArch64::GLDFF1D_IMM_REAL - 162 |
| {2081, 602, 4, 5 }, |
| // AArch64::GLDFF1H_D_IMM_REAL - 163 |
| {2109, 607, 4, 5 }, |
| // AArch64::GLDFF1H_S_IMM_REAL - 164 |
| {2137, 612, 4, 5 }, |
| // AArch64::GLDFF1SB_D_IMM_REAL - 165 |
| {2165, 617, 4, 5 }, |
| // AArch64::GLDFF1SB_S_IMM_REAL - 166 |
| {2194, 622, 4, 5 }, |
| // AArch64::GLDFF1SH_D_IMM_REAL - 167 |
| {2223, 627, 4, 5 }, |
| // AArch64::GLDFF1SH_S_IMM_REAL - 168 |
| {2252, 632, 4, 5 }, |
| // AArch64::GLDFF1SW_D_IMM_REAL - 169 |
| {2281, 637, 4, 5 }, |
| // AArch64::GLDFF1W_D_IMM_REAL - 170 |
| {2310, 642, 4, 5 }, |
| // AArch64::GLDFF1W_IMM_REAL - 171 |
| {2338, 647, 4, 5 }, |
| // AArch64::HINT - 172 |
| {2366, 652, 1, 1 }, |
| {2370, 653, 1, 1 }, |
| {2376, 654, 1, 1 }, |
| {2380, 655, 1, 1 }, |
| {2384, 656, 1, 1 }, |
| {2388, 657, 1, 1 }, |
| {2393, 658, 1, 2 }, |
| {2397, 660, 1, 1 }, |
| {2402, 661, 1, 2 }, |
| {2406, 663, 1, 2 }, |
| {2415, 665, 1, 2 }, |
| // AArch64::INCB_XPiI - 183 |
| {2424, 667, 4, 5 }, |
| {2432, 672, 4, 5 }, |
| // AArch64::INCD_XPiI - 185 |
| {2446, 677, 4, 5 }, |
| {2454, 682, 4, 5 }, |
| // AArch64::INCD_ZPiI - 187 |
| {2468, 687, 4, 5 }, |
| {2478, 692, 4, 5 }, |
| // AArch64::INCH_XPiI - 189 |
| {2494, 697, 4, 5 }, |
| {2502, 702, 4, 5 }, |
| // AArch64::INCH_ZPiI - 191 |
| {2516, 707, 4, 5 }, |
| {2526, 712, 4, 5 }, |
| // AArch64::INCW_XPiI - 193 |
| {2542, 717, 4, 5 }, |
| {2550, 722, 4, 5 }, |
| // AArch64::INCW_ZPiI - 195 |
| {2564, 727, 4, 5 }, |
| {2574, 732, 4, 5 }, |
| // AArch64::INSvi16gpr - 197 |
| {2590, 737, 4, 5 }, |
| // AArch64::INSvi16lane - 198 |
| {2609, 742, 5, 5 }, |
| // AArch64::INSvi32gpr - 199 |
| {2636, 747, 4, 5 }, |
| // AArch64::INSvi32lane - 200 |
| {2655, 752, 5, 5 }, |
| // AArch64::INSvi64gpr - 201 |
| {2682, 757, 4, 5 }, |
| // AArch64::INSvi64lane - 202 |
| {2701, 762, 5, 5 }, |
| // AArch64::INSvi8gpr - 203 |
| {2728, 767, 4, 5 }, |
| // AArch64::INSvi8lane - 204 |
| {2747, 772, 5, 5 }, |
| // AArch64::IRG - 205 |
| {2774, 777, 3, 4 }, |
| // AArch64::ISB - 206 |
| {2785, 781, 1, 1 }, |
| // AArch64::LD1B_D_IMM - 207 |
| {2789, 782, 4, 5 }, |
| // AArch64::LD1B_H_IMM - 208 |
| {2813, 787, 4, 5 }, |
| // AArch64::LD1B_IMM - 209 |
| {2837, 792, 4, 5 }, |
| // AArch64::LD1B_S_IMM - 210 |
| {2861, 797, 4, 5 }, |
| // AArch64::LD1D_IMM - 211 |
| {2885, 802, 4, 5 }, |
| // AArch64::LD1Fourv16b_POST - 212 |
| {2909, 807, 4, 5 }, |
| // AArch64::LD1Fourv1d_POST - 213 |
| {2929, 812, 4, 5 }, |
| // AArch64::LD1Fourv2d_POST - 214 |
| {2949, 817, 4, 5 }, |
| // AArch64::LD1Fourv2s_POST - 215 |
| {2969, 822, 4, 5 }, |
| // AArch64::LD1Fourv4h_POST - 216 |
| {2989, 827, 4, 5 }, |
| // AArch64::LD1Fourv4s_POST - 217 |
| {3009, 832, 4, 5 }, |
| // AArch64::LD1Fourv8b_POST - 218 |
| {3029, 837, 4, 5 }, |
| // AArch64::LD1Fourv8h_POST - 219 |
| {3049, 842, 4, 5 }, |
| // AArch64::LD1H_D_IMM - 220 |
| {3069, 847, 4, 5 }, |
| // AArch64::LD1H_IMM - 221 |
| {3093, 852, 4, 5 }, |
| // AArch64::LD1H_S_IMM - 222 |
| {3117, 857, 4, 5 }, |
| // AArch64::LD1Onev16b_POST - 223 |
| {3141, 862, 4, 5 }, |
| // AArch64::LD1Onev1d_POST - 224 |
| {3161, 867, 4, 5 }, |
| // AArch64::LD1Onev2d_POST - 225 |
| {3180, 872, 4, 5 }, |
| // AArch64::LD1Onev2s_POST - 226 |
| {3200, 877, 4, 5 }, |
| // AArch64::LD1Onev4h_POST - 227 |
| {3219, 882, 4, 5 }, |
| // AArch64::LD1Onev4s_POST - 228 |
| {3238, 887, 4, 5 }, |
| // AArch64::LD1Onev8b_POST - 229 |
| {3258, 892, 4, 5 }, |
| // AArch64::LD1Onev8h_POST - 230 |
| {3277, 897, 4, 5 }, |
| // AArch64::LD1RB_D_IMM - 231 |
| {3297, 902, 4, 5 }, |
| // AArch64::LD1RB_H_IMM - 232 |
| {3322, 907, 4, 5 }, |
| // AArch64::LD1RB_IMM - 233 |
| {3347, 912, 4, 5 }, |
| // AArch64::LD1RB_S_IMM - 234 |
| {3372, 917, 4, 5 }, |
| // AArch64::LD1RD_IMM - 235 |
| {3397, 922, 4, 5 }, |
| // AArch64::LD1RH_D_IMM - 236 |
| {3422, 927, 4, 5 }, |
| // AArch64::LD1RH_IMM - 237 |
| {3447, 932, 4, 5 }, |
| // AArch64::LD1RH_S_IMM - 238 |
| {3472, 937, 4, 5 }, |
| // AArch64::LD1RQ_B_IMM - 239 |
| {3497, 942, 4, 5 }, |
| // AArch64::LD1RQ_D_IMM - 240 |
| {3523, 947, 4, 5 }, |
| // AArch64::LD1RQ_H_IMM - 241 |
| {3549, 952, 4, 5 }, |
| // AArch64::LD1RQ_W_IMM - 242 |
| {3575, 957, 4, 5 }, |
| // AArch64::LD1RSB_D_IMM - 243 |
| {3601, 962, 4, 5 }, |
| // AArch64::LD1RSB_H_IMM - 244 |
| {3627, 967, 4, 5 }, |
| // AArch64::LD1RSB_S_IMM - 245 |
| {3653, 972, 4, 5 }, |
| // AArch64::LD1RSH_D_IMM - 246 |
| {3679, 977, 4, 5 }, |
| // AArch64::LD1RSH_S_IMM - 247 |
| {3705, 982, 4, 5 }, |
| // AArch64::LD1RSW_IMM - 248 |
| {3731, 987, 4, 5 }, |
| // AArch64::LD1RW_D_IMM - 249 |
| {3757, 992, 4, 5 }, |
| // AArch64::LD1RW_IMM - 250 |
| {3782, 997, 4, 5 }, |
| // AArch64::LD1Rv16b_POST - 251 |
| {3807, 1002, 4, 5 }, |
| // AArch64::LD1Rv1d_POST - 252 |
| {3827, 1007, 4, 5 }, |
| // AArch64::LD1Rv2d_POST - 253 |
| {3847, 1012, 4, 5 }, |
| // AArch64::LD1Rv2s_POST - 254 |
| {3867, 1017, 4, 5 }, |
| // AArch64::LD1Rv4h_POST - 255 |
| {3887, 1022, 4, 5 }, |
| // AArch64::LD1Rv4s_POST - 256 |
| {3907, 1027, 4, 5 }, |
| // AArch64::LD1Rv8b_POST - 257 |
| {3927, 1032, 4, 5 }, |
| // AArch64::LD1Rv8h_POST - 258 |
| {3947, 1037, 4, 5 }, |
| // AArch64::LD1SB_D_IMM - 259 |
| {3967, 1042, 4, 5 }, |
| // AArch64::LD1SB_H_IMM - 260 |
| {3992, 1047, 4, 5 }, |
| // AArch64::LD1SB_S_IMM - 261 |
| {4017, 1052, 4, 5 }, |
| // AArch64::LD1SH_D_IMM - 262 |
| {4042, 1057, 4, 5 }, |
| // AArch64::LD1SH_S_IMM - 263 |
| {4067, 1062, 4, 5 }, |
| // AArch64::LD1SW_D_IMM - 264 |
| {4092, 1067, 4, 5 }, |
| // AArch64::LD1Threev16b_POST - 265 |
| {4117, 1072, 4, 5 }, |
| // AArch64::LD1Threev1d_POST - 266 |
| {4137, 1077, 4, 5 }, |
| // AArch64::LD1Threev2d_POST - 267 |
| {4157, 1082, 4, 5 }, |
| // AArch64::LD1Threev2s_POST - 268 |
| {4177, 1087, 4, 5 }, |
| // AArch64::LD1Threev4h_POST - 269 |
| {4197, 1092, 4, 5 }, |
| // AArch64::LD1Threev4s_POST - 270 |
| {4217, 1097, 4, 5 }, |
| // AArch64::LD1Threev8b_POST - 271 |
| {4237, 1102, 4, 5 }, |
| // AArch64::LD1Threev8h_POST - 272 |
| {4257, 1107, 4, 5 }, |
| // AArch64::LD1Twov16b_POST - 273 |
| {4277, 1112, 4, 5 }, |
| // AArch64::LD1Twov1d_POST - 274 |
| {4297, 1117, 4, 5 }, |
| // AArch64::LD1Twov2d_POST - 275 |
| {4317, 1122, 4, 5 }, |
| // AArch64::LD1Twov2s_POST - 276 |
| {4337, 1127, 4, 5 }, |
| // AArch64::LD1Twov4h_POST - 277 |
| {4357, 1132, 4, 5 }, |
| // AArch64::LD1Twov4s_POST - 278 |
| {4377, 1137, 4, 5 }, |
| // AArch64::LD1Twov8b_POST - 279 |
| {4397, 1142, 4, 5 }, |
| // AArch64::LD1Twov8h_POST - 280 |
| {4417, 1147, 4, 5 }, |
| // AArch64::LD1W_D_IMM - 281 |
| {4437, 1152, 4, 5 }, |
| // AArch64::LD1W_IMM - 282 |
| {4461, 1157, 4, 5 }, |
| // AArch64::LD1i16_POST - 283 |
| {4485, 1162, 6, 7 }, |
| // AArch64::LD1i32_POST - 284 |
| {4508, 1169, 6, 7 }, |
| // AArch64::LD1i64_POST - 285 |
| {4531, 1176, 6, 7 }, |
| // AArch64::LD1i8_POST - 286 |
| {4554, 1183, 6, 7 }, |
| // AArch64::LD2B_IMM - 287 |
| {4577, 1190, 4, 5 }, |
| // AArch64::LD2D_IMM - 288 |
| {4601, 1195, 4, 5 }, |
| // AArch64::LD2H_IMM - 289 |
| {4625, 1200, 4, 5 }, |
| // AArch64::LD2Rv16b_POST - 290 |
| {4649, 1205, 4, 5 }, |
| // AArch64::LD2Rv1d_POST - 291 |
| {4669, 1210, 4, 5 }, |
| // AArch64::LD2Rv2d_POST - 292 |
| {4690, 1215, 4, 5 }, |
| // AArch64::LD2Rv2s_POST - 293 |
| {4711, 1220, 4, 5 }, |
| // AArch64::LD2Rv4h_POST - 294 |
| {4731, 1225, 4, 5 }, |
| // AArch64::LD2Rv4s_POST - 295 |
| {4751, 1230, 4, 5 }, |
| // AArch64::LD2Rv8b_POST - 296 |
| {4771, 1235, 4, 5 }, |
| // AArch64::LD2Rv8h_POST - 297 |
| {4791, 1240, 4, 5 }, |
| // AArch64::LD2Twov16b_POST - 298 |
| {4811, 1245, 4, 5 }, |
| // AArch64::LD2Twov2d_POST - 299 |
| {4831, 1250, 4, 5 }, |
| // AArch64::LD2Twov2s_POST - 300 |
| {4851, 1255, 4, 5 }, |
| // AArch64::LD2Twov4h_POST - 301 |
| {4871, 1260, 4, 5 }, |
| // AArch64::LD2Twov4s_POST - 302 |
| {4891, 1265, 4, 5 }, |
| // AArch64::LD2Twov8b_POST - 303 |
| {4911, 1270, 4, 5 }, |
| // AArch64::LD2Twov8h_POST - 304 |
| {4931, 1275, 4, 5 }, |
| // AArch64::LD2W_IMM - 305 |
| {4951, 1280, 4, 5 }, |
| // AArch64::LD2i16_POST - 306 |
| {4975, 1285, 6, 7 }, |
| // AArch64::LD2i32_POST - 307 |
| {4998, 1292, 6, 7 }, |
| // AArch64::LD2i64_POST - 308 |
| {5021, 1299, 6, 7 }, |
| // AArch64::LD2i8_POST - 309 |
| {5045, 1306, 6, 7 }, |
| // AArch64::LD3B_IMM - 310 |
| {5068, 1313, 4, 5 }, |
| // AArch64::LD3D_IMM - 311 |
| {5092, 1318, 4, 5 }, |
| // AArch64::LD3H_IMM - 312 |
| {5116, 1323, 4, 5 }, |
| // AArch64::LD3Rv16b_POST - 313 |
| {5140, 1328, 4, 5 }, |
| // AArch64::LD3Rv1d_POST - 314 |
| {5160, 1333, 4, 5 }, |
| // AArch64::LD3Rv2d_POST - 315 |
| {5181, 1338, 4, 5 }, |
| // AArch64::LD3Rv2s_POST - 316 |
| {5202, 1343, 4, 5 }, |
| // AArch64::LD3Rv4h_POST - 317 |
| {5223, 1348, 4, 5 }, |
| // AArch64::LD3Rv4s_POST - 318 |
| {5243, 1353, 4, 5 }, |
| // AArch64::LD3Rv8b_POST - 319 |
| {5264, 1358, 4, 5 }, |
| // AArch64::LD3Rv8h_POST - 320 |
| {5284, 1363, 4, 5 }, |
| // AArch64::LD3Threev16b_POST - 321 |
| {5304, 1368, 4, 5 }, |
| // AArch64::LD3Threev2d_POST - 322 |
| {5324, 1373, 4, 5 }, |
| // AArch64::LD3Threev2s_POST - 323 |
| {5344, 1378, 4, 5 }, |
| // AArch64::LD3Threev4h_POST - 324 |
| {5364, 1383, 4, 5 }, |
| // AArch64::LD3Threev4s_POST - 325 |
| {5384, 1388, 4, 5 }, |
| // AArch64::LD3Threev8b_POST - 326 |
| {5404, 1393, 4, 5 }, |
| // AArch64::LD3Threev8h_POST - 327 |
| {5424, 1398, 4, 5 }, |
| // AArch64::LD3W_IMM - 328 |
| {5444, 1403, 4, 5 }, |
| // AArch64::LD3i16_POST - 329 |
| {5468, 1408, 6, 7 }, |
| // AArch64::LD3i32_POST - 330 |
| {5491, 1415, 6, 7 }, |
| // AArch64::LD3i64_POST - 331 |
| {5515, 1422, 6, 7 }, |
| // AArch64::LD3i8_POST - 332 |
| {5539, 1429, 6, 7 }, |
| // AArch64::LD4B_IMM - 333 |
| {5562, 1436, 4, 5 }, |
| // AArch64::LD4D_IMM - 334 |
| {5586, 1441, 4, 5 }, |
| // AArch64::LD4Fourv16b_POST - 335 |
| {5610, 1446, 4, 5 }, |
| // AArch64::LD4Fourv2d_POST - 336 |
| {5630, 1451, 4, 5 }, |
| // AArch64::LD4Fourv2s_POST - 337 |
| {5650, 1456, 4, 5 }, |
| // AArch64::LD4Fourv4h_POST - 338 |
| {5670, 1461, 4, 5 }, |
| // AArch64::LD4Fourv4s_POST - 339 |
| {5690, 1466, 4, 5 }, |
| // AArch64::LD4Fourv8b_POST - 340 |
| {5710, 1471, 4, 5 }, |
| // AArch64::LD4Fourv8h_POST - 341 |
| {5730, 1476, 4, 5 }, |
| // AArch64::LD4H_IMM - 342 |
| {5750, 1481, 4, 5 }, |
| // AArch64::LD4Rv16b_POST - 343 |
| {5774, 1486, 4, 5 }, |
| // AArch64::LD4Rv1d_POST - 344 |
| {5794, 1491, 4, 5 }, |
| // AArch64::LD4Rv2d_POST - 345 |
| {5815, 1496, 4, 5 }, |
| // AArch64::LD4Rv2s_POST - 346 |
| {5836, 1501, 4, 5 }, |
| // AArch64::LD4Rv4h_POST - 347 |
| {5857, 1506, 4, 5 }, |
| // AArch64::LD4Rv4s_POST - 348 |
| {5877, 1511, 4, 5 }, |
| // AArch64::LD4Rv8b_POST - 349 |
| {5898, 1516, 4, 5 }, |
| // AArch64::LD4Rv8h_POST - 350 |
| {5918, 1521, 4, 5 }, |
| // AArch64::LD4W_IMM - 351 |
| {5938, 1526, 4, 5 }, |
| // AArch64::LD4i16_POST - 352 |
| {5962, 1531, 6, 7 }, |
| // AArch64::LD4i32_POST - 353 |
| {5985, 1538, 6, 7 }, |
| // AArch64::LD4i64_POST - 354 |
| {6009, 1545, 6, 7 }, |
| // AArch64::LD4i8_POST - 355 |
| {6033, 1552, 6, 7 }, |
| // AArch64::LDADDB - 356 |
| {6056, 1559, 3, 4 }, |
| // AArch64::LDADDH - 357 |
| {6072, 1563, 3, 4 }, |
| // AArch64::LDADDLB - 358 |
| {6088, 1567, 3, 4 }, |
| // AArch64::LDADDLH - 359 |
| {6105, 1571, 3, 4 }, |
| // AArch64::LDADDLW - 360 |
| {6122, 1575, 3, 4 }, |
| // AArch64::LDADDLX - 361 |
| {6122, 1579, 3, 4 }, |
| // AArch64::LDADDW - 362 |
| {6138, 1583, 3, 4 }, |
| // AArch64::LDADDX - 363 |
| {6138, 1587, 3, 4 }, |
| // AArch64::LDAPURBi - 364 |
| {6153, 1591, 3, 4 }, |
| // AArch64::LDAPURHi - 365 |
| {6170, 1595, 3, 4 }, |
| // AArch64::LDAPURSBWi - 366 |
| {6187, 1599, 3, 4 }, |
| // AArch64::LDAPURSBXi - 367 |
| {6187, 1603, 3, 4 }, |
| // AArch64::LDAPURSHWi - 368 |
| {6205, 1607, 3, 4 }, |
| // AArch64::LDAPURSHXi - 369 |
| {6205, 1611, 3, 4 }, |
| // AArch64::LDAPURSWi - 370 |
| {6223, 1615, 3, 4 }, |
| // AArch64::LDAPURXi - 371 |
| {6241, 1619, 3, 4 }, |
| // AArch64::LDAPURi - 372 |
| {6241, 1623, 3, 4 }, |
| // AArch64::LDCLRB - 373 |
| {6257, 1627, 3, 4 }, |
| // AArch64::LDCLRH - 374 |
| {6273, 1631, 3, 4 }, |
| // AArch64::LDCLRLB - 375 |
| {6289, 1635, 3, 4 }, |
| // AArch64::LDCLRLH - 376 |
| {6306, 1639, 3, 4 }, |
| // AArch64::LDCLRLW - 377 |
| {6323, 1643, 3, 4 }, |
| // AArch64::LDCLRLX - 378 |
| {6323, 1647, 3, 4 }, |
| // AArch64::LDCLRW - 379 |
| {6339, 1651, 3, 4 }, |
| // AArch64::LDCLRX - 380 |
| {6339, 1655, 3, 4 }, |
| // AArch64::LDEORB - 381 |
| {6354, 1659, 3, 4 }, |
| // AArch64::LDEORH - 382 |
| {6370, 1663, 3, 4 }, |
| // AArch64::LDEORLB - 383 |
| {6386, 1667, 3, 4 }, |
| // AArch64::LDEORLH - 384 |
| {6403, 1671, 3, 4 }, |
| // AArch64::LDEORLW - 385 |
| {6420, 1675, 3, 4 }, |
| // AArch64::LDEORLX - 386 |
| {6420, 1679, 3, 4 }, |
| // AArch64::LDEORW - 387 |
| {6436, 1683, 3, 4 }, |
| // AArch64::LDEORX - 388 |
| {6436, 1687, 3, 4 }, |
| // AArch64::LDFF1B_D_REAL - 389 |
| {6451, 1691, 4, 5 }, |
| // AArch64::LDFF1B_H_REAL - 390 |
| {6477, 1696, 4, 5 }, |
| // AArch64::LDFF1B_REAL - 391 |
| {6503, 1701, 4, 5 }, |
| // AArch64::LDFF1B_S_REAL - 392 |
| {6529, 1706, 4, 5 }, |
| // AArch64::LDFF1D_REAL - 393 |
| {6555, 1711, 4, 5 }, |
| // AArch64::LDFF1H_D_REAL - 394 |
| {6581, 1716, 4, 5 }, |
| // AArch64::LDFF1H_REAL - 395 |
| {6607, 1721, 4, 5 }, |
| // AArch64::LDFF1H_S_REAL - 396 |
| {6633, 1726, 4, 5 }, |
| // AArch64::LDFF1SB_D_REAL - 397 |
| {6659, 1731, 4, 5 }, |
| // AArch64::LDFF1SB_H_REAL - 398 |
| {6686, 1736, 4, 5 }, |
| // AArch64::LDFF1SB_S_REAL - 399 |
| {6713, 1741, 4, 5 }, |
| // AArch64::LDFF1SH_D_REAL - 400 |
| {6740, 1746, 4, 5 }, |
| // AArch64::LDFF1SH_S_REAL - 401 |
| {6767, 1751, 4, 5 }, |
| // AArch64::LDFF1SW_D_REAL - 402 |
| {6794, 1756, 4, 5 }, |
| // AArch64::LDFF1W_D_REAL - 403 |
| {6821, 1761, 4, 5 }, |
| // AArch64::LDFF1W_REAL - 404 |
| {6847, 1766, 4, 5 }, |
| // AArch64::LDG - 405 |
| {6873, 1771, 4, 5 }, |
| // AArch64::LDNF1B_D_IMM - 406 |
| {6886, 1776, 4, 5 }, |
| // AArch64::LDNF1B_H_IMM - 407 |
| {6912, 1781, 4, 5 }, |
| // AArch64::LDNF1B_IMM - 408 |
| {6938, 1786, 4, 5 }, |
| // AArch64::LDNF1B_S_IMM - 409 |
| {6964, 1791, 4, 5 }, |
| // AArch64::LDNF1D_IMM - 410 |
| {6990, 1796, 4, 5 }, |
| // AArch64::LDNF1H_D_IMM - 411 |
| {7016, 1801, 4, 5 }, |
| // AArch64::LDNF1H_IMM - 412 |
| {7042, 1806, 4, 5 }, |
| // AArch64::LDNF1H_S_IMM - 413 |
| {7068, 1811, 4, 5 }, |
| // AArch64::LDNF1SB_D_IMM - 414 |
| {7094, 1816, 4, 5 }, |
| // AArch64::LDNF1SB_H_IMM - 415 |
| {7121, 1821, 4, 5 }, |
| // AArch64::LDNF1SB_S_IMM - 416 |
| {7148, 1826, 4, 5 }, |
| // AArch64::LDNF1SH_D_IMM - 417 |
| {7175, 1831, 4, 5 }, |
| // AArch64::LDNF1SH_S_IMM - 418 |
| {7202, 1836, 4, 5 }, |
| // AArch64::LDNF1SW_D_IMM - 419 |
| {7229, 1841, 4, 5 }, |
| // AArch64::LDNF1W_D_IMM - 420 |
| {7256, 1846, 4, 5 }, |
| // AArch64::LDNF1W_IMM - 421 |
| {7282, 1851, 4, 5 }, |
| // AArch64::LDNPDi - 422 |
| {7308, 1856, 4, 4 }, |
| // AArch64::LDNPQi - 423 |
| {7308, 1860, 4, 4 }, |
| // AArch64::LDNPSi - 424 |
| {7308, 1864, 4, 4 }, |
| // AArch64::LDNPWi - 425 |
| {7308, 1868, 4, 4 }, |
| // AArch64::LDNPXi - 426 |
| {7308, 1872, 4, 4 }, |
| // AArch64::LDNT1B_ZRI - 427 |
| {7326, 1876, 4, 5 }, |
| // AArch64::LDNT1B_ZZR_D_REAL - 428 |
| {7352, 1881, 4, 5 }, |
| // AArch64::LDNT1B_ZZR_S_REAL - 429 |
| {7380, 1886, 4, 5 }, |
| // AArch64::LDNT1D_ZRI - 430 |
| {7408, 1891, 4, 5 }, |
| // AArch64::LDNT1D_ZZR_D_REAL - 431 |
| {7434, 1896, 4, 5 }, |
| // AArch64::LDNT1H_ZRI - 432 |
| {7462, 1901, 4, 5 }, |
| // AArch64::LDNT1H_ZZR_D_REAL - 433 |
| {7488, 1906, 4, 5 }, |
| // AArch64::LDNT1H_ZZR_S_REAL - 434 |
| {7516, 1911, 4, 5 }, |
| // AArch64::LDNT1SB_ZZR_D_REAL - 435 |
| {7544, 1916, 4, 5 }, |
| // AArch64::LDNT1SB_ZZR_S_REAL - 436 |
| {7573, 1921, 4, 5 }, |
| // AArch64::LDNT1SH_ZZR_D_REAL - 437 |
| {7602, 1926, 4, 5 }, |
| // AArch64::LDNT1SH_ZZR_S_REAL - 438 |
| {7631, 1931, 4, 5 }, |
| // AArch64::LDNT1SW_ZZR_D_REAL - 439 |
| {7660, 1936, 4, 5 }, |
| // AArch64::LDNT1W_ZRI - 440 |
| {7689, 1941, 4, 5 }, |
| // AArch64::LDNT1W_ZZR_D_REAL - 441 |
| {7715, 1946, 4, 5 }, |
| // AArch64::LDNT1W_ZZR_S_REAL - 442 |
| {7743, 1951, 4, 5 }, |
| // AArch64::LDPDi - 443 |
| {7771, 1956, 4, 4 }, |
| // AArch64::LDPQi - 444 |
| {7771, 1960, 4, 4 }, |
| // AArch64::LDPSWi - 445 |
| {7788, 1964, 4, 4 }, |
| // AArch64::LDPSi - 446 |
| {7771, 1968, 4, 4 }, |
| // AArch64::LDPWi - 447 |
| {7771, 1972, 4, 4 }, |
| // AArch64::LDPXi - 448 |
| {7771, 1976, 4, 4 }, |
| // AArch64::LDRAAindexed - 449 |
| {7807, 1980, 3, 4 }, |
| // AArch64::LDRABindexed - 450 |
| {7822, 1984, 3, 4 }, |
| // AArch64::LDRBBroX - 451 |
| {7837, 1988, 5, 5 }, |
| // AArch64::LDRBBui - 452 |
| {7855, 1993, 3, 3 }, |
| // AArch64::LDRBroX - 453 |
| {7869, 1996, 5, 5 }, |
| // AArch64::LDRBui - 454 |
| {7886, 2001, 3, 3 }, |
| // AArch64::LDRDroX - 455 |
| {7869, 2004, 5, 5 }, |
| // AArch64::LDRDui - 456 |
| {7886, 2009, 3, 3 }, |
| // AArch64::LDRHHroX - 457 |
| {7899, 2012, 5, 5 }, |
| // AArch64::LDRHHui - 458 |
| {7917, 2017, 3, 3 }, |
| // AArch64::LDRHroX - 459 |
| {7869, 2020, 5, 5 }, |
| // AArch64::LDRHui - 460 |
| {7886, 2025, 3, 3 }, |
| // AArch64::LDRQroX - 461 |
| {7869, 2028, 5, 5 }, |
| // AArch64::LDRQui - 462 |
| {7886, 2033, 3, 3 }, |
| // AArch64::LDRSBWroX - 463 |
| {7931, 2036, 5, 5 }, |
| // AArch64::LDRSBWui - 464 |
| {7950, 2041, 3, 3 }, |
| // AArch64::LDRSBXroX - 465 |
| {7931, 2044, 5, 5 }, |
| // AArch64::LDRSBXui - 466 |
| {7950, 2049, 3, 3 }, |
| // AArch64::LDRSHWroX - 467 |
| {7965, 2052, 5, 5 }, |
| // AArch64::LDRSHWui - 468 |
| {7984, 2057, 3, 3 }, |
| // AArch64::LDRSHXroX - 469 |
| {7965, 2060, 5, 5 }, |
| // AArch64::LDRSHXui - 470 |
| {7984, 2065, 3, 3 }, |
| // AArch64::LDRSWroX - 471 |
| {7999, 2068, 5, 5 }, |
| // AArch64::LDRSWui - 472 |
| {8018, 2073, 3, 3 }, |
| // AArch64::LDRSroX - 473 |
| {7869, 2076, 5, 5 }, |
| // AArch64::LDRSui - 474 |
| {7886, 2081, 3, 3 }, |
| // AArch64::LDRWroX - 475 |
| {7869, 2084, 5, 5 }, |
| // AArch64::LDRWui - 476 |
| {7886, 2089, 3, 3 }, |
| // AArch64::LDRXroX - 477 |
| {7869, 2092, 5, 5 }, |
| // AArch64::LDRXui - 478 |
| {7886, 2097, 3, 3 }, |
| // AArch64::LDR_PXI - 479 |
| {8033, 2100, 3, 4 }, |
| // AArch64::LDR_ZXI - 480 |
| {8033, 2104, 3, 4 }, |
| // AArch64::LDSETB - 481 |
| {8048, 2108, 3, 4 }, |
| // AArch64::LDSETH - 482 |
| {8064, 2112, 3, 4 }, |
| // AArch64::LDSETLB - 483 |
| {8080, 2116, 3, 4 }, |
| // AArch64::LDSETLH - 484 |
| {8097, 2120, 3, 4 }, |
| // AArch64::LDSETLW - 485 |
| {8114, 2124, 3, 4 }, |
| // AArch64::LDSETLX - 486 |
| {8114, 2128, 3, 4 }, |
| // AArch64::LDSETW - 487 |
| {8130, 2132, 3, 4 }, |
| // AArch64::LDSETX - 488 |
| {8130, 2136, 3, 4 }, |
| // AArch64::LDSMAXB - 489 |
| {8145, 2140, 3, 4 }, |
| // AArch64::LDSMAXH - 490 |
| {8162, 2144, 3, 4 }, |
| // AArch64::LDSMAXLB - 491 |
| {8179, 2148, 3, 4 }, |
| // AArch64::LDSMAXLH - 492 |
| {8197, 2152, 3, 4 }, |
| // AArch64::LDSMAXLW - 493 |
| {8215, 2156, 3, 4 }, |
| // AArch64::LDSMAXLX - 494 |
| {8215, 2160, 3, 4 }, |
| // AArch64::LDSMAXW - 495 |
| {8232, 2164, 3, 4 }, |
| // AArch64::LDSMAXX - 496 |
| {8232, 2168, 3, 4 }, |
| // AArch64::LDSMINB - 497 |
| {8248, 2172, 3, 4 }, |
| // AArch64::LDSMINH - 498 |
| {8265, 2176, 3, 4 }, |
| // AArch64::LDSMINLB - 499 |
| {8282, 2180, 3, 4 }, |
| // AArch64::LDSMINLH - 500 |
| {8300, 2184, 3, 4 }, |
| // AArch64::LDSMINLW - 501 |
| {8318, 2188, 3, 4 }, |
| // AArch64::LDSMINLX - 502 |
| {8318, 2192, 3, 4 }, |
| // AArch64::LDSMINW - 503 |
| {8335, 2196, 3, 4 }, |
| // AArch64::LDSMINX - 504 |
| {8335, 2200, 3, 4 }, |
| // AArch64::LDTRBi - 505 |
| {8351, 2204, 3, 3 }, |
| // AArch64::LDTRHi - 506 |
| {8366, 2207, 3, 3 }, |
| // AArch64::LDTRSBWi - 507 |
| {8381, 2210, 3, 3 }, |
| // AArch64::LDTRSBXi - 508 |
| {8381, 2213, 3, 3 }, |
| // AArch64::LDTRSHWi - 509 |
| {8397, 2216, 3, 3 }, |
| // AArch64::LDTRSHXi - 510 |
| {8397, 2219, 3, 3 }, |
| // AArch64::LDTRSWi - 511 |
| {8413, 2222, 3, 3 }, |
| // AArch64::LDTRWi - 512 |
| {8429, 2225, 3, 3 }, |
| // AArch64::LDTRXi - 513 |
| {8429, 2228, 3, 3 }, |
| // AArch64::LDUMAXB - 514 |
| {8443, 2231, 3, 4 }, |
| // AArch64::LDUMAXH - 515 |
| {8460, 2235, 3, 4 }, |
| // AArch64::LDUMAXLB - 516 |
| {8477, 2239, 3, 4 }, |
| // AArch64::LDUMAXLH - 517 |
| {8495, 2243, 3, 4 }, |
| // AArch64::LDUMAXLW - 518 |
| {8513, 2247, 3, 4 }, |
| // AArch64::LDUMAXLX - 519 |
| {8513, 2251, 3, 4 }, |
| // AArch64::LDUMAXW - 520 |
| {8530, 2255, 3, 4 }, |
| // AArch64::LDUMAXX - 521 |
| {8530, 2259, 3, 4 }, |
| // AArch64::LDUMINB - 522 |
| {8546, 2263, 3, 4 }, |
| // AArch64::LDUMINH - 523 |
| {8563, 2267, 3, 4 }, |
| // AArch64::LDUMINLB - 524 |
| {8580, 2271, 3, 4 }, |
| // AArch64::LDUMINLH - 525 |
| {8598, 2275, 3, 4 }, |
| // AArch64::LDUMINLW - 526 |
| {8616, 2279, 3, 4 }, |
| // AArch64::LDUMINLX - 527 |
| {8616, 2283, 3, 4 }, |
| // AArch64::LDUMINW - 528 |
| {8633, 2287, 3, 4 }, |
| // AArch64::LDUMINX - 529 |
| {8633, 2291, 3, 4 }, |
| // AArch64::LDURBBi - 530 |
| {8649, 2295, 3, 3 }, |
| // AArch64::LDURBi - 531 |
| {8664, 2298, 3, 3 }, |
| // AArch64::LDURDi - 532 |
| {8664, 2301, 3, 3 }, |
| // AArch64::LDURHHi - 533 |
| {8678, 2304, 3, 3 }, |
| // AArch64::LDURHi - 534 |
| {8664, 2307, 3, 3 }, |
| // AArch64::LDURQi - 535 |
| {8664, 2310, 3, 3 }, |
| // AArch64::LDURSBWi - 536 |
| {8693, 2313, 3, 3 }, |
| // AArch64::LDURSBXi - 537 |
| {8693, 2316, 3, 3 }, |
| // AArch64::LDURSHWi - 538 |
| {8709, 2319, 3, 3 }, |
| // AArch64::LDURSHXi - 539 |
| {8709, 2322, 3, 3 }, |
| // AArch64::LDURSWi - 540 |
| {8725, 2325, 3, 3 }, |
| // AArch64::LDURSi - 541 |
| {8664, 2328, 3, 3 }, |
| // AArch64::LDURWi - 542 |
| {8664, 2331, 3, 3 }, |
| // AArch64::LDURXi - 543 |
| {8664, 2334, 3, 3 }, |
| // AArch64::MADDWrrr - 544 |
| {8741, 2337, 4, 4 }, |
| // AArch64::MADDXrrr - 545 |
| {8741, 2341, 4, 4 }, |
| // AArch64::MSUBWrrr - 546 |
| {8756, 2345, 4, 4 }, |
| // AArch64::MSUBXrrr - 547 |
| {8756, 2349, 4, 4 }, |
| // AArch64::NOTv16i8 - 548 |
| {8772, 2353, 2, 2 }, |
| // AArch64::NOTv8i8 - 549 |
| {8795, 2355, 2, 2 }, |
| // AArch64::ORNWrs - 550 |
| {8816, 2357, 4, 4 }, |
| {8827, 2361, 4, 3 }, |
| {8842, 2364, 4, 4 }, |
| // AArch64::ORNXrs - 553 |
| {8816, 2368, 4, 4 }, |
| {8827, 2372, 4, 3 }, |
| {8842, 2375, 4, 4 }, |
| // AArch64::ORRS_PPzPP - 556 |
| {8857, 2379, 4, 5 }, |
| // AArch64::ORRWrs - 557 |
| {8873, 2384, 4, 4 }, |
| {8884, 2388, 4, 4 }, |
| // AArch64::ORRXrs - 559 |
| {8873, 2392, 4, 4 }, |
| {8884, 2396, 4, 4 }, |
| // AArch64::ORR_PPzPP - 561 |
| {8899, 2400, 4, 5 }, |
| // AArch64::ORR_ZI - 562 |
| {8914, 2405, 3, 4 }, |
| {8935, 2409, 3, 4 }, |
| {8956, 2413, 3, 4 }, |
| // AArch64::ORR_ZZZ - 565 |
| {8977, 2417, 3, 4 }, |
| // AArch64::ORRv16i8 - 566 |
| {8992, 2421, 3, 3 }, |
| // AArch64::ORRv8i8 - 567 |
| {9015, 2424, 3, 3 }, |
| // AArch64::PACIA1716 - 568 |
| {9036, 2427, 0, 1 }, |
| // AArch64::PACIASP - 569 |
| {9046, 2428, 0, 1 }, |
| // AArch64::PACIAZ - 570 |
| {9054, 2429, 0, 1 }, |
| // AArch64::PACIB1716 - 571 |
| {9061, 2430, 0, 1 }, |
| // AArch64::PACIBSP - 572 |
| {9071, 2431, 0, 1 }, |
| // AArch64::PACIBZ - 573 |
| {9079, 2432, 0, 1 }, |
| // AArch64::PRFB_D_PZI - 574 |
| {9086, 2433, 4, 5 }, |
| // AArch64::PRFB_PRI - 575 |
| {9110, 2438, 4, 5 }, |
| // AArch64::PRFB_S_PZI - 576 |
| {9132, 2443, 4, 5 }, |
| // AArch64::PRFD_D_PZI - 577 |
| {9156, 2448, 4, 5 }, |
| // AArch64::PRFD_PRI - 578 |
| {9180, 2453, 4, 5 }, |
| // AArch64::PRFD_S_PZI - 579 |
| {9202, 2458, 4, 5 }, |
| // AArch64::PRFH_D_PZI - 580 |
| {9226, 2463, 4, 5 }, |
| // AArch64::PRFH_PRI - 581 |
| {9250, 2468, 4, 5 }, |
| // AArch64::PRFH_S_PZI - 582 |
| {9272, 2473, 4, 5 }, |
| // AArch64::PRFMroX - 583 |
| {9296, 2478, 5, 5 }, |
| // AArch64::PRFMui - 584 |
| {9316, 2483, 3, 3 }, |
| // AArch64::PRFUMi - 585 |
| {9332, 2486, 3, 3 }, |
| // AArch64::PRFW_D_PZI - 586 |
| {9349, 2489, 4, 5 }, |
| // AArch64::PRFW_PRI - 587 |
| {9373, 2494, 4, 5 }, |
| // AArch64::PRFW_S_PZI - 588 |
| {9395, 2499, 4, 5 }, |
| // AArch64::PTRUES_B - 589 |
| {9419, 2504, 2, 3 }, |
| // AArch64::PTRUES_D - 590 |
| {9431, 2507, 2, 3 }, |
| // AArch64::PTRUES_H - 591 |
| {9443, 2510, 2, 3 }, |
| // AArch64::PTRUES_S - 592 |
| {9455, 2513, 2, 3 }, |
| // AArch64::PTRUE_B - 593 |
| {9467, 2516, 2, 3 }, |
| // AArch64::PTRUE_D - 594 |
| {9478, 2519, 2, 3 }, |
| // AArch64::PTRUE_H - 595 |
| {9489, 2522, 2, 3 }, |
| // AArch64::PTRUE_S - 596 |
| {9500, 2525, 2, 3 }, |
| // AArch64::RET - 597 |
| {9511, 2528, 1, 1 }, |
| // AArch64::SBCSWr - 598 |
| {9515, 2529, 3, 3 }, |
| // AArch64::SBCSXr - 599 |
| {9515, 2532, 3, 3 }, |
| // AArch64::SBCWr - 600 |
| {9527, 2535, 3, 3 }, |
| // AArch64::SBCXr - 601 |
| {9527, 2538, 3, 3 }, |
| // AArch64::SBFMWri - 602 |
| {9538, 2541, 4, 4 }, |
| {9553, 2545, 4, 4 }, |
| {9565, 2549, 4, 4 }, |
| // AArch64::SBFMXri - 605 |
| {9538, 2553, 4, 4 }, |
| {9553, 2557, 4, 4 }, |
| {9565, 2561, 4, 4 }, |
| {9577, 2565, 4, 4 }, |
| // AArch64::SEL_PPPP - 609 |
| {9589, 2569, 4, 5 }, |
| // AArch64::SEL_ZPZZ_B - 610 |
| {9589, 2574, 4, 5 }, |
| // AArch64::SEL_ZPZZ_D - 611 |
| {9612, 2579, 4, 5 }, |
| // AArch64::SEL_ZPZZ_H - 612 |
| {9635, 2584, 4, 5 }, |
| // AArch64::SEL_ZPZZ_S - 613 |
| {9658, 2589, 4, 5 }, |
| // AArch64::SMADDLrrr - 614 |
| {9681, 2594, 4, 4 }, |
| // AArch64::SMSUBLrrr - 615 |
| {9698, 2598, 4, 4 }, |
| // AArch64::SQDECB_XPiI - 616 |
| {9716, 2602, 4, 5 }, |
| {9726, 2607, 4, 5 }, |
| // AArch64::SQDECB_XPiWdI - 618 |
| {9742, 2612, 4, 5 }, |
| {9758, 2617, 4, 5 }, |
| // AArch64::SQDECD_XPiI - 620 |
| {9780, 2622, 4, 5 }, |
| {9790, 2627, 4, 5 }, |
| // AArch64::SQDECD_XPiWdI - 622 |
| {9806, 2632, 4, 5 }, |
| {9822, 2637, 4, 5 }, |
| // AArch64::SQDECD_ZPiI - 624 |
| {9844, 2642, 4, 5 }, |
| {9856, 2647, 4, 5 }, |
| // AArch64::SQDECH_XPiI - 626 |
| {9874, 2652, 4, 5 }, |
| {9884, 2657, 4, 5 }, |
| // AArch64::SQDECH_XPiWdI - 628 |
| {9900, 2662, 4, 5 }, |
| {9916, 2667, 4, 5 }, |
| // AArch64::SQDECH_ZPiI - 630 |
| {9938, 2672, 4, 5 }, |
| {9950, 2677, 4, 5 }, |
| // AArch64::SQDECW_XPiI - 632 |
| {9968, 2682, 4, 5 }, |
| {9978, 2687, 4, 5 }, |
| // AArch64::SQDECW_XPiWdI - 634 |
| {9994, 2692, 4, 5 }, |
| {10010, 2697, 4, 5 }, |
| // AArch64::SQDECW_ZPiI - 636 |
| {10032, 2702, 4, 5 }, |
| {10044, 2707, 4, 5 }, |
| // AArch64::SQINCB_XPiI - 638 |
| {10062, 2712, 4, 5 }, |
| {10072, 2717, 4, 5 }, |
| // AArch64::SQINCB_XPiWdI - 640 |
| {10088, 2722, 4, 5 }, |
| {10104, 2727, 4, 5 }, |
| // AArch64::SQINCD_XPiI - 642 |
| {10126, 2732, 4, 5 }, |
| {10136, 2737, 4, 5 }, |
| // AArch64::SQINCD_XPiWdI - 644 |
| {10152, 2742, 4, 5 }, |
| {10168, 2747, 4, 5 }, |
| // AArch64::SQINCD_ZPiI - 646 |
| {10190, 2752, 4, 5 }, |
| {10202, 2757, 4, 5 }, |
| // AArch64::SQINCH_XPiI - 648 |
| {10220, 2762, 4, 5 }, |
| {10230, 2767, 4, 5 }, |
| // AArch64::SQINCH_XPiWdI - 650 |
| {10246, 2772, 4, 5 }, |
| {10262, 2777, 4, 5 }, |
| // AArch64::SQINCH_ZPiI - 652 |
| {10284, 2782, 4, 5 }, |
| {10296, 2787, 4, 5 }, |
| // AArch64::SQINCW_XPiI - 654 |
| {10314, 2792, 4, 5 }, |
| {10324, 2797, 4, 5 }, |
| // AArch64::SQINCW_XPiWdI - 656 |
| {10340, 2802, 4, 5 }, |
| {10356, 2807, 4, 5 }, |
| // AArch64::SQINCW_ZPiI - 658 |
| {10378, 2812, 4, 5 }, |
| {10390, 2817, 4, 5 }, |
| // AArch64::SST1B_D_IMM - 660 |
| {10408, 2822, 4, 5 }, |
| // AArch64::SST1B_S_IMM - 661 |
| {10432, 2827, 4, 5 }, |
| // AArch64::SST1D_IMM - 662 |
| {10456, 2832, 4, 5 }, |
| // AArch64::SST1H_D_IMM - 663 |
| {10480, 2837, 4, 5 }, |
| // AArch64::SST1H_S_IMM - 664 |
| {10504, 2842, 4, 5 }, |
| // AArch64::SST1W_D_IMM - 665 |
| {10528, 2847, 4, 5 }, |
| // AArch64::SST1W_IMM - 666 |
| {10552, 2852, 4, 5 }, |
| // AArch64::ST1B_D_IMM - 667 |
| {10576, 2857, 4, 5 }, |
| // AArch64::ST1B_H_IMM - 668 |
| {10598, 2862, 4, 5 }, |
| // AArch64::ST1B_IMM - 669 |
| {10620, 2867, 4, 5 }, |
| // AArch64::ST1B_S_IMM - 670 |
| {10642, 2872, 4, 5 }, |
| // AArch64::ST1D_IMM - 671 |
| {10664, 2877, 4, 5 }, |
| // AArch64::ST1Fourv16b_POST - 672 |
| {10686, 2882, 4, 5 }, |
| // AArch64::ST1Fourv1d_POST - 673 |
| {10706, 2887, 4, 5 }, |
| // AArch64::ST1Fourv2d_POST - 674 |
| {10726, 2892, 4, 5 }, |
| // AArch64::ST1Fourv2s_POST - 675 |
| {10746, 2897, 4, 5 }, |
| // AArch64::ST1Fourv4h_POST - 676 |
| {10766, 2902, 4, 5 }, |
| // AArch64::ST1Fourv4s_POST - 677 |
| {10786, 2907, 4, 5 }, |
| // AArch64::ST1Fourv8b_POST - 678 |
| {10806, 2912, 4, 5 }, |
| // AArch64::ST1Fourv8h_POST - 679 |
| {10826, 2917, 4, 5 }, |
| // AArch64::ST1H_D_IMM - 680 |
| {10846, 2922, 4, 5 }, |
| // AArch64::ST1H_IMM - 681 |
| {10868, 2927, 4, 5 }, |
| // AArch64::ST1H_S_IMM - 682 |
| {10890, 2932, 4, 5 }, |
| // AArch64::ST1Onev16b_POST - 683 |
| {10912, 2937, 4, 5 }, |
| // AArch64::ST1Onev1d_POST - 684 |
| {10932, 2942, 4, 5 }, |
| // AArch64::ST1Onev2d_POST - 685 |
| {10951, 2947, 4, 5 }, |
| // AArch64::ST1Onev2s_POST - 686 |
| {10971, 2952, 4, 5 }, |
| // AArch64::ST1Onev4h_POST - 687 |
| {10990, 2957, 4, 5 }, |
| // AArch64::ST1Onev4s_POST - 688 |
| {11009, 2962, 4, 5 }, |
| // AArch64::ST1Onev8b_POST - 689 |
| {11029, 2967, 4, 5 }, |
| // AArch64::ST1Onev8h_POST - 690 |
| {11048, 2972, 4, 5 }, |
| // AArch64::ST1Threev16b_POST - 691 |
| {11068, 2977, 4, 5 }, |
| // AArch64::ST1Threev1d_POST - 692 |
| {11088, 2982, 4, 5 }, |
| // AArch64::ST1Threev2d_POST - 693 |
| {11108, 2987, 4, 5 }, |
| // AArch64::ST1Threev2s_POST - 694 |
| {11128, 2992, 4, 5 }, |
| // AArch64::ST1Threev4h_POST - 695 |
| {11148, 2997, 4, 5 }, |
| // AArch64::ST1Threev4s_POST - 696 |
| {11168, 3002, 4, 5 }, |
| // AArch64::ST1Threev8b_POST - 697 |
| {11188, 3007, 4, 5 }, |
| // AArch64::ST1Threev8h_POST - 698 |
| {11208, 3012, 4, 5 }, |
| // AArch64::ST1Twov16b_POST - 699 |
| {11228, 3017, 4, 5 }, |
| // AArch64::ST1Twov1d_POST - 700 |
| {11248, 3022, 4, 5 }, |
| // AArch64::ST1Twov2d_POST - 701 |
| {11268, 3027, 4, 5 }, |
| // AArch64::ST1Twov2s_POST - 702 |
| {11288, 3032, 4, 5 }, |
| // AArch64::ST1Twov4h_POST - 703 |
| {11308, 3037, 4, 5 }, |
| // AArch64::ST1Twov4s_POST - 704 |
| {11328, 3042, 4, 5 }, |
| // AArch64::ST1Twov8b_POST - 705 |
| {11348, 3047, 4, 5 }, |
| // AArch64::ST1Twov8h_POST - 706 |
| {11368, 3052, 4, 5 }, |
| // AArch64::ST1W_D_IMM - 707 |
| {11388, 3057, 4, 5 }, |
| // AArch64::ST1W_IMM - 708 |
| {11410, 3062, 4, 5 }, |
| // AArch64::ST1i16_POST - 709 |
| {11432, 3067, 5, 6 }, |
| // AArch64::ST1i32_POST - 710 |
| {11455, 3073, 5, 6 }, |
| // AArch64::ST1i64_POST - 711 |
| {11478, 3079, 5, 6 }, |
| // AArch64::ST1i8_POST - 712 |
| {11501, 3085, 5, 6 }, |
| // AArch64::ST2B_IMM - 713 |
| {11524, 3091, 4, 5 }, |
| // AArch64::ST2D_IMM - 714 |
| {11546, 3096, 4, 5 }, |
| // AArch64::ST2GOffset - 715 |
| {11568, 3101, 3, 4 }, |
| // AArch64::ST2H_IMM - 716 |
| {11582, 3105, 4, 5 }, |
| // AArch64::ST2Twov16b_POST - 717 |
| {11604, 3110, 4, 5 }, |
| // AArch64::ST2Twov2d_POST - 718 |
| {11624, 3115, 4, 5 }, |
| // AArch64::ST2Twov2s_POST - 719 |
| {11644, 3120, 4, 5 }, |
| // AArch64::ST2Twov4h_POST - 720 |
| {11664, 3125, 4, 5 }, |
| // AArch64::ST2Twov4s_POST - 721 |
| {11684, 3130, 4, 5 }, |
| // AArch64::ST2Twov8b_POST - 722 |
| {11704, 3135, 4, 5 }, |
| // AArch64::ST2Twov8h_POST - 723 |
| {11724, 3140, 4, 5 }, |
| // AArch64::ST2W_IMM - 724 |
| {11744, 3145, 4, 5 }, |
| // AArch64::ST2i16_POST - 725 |
| {11766, 3150, 5, 6 }, |
| // AArch64::ST2i32_POST - 726 |
| {11789, 3156, 5, 6 }, |
| // AArch64::ST2i64_POST - 727 |
| {11812, 3162, 5, 6 }, |
| // AArch64::ST2i8_POST - 728 |
| {11836, 3168, 5, 6 }, |
| // AArch64::ST3B_IMM - 729 |
| {11859, 3174, 4, 5 }, |
| // AArch64::ST3D_IMM - 730 |
| {11881, 3179, 4, 5 }, |
| // AArch64::ST3H_IMM - 731 |
| {11903, 3184, 4, 5 }, |
| // AArch64::ST3Threev16b_POST - 732 |
| {11925, 3189, 4, 5 }, |
| // AArch64::ST3Threev2d_POST - 733 |
| {11945, 3194, 4, 5 }, |
| // AArch64::ST3Threev2s_POST - 734 |
| {11965, 3199, 4, 5 }, |
| // AArch64::ST3Threev4h_POST - 735 |
| {11985, 3204, 4, 5 }, |
| // AArch64::ST3Threev4s_POST - 736 |
| {12005, 3209, 4, 5 }, |
| // AArch64::ST3Threev8b_POST - 737 |
| {12025, 3214, 4, 5 }, |
| // AArch64::ST3Threev8h_POST - 738 |
| {12045, 3219, 4, 5 }, |
| // AArch64::ST3W_IMM - 739 |
| {12065, 3224, 4, 5 }, |
| // AArch64::ST3i16_POST - 740 |
| {12087, 3229, 5, 6 }, |
| // AArch64::ST3i32_POST - 741 |
| {12110, 3235, 5, 6 }, |
| // AArch64::ST3i64_POST - 742 |
| {12134, 3241, 5, 6 }, |
| // AArch64::ST3i8_POST - 743 |
| {12158, 3247, 5, 6 }, |
| // AArch64::ST4B_IMM - 744 |
| {12181, 3253, 4, 5 }, |
| // AArch64::ST4D_IMM - 745 |
| {12203, 3258, 4, 5 }, |
| // AArch64::ST4Fourv16b_POST - 746 |
| {12225, 3263, 4, 5 }, |
| // AArch64::ST4Fourv2d_POST - 747 |
| {12245, 3268, 4, 5 }, |
| // AArch64::ST4Fourv2s_POST - 748 |
| {12265, 3273, 4, 5 }, |
| // AArch64::ST4Fourv4h_POST - 749 |
| {12285, 3278, 4, 5 }, |
| // AArch64::ST4Fourv4s_POST - 750 |
| {12305, 3283, 4, 5 }, |
| // AArch64::ST4Fourv8b_POST - 751 |
| {12325, 3288, 4, 5 }, |
| // AArch64::ST4Fourv8h_POST - 752 |
| {12345, 3293, 4, 5 }, |
| // AArch64::ST4H_IMM - 753 |
| {12365, 3298, 4, 5 }, |
| // AArch64::ST4W_IMM - 754 |
| {12387, 3303, 4, 5 }, |
| // AArch64::ST4i16_POST - 755 |
| {12409, 3308, 5, 6 }, |
| // AArch64::ST4i32_POST - 756 |
| {12432, 3314, 5, 6 }, |
| // AArch64::ST4i64_POST - 757 |
| {12456, 3320, 5, 6 }, |
| // AArch64::ST4i8_POST - 758 |
| {12480, 3326, 5, 6 }, |
| // AArch64::STGOffset - 759 |
| {12503, 3332, 3, 4 }, |
| // AArch64::STGPi - 760 |
| {12516, 3336, 4, 5 }, |
| // AArch64::STLURBi - 761 |
| {12534, 3341, 3, 4 }, |
| // AArch64::STLURHi - 762 |
| {12550, 3345, 3, 4 }, |
| // AArch64::STLURWi - 763 |
| {12566, 3349, 3, 4 }, |
| // AArch64::STLURXi - 764 |
| {12566, 3353, 3, 4 }, |
| // AArch64::STNPDi - 765 |
| {12581, 3357, 4, 4 }, |
| // AArch64::STNPQi - 766 |
| {12581, 3361, 4, 4 }, |
| // AArch64::STNPSi - 767 |
| {12581, 3365, 4, 4 }, |
| // AArch64::STNPWi - 768 |
| {12581, 3369, 4, 4 }, |
| // AArch64::STNPXi - 769 |
| {12581, 3373, 4, 4 }, |
| // AArch64::STNT1B_ZRI - 770 |
| {12599, 3377, 4, 5 }, |
| // AArch64::STNT1B_ZZR_D_REAL - 771 |
| {12623, 3382, 4, 5 }, |
| // AArch64::STNT1B_ZZR_S_REAL - 772 |
| {12649, 3387, 4, 5 }, |
| // AArch64::STNT1D_ZRI - 773 |
| {12675, 3392, 4, 5 }, |
| // AArch64::STNT1D_ZZR_D_REAL - 774 |
| {12699, 3397, 4, 5 }, |
| // AArch64::STNT1H_ZRI - 775 |
| {12725, 3402, 4, 5 }, |
| // AArch64::STNT1H_ZZR_D_REAL - 776 |
| {12749, 3407, 4, 5 }, |
| // AArch64::STNT1H_ZZR_S_REAL - 777 |
| {12775, 3412, 4, 5 }, |
| // AArch64::STNT1W_ZRI - 778 |
| {12801, 3417, 4, 5 }, |
| // AArch64::STNT1W_ZZR_D_REAL - 779 |
| {12825, 3422, 4, 5 }, |
| // AArch64::STNT1W_ZZR_S_REAL - 780 |
| {12851, 3427, 4, 5 }, |
| // AArch64::STPDi - 781 |
| {12877, 3432, 4, 4 }, |
| // AArch64::STPQi - 782 |
| {12877, 3436, 4, 4 }, |
| // AArch64::STPSi - 783 |
| {12877, 3440, 4, 4 }, |
| // AArch64::STPWi - 784 |
| {12877, 3444, 4, 4 }, |
| // AArch64::STPXi - 785 |
| {12877, 3448, 4, 4 }, |
| // AArch64::STRBBroX - 786 |
| {12894, 3452, 5, 5 }, |
| // AArch64::STRBBui - 787 |
| {12912, 3457, 3, 3 }, |
| // AArch64::STRBroX - 788 |
| {12926, 3460, 5, 5 }, |
| // AArch64::STRBui - 789 |
| {12943, 3465, 3, 3 }, |
| // AArch64::STRDroX - 790 |
| {12926, 3468, 5, 5 }, |
| // AArch64::STRDui - 791 |
| {12943, 3473, 3, 3 }, |
| // AArch64::STRHHroX - 792 |
| {12956, 3476, 5, 5 }, |
| // AArch64::STRHHui - 793 |
| {12974, 3481, 3, 3 }, |
| // AArch64::STRHroX - 794 |
| {12926, 3484, 5, 5 }, |
| // AArch64::STRHui - 795 |
| {12943, 3489, 3, 3 }, |
| // AArch64::STRQroX - 796 |
| {12926, 3492, 5, 5 }, |
| // AArch64::STRQui - 797 |
| {12943, 3497, 3, 3 }, |
| // AArch64::STRSroX - 798 |
| {12926, 3500, 5, 5 }, |
| // AArch64::STRSui - 799 |
| {12943, 3505, 3, 3 }, |
| // AArch64::STRWroX - 800 |
| {12926, 3508, 5, 5 }, |
| // AArch64::STRWui - 801 |
| {12943, 3513, 3, 3 }, |
| // AArch64::STRXroX - 802 |
| {12926, 3516, 5, 5 }, |
| // AArch64::STRXui - 803 |
| {12943, 3521, 3, 3 }, |
| // AArch64::STR_PXI - 804 |
| {12988, 3524, 3, 4 }, |
| // AArch64::STR_ZXI - 805 |
| {12988, 3528, 3, 4 }, |
| // AArch64::STTRBi - 806 |
| {13003, 3532, 3, 3 }, |
| // AArch64::STTRHi - 807 |
| {13018, 3535, 3, 3 }, |
| // AArch64::STTRWi - 808 |
| {13033, 3538, 3, 3 }, |
| // AArch64::STTRXi - 809 |
| {13033, 3541, 3, 3 }, |
| // AArch64::STURBBi - 810 |
| {13047, 3544, 3, 3 }, |
| // AArch64::STURBi - 811 |
| {13062, 3547, 3, 3 }, |
| // AArch64::STURDi - 812 |
| {13062, 3550, 3, 3 }, |
| // AArch64::STURHHi - 813 |
| {13076, 3553, 3, 3 }, |
| // AArch64::STURHi - 814 |
| {13062, 3556, 3, 3 }, |
| // AArch64::STURQi - 815 |
| {13062, 3559, 3, 3 }, |
| // AArch64::STURSi - 816 |
| {13062, 3562, 3, 3 }, |
| // AArch64::STURWi - 817 |
| {13062, 3565, 3, 3 }, |
| // AArch64::STURXi - 818 |
| {13062, 3568, 3, 3 }, |
| // AArch64::STZ2GOffset - 819 |
| {13091, 3571, 3, 4 }, |
| // AArch64::STZGOffset - 820 |
| {13106, 3575, 3, 4 }, |
| // AArch64::SUBSWri - 821 |
| {13120, 3579, 4, 2 }, |
| // AArch64::SUBSWrs - 822 |
| {13133, 3581, 4, 4 }, |
| {13144, 3585, 4, 3 }, |
| {13159, 3588, 4, 4 }, |
| {13171, 3592, 4, 3 }, |
| {13187, 3595, 4, 4 }, |
| // AArch64::SUBSWrx - 827 |
| {13133, 3599, 4, 4 }, |
| {13203, 3603, 4, 3 }, |
| {13187, 3606, 4, 4 }, |
| // AArch64::SUBSXri - 830 |
| {13120, 3610, 4, 2 }, |
| // AArch64::SUBSXrs - 831 |
| {13133, 3612, 4, 4 }, |
| {13144, 3616, 4, 3 }, |
| {13159, 3619, 4, 4 }, |
| {13171, 3623, 4, 3 }, |
| {13187, 3626, 4, 4 }, |
| // AArch64::SUBSXrx - 836 |
| {13203, 3630, 4, 3 }, |
| // AArch64::SUBSXrx64 - 837 |
| {13133, 3633, 4, 4 }, |
| {13203, 3637, 4, 3 }, |
| {13187, 3640, 4, 4 }, |
| // AArch64::SUBWrs - 840 |
| {13218, 3644, 4, 4 }, |
| {13229, 3648, 4, 3 }, |
| {13244, 3651, 4, 4 }, |
| // AArch64::SUBWrx - 843 |
| {13244, 3655, 4, 4 }, |
| {13244, 3659, 4, 4 }, |
| // AArch64::SUBXrs - 845 |
| {13218, 3663, 4, 4 }, |
| {13229, 3667, 4, 3 }, |
| {13244, 3670, 4, 4 }, |
| // AArch64::SUBXrx64 - 848 |
| {13244, 3674, 4, 4 }, |
| {13244, 3678, 4, 4 }, |
| // AArch64::SYSxt - 850 |
| {13259, 3682, 5, 5 }, |
| // AArch64::UBFMWri - 851 |
| {13282, 3687, 4, 4 }, |
| {13297, 3691, 4, 4 }, |
| {13309, 3695, 4, 4 }, |
| // AArch64::UBFMXri - 854 |
| {13282, 3699, 4, 4 }, |
| {13297, 3703, 4, 4 }, |
| {13309, 3707, 4, 4 }, |
| {13321, 3711, 4, 4 }, |
| // AArch64::UMADDLrrr - 858 |
| {13333, 3715, 4, 4 }, |
| // AArch64::UMOVvi32 - 859 |
| {13350, 3719, 3, 3 }, |
| // AArch64::UMOVvi64 - 860 |
| {13369, 3722, 3, 3 }, |
| // AArch64::UMSUBLrrr - 861 |
| {13388, 3725, 4, 4 }, |
| // AArch64::UQDECB_WPiI - 862 |
| {13406, 3729, 4, 5 }, |
| {13416, 3734, 4, 5 }, |
| // AArch64::UQDECB_XPiI - 864 |
| {13406, 3739, 4, 5 }, |
| {13416, 3744, 4, 5 }, |
| // AArch64::UQDECD_WPiI - 866 |
| {13432, 3749, 4, 5 }, |
| {13442, 3754, 4, 5 }, |
| // AArch64::UQDECD_XPiI - 868 |
| {13432, 3759, 4, 5 }, |
| {13442, 3764, 4, 5 }, |
| // AArch64::UQDECD_ZPiI - 870 |
| {13458, 3769, 4, 5 }, |
| {13470, 3774, 4, 5 }, |
| // AArch64::UQDECH_WPiI - 872 |
| {13488, 3779, 4, 5 }, |
| {13498, 3784, 4, 5 }, |
| // AArch64::UQDECH_XPiI - 874 |
| {13488, 3789, 4, 5 }, |
| {13498, 3794, 4, 5 }, |
| // AArch64::UQDECH_ZPiI - 876 |
| {13514, 3799, 4, 5 }, |
| {13526, 3804, 4, 5 }, |
| // AArch64::UQDECW_WPiI - 878 |
| {13544, 3809, 4, 5 }, |
| {13554, 3814, 4, 5 }, |
| // AArch64::UQDECW_XPiI - 880 |
| {13544, 3819, 4, 5 }, |
| {13554, 3824, 4, 5 }, |
| // AArch64::UQDECW_ZPiI - 882 |
| {13570, 3829, 4, 5 }, |
| {13582, 3834, 4, 5 }, |
| // AArch64::UQINCB_WPiI - 884 |
| {13600, 3839, 4, 5 }, |
| {13610, 3844, 4, 5 }, |
| // AArch64::UQINCB_XPiI - 886 |
| {13600, 3849, 4, 5 }, |
| {13610, 3854, 4, 5 }, |
| // AArch64::UQINCD_WPiI - 888 |
| {13626, 3859, 4, 5 }, |
| {13636, 3864, 4, 5 }, |
| // AArch64::UQINCD_XPiI - 890 |
| {13626, 3869, 4, 5 }, |
| {13636, 3874, 4, 5 }, |
| // AArch64::UQINCD_ZPiI - 892 |
| {13652, 3879, 4, 5 }, |
| {13664, 3884, 4, 5 }, |
| // AArch64::UQINCH_WPiI - 894 |
| {13682, 3889, 4, 5 }, |
| {13692, 3894, 4, 5 }, |
| // AArch64::UQINCH_XPiI - 896 |
| {13682, 3899, 4, 5 }, |
| {13692, 3904, 4, 5 }, |
| // AArch64::UQINCH_ZPiI - 898 |
| {13708, 3909, 4, 5 }, |
| {13720, 3914, 4, 5 }, |
| // AArch64::UQINCW_WPiI - 900 |
| {13738, 3919, 4, 5 }, |
| {13748, 3924, 4, 5 }, |
| // AArch64::UQINCW_XPiI - 902 |
| {13738, 3929, 4, 5 }, |
| {13748, 3934, 4, 5 }, |
| // AArch64::UQINCW_ZPiI - 904 |
| {13764, 3939, 4, 5 }, |
| {13776, 3944, 4, 5 }, |
| // AArch64::XPACLRI - 906 |
| {13794, 3949, 0, 1 }, |
| }; |
| |
| static const AliasPatternCond Conds[] = { |
| // (ADDSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - 0 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 2 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) - 6 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (ADDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 9 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) - 13 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| // (ADDSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) - 17 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (ADDSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 20 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| // (ADDSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - 24 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 26 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) - 30 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (ADDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 33 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) - 37 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (ADDSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - 40 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(24)}, |
| // (ADDSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - 44 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (ADDSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 47 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(24)}, |
| // (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0) - 51 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0) - 55 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 59 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) - 63 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| // (ADDWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 67 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| // (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0) - 71 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0) - 75 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 79 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - 83 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(24)}, |
| // (ADDXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 87 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(24)}, |
| // (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2) - 91 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 93 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh) - 97 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (ANDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 100 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2) - 104 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 106 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh) - 110 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (ANDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 113 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 117 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 2}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ANDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 122 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ANDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 126 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 130 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 2}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (AND_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 135 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Custom, 1}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (AND_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 139 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Custom, 2}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (AND_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 143 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Custom, 3}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (AUTIA1716) - 147 |
| {AliasPatternCond::K_Feature, AArch64::FeaturePA}, |
| // (AUTIASP) - 148 |
| {AliasPatternCond::K_Feature, AArch64::FeaturePA}, |
| // (AUTIAZ) - 149 |
| {AliasPatternCond::K_Feature, AArch64::FeaturePA}, |
| // (AUTIB1716) - 150 |
| {AliasPatternCond::K_Feature, AArch64::FeaturePA}, |
| // (AUTIBSP) - 151 |
| {AliasPatternCond::K_Feature, AArch64::FeaturePA}, |
| // (AUTIBZ) - 152 |
| {AliasPatternCond::K_Feature, AArch64::FeaturePA}, |
| // (BICSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 153 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (BICSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 157 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (BICWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 161 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (BICXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 165 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (CLREX 15) - 169 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| // (CNTB_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 170 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CNTB_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 174 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CNTD_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 178 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CNTD_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 182 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CNTH_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 186 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CNTH_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 190 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CNTW_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 194 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CNTW_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 198 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CPY_ZPmI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 202 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 206 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 210 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 214 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CPY_ZPmR_B ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 218 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CPY_ZPmR_D ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn) - 223 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CPY_ZPmR_H ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 228 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CPY_ZPmR_S ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 233 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CPY_ZPmV_B ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn) - 238 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CPY_ZPmV_D ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn) - 243 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CPY_ZPmV_H ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn) - 248 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CPY_ZPmV_S ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn) - 253 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CPY_ZPzI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 258 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CPY_ZPzI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 261 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CPY_ZPzI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 264 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CPY_ZPzI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 267 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - 270 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_Custom, 4}, |
| // (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 274 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Custom, 4}, |
| // (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - 278 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Custom, 4}, |
| // (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 282 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Custom, 4}, |
| // (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - 286 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_Custom, 4}, |
| // (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 290 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Custom, 4}, |
| // (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - 294 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Custom, 4}, |
| // (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 298 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Custom, 4}, |
| // (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 302 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Custom, 4}, |
| // (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 306 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Custom, 4}, |
| // (DCPS1 0) - 310 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (DCPS2 0) - 311 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (DCPS3 0) - 312 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (DECB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 313 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DECB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 318 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DECD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 323 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DECD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 328 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 333 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 338 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DECH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 343 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DECH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 348 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 353 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 358 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DECW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 363 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DECW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 368 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 373 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 378 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DSB 0) - 383 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (DSB 4) - 384 |
| {AliasPatternCond::K_Imm, uint32_t(4)}, |
| // (DUPM_ZI ZPR16:$Zd, sve_preferred_logical_imm16:$imm) - 385 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Custom, 5}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUPM_ZI ZPR32:$Zd, sve_preferred_logical_imm32:$imm) - 388 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Custom, 6}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUPM_ZI ZPR64:$Zd, sve_preferred_logical_imm64:$imm) - 391 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Custom, 7}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUPM_ZI ZPR8:$Zd, sve_logical_imm8:$imm) - 394 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Custom, 1}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUPM_ZI ZPR16:$Zd, sve_logical_imm16:$imm) - 397 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Custom, 2}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUPM_ZI ZPR32:$Zd, sve_logical_imm32:$imm) - 400 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Custom, 3}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZI_B ZPR8:$Zd, cpy_imm8_opt_lsl_i8:$imm) - 403 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZI_D ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm) - 405 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZI_D ZPR64:$Zd, 0, 0) - 407 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZI_H ZPR16:$Zd, cpy_imm8_opt_lsl_i16:$imm) - 411 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZI_H ZPR16:$Zd, 0, 0) - 413 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZI_S ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm) - 417 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZI_S ZPR32:$Zd, 0, 0) - 419 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZR_B ZPR8:$Zd, GPR32sp:$Rn) - 423 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZR_D ZPR64:$Zd, GPR64sp:$Rn) - 426 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZR_H ZPR16:$Zd, GPR32sp:$Rn) - 429 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZR_S ZPR32:$Zd, GPR32sp:$Rn) - 432 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZZI_B ZPR8:$Zd, FPR8asZPR:$Bn, 0) - 435 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZZI_B ZPR8:$Zd, ZPR8:$Zn, sve_elm_idx_extdup_b:$idx) - 439 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZZI_D ZPR64:$Zd, FPR64asZPR:$Dn, 0) - 442 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZZI_D ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx) - 446 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZZI_H ZPR16:$Zd, FPR16asZPR:$Hn, 0) - 449 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZZI_H ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx) - 453 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZZI_Q ZPR128:$Zd, FPR128asZPR:$Qn, 0) - 456 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZZI_Q ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx) - 460 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZZI_S ZPR32:$Zd, FPR32asZPR:$Sn, 0) - 463 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (DUP_ZZI_S ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx) - 467 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (EONWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 470 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (EONXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 474 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) - 478 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (EORWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 483 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (EORXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 487 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) - 491 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (EOR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 496 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Custom, 1}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (EOR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 500 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Custom, 2}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (EOR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 504 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Custom, 3}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift) - 508 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift) - 511 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (FCPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, fpimm64:$imm8) - 514 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (FCPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, fpimm16:$imm8) - 518 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (FCPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, fpimm32:$imm8) - 522 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (FDUP_ZI_D ZPR64:$Zd, fpimm64:$imm8) - 526 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (FDUP_ZI_H ZPR16:$Zd, fpimm16:$imm8) - 528 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (FDUP_ZI_S ZPR32:$Zd, fpimm32:$imm8) - 530 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLD1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 532 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLD1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 537 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLD1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 542 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLD1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 547 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLD1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 552 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 557 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 562 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 567 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 572 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 577 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLD1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 582 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLD1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 587 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLDFF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 592 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLDFF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 597 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLDFF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 602 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLDFF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 607 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLDFF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 612 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLDFF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 617 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLDFF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 622 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLDFF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 627 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLDFF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 632 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLDFF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 637 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLDFF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 642 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (GLDFF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 647 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (HINT { 0, 0, 0 }) - 652 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (HINT { 0, 0, 1 }) - 653 |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| // (HINT { 0, 1, 0 }) - 654 |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| // (HINT { 0, 1, 1 }) - 655 |
| {AliasPatternCond::K_Imm, uint32_t(3)}, |
| // (HINT { 1, 0, 0 }) - 656 |
| {AliasPatternCond::K_Imm, uint32_t(4)}, |
| // (HINT { 1, 0, 1 }) - 657 |
| {AliasPatternCond::K_Imm, uint32_t(5)}, |
| // (HINT { 1, 0, 0, 0, 0 }) - 658 |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureRAS}, |
| // (HINT 20) - 660 |
| {AliasPatternCond::K_Imm, uint32_t(20)}, |
| // (HINT 32) - 661 |
| {AliasPatternCond::K_Imm, uint32_t(32)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureBranchTargetId}, |
| // (HINT btihint_op:$op) - 663 |
| {AliasPatternCond::K_Custom, 8}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureBranchTargetId}, |
| // (HINT psbhint_op:$op) - 665 |
| {AliasPatternCond::K_Custom, 9}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSPE}, |
| // (INCB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 667 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (INCB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 672 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (INCD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 677 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (INCD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 682 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (INCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 687 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (INCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 692 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (INCH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 697 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (INCH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 702 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (INCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 707 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (INCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 712 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (INCW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 717 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (INCW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 722 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (INCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 727 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (INCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 732 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (INSvi16gpr V128:$dst, VectorIndexH:$idx, GPR32:$src) - 737 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, VectorIndexH:$idx2) - 742 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (INSvi32gpr V128:$dst, VectorIndexS:$idx, GPR32:$src) - 747 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, VectorIndexS:$idx2) - 752 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (INSvi64gpr V128:$dst, VectorIndexD:$idx, GPR64:$src) - 757 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, VectorIndexD:$idx2) - 762 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (INSvi8gpr V128:$dst, VectorIndexB:$idx, GPR32:$src) - 767 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, VectorIndexB:$idx2) - 772 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (IRG GPR64sp:$dst, GPR64sp:$src, XZR) - 777 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureMTE}, |
| // (ISB 15) - 781 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| // (LD1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 782 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 787 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 792 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 797 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 802 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 807 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 812 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 817 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 822 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 827 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 832 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 837 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 842 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 847 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 852 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 857 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 862 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 867 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 872 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 877 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 882 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 887 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 892 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 897 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1RB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 902 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1RB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 907 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1RB_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 912 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1RB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 917 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1RD_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 922 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1RH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 927 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1RH_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 932 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1RH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 937 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1RQ_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 942 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1RQ_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 947 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1RQ_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 952 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1RQ_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 957 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1RSB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 962 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1RSB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 967 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1RSB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 972 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1RSH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 977 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1RSH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 982 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1RSW_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 987 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1RW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 992 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1RW_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 997 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1Rv16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 1002 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Rv1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 1007 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Rv2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 1012 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Rv2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 1017 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Rv4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 1022 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Rv4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 1027 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Rv8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 1032 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Rv8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 1037 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1SB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1042 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1SB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1047 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1SB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1052 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1SH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1057 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1SH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1062 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1SW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1067 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 1072 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 1077 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 1082 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 1087 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 1092 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 1097 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 1102 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 1107 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 1112 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 1117 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 1122 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 1127 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 1132 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 1137 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 1142 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 1147 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1152 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1157 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - 1162 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - 1169 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - 1176 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - 1183 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1190 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1195 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1200 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD2Rv16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 1205 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD2Rv1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 1210 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD2Rv2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 1215 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD2Rv2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 1220 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD2Rv4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 1225 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD2Rv4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 1230 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD2Rv8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 1235 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD2Rv8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 1240 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 1245 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 1250 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 1255 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 1260 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 1265 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 1270 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 1275 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1280 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - 1285 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - 1292 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - 1299 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - 1306 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1313 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1318 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1323 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD3Rv16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 1328 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD3Rv1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 1333 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD3Rv2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 1338 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD3Rv2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 1343 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD3Rv4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 1348 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD3Rv4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 1353 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD3Rv8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 1358 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD3Rv8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 1363 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 1368 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 1373 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 1378 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 1383 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 1388 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 1393 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 1398 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1403 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - 1408 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - 1415 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - 1422 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - 1429 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1436 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1441 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 1446 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 1451 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 1456 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 1461 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 1466 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 1471 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 1476 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1481 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD4Rv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 1486 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD4Rv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 1491 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD4Rv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 1496 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD4Rv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 1501 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD4Rv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 1506 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD4Rv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 1511 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD4Rv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 1516 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD4Rv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 1521 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1526 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LD4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - 1531 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - 1538 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - 1545 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LD4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - 1552 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (LDADDB WZR, GPR32:$Rs, GPR64sp:$Rn) - 1559 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDADDH WZR, GPR32:$Rs, GPR64sp:$Rn) - 1563 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDADDLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 1567 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDADDLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 1571 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDADDLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 1575 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDADDLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 1579 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDADDW WZR, GPR32:$Rs, GPR64sp:$Rn) - 1583 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDADDX XZR, GPR64:$Rs, GPR64sp:$Rn) - 1587 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDAPURBi GPR32:$Rt, GPR64sp:$Rn, 0) - 1591 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO}, |
| // (LDAPURHi GPR32:$Rt, GPR64sp:$Rn, 0) - 1595 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO}, |
| // (LDAPURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 1599 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO}, |
| // (LDAPURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 1603 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO}, |
| // (LDAPURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 1607 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO}, |
| // (LDAPURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 1611 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO}, |
| // (LDAPURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 1615 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO}, |
| // (LDAPURXi GPR64:$Rt, GPR64sp:$Rn, 0) - 1619 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO}, |
| // (LDAPURi GPR32:$Rt, GPR64sp:$Rn, 0) - 1623 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO}, |
| // (LDCLRB WZR, GPR32:$Rs, GPR64sp:$Rn) - 1627 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDCLRH WZR, GPR32:$Rs, GPR64sp:$Rn) - 1631 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDCLRLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 1635 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDCLRLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 1639 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDCLRLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 1643 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDCLRLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 1647 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDCLRW WZR, GPR32:$Rs, GPR64sp:$Rn) - 1651 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDCLRX XZR, GPR64:$Rs, GPR64sp:$Rn) - 1655 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDEORB WZR, GPR32:$Rs, GPR64sp:$Rn) - 1659 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDEORH WZR, GPR32:$Rs, GPR64sp:$Rn) - 1663 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDEORLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 1667 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDEORLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 1671 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDEORLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 1675 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDEORLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 1679 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDEORW WZR, GPR32:$Rs, GPR64sp:$Rn) - 1683 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDEORX XZR, GPR64:$Rs, GPR64sp:$Rn) - 1687 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDFF1B_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1691 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDFF1B_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1696 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDFF1B_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1701 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDFF1B_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1706 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDFF1D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1711 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDFF1H_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1716 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDFF1H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1721 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDFF1H_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1726 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDFF1SB_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1731 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDFF1SB_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1736 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDFF1SB_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1741 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDFF1SH_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1746 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDFF1SH_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1751 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDFF1SW_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1756 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDFF1W_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1761 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDFF1W_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 1766 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDG GPR64:$Rt, GPR64sp:$Rn, 0) - 1771 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureMTE}, |
| // (LDNF1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1776 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDNF1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1781 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDNF1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1786 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDNF1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1791 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDNF1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1796 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDNF1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1801 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDNF1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1806 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDNF1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1811 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDNF1SB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1816 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDNF1SB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1821 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDNF1SB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1826 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDNF1SH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1831 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDNF1SH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1836 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDNF1SW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1841 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDNF1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1846 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDNF1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1851 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 1856 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 1860 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 1864 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 1868 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 1872 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1876 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDNT1B_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1881 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE2}, |
| // (LDNT1B_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 1886 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE2}, |
| // (LDNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1891 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDNT1D_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1896 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE2}, |
| // (LDNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1901 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDNT1H_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1906 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE2}, |
| // (LDNT1H_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 1911 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE2}, |
| // (LDNT1SB_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1916 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE2}, |
| // (LDNT1SB_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 1921 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE2}, |
| // (LDNT1SH_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1926 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE2}, |
| // (LDNT1SH_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 1931 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE2}, |
| // (LDNT1SW_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1936 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE2}, |
| // (LDNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1941 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDNT1W_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 1946 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE2}, |
| // (LDNT1W_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 1951 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE2}, |
| // (LDPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 1956 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 1960 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDPSWi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 1964 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 1968 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 1972 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 1976 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRAAindexed GPR64:$Rt, GPR64sp:$Rn, 0) - 1980 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeaturePA}, |
| // (LDRABindexed GPR64:$Rt, GPR64sp:$Rn, 0) - 1984 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeaturePA}, |
| // (LDRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 1988 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRBBui GPR32:$Rt, GPR64sp:$Rn, 0) - 1993 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 1996 |
| {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) - 2001 |
| {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2004 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) - 2009 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2012 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRHHui GPR32:$Rt, GPR64sp:$Rn, 0) - 2017 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2020 |
| {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) - 2025 |
| {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2028 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) - 2033 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSBWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2036 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSBWui GPR32:$Rt, GPR64sp:$Rn, 0) - 2041 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSBXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2044 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSBXui GPR64:$Rt, GPR64sp:$Rn, 0) - 2049 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSHWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2052 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSHWui GPR32:$Rt, GPR64sp:$Rn, 0) - 2057 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSHXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2060 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSHXui GPR64:$Rt, GPR64sp:$Rn, 0) - 2065 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSWroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2068 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSWui GPR64:$Rt, GPR64sp:$Rn, 0) - 2073 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2076 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) - 2081 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2084 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRWui GPR32z:$Rt, GPR64sp:$Rn, 0) - 2089 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2092 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRXui GPR64z:$Rt, GPR64sp:$Rn, 0) - 2097 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) - 2100 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) - 2104 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (LDSETB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2108 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSETH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2112 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSETLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2116 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSETLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2120 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSETLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2124 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSETLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2128 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSETW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2132 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSETX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2136 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2140 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2144 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2148 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2152 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2156 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2160 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2164 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2168 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSMINB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2172 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSMINH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2176 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2180 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2184 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2188 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2192 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSMINW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2196 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDSMINX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2200 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - 2204 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - 2207 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDTRSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2210 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDTRSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2213 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDTRSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2216 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDTRSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2219 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDTRSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 2222 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2225 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2228 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDUMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2231 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDUMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2235 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDUMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2239 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDUMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2243 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDUMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2247 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDUMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2251 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDUMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2255 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDUMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2259 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDUMINB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2263 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDUMINH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2267 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDUMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2271 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDUMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2275 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDUMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2279 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDUMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2283 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDUMINW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2287 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDUMINX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2291 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureLSE}, |
| // (LDURBBi GPR32:$Rt, GPR64sp:$Rn, 0) - 2295 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) - 2298 |
| {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) - 2301 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURHHi GPR32:$Rt, GPR64sp:$Rn, 0) - 2304 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) - 2307 |
| {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) - 2310 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2313 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2316 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2319 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2322 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 2325 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) - 2328 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURWi GPR32z:$Rt, GPR64sp:$Rn, 0) - 2331 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURXi GPR64z:$Rt, GPR64sp:$Rn, 0) - 2334 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (MADDWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - 2337 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| // (MADDXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - 2341 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| // (MSUBWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - 2345 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| // (MSUBXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - 2349 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| // (NOTv16i8 V128:$Vd, V128:$Vn) - 2353 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| // (NOTv8i8 V64:$Vd, V64:$Vn) - 2355 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0) - 2357 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh) - 2361 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (ORNWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 2364 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0) - 2368 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh) - 2372 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (ORNXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 2375 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) - 2379 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0) - 2384 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ORRWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 2388 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0) - 2392 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ORRXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 2396 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) - 2400 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ORR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 2405 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Custom, 1}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ORR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 2409 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Custom, 2}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ORR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 2413 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Custom, 3}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn) - 2417 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ORRv16i8 V128:$dst, V128:$src, V128:$src) - 2421 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (ORRv8i8 V64:$dst, V64:$src, V64:$src) - 2424 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (PACIA1716) - 2427 |
| {AliasPatternCond::K_Feature, AArch64::FeaturePA}, |
| // (PACIASP) - 2428 |
| {AliasPatternCond::K_Feature, AArch64::FeaturePA}, |
| // (PACIAZ) - 2429 |
| {AliasPatternCond::K_Feature, AArch64::FeaturePA}, |
| // (PACIB1716) - 2430 |
| {AliasPatternCond::K_Feature, AArch64::FeaturePA}, |
| // (PACIBSP) - 2431 |
| {AliasPatternCond::K_Feature, AArch64::FeaturePA}, |
| // (PACIBZ) - 2432 |
| {AliasPatternCond::K_Feature, AArch64::FeaturePA}, |
| // (PRFB_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2433 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (PRFB_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2438 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (PRFB_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2443 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (PRFD_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2448 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (PRFD_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2453 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (PRFD_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2458 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (PRFH_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2463 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (PRFH_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2468 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (PRFH_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2473 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (PRFMroX prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 2478 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (PRFMui prfop:$Rt, GPR64sp:$Rn, 0) - 2483 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (PRFUMi prfop:$Rt, GPR64sp:$Rn, 0) - 2486 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (PRFW_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2489 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (PRFW_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2494 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (PRFW_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2499 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (PTRUES_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) - 2504 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (PTRUES_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) - 2507 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (PTRUES_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) - 2510 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (PTRUES_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) - 2513 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (PTRUE_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) - 2516 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (PTRUE_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) - 2519 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (PTRUE_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) - 2522 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (PTRUE_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) - 2525 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (RET LR) - 2528 |
| {AliasPatternCond::K_Reg, AArch64::LR}, |
| // (SBCSWr GPR32:$dst, WZR, GPR32:$src) - 2529 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (SBCSXr GPR64:$dst, XZR, GPR64:$src) - 2532 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (SBCWr GPR32:$dst, WZR, GPR32:$src) - 2535 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (SBCXr GPR64:$dst, XZR, GPR64:$src) - 2538 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) - 2541 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| // (SBFMWri GPR32:$dst, GPR32:$src, 0, 7) - 2545 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| // (SBFMWri GPR32:$dst, GPR32:$src, 0, 15) - 2549 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| // (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) - 2553 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(63)}, |
| // (SBFMXri GPR64:$dst, GPR64:$src, 0, 7) - 2557 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| // (SBFMXri GPR64:$dst, GPR64:$src, 0, 15) - 2561 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| // (SBFMXri GPR64:$dst, GPR64:$src, 0, 31) - 2565 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| // (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd) - 2569 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 0}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SEL_ZPZZ_B ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd) - 2574 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 0}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SEL_ZPZZ_D ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd) - 2579 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 0}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SEL_ZPZZ_H ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd) - 2584 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 0}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SEL_ZPZZ_S ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd) - 2589 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 0}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 2594 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| // (SMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 2598 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| // (SQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2602 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2607 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2612 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2617 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2622 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2627 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2632 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2637 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 2642 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 2647 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2652 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2657 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2662 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2667 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 2672 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 2677 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2682 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2687 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2692 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2697 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 2702 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 2707 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2712 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2717 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2722 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2727 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2732 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2737 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2742 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2747 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 2752 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 2757 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2762 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2767 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2772 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2777 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 2782 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 2787 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 2792 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 2797 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 2802 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 2807 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 2812 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 2817 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SST1B_D_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2822 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2827 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SST1D_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2832 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SST1H_D_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2837 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2842 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SST1W_D_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 2847 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (SST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 2852 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2857 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2862 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2867 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2872 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2877 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 2882 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 2887 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 2892 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 2897 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 2902 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 2907 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 2912 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 2917 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2922 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2927 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2932 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 2937 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 2942 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 2947 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 2952 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 2957 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 2962 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 2967 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 2972 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 2977 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 2982 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 2987 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 2992 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 2997 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 3002 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 3007 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 3012 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 3017 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 3022 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 3027 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 3032 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 3037 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 3042 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 3047 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 3052 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3057 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3062 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - 3067 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - 3073 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - 3079 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - 3085 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3091 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3096 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST2GOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 3101 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureMTE}, |
| // (ST2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3105 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 3110 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 3115 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 3120 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 3125 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 3130 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 3135 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 3140 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3145 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - 3150 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - 3156 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - 3162 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - 3168 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3174 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3179 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3184 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 3189 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 3194 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 3199 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 3204 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 3209 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 3214 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 3219 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3224 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - 3229 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - 3235 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - 3241 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - 3247 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3253 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3258 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 3263 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 3268 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 3273 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 3278 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 3283 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 3288 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 3293 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3298 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3303 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (ST4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - 3308 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - 3314 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - 3320 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (ST4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - 3326 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (STGOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 3332 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureMTE}, |
| // (STGPi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3336 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureMTE}, |
| // (STLURBi GPR32:$Rt, GPR64sp:$Rn, 0) - 3341 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO}, |
| // (STLURHi GPR32:$Rt, GPR64sp:$Rn, 0) - 3345 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO}, |
| // (STLURWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3349 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO}, |
| // (STLURXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3353 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureRCPC_IMMO}, |
| // (STNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 3357 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 3361 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 3365 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 3369 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3373 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3377 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (STNT1B_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3382 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE2}, |
| // (STNT1B_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3387 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE2}, |
| // (STNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3392 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (STNT1D_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3397 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE2}, |
| // (STNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3402 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (STNT1H_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3407 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE2}, |
| // (STNT1H_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3412 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE2}, |
| // (STNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3417 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (STNT1W_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3422 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE2}, |
| // (STNT1W_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3427 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE2}, |
| // (STPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 3432 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 3436 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 3440 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 3444 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3448 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3452 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRBBui GPR32z:$Rt, GPR64sp:$Rn, 0) - 3457 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3460 |
| {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) - 3465 |
| {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3468 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) - 3473 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3476 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRHHui GPR32z:$Rt, GPR64sp:$Rn, 0) - 3481 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3484 |
| {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) - 3489 |
| {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3492 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) - 3497 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3500 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) - 3505 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3508 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRWui GPR32z:$Rt, GPR64sp:$Rn, 0) - 3513 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3516 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRXui GPR64z:$Rt, GPR64sp:$Rn, 0) - 3521 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) - 3524 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (STR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) - 3528 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (STTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - 3532 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - 3535 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3538 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3541 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STURBBi GPR32z:$Rt, GPR64sp:$Rn, 0) - 3544 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) - 3547 |
| {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) - 3550 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STURHHi GPR32z:$Rt, GPR64sp:$Rn, 0) - 3553 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) - 3556 |
| {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) - 3559 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) - 3562 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STURWi GPR32z:$Rt, GPR64sp:$Rn, 0) - 3565 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STURXi GPR64z:$Rt, GPR64sp:$Rn, 0) - 3568 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STZ2GOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 3571 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureMTE}, |
| // (STZGOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 3575 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureMTE}, |
| // (SUBSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - 3579 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 3581 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) - 3585 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0) - 3588 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) - 3592 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (SUBSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 3595 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) - 3599 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| // (SUBSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) - 3603 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (SUBSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 3606 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| // (SUBSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - 3610 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 3612 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) - 3616 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0) - 3619 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) - 3623 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (SUBSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 3626 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) - 3630 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (SUBSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - 3633 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(24)}, |
| // (SUBSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - 3637 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (SUBSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 3640 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(24)}, |
| // (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0) - 3644 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) - 3648 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (SUBWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 3651 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) - 3655 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| // (SUBWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 3659 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| // (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0) - 3663 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) - 3667 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (SUBXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 3670 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - 3674 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(24)}, |
| // (SUBXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 3678 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(24)}, |
| // (SYSxt imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) - 3682 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| // (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) - 3687 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| // (UBFMWri GPR32:$dst, GPR32:$src, 0, 7) - 3691 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| // (UBFMWri GPR32:$dst, GPR32:$src, 0, 15) - 3695 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| // (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) - 3699 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(63)}, |
| // (UBFMXri GPR64:$dst, GPR64:$src, 0, 7) - 3703 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| // (UBFMXri GPR64:$dst, GPR64:$src, 0, 15) - 3707 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| // (UBFMXri GPR64:$dst, GPR64:$src, 0, 31) - 3711 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| // (UMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 3715 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| // (UMOVvi32 GPR32:$dst, V128:$src, VectorIndexS:$idx) - 3719 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (UMOVvi64 GPR64:$dst, V128:$src, VectorIndexD:$idx) - 3722 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureNEON}, |
| // (UMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 3725 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| // (UQDECB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3729 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3734 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3739 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3744 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3749 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3754 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3759 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3764 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3769 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 3774 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3779 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3784 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3789 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3794 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3799 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 3804 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3809 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3814 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3819 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3824 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3829 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 3834 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3839 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3844 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3849 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3854 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3859 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3864 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3869 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3874 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3879 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 3884 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3889 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3894 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3899 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3904 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3909 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 3914 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3919 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 3924 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 3929 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 3934 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 3939 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (UQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 3944 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, AArch64::FeatureSVE}, |
| // (XPACLRI) - 3949 |
| {AliasPatternCond::K_Feature, AArch64::FeaturePA}, |
| }; |
| |
| static const char AsmStrings[] = |
| /* 0 */ "cmn $\x02, $\xFF\x03\x01\0" |
| /* 13 */ "cmn $\x02, $\x03\0" |
| /* 24 */ "cmn $\x02, $\x03$\xFF\x04\x02\0" |
| /* 39 */ "adds $\x01, $\x02, $\x03\0" |
| /* 55 */ "cmn $\x02, $\x03$\xFF\x04\x03\0" |
| /* 70 */ "mov $\x01, $\x02\0" |
| /* 81 */ "add $\x01, $\x02, $\x03\0" |
| /* 96 */ "tst $\x02, $\xFF\x03\x04\0" |
| /* 109 */ "tst $\x02, $\x03\0" |
| /* 120 */ "tst $\x02, $\x03$\xFF\x04\x02\0" |
| /* 135 */ "ands $\x01, $\x02, $\x03\0" |
| /* 151 */ "tst $\x02, $\xFF\x03\x05\0" |
| /* 164 */ "movs $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" |
| /* 188 */ "and $\x01, $\x02, $\x03\0" |
| /* 203 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" |
| /* 226 */ "and $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0" |
| /* 247 */ "and $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0" |
| /* 268 */ "and $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0" |
| /* 289 */ "autia1716\0" |
| /* 299 */ "autiasp\0" |
| /* 307 */ "autiaz\0" |
| /* 314 */ "autib1716\0" |
| /* 324 */ "autibsp\0" |
| /* 332 */ "autibz\0" |
| /* 339 */ "bics $\x01, $\x02, $\x03\0" |
| /* 355 */ "bic $\x01, $\x02, $\x03\0" |
| /* 370 */ "clrex\0" |
| /* 376 */ "cntb $\x01\0" |
| /* 384 */ "cntb $\x01, $\xFF\x02\x0E\0" |
| /* 398 */ "cntd $\x01\0" |
| /* 406 */ "cntd $\x01, $\xFF\x02\x0E\0" |
| /* 420 */ "cnth $\x01\0" |
| /* 428 */ "cnth $\x01, $\xFF\x02\x0E\0" |
| /* 442 */ "cntw $\x01\0" |
| /* 450 */ "cntw $\x01, $\xFF\x02\x0E\0" |
| /* 464 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x0F\0" |
| /* 487 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x11\0" |
| /* 510 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x12\0" |
| /* 533 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x13\0" |
| /* 556 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\x04\0" |
| /* 577 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\x04\0" |
| /* 598 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\x04\0" |
| /* 619 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\x04\0" |
| /* 640 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x0F\0" |
| /* 663 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/z, $\xFF\x03\x11\0" |
| /* 686 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/z, $\xFF\x03\x12\0" |
| /* 709 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/z, $\xFF\x03\x13\0" |
| /* 732 */ "cset $\x01, $\xFF\x04\x14\0" |
| /* 746 */ "cinc $\x01, $\x02, $\xFF\x04\x14\0" |
| /* 764 */ "csetm $\x01, $\xFF\x04\x14\0" |
| /* 779 */ "cinv $\x01, $\x02, $\xFF\x04\x14\0" |
| /* 797 */ "cneg $\x01, $\x02, $\xFF\x04\x14\0" |
| /* 815 */ "dcps1\0" |
| /* 821 */ "dcps2\0" |
| /* 827 */ "dcps3\0" |
| /* 833 */ "decb $\x01\0" |
| /* 841 */ "decb $\x01, $\xFF\x03\x0E\0" |
| /* 855 */ "decd $\x01\0" |
| /* 863 */ "decd $\x01, $\xFF\x03\x0E\0" |
| /* 877 */ "decd $\xFF\x01\x10\0" |
| /* 887 */ "decd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| /* 903 */ "dech $\x01\0" |
| /* 911 */ "dech $\x01, $\xFF\x03\x0E\0" |
| /* 925 */ "dech $\xFF\x01\x09\0" |
| /* 935 */ "dech $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| /* 951 */ "decw $\x01\0" |
| /* 959 */ "decw $\x01, $\xFF\x03\x0E\0" |
| /* 973 */ "decw $\xFF\x01\x0B\0" |
| /* 983 */ "decw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| /* 999 */ "ssbb\0" |
| /* 1004 */ "pssbb\0" |
| /* 1010 */ "mov $\xFF\x01\x09, $\xFF\x02\x15\0" |
| /* 1025 */ "mov $\xFF\x01\x0B, $\xFF\x02\x16\0" |
| /* 1040 */ "mov $\xFF\x01\x10, $\xFF\x02\x17\0" |
| /* 1055 */ "dupm $\xFF\x01\x06, $\xFF\x02\x08\0" |
| /* 1071 */ "dupm $\xFF\x01\x09, $\xFF\x02\x0A\0" |
| /* 1087 */ "dupm $\xFF\x01\x0B, $\xFF\x02\x04\0" |
| /* 1103 */ "mov $\xFF\x01\x06, $\xFF\x02\x0F\0" |
| /* 1118 */ "mov $\xFF\x01\x10, $\xFF\x02\x11\0" |
| /* 1133 */ "fmov $\xFF\x01\x10, #0.0\0" |
| /* 1149 */ "mov $\xFF\x01\x09, $\xFF\x02\x12\0" |
| /* 1164 */ "fmov $\xFF\x01\x09, #0.0\0" |
| /* 1180 */ "mov $\xFF\x01\x0B, $\xFF\x02\x13\0" |
| /* 1195 */ "fmov $\xFF\x01\x0B, #0.0\0" |
| /* 1211 */ "mov $\xFF\x01\x06, $\x02\0" |
| /* 1224 */ "mov $\xFF\x01\x10, $\x02\0" |
| /* 1237 */ "mov $\xFF\x01\x09, $\x02\0" |
| /* 1250 */ "mov $\xFF\x01\x0B, $\x02\0" |
| /* 1263 */ "mov $\xFF\x01\x06, $\xFF\x02\x18\0" |
| /* 1278 */ "mov $\xFF\x01\x06, $\xFF\x02\x06$\xFF\x03\x19\0" |
| /* 1297 */ "mov $\xFF\x01\x10, $\xFF\x02\x1A\0" |
| /* 1312 */ "mov $\xFF\x01\x10, $\xFF\x02\x10$\xFF\x03\x19\0" |
| /* 1331 */ "mov $\xFF\x01\x09, $\xFF\x02\x1B\0" |
| /* 1346 */ "mov $\xFF\x01\x09, $\xFF\x02\x09$\xFF\x03\x19\0" |
| /* 1365 */ "mov $\xFF\x01\x1C, $\xFF\x02\x1D\0" |
| /* 1380 */ "mov $\xFF\x01\x1C, $\xFF\x02\x1C$\xFF\x03\x19\0" |
| /* 1399 */ "mov $\xFF\x01\x0B, $\xFF\x02\x1E\0" |
| /* 1414 */ "mov $\xFF\x01\x0B, $\xFF\x02\x0B$\xFF\x03\x19\0" |
| /* 1433 */ "eon $\x01, $\x02, $\x03\0" |
| /* 1448 */ "nots $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" |
| /* 1472 */ "eor $\x01, $\x02, $\x03\0" |
| /* 1487 */ "not $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" |
| /* 1510 */ "eor $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0" |
| /* 1531 */ "eor $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0" |
| /* 1552 */ "eor $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0" |
| /* 1573 */ "ror $\x01, $\x02, $\x04\0" |
| /* 1588 */ "fmov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x1F\0" |
| /* 1612 */ "fmov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x1F\0" |
| /* 1636 */ "fmov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x1F\0" |
| /* 1660 */ "fmov $\xFF\x01\x10, $\xFF\x02\x1F\0" |
| /* 1676 */ "fmov $\xFF\x01\x09, $\xFF\x02\x1F\0" |
| /* 1692 */ "fmov $\xFF\x01\x0B, $\xFF\x02\x1F\0" |
| /* 1708 */ "ld1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 1734 */ "ld1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 1760 */ "ld1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 1786 */ "ld1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 1812 */ "ld1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 1838 */ "ld1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 1865 */ "ld1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 1892 */ "ld1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 1919 */ "ld1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 1946 */ "ld1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 1973 */ "ld1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 1999 */ "ld1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 2025 */ "ldff1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2053 */ "ldff1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 2081 */ "ldff1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2109 */ "ldff1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2137 */ "ldff1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 2165 */ "ldff1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2194 */ "ldff1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 2223 */ "ldff1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2252 */ "ldff1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 2281 */ "ldff1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2310 */ "ldff1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2338 */ "ldff1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 2366 */ "nop\0" |
| /* 2370 */ "yield\0" |
| /* 2376 */ "wfe\0" |
| /* 2380 */ "wfi\0" |
| /* 2384 */ "sev\0" |
| /* 2388 */ "sevl\0" |
| /* 2393 */ "esb\0" |
| /* 2397 */ "csdb\0" |
| /* 2402 */ "bti\0" |
| /* 2406 */ "bti $\xFF\x01\x22\0" |
| /* 2415 */ "psb $\xFF\x01\x23\0" |
| /* 2424 */ "incb $\x01\0" |
| /* 2432 */ "incb $\x01, $\xFF\x03\x0E\0" |
| /* 2446 */ "incd $\x01\0" |
| /* 2454 */ "incd $\x01, $\xFF\x03\x0E\0" |
| /* 2468 */ "incd $\xFF\x01\x10\0" |
| /* 2478 */ "incd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| /* 2494 */ "inch $\x01\0" |
| /* 2502 */ "inch $\x01, $\xFF\x03\x0E\0" |
| /* 2516 */ "inch $\xFF\x01\x09\0" |
| /* 2526 */ "inch $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| /* 2542 */ "incw $\x01\0" |
| /* 2550 */ "incw $\x01, $\xFF\x03\x0E\0" |
| /* 2564 */ "incw $\xFF\x01\x0B\0" |
| /* 2574 */ "incw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| /* 2590 */ "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\x04\0" |
| /* 2609 */ "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\xFF\x04\x0C.h$\xFF\x05\x19\0" |
| /* 2636 */ "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\x04\0" |
| /* 2655 */ "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\xFF\x04\x0C.s$\xFF\x05\x19\0" |
| /* 2682 */ "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\x04\0" |
| /* 2701 */ "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\xFF\x04\x0C.d$\xFF\x05\x19\0" |
| /* 2728 */ "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\x04\0" |
| /* 2747 */ "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\xFF\x04\x0C.b$\xFF\x05\x19\0" |
| /* 2774 */ "irg $\x01, $\x02\0" |
| /* 2785 */ "isb\0" |
| /* 2789 */ "ld1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 2813 */ "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 2837 */ "ld1b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 2861 */ "ld1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 2885 */ "ld1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 2909 */ "ld1 $\xFF\x02\x26, [$\x01], #64\0" |
| /* 2929 */ "ld1 $\xFF\x02\x27, [$\x01], #32\0" |
| /* 2949 */ "ld1 $\xFF\x02\x28, [$\x01], #64\0" |
| /* 2969 */ "ld1 $\xFF\x02\x29, [$\x01], #32\0" |
| /* 2989 */ "ld1 $\xFF\x02\x2A, [$\x01], #32\0" |
| /* 3009 */ "ld1 $\xFF\x02\x2B, [$\x01], #64\0" |
| /* 3029 */ "ld1 $\xFF\x02\x2C, [$\x01], #32\0" |
| /* 3049 */ "ld1 $\xFF\x02\x2D, [$\x01], #64\0" |
| /* 3069 */ "ld1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3093 */ "ld1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3117 */ "ld1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3141 */ "ld1 $\xFF\x02\x26, [$\x01], #16\0" |
| /* 3161 */ "ld1 $\xFF\x02\x27, [$\x01], #8\0" |
| /* 3180 */ "ld1 $\xFF\x02\x28, [$\x01], #16\0" |
| /* 3200 */ "ld1 $\xFF\x02\x29, [$\x01], #8\0" |
| /* 3219 */ "ld1 $\xFF\x02\x2A, [$\x01], #8\0" |
| /* 3238 */ "ld1 $\xFF\x02\x2B, [$\x01], #16\0" |
| /* 3258 */ "ld1 $\xFF\x02\x2C, [$\x01], #8\0" |
| /* 3277 */ "ld1 $\xFF\x02\x2D, [$\x01], #16\0" |
| /* 3297 */ "ld1rb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3322 */ "ld1rb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3347 */ "ld1rb $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3372 */ "ld1rb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3397 */ "ld1rd $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3422 */ "ld1rh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3447 */ "ld1rh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3472 */ "ld1rh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3497 */ "ld1rqb $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3523 */ "ld1rqd $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3549 */ "ld1rqh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3575 */ "ld1rqw $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3601 */ "ld1rsb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3627 */ "ld1rsb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3653 */ "ld1rsb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3679 */ "ld1rsh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3705 */ "ld1rsh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3731 */ "ld1rsw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3757 */ "ld1rw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3782 */ "ld1rw $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3807 */ "ld1r $\xFF\x02\x26, [$\x01], #1\0" |
| /* 3827 */ "ld1r $\xFF\x02\x27, [$\x01], #8\0" |
| /* 3847 */ "ld1r $\xFF\x02\x28, [$\x01], #8\0" |
| /* 3867 */ "ld1r $\xFF\x02\x29, [$\x01], #4\0" |
| /* 3887 */ "ld1r $\xFF\x02\x2A, [$\x01], #2\0" |
| /* 3907 */ "ld1r $\xFF\x02\x2B, [$\x01], #4\0" |
| /* 3927 */ "ld1r $\xFF\x02\x2C, [$\x01], #1\0" |
| /* 3947 */ "ld1r $\xFF\x02\x2D, [$\x01], #2\0" |
| /* 3967 */ "ld1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3992 */ "ld1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4017 */ "ld1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4042 */ "ld1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4067 */ "ld1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4092 */ "ld1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4117 */ "ld1 $\xFF\x02\x26, [$\x01], #48\0" |
| /* 4137 */ "ld1 $\xFF\x02\x27, [$\x01], #24\0" |
| /* 4157 */ "ld1 $\xFF\x02\x28, [$\x01], #48\0" |
| /* 4177 */ "ld1 $\xFF\x02\x29, [$\x01], #24\0" |
| /* 4197 */ "ld1 $\xFF\x02\x2A, [$\x01], #24\0" |
| /* 4217 */ "ld1 $\xFF\x02\x2B, [$\x01], #48\0" |
| /* 4237 */ "ld1 $\xFF\x02\x2C, [$\x01], #24\0" |
| /* 4257 */ "ld1 $\xFF\x02\x2D, [$\x01], #48\0" |
| /* 4277 */ "ld1 $\xFF\x02\x26, [$\x01], #32\0" |
| /* 4297 */ "ld1 $\xFF\x02\x27, [$\x01], #16\0" |
| /* 4317 */ "ld1 $\xFF\x02\x28, [$\x01], #32\0" |
| /* 4337 */ "ld1 $\xFF\x02\x29, [$\x01], #16\0" |
| /* 4357 */ "ld1 $\xFF\x02\x2A, [$\x01], #16\0" |
| /* 4377 */ "ld1 $\xFF\x02\x2B, [$\x01], #32\0" |
| /* 4397 */ "ld1 $\xFF\x02\x2C, [$\x01], #16\0" |
| /* 4417 */ "ld1 $\xFF\x02\x2D, [$\x01], #32\0" |
| /* 4437 */ "ld1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4461 */ "ld1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4485 */ "ld1 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #2\0" |
| /* 4508 */ "ld1 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #4\0" |
| /* 4531 */ "ld1 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #8\0" |
| /* 4554 */ "ld1 $\xFF\x02\x31$\xFF\x04\x19, [$\x01], #1\0" |
| /* 4577 */ "ld2b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4601 */ "ld2d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4625 */ "ld2h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4649 */ "ld2r $\xFF\x02\x26, [$\x01], #2\0" |
| /* 4669 */ "ld2r $\xFF\x02\x27, [$\x01], #16\0" |
| /* 4690 */ "ld2r $\xFF\x02\x28, [$\x01], #16\0" |
| /* 4711 */ "ld2r $\xFF\x02\x29, [$\x01], #8\0" |
| /* 4731 */ "ld2r $\xFF\x02\x2A, [$\x01], #4\0" |
| /* 4751 */ "ld2r $\xFF\x02\x2B, [$\x01], #8\0" |
| /* 4771 */ "ld2r $\xFF\x02\x2C, [$\x01], #2\0" |
| /* 4791 */ "ld2r $\xFF\x02\x2D, [$\x01], #4\0" |
| /* 4811 */ "ld2 $\xFF\x02\x26, [$\x01], #32\0" |
| /* 4831 */ "ld2 $\xFF\x02\x28, [$\x01], #32\0" |
| /* 4851 */ "ld2 $\xFF\x02\x29, [$\x01], #16\0" |
| /* 4871 */ "ld2 $\xFF\x02\x2A, [$\x01], #16\0" |
| /* 4891 */ "ld2 $\xFF\x02\x2B, [$\x01], #32\0" |
| /* 4911 */ "ld2 $\xFF\x02\x2C, [$\x01], #16\0" |
| /* 4931 */ "ld2 $\xFF\x02\x2D, [$\x01], #32\0" |
| /* 4951 */ "ld2w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4975 */ "ld2 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #4\0" |
| /* 4998 */ "ld2 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #8\0" |
| /* 5021 */ "ld2 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #16\0" |
| /* 5045 */ "ld2 $\xFF\x02\x31$\xFF\x04\x19, [$\x01], #2\0" |
| /* 5068 */ "ld3b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 5092 */ "ld3d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 5116 */ "ld3h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 5140 */ "ld3r $\xFF\x02\x26, [$\x01], #3\0" |
| /* 5160 */ "ld3r $\xFF\x02\x27, [$\x01], #24\0" |
| /* 5181 */ "ld3r $\xFF\x02\x28, [$\x01], #24\0" |
| /* 5202 */ "ld3r $\xFF\x02\x29, [$\x01], #12\0" |
| /* 5223 */ "ld3r $\xFF\x02\x2A, [$\x01], #6\0" |
| /* 5243 */ "ld3r $\xFF\x02\x2B, [$\x01], #12\0" |
| /* 5264 */ "ld3r $\xFF\x02\x2C, [$\x01], #3\0" |
| /* 5284 */ "ld3r $\xFF\x02\x2D, [$\x01], #6\0" |
| /* 5304 */ "ld3 $\xFF\x02\x26, [$\x01], #48\0" |
| /* 5324 */ "ld3 $\xFF\x02\x28, [$\x01], #48\0" |
| /* 5344 */ "ld3 $\xFF\x02\x29, [$\x01], #24\0" |
| /* 5364 */ "ld3 $\xFF\x02\x2A, [$\x01], #24\0" |
| /* 5384 */ "ld3 $\xFF\x02\x2B, [$\x01], #48\0" |
| /* 5404 */ "ld3 $\xFF\x02\x2C, [$\x01], #24\0" |
| /* 5424 */ "ld3 $\xFF\x02\x2D, [$\x01], #48\0" |
| /* 5444 */ "ld3w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 5468 */ "ld3 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #6\0" |
| /* 5491 */ "ld3 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #12\0" |
| /* 5515 */ "ld3 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #24\0" |
| /* 5539 */ "ld3 $\xFF\x02\x31$\xFF\x04\x19, [$\x01], #3\0" |
| /* 5562 */ "ld4b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 5586 */ "ld4d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 5610 */ "ld4 $\xFF\x02\x26, [$\x01], #64\0" |
| /* 5630 */ "ld4 $\xFF\x02\x28, [$\x01], #64\0" |
| /* 5650 */ "ld4 $\xFF\x02\x29, [$\x01], #32\0" |
| /* 5670 */ "ld4 $\xFF\x02\x2A, [$\x01], #32\0" |
| /* 5690 */ "ld4 $\xFF\x02\x2B, [$\x01], #64\0" |
| /* 5710 */ "ld4 $\xFF\x02\x2C, [$\x01], #32\0" |
| /* 5730 */ "ld4 $\xFF\x02\x2D, [$\x01], #64\0" |
| /* 5750 */ "ld4h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 5774 */ "ld4r $\xFF\x02\x26, [$\x01], #4\0" |
| /* 5794 */ "ld4r $\xFF\x02\x27, [$\x01], #32\0" |
| /* 5815 */ "ld4r $\xFF\x02\x28, [$\x01], #32\0" |
| /* 5836 */ "ld4r $\xFF\x02\x29, [$\x01], #16\0" |
| /* 5857 */ "ld4r $\xFF\x02\x2A, [$\x01], #8\0" |
| /* 5877 */ "ld4r $\xFF\x02\x2B, [$\x01], #16\0" |
| /* 5898 */ "ld4r $\xFF\x02\x2C, [$\x01], #4\0" |
| /* 5918 */ "ld4r $\xFF\x02\x2D, [$\x01], #8\0" |
| /* 5938 */ "ld4w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 5962 */ "ld4 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #8\0" |
| /* 5985 */ "ld4 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #16\0" |
| /* 6009 */ "ld4 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #32\0" |
| /* 6033 */ "ld4 $\xFF\x02\x31$\xFF\x04\x19, [$\x01], #4\0" |
| /* 6056 */ "staddb $\x02, [$\x03]\0" |
| /* 6072 */ "staddh $\x02, [$\x03]\0" |
| /* 6088 */ "staddlb $\x02, [$\x03]\0" |
| /* 6105 */ "staddlh $\x02, [$\x03]\0" |
| /* 6122 */ "staddl $\x02, [$\x03]\0" |
| /* 6138 */ "stadd $\x02, [$\x03]\0" |
| /* 6153 */ "ldapurb $\x01, [$\x02]\0" |
| /* 6170 */ "ldapurh $\x01, [$\x02]\0" |
| /* 6187 */ "ldapursb $\x01, [$\x02]\0" |
| /* 6205 */ "ldapursh $\x01, [$\x02]\0" |
| /* 6223 */ "ldapursw $\x01, [$\x02]\0" |
| /* 6241 */ "ldapur $\x01, [$\x02]\0" |
| /* 6257 */ "stclrb $\x02, [$\x03]\0" |
| /* 6273 */ "stclrh $\x02, [$\x03]\0" |
| /* 6289 */ "stclrlb $\x02, [$\x03]\0" |
| /* 6306 */ "stclrlh $\x02, [$\x03]\0" |
| /* 6323 */ "stclrl $\x02, [$\x03]\0" |
| /* 6339 */ "stclr $\x02, [$\x03]\0" |
| /* 6354 */ "steorb $\x02, [$\x03]\0" |
| /* 6370 */ "steorh $\x02, [$\x03]\0" |
| /* 6386 */ "steorlb $\x02, [$\x03]\0" |
| /* 6403 */ "steorlh $\x02, [$\x03]\0" |
| /* 6420 */ "steorl $\x02, [$\x03]\0" |
| /* 6436 */ "steor $\x02, [$\x03]\0" |
| /* 6451 */ "ldff1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6477 */ "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6503 */ "ldff1b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6529 */ "ldff1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6555 */ "ldff1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6581 */ "ldff1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6607 */ "ldff1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6633 */ "ldff1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6659 */ "ldff1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6686 */ "ldff1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6713 */ "ldff1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6740 */ "ldff1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6767 */ "ldff1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6794 */ "ldff1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6821 */ "ldff1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6847 */ "ldff1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6873 */ "ldg $\x01, [$\x03]\0" |
| /* 6886 */ "ldnf1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6912 */ "ldnf1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6938 */ "ldnf1b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6964 */ "ldnf1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6990 */ "ldnf1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7016 */ "ldnf1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7042 */ "ldnf1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7068 */ "ldnf1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7094 */ "ldnf1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7121 */ "ldnf1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7148 */ "ldnf1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7175 */ "ldnf1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7202 */ "ldnf1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7229 */ "ldnf1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7256 */ "ldnf1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7282 */ "ldnf1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7308 */ "ldnp $\x01, $\x02, [$\x03]\0" |
| /* 7326 */ "ldnt1b $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7352 */ "ldnt1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 7380 */ "ldnt1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 7408 */ "ldnt1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7434 */ "ldnt1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 7462 */ "ldnt1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7488 */ "ldnt1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 7516 */ "ldnt1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 7544 */ "ldnt1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 7573 */ "ldnt1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 7602 */ "ldnt1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 7631 */ "ldnt1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 7660 */ "ldnt1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 7689 */ "ldnt1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7715 */ "ldnt1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 7743 */ "ldnt1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 7771 */ "ldp $\x01, $\x02, [$\x03]\0" |
| /* 7788 */ "ldpsw $\x01, $\x02, [$\x03]\0" |
| /* 7807 */ "ldraa $\x01, [$\x02]\0" |
| /* 7822 */ "ldrab $\x01, [$\x02]\0" |
| /* 7837 */ "ldrb $\x01, [$\x02, $\x03]\0" |
| /* 7855 */ "ldrb $\x01, [$\x02]\0" |
| /* 7869 */ "ldr $\x01, [$\x02, $\x03]\0" |
| /* 7886 */ "ldr $\x01, [$\x02]\0" |
| /* 7899 */ "ldrh $\x01, [$\x02, $\x03]\0" |
| /* 7917 */ "ldrh $\x01, [$\x02]\0" |
| /* 7931 */ "ldrsb $\x01, [$\x02, $\x03]\0" |
| /* 7950 */ "ldrsb $\x01, [$\x02]\0" |
| /* 7965 */ "ldrsh $\x01, [$\x02, $\x03]\0" |
| /* 7984 */ "ldrsh $\x01, [$\x02]\0" |
| /* 7999 */ "ldrsw $\x01, [$\x02, $\x03]\0" |
| /* 8018 */ "ldrsw $\x01, [$\x02]\0" |
| /* 8033 */ "ldr $\xFF\x01\x07, [$\x02]\0" |
| /* 8048 */ "stsetb $\x02, [$\x03]\0" |
| /* 8064 */ "stseth $\x02, [$\x03]\0" |
| /* 8080 */ "stsetlb $\x02, [$\x03]\0" |
| /* 8097 */ "stsetlh $\x02, [$\x03]\0" |
| /* 8114 */ "stsetl $\x02, [$\x03]\0" |
| /* 8130 */ "stset $\x02, [$\x03]\0" |
| /* 8145 */ "stsmaxb $\x02, [$\x03]\0" |
| /* 8162 */ "stsmaxh $\x02, [$\x03]\0" |
| /* 8179 */ "stsmaxlb $\x02, [$\x03]\0" |
| /* 8197 */ "stsmaxlh $\x02, [$\x03]\0" |
| /* 8215 */ "stsmaxl $\x02, [$\x03]\0" |
| /* 8232 */ "stsmax $\x02, [$\x03]\0" |
| /* 8248 */ "stsminb $\x02, [$\x03]\0" |
| /* 8265 */ "stsminh $\x02, [$\x03]\0" |
| /* 8282 */ "stsminlb $\x02, [$\x03]\0" |
| /* 8300 */ "stsminlh $\x02, [$\x03]\0" |
| /* 8318 */ "stsminl $\x02, [$\x03]\0" |
| /* 8335 */ "stsmin $\x02, [$\x03]\0" |
| /* 8351 */ "ldtrb $\x01, [$\x02]\0" |
| /* 8366 */ "ldtrh $\x01, [$\x02]\0" |
| /* 8381 */ "ldtrsb $\x01, [$\x02]\0" |
| /* 8397 */ "ldtrsh $\x01, [$\x02]\0" |
| /* 8413 */ "ldtrsw $\x01, [$\x02]\0" |
| /* 8429 */ "ldtr $\x01, [$\x02]\0" |
| /* 8443 */ "stumaxb $\x02, [$\x03]\0" |
| /* 8460 */ "stumaxh $\x02, [$\x03]\0" |
| /* 8477 */ "stumaxlb $\x02, [$\x03]\0" |
| /* 8495 */ "stumaxlh $\x02, [$\x03]\0" |
| /* 8513 */ "stumaxl $\x02, [$\x03]\0" |
| /* 8530 */ "stumax $\x02, [$\x03]\0" |
| /* 8546 */ "stuminb $\x02, [$\x03]\0" |
| /* 8563 */ "stuminh $\x02, [$\x03]\0" |
| /* 8580 */ "stuminlb $\x02, [$\x03]\0" |
| /* 8598 */ "stuminlh $\x02, [$\x03]\0" |
| /* 8616 */ "stuminl $\x02, [$\x03]\0" |
| /* 8633 */ "stumin $\x02, [$\x03]\0" |
| /* 8649 */ "ldurb $\x01, [$\x02]\0" |
| /* 8664 */ "ldur $\x01, [$\x02]\0" |
| /* 8678 */ "ldurh $\x01, [$\x02]\0" |
| /* 8693 */ "ldursb $\x01, [$\x02]\0" |
| /* 8709 */ "ldursh $\x01, [$\x02]\0" |
| /* 8725 */ "ldursw $\x01, [$\x02]\0" |
| /* 8741 */ "mul $\x01, $\x02, $\x03\0" |
| /* 8756 */ "mneg $\x01, $\x02, $\x03\0" |
| /* 8772 */ "mvn $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b\0" |
| /* 8795 */ "mvn $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b\0" |
| /* 8816 */ "mvn $\x01, $\x03\0" |
| /* 8827 */ "mvn $\x01, $\x03$\xFF\x04\x02\0" |
| /* 8842 */ "orn $\x01, $\x02, $\x03\0" |
| /* 8857 */ "movs $\xFF\x01\x06, $\xFF\x02\x06\0" |
| /* 8873 */ "mov $\x01, $\x03\0" |
| /* 8884 */ "orr $\x01, $\x02, $\x03\0" |
| /* 8899 */ "mov $\xFF\x01\x06, $\xFF\x02\x06\0" |
| /* 8914 */ "orr $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0" |
| /* 8935 */ "orr $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0" |
| /* 8956 */ "orr $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0" |
| /* 8977 */ "mov $\xFF\x01\x10, $\xFF\x02\x10\0" |
| /* 8992 */ "mov $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b\0" |
| /* 9015 */ "mov $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b\0" |
| /* 9036 */ "pacia1716\0" |
| /* 9046 */ "paciasp\0" |
| /* 9054 */ "paciaz\0" |
| /* 9061 */ "pacib1716\0" |
| /* 9071 */ "pacibsp\0" |
| /* 9079 */ "pacibz\0" |
| /* 9086 */ "prfb $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 9110 */ "prfb $\xFF\x01\x33, $\xFF\x02\x07, [$\x03]\0" |
| /* 9132 */ "prfb $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| /* 9156 */ "prfd $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 9180 */ "prfd $\xFF\x01\x33, $\xFF\x02\x07, [$\x03]\0" |
| /* 9202 */ "prfd $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| /* 9226 */ "prfh $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 9250 */ "prfh $\xFF\x01\x33, $\xFF\x02\x07, [$\x03]\0" |
| /* 9272 */ "prfh $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| /* 9296 */ "prfm $\xFF\x01\x34, [$\x02, $\x03]\0" |
| /* 9316 */ "prfm $\xFF\x01\x34, [$\x02]\0" |
| /* 9332 */ "prfum $\xFF\x01\x34, [$\x02]\0" |
| /* 9349 */ "prfw $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 9373 */ "prfw $\xFF\x01\x33, $\xFF\x02\x07, [$\x03]\0" |
| /* 9395 */ "prfw $\xFF\x01\x33, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| /* 9419 */ "ptrues $\xFF\x01\x06\0" |
| /* 9431 */ "ptrues $\xFF\x01\x10\0" |
| /* 9443 */ "ptrues $\xFF\x01\x09\0" |
| /* 9455 */ "ptrues $\xFF\x01\x0B\0" |
| /* 9467 */ "ptrue $\xFF\x01\x06\0" |
| /* 9478 */ "ptrue $\xFF\x01\x10\0" |
| /* 9489 */ "ptrue $\xFF\x01\x09\0" |
| /* 9500 */ "ptrue $\xFF\x01\x0B\0" |
| /* 9511 */ "ret\0" |
| /* 9515 */ "ngcs $\x01, $\x03\0" |
| /* 9527 */ "ngc $\x01, $\x03\0" |
| /* 9538 */ "asr $\x01, $\x02, $\x03\0" |
| /* 9553 */ "sxtb $\x01, $\x02\0" |
| /* 9565 */ "sxth $\x01, $\x02\0" |
| /* 9577 */ "sxtw $\x01, $\x02\0" |
| /* 9589 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x06\0" |
| /* 9612 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/m, $\xFF\x03\x10\0" |
| /* 9635 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/m, $\xFF\x03\x09\0" |
| /* 9658 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/m, $\xFF\x03\x0B\0" |
| /* 9681 */ "smull $\x01, $\x02, $\x03\0" |
| /* 9698 */ "smnegl $\x01, $\x02, $\x03\0" |
| /* 9716 */ "sqdecb $\x01\0" |
| /* 9726 */ "sqdecb $\x01, $\xFF\x03\x0E\0" |
| /* 9742 */ "sqdecb $\x01, $\xFF\x02\x35\0" |
| /* 9758 */ "sqdecb $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0" |
| /* 9780 */ "sqdecd $\x01\0" |
| /* 9790 */ "sqdecd $\x01, $\xFF\x03\x0E\0" |
| /* 9806 */ "sqdecd $\x01, $\xFF\x02\x35\0" |
| /* 9822 */ "sqdecd $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0" |
| /* 9844 */ "sqdecd $\xFF\x01\x10\0" |
| /* 9856 */ "sqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| /* 9874 */ "sqdech $\x01\0" |
| /* 9884 */ "sqdech $\x01, $\xFF\x03\x0E\0" |
| /* 9900 */ "sqdech $\x01, $\xFF\x02\x35\0" |
| /* 9916 */ "sqdech $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0" |
| /* 9938 */ "sqdech $\xFF\x01\x09\0" |
| /* 9950 */ "sqdech $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| /* 9968 */ "sqdecw $\x01\0" |
| /* 9978 */ "sqdecw $\x01, $\xFF\x03\x0E\0" |
| /* 9994 */ "sqdecw $\x01, $\xFF\x02\x35\0" |
| /* 10010 */ "sqdecw $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0" |
| /* 10032 */ "sqdecw $\xFF\x01\x0B\0" |
| /* 10044 */ "sqdecw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| /* 10062 */ "sqincb $\x01\0" |
| /* 10072 */ "sqincb $\x01, $\xFF\x03\x0E\0" |
| /* 10088 */ "sqincb $\x01, $\xFF\x02\x35\0" |
| /* 10104 */ "sqincb $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0" |
| /* 10126 */ "sqincd $\x01\0" |
| /* 10136 */ "sqincd $\x01, $\xFF\x03\x0E\0" |
| /* 10152 */ "sqincd $\x01, $\xFF\x02\x35\0" |
| /* 10168 */ "sqincd $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0" |
| /* 10190 */ "sqincd $\xFF\x01\x10\0" |
| /* 10202 */ "sqincd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| /* 10220 */ "sqinch $\x01\0" |
| /* 10230 */ "sqinch $\x01, $\xFF\x03\x0E\0" |
| /* 10246 */ "sqinch $\x01, $\xFF\x02\x35\0" |
| /* 10262 */ "sqinch $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0" |
| /* 10284 */ "sqinch $\xFF\x01\x09\0" |
| /* 10296 */ "sqinch $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| /* 10314 */ "sqincw $\x01\0" |
| /* 10324 */ "sqincw $\x01, $\xFF\x03\x0E\0" |
| /* 10340 */ "sqincw $\x01, $\xFF\x02\x35\0" |
| /* 10356 */ "sqincw $\x01, $\xFF\x02\x35, $\xFF\x03\x0E\0" |
| /* 10378 */ "sqincw $\xFF\x01\x0B\0" |
| /* 10390 */ "sqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| /* 10408 */ "st1b $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 10432 */ "st1b $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| /* 10456 */ "st1d $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 10480 */ "st1h $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 10504 */ "st1h $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| /* 10528 */ "st1w $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 10552 */ "st1w $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| /* 10576 */ "st1b $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0" |
| /* 10598 */ "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| /* 10620 */ "st1b $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| /* 10642 */ "st1b $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0" |
| /* 10664 */ "st1d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0" |
| /* 10686 */ "st1 $\xFF\x02\x26, [$\x01], #64\0" |
| /* 10706 */ "st1 $\xFF\x02\x27, [$\x01], #32\0" |
| /* 10726 */ "st1 $\xFF\x02\x28, [$\x01], #64\0" |
| /* 10746 */ "st1 $\xFF\x02\x29, [$\x01], #32\0" |
| /* 10766 */ "st1 $\xFF\x02\x2A, [$\x01], #32\0" |
| /* 10786 */ "st1 $\xFF\x02\x2B, [$\x01], #64\0" |
| /* 10806 */ "st1 $\xFF\x02\x2C, [$\x01], #32\0" |
| /* 10826 */ "st1 $\xFF\x02\x2D, [$\x01], #64\0" |
| /* 10846 */ "st1h $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0" |
| /* 10868 */ "st1h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| /* 10890 */ "st1h $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0" |
| /* 10912 */ "st1 $\xFF\x02\x26, [$\x01], #16\0" |
| /* 10932 */ "st1 $\xFF\x02\x27, [$\x01], #8\0" |
| /* 10951 */ "st1 $\xFF\x02\x28, [$\x01], #16\0" |
| /* 10971 */ "st1 $\xFF\x02\x29, [$\x01], #8\0" |
| /* 10990 */ "st1 $\xFF\x02\x2A, [$\x01], #8\0" |
| /* 11009 */ "st1 $\xFF\x02\x2B, [$\x01], #16\0" |
| /* 11029 */ "st1 $\xFF\x02\x2C, [$\x01], #8\0" |
| /* 11048 */ "st1 $\xFF\x02\x2D, [$\x01], #16\0" |
| /* 11068 */ "st1 $\xFF\x02\x26, [$\x01], #48\0" |
| /* 11088 */ "st1 $\xFF\x02\x27, [$\x01], #24\0" |
| /* 11108 */ "st1 $\xFF\x02\x28, [$\x01], #48\0" |
| /* 11128 */ "st1 $\xFF\x02\x29, [$\x01], #24\0" |
| /* 11148 */ "st1 $\xFF\x02\x2A, [$\x01], #24\0" |
| /* 11168 */ "st1 $\xFF\x02\x2B, [$\x01], #48\0" |
| /* 11188 */ "st1 $\xFF\x02\x2C, [$\x01], #24\0" |
| /* 11208 */ "st1 $\xFF\x02\x2D, [$\x01], #48\0" |
| /* 11228 */ "st1 $\xFF\x02\x26, [$\x01], #32\0" |
| /* 11248 */ "st1 $\xFF\x02\x27, [$\x01], #16\0" |
| /* 11268 */ "st1 $\xFF\x02\x28, [$\x01], #32\0" |
| /* 11288 */ "st1 $\xFF\x02\x29, [$\x01], #16\0" |
| /* 11308 */ "st1 $\xFF\x02\x2A, [$\x01], #16\0" |
| /* 11328 */ "st1 $\xFF\x02\x2B, [$\x01], #32\0" |
| /* 11348 */ "st1 $\xFF\x02\x2C, [$\x01], #16\0" |
| /* 11368 */ "st1 $\xFF\x02\x2D, [$\x01], #32\0" |
| /* 11388 */ "st1w $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0" |
| /* 11410 */ "st1w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0" |
| /* 11432 */ "st1 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #2\0" |
| /* 11455 */ "st1 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #4\0" |
| /* 11478 */ "st1 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #8\0" |
| /* 11501 */ "st1 $\xFF\x02\x31$\xFF\x03\x19, [$\x01], #1\0" |
| /* 11524 */ "st2b $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| /* 11546 */ "st2d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0" |
| /* 11568 */ "st2g $\x01, [$\x02]\0" |
| /* 11582 */ "st2h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| /* 11604 */ "st2 $\xFF\x02\x26, [$\x01], #32\0" |
| /* 11624 */ "st2 $\xFF\x02\x28, [$\x01], #32\0" |
| /* 11644 */ "st2 $\xFF\x02\x29, [$\x01], #16\0" |
| /* 11664 */ "st2 $\xFF\x02\x2A, [$\x01], #16\0" |
| /* 11684 */ "st2 $\xFF\x02\x2B, [$\x01], #32\0" |
| /* 11704 */ "st2 $\xFF\x02\x2C, [$\x01], #16\0" |
| /* 11724 */ "st2 $\xFF\x02\x2D, [$\x01], #32\0" |
| /* 11744 */ "st2w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0" |
| /* 11766 */ "st2 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #4\0" |
| /* 11789 */ "st2 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #8\0" |
| /* 11812 */ "st2 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #16\0" |
| /* 11836 */ "st2 $\xFF\x02\x31$\xFF\x03\x19, [$\x01], #2\0" |
| /* 11859 */ "st3b $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| /* 11881 */ "st3d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0" |
| /* 11903 */ "st3h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| /* 11925 */ "st3 $\xFF\x02\x26, [$\x01], #48\0" |
| /* 11945 */ "st3 $\xFF\x02\x28, [$\x01], #48\0" |
| /* 11965 */ "st3 $\xFF\x02\x29, [$\x01], #24\0" |
| /* 11985 */ "st3 $\xFF\x02\x2A, [$\x01], #24\0" |
| /* 12005 */ "st3 $\xFF\x02\x2B, [$\x01], #48\0" |
| /* 12025 */ "st3 $\xFF\x02\x2C, [$\x01], #24\0" |
| /* 12045 */ "st3 $\xFF\x02\x2D, [$\x01], #48\0" |
| /* 12065 */ "st3w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0" |
| /* 12087 */ "st3 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #6\0" |
| /* 12110 */ "st3 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #12\0" |
| /* 12134 */ "st3 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #24\0" |
| /* 12158 */ "st3 $\xFF\x02\x31$\xFF\x03\x19, [$\x01], #3\0" |
| /* 12181 */ "st4b $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| /* 12203 */ "st4d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0" |
| /* 12225 */ "st4 $\xFF\x02\x26, [$\x01], #64\0" |
| /* 12245 */ "st4 $\xFF\x02\x28, [$\x01], #64\0" |
| /* 12265 */ "st4 $\xFF\x02\x29, [$\x01], #32\0" |
| /* 12285 */ "st4 $\xFF\x02\x2A, [$\x01], #32\0" |
| /* 12305 */ "st4 $\xFF\x02\x2B, [$\x01], #64\0" |
| /* 12325 */ "st4 $\xFF\x02\x2C, [$\x01], #32\0" |
| /* 12345 */ "st4 $\xFF\x02\x2D, [$\x01], #64\0" |
| /* 12365 */ "st4h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| /* 12387 */ "st4w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0" |
| /* 12409 */ "st4 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #8\0" |
| /* 12432 */ "st4 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #16\0" |
| /* 12456 */ "st4 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #32\0" |
| /* 12480 */ "st4 $\xFF\x02\x31$\xFF\x03\x19, [$\x01], #4\0" |
| /* 12503 */ "stg $\x01, [$\x02]\0" |
| /* 12516 */ "stgp $\x01, $\x02, [$\x03]\0" |
| /* 12534 */ "stlurb $\x01, [$\x02]\0" |
| /* 12550 */ "stlurh $\x01, [$\x02]\0" |
| /* 12566 */ "stlur $\x01, [$\x02]\0" |
| /* 12581 */ "stnp $\x01, $\x02, [$\x03]\0" |
| /* 12599 */ "stnt1b $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| /* 12623 */ "stnt1b $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 12649 */ "stnt1b $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| /* 12675 */ "stnt1d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]\0" |
| /* 12699 */ "stnt1d $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 12725 */ "stnt1h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| /* 12749 */ "stnt1h $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 12775 */ "stnt1h $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| /* 12801 */ "stnt1w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]\0" |
| /* 12825 */ "stnt1w $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 12851 */ "stnt1w $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| /* 12877 */ "stp $\x01, $\x02, [$\x03]\0" |
| /* 12894 */ "strb $\x01, [$\x02, $\x03]\0" |
| /* 12912 */ "strb $\x01, [$\x02]\0" |
| /* 12926 */ "str $\x01, [$\x02, $\x03]\0" |
| /* 12943 */ "str $\x01, [$\x02]\0" |
| /* 12956 */ "strh $\x01, [$\x02, $\x03]\0" |
| /* 12974 */ "strh $\x01, [$\x02]\0" |
| /* 12988 */ "str $\xFF\x01\x07, [$\x02]\0" |
| /* 13003 */ "sttrb $\x01, [$\x02]\0" |
| /* 13018 */ "sttrh $\x01, [$\x02]\0" |
| /* 13033 */ "sttr $\x01, [$\x02]\0" |
| /* 13047 */ "sturb $\x01, [$\x02]\0" |
| /* 13062 */ "stur $\x01, [$\x02]\0" |
| /* 13076 */ "sturh $\x01, [$\x02]\0" |
| /* 13091 */ "stz2g $\x01, [$\x02]\0" |
| /* 13106 */ "stzg $\x01, [$\x02]\0" |
| /* 13120 */ "cmp $\x02, $\xFF\x03\x01\0" |
| /* 13133 */ "cmp $\x02, $\x03\0" |
| /* 13144 */ "cmp $\x02, $\x03$\xFF\x04\x02\0" |
| /* 13159 */ "negs $\x01, $\x03\0" |
| /* 13171 */ "negs $\x01, $\x03$\xFF\x04\x02\0" |
| /* 13187 */ "subs $\x01, $\x02, $\x03\0" |
| /* 13203 */ "cmp $\x02, $\x03$\xFF\x04\x03\0" |
| /* 13218 */ "neg $\x01, $\x03\0" |
| /* 13229 */ "neg $\x01, $\x03$\xFF\x04\x02\0" |
| /* 13244 */ "sub $\x01, $\x02, $\x03\0" |
| /* 13259 */ "sys $\x01, $\xFF\x02\x36, $\xFF\x03\x36, $\x04\0" |
| /* 13282 */ "lsr $\x01, $\x02, $\x03\0" |
| /* 13297 */ "uxtb $\x01, $\x02\0" |
| /* 13309 */ "uxth $\x01, $\x02\0" |
| /* 13321 */ "uxtw $\x01, $\x02\0" |
| /* 13333 */ "umull $\x01, $\x02, $\x03\0" |
| /* 13350 */ "mov $\x01, $\xFF\x02\x0C.s$\xFF\x03\x19\0" |
| /* 13369 */ "mov $\x01, $\xFF\x02\x0C.d$\xFF\x03\x19\0" |
| /* 13388 */ "umnegl $\x01, $\x02, $\x03\0" |
| /* 13406 */ "uqdecb $\x01\0" |
| /* 13416 */ "uqdecb $\x01, $\xFF\x03\x0E\0" |
| /* 13432 */ "uqdecd $\x01\0" |
| /* 13442 */ "uqdecd $\x01, $\xFF\x03\x0E\0" |
| /* 13458 */ "uqdecd $\xFF\x01\x10\0" |
| /* 13470 */ "uqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| /* 13488 */ "uqdech $\x01\0" |
| /* 13498 */ "uqdech $\x01, $\xFF\x03\x0E\0" |
| /* 13514 */ "uqdech $\xFF\x01\x09\0" |
| /* 13526 */ "uqdech $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| /* 13544 */ "uqdecw $\x01\0" |
| /* 13554 */ "uqdecw $\x01, $\xFF\x03\x0E\0" |
| /* 13570 */ "uqdecw $\xFF\x01\x0B\0" |
| /* 13582 */ "uqdecw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| /* 13600 */ "uqincb $\x01\0" |
| /* 13610 */ "uqincb $\x01, $\xFF\x03\x0E\0" |
| /* 13626 */ "uqincd $\x01\0" |
| /* 13636 */ "uqincd $\x01, $\xFF\x03\x0E\0" |
| /* 13652 */ "uqincd $\xFF\x01\x10\0" |
| /* 13664 */ "uqincd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| /* 13682 */ "uqinch $\x01\0" |
| /* 13692 */ "uqinch $\x01, $\xFF\x03\x0E\0" |
| /* 13708 */ "uqinch $\xFF\x01\x09\0" |
| /* 13720 */ "uqinch $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| /* 13738 */ "uqincw $\x01\0" |
| /* 13748 */ "uqincw $\x01, $\xFF\x03\x0E\0" |
| /* 13764 */ "uqincw $\xFF\x01\x0B\0" |
| /* 13776 */ "uqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| /* 13794 */ "xpaclri\0" |
| ; |
| |
| #ifndef NDEBUG |
| static struct SortCheck { |
| SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) { |
| assert(std::is_sorted( |
| OpToPatterns.begin(), OpToPatterns.end(), |
| [](const PatternsForOpcode &L, const PatternsForOpcode &R) { |
| return L.Opcode < R.Opcode; |
| }) && |
| "tablegen failed to sort opcode patterns"); |
| } |
| } sortCheckVar(OpToPatterns); |
| #endif |
| |
| AliasMatchingData M { |
| makeArrayRef(OpToPatterns), |
| makeArrayRef(Patterns), |
| makeArrayRef(Conds), |
| StringRef(AsmStrings, array_lengthof(AsmStrings)), |
| &AArch64InstPrinterValidateMCOperand, |
| }; |
| const char *AsmString = matchAliasPatterns(MI, &STI, M); |
| if (!AsmString) return false; |
| |
| unsigned I = 0; |
| while (AsmString[I] != ' ' && AsmString[I] != '\t' && |
| AsmString[I] != '$' && AsmString[I] != '\0') |
| ++I; |
| OS << '\t' << StringRef(AsmString, I); |
| if (AsmString[I] != '\0') { |
| if (AsmString[I] == ' ' || AsmString[I] == '\t') { |
| OS << '\t'; |
| ++I; |
| } |
| do { |
| if (AsmString[I] == '$') { |
| ++I; |
| if (AsmString[I] == (char)0xff) { |
| ++I; |
| int OpIdx = AsmString[I++] - 1; |
| int PrintMethodIdx = AsmString[I++] - 1; |
| printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, STI, OS); |
| } else |
| printOperand(MI, unsigned(AsmString[I++]) - 1, STI, OS); |
| } else { |
| OS << AsmString[I++]; |
| } |
| } while (AsmString[I] != '\0'); |
| } |
| |
| return true; |
| } |
| |
| void AArch64InstPrinter::printCustomAliasOperand( |
| const MCInst *MI, unsigned OpIdx, |
| unsigned PrintMethodIdx, |
| const MCSubtargetInfo &STI, |
| raw_ostream &OS) { |
| switch (PrintMethodIdx) { |
| default: |
| llvm_unreachable("Unknown PrintMethod kind"); |
| break; |
| case 0: |
| printAddSubImm(MI, OpIdx, STI, OS); |
| break; |
| case 1: |
| printShifter(MI, OpIdx, STI, OS); |
| break; |
| case 2: |
| printArithExtend(MI, OpIdx, STI, OS); |
| break; |
| case 3: |
| printLogicalImm<int32_t>(MI, OpIdx, STI, OS); |
| break; |
| case 4: |
| printLogicalImm<int64_t>(MI, OpIdx, STI, OS); |
| break; |
| case 5: |
| printSVERegOp<'b'>(MI, OpIdx, STI, OS); |
| break; |
| case 6: |
| printSVERegOp<>(MI, OpIdx, STI, OS); |
| break; |
| case 7: |
| printLogicalImm<int8_t>(MI, OpIdx, STI, OS); |
| break; |
| case 8: |
| printSVERegOp<'h'>(MI, OpIdx, STI, OS); |
| break; |
| case 9: |
| printLogicalImm<int16_t>(MI, OpIdx, STI, OS); |
| break; |
| case 10: |
| printSVERegOp<'s'>(MI, OpIdx, STI, OS); |
| break; |
| case 11: |
| printVRegOperand(MI, OpIdx, STI, OS); |
| break; |
| case 12: |
| printImm(MI, OpIdx, STI, OS); |
| break; |
| case 13: |
| printSVEPattern(MI, OpIdx, STI, OS); |
| break; |
| case 14: |
| printImm8OptLsl<int8_t>(MI, OpIdx, STI, OS); |
| break; |
| case 15: |
| printSVERegOp<'d'>(MI, OpIdx, STI, OS); |
| break; |
| case 16: |
| printImm8OptLsl<int64_t>(MI, OpIdx, STI, OS); |
| break; |
| case 17: |
| printImm8OptLsl<int16_t>(MI, OpIdx, STI, OS); |
| break; |
| case 18: |
| printImm8OptLsl<int32_t>(MI, OpIdx, STI, OS); |
| break; |
| case 19: |
| printInverseCondCode(MI, OpIdx, STI, OS); |
| break; |
| case 20: |
| printSVELogicalImm<int16_t>(MI, OpIdx, STI, OS); |
| break; |
| case 21: |
| printSVELogicalImm<int32_t>(MI, OpIdx, STI, OS); |
| break; |
| case 22: |
| printSVELogicalImm<int64_t>(MI, OpIdx, STI, OS); |
| break; |
| case 23: |
| printZPRasFPR<8>(MI, OpIdx, STI, OS); |
| break; |
| case 24: |
| printVectorIndex(MI, OpIdx, STI, OS); |
| break; |
| case 25: |
| printZPRasFPR<64>(MI, OpIdx, STI, OS); |
| break; |
| case 26: |
| printZPRasFPR<16>(MI, OpIdx, STI, OS); |
| break; |
| case 27: |
| printSVERegOp<'q'>(MI, OpIdx, STI, OS); |
| break; |
| case 28: |
| printZPRasFPR<128>(MI, OpIdx, STI, OS); |
| break; |
| case 29: |
| printZPRasFPR<32>(MI, OpIdx, STI, OS); |
| break; |
| case 30: |
| printFPImmOperand(MI, OpIdx, STI, OS); |
| break; |
| case 31: |
| printTypedVectorList<0,'d'>(MI, OpIdx, STI, OS); |
| break; |
| case 32: |
| printTypedVectorList<0,'s'>(MI, OpIdx, STI, OS); |
| break; |
| case 33: |
| printBTIHintOp(MI, OpIdx, STI, OS); |
| break; |
| case 34: |
| printPSBHintOp(MI, OpIdx, STI, OS); |
| break; |
| case 35: |
| printTypedVectorList<0,'h'>(MI, OpIdx, STI, OS); |
| break; |
| case 36: |
| printTypedVectorList<0,'b'>(MI, OpIdx, STI, OS); |
| break; |
| case 37: |
| printTypedVectorList<16, 'b'>(MI, OpIdx, STI, OS); |
| break; |
| case 38: |
| printTypedVectorList<1, 'd'>(MI, OpIdx, STI, OS); |
| break; |
| case 39: |
| printTypedVectorList<2, 'd'>(MI, OpIdx, STI, OS); |
| break; |
| case 40: |
| printTypedVectorList<2, 's'>(MI, OpIdx, STI, OS); |
| break; |
| case 41: |
| printTypedVectorList<4, 'h'>(MI, OpIdx, STI, OS); |
| break; |
| case 42: |
| printTypedVectorList<4, 's'>(MI, OpIdx, STI, OS); |
| break; |
| case 43: |
| printTypedVectorList<8, 'b'>(MI, OpIdx, STI, OS); |
| break; |
| case 44: |
| printTypedVectorList<8, 'h'>(MI, OpIdx, STI, OS); |
| break; |
| case 45: |
| printTypedVectorList<0, 'h'>(MI, OpIdx, STI, OS); |
| break; |
| case 46: |
| printTypedVectorList<0, 's'>(MI, OpIdx, STI, OS); |
| break; |
| case 47: |
| printTypedVectorList<0, 'd'>(MI, OpIdx, STI, OS); |
| break; |
| case 48: |
| printTypedVectorList<0, 'b'>(MI, OpIdx, STI, OS); |
| break; |
| case 49: |
| printImmHex(MI, OpIdx, STI, OS); |
| break; |
| case 50: |
| printPrefetchOp<true>(MI, OpIdx, STI, OS); |
| break; |
| case 51: |
| printPrefetchOp(MI, OpIdx, STI, OS); |
| break; |
| case 52: |
| printGPR64as32(MI, OpIdx, STI, OS); |
| break; |
| case 53: |
| printSysCROperand(MI, OpIdx, STI, OS); |
| break; |
| } |
| } |
| |
| static bool AArch64InstPrinterValidateMCOperand(const MCOperand &MCOp, |
| const MCSubtargetInfo &STI, |
| unsigned PredicateIndex) { |
| switch (PredicateIndex) { |
| default: |
| llvm_unreachable("Unknown MCOperandPredicate kind"); |
| break; |
| case 1: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int8_t>(Val); |
| |
| } |
| case 2: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val); |
| |
| } |
| case 3: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val); |
| |
| } |
| case 4: { |
| |
| return MCOp.isImm() && |
| MCOp.getImm() != AArch64CC::AL && |
| MCOp.getImm() != AArch64CC::NV; |
| |
| } |
| case 5: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val) && |
| AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); |
| |
| } |
| case 6: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val) && |
| AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); |
| |
| } |
| case 7: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int64_t>(Val) && |
| AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); |
| |
| } |
| case 8: { |
| |
| // "bti" is an alias to "hint" only for certain values of CRm:Op2 fields. |
| if (!MCOp.isImm()) |
| return false; |
| return AArch64BTIHint::lookupBTIByEncoding((MCOp.getImm() ^ 32) >> 1) != nullptr; |
| |
| } |
| case 9: { |
| |
| // Check, if operand is valid, to fix exhaustive aliasing in disassembly. |
| // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields. |
| if (!MCOp.isImm()) |
| return false; |
| return AArch64PSBHint::lookupPSBByEncoding(MCOp.getImm()) != nullptr; |
| |
| } |
| } |
| } |
| |
| #endif // PRINT_ALIAS_INSTR |
