Don't use global variables for CPUID
CPUID tracks device capabilities such as the availability of SSE
instructions, core count, and processor affinity. In order to avoid
costly system calls to determine this information, CPUID used several
static global variables initialized at startup.
However, in practice this added unnecessary complexity to CPUID and
doesn't actually improve performance.
This CL doesn't touch the OpenGL CPUID.
Bug: b/175073772
Change-Id: If69100014cec3e4aaaf7562196034d00c2bd5725
Reviewed-on: https://swiftshader-review.googlesource.com/c/SwiftShader/+/56508
Kokoro-Result: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nicolas Capens <nicolascapens@google.com>
Tested-by: Sean Risser <srisser@google.com>
Commit-Queue: Sean Risser <srisser@google.com>
diff --git a/src/Reactor/CPUID.cpp b/src/Reactor/CPUID.cpp
index 12637a7..98e267e 100644
--- a/src/Reactor/CPUID.cpp
+++ b/src/Reactor/CPUID.cpp
@@ -29,137 +29,6 @@
namespace rr {
-bool CPUID::MMX = detectMMX();
-bool CPUID::CMOV = detectCMOV();
-bool CPUID::SSE = detectSSE();
-bool CPUID::SSE2 = detectSSE2();
-bool CPUID::SSE3 = detectSSE3();
-bool CPUID::SSSE3 = detectSSSE3();
-bool CPUID::SSE4_1 = detectSSE4_1();
-
-bool CPUID::enableMMX = true;
-bool CPUID::enableCMOV = true;
-bool CPUID::enableSSE = true;
-bool CPUID::enableSSE2 = true;
-bool CPUID::enableSSE3 = true;
-bool CPUID::enableSSSE3 = true;
-bool CPUID::enableSSE4_1 = true;
-
-void CPUID::setEnableMMX(bool enable)
-{
- enableMMX = enable;
-
- if(!enableMMX)
- {
- enableSSE = false;
- enableSSE2 = false;
- enableSSE3 = false;
- enableSSSE3 = false;
- enableSSE4_1 = false;
- }
-}
-
-void CPUID::setEnableCMOV(bool enable)
-{
- enableCMOV = enable;
-
- if(!CMOV)
- {
- enableSSE = false;
- enableSSE2 = false;
- enableSSE3 = false;
- enableSSSE3 = false;
- enableSSE4_1 = false;
- }
-}
-
-void CPUID::setEnableSSE(bool enable)
-{
- enableSSE = enable;
-
- if(enableSSE)
- {
- enableMMX = true;
- enableCMOV = true;
- }
- else
- {
- enableSSE2 = false;
- enableSSE3 = false;
- enableSSSE3 = false;
- enableSSE4_1 = false;
- }
-}
-
-void CPUID::setEnableSSE2(bool enable)
-{
- enableSSE2 = enable;
-
- if(enableSSE2)
- {
- enableMMX = true;
- enableCMOV = true;
- enableSSE = true;
- }
- else
- {
- enableSSE3 = false;
- enableSSSE3 = false;
- enableSSE4_1 = false;
- }
-}
-
-void CPUID::setEnableSSE3(bool enable)
-{
- enableSSE3 = enable;
-
- if(enableSSE3)
- {
- enableMMX = true;
- enableCMOV = true;
- enableSSE = true;
- enableSSE2 = true;
- }
- else
- {
- enableSSSE3 = false;
- enableSSE4_1 = false;
- }
-}
-
-void CPUID::setEnableSSSE3(bool enable)
-{
- enableSSSE3 = enable;
-
- if(enableSSSE3)
- {
- enableMMX = true;
- enableCMOV = true;
- enableSSE = true;
- enableSSE2 = true;
- enableSSE3 = true;
- }
- else
- {
- enableSSE4_1 = false;
- }
-}
-
-void CPUID::setEnableSSE4_1(bool enable)
-{
- enableSSE4_1 = enable;
-
- if(enableSSE4_1)
- {
- enableMMX = true;
- enableCMOV = true;
- enableSSE = true;
- enableSSE2 = true;
- enableSSE3 = true;
- enableSSSE3 = true;
- }
-}
-
static void cpuid(int registers[4], int info)
{
#if defined(__i386__) || defined(__x86_64__)
@@ -178,53 +47,53 @@
#endif
}
-bool CPUID::detectMMX()
+bool CPUID::supportsMMX()
{
int registers[4];
cpuid(registers, 1);
- return MMX = (registers[3] & 0x00800000) != 0;
+ return (registers[3] & 0x00800000) != 0;
}
-bool CPUID::detectCMOV()
+bool CPUID::supportsCMOV()
{
int registers[4];
cpuid(registers, 1);
- return CMOV = (registers[3] & 0x00008000) != 0;
+ return (registers[3] & 0x00008000) != 0;
}
-bool CPUID::detectSSE()
+bool CPUID::supportsSSE()
{
int registers[4];
cpuid(registers, 1);
- return SSE = (registers[3] & 0x02000000) != 0;
+ return (registers[3] & 0x02000000) != 0;
}
-bool CPUID::detectSSE2()
+bool CPUID::supportsSSE2()
{
int registers[4];
cpuid(registers, 1);
- return SSE2 = (registers[3] & 0x04000000) != 0;
+ return (registers[3] & 0x04000000) != 0;
}
-bool CPUID::detectSSE3()
+bool CPUID::supportsSSE3()
{
int registers[4];
cpuid(registers, 1);
- return SSE3 = (registers[2] & 0x00000001) != 0;
+ return (registers[2] & 0x00000001) != 0;
}
-bool CPUID::detectSSSE3()
+bool CPUID::supportsSSSE3()
{
int registers[4];
cpuid(registers, 1);
- return SSSE3 = (registers[2] & 0x00000200) != 0;
+ return (registers[2] & 0x00000200) != 0;
}
-bool CPUID::detectSSE4_1()
+bool CPUID::supportsSSE4_1()
{
int registers[4];
cpuid(registers, 1);
- return SSE4_1 = (registers[2] & 0x00080000) != 0;
+ return (registers[2] & 0x00080000) != 0;
}
} // namespace rr
diff --git a/src/Reactor/CPUID.hpp b/src/Reactor/CPUID.hpp
index a97c6d4..3f368c4 100644
--- a/src/Reactor/CPUID.hpp
+++ b/src/Reactor/CPUID.hpp
@@ -36,87 +36,8 @@
static bool supportsSSE3();
static bool supportsSSSE3();
static bool supportsSSE4_1();
-
- static void setEnableMMX(bool enable);
- static void setEnableCMOV(bool enable);
- static void setEnableSSE(bool enable);
- static void setEnableSSE2(bool enable);
- static void setEnableSSE3(bool enable);
- static void setEnableSSSE3(bool enable);
- static void setEnableSSE4_1(bool enable);
-
-private:
- static bool MMX;
- static bool CMOV;
- static bool SSE;
- static bool SSE2;
- static bool SSE3;
- static bool SSSE3;
- static bool SSE4_1;
-
- static bool enableMMX;
- static bool enableCMOV;
- static bool enableSSE;
- static bool enableSSE2;
- static bool enableSSE3;
- static bool enableSSSE3;
- static bool enableSSE4_1;
-
- static bool detectMMX();
- static bool detectCMOV();
- static bool detectSSE();
- static bool detectSSE2();
- static bool detectSSE3();
- static bool detectSSSE3();
- static bool detectSSE4_1();
};
} // namespace rr
-/* Inline implementation */
-
-namespace rr {
-
-inline bool CPUID::supportsMMX()
-{
- return MMX && enableMMX;
-}
-
-inline bool CPUID::supportsCMOV()
-{
- return CMOV && enableCMOV;
-}
-
-inline bool CPUID::supportsMMX2()
-{
- return supportsSSE(); // Coincides with 64-bit integer vector instructions supported by SSE
-}
-
-inline bool CPUID::supportsSSE()
-{
- return SSE && enableSSE;
-}
-
-inline bool CPUID::supportsSSE2()
-{
- return SSE2 && enableSSE2;
-}
-
-inline bool CPUID::supportsSSE3()
-{
- return SSE3 && enableSSE3;
-}
-
-inline bool CPUID::supportsSSSE3()
-{
- return SSSE3 && enableSSSE3;
-}
-
-inline bool CPUID::supportsSSE4_1()
-{
- return SSE4_1 && enableSSE4_1;
-}
-
-} // namespace rr
-
#endif // rr_CPUID_hpp
diff --git a/src/System/CPUID.cpp b/src/System/CPUID.cpp
index 698fe887..7e0809b 100644
--- a/src/System/CPUID.cpp
+++ b/src/System/CPUID.cpp
@@ -29,139 +29,6 @@
namespace sw {
-bool CPUID::MMX = detectMMX();
-bool CPUID::CMOV = detectCMOV();
-bool CPUID::SSE = detectSSE();
-bool CPUID::SSE2 = detectSSE2();
-bool CPUID::SSE3 = detectSSE3();
-bool CPUID::SSSE3 = detectSSSE3();
-bool CPUID::SSE4_1 = detectSSE4_1();
-int CPUID::cores = detectCoreCount();
-int CPUID::affinity = detectAffinity();
-
-bool CPUID::enableMMX = true;
-bool CPUID::enableCMOV = true;
-bool CPUID::enableSSE = true;
-bool CPUID::enableSSE2 = true;
-bool CPUID::enableSSE3 = true;
-bool CPUID::enableSSSE3 = true;
-bool CPUID::enableSSE4_1 = true;
-
-void CPUID::setEnableMMX(bool enable)
-{
- enableMMX = enable;
-
- if(!enableMMX)
- {
- enableSSE = false;
- enableSSE2 = false;
- enableSSE3 = false;
- enableSSSE3 = false;
- enableSSE4_1 = false;
- }
-}
-
-void CPUID::setEnableCMOV(bool enable)
-{
- enableCMOV = enable;
-
- if(!CMOV)
- {
- enableSSE = false;
- enableSSE2 = false;
- enableSSE3 = false;
- enableSSSE3 = false;
- enableSSE4_1 = false;
- }
-}
-
-void CPUID::setEnableSSE(bool enable)
-{
- enableSSE = enable;
-
- if(enableSSE)
- {
- enableMMX = true;
- enableCMOV = true;
- }
- else
- {
- enableSSE2 = false;
- enableSSE3 = false;
- enableSSSE3 = false;
- enableSSE4_1 = false;
- }
-}
-
-void CPUID::setEnableSSE2(bool enable)
-{
- enableSSE2 = enable;
-
- if(enableSSE2)
- {
- enableMMX = true;
- enableCMOV = true;
- enableSSE = true;
- }
- else
- {
- enableSSE3 = false;
- enableSSSE3 = false;
- enableSSE4_1 = false;
- }
-}
-
-void CPUID::setEnableSSE3(bool enable)
-{
- enableSSE3 = enable;
-
- if(enableSSE3)
- {
- enableMMX = true;
- enableCMOV = true;
- enableSSE = true;
- enableSSE2 = true;
- }
- else
- {
- enableSSSE3 = false;
- enableSSE4_1 = false;
- }
-}
-
-void CPUID::setEnableSSSE3(bool enable)
-{
- enableSSSE3 = enable;
-
- if(enableSSSE3)
- {
- enableMMX = true;
- enableCMOV = true;
- enableSSE = true;
- enableSSE2 = true;
- enableSSE3 = true;
- }
- else
- {
- enableSSE4_1 = false;
- }
-}
-
-void CPUID::setEnableSSE4_1(bool enable)
-{
- enableSSE4_1 = enable;
-
- if(enableSSE4_1)
- {
- enableMMX = true;
- enableCMOV = true;
- enableSSE = true;
- enableSSE2 = true;
- enableSSE3 = true;
- enableSSSE3 = true;
- }
-}
-
static void cpuid(int registers[4], int info)
{
#if defined(__i386__) || defined(__x86_64__)
@@ -180,56 +47,56 @@
#endif
}
-bool CPUID::detectMMX()
+bool CPUID::supportsMMX()
{
int registers[4];
cpuid(registers, 1);
- return MMX = (registers[3] & 0x00800000) != 0;
+ return (registers[3] & 0x00800000) != 0;
}
-bool CPUID::detectCMOV()
+bool CPUID::supportsCMOV()
{
int registers[4];
cpuid(registers, 1);
- return CMOV = (registers[3] & 0x00008000) != 0;
+ return (registers[3] & 0x00008000) != 0;
}
-bool CPUID::detectSSE()
+bool CPUID::supportsSSE()
{
int registers[4];
cpuid(registers, 1);
- return SSE = (registers[3] & 0x02000000) != 0;
+ return (registers[3] & 0x02000000) != 0;
}
-bool CPUID::detectSSE2()
+bool CPUID::supportsSSE2()
{
int registers[4];
cpuid(registers, 1);
- return SSE2 = (registers[3] & 0x04000000) != 0;
+ return (registers[3] & 0x04000000) != 0;
}
-bool CPUID::detectSSE3()
+bool CPUID::supportsSSE3()
{
int registers[4];
cpuid(registers, 1);
- return SSE3 = (registers[2] & 0x00000001) != 0;
+ return (registers[2] & 0x00000001) != 0;
}
-bool CPUID::detectSSSE3()
+bool CPUID::supportsSSSE3()
{
int registers[4];
cpuid(registers, 1);
- return SSSE3 = (registers[2] & 0x00000200) != 0;
+ return (registers[2] & 0x00000200) != 0;
}
-bool CPUID::detectSSE4_1()
+bool CPUID::supportsSSE4_1()
{
int registers[4];
cpuid(registers, 1);
- return SSE4_1 = (registers[2] & 0x00080000) != 0;
+ return (registers[2] & 0x00080000) != 0;
}
-int CPUID::detectCoreCount()
+int CPUID::coreCount()
{
int cores = 0;
@@ -258,7 +125,7 @@
return cores; // FIXME: Number of physical cores
}
-int CPUID::detectAffinity()
+int CPUID::processAffinity()
{
int cores = 0;
@@ -278,7 +145,7 @@
processAffinityMask >>= 1;
}
#else
- return detectCoreCount(); // FIXME: Assumes no affinity limitation
+ return coreCount(); // FIXME: Assumes no affinity limitation
#endif
if(cores < 1) cores = 1;
@@ -292,7 +159,7 @@
#if defined(_MSC_VER)
_controlfp(enable ? _DN_FLUSH : _DN_SAVE, _MCW_DN);
#else
- // Unimplemented
+ // Unimplemented
#endif
}
diff --git a/src/System/CPUID.hpp b/src/System/CPUID.hpp
index 407af16..f5be444 100644
--- a/src/System/CPUID.hpp
+++ b/src/System/CPUID.hpp
@@ -39,103 +39,10 @@
static int coreCount();
static int processAffinity();
- static void setEnableMMX(bool enable);
- static void setEnableCMOV(bool enable);
- static void setEnableSSE(bool enable);
- static void setEnableSSE2(bool enable);
- static void setEnableSSE3(bool enable);
- static void setEnableSSSE3(bool enable);
- static void setEnableSSE4_1(bool enable);
-
static void setFlushToZero(bool enable); // Denormal results are written as zero
static void setDenormalsAreZero(bool enable); // Denormal inputs are read as zero
-
-private:
- static bool MMX;
- static bool CMOV;
- static bool SSE;
- static bool SSE2;
- static bool SSE3;
- static bool SSSE3;
- static bool SSE4_1;
- static int cores;
- static int affinity;
-
- static bool enableMMX;
- static bool enableCMOV;
- static bool enableSSE;
- static bool enableSSE2;
- static bool enableSSE3;
- static bool enableSSSE3;
- static bool enableSSE4_1;
-
- static bool detectMMX();
- static bool detectCMOV();
- static bool detectSSE();
- static bool detectSSE2();
- static bool detectSSE3();
- static bool detectSSSE3();
- static bool detectSSE4_1();
- static int detectCoreCount();
- static int detectAffinity();
};
} // namespace sw
-/* Inline implementation */
-
-namespace sw {
-
-inline bool CPUID::supportsMMX()
-{
- return MMX && enableMMX;
-}
-
-inline bool CPUID::supportsCMOV()
-{
- return CMOV && enableCMOV;
-}
-
-inline bool CPUID::supportsMMX2()
-{
- return supportsSSE(); // Coincides with 64-bit integer vector instructions supported by SSE
-}
-
-inline bool CPUID::supportsSSE()
-{
- return SSE && enableSSE;
-}
-
-inline bool CPUID::supportsSSE2()
-{
- return SSE2 && enableSSE2;
-}
-
-inline bool CPUID::supportsSSE3()
-{
- return SSE3 && enableSSE3;
-}
-
-inline bool CPUID::supportsSSSE3()
-{
- return SSSE3 && enableSSSE3;
-}
-
-inline bool CPUID::supportsSSE4_1()
-{
- return SSE4_1 && enableSSE4_1;
-}
-
-inline int CPUID::coreCount()
-{
- return cores;
-}
-
-inline int CPUID::processAffinity()
-{
- return affinity;
-}
-
-} // namespace sw
-
#endif // sw_CPUID_hpp
diff --git a/src/Vulkan/libVulkan.cpp b/src/Vulkan/libVulkan.cpp
index 92dcf97..0a293a5 100644
--- a/src/Vulkan/libVulkan.cpp
+++ b/src/Vulkan/libVulkan.cpp
@@ -132,15 +132,6 @@
rr::Nucleus::adjustDefaultConfig(cfg);
}
-void setCPUDefaults()
-{
- sw::CPUID::setEnableSSE4_1(true);
- sw::CPUID::setEnableSSSE3(true);
- sw::CPUID::setEnableSSE3(true);
- sw::CPUID::setEnableSSE2(true);
- sw::CPUID::setEnableSSE(true);
-}
-
std::shared_ptr<marl::Scheduler> getOrCreateScheduler()
{
struct Scheduler
@@ -176,7 +167,6 @@
logBuildVersionInformation();
#endif // __ANDROID__ && ENABLE_BUILD_VERSION_OUTPUT
setReactorDefaultConfig();
- setCPUDefaults();
return true;
}();
(void)doOnce;
