| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Target Register Enum Values *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| |
| #ifdef GET_REGINFO_ENUM |
| #undef GET_REGINFO_ENUM |
| |
| namespace llvm { |
| |
| class MCRegisterClass; |
| extern const MCRegisterClass PPCMCRegisterClasses[]; |
| |
| namespace PPC { |
| enum { |
| NoRegister, |
| BP = 1, |
| CARRY = 2, |
| CTR = 3, |
| FP = 4, |
| LR = 5, |
| RM = 6, |
| SPEFSCR = 7, |
| VRSAVE = 8, |
| XER = 9, |
| ZERO = 10, |
| BP8 = 11, |
| CR0 = 12, |
| CR1 = 13, |
| CR2 = 14, |
| CR3 = 15, |
| CR4 = 16, |
| CR5 = 17, |
| CR6 = 18, |
| CR7 = 19, |
| CTR8 = 20, |
| F0 = 21, |
| F1 = 22, |
| F2 = 23, |
| F3 = 24, |
| F4 = 25, |
| F5 = 26, |
| F6 = 27, |
| F7 = 28, |
| F8 = 29, |
| F9 = 30, |
| F10 = 31, |
| F11 = 32, |
| F12 = 33, |
| F13 = 34, |
| F14 = 35, |
| F15 = 36, |
| F16 = 37, |
| F17 = 38, |
| F18 = 39, |
| F19 = 40, |
| F20 = 41, |
| F21 = 42, |
| F22 = 43, |
| F23 = 44, |
| F24 = 45, |
| F25 = 46, |
| F26 = 47, |
| F27 = 48, |
| F28 = 49, |
| F29 = 50, |
| F30 = 51, |
| F31 = 52, |
| FP8 = 53, |
| LR8 = 54, |
| QF0 = 55, |
| QF1 = 56, |
| QF2 = 57, |
| QF3 = 58, |
| QF4 = 59, |
| QF5 = 60, |
| QF6 = 61, |
| QF7 = 62, |
| QF8 = 63, |
| QF9 = 64, |
| QF10 = 65, |
| QF11 = 66, |
| QF12 = 67, |
| QF13 = 68, |
| QF14 = 69, |
| QF15 = 70, |
| QF16 = 71, |
| QF17 = 72, |
| QF18 = 73, |
| QF19 = 74, |
| QF20 = 75, |
| QF21 = 76, |
| QF22 = 77, |
| QF23 = 78, |
| QF24 = 79, |
| QF25 = 80, |
| QF26 = 81, |
| QF27 = 82, |
| QF28 = 83, |
| QF29 = 84, |
| QF30 = 85, |
| QF31 = 86, |
| R0 = 87, |
| R1 = 88, |
| R2 = 89, |
| R3 = 90, |
| R4 = 91, |
| R5 = 92, |
| R6 = 93, |
| R7 = 94, |
| R8 = 95, |
| R9 = 96, |
| R10 = 97, |
| R11 = 98, |
| R12 = 99, |
| R13 = 100, |
| R14 = 101, |
| R15 = 102, |
| R16 = 103, |
| R17 = 104, |
| R18 = 105, |
| R19 = 106, |
| R20 = 107, |
| R21 = 108, |
| R22 = 109, |
| R23 = 110, |
| R24 = 111, |
| R25 = 112, |
| R26 = 113, |
| R27 = 114, |
| R28 = 115, |
| R29 = 116, |
| R30 = 117, |
| R31 = 118, |
| S0 = 119, |
| S1 = 120, |
| S2 = 121, |
| S3 = 122, |
| S4 = 123, |
| S5 = 124, |
| S6 = 125, |
| S7 = 126, |
| S8 = 127, |
| S9 = 128, |
| S10 = 129, |
| S11 = 130, |
| S12 = 131, |
| S13 = 132, |
| S14 = 133, |
| S15 = 134, |
| S16 = 135, |
| S17 = 136, |
| S18 = 137, |
| S19 = 138, |
| S20 = 139, |
| S21 = 140, |
| S22 = 141, |
| S23 = 142, |
| S24 = 143, |
| S25 = 144, |
| S26 = 145, |
| S27 = 146, |
| S28 = 147, |
| S29 = 148, |
| S30 = 149, |
| S31 = 150, |
| V0 = 151, |
| V1 = 152, |
| V2 = 153, |
| V3 = 154, |
| V4 = 155, |
| V5 = 156, |
| V6 = 157, |
| V7 = 158, |
| V8 = 159, |
| V9 = 160, |
| V10 = 161, |
| V11 = 162, |
| V12 = 163, |
| V13 = 164, |
| V14 = 165, |
| V15 = 166, |
| V16 = 167, |
| V17 = 168, |
| V18 = 169, |
| V19 = 170, |
| V20 = 171, |
| V21 = 172, |
| V22 = 173, |
| V23 = 174, |
| V24 = 175, |
| V25 = 176, |
| V26 = 177, |
| V27 = 178, |
| V28 = 179, |
| V29 = 180, |
| V30 = 181, |
| V31 = 182, |
| VF0 = 183, |
| VF1 = 184, |
| VF2 = 185, |
| VF3 = 186, |
| VF4 = 187, |
| VF5 = 188, |
| VF6 = 189, |
| VF7 = 190, |
| VF8 = 191, |
| VF9 = 192, |
| VF10 = 193, |
| VF11 = 194, |
| VF12 = 195, |
| VF13 = 196, |
| VF14 = 197, |
| VF15 = 198, |
| VF16 = 199, |
| VF17 = 200, |
| VF18 = 201, |
| VF19 = 202, |
| VF20 = 203, |
| VF21 = 204, |
| VF22 = 205, |
| VF23 = 206, |
| VF24 = 207, |
| VF25 = 208, |
| VF26 = 209, |
| VF27 = 210, |
| VF28 = 211, |
| VF29 = 212, |
| VF30 = 213, |
| VF31 = 214, |
| VSL0 = 215, |
| VSL1 = 216, |
| VSL2 = 217, |
| VSL3 = 218, |
| VSL4 = 219, |
| VSL5 = 220, |
| VSL6 = 221, |
| VSL7 = 222, |
| VSL8 = 223, |
| VSL9 = 224, |
| VSL10 = 225, |
| VSL11 = 226, |
| VSL12 = 227, |
| VSL13 = 228, |
| VSL14 = 229, |
| VSL15 = 230, |
| VSL16 = 231, |
| VSL17 = 232, |
| VSL18 = 233, |
| VSL19 = 234, |
| VSL20 = 235, |
| VSL21 = 236, |
| VSL22 = 237, |
| VSL23 = 238, |
| VSL24 = 239, |
| VSL25 = 240, |
| VSL26 = 241, |
| VSL27 = 242, |
| VSL28 = 243, |
| VSL29 = 244, |
| VSL30 = 245, |
| VSL31 = 246, |
| VSX32 = 247, |
| VSX33 = 248, |
| VSX34 = 249, |
| VSX35 = 250, |
| VSX36 = 251, |
| VSX37 = 252, |
| VSX38 = 253, |
| VSX39 = 254, |
| VSX40 = 255, |
| VSX41 = 256, |
| VSX42 = 257, |
| VSX43 = 258, |
| VSX44 = 259, |
| VSX45 = 260, |
| VSX46 = 261, |
| VSX47 = 262, |
| VSX48 = 263, |
| VSX49 = 264, |
| VSX50 = 265, |
| VSX51 = 266, |
| VSX52 = 267, |
| VSX53 = 268, |
| VSX54 = 269, |
| VSX55 = 270, |
| VSX56 = 271, |
| VSX57 = 272, |
| VSX58 = 273, |
| VSX59 = 274, |
| VSX60 = 275, |
| VSX61 = 276, |
| VSX62 = 277, |
| VSX63 = 278, |
| X0 = 279, |
| X1 = 280, |
| X2 = 281, |
| X3 = 282, |
| X4 = 283, |
| X5 = 284, |
| X6 = 285, |
| X7 = 286, |
| X8 = 287, |
| X9 = 288, |
| X10 = 289, |
| X11 = 290, |
| X12 = 291, |
| X13 = 292, |
| X14 = 293, |
| X15 = 294, |
| X16 = 295, |
| X17 = 296, |
| X18 = 297, |
| X19 = 298, |
| X20 = 299, |
| X21 = 300, |
| X22 = 301, |
| X23 = 302, |
| X24 = 303, |
| X25 = 304, |
| X26 = 305, |
| X27 = 306, |
| X28 = 307, |
| X29 = 308, |
| X30 = 309, |
| X31 = 310, |
| ZERO8 = 311, |
| CR0EQ = 312, |
| CR1EQ = 313, |
| CR2EQ = 314, |
| CR3EQ = 315, |
| CR4EQ = 316, |
| CR5EQ = 317, |
| CR6EQ = 318, |
| CR7EQ = 319, |
| CR0GT = 320, |
| CR1GT = 321, |
| CR2GT = 322, |
| CR3GT = 323, |
| CR4GT = 324, |
| CR5GT = 325, |
| CR6GT = 326, |
| CR7GT = 327, |
| CR0LT = 328, |
| CR1LT = 329, |
| CR2LT = 330, |
| CR3LT = 331, |
| CR4LT = 332, |
| CR5LT = 333, |
| CR6LT = 334, |
| CR7LT = 335, |
| CR0UN = 336, |
| CR1UN = 337, |
| CR2UN = 338, |
| CR3UN = 339, |
| CR4UN = 340, |
| CR5UN = 341, |
| CR6UN = 342, |
| CR7UN = 343, |
| NUM_TARGET_REGS // 344 |
| }; |
| } // end namespace PPC |
| |
| // Register classes |
| |
| namespace PPC { |
| enum { |
| VSSRCRegClassID = 0, |
| GPRCRegClassID = 1, |
| GPRC_NOR0RegClassID = 2, |
| SPE4RCRegClassID = 3, |
| GPRC_and_GPRC_NOR0RegClassID = 4, |
| CRBITRCRegClassID = 5, |
| F4RCRegClassID = 6, |
| CRRCRegClassID = 7, |
| CARRYRCRegClassID = 8, |
| CRRC0RegClassID = 9, |
| CTRRCRegClassID = 10, |
| VRSAVERCRegClassID = 11, |
| SPILLTOVSRRCRegClassID = 12, |
| VSFRCRegClassID = 13, |
| G8RCRegClassID = 14, |
| G8RC_NOX0RegClassID = 15, |
| SPILLTOVSRRC_and_VSFRCRegClassID = 16, |
| G8RC_and_G8RC_NOX0RegClassID = 17, |
| F8RCRegClassID = 18, |
| SPERCRegClassID = 19, |
| VFRCRegClassID = 20, |
| SPERC_with_sub_32_in_GPRC_NOR0RegClassID = 21, |
| SPILLTOVSRRC_and_VFRCRegClassID = 22, |
| SPILLTOVSRRC_and_F4RCRegClassID = 23, |
| CTRRC8RegClassID = 24, |
| VSRCRegClassID = 25, |
| VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 26, |
| QSRCRegClassID = 27, |
| VRRCRegClassID = 28, |
| VSLRCRegClassID = 29, |
| VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 30, |
| QSRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 31, |
| VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 32, |
| QBRCRegClassID = 33, |
| QFRCRegClassID = 34, |
| QBRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 35, |
| |
| }; |
| } // end namespace PPC |
| |
| |
| // Subregister indices |
| |
| namespace PPC { |
| enum { |
| NoSubRegister, |
| sub_32, // 1 |
| sub_64, // 2 |
| sub_eq, // 3 |
| sub_gt, // 4 |
| sub_lt, // 5 |
| sub_un, // 6 |
| NUM_TARGET_SUBREGS |
| }; |
| } // end namespace PPC |
| |
| } // end namespace llvm |
| |
| #endif // GET_REGINFO_ENUM |
| |
| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* MC Register Information *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| |
| #ifdef GET_REGINFO_MC_DESC |
| #undef GET_REGINFO_MC_DESC |
| |
| namespace llvm { |
| |
| extern const MCPhysReg PPCRegDiffLists[] = { |
| /* 0 */ 0, 0, |
| /* 2 */ 65497, 1, 1, 1, 0, |
| /* 7 */ 3, 0, |
| /* 9 */ 10, 0, |
| /* 11 */ 21, 0, |
| /* 13 */ 316, 65528, 65528, 24, 0, |
| /* 18 */ 32, 0, |
| /* 20 */ 49, 0, |
| /* 22 */ 74, 0, |
| /* 24 */ 32, 160, 0, |
| /* 27 */ 34, 160, 0, |
| /* 30 */ 301, 0, |
| /* 32 */ 64204, 0, |
| /* 34 */ 64233, 0, |
| /* 36 */ 64266, 0, |
| /* 38 */ 64299, 0, |
| /* 40 */ 64611, 0, |
| /* 42 */ 65212, 0, |
| /* 44 */ 65220, 0, |
| /* 46 */ 65228, 0, |
| /* 48 */ 65235, 0, |
| /* 50 */ 65236, 0, |
| /* 52 */ 65332, 0, |
| /* 54 */ 65342, 0, |
| /* 56 */ 65344, 0, |
| /* 58 */ 65363, 0, |
| /* 60 */ 65428, 0, |
| /* 62 */ 65460, 0, |
| /* 64 */ 65474, 0, |
| /* 66 */ 65487, 0, |
| /* 68 */ 65492, 0, |
| /* 70 */ 65502, 0, |
| /* 72 */ 65504, 0, |
| /* 74 */ 65523, 0, |
| /* 76 */ 65524, 0, |
| /* 78 */ 65526, 0, |
| /* 80 */ 65535, 0, |
| }; |
| |
| extern const LaneBitmask PPCLaneMaskLists[] = { |
| /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(), |
| /* 2 */ LaneBitmask(0x00000001), LaneBitmask::getAll(), |
| /* 4 */ LaneBitmask(0x00000002), LaneBitmask::getAll(), |
| /* 6 */ LaneBitmask(0x00000010), LaneBitmask(0x00000008), LaneBitmask(0x00000004), LaneBitmask(0x00000020), LaneBitmask::getAll(), |
| }; |
| |
| extern const uint16_t PPCSubRegIdxLists[] = { |
| /* 0 */ 1, 0, |
| /* 2 */ 2, 0, |
| /* 4 */ 5, 4, 3, 6, 0, |
| }; |
| |
| extern const MCRegisterInfo::SubRegCoveredBits PPCSubRegIdxRanges[] = { |
| { 65535, 65535 }, |
| { 0, 32 }, // sub_32 |
| { 0, 64 }, // sub_64 |
| { 2, 1 }, // sub_eq |
| { 1, 1 }, // sub_gt |
| { 0, 1 }, // sub_lt |
| { 3, 1 }, // sub_un |
| }; |
| |
| extern const char PPCRegStrings[] = { |
| /* 0 */ 'Q', 'F', '1', '0', 0, |
| /* 5 */ 'V', 'F', '1', '0', 0, |
| /* 10 */ 'V', 'S', 'L', '1', '0', 0, |
| /* 16 */ 'R', '1', '0', 0, |
| /* 20 */ 'S', '1', '0', 0, |
| /* 24 */ 'V', '1', '0', 0, |
| /* 28 */ 'X', '1', '0', 0, |
| /* 32 */ 'Q', 'F', '2', '0', 0, |
| /* 37 */ 'V', 'F', '2', '0', 0, |
| /* 42 */ 'V', 'S', 'L', '2', '0', 0, |
| /* 48 */ 'R', '2', '0', 0, |
| /* 52 */ 'S', '2', '0', 0, |
| /* 56 */ 'V', '2', '0', 0, |
| /* 60 */ 'X', '2', '0', 0, |
| /* 64 */ 'Q', 'F', '3', '0', 0, |
| /* 69 */ 'V', 'F', '3', '0', 0, |
| /* 74 */ 'V', 'S', 'L', '3', '0', 0, |
| /* 80 */ 'R', '3', '0', 0, |
| /* 84 */ 'S', '3', '0', 0, |
| /* 88 */ 'V', '3', '0', 0, |
| /* 92 */ 'X', '3', '0', 0, |
| /* 96 */ 'V', 'S', 'X', '4', '0', 0, |
| /* 102 */ 'V', 'S', 'X', '5', '0', 0, |
| /* 108 */ 'V', 'S', 'X', '6', '0', 0, |
| /* 114 */ 'Q', 'F', '0', 0, |
| /* 118 */ 'V', 'F', '0', 0, |
| /* 122 */ 'V', 'S', 'L', '0', 0, |
| /* 127 */ 'C', 'R', '0', 0, |
| /* 131 */ 'S', '0', 0, |
| /* 134 */ 'V', '0', 0, |
| /* 137 */ 'X', '0', 0, |
| /* 140 */ 'Q', 'F', '1', '1', 0, |
| /* 145 */ 'V', 'F', '1', '1', 0, |
| /* 150 */ 'V', 'S', 'L', '1', '1', 0, |
| /* 156 */ 'R', '1', '1', 0, |
| /* 160 */ 'S', '1', '1', 0, |
| /* 164 */ 'V', '1', '1', 0, |
| /* 168 */ 'X', '1', '1', 0, |
| /* 172 */ 'Q', 'F', '2', '1', 0, |
| /* 177 */ 'V', 'F', '2', '1', 0, |
| /* 182 */ 'V', 'S', 'L', '2', '1', 0, |
| /* 188 */ 'R', '2', '1', 0, |
| /* 192 */ 'S', '2', '1', 0, |
| /* 196 */ 'V', '2', '1', 0, |
| /* 200 */ 'X', '2', '1', 0, |
| /* 204 */ 'Q', 'F', '3', '1', 0, |
| /* 209 */ 'V', 'F', '3', '1', 0, |
| /* 214 */ 'V', 'S', 'L', '3', '1', 0, |
| /* 220 */ 'R', '3', '1', 0, |
| /* 224 */ 'S', '3', '1', 0, |
| /* 228 */ 'V', '3', '1', 0, |
| /* 232 */ 'X', '3', '1', 0, |
| /* 236 */ 'V', 'S', 'X', '4', '1', 0, |
| /* 242 */ 'V', 'S', 'X', '5', '1', 0, |
| /* 248 */ 'V', 'S', 'X', '6', '1', 0, |
| /* 254 */ 'Q', 'F', '1', 0, |
| /* 258 */ 'V', 'F', '1', 0, |
| /* 262 */ 'V', 'S', 'L', '1', 0, |
| /* 267 */ 'C', 'R', '1', 0, |
| /* 271 */ 'S', '1', 0, |
| /* 274 */ 'V', '1', 0, |
| /* 277 */ 'X', '1', 0, |
| /* 280 */ 'Q', 'F', '1', '2', 0, |
| /* 285 */ 'V', 'F', '1', '2', 0, |
| /* 290 */ 'V', 'S', 'L', '1', '2', 0, |
| /* 296 */ 'R', '1', '2', 0, |
| /* 300 */ 'S', '1', '2', 0, |
| /* 304 */ 'V', '1', '2', 0, |
| /* 308 */ 'X', '1', '2', 0, |
| /* 312 */ 'Q', 'F', '2', '2', 0, |
| /* 317 */ 'V', 'F', '2', '2', 0, |
| /* 322 */ 'V', 'S', 'L', '2', '2', 0, |
| /* 328 */ 'R', '2', '2', 0, |
| /* 332 */ 'S', '2', '2', 0, |
| /* 336 */ 'V', '2', '2', 0, |
| /* 340 */ 'X', '2', '2', 0, |
| /* 344 */ 'V', 'S', 'X', '3', '2', 0, |
| /* 350 */ 'V', 'S', 'X', '4', '2', 0, |
| /* 356 */ 'V', 'S', 'X', '5', '2', 0, |
| /* 362 */ 'V', 'S', 'X', '6', '2', 0, |
| /* 368 */ 'Q', 'F', '2', 0, |
| /* 372 */ 'V', 'F', '2', 0, |
| /* 376 */ 'V', 'S', 'L', '2', 0, |
| /* 381 */ 'C', 'R', '2', 0, |
| /* 385 */ 'S', '2', 0, |
| /* 388 */ 'V', '2', 0, |
| /* 391 */ 'X', '2', 0, |
| /* 394 */ 'Q', 'F', '1', '3', 0, |
| /* 399 */ 'V', 'F', '1', '3', 0, |
| /* 404 */ 'V', 'S', 'L', '1', '3', 0, |
| /* 410 */ 'R', '1', '3', 0, |
| /* 414 */ 'S', '1', '3', 0, |
| /* 418 */ 'V', '1', '3', 0, |
| /* 422 */ 'X', '1', '3', 0, |
| /* 426 */ 'Q', 'F', '2', '3', 0, |
| /* 431 */ 'V', 'F', '2', '3', 0, |
| /* 436 */ 'V', 'S', 'L', '2', '3', 0, |
| /* 442 */ 'R', '2', '3', 0, |
| /* 446 */ 'S', '2', '3', 0, |
| /* 450 */ 'V', '2', '3', 0, |
| /* 454 */ 'X', '2', '3', 0, |
| /* 458 */ 'V', 'S', 'X', '3', '3', 0, |
| /* 464 */ 'V', 'S', 'X', '4', '3', 0, |
| /* 470 */ 'V', 'S', 'X', '5', '3', 0, |
| /* 476 */ 'V', 'S', 'X', '6', '3', 0, |
| /* 482 */ 'Q', 'F', '3', 0, |
| /* 486 */ 'V', 'F', '3', 0, |
| /* 490 */ 'V', 'S', 'L', '3', 0, |
| /* 495 */ 'C', 'R', '3', 0, |
| /* 499 */ 'S', '3', 0, |
| /* 502 */ 'V', '3', 0, |
| /* 505 */ 'X', '3', 0, |
| /* 508 */ 'Q', 'F', '1', '4', 0, |
| /* 513 */ 'V', 'F', '1', '4', 0, |
| /* 518 */ 'V', 'S', 'L', '1', '4', 0, |
| /* 524 */ 'R', '1', '4', 0, |
| /* 528 */ 'S', '1', '4', 0, |
| /* 532 */ 'V', '1', '4', 0, |
| /* 536 */ 'X', '1', '4', 0, |
| /* 540 */ 'Q', 'F', '2', '4', 0, |
| /* 545 */ 'V', 'F', '2', '4', 0, |
| /* 550 */ 'V', 'S', 'L', '2', '4', 0, |
| /* 556 */ 'R', '2', '4', 0, |
| /* 560 */ 'S', '2', '4', 0, |
| /* 564 */ 'V', '2', '4', 0, |
| /* 568 */ 'X', '2', '4', 0, |
| /* 572 */ 'V', 'S', 'X', '3', '4', 0, |
| /* 578 */ 'V', 'S', 'X', '4', '4', 0, |
| /* 584 */ 'V', 'S', 'X', '5', '4', 0, |
| /* 590 */ 'Q', 'F', '4', 0, |
| /* 594 */ 'V', 'F', '4', 0, |
| /* 598 */ 'V', 'S', 'L', '4', 0, |
| /* 603 */ 'C', 'R', '4', 0, |
| /* 607 */ 'S', '4', 0, |
| /* 610 */ 'V', '4', 0, |
| /* 613 */ 'X', '4', 0, |
| /* 616 */ 'Q', 'F', '1', '5', 0, |
| /* 621 */ 'V', 'F', '1', '5', 0, |
| /* 626 */ 'V', 'S', 'L', '1', '5', 0, |
| /* 632 */ 'R', '1', '5', 0, |
| /* 636 */ 'S', '1', '5', 0, |
| /* 640 */ 'V', '1', '5', 0, |
| /* 644 */ 'X', '1', '5', 0, |
| /* 648 */ 'Q', 'F', '2', '5', 0, |
| /* 653 */ 'V', 'F', '2', '5', 0, |
| /* 658 */ 'V', 'S', 'L', '2', '5', 0, |
| /* 664 */ 'R', '2', '5', 0, |
| /* 668 */ 'S', '2', '5', 0, |
| /* 672 */ 'V', '2', '5', 0, |
| /* 676 */ 'X', '2', '5', 0, |
| /* 680 */ 'V', 'S', 'X', '3', '5', 0, |
| /* 686 */ 'V', 'S', 'X', '4', '5', 0, |
| /* 692 */ 'V', 'S', 'X', '5', '5', 0, |
| /* 698 */ 'Q', 'F', '5', 0, |
| /* 702 */ 'V', 'F', '5', 0, |
| /* 706 */ 'V', 'S', 'L', '5', 0, |
| /* 711 */ 'C', 'R', '5', 0, |
| /* 715 */ 'S', '5', 0, |
| /* 718 */ 'V', '5', 0, |
| /* 721 */ 'X', '5', 0, |
| /* 724 */ 'Q', 'F', '1', '6', 0, |
| /* 729 */ 'V', 'F', '1', '6', 0, |
| /* 734 */ 'V', 'S', 'L', '1', '6', 0, |
| /* 740 */ 'R', '1', '6', 0, |
| /* 744 */ 'S', '1', '6', 0, |
| /* 748 */ 'V', '1', '6', 0, |
| /* 752 */ 'X', '1', '6', 0, |
| /* 756 */ 'Q', 'F', '2', '6', 0, |
| /* 761 */ 'V', 'F', '2', '6', 0, |
| /* 766 */ 'V', 'S', 'L', '2', '6', 0, |
| /* 772 */ 'R', '2', '6', 0, |
| /* 776 */ 'S', '2', '6', 0, |
| /* 780 */ 'V', '2', '6', 0, |
| /* 784 */ 'X', '2', '6', 0, |
| /* 788 */ 'V', 'S', 'X', '3', '6', 0, |
| /* 794 */ 'V', 'S', 'X', '4', '6', 0, |
| /* 800 */ 'V', 'S', 'X', '5', '6', 0, |
| /* 806 */ 'Q', 'F', '6', 0, |
| /* 810 */ 'V', 'F', '6', 0, |
| /* 814 */ 'V', 'S', 'L', '6', 0, |
| /* 819 */ 'C', 'R', '6', 0, |
| /* 823 */ 'S', '6', 0, |
| /* 826 */ 'V', '6', 0, |
| /* 829 */ 'X', '6', 0, |
| /* 832 */ 'Q', 'F', '1', '7', 0, |
| /* 837 */ 'V', 'F', '1', '7', 0, |
| /* 842 */ 'V', 'S', 'L', '1', '7', 0, |
| /* 848 */ 'R', '1', '7', 0, |
| /* 852 */ 'S', '1', '7', 0, |
| /* 856 */ 'V', '1', '7', 0, |
| /* 860 */ 'X', '1', '7', 0, |
| /* 864 */ 'Q', 'F', '2', '7', 0, |
| /* 869 */ 'V', 'F', '2', '7', 0, |
| /* 874 */ 'V', 'S', 'L', '2', '7', 0, |
| /* 880 */ 'R', '2', '7', 0, |
| /* 884 */ 'S', '2', '7', 0, |
| /* 888 */ 'V', '2', '7', 0, |
| /* 892 */ 'X', '2', '7', 0, |
| /* 896 */ 'V', 'S', 'X', '3', '7', 0, |
| /* 902 */ 'V', 'S', 'X', '4', '7', 0, |
| /* 908 */ 'V', 'S', 'X', '5', '7', 0, |
| /* 914 */ 'Q', 'F', '7', 0, |
| /* 918 */ 'V', 'F', '7', 0, |
| /* 922 */ 'V', 'S', 'L', '7', 0, |
| /* 927 */ 'C', 'R', '7', 0, |
| /* 931 */ 'S', '7', 0, |
| /* 934 */ 'V', '7', 0, |
| /* 937 */ 'X', '7', 0, |
| /* 940 */ 'Q', 'F', '1', '8', 0, |
| /* 945 */ 'V', 'F', '1', '8', 0, |
| /* 950 */ 'V', 'S', 'L', '1', '8', 0, |
| /* 956 */ 'R', '1', '8', 0, |
| /* 960 */ 'S', '1', '8', 0, |
| /* 964 */ 'V', '1', '8', 0, |
| /* 968 */ 'X', '1', '8', 0, |
| /* 972 */ 'Q', 'F', '2', '8', 0, |
| /* 977 */ 'V', 'F', '2', '8', 0, |
| /* 982 */ 'V', 'S', 'L', '2', '8', 0, |
| /* 988 */ 'R', '2', '8', 0, |
| /* 992 */ 'S', '2', '8', 0, |
| /* 996 */ 'V', '2', '8', 0, |
| /* 1000 */ 'X', '2', '8', 0, |
| /* 1004 */ 'V', 'S', 'X', '3', '8', 0, |
| /* 1010 */ 'V', 'S', 'X', '4', '8', 0, |
| /* 1016 */ 'V', 'S', 'X', '5', '8', 0, |
| /* 1022 */ 'Q', 'F', '8', 0, |
| /* 1026 */ 'V', 'F', '8', 0, |
| /* 1030 */ 'V', 'S', 'L', '8', 0, |
| /* 1035 */ 'Z', 'E', 'R', 'O', '8', 0, |
| /* 1041 */ 'B', 'P', '8', 0, |
| /* 1045 */ 'F', 'P', '8', 0, |
| /* 1049 */ 'L', 'R', '8', 0, |
| /* 1053 */ 'C', 'T', 'R', '8', 0, |
| /* 1058 */ 'S', '8', 0, |
| /* 1061 */ 'V', '8', 0, |
| /* 1064 */ 'X', '8', 0, |
| /* 1067 */ 'Q', 'F', '1', '9', 0, |
| /* 1072 */ 'V', 'F', '1', '9', 0, |
| /* 1077 */ 'V', 'S', 'L', '1', '9', 0, |
| /* 1083 */ 'R', '1', '9', 0, |
| /* 1087 */ 'S', '1', '9', 0, |
| /* 1091 */ 'V', '1', '9', 0, |
| /* 1095 */ 'X', '1', '9', 0, |
| /* 1099 */ 'Q', 'F', '2', '9', 0, |
| /* 1104 */ 'V', 'F', '2', '9', 0, |
| /* 1109 */ 'V', 'S', 'L', '2', '9', 0, |
| /* 1115 */ 'R', '2', '9', 0, |
| /* 1119 */ 'S', '2', '9', 0, |
| /* 1123 */ 'V', '2', '9', 0, |
| /* 1127 */ 'X', '2', '9', 0, |
| /* 1131 */ 'V', 'S', 'X', '3', '9', 0, |
| /* 1137 */ 'V', 'S', 'X', '4', '9', 0, |
| /* 1143 */ 'V', 'S', 'X', '5', '9', 0, |
| /* 1149 */ 'Q', 'F', '9', 0, |
| /* 1153 */ 'V', 'F', '9', 0, |
| /* 1157 */ 'V', 'S', 'L', '9', 0, |
| /* 1162 */ 'R', '9', 0, |
| /* 1165 */ 'S', '9', 0, |
| /* 1168 */ 'V', '9', 0, |
| /* 1171 */ 'X', '9', 0, |
| /* 1174 */ 'V', 'R', 'S', 'A', 'V', 'E', 0, |
| /* 1181 */ 'R', 'M', 0, |
| /* 1184 */ 'C', 'R', '0', 'U', 'N', 0, |
| /* 1190 */ 'C', 'R', '1', 'U', 'N', 0, |
| /* 1196 */ 'C', 'R', '2', 'U', 'N', 0, |
| /* 1202 */ 'C', 'R', '3', 'U', 'N', 0, |
| /* 1208 */ 'C', 'R', '4', 'U', 'N', 0, |
| /* 1214 */ 'C', 'R', '5', 'U', 'N', 0, |
| /* 1220 */ 'C', 'R', '6', 'U', 'N', 0, |
| /* 1226 */ 'C', 'R', '7', 'U', 'N', 0, |
| /* 1232 */ 'Z', 'E', 'R', 'O', 0, |
| /* 1237 */ 'B', 'P', 0, |
| /* 1240 */ 'F', 'P', 0, |
| /* 1243 */ 'C', 'R', '0', 'E', 'Q', 0, |
| /* 1249 */ 'C', 'R', '1', 'E', 'Q', 0, |
| /* 1255 */ 'C', 'R', '2', 'E', 'Q', 0, |
| /* 1261 */ 'C', 'R', '3', 'E', 'Q', 0, |
| /* 1267 */ 'C', 'R', '4', 'E', 'Q', 0, |
| /* 1273 */ 'C', 'R', '5', 'E', 'Q', 0, |
| /* 1279 */ 'C', 'R', '6', 'E', 'Q', 0, |
| /* 1285 */ 'C', 'R', '7', 'E', 'Q', 0, |
| /* 1291 */ 'S', 'P', 'E', 'F', 'S', 'C', 'R', 0, |
| /* 1299 */ 'X', 'E', 'R', 0, |
| /* 1303 */ 'L', 'R', 0, |
| /* 1306 */ 'C', 'T', 'R', 0, |
| /* 1310 */ 'C', 'R', '0', 'G', 'T', 0, |
| /* 1316 */ 'C', 'R', '1', 'G', 'T', 0, |
| /* 1322 */ 'C', 'R', '2', 'G', 'T', 0, |
| /* 1328 */ 'C', 'R', '3', 'G', 'T', 0, |
| /* 1334 */ 'C', 'R', '4', 'G', 'T', 0, |
| /* 1340 */ 'C', 'R', '5', 'G', 'T', 0, |
| /* 1346 */ 'C', 'R', '6', 'G', 'T', 0, |
| /* 1352 */ 'C', 'R', '7', 'G', 'T', 0, |
| /* 1358 */ 'C', 'R', '0', 'L', 'T', 0, |
| /* 1364 */ 'C', 'R', '1', 'L', 'T', 0, |
| /* 1370 */ 'C', 'R', '2', 'L', 'T', 0, |
| /* 1376 */ 'C', 'R', '3', 'L', 'T', 0, |
| /* 1382 */ 'C', 'R', '4', 'L', 'T', 0, |
| /* 1388 */ 'C', 'R', '5', 'L', 'T', 0, |
| /* 1394 */ 'C', 'R', '6', 'L', 'T', 0, |
| /* 1400 */ 'C', 'R', '7', 'L', 'T', 0, |
| /* 1406 */ 'C', 'A', 'R', 'R', 'Y', 0, |
| }; |
| |
| extern const MCRegisterDesc PPCRegDesc[] = { // Descriptors |
| { 4, 0, 0, 0, 0, 0 }, |
| { 1237, 1, 9, 1, 1281, 0 }, |
| { 1406, 1, 1, 1, 1281, 0 }, |
| { 1306, 1, 1, 1, 1281, 0 }, |
| { 1240, 1, 20, 1, 1281, 0 }, |
| { 1303, 1, 1, 1, 1281, 0 }, |
| { 1181, 1, 1, 1, 1281, 0 }, |
| { 1291, 1, 1, 1, 1281, 0 }, |
| { 1174, 1, 1, 1, 1281, 0 }, |
| { 1299, 1, 1, 1, 1031, 0 }, |
| { 1232, 1, 30, 1, 1031, 0 }, |
| { 1041, 78, 1, 0, 0, 2 }, |
| { 127, 13, 1, 4, 36, 6 }, |
| { 267, 13, 1, 4, 36, 6 }, |
| { 381, 13, 1, 4, 36, 6 }, |
| { 495, 13, 1, 4, 36, 6 }, |
| { 603, 13, 1, 4, 36, 6 }, |
| { 711, 13, 1, 4, 36, 6 }, |
| { 819, 13, 1, 4, 36, 6 }, |
| { 927, 13, 1, 4, 36, 6 }, |
| { 1053, 1, 1, 1, 177, 0 }, |
| { 115, 1, 27, 1, 177, 0 }, |
| { 255, 1, 27, 1, 177, 0 }, |
| { 369, 1, 27, 1, 177, 0 }, |
| { 483, 1, 27, 1, 177, 0 }, |
| { 591, 1, 27, 1, 177, 0 }, |
| { 699, 1, 27, 1, 177, 0 }, |
| { 807, 1, 27, 1, 177, 0 }, |
| { 915, 1, 27, 1, 177, 0 }, |
| { 1023, 1, 27, 1, 177, 0 }, |
| { 1150, 1, 27, 1, 177, 0 }, |
| { 1, 1, 27, 1, 177, 0 }, |
| { 141, 1, 27, 1, 177, 0 }, |
| { 281, 1, 27, 1, 177, 0 }, |
| { 395, 1, 27, 1, 177, 0 }, |
| { 509, 1, 27, 1, 177, 0 }, |
| { 617, 1, 27, 1, 177, 0 }, |
| { 725, 1, 27, 1, 177, 0 }, |
| { 833, 1, 27, 1, 177, 0 }, |
| { 941, 1, 27, 1, 177, 0 }, |
| { 1068, 1, 27, 1, 177, 0 }, |
| { 33, 1, 27, 1, 177, 0 }, |
| { 173, 1, 27, 1, 177, 0 }, |
| { 313, 1, 27, 1, 177, 0 }, |
| { 427, 1, 27, 1, 177, 0 }, |
| { 541, 1, 27, 1, 177, 0 }, |
| { 649, 1, 27, 1, 177, 0 }, |
| { 757, 1, 27, 1, 177, 0 }, |
| { 865, 1, 27, 1, 177, 0 }, |
| { 973, 1, 27, 1, 177, 0 }, |
| { 1100, 1, 27, 1, 177, 0 }, |
| { 65, 1, 27, 1, 177, 0 }, |
| { 205, 1, 27, 1, 177, 0 }, |
| { 1045, 66, 1, 0, 112, 2 }, |
| { 1049, 1, 1, 1, 352, 0 }, |
| { 114, 70, 1, 2, 1185, 4 }, |
| { 254, 70, 1, 2, 1185, 4 }, |
| { 368, 70, 1, 2, 1185, 4 }, |
| { 482, 70, 1, 2, 1185, 4 }, |
| { 590, 70, 1, 2, 1185, 4 }, |
| { 698, 70, 1, 2, 1185, 4 }, |
| { 806, 70, 1, 2, 1185, 4 }, |
| { 914, 70, 1, 2, 1185, 4 }, |
| { 1022, 70, 1, 2, 1185, 4 }, |
| { 1149, 70, 1, 2, 1185, 4 }, |
| { 0, 70, 1, 2, 1185, 4 }, |
| { 140, 70, 1, 2, 1185, 4 }, |
| { 280, 70, 1, 2, 1185, 4 }, |
| { 394, 70, 1, 2, 1185, 4 }, |
| { 508, 70, 1, 2, 1185, 4 }, |
| { 616, 70, 1, 2, 1185, 4 }, |
| { 724, 70, 1, 2, 1185, 4 }, |
| { 832, 70, 1, 2, 1185, 4 }, |
| { 940, 70, 1, 2, 1185, 4 }, |
| { 1067, 70, 1, 2, 1185, 4 }, |
| { 32, 70, 1, 2, 1185, 4 }, |
| { 172, 70, 1, 2, 1185, 4 }, |
| { 312, 70, 1, 2, 1185, 4 }, |
| { 426, 70, 1, 2, 1185, 4 }, |
| { 540, 70, 1, 2, 1185, 4 }, |
| { 648, 70, 1, 2, 1185, 4 }, |
| { 756, 70, 1, 2, 1185, 4 }, |
| { 864, 70, 1, 2, 1185, 4 }, |
| { 972, 70, 1, 2, 1185, 4 }, |
| { 1099, 70, 1, 2, 1185, 4 }, |
| { 64, 70, 1, 2, 1185, 4 }, |
| { 204, 70, 1, 2, 1185, 4 }, |
| { 128, 1, 24, 1, 1217, 0 }, |
| { 268, 1, 24, 1, 1217, 0 }, |
| { 382, 1, 24, 1, 1217, 0 }, |
| { 496, 1, 24, 1, 1217, 0 }, |
| { 604, 1, 24, 1, 1217, 0 }, |
| { 712, 1, 24, 1, 1217, 0 }, |
| { 820, 1, 24, 1, 1217, 0 }, |
| { 928, 1, 24, 1, 1217, 0 }, |
| { 1050, 1, 24, 1, 1217, 0 }, |
| { 1162, 1, 24, 1, 1217, 0 }, |
| { 16, 1, 24, 1, 1217, 0 }, |
| { 156, 1, 24, 1, 1217, 0 }, |
| { 296, 1, 24, 1, 1217, 0 }, |
| { 410, 1, 24, 1, 1217, 0 }, |
| { 524, 1, 24, 1, 1217, 0 }, |
| { 632, 1, 24, 1, 1217, 0 }, |
| { 740, 1, 24, 1, 1217, 0 }, |
| { 848, 1, 24, 1, 1217, 0 }, |
| { 956, 1, 24, 1, 1217, 0 }, |
| { 1083, 1, 24, 1, 1217, 0 }, |
| { 48, 1, 24, 1, 1217, 0 }, |
| { 188, 1, 24, 1, 1217, 0 }, |
| { 328, 1, 24, 1, 1217, 0 }, |
| { 442, 1, 24, 1, 1217, 0 }, |
| { 556, 1, 24, 1, 1217, 0 }, |
| { 664, 1, 24, 1, 1217, 0 }, |
| { 772, 1, 24, 1, 1217, 0 }, |
| { 880, 1, 24, 1, 1217, 0 }, |
| { 988, 1, 24, 1, 1217, 0 }, |
| { 1115, 1, 24, 1, 1217, 0 }, |
| { 80, 1, 24, 1, 1217, 0 }, |
| { 220, 1, 24, 1, 1217, 0 }, |
| { 131, 72, 1, 0, 1089, 2 }, |
| { 271, 72, 1, 0, 1089, 2 }, |
| { 385, 72, 1, 0, 1089, 2 }, |
| { 499, 72, 1, 0, 1089, 2 }, |
| { 607, 72, 1, 0, 1089, 2 }, |
| { 715, 72, 1, 0, 1089, 2 }, |
| { 823, 72, 1, 0, 1089, 2 }, |
| { 931, 72, 1, 0, 1089, 2 }, |
| { 1058, 72, 1, 0, 1089, 2 }, |
| { 1165, 72, 1, 0, 1089, 2 }, |
| { 20, 72, 1, 0, 1089, 2 }, |
| { 160, 72, 1, 0, 1089, 2 }, |
| { 300, 72, 1, 0, 1089, 2 }, |
| { 414, 72, 1, 0, 1089, 2 }, |
| { 528, 72, 1, 0, 1089, 2 }, |
| { 636, 72, 1, 0, 1089, 2 }, |
| { 744, 72, 1, 0, 1089, 2 }, |
| { 852, 72, 1, 0, 1089, 2 }, |
| { 960, 72, 1, 0, 1089, 2 }, |
| { 1087, 72, 1, 0, 1089, 2 }, |
| { 52, 72, 1, 0, 1089, 2 }, |
| { 192, 72, 1, 0, 1089, 2 }, |
| { 332, 72, 1, 0, 1089, 2 }, |
| { 446, 72, 1, 0, 1089, 2 }, |
| { 560, 72, 1, 0, 1089, 2 }, |
| { 668, 72, 1, 0, 1089, 2 }, |
| { 776, 72, 1, 0, 1089, 2 }, |
| { 884, 72, 1, 0, 1089, 2 }, |
| { 992, 72, 1, 0, 1089, 2 }, |
| { 1119, 72, 1, 0, 1089, 2 }, |
| { 84, 72, 1, 0, 1089, 2 }, |
| { 224, 72, 1, 0, 1089, 2 }, |
| { 134, 18, 1, 2, 1089, 4 }, |
| { 274, 18, 1, 2, 1089, 4 }, |
| { 388, 18, 1, 2, 1089, 4 }, |
| { 502, 18, 1, 2, 1089, 4 }, |
| { 610, 18, 1, 2, 1089, 4 }, |
| { 718, 18, 1, 2, 1089, 4 }, |
| { 826, 18, 1, 2, 1089, 4 }, |
| { 934, 18, 1, 2, 1089, 4 }, |
| { 1061, 18, 1, 2, 1089, 4 }, |
| { 1168, 18, 1, 2, 1089, 4 }, |
| { 24, 18, 1, 2, 1089, 4 }, |
| { 164, 18, 1, 2, 1089, 4 }, |
| { 304, 18, 1, 2, 1089, 4 }, |
| { 418, 18, 1, 2, 1089, 4 }, |
| { 532, 18, 1, 2, 1089, 4 }, |
| { 640, 18, 1, 2, 1089, 4 }, |
| { 748, 18, 1, 2, 1089, 4 }, |
| { 856, 18, 1, 2, 1089, 4 }, |
| { 964, 18, 1, 2, 1089, 4 }, |
| { 1091, 18, 1, 2, 1089, 4 }, |
| { 56, 18, 1, 2, 1089, 4 }, |
| { 196, 18, 1, 2, 1089, 4 }, |
| { 336, 18, 1, 2, 1089, 4 }, |
| { 450, 18, 1, 2, 1089, 4 }, |
| { 564, 18, 1, 2, 1089, 4 }, |
| { 672, 18, 1, 2, 1089, 4 }, |
| { 780, 18, 1, 2, 1089, 4 }, |
| { 888, 18, 1, 2, 1089, 4 }, |
| { 996, 18, 1, 2, 1089, 4 }, |
| { 1123, 18, 1, 2, 1089, 4 }, |
| { 88, 18, 1, 2, 1089, 4 }, |
| { 228, 18, 1, 2, 1089, 4 }, |
| { 118, 1, 72, 1, 993, 0 }, |
| { 258, 1, 72, 1, 993, 0 }, |
| { 372, 1, 72, 1, 993, 0 }, |
| { 486, 1, 72, 1, 993, 0 }, |
| { 594, 1, 72, 1, 993, 0 }, |
| { 702, 1, 72, 1, 993, 0 }, |
| { 810, 1, 72, 1, 993, 0 }, |
| { 918, 1, 72, 1, 993, 0 }, |
| { 1026, 1, 72, 1, 993, 0 }, |
| { 1153, 1, 72, 1, 993, 0 }, |
| { 5, 1, 72, 1, 993, 0 }, |
| { 145, 1, 72, 1, 993, 0 }, |
| { 285, 1, 72, 1, 993, 0 }, |
| { 399, 1, 72, 1, 993, 0 }, |
| { 513, 1, 72, 1, 993, 0 }, |
| { 621, 1, 72, 1, 993, 0 }, |
| { 729, 1, 72, 1, 993, 0 }, |
| { 837, 1, 72, 1, 993, 0 }, |
| { 945, 1, 72, 1, 993, 0 }, |
| { 1072, 1, 72, 1, 993, 0 }, |
| { 37, 1, 72, 1, 993, 0 }, |
| { 177, 1, 72, 1, 993, 0 }, |
| { 317, 1, 72, 1, 993, 0 }, |
| { 431, 1, 72, 1, 993, 0 }, |
| { 545, 1, 72, 1, 993, 0 }, |
| { 653, 1, 72, 1, 993, 0 }, |
| { 761, 1, 72, 1, 993, 0 }, |
| { 869, 1, 72, 1, 993, 0 }, |
| { 977, 1, 72, 1, 993, 0 }, |
| { 1104, 1, 72, 1, 993, 0 }, |
| { 69, 1, 72, 1, 993, 0 }, |
| { 209, 1, 72, 1, 993, 0 }, |
| { 122, 54, 1, 2, 929, 4 }, |
| { 262, 54, 1, 2, 929, 4 }, |
| { 376, 54, 1, 2, 929, 4 }, |
| { 490, 54, 1, 2, 929, 4 }, |
| { 598, 54, 1, 2, 929, 4 }, |
| { 706, 54, 1, 2, 929, 4 }, |
| { 814, 54, 1, 2, 929, 4 }, |
| { 922, 54, 1, 2, 929, 4 }, |
| { 1030, 54, 1, 2, 929, 4 }, |
| { 1157, 54, 1, 2, 929, 4 }, |
| { 10, 54, 1, 2, 929, 4 }, |
| { 150, 54, 1, 2, 929, 4 }, |
| { 290, 54, 1, 2, 929, 4 }, |
| { 404, 54, 1, 2, 929, 4 }, |
| { 518, 54, 1, 2, 929, 4 }, |
| { 626, 54, 1, 2, 929, 4 }, |
| { 734, 54, 1, 2, 929, 4 }, |
| { 842, 54, 1, 2, 929, 4 }, |
| { 950, 54, 1, 2, 929, 4 }, |
| { 1077, 54, 1, 2, 929, 4 }, |
| { 42, 54, 1, 2, 929, 4 }, |
| { 182, 54, 1, 2, 929, 4 }, |
| { 322, 54, 1, 2, 929, 4 }, |
| { 436, 54, 1, 2, 929, 4 }, |
| { 550, 54, 1, 2, 929, 4 }, |
| { 658, 54, 1, 2, 929, 4 }, |
| { 766, 54, 1, 2, 929, 4 }, |
| { 874, 54, 1, 2, 929, 4 }, |
| { 982, 54, 1, 2, 929, 4 }, |
| { 1109, 54, 1, 2, 929, 4 }, |
| { 74, 54, 1, 2, 929, 4 }, |
| { 214, 54, 1, 2, 929, 4 }, |
| { 344, 1, 1, 1, 961, 0 }, |
| { 458, 1, 1, 1, 961, 0 }, |
| { 572, 1, 1, 1, 961, 0 }, |
| { 680, 1, 1, 1, 961, 0 }, |
| { 788, 1, 1, 1, 961, 0 }, |
| { 896, 1, 1, 1, 961, 0 }, |
| { 1004, 1, 1, 1, 961, 0 }, |
| { 1131, 1, 1, 1, 961, 0 }, |
| { 96, 1, 1, 1, 961, 0 }, |
| { 236, 1, 1, 1, 961, 0 }, |
| { 350, 1, 1, 1, 961, 0 }, |
| { 464, 1, 1, 1, 961, 0 }, |
| { 578, 1, 1, 1, 961, 0 }, |
| { 686, 1, 1, 1, 961, 0 }, |
| { 794, 1, 1, 1, 961, 0 }, |
| { 902, 1, 1, 1, 961, 0 }, |
| { 1010, 1, 1, 1, 961, 0 }, |
| { 1137, 1, 1, 1, 961, 0 }, |
| { 102, 1, 1, 1, 961, 0 }, |
| { 242, 1, 1, 1, 961, 0 }, |
| { 356, 1, 1, 1, 961, 0 }, |
| { 470, 1, 1, 1, 961, 0 }, |
| { 584, 1, 1, 1, 961, 0 }, |
| { 692, 1, 1, 1, 961, 0 }, |
| { 800, 1, 1, 1, 961, 0 }, |
| { 908, 1, 1, 1, 961, 0 }, |
| { 1016, 1, 1, 1, 961, 0 }, |
| { 1143, 1, 1, 1, 961, 0 }, |
| { 108, 1, 1, 1, 961, 0 }, |
| { 248, 1, 1, 1, 961, 0 }, |
| { 362, 1, 1, 1, 961, 0 }, |
| { 476, 1, 1, 1, 961, 0 }, |
| { 137, 56, 1, 0, 833, 2 }, |
| { 277, 56, 1, 0, 833, 2 }, |
| { 391, 56, 1, 0, 833, 2 }, |
| { 505, 56, 1, 0, 833, 2 }, |
| { 613, 56, 1, 0, 833, 2 }, |
| { 721, 56, 1, 0, 833, 2 }, |
| { 829, 56, 1, 0, 833, 2 }, |
| { 937, 56, 1, 0, 833, 2 }, |
| { 1064, 56, 1, 0, 833, 2 }, |
| { 1171, 56, 1, 0, 833, 2 }, |
| { 28, 56, 1, 0, 833, 2 }, |
| { 168, 56, 1, 0, 833, 2 }, |
| { 308, 56, 1, 0, 833, 2 }, |
| { 422, 56, 1, 0, 833, 2 }, |
| { 536, 56, 1, 0, 833, 2 }, |
| { 644, 56, 1, 0, 833, 2 }, |
| { 752, 56, 1, 0, 833, 2 }, |
| { 860, 56, 1, 0, 833, 2 }, |
| { 968, 56, 1, 0, 833, 2 }, |
| { 1095, 56, 1, 0, 833, 2 }, |
| { 60, 56, 1, 0, 833, 2 }, |
| { 200, 56, 1, 0, 833, 2 }, |
| { 340, 56, 1, 0, 833, 2 }, |
| { 454, 56, 1, 0, 833, 2 }, |
| { 568, 56, 1, 0, 833, 2 }, |
| { 676, 56, 1, 0, 833, 2 }, |
| { 784, 56, 1, 0, 833, 2 }, |
| { 892, 56, 1, 0, 833, 2 }, |
| { 1000, 56, 1, 0, 833, 2 }, |
| { 1127, 56, 1, 0, 833, 2 }, |
| { 92, 56, 1, 0, 833, 2 }, |
| { 232, 56, 1, 0, 833, 2 }, |
| { 1035, 48, 1, 0, 643, 2 }, |
| { 1243, 1, 50, 1, 643, 0 }, |
| { 1249, 1, 50, 1, 612, 0 }, |
| { 1255, 1, 50, 1, 612, 0 }, |
| { 1261, 1, 50, 1, 612, 0 }, |
| { 1267, 1, 50, 1, 612, 0 }, |
| { 1273, 1, 50, 1, 612, 0 }, |
| { 1279, 1, 50, 1, 612, 0 }, |
| { 1285, 1, 50, 1, 612, 0 }, |
| { 1310, 1, 46, 1, 580, 0 }, |
| { 1316, 1, 46, 1, 580, 0 }, |
| { 1322, 1, 46, 1, 580, 0 }, |
| { 1328, 1, 46, 1, 580, 0 }, |
| { 1334, 1, 46, 1, 580, 0 }, |
| { 1340, 1, 46, 1, 580, 0 }, |
| { 1346, 1, 46, 1, 580, 0 }, |
| { 1352, 1, 46, 1, 580, 0 }, |
| { 1358, 1, 44, 1, 548, 0 }, |
| { 1364, 1, 44, 1, 548, 0 }, |
| { 1370, 1, 44, 1, 548, 0 }, |
| { 1376, 1, 44, 1, 548, 0 }, |
| { 1382, 1, 44, 1, 548, 0 }, |
| { 1388, 1, 44, 1, 548, 0 }, |
| { 1394, 1, 44, 1, 548, 0 }, |
| { 1400, 1, 44, 1, 548, 0 }, |
| { 1184, 1, 42, 1, 516, 0 }, |
| { 1190, 1, 42, 1, 516, 0 }, |
| { 1196, 1, 42, 1, 516, 0 }, |
| { 1202, 1, 42, 1, 516, 0 }, |
| { 1208, 1, 42, 1, 516, 0 }, |
| { 1214, 1, 42, 1, 516, 0 }, |
| { 1220, 1, 42, 1, 516, 0 }, |
| { 1226, 1, 42, 1, 516, 0 }, |
| }; |
| |
| extern const MCPhysReg PPCRegUnitRoots[][2] = { |
| { PPC::BP }, |
| { PPC::CARRY, PPC::XER }, |
| { PPC::CTR }, |
| { PPC::FP }, |
| { PPC::LR }, |
| { PPC::RM }, |
| { PPC::SPEFSCR }, |
| { PPC::VRSAVE }, |
| { PPC::ZERO }, |
| { PPC::CR0LT }, |
| { PPC::CR0GT }, |
| { PPC::CR0EQ }, |
| { PPC::CR0UN }, |
| { PPC::CR1LT }, |
| { PPC::CR1GT }, |
| { PPC::CR1EQ }, |
| { PPC::CR1UN }, |
| { PPC::CR2LT }, |
| { PPC::CR2GT }, |
| { PPC::CR2EQ }, |
| { PPC::CR2UN }, |
| { PPC::CR3LT }, |
| { PPC::CR3GT }, |
| { PPC::CR3EQ }, |
| { PPC::CR3UN }, |
| { PPC::CR4LT }, |
| { PPC::CR4GT }, |
| { PPC::CR4EQ }, |
| { PPC::CR4UN }, |
| { PPC::CR5LT }, |
| { PPC::CR5GT }, |
| { PPC::CR5EQ }, |
| { PPC::CR5UN }, |
| { PPC::CR6LT }, |
| { PPC::CR6GT }, |
| { PPC::CR6EQ }, |
| { PPC::CR6UN }, |
| { PPC::CR7LT }, |
| { PPC::CR7GT }, |
| { PPC::CR7EQ }, |
| { PPC::CR7UN }, |
| { PPC::CTR8 }, |
| { PPC::F0 }, |
| { PPC::F1 }, |
| { PPC::F2 }, |
| { PPC::F3 }, |
| { PPC::F4 }, |
| { PPC::F5 }, |
| { PPC::F6 }, |
| { PPC::F7 }, |
| { PPC::F8 }, |
| { PPC::F9 }, |
| { PPC::F10 }, |
| { PPC::F11 }, |
| { PPC::F12 }, |
| { PPC::F13 }, |
| { PPC::F14 }, |
| { PPC::F15 }, |
| { PPC::F16 }, |
| { PPC::F17 }, |
| { PPC::F18 }, |
| { PPC::F19 }, |
| { PPC::F20 }, |
| { PPC::F21 }, |
| { PPC::F22 }, |
| { PPC::F23 }, |
| { PPC::F24 }, |
| { PPC::F25 }, |
| { PPC::F26 }, |
| { PPC::F27 }, |
| { PPC::F28 }, |
| { PPC::F29 }, |
| { PPC::F30 }, |
| { PPC::F31 }, |
| { PPC::LR8 }, |
| { PPC::R0 }, |
| { PPC::R1 }, |
| { PPC::R2 }, |
| { PPC::R3 }, |
| { PPC::R4 }, |
| { PPC::R5 }, |
| { PPC::R6 }, |
| { PPC::R7 }, |
| { PPC::R8 }, |
| { PPC::R9 }, |
| { PPC::R10 }, |
| { PPC::R11 }, |
| { PPC::R12 }, |
| { PPC::R13 }, |
| { PPC::R14 }, |
| { PPC::R15 }, |
| { PPC::R16 }, |
| { PPC::R17 }, |
| { PPC::R18 }, |
| { PPC::R19 }, |
| { PPC::R20 }, |
| { PPC::R21 }, |
| { PPC::R22 }, |
| { PPC::R23 }, |
| { PPC::R24 }, |
| { PPC::R25 }, |
| { PPC::R26 }, |
| { PPC::R27 }, |
| { PPC::R28 }, |
| { PPC::R29 }, |
| { PPC::R30 }, |
| { PPC::R31 }, |
| { PPC::VF0 }, |
| { PPC::VF1 }, |
| { PPC::VF2 }, |
| { PPC::VF3 }, |
| { PPC::VF4 }, |
| { PPC::VF5 }, |
| { PPC::VF6 }, |
| { PPC::VF7 }, |
| { PPC::VF8 }, |
| { PPC::VF9 }, |
| { PPC::VF10 }, |
| { PPC::VF11 }, |
| { PPC::VF12 }, |
| { PPC::VF13 }, |
| { PPC::VF14 }, |
| { PPC::VF15 }, |
| { PPC::VF16 }, |
| { PPC::VF17 }, |
| { PPC::VF18 }, |
| { PPC::VF19 }, |
| { PPC::VF20 }, |
| { PPC::VF21 }, |
| { PPC::VF22 }, |
| { PPC::VF23 }, |
| { PPC::VF24 }, |
| { PPC::VF25 }, |
| { PPC::VF26 }, |
| { PPC::VF27 }, |
| { PPC::VF28 }, |
| { PPC::VF29 }, |
| { PPC::VF30 }, |
| { PPC::VF31 }, |
| { PPC::VSX32 }, |
| { PPC::VSX33 }, |
| { PPC::VSX34 }, |
| { PPC::VSX35 }, |
| { PPC::VSX36 }, |
| { PPC::VSX37 }, |
| { PPC::VSX38 }, |
| { PPC::VSX39 }, |
| { PPC::VSX40 }, |
| { PPC::VSX41 }, |
| { PPC::VSX42 }, |
| { PPC::VSX43 }, |
| { PPC::VSX44 }, |
| { PPC::VSX45 }, |
| { PPC::VSX46 }, |
| { PPC::VSX47 }, |
| { PPC::VSX48 }, |
| { PPC::VSX49 }, |
| { PPC::VSX50 }, |
| { PPC::VSX51 }, |
| { PPC::VSX52 }, |
| { PPC::VSX53 }, |
| { PPC::VSX54 }, |
| { PPC::VSX55 }, |
| { PPC::VSX56 }, |
| { PPC::VSX57 }, |
| { PPC::VSX58 }, |
| { PPC::VSX59 }, |
| { PPC::VSX60 }, |
| { PPC::VSX61 }, |
| { PPC::VSX62 }, |
| { PPC::VSX63 }, |
| }; |
| |
| namespace { // Register classes... |
| // VSSRC Register Class... |
| const MCPhysReg VSSRC[] = { |
| PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, PPC::VF31, PPC::VF30, PPC::VF29, PPC::VF28, PPC::VF27, PPC::VF26, PPC::VF25, PPC::VF24, PPC::VF23, PPC::VF22, PPC::VF21, PPC::VF20, |
| }; |
| |
| // VSSRC Bit set. |
| const uint8_t VSSRCBits[] = { |
| 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, |
| }; |
| |
| // GPRC Register Class... |
| const MCPhysReg GPRC[] = { |
| PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R0, PPC::R1, PPC::FP, PPC::BP, |
| }; |
| |
| // GPRC Bit set. |
| const uint8_t GPRCBits[] = { |
| 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, |
| }; |
| |
| // GPRC_NOR0 Register Class... |
| const MCPhysReg GPRC_NOR0[] = { |
| PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, PPC::ZERO, |
| }; |
| |
| // GPRC_NOR0 Bit set. |
| const uint8_t GPRC_NOR0Bits[] = { |
| 0x12, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, |
| }; |
| |
| // SPE4RC Register Class... |
| const MCPhysReg SPE4RC[] = { |
| PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R0, PPC::R1, PPC::FP, PPC::BP, |
| }; |
| |
| // SPE4RC Bit set. |
| const uint8_t SPE4RCBits[] = { |
| 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, |
| }; |
| |
| // GPRC_and_GPRC_NOR0 Register Class... |
| const MCPhysReg GPRC_and_GPRC_NOR0[] = { |
| PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, |
| }; |
| |
| // GPRC_and_GPRC_NOR0 Bit set. |
| const uint8_t GPRC_and_GPRC_NOR0Bits[] = { |
| 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, |
| }; |
| |
| // CRBITRC Register Class... |
| const MCPhysReg CRBITRC[] = { |
| PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN, PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, |
| }; |
| |
| // CRBITRC Bit set. |
| const uint8_t CRBITRCBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, |
| }; |
| |
| // F4RC Register Class... |
| const MCPhysReg F4RC[] = { |
| PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14, |
| }; |
| |
| // F4RC Bit set. |
| const uint8_t F4RCBits[] = { |
| 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, |
| }; |
| |
| // CRRC Register Class... |
| const MCPhysReg CRRC[] = { |
| PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CR2, PPC::CR3, PPC::CR4, |
| }; |
| |
| // CRRC Bit set. |
| const uint8_t CRRCBits[] = { |
| 0x00, 0xf0, 0x0f, |
| }; |
| |
| // CARRYRC Register Class... |
| const MCPhysReg CARRYRC[] = { |
| PPC::CARRY, PPC::XER, |
| }; |
| |
| // CARRYRC Bit set. |
| const uint8_t CARRYRCBits[] = { |
| 0x04, 0x02, |
| }; |
| |
| // CRRC0 Register Class... |
| const MCPhysReg CRRC0[] = { |
| PPC::CR0, |
| }; |
| |
| // CRRC0 Bit set. |
| const uint8_t CRRC0Bits[] = { |
| 0x00, 0x10, |
| }; |
| |
| // CTRRC Register Class... |
| const MCPhysReg CTRRC[] = { |
| PPC::CTR, |
| }; |
| |
| // CTRRC Bit set. |
| const uint8_t CTRRCBits[] = { |
| 0x08, |
| }; |
| |
| // VRSAVERC Register Class... |
| const MCPhysReg VRSAVERC[] = { |
| PPC::VRSAVE, |
| }; |
| |
| // VRSAVERC Bit set. |
| const uint8_t VRSAVERCBits[] = { |
| 0x00, 0x01, |
| }; |
| |
| // SPILLTOVSRRC Register Class... |
| const MCPhysReg SPILLTOVSRRC[] = { |
| PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, |
| }; |
| |
| // SPILLTOVSRRC Bit set. |
| const uint8_t SPILLTOVSRRCBits[] = { |
| 0x00, 0x08, 0xe0, 0xff, 0x07, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, |
| }; |
| |
| // VSFRC Register Class... |
| const MCPhysReg VSFRC[] = { |
| PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, PPC::VF31, PPC::VF30, PPC::VF29, PPC::VF28, PPC::VF27, PPC::VF26, PPC::VF25, PPC::VF24, PPC::VF23, PPC::VF22, PPC::VF21, PPC::VF20, |
| }; |
| |
| // VSFRC Bit set. |
| const uint8_t VSFRCBits[] = { |
| 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, |
| }; |
| |
| // G8RC Register Class... |
| const MCPhysReg G8RC[] = { |
| PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8, |
| }; |
| |
| // G8RC Bit set. |
| const uint8_t G8RCBits[] = { |
| 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, |
| }; |
| |
| // G8RC_NOX0 Register Class... |
| const MCPhysReg G8RC_NOX0[] = { |
| PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::ZERO8, |
| }; |
| |
| // G8RC_NOX0 Bit set. |
| const uint8_t G8RC_NOX0Bits[] = { |
| 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, |
| }; |
| |
| // SPILLTOVSRRC_and_VSFRC Register Class... |
| const MCPhysReg SPILLTOVSRRC_and_VSFRC[] = { |
| PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, |
| }; |
| |
| // SPILLTOVSRRC_and_VSFRC Bit set. |
| const uint8_t SPILLTOVSRRC_and_VSFRCBits[] = { |
| 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x07, |
| }; |
| |
| // G8RC_and_G8RC_NOX0 Register Class... |
| const MCPhysReg G8RC_and_G8RC_NOX0[] = { |
| PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, |
| }; |
| |
| // G8RC_and_G8RC_NOX0 Bit set. |
| const uint8_t G8RC_and_G8RC_NOX0Bits[] = { |
| 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, |
| }; |
| |
| // F8RC Register Class... |
| const MCPhysReg F8RC[] = { |
| PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14, |
| }; |
| |
| // F8RC Bit set. |
| const uint8_t F8RCBits[] = { |
| 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, |
| }; |
| |
| // SPERC Register Class... |
| const MCPhysReg SPERC[] = { |
| PPC::S2, PPC::S3, PPC::S4, PPC::S5, PPC::S6, PPC::S7, PPC::S8, PPC::S9, PPC::S10, PPC::S11, PPC::S12, PPC::S30, PPC::S29, PPC::S28, PPC::S27, PPC::S26, PPC::S25, PPC::S24, PPC::S23, PPC::S22, PPC::S21, PPC::S20, PPC::S19, PPC::S18, PPC::S17, PPC::S16, PPC::S15, PPC::S14, PPC::S13, PPC::S31, PPC::S0, PPC::S1, |
| }; |
| |
| // SPERC Bit set. |
| const uint8_t SPERCBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, |
| }; |
| |
| // VFRC Register Class... |
| const MCPhysReg VFRC[] = { |
| PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, PPC::VF31, PPC::VF30, PPC::VF29, PPC::VF28, PPC::VF27, PPC::VF26, PPC::VF25, PPC::VF24, PPC::VF23, PPC::VF22, PPC::VF21, PPC::VF20, |
| }; |
| |
| // VFRC Bit set. |
| const uint8_t VFRCBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, |
| }; |
| |
| // SPERC_with_sub_32_in_GPRC_NOR0 Register Class... |
| const MCPhysReg SPERC_with_sub_32_in_GPRC_NOR0[] = { |
| PPC::S2, PPC::S3, PPC::S4, PPC::S5, PPC::S6, PPC::S7, PPC::S8, PPC::S9, PPC::S10, PPC::S11, PPC::S12, PPC::S30, PPC::S29, PPC::S28, PPC::S27, PPC::S26, PPC::S25, PPC::S24, PPC::S23, PPC::S22, PPC::S21, PPC::S20, PPC::S19, PPC::S18, PPC::S17, PPC::S16, PPC::S15, PPC::S14, PPC::S13, PPC::S31, PPC::S1, |
| }; |
| |
| // SPERC_with_sub_32_in_GPRC_NOR0 Bit set. |
| const uint8_t SPERC_with_sub_32_in_GPRC_NOR0Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, |
| }; |
| |
| // SPILLTOVSRRC_and_VFRC Register Class... |
| const MCPhysReg SPILLTOVSRRC_and_VFRC[] = { |
| PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, |
| }; |
| |
| // SPILLTOVSRRC_and_VFRC Bit set. |
| const uint8_t SPILLTOVSRRC_and_VFRCBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x07, |
| }; |
| |
| // SPILLTOVSRRC_and_F4RC Register Class... |
| const MCPhysReg SPILLTOVSRRC_and_F4RC[] = { |
| PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, |
| }; |
| |
| // SPILLTOVSRRC_and_F4RC Bit set. |
| const uint8_t SPILLTOVSRRC_and_F4RCBits[] = { |
| 0x00, 0x00, 0xe0, 0xff, 0x07, |
| }; |
| |
| // CTRRC8 Register Class... |
| const MCPhysReg CTRRC8[] = { |
| PPC::CTR8, |
| }; |
| |
| // CTRRC8 Bit set. |
| const uint8_t CTRRC8Bits[] = { |
| 0x00, 0x00, 0x10, |
| }; |
| |
| // VSRC Register Class... |
| const MCPhysReg VSRC[] = { |
| PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL31, PPC::VSL30, PPC::VSL29, PPC::VSL28, PPC::VSL27, PPC::VSL26, PPC::VSL25, PPC::VSL24, PPC::VSL23, PPC::VSL22, PPC::VSL21, PPC::VSL20, PPC::VSL19, PPC::VSL18, PPC::VSL17, PPC::VSL16, PPC::VSL15, PPC::VSL14, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V31, PPC::V30, PPC::V29, PPC::V28, PPC::V27, PPC::V26, PPC::V25, PPC::V24, PPC::V23, PPC::V22, PPC::V21, PPC::V20, |
| }; |
| |
| // VSRC Bit set. |
| const uint8_t VSRCBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, |
| }; |
| |
| // VSRC_with_sub_64_in_SPILLTOVSRRC Register Class... |
| const MCPhysReg VSRC_with_sub_64_in_SPILLTOVSRRC[] = { |
| PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, |
| }; |
| |
| // VSRC_with_sub_64_in_SPILLTOVSRRC Bit set. |
| const uint8_t VSRC_with_sub_64_in_SPILLTOVSRRCBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, |
| }; |
| |
| // QSRC Register Class... |
| const MCPhysReg QSRC[] = { |
| PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7, PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13, PPC::QF31, PPC::QF30, PPC::QF29, PPC::QF28, PPC::QF27, PPC::QF26, PPC::QF25, PPC::QF24, PPC::QF23, PPC::QF22, PPC::QF21, PPC::QF20, PPC::QF19, PPC::QF18, PPC::QF17, PPC::QF16, PPC::QF15, PPC::QF14, |
| }; |
| |
| // QSRC Bit set. |
| const uint8_t QSRCBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, |
| }; |
| |
| // VRRC Register Class... |
| const MCPhysReg VRRC[] = { |
| PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V31, PPC::V30, PPC::V29, PPC::V28, PPC::V27, PPC::V26, PPC::V25, PPC::V24, PPC::V23, PPC::V22, PPC::V21, PPC::V20, |
| }; |
| |
| // VRRC Bit set. |
| const uint8_t VRRCBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, |
| }; |
| |
| // VSLRC Register Class... |
| const MCPhysReg VSLRC[] = { |
| PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL31, PPC::VSL30, PPC::VSL29, PPC::VSL28, PPC::VSL27, PPC::VSL26, PPC::VSL25, PPC::VSL24, PPC::VSL23, PPC::VSL22, PPC::VSL21, PPC::VSL20, PPC::VSL19, PPC::VSL18, PPC::VSL17, PPC::VSL16, PPC::VSL15, PPC::VSL14, |
| }; |
| |
| // VSLRC Bit set. |
| const uint8_t VSLRCBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, |
| }; |
| |
| // VRRC_with_sub_64_in_SPILLTOVSRRC Register Class... |
| const MCPhysReg VRRC_with_sub_64_in_SPILLTOVSRRC[] = { |
| PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, |
| }; |
| |
| // VRRC_with_sub_64_in_SPILLTOVSRRC Bit set. |
| const uint8_t VRRC_with_sub_64_in_SPILLTOVSRRCBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x07, |
| }; |
| |
| // QSRC_with_sub_64_in_SPILLTOVSRRC Register Class... |
| const MCPhysReg QSRC_with_sub_64_in_SPILLTOVSRRC[] = { |
| PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7, PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13, |
| }; |
| |
| // QSRC_with_sub_64_in_SPILLTOVSRRC Bit set. |
| const uint8_t QSRC_with_sub_64_in_SPILLTOVSRRCBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, |
| }; |
| |
| // VSLRC_with_sub_64_in_SPILLTOVSRRC Register Class... |
| const MCPhysReg VSLRC_with_sub_64_in_SPILLTOVSRRC[] = { |
| PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, |
| }; |
| |
| // VSLRC_with_sub_64_in_SPILLTOVSRRC Bit set. |
| const uint8_t VSLRC_with_sub_64_in_SPILLTOVSRRCBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, |
| }; |
| |
| // QBRC Register Class... |
| const MCPhysReg QBRC[] = { |
| PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7, PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13, PPC::QF31, PPC::QF30, PPC::QF29, PPC::QF28, PPC::QF27, PPC::QF26, PPC::QF25, PPC::QF24, PPC::QF23, PPC::QF22, PPC::QF21, PPC::QF20, PPC::QF19, PPC::QF18, PPC::QF17, PPC::QF16, PPC::QF15, PPC::QF14, |
| }; |
| |
| // QBRC Bit set. |
| const uint8_t QBRCBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, |
| }; |
| |
| // QFRC Register Class... |
| const MCPhysReg QFRC[] = { |
| PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7, PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13, PPC::QF31, PPC::QF30, PPC::QF29, PPC::QF28, PPC::QF27, PPC::QF26, PPC::QF25, PPC::QF24, PPC::QF23, PPC::QF22, PPC::QF21, PPC::QF20, PPC::QF19, PPC::QF18, PPC::QF17, PPC::QF16, PPC::QF15, PPC::QF14, |
| }; |
| |
| // QFRC Bit set. |
| const uint8_t QFRCBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, |
| }; |
| |
| // QBRC_with_sub_64_in_SPILLTOVSRRC Register Class... |
| const MCPhysReg QBRC_with_sub_64_in_SPILLTOVSRRC[] = { |
| PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7, PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13, |
| }; |
| |
| // QBRC_with_sub_64_in_SPILLTOVSRRC Bit set. |
| const uint8_t QBRC_with_sub_64_in_SPILLTOVSRRCBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, |
| }; |
| |
| } // end anonymous namespace |
| |
| extern const char PPCRegClassStrings[] = { |
| /* 0 */ 'C', 'R', 'R', 'C', '0', 0, |
| /* 6 */ 'G', 'P', 'R', 'C', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'C', '_', 'N', 'O', 'R', '0', 0, |
| /* 25 */ 'S', 'P', 'E', 'R', 'C', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'C', '_', 'N', 'O', 'R', '0', 0, |
| /* 56 */ 'G', '8', 'R', 'C', '_', 'a', 'n', 'd', '_', 'G', '8', 'R', 'C', '_', 'N', 'O', 'X', '0', 0, |
| /* 75 */ 'C', 'T', 'R', 'R', 'C', '8', 0, |
| /* 82 */ 'S', 'P', 'E', '4', 'R', 'C', 0, |
| /* 89 */ 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', 'R', 'C', '_', 'a', 'n', 'd', '_', 'F', '4', 'R', 'C', 0, |
| /* 111 */ 'F', '8', 'R', 'C', 0, |
| /* 116 */ 'G', '8', 'R', 'C', 0, |
| /* 121 */ 'Q', 'B', 'R', 'C', 0, |
| /* 126 */ 'S', 'P', 'E', 'R', 'C', 0, |
| /* 132 */ 'V', 'R', 'S', 'A', 'V', 'E', 'R', 'C', 0, |
| /* 141 */ 'Q', 'F', 'R', 'C', 0, |
| /* 146 */ 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', 'R', 'C', '_', 'a', 'n', 'd', '_', 'V', 'S', 'F', 'R', 'C', 0, |
| /* 169 */ 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', 'R', 'C', '_', 'a', 'n', 'd', '_', 'V', 'F', 'R', 'C', 0, |
| /* 191 */ 'V', 'S', 'L', 'R', 'C', 0, |
| /* 197 */ 'G', 'P', 'R', 'C', 0, |
| /* 202 */ 'C', 'R', 'R', 'C', 0, |
| /* 207 */ 'Q', 'B', 'R', 'C', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '6', '4', '_', 'i', 'n', '_', 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', 'R', 'C', 0, |
| /* 240 */ 'V', 'S', 'L', 'R', 'C', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '6', '4', '_', 'i', 'n', '_', 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', 'R', 'C', 0, |
| /* 274 */ 'V', 'R', 'R', 'C', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '6', '4', '_', 'i', 'n', '_', 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', 'R', 'C', 0, |
| /* 307 */ 'Q', 'S', 'R', 'C', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '6', '4', '_', 'i', 'n', '_', 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', 'R', 'C', 0, |
| /* 340 */ 'V', 'S', 'R', 'C', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '6', '4', '_', 'i', 'n', '_', 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', 'R', 'C', 0, |
| /* 373 */ 'C', 'T', 'R', 'R', 'C', 0, |
| /* 379 */ 'V', 'R', 'R', 'C', 0, |
| /* 384 */ 'Q', 'S', 'R', 'C', 0, |
| /* 389 */ 'V', 'S', 'S', 'R', 'C', 0, |
| /* 395 */ 'V', 'S', 'R', 'C', 0, |
| /* 400 */ 'C', 'R', 'B', 'I', 'T', 'R', 'C', 0, |
| /* 408 */ 'C', 'A', 'R', 'R', 'Y', 'R', 'C', 0, |
| }; |
| |
| extern const MCRegisterClass PPCMCRegisterClasses[] = { |
| { VSSRC, VSSRCBits, 389, 64, sizeof(VSSRCBits), PPC::VSSRCRegClassID, 4, 1, true }, |
| { GPRC, GPRCBits, 197, 34, sizeof(GPRCBits), PPC::GPRCRegClassID, 4, 1, true }, |
| { GPRC_NOR0, GPRC_NOR0Bits, 15, 34, sizeof(GPRC_NOR0Bits), PPC::GPRC_NOR0RegClassID, 4, 1, true }, |
| { SPE4RC, SPE4RCBits, 82, 34, sizeof(SPE4RCBits), PPC::SPE4RCRegClassID, 4, 1, true }, |
| { GPRC_and_GPRC_NOR0, GPRC_and_GPRC_NOR0Bits, 6, 33, sizeof(GPRC_and_GPRC_NOR0Bits), PPC::GPRC_and_GPRC_NOR0RegClassID, 4, 1, true }, |
| { CRBITRC, CRBITRCBits, 400, 32, sizeof(CRBITRCBits), PPC::CRBITRCRegClassID, 4, 1, true }, |
| { F4RC, F4RCBits, 106, 32, sizeof(F4RCBits), PPC::F4RCRegClassID, 4, 1, true }, |
| { CRRC, CRRCBits, 202, 8, sizeof(CRRCBits), PPC::CRRCRegClassID, 4, 1, true }, |
| { CARRYRC, CARRYRCBits, 408, 2, sizeof(CARRYRCBits), PPC::CARRYRCRegClassID, 4, -1, true }, |
| { CRRC0, CRRC0Bits, 0, 1, sizeof(CRRC0Bits), PPC::CRRC0RegClassID, 4, 1, true }, |
| { CTRRC, CTRRCBits, 373, 1, sizeof(CTRRCBits), PPC::CTRRCRegClassID, 4, 1, false }, |
| { VRSAVERC, VRSAVERCBits, 132, 1, sizeof(VRSAVERCBits), PPC::VRSAVERCRegClassID, 4, 1, true }, |
| { SPILLTOVSRRC, SPILLTOVSRRCBits, 227, 68, sizeof(SPILLTOVSRRCBits), PPC::SPILLTOVSRRCRegClassID, 8, 1, true }, |
| { VSFRC, VSFRCBits, 163, 64, sizeof(VSFRCBits), PPC::VSFRCRegClassID, 8, 1, true }, |
| { G8RC, G8RCBits, 116, 34, sizeof(G8RCBits), PPC::G8RCRegClassID, 8, 1, true }, |
| { G8RC_NOX0, G8RC_NOX0Bits, 65, 34, sizeof(G8RC_NOX0Bits), PPC::G8RC_NOX0RegClassID, 8, 1, true }, |
| { SPILLTOVSRRC_and_VSFRC, SPILLTOVSRRC_and_VSFRCBits, 146, 34, sizeof(SPILLTOVSRRC_and_VSFRCBits), PPC::SPILLTOVSRRC_and_VSFRCRegClassID, 8, 1, true }, |
| { G8RC_and_G8RC_NOX0, G8RC_and_G8RC_NOX0Bits, 56, 33, sizeof(G8RC_and_G8RC_NOX0Bits), PPC::G8RC_and_G8RC_NOX0RegClassID, 8, 1, true }, |
| { F8RC, F8RCBits, 111, 32, sizeof(F8RCBits), PPC::F8RCRegClassID, 8, 1, true }, |
| { SPERC, SPERCBits, 126, 32, sizeof(SPERCBits), PPC::SPERCRegClassID, 8, 1, true }, |
| { VFRC, VFRCBits, 186, 32, sizeof(VFRCBits), PPC::VFRCRegClassID, 8, 1, true }, |
| { SPERC_with_sub_32_in_GPRC_NOR0, SPERC_with_sub_32_in_GPRC_NOR0Bits, 25, 31, sizeof(SPERC_with_sub_32_in_GPRC_NOR0Bits), PPC::SPERC_with_sub_32_in_GPRC_NOR0RegClassID, 8, 1, true }, |
| { SPILLTOVSRRC_and_VFRC, SPILLTOVSRRC_and_VFRCBits, 169, 20, sizeof(SPILLTOVSRRC_and_VFRCBits), PPC::SPILLTOVSRRC_and_VFRCRegClassID, 8, 1, true }, |
| { SPILLTOVSRRC_and_F4RC, SPILLTOVSRRC_and_F4RCBits, 89, 14, sizeof(SPILLTOVSRRC_and_F4RCBits), PPC::SPILLTOVSRRC_and_F4RCRegClassID, 8, 1, true }, |
| { CTRRC8, CTRRC8Bits, 75, 1, sizeof(CTRRC8Bits), PPC::CTRRC8RegClassID, 8, 1, false }, |
| { VSRC, VSRCBits, 395, 64, sizeof(VSRCBits), PPC::VSRCRegClassID, 16, 1, true }, |
| { VSRC_with_sub_64_in_SPILLTOVSRRC, VSRC_with_sub_64_in_SPILLTOVSRRCBits, 340, 34, sizeof(VSRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 16, 1, true }, |
| { QSRC, QSRCBits, 384, 32, sizeof(QSRCBits), PPC::QSRCRegClassID, 16, 1, true }, |
| { VRRC, VRRCBits, 379, 32, sizeof(VRRCBits), PPC::VRRCRegClassID, 16, 1, true }, |
| { VSLRC, VSLRCBits, 191, 32, sizeof(VSLRCBits), PPC::VSLRCRegClassID, 16, 1, true }, |
| { VRRC_with_sub_64_in_SPILLTOVSRRC, VRRC_with_sub_64_in_SPILLTOVSRRCBits, 274, 20, sizeof(VRRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 16, 1, true }, |
| { QSRC_with_sub_64_in_SPILLTOVSRRC, QSRC_with_sub_64_in_SPILLTOVSRRCBits, 307, 14, sizeof(QSRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::QSRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 16, 1, true }, |
| { VSLRC_with_sub_64_in_SPILLTOVSRRC, VSLRC_with_sub_64_in_SPILLTOVSRRCBits, 240, 14, sizeof(VSLRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 16, 1, true }, |
| { QBRC, QBRCBits, 121, 32, sizeof(QBRCBits), PPC::QBRCRegClassID, 32, 1, true }, |
| { QFRC, QFRCBits, 141, 32, sizeof(QFRCBits), PPC::QFRCRegClassID, 32, 1, true }, |
| { QBRC_with_sub_64_in_SPILLTOVSRRC, QBRC_with_sub_64_in_SPILLTOVSRRCBits, 207, 14, sizeof(QBRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::QBRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 32, 1, true }, |
| }; |
| |
| // PPC Dwarf<->LLVM register mappings. |
| extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0Dwarf2L[] = { |
| { 0U, PPC::X0 }, |
| { 1U, PPC::X1 }, |
| { 2U, PPC::X2 }, |
| { 3U, PPC::X3 }, |
| { 4U, PPC::X4 }, |
| { 5U, PPC::X5 }, |
| { 6U, PPC::X6 }, |
| { 7U, PPC::X7 }, |
| { 8U, PPC::X8 }, |
| { 9U, PPC::X9 }, |
| { 10U, PPC::X10 }, |
| { 11U, PPC::X11 }, |
| { 12U, PPC::X12 }, |
| { 13U, PPC::X13 }, |
| { 14U, PPC::X14 }, |
| { 15U, PPC::X15 }, |
| { 16U, PPC::X16 }, |
| { 17U, PPC::X17 }, |
| { 18U, PPC::X18 }, |
| { 19U, PPC::X19 }, |
| { 20U, PPC::X20 }, |
| { 21U, PPC::X21 }, |
| { 22U, PPC::X22 }, |
| { 23U, PPC::X23 }, |
| { 24U, PPC::X24 }, |
| { 25U, PPC::X25 }, |
| { 26U, PPC::X26 }, |
| { 27U, PPC::X27 }, |
| { 28U, PPC::X28 }, |
| { 29U, PPC::X29 }, |
| { 30U, PPC::X30 }, |
| { 31U, PPC::X31 }, |
| { 32U, PPC::QF0 }, |
| { 33U, PPC::QF1 }, |
| { 34U, PPC::QF2 }, |
| { 35U, PPC::QF3 }, |
| { 36U, PPC::QF4 }, |
| { 37U, PPC::QF5 }, |
| { 38U, PPC::QF6 }, |
| { 39U, PPC::QF7 }, |
| { 40U, PPC::QF8 }, |
| { 41U, PPC::QF9 }, |
| { 42U, PPC::QF10 }, |
| { 43U, PPC::QF11 }, |
| { 44U, PPC::QF12 }, |
| { 45U, PPC::QF13 }, |
| { 46U, PPC::QF14 }, |
| { 47U, PPC::QF15 }, |
| { 48U, PPC::QF16 }, |
| { 49U, PPC::QF17 }, |
| { 50U, PPC::QF18 }, |
| { 51U, PPC::QF19 }, |
| { 52U, PPC::QF20 }, |
| { 53U, PPC::QF21 }, |
| { 54U, PPC::QF22 }, |
| { 55U, PPC::QF23 }, |
| { 56U, PPC::QF24 }, |
| { 57U, PPC::QF25 }, |
| { 58U, PPC::QF26 }, |
| { 59U, PPC::QF27 }, |
| { 60U, PPC::QF28 }, |
| { 61U, PPC::QF29 }, |
| { 62U, PPC::QF30 }, |
| { 63U, PPC::QF31 }, |
| { 65U, PPC::LR8 }, |
| { 66U, PPC::CTR8 }, |
| { 68U, PPC::CR0 }, |
| { 69U, PPC::CR1 }, |
| { 70U, PPC::CR2 }, |
| { 71U, PPC::CR3 }, |
| { 72U, PPC::CR4 }, |
| { 73U, PPC::CR5 }, |
| { 74U, PPC::CR6 }, |
| { 75U, PPC::CR7 }, |
| { 76U, PPC::XER }, |
| { 77U, PPC::VF0 }, |
| { 78U, PPC::VF1 }, |
| { 79U, PPC::VF2 }, |
| { 80U, PPC::VF3 }, |
| { 81U, PPC::VF4 }, |
| { 82U, PPC::VF5 }, |
| { 83U, PPC::VF6 }, |
| { 84U, PPC::VF7 }, |
| { 85U, PPC::VF8 }, |
| { 86U, PPC::VF9 }, |
| { 87U, PPC::VF10 }, |
| { 88U, PPC::VF11 }, |
| { 89U, PPC::VF12 }, |
| { 90U, PPC::VF13 }, |
| { 91U, PPC::VF14 }, |
| { 92U, PPC::VF15 }, |
| { 93U, PPC::VF16 }, |
| { 94U, PPC::VF17 }, |
| { 95U, PPC::VF18 }, |
| { 96U, PPC::VF19 }, |
| { 97U, PPC::VF20 }, |
| { 98U, PPC::VF21 }, |
| { 99U, PPC::VF22 }, |
| { 100U, PPC::VF23 }, |
| { 101U, PPC::VF24 }, |
| { 102U, PPC::VF25 }, |
| { 103U, PPC::VF26 }, |
| { 104U, PPC::VF27 }, |
| { 105U, PPC::VF28 }, |
| { 106U, PPC::VF29 }, |
| { 107U, PPC::VF30 }, |
| { 108U, PPC::VF31 }, |
| { 109U, PPC::VRSAVE }, |
| { 612U, PPC::SPEFSCR }, |
| { 1200U, PPC::S0 }, |
| { 1201U, PPC::S1 }, |
| { 1202U, PPC::S2 }, |
| { 1203U, PPC::S3 }, |
| { 1204U, PPC::S4 }, |
| { 1205U, PPC::S5 }, |
| { 1206U, PPC::S6 }, |
| { 1207U, PPC::S7 }, |
| { 1208U, PPC::S8 }, |
| { 1209U, PPC::S9 }, |
| { 1210U, PPC::S10 }, |
| { 1211U, PPC::S11 }, |
| { 1212U, PPC::S12 }, |
| { 1213U, PPC::S13 }, |
| { 1214U, PPC::S14 }, |
| { 1215U, PPC::S15 }, |
| { 1216U, PPC::S16 }, |
| { 1217U, PPC::S17 }, |
| { 1218U, PPC::S18 }, |
| { 1219U, PPC::S19 }, |
| { 1220U, PPC::S20 }, |
| { 1221U, PPC::S21 }, |
| { 1222U, PPC::S22 }, |
| { 1223U, PPC::S23 }, |
| { 1224U, PPC::S24 }, |
| { 1225U, PPC::S25 }, |
| { 1226U, PPC::S26 }, |
| { 1227U, PPC::S27 }, |
| { 1228U, PPC::S28 }, |
| { 1229U, PPC::S29 }, |
| { 1230U, PPC::S30 }, |
| { 1231U, PPC::S31 }, |
| }; |
| extern const unsigned PPCDwarfFlavour0Dwarf2LSize = array_lengthof(PPCDwarfFlavour0Dwarf2L); |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1Dwarf2L[] = { |
| { 0U, PPC::R0 }, |
| { 1U, PPC::R1 }, |
| { 2U, PPC::R2 }, |
| { 3U, PPC::R3 }, |
| { 4U, PPC::R4 }, |
| { 5U, PPC::R5 }, |
| { 6U, PPC::R6 }, |
| { 7U, PPC::R7 }, |
| { 8U, PPC::R8 }, |
| { 9U, PPC::R9 }, |
| { 10U, PPC::R10 }, |
| { 11U, PPC::R11 }, |
| { 12U, PPC::R12 }, |
| { 13U, PPC::R13 }, |
| { 14U, PPC::R14 }, |
| { 15U, PPC::R15 }, |
| { 16U, PPC::R16 }, |
| { 17U, PPC::R17 }, |
| { 18U, PPC::R18 }, |
| { 19U, PPC::R19 }, |
| { 20U, PPC::R20 }, |
| { 21U, PPC::R21 }, |
| { 22U, PPC::R22 }, |
| { 23U, PPC::R23 }, |
| { 24U, PPC::R24 }, |
| { 25U, PPC::R25 }, |
| { 26U, PPC::R26 }, |
| { 27U, PPC::R27 }, |
| { 28U, PPC::R28 }, |
| { 29U, PPC::R29 }, |
| { 30U, PPC::R30 }, |
| { 31U, PPC::R31 }, |
| { 32U, PPC::QF0 }, |
| { 33U, PPC::QF1 }, |
| { 34U, PPC::QF2 }, |
| { 35U, PPC::QF3 }, |
| { 36U, PPC::QF4 }, |
| { 37U, PPC::QF5 }, |
| { 38U, PPC::QF6 }, |
| { 39U, PPC::QF7 }, |
| { 40U, PPC::QF8 }, |
| { 41U, PPC::QF9 }, |
| { 42U, PPC::QF10 }, |
| { 43U, PPC::QF11 }, |
| { 44U, PPC::QF12 }, |
| { 45U, PPC::QF13 }, |
| { 46U, PPC::QF14 }, |
| { 47U, PPC::QF15 }, |
| { 48U, PPC::QF16 }, |
| { 49U, PPC::QF17 }, |
| { 50U, PPC::QF18 }, |
| { 51U, PPC::QF19 }, |
| { 52U, PPC::QF20 }, |
| { 53U, PPC::QF21 }, |
| { 54U, PPC::QF22 }, |
| { 55U, PPC::QF23 }, |
| { 56U, PPC::QF24 }, |
| { 57U, PPC::QF25 }, |
| { 58U, PPC::QF26 }, |
| { 59U, PPC::QF27 }, |
| { 60U, PPC::QF28 }, |
| { 61U, PPC::QF29 }, |
| { 62U, PPC::QF30 }, |
| { 63U, PPC::QF31 }, |
| { 65U, PPC::LR }, |
| { 66U, PPC::CTR }, |
| { 68U, PPC::CR0 }, |
| { 69U, PPC::CR1 }, |
| { 70U, PPC::CR2 }, |
| { 71U, PPC::CR3 }, |
| { 72U, PPC::CR4 }, |
| { 73U, PPC::CR5 }, |
| { 74U, PPC::CR6 }, |
| { 75U, PPC::CR7 }, |
| { 77U, PPC::VF0 }, |
| { 78U, PPC::VF1 }, |
| { 79U, PPC::VF2 }, |
| { 80U, PPC::VF3 }, |
| { 81U, PPC::VF4 }, |
| { 82U, PPC::VF5 }, |
| { 83U, PPC::VF6 }, |
| { 84U, PPC::VF7 }, |
| { 85U, PPC::VF8 }, |
| { 86U, PPC::VF9 }, |
| { 87U, PPC::VF10 }, |
| { 88U, PPC::VF11 }, |
| { 89U, PPC::VF12 }, |
| { 90U, PPC::VF13 }, |
| { 91U, PPC::VF14 }, |
| { 92U, PPC::VF15 }, |
| { 93U, PPC::VF16 }, |
| { 94U, PPC::VF17 }, |
| { 95U, PPC::VF18 }, |
| { 96U, PPC::VF19 }, |
| { 97U, PPC::VF20 }, |
| { 98U, PPC::VF21 }, |
| { 99U, PPC::VF22 }, |
| { 100U, PPC::VF23 }, |
| { 101U, PPC::VF24 }, |
| { 102U, PPC::VF25 }, |
| { 103U, PPC::VF26 }, |
| { 104U, PPC::VF27 }, |
| { 105U, PPC::VF28 }, |
| { 106U, PPC::VF29 }, |
| { 107U, PPC::VF30 }, |
| { 108U, PPC::VF31 }, |
| { 112U, PPC::SPEFSCR }, |
| { 1200U, PPC::S0 }, |
| { 1201U, PPC::S1 }, |
| { 1202U, PPC::S2 }, |
| { 1203U, PPC::S3 }, |
| { 1204U, PPC::S4 }, |
| { 1205U, PPC::S5 }, |
| { 1206U, PPC::S6 }, |
| { 1207U, PPC::S7 }, |
| { 1208U, PPC::S8 }, |
| { 1209U, PPC::S9 }, |
| { 1210U, PPC::S10 }, |
| { 1211U, PPC::S11 }, |
| { 1212U, PPC::S12 }, |
| { 1213U, PPC::S13 }, |
| { 1214U, PPC::S14 }, |
| { 1215U, PPC::S15 }, |
| { 1216U, PPC::S16 }, |
| { 1217U, PPC::S17 }, |
| { 1218U, PPC::S18 }, |
| { 1219U, PPC::S19 }, |
| { 1220U, PPC::S20 }, |
| { 1221U, PPC::S21 }, |
| { 1222U, PPC::S22 }, |
| { 1223U, PPC::S23 }, |
| { 1224U, PPC::S24 }, |
| { 1225U, PPC::S25 }, |
| { 1226U, PPC::S26 }, |
| { 1227U, PPC::S27 }, |
| { 1228U, PPC::S28 }, |
| { 1229U, PPC::S29 }, |
| { 1230U, PPC::S30 }, |
| { 1231U, PPC::S31 }, |
| }; |
| extern const unsigned PPCDwarfFlavour1Dwarf2LSize = array_lengthof(PPCDwarfFlavour1Dwarf2L); |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0Dwarf2L[] = { |
| { 0U, PPC::X0 }, |
| { 1U, PPC::X1 }, |
| { 2U, PPC::X2 }, |
| { 3U, PPC::X3 }, |
| { 4U, PPC::X4 }, |
| { 5U, PPC::X5 }, |
| { 6U, PPC::X6 }, |
| { 7U, PPC::X7 }, |
| { 8U, PPC::X8 }, |
| { 9U, PPC::X9 }, |
| { 10U, PPC::X10 }, |
| { 11U, PPC::X11 }, |
| { 12U, PPC::X12 }, |
| { 13U, PPC::X13 }, |
| { 14U, PPC::X14 }, |
| { 15U, PPC::X15 }, |
| { 16U, PPC::X16 }, |
| { 17U, PPC::X17 }, |
| { 18U, PPC::X18 }, |
| { 19U, PPC::X19 }, |
| { 20U, PPC::X20 }, |
| { 21U, PPC::X21 }, |
| { 22U, PPC::X22 }, |
| { 23U, PPC::X23 }, |
| { 24U, PPC::X24 }, |
| { 25U, PPC::X25 }, |
| { 26U, PPC::X26 }, |
| { 27U, PPC::X27 }, |
| { 28U, PPC::X28 }, |
| { 29U, PPC::X29 }, |
| { 30U, PPC::X30 }, |
| { 31U, PPC::X31 }, |
| { 32U, PPC::QF0 }, |
| { 33U, PPC::QF1 }, |
| { 34U, PPC::QF2 }, |
| { 35U, PPC::QF3 }, |
| { 36U, PPC::QF4 }, |
| { 37U, PPC::QF5 }, |
| { 38U, PPC::QF6 }, |
| { 39U, PPC::QF7 }, |
| { 40U, PPC::QF8 }, |
| { 41U, PPC::QF9 }, |
| { 42U, PPC::QF10 }, |
| { 43U, PPC::QF11 }, |
| { 44U, PPC::QF12 }, |
| { 45U, PPC::QF13 }, |
| { 46U, PPC::QF14 }, |
| { 47U, PPC::QF15 }, |
| { 48U, PPC::QF16 }, |
| { 49U, PPC::QF17 }, |
| { 50U, PPC::QF18 }, |
| { 51U, PPC::QF19 }, |
| { 52U, PPC::QF20 }, |
| { 53U, PPC::QF21 }, |
| { 54U, PPC::QF22 }, |
| { 55U, PPC::QF23 }, |
| { 56U, PPC::QF24 }, |
| { 57U, PPC::QF25 }, |
| { 58U, PPC::QF26 }, |
| { 59U, PPC::QF27 }, |
| { 60U, PPC::QF28 }, |
| { 61U, PPC::QF29 }, |
| { 62U, PPC::QF30 }, |
| { 63U, PPC::QF31 }, |
| { 65U, PPC::LR8 }, |
| { 66U, PPC::CTR8 }, |
| { 68U, PPC::CR0 }, |
| { 69U, PPC::CR1 }, |
| { 70U, PPC::CR2 }, |
| { 71U, PPC::CR3 }, |
| { 72U, PPC::CR4 }, |
| { 73U, PPC::CR5 }, |
| { 74U, PPC::CR6 }, |
| { 75U, PPC::CR7 }, |
| { 76U, PPC::XER }, |
| { 77U, PPC::VF0 }, |
| { 78U, PPC::VF1 }, |
| { 79U, PPC::VF2 }, |
| { 80U, PPC::VF3 }, |
| { 81U, PPC::VF4 }, |
| { 82U, PPC::VF5 }, |
| { 83U, PPC::VF6 }, |
| { 84U, PPC::VF7 }, |
| { 85U, PPC::VF8 }, |
| { 86U, PPC::VF9 }, |
| { 87U, PPC::VF10 }, |
| { 88U, PPC::VF11 }, |
| { 89U, PPC::VF12 }, |
| { 90U, PPC::VF13 }, |
| { 91U, PPC::VF14 }, |
| { 92U, PPC::VF15 }, |
| { 93U, PPC::VF16 }, |
| { 94U, PPC::VF17 }, |
| { 95U, PPC::VF18 }, |
| { 96U, PPC::VF19 }, |
| { 97U, PPC::VF20 }, |
| { 98U, PPC::VF21 }, |
| { 99U, PPC::VF22 }, |
| { 100U, PPC::VF23 }, |
| { 101U, PPC::VF24 }, |
| { 102U, PPC::VF25 }, |
| { 103U, PPC::VF26 }, |
| { 104U, PPC::VF27 }, |
| { 105U, PPC::VF28 }, |
| { 106U, PPC::VF29 }, |
| { 107U, PPC::VF30 }, |
| { 108U, PPC::VF31 }, |
| { 109U, PPC::VRSAVE }, |
| { 612U, PPC::SPEFSCR }, |
| { 1200U, PPC::S0 }, |
| { 1201U, PPC::S1 }, |
| { 1202U, PPC::S2 }, |
| { 1203U, PPC::S3 }, |
| { 1204U, PPC::S4 }, |
| { 1205U, PPC::S5 }, |
| { 1206U, PPC::S6 }, |
| { 1207U, PPC::S7 }, |
| { 1208U, PPC::S8 }, |
| { 1209U, PPC::S9 }, |
| { 1210U, PPC::S10 }, |
| { 1211U, PPC::S11 }, |
| { 1212U, PPC::S12 }, |
| { 1213U, PPC::S13 }, |
| { 1214U, PPC::S14 }, |
| { 1215U, PPC::S15 }, |
| { 1216U, PPC::S16 }, |
| { 1217U, PPC::S17 }, |
| { 1218U, PPC::S18 }, |
| { 1219U, PPC::S19 }, |
| { 1220U, PPC::S20 }, |
| { 1221U, PPC::S21 }, |
| { 1222U, PPC::S22 }, |
| { 1223U, PPC::S23 }, |
| { 1224U, PPC::S24 }, |
| { 1225U, PPC::S25 }, |
| { 1226U, PPC::S26 }, |
| { 1227U, PPC::S27 }, |
| { 1228U, PPC::S28 }, |
| { 1229U, PPC::S29 }, |
| { 1230U, PPC::S30 }, |
| { 1231U, PPC::S31 }, |
| }; |
| extern const unsigned PPCEHFlavour0Dwarf2LSize = array_lengthof(PPCEHFlavour0Dwarf2L); |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1Dwarf2L[] = { |
| { 0U, PPC::R0 }, |
| { 1U, PPC::R1 }, |
| { 2U, PPC::R2 }, |
| { 3U, PPC::R3 }, |
| { 4U, PPC::R4 }, |
| { 5U, PPC::R5 }, |
| { 6U, PPC::R6 }, |
| { 7U, PPC::R7 }, |
| { 8U, PPC::R8 }, |
| { 9U, PPC::R9 }, |
| { 10U, PPC::R10 }, |
| { 11U, PPC::R11 }, |
| { 12U, PPC::R12 }, |
| { 13U, PPC::R13 }, |
| { 14U, PPC::R14 }, |
| { 15U, PPC::R15 }, |
| { 16U, PPC::R16 }, |
| { 17U, PPC::R17 }, |
| { 18U, PPC::R18 }, |
| { 19U, PPC::R19 }, |
| { 20U, PPC::R20 }, |
| { 21U, PPC::R21 }, |
| { 22U, PPC::R22 }, |
| { 23U, PPC::R23 }, |
| { 24U, PPC::R24 }, |
| { 25U, PPC::R25 }, |
| { 26U, PPC::R26 }, |
| { 27U, PPC::R27 }, |
| { 28U, PPC::R28 }, |
| { 29U, PPC::R29 }, |
| { 30U, PPC::R30 }, |
| { 31U, PPC::R31 }, |
| { 32U, PPC::QF0 }, |
| { 33U, PPC::QF1 }, |
| { 34U, PPC::QF2 }, |
| { 35U, PPC::QF3 }, |
| { 36U, PPC::QF4 }, |
| { 37U, PPC::QF5 }, |
| { 38U, PPC::QF6 }, |
| { 39U, PPC::QF7 }, |
| { 40U, PPC::QF8 }, |
| { 41U, PPC::QF9 }, |
| { 42U, PPC::QF10 }, |
| { 43U, PPC::QF11 }, |
| { 44U, PPC::QF12 }, |
| { 45U, PPC::QF13 }, |
| { 46U, PPC::QF14 }, |
| { 47U, PPC::QF15 }, |
| { 48U, PPC::QF16 }, |
| { 49U, PPC::QF17 }, |
| { 50U, PPC::QF18 }, |
| { 51U, PPC::QF19 }, |
| { 52U, PPC::QF20 }, |
| { 53U, PPC::QF21 }, |
| { 54U, PPC::QF22 }, |
| { 55U, PPC::QF23 }, |
| { 56U, PPC::QF24 }, |
| { 57U, PPC::QF25 }, |
| { 58U, PPC::QF26 }, |
| { 59U, PPC::QF27 }, |
| { 60U, PPC::QF28 }, |
| { 61U, PPC::QF29 }, |
| { 62U, PPC::QF30 }, |
| { 63U, PPC::QF31 }, |
| { 65U, PPC::LR }, |
| { 66U, PPC::CTR }, |
| { 68U, PPC::CR0 }, |
| { 69U, PPC::CR1 }, |
| { 70U, PPC::CR2 }, |
| { 71U, PPC::CR3 }, |
| { 72U, PPC::CR4 }, |
| { 73U, PPC::CR5 }, |
| { 74U, PPC::CR6 }, |
| { 75U, PPC::CR7 }, |
| { 77U, PPC::VF0 }, |
| { 78U, PPC::VF1 }, |
| { 79U, PPC::VF2 }, |
| { 80U, PPC::VF3 }, |
| { 81U, PPC::VF4 }, |
| { 82U, PPC::VF5 }, |
| { 83U, PPC::VF6 }, |
| { 84U, PPC::VF7 }, |
| { 85U, PPC::VF8 }, |
| { 86U, PPC::VF9 }, |
| { 87U, PPC::VF10 }, |
| { 88U, PPC::VF11 }, |
| { 89U, PPC::VF12 }, |
| { 90U, PPC::VF13 }, |
| { 91U, PPC::VF14 }, |
| { 92U, PPC::VF15 }, |
| { 93U, PPC::VF16 }, |
| { 94U, PPC::VF17 }, |
| { 95U, PPC::VF18 }, |
| { 96U, PPC::VF19 }, |
| { 97U, PPC::VF20 }, |
| { 98U, PPC::VF21 }, |
| { 99U, PPC::VF22 }, |
| { 100U, PPC::VF23 }, |
| { 101U, PPC::VF24 }, |
| { 102U, PPC::VF25 }, |
| { 103U, PPC::VF26 }, |
| { 104U, PPC::VF27 }, |
| { 105U, PPC::VF28 }, |
| { 106U, PPC::VF29 }, |
| { 107U, PPC::VF30 }, |
| { 108U, PPC::VF31 }, |
| { 112U, PPC::SPEFSCR }, |
| { 1200U, PPC::S0 }, |
| { 1201U, PPC::S1 }, |
| { 1202U, PPC::S2 }, |
| { 1203U, PPC::S3 }, |
| { 1204U, PPC::S4 }, |
| { 1205U, PPC::S5 }, |
| { 1206U, PPC::S6 }, |
| { 1207U, PPC::S7 }, |
| { 1208U, PPC::S8 }, |
| { 1209U, PPC::S9 }, |
| { 1210U, PPC::S10 }, |
| { 1211U, PPC::S11 }, |
| { 1212U, PPC::S12 }, |
| { 1213U, PPC::S13 }, |
| { 1214U, PPC::S14 }, |
| { 1215U, PPC::S15 }, |
| { 1216U, PPC::S16 }, |
| { 1217U, PPC::S17 }, |
| { 1218U, PPC::S18 }, |
| { 1219U, PPC::S19 }, |
| { 1220U, PPC::S20 }, |
| { 1221U, PPC::S21 }, |
| { 1222U, PPC::S22 }, |
| { 1223U, PPC::S23 }, |
| { 1224U, PPC::S24 }, |
| { 1225U, PPC::S25 }, |
| { 1226U, PPC::S26 }, |
| { 1227U, PPC::S27 }, |
| { 1228U, PPC::S28 }, |
| { 1229U, PPC::S29 }, |
| { 1230U, PPC::S30 }, |
| { 1231U, PPC::S31 }, |
| }; |
| extern const unsigned PPCEHFlavour1Dwarf2LSize = array_lengthof(PPCEHFlavour1Dwarf2L); |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0L2Dwarf[] = { |
| { PPC::CARRY, 76U }, |
| { PPC::CTR, -2U }, |
| { PPC::LR, -2U }, |
| { PPC::SPEFSCR, 612U }, |
| { PPC::VRSAVE, 109U }, |
| { PPC::XER, 76U }, |
| { PPC::ZERO, -2U }, |
| { PPC::CR0, 68U }, |
| { PPC::CR1, 69U }, |
| { PPC::CR2, 70U }, |
| { PPC::CR3, 71U }, |
| { PPC::CR4, 72U }, |
| { PPC::CR5, 73U }, |
| { PPC::CR6, 74U }, |
| { PPC::CR7, 75U }, |
| { PPC::CTR8, 66U }, |
| { PPC::F0, 32U }, |
| { PPC::F1, 33U }, |
| { PPC::F2, 34U }, |
| { PPC::F3, 35U }, |
| { PPC::F4, 36U }, |
| { PPC::F5, 37U }, |
| { PPC::F6, 38U }, |
| { PPC::F7, 39U }, |
| { PPC::F8, 40U }, |
| { PPC::F9, 41U }, |
| { PPC::F10, 42U }, |
| { PPC::F11, 43U }, |
| { PPC::F12, 44U }, |
| { PPC::F13, 45U }, |
| { PPC::F14, 46U }, |
| { PPC::F15, 47U }, |
| { PPC::F16, 48U }, |
| { PPC::F17, 49U }, |
| { PPC::F18, 50U }, |
| { PPC::F19, 51U }, |
| { PPC::F20, 52U }, |
| { PPC::F21, 53U }, |
| { PPC::F22, 54U }, |
| { PPC::F23, 55U }, |
| { PPC::F24, 56U }, |
| { PPC::F25, 57U }, |
| { PPC::F26, 58U }, |
| { PPC::F27, 59U }, |
| { PPC::F28, 60U }, |
| { PPC::F29, 61U }, |
| { PPC::F30, 62U }, |
| { PPC::F31, 63U }, |
| { PPC::LR8, 65U }, |
| { PPC::QF0, 32U }, |
| { PPC::QF1, 33U }, |
| { PPC::QF2, 34U }, |
| { PPC::QF3, 35U }, |
| { PPC::QF4, 36U }, |
| { PPC::QF5, 37U }, |
| { PPC::QF6, 38U }, |
| { PPC::QF7, 39U }, |
| { PPC::QF8, 40U }, |
| { PPC::QF9, 41U }, |
| { PPC::QF10, 42U }, |
| { PPC::QF11, 43U }, |
| { PPC::QF12, 44U }, |
| { PPC::QF13, 45U }, |
| { PPC::QF14, 46U }, |
| { PPC::QF15, 47U }, |
| { PPC::QF16, 48U }, |
| { PPC::QF17, 49U }, |
| { PPC::QF18, 50U }, |
| { PPC::QF19, 51U }, |
| { PPC::QF20, 52U }, |
| { PPC::QF21, 53U }, |
| { PPC::QF22, 54U }, |
| { PPC::QF23, 55U }, |
| { PPC::QF24, 56U }, |
| { PPC::QF25, 57U }, |
| { PPC::QF26, 58U }, |
| { PPC::QF27, 59U }, |
| { PPC::QF28, 60U }, |
| { PPC::QF29, 61U }, |
| { PPC::QF30, 62U }, |
| { PPC::QF31, 63U }, |
| { PPC::R0, -2U }, |
| { PPC::R1, -2U }, |
| { PPC::R2, -2U }, |
| { PPC::R3, -2U }, |
| { PPC::R4, -2U }, |
| { PPC::R5, -2U }, |
| { PPC::R6, -2U }, |
| { PPC::R7, -2U }, |
| { PPC::R8, -2U }, |
| { PPC::R9, -2U }, |
| { PPC::R10, -2U }, |
| { PPC::R11, -2U }, |
| { PPC::R12, -2U }, |
| { PPC::R13, -2U }, |
| { PPC::R14, -2U }, |
| { PPC::R15, -2U }, |
| { PPC::R16, -2U }, |
| { PPC::R17, -2U }, |
| { PPC::R18, -2U }, |
| { PPC::R19, -2U }, |
| { PPC::R20, -2U }, |
| { PPC::R21, -2U }, |
| { PPC::R22, -2U }, |
| { PPC::R23, -2U }, |
| { PPC::R24, -2U }, |
| { PPC::R25, -2U }, |
| { PPC::R26, -2U }, |
| { PPC::R27, -2U }, |
| { PPC::R28, -2U }, |
| { PPC::R29, -2U }, |
| { PPC::R30, -2U }, |
| { PPC::R31, -2U }, |
| { PPC::S0, 1200U }, |
| { PPC::S1, 1201U }, |
| { PPC::S2, 1202U }, |
| { PPC::S3, 1203U }, |
| { PPC::S4, 1204U }, |
| { PPC::S5, 1205U }, |
| { PPC::S6, 1206U }, |
| { PPC::S7, 1207U }, |
| { PPC::S8, 1208U }, |
| { PPC::S9, 1209U }, |
| { PPC::S10, 1210U }, |
| { PPC::S11, 1211U }, |
| { PPC::S12, 1212U }, |
| { PPC::S13, 1213U }, |
| { PPC::S14, 1214U }, |
| { PPC::S15, 1215U }, |
| { PPC::S16, 1216U }, |
| { PPC::S17, 1217U }, |
| { PPC::S18, 1218U }, |
| { PPC::S19, 1219U }, |
| { PPC::S20, 1220U }, |
| { PPC::S21, 1221U }, |
| { PPC::S22, 1222U }, |
| { PPC::S23, 1223U }, |
| { PPC::S24, 1224U }, |
| { PPC::S25, 1225U }, |
| { PPC::S26, 1226U }, |
| { PPC::S27, 1227U }, |
| { PPC::S28, 1228U }, |
| { PPC::S29, 1229U }, |
| { PPC::S30, 1230U }, |
| { PPC::S31, 1231U }, |
| { PPC::V0, 77U }, |
| { PPC::V1, 78U }, |
| { PPC::V2, 79U }, |
| { PPC::V3, 80U }, |
| { PPC::V4, 81U }, |
| { PPC::V5, 82U }, |
| { PPC::V6, 83U }, |
| { PPC::V7, 84U }, |
| { PPC::V8, 85U }, |
| { PPC::V9, 86U }, |
| { PPC::V10, 87U }, |
| { PPC::V11, 88U }, |
| { PPC::V12, 89U }, |
| { PPC::V13, 90U }, |
| { PPC::V14, 91U }, |
| { PPC::V15, 92U }, |
| { PPC::V16, 93U }, |
| { PPC::V17, 94U }, |
| { PPC::V18, 95U }, |
| { PPC::V19, 96U }, |
| { PPC::V20, 97U }, |
| { PPC::V21, 98U }, |
| { PPC::V22, 99U }, |
| { PPC::V23, 100U }, |
| { PPC::V24, 101U }, |
| { PPC::V25, 102U }, |
| { PPC::V26, 103U }, |
| { PPC::V27, 104U }, |
| { PPC::V28, 105U }, |
| { PPC::V29, 106U }, |
| { PPC::V30, 107U }, |
| { PPC::V31, 108U }, |
| { PPC::VF0, 77U }, |
| { PPC::VF1, 78U }, |
| { PPC::VF2, 79U }, |
| { PPC::VF3, 80U }, |
| { PPC::VF4, 81U }, |
| { PPC::VF5, 82U }, |
| { PPC::VF6, 83U }, |
| { PPC::VF7, 84U }, |
| { PPC::VF8, 85U }, |
| { PPC::VF9, 86U }, |
| { PPC::VF10, 87U }, |
| { PPC::VF11, 88U }, |
| { PPC::VF12, 89U }, |
| { PPC::VF13, 90U }, |
| { PPC::VF14, 91U }, |
| { PPC::VF15, 92U }, |
| { PPC::VF16, 93U }, |
| { PPC::VF17, 94U }, |
| { PPC::VF18, 95U }, |
| { PPC::VF19, 96U }, |
| { PPC::VF20, 97U }, |
| { PPC::VF21, 98U }, |
| { PPC::VF22, 99U }, |
| { PPC::VF23, 100U }, |
| { PPC::VF24, 101U }, |
| { PPC::VF25, 102U }, |
| { PPC::VF26, 103U }, |
| { PPC::VF27, 104U }, |
| { PPC::VF28, 105U }, |
| { PPC::VF29, 106U }, |
| { PPC::VF30, 107U }, |
| { PPC::VF31, 108U }, |
| { PPC::VSL0, 32U }, |
| { PPC::VSL1, 33U }, |
| { PPC::VSL2, 34U }, |
| { PPC::VSL3, 35U }, |
| { PPC::VSL4, 36U }, |
| { PPC::VSL5, 37U }, |
| { PPC::VSL6, 38U }, |
| { PPC::VSL7, 39U }, |
| { PPC::VSL8, 40U }, |
| { PPC::VSL9, 41U }, |
| { PPC::VSL10, 42U }, |
| { PPC::VSL11, 43U }, |
| { PPC::VSL12, 44U }, |
| { PPC::VSL13, 45U }, |
| { PPC::VSL14, 46U }, |
| { PPC::VSL15, 47U }, |
| { PPC::VSL16, 48U }, |
| { PPC::VSL17, 49U }, |
| { PPC::VSL18, 50U }, |
| { PPC::VSL19, 51U }, |
| { PPC::VSL20, 52U }, |
| { PPC::VSL21, 53U }, |
| { PPC::VSL22, 54U }, |
| { PPC::VSL23, 55U }, |
| { PPC::VSL24, 56U }, |
| { PPC::VSL25, 57U }, |
| { PPC::VSL26, 58U }, |
| { PPC::VSL27, 59U }, |
| { PPC::VSL28, 60U }, |
| { PPC::VSL29, 61U }, |
| { PPC::VSL30, 62U }, |
| { PPC::VSL31, 63U }, |
| { PPC::X0, 0U }, |
| { PPC::X1, 1U }, |
| { PPC::X2, 2U }, |
| { PPC::X3, 3U }, |
| { PPC::X4, 4U }, |
| { PPC::X5, 5U }, |
| { PPC::X6, 6U }, |
| { PPC::X7, 7U }, |
| { PPC::X8, 8U }, |
| { PPC::X9, 9U }, |
| { PPC::X10, 10U }, |
| { PPC::X11, 11U }, |
| { PPC::X12, 12U }, |
| { PPC::X13, 13U }, |
| { PPC::X14, 14U }, |
| { PPC::X15, 15U }, |
| { PPC::X16, 16U }, |
| { PPC::X17, 17U }, |
| { PPC::X18, 18U }, |
| { PPC::X19, 19U }, |
| { PPC::X20, 20U }, |
| { PPC::X21, 21U }, |
| { PPC::X22, 22U }, |
| { PPC::X23, 23U }, |
| { PPC::X24, 24U }, |
| { PPC::X25, 25U }, |
| { PPC::X26, 26U }, |
| { PPC::X27, 27U }, |
| { PPC::X28, 28U }, |
| { PPC::X29, 29U }, |
| { PPC::X30, 30U }, |
| { PPC::X31, 31U }, |
| { PPC::ZERO8, 0U }, |
| }; |
| extern const unsigned PPCDwarfFlavour0L2DwarfSize = array_lengthof(PPCDwarfFlavour0L2Dwarf); |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1L2Dwarf[] = { |
| { PPC::CTR, 66U }, |
| { PPC::LR, 65U }, |
| { PPC::SPEFSCR, 112U }, |
| { PPC::ZERO, 0U }, |
| { PPC::CR0, 68U }, |
| { PPC::CR1, 69U }, |
| { PPC::CR2, 70U }, |
| { PPC::CR3, 71U }, |
| { PPC::CR4, 72U }, |
| { PPC::CR5, 73U }, |
| { PPC::CR6, 74U }, |
| { PPC::CR7, 75U }, |
| { PPC::CTR8, -2U }, |
| { PPC::F0, 32U }, |
| { PPC::F1, 33U }, |
| { PPC::F2, 34U }, |
| { PPC::F3, 35U }, |
| { PPC::F4, 36U }, |
| { PPC::F5, 37U }, |
| { PPC::F6, 38U }, |
| { PPC::F7, 39U }, |
| { PPC::F8, 40U }, |
| { PPC::F9, 41U }, |
| { PPC::F10, 42U }, |
| { PPC::F11, 43U }, |
| { PPC::F12, 44U }, |
| { PPC::F13, 45U }, |
| { PPC::F14, 46U }, |
| { PPC::F15, 47U }, |
| { PPC::F16, 48U }, |
| { PPC::F17, 49U }, |
| { PPC::F18, 50U }, |
| { PPC::F19, 51U }, |
| { PPC::F20, 52U }, |
| { PPC::F21, 53U }, |
| { PPC::F22, 54U }, |
| { PPC::F23, 55U }, |
| { PPC::F24, 56U }, |
| { PPC::F25, 57U }, |
| { PPC::F26, 58U }, |
| { PPC::F27, 59U }, |
| { PPC::F28, 60U }, |
| { PPC::F29, 61U }, |
| { PPC::F30, 62U }, |
| { PPC::F31, 63U }, |
| { PPC::LR8, -2U }, |
| { PPC::QF0, 32U }, |
| { PPC::QF1, 33U }, |
| { PPC::QF2, 34U }, |
| { PPC::QF3, 35U }, |
| { PPC::QF4, 36U }, |
| { PPC::QF5, 37U }, |
| { PPC::QF6, 38U }, |
| { PPC::QF7, 39U }, |
| { PPC::QF8, 40U }, |
| { PPC::QF9, 41U }, |
| { PPC::QF10, 42U }, |
| { PPC::QF11, 43U }, |
| { PPC::QF12, 44U }, |
| { PPC::QF13, 45U }, |
| { PPC::QF14, 46U }, |
| { PPC::QF15, 47U }, |
| { PPC::QF16, 48U }, |
| { PPC::QF17, 49U }, |
| { PPC::QF18, 50U }, |
| { PPC::QF19, 51U }, |
| { PPC::QF20, 52U }, |
| { PPC::QF21, 53U }, |
| { PPC::QF22, 54U }, |
| { PPC::QF23, 55U }, |
| { PPC::QF24, 56U }, |
| { PPC::QF25, 57U }, |
| { PPC::QF26, 58U }, |
| { PPC::QF27, 59U }, |
| { PPC::QF28, 60U }, |
| { PPC::QF29, 61U }, |
| { PPC::QF30, 62U }, |
| { PPC::QF31, 63U }, |
| { PPC::R0, 0U }, |
| { PPC::R1, 1U }, |
| { PPC::R2, 2U }, |
| { PPC::R3, 3U }, |
| { PPC::R4, 4U }, |
| { PPC::R5, 5U }, |
| { PPC::R6, 6U }, |
| { PPC::R7, 7U }, |
| { PPC::R8, 8U }, |
| { PPC::R9, 9U }, |
| { PPC::R10, 10U }, |
| { PPC::R11, 11U }, |
| { PPC::R12, 12U }, |
| { PPC::R13, 13U }, |
| { PPC::R14, 14U }, |
| { PPC::R15, 15U }, |
| { PPC::R16, 16U }, |
| { PPC::R17, 17U }, |
| { PPC::R18, 18U }, |
| { PPC::R19, 19U }, |
| { PPC::R20, 20U }, |
| { PPC::R21, 21U }, |
| { PPC::R22, 22U }, |
| { PPC::R23, 23U }, |
| { PPC::R24, 24U }, |
| { PPC::R25, 25U }, |
| { PPC::R26, 26U }, |
| { PPC::R27, 27U }, |
| { PPC::R28, 28U }, |
| { PPC::R29, 29U }, |
| { PPC::R30, 30U }, |
| { PPC::R31, 31U }, |
| { PPC::S0, 1200U }, |
| { PPC::S1, 1201U }, |
| { PPC::S2, 1202U }, |
| { PPC::S3, 1203U }, |
| { PPC::S4, 1204U }, |
| { PPC::S5, 1205U }, |
| { PPC::S6, 1206U }, |
| { PPC::S7, 1207U }, |
| { PPC::S8, 1208U }, |
| { PPC::S9, 1209U }, |
| { PPC::S10, 1210U }, |
| { PPC::S11, 1211U }, |
| { PPC::S12, 1212U }, |
| { PPC::S13, 1213U }, |
| { PPC::S14, 1214U }, |
| { PPC::S15, 1215U }, |
| { PPC::S16, 1216U }, |
| { PPC::S17, 1217U }, |
| { PPC::S18, 1218U }, |
| { PPC::S19, 1219U }, |
| { PPC::S20, 1220U }, |
| { PPC::S21, 1221U }, |
| { PPC::S22, 1222U }, |
| { PPC::S23, 1223U }, |
| { PPC::S24, 1224U }, |
| { PPC::S25, 1225U }, |
| { PPC::S26, 1226U }, |
| { PPC::S27, 1227U }, |
| { PPC::S28, 1228U }, |
| { PPC::S29, 1229U }, |
| { PPC::S30, 1230U }, |
| { PPC::S31, 1231U }, |
| { PPC::V0, 77U }, |
| { PPC::V1, 78U }, |
| { PPC::V2, 79U }, |
| { PPC::V3, 80U }, |
| { PPC::V4, 81U }, |
| { PPC::V5, 82U }, |
| { PPC::V6, 83U }, |
| { PPC::V7, 84U }, |
| { PPC::V8, 85U }, |
| { PPC::V9, 86U }, |
| { PPC::V10, 87U }, |
| { PPC::V11, 88U }, |
| { PPC::V12, 89U }, |
| { PPC::V13, 90U }, |
| { PPC::V14, 91U }, |
| { PPC::V15, 92U }, |
| { PPC::V16, 93U }, |
| { PPC::V17, 94U }, |
| { PPC::V18, 95U }, |
| { PPC::V19, 96U }, |
| { PPC::V20, 97U }, |
| { PPC::V21, 98U }, |
| { PPC::V22, 99U }, |
| { PPC::V23, 100U }, |
| { PPC::V24, 101U }, |
| { PPC::V25, 102U }, |
| { PPC::V26, 103U }, |
| { PPC::V27, 104U }, |
| { PPC::V28, 105U }, |
| { PPC::V29, 106U }, |
| { PPC::V30, 107U }, |
| { PPC::V31, 108U }, |
| { PPC::VF0, 77U }, |
| { PPC::VF1, 78U }, |
| { PPC::VF2, 79U }, |
| { PPC::VF3, 80U }, |
| { PPC::VF4, 81U }, |
| { PPC::VF5, 82U }, |
| { PPC::VF6, 83U }, |
| { PPC::VF7, 84U }, |
| { PPC::VF8, 85U }, |
| { PPC::VF9, 86U }, |
| { PPC::VF10, 87U }, |
| { PPC::VF11, 88U }, |
| { PPC::VF12, 89U }, |
| { PPC::VF13, 90U }, |
| { PPC::VF14, 91U }, |
| { PPC::VF15, 92U }, |
| { PPC::VF16, 93U }, |
| { PPC::VF17, 94U }, |
| { PPC::VF18, 95U }, |
| { PPC::VF19, 96U }, |
| { PPC::VF20, 97U }, |
| { PPC::VF21, 98U }, |
| { PPC::VF22, 99U }, |
| { PPC::VF23, 100U }, |
| { PPC::VF24, 101U }, |
| { PPC::VF25, 102U }, |
| { PPC::VF26, 103U }, |
| { PPC::VF27, 104U }, |
| { PPC::VF28, 105U }, |
| { PPC::VF29, 106U }, |
| { PPC::VF30, 107U }, |
| { PPC::VF31, 108U }, |
| { PPC::VSL0, 32U }, |
| { PPC::VSL1, 33U }, |
| { PPC::VSL2, 34U }, |
| { PPC::VSL3, 35U }, |
| { PPC::VSL4, 36U }, |
| { PPC::VSL5, 37U }, |
| { PPC::VSL6, 38U }, |
| { PPC::VSL7, 39U }, |
| { PPC::VSL8, 40U }, |
| { PPC::VSL9, 41U }, |
| { PPC::VSL10, 42U }, |
| { PPC::VSL11, 43U }, |
| { PPC::VSL12, 44U }, |
| { PPC::VSL13, 45U }, |
| { PPC::VSL14, 46U }, |
| { PPC::VSL15, 47U }, |
| { PPC::VSL16, 48U }, |
| { PPC::VSL17, 49U }, |
| { PPC::VSL18, 50U }, |
| { PPC::VSL19, 51U }, |
| { PPC::VSL20, 52U }, |
| { PPC::VSL21, 53U }, |
| { PPC::VSL22, 54U }, |
| { PPC::VSL23, 55U }, |
| { PPC::VSL24, 56U }, |
| { PPC::VSL25, 57U }, |
| { PPC::VSL26, 58U }, |
| { PPC::VSL27, 59U }, |
| { PPC::VSL28, 60U }, |
| { PPC::VSL29, 61U }, |
| { PPC::VSL30, 62U }, |
| { PPC::VSL31, 63U }, |
| { PPC::X0, -2U }, |
| { PPC::X1, -2U }, |
| { PPC::X2, -2U }, |
| { PPC::X3, -2U }, |
| { PPC::X4, -2U }, |
| { PPC::X5, -2U }, |
| { PPC::X6, -2U }, |
| { PPC::X7, -2U }, |
| { PPC::X8, -2U }, |
| { PPC::X9, -2U }, |
| { PPC::X10, -2U }, |
| { PPC::X11, -2U }, |
| { PPC::X12, -2U }, |
| { PPC::X13, -2U }, |
| { PPC::X14, -2U }, |
| { PPC::X15, -2U }, |
| { PPC::X16, -2U }, |
| { PPC::X17, -2U }, |
| { PPC::X18, -2U }, |
| { PPC::X19, -2U }, |
| { PPC::X20, -2U }, |
| { PPC::X21, -2U }, |
| { PPC::X22, -2U }, |
| { PPC::X23, -2U }, |
| { PPC::X24, -2U }, |
| { PPC::X25, -2U }, |
| { PPC::X26, -2U }, |
| { PPC::X27, -2U }, |
| { PPC::X28, -2U }, |
| { PPC::X29, -2U }, |
| { PPC::X30, -2U }, |
| { PPC::X31, -2U }, |
| { PPC::ZERO8, -2U }, |
| }; |
| extern const unsigned PPCDwarfFlavour1L2DwarfSize = array_lengthof(PPCDwarfFlavour1L2Dwarf); |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0L2Dwarf[] = { |
| { PPC::CARRY, 76U }, |
| { PPC::CTR, -2U }, |
| { PPC::LR, -2U }, |
| { PPC::SPEFSCR, 612U }, |
| { PPC::VRSAVE, 109U }, |
| { PPC::XER, 76U }, |
| { PPC::ZERO, -2U }, |
| { PPC::CR0, 68U }, |
| { PPC::CR1, 69U }, |
| { PPC::CR2, 70U }, |
| { PPC::CR3, 71U }, |
| { PPC::CR4, 72U }, |
| { PPC::CR5, 73U }, |
| { PPC::CR6, 74U }, |
| { PPC::CR7, 75U }, |
| { PPC::CTR8, 66U }, |
| { PPC::F0, 32U }, |
| { PPC::F1, 33U }, |
| { PPC::F2, 34U }, |
| { PPC::F3, 35U }, |
| { PPC::F4, 36U }, |
| { PPC::F5, 37U }, |
| { PPC::F6, 38U }, |
| { PPC::F7, 39U }, |
| { PPC::F8, 40U }, |
| { PPC::F9, 41U }, |
| { PPC::F10, 42U }, |
| { PPC::F11, 43U }, |
| { PPC::F12, 44U }, |
| { PPC::F13, 45U }, |
| { PPC::F14, 46U }, |
| { PPC::F15, 47U }, |
| { PPC::F16, 48U }, |
| { PPC::F17, 49U }, |
| { PPC::F18, 50U }, |
| { PPC::F19, 51U }, |
| { PPC::F20, 52U }, |
| { PPC::F21, 53U }, |
| { PPC::F22, 54U }, |
| { PPC::F23, 55U }, |
| { PPC::F24, 56U }, |
| { PPC::F25, 57U }, |
| { PPC::F26, 58U }, |
| { PPC::F27, 59U }, |
| { PPC::F28, 60U }, |
| { PPC::F29, 61U }, |
| { PPC::F30, 62U }, |
| { PPC::F31, 63U }, |
| { PPC::LR8, 65U }, |
| { PPC::QF0, 32U }, |
| { PPC::QF1, 33U }, |
| { PPC::QF2, 34U }, |
| { PPC::QF3, 35U }, |
| { PPC::QF4, 36U }, |
| { PPC::QF5, 37U }, |
| { PPC::QF6, 38U }, |
| { PPC::QF7, 39U }, |
| { PPC::QF8, 40U }, |
| { PPC::QF9, 41U }, |
| { PPC::QF10, 42U }, |
| { PPC::QF11, 43U }, |
| { PPC::QF12, 44U }, |
| { PPC::QF13, 45U }, |
| { PPC::QF14, 46U }, |
| { PPC::QF15, 47U }, |
| { PPC::QF16, 48U }, |
| { PPC::QF17, 49U }, |
| { PPC::QF18, 50U }, |
| { PPC::QF19, 51U }, |
| { PPC::QF20, 52U }, |
| { PPC::QF21, 53U }, |
| { PPC::QF22, 54U }, |
| { PPC::QF23, 55U }, |
| { PPC::QF24, 56U }, |
| { PPC::QF25, 57U }, |
| { PPC::QF26, 58U }, |
| { PPC::QF27, 59U }, |
| { PPC::QF28, 60U }, |
| { PPC::QF29, 61U }, |
| { PPC::QF30, 62U }, |
| { PPC::QF31, 63U }, |
| { PPC::R0, -2U }, |
| { PPC::R1, -2U }, |
| { PPC::R2, -2U }, |
| { PPC::R3, -2U }, |
| { PPC::R4, -2U }, |
| { PPC::R5, -2U }, |
| { PPC::R6, -2U }, |
| { PPC::R7, -2U }, |
| { PPC::R8, -2U }, |
| { PPC::R9, -2U }, |
| { PPC::R10, -2U }, |
| { PPC::R11, -2U }, |
| { PPC::R12, -2U }, |
| { PPC::R13, -2U }, |
| { PPC::R14, -2U }, |
| { PPC::R15, -2U }, |
| { PPC::R16, -2U }, |
| { PPC::R17, -2U }, |
| { PPC::R18, -2U }, |
| { PPC::R19, -2U }, |
| { PPC::R20, -2U }, |
| { PPC::R21, -2U }, |
| { PPC::R22, -2U }, |
| { PPC::R23, -2U }, |
| { PPC::R24, -2U }, |
| { PPC::R25, -2U }, |
| { PPC::R26, -2U }, |
| { PPC::R27, -2U }, |
| { PPC::R28, -2U }, |
| { PPC::R29, -2U }, |
| { PPC::R30, -2U }, |
| { PPC::R31, -2U }, |
| { PPC::S0, 1200U }, |
| { PPC::S1, 1201U }, |
| { PPC::S2, 1202U }, |
| { PPC::S3, 1203U }, |
| { PPC::S4, 1204U }, |
| { PPC::S5, 1205U }, |
| { PPC::S6, 1206U }, |
| { PPC::S7, 1207U }, |
| { PPC::S8, 1208U }, |
| { PPC::S9, 1209U }, |
| { PPC::S10, 1210U }, |
| { PPC::S11, 1211U }, |
| { PPC::S12, 1212U }, |
| { PPC::S13, 1213U }, |
| { PPC::S14, 1214U }, |
| { PPC::S15, 1215U }, |
| { PPC::S16, 1216U }, |
| { PPC::S17, 1217U }, |
| { PPC::S18, 1218U }, |
| { PPC::S19, 1219U }, |
| { PPC::S20, 1220U }, |
| { PPC::S21, 1221U }, |
| { PPC::S22, 1222U }, |
| { PPC::S23, 1223U }, |
| { PPC::S24, 1224U }, |
| { PPC::S25, 1225U }, |
| { PPC::S26, 1226U }, |
| { PPC::S27, 1227U }, |
| { PPC::S28, 1228U }, |
| { PPC::S29, 1229U }, |
| { PPC::S30, 1230U }, |
| { PPC::S31, 1231U }, |
| { PPC::V0, 77U }, |
| { PPC::V1, 78U }, |
| { PPC::V2, 79U }, |
| { PPC::V3, 80U }, |
| { PPC::V4, 81U }, |
| { PPC::V5, 82U }, |
| { PPC::V6, 83U }, |
| { PPC::V7, 84U }, |
| { PPC::V8, 85U }, |
| { PPC::V9, 86U }, |
| { PPC::V10, 87U }, |
| { PPC::V11, 88U }, |
| { PPC::V12, 89U }, |
| { PPC::V13, 90U }, |
| { PPC::V14, 91U }, |
| { PPC::V15, 92U }, |
| { PPC::V16, 93U }, |
| { PPC::V17, 94U }, |
| { PPC::V18, 95U }, |
| { PPC::V19, 96U }, |
| { PPC::V20, 97U }, |
| { PPC::V21, 98U }, |
| { PPC::V22, 99U }, |
| { PPC::V23, 100U }, |
| { PPC::V24, 101U }, |
| { PPC::V25, 102U }, |
| { PPC::V26, 103U }, |
| { PPC::V27, 104U }, |
| { PPC::V28, 105U }, |
| { PPC::V29, 106U }, |
| { PPC::V30, 107U }, |
| { PPC::V31, 108U }, |
| { PPC::VF0, 77U }, |
| { PPC::VF1, 78U }, |
| { PPC::VF2, 79U }, |
| { PPC::VF3, 80U }, |
| { PPC::VF4, 81U }, |
| { PPC::VF5, 82U }, |
| { PPC::VF6, 83U }, |
| { PPC::VF7, 84U }, |
| { PPC::VF8, 85U }, |
| { PPC::VF9, 86U }, |
| { PPC::VF10, 87U }, |
| { PPC::VF11, 88U }, |
| { PPC::VF12, 89U }, |
| { PPC::VF13, 90U }, |
| { PPC::VF14, 91U }, |
| { PPC::VF15, 92U }, |
| { PPC::VF16, 93U }, |
| { PPC::VF17, 94U }, |
| { PPC::VF18, 95U }, |
| { PPC::VF19, 96U }, |
| { PPC::VF20, 97U }, |
| { PPC::VF21, 98U }, |
| { PPC::VF22, 99U }, |
| { PPC::VF23, 100U }, |
| { PPC::VF24, 101U }, |
| { PPC::VF25, 102U }, |
| { PPC::VF26, 103U }, |
| { PPC::VF27, 104U }, |
| { PPC::VF28, 105U }, |
| { PPC::VF29, 106U }, |
| { PPC::VF30, 107U }, |
| { PPC::VF31, 108U }, |
| { PPC::VSL0, 32U }, |
| { PPC::VSL1, 33U }, |
| { PPC::VSL2, 34U }, |
| { PPC::VSL3, 35U }, |
| { PPC::VSL4, 36U }, |
| { PPC::VSL5, 37U }, |
| { PPC::VSL6, 38U }, |
| { PPC::VSL7, 39U }, |
| { PPC::VSL8, 40U }, |
| { PPC::VSL9, 41U }, |
| { PPC::VSL10, 42U }, |
| { PPC::VSL11, 43U }, |
| { PPC::VSL12, 44U }, |
| { PPC::VSL13, 45U }, |
| { PPC::VSL14, 46U }, |
| { PPC::VSL15, 47U }, |
| { PPC::VSL16, 48U }, |
| { PPC::VSL17, 49U }, |
| { PPC::VSL18, 50U }, |
| { PPC::VSL19, 51U }, |
| { PPC::VSL20, 52U }, |
| { PPC::VSL21, 53U }, |
| { PPC::VSL22, 54U }, |
| { PPC::VSL23, 55U }, |
| { PPC::VSL24, 56U }, |
| { PPC::VSL25, 57U }, |
| { PPC::VSL26, 58U }, |
| { PPC::VSL27, 59U }, |
| { PPC::VSL28, 60U }, |
| { PPC::VSL29, 61U }, |
| { PPC::VSL30, 62U }, |
| { PPC::VSL31, 63U }, |
| { PPC::X0, 0U }, |
| { PPC::X1, 1U }, |
| { PPC::X2, 2U }, |
| { PPC::X3, 3U }, |
| { PPC::X4, 4U }, |
| { PPC::X5, 5U }, |
| { PPC::X6, 6U }, |
| { PPC::X7, 7U }, |
| { PPC::X8, 8U }, |
| { PPC::X9, 9U }, |
| { PPC::X10, 10U }, |
| { PPC::X11, 11U }, |
| { PPC::X12, 12U }, |
| { PPC::X13, 13U }, |
| { PPC::X14, 14U }, |
| { PPC::X15, 15U }, |
| { PPC::X16, 16U }, |
| { PPC::X17, 17U }, |
| { PPC::X18, 18U }, |
| { PPC::X19, 19U }, |
| { PPC::X20, 20U }, |
| { PPC::X21, 21U }, |
| { PPC::X22, 22U }, |
| { PPC::X23, 23U }, |
| { PPC::X24, 24U }, |
| { PPC::X25, 25U }, |
| { PPC::X26, 26U }, |
| { PPC::X27, 27U }, |
| { PPC::X28, 28U }, |
| { PPC::X29, 29U }, |
| { PPC::X30, 30U }, |
| { PPC::X31, 31U }, |
| { PPC::ZERO8, 0U }, |
| }; |
| extern const unsigned PPCEHFlavour0L2DwarfSize = array_lengthof(PPCEHFlavour0L2Dwarf); |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1L2Dwarf[] = { |
| { PPC::CTR, 66U }, |
| { PPC::LR, 65U }, |
| { PPC::SPEFSCR, 112U }, |
| { PPC::ZERO, 0U }, |
| { PPC::CR0, 68U }, |
| { PPC::CR1, 69U }, |
| { PPC::CR2, 70U }, |
| { PPC::CR3, 71U }, |
| { PPC::CR4, 72U }, |
| { PPC::CR5, 73U }, |
| { PPC::CR6, 74U }, |
| { PPC::CR7, 75U }, |
| { PPC::CTR8, -2U }, |
| { PPC::F0, 32U }, |
| { PPC::F1, 33U }, |
| { PPC::F2, 34U }, |
| { PPC::F3, 35U }, |
| { PPC::F4, 36U }, |
| { PPC::F5, 37U }, |
| { PPC::F6, 38U }, |
| { PPC::F7, 39U }, |
| { PPC::F8, 40U }, |
| { PPC::F9, 41U }, |
| { PPC::F10, 42U }, |
| { PPC::F11, 43U }, |
| { PPC::F12, 44U }, |
| { PPC::F13, 45U }, |
| { PPC::F14, 46U }, |
| { PPC::F15, 47U }, |
| { PPC::F16, 48U }, |
| { PPC::F17, 49U }, |
| { PPC::F18, 50U }, |
| { PPC::F19, 51U }, |
| { PPC::F20, 52U }, |
| { PPC::F21, 53U }, |
| { PPC::F22, 54U }, |
| { PPC::F23, 55U }, |
| { PPC::F24, 56U }, |
| { PPC::F25, 57U }, |
| { PPC::F26, 58U }, |
| { PPC::F27, 59U }, |
| { PPC::F28, 60U }, |
| { PPC::F29, 61U }, |
| { PPC::F30, 62U }, |
| { PPC::F31, 63U }, |
| { PPC::LR8, -2U }, |
| { PPC::QF0, 32U }, |
| { PPC::QF1, 33U }, |
| { PPC::QF2, 34U }, |
| { PPC::QF3, 35U }, |
| { PPC::QF4, 36U }, |
| { PPC::QF5, 37U }, |
| { PPC::QF6, 38U }, |
| { PPC::QF7, 39U }, |
| { PPC::QF8, 40U }, |
| { PPC::QF9, 41U }, |
| { PPC::QF10, 42U }, |
| { PPC::QF11, 43U }, |
| { PPC::QF12, 44U }, |
| { PPC::QF13, 45U }, |
| { PPC::QF14, 46U }, |
| { PPC::QF15, 47U }, |
| { PPC::QF16, 48U }, |
| { PPC::QF17, 49U }, |
| { PPC::QF18, 50U }, |
| { PPC::QF19, 51U }, |
| { PPC::QF20, 52U }, |
| { PPC::QF21, 53U }, |
| { PPC::QF22, 54U }, |
| { PPC::QF23, 55U }, |
| { PPC::QF24, 56U }, |
| { PPC::QF25, 57U }, |
| { PPC::QF26, 58U }, |
| { PPC::QF27, 59U }, |
| { PPC::QF28, 60U }, |
| { PPC::QF29, 61U }, |
| { PPC::QF30, 62U }, |
| { PPC::QF31, 63U }, |
| { PPC::R0, 0U }, |
| { PPC::R1, 1U }, |
| { PPC::R2, 2U }, |
| { PPC::R3, 3U }, |
| { PPC::R4, 4U }, |
| { PPC::R5, 5U }, |
| { PPC::R6, 6U }, |
| { PPC::R7, 7U }, |
| { PPC::R8, 8U }, |
| { PPC::R9, 9U }, |
| { PPC::R10, 10U }, |
| { PPC::R11, 11U }, |
| { PPC::R12, 12U }, |
| { PPC::R13, 13U }, |
| { PPC::R14, 14U }, |
| { PPC::R15, 15U }, |
| { PPC::R16, 16U }, |
| { PPC::R17, 17U }, |
| { PPC::R18, 18U }, |
| { PPC::R19, 19U }, |
| { PPC::R20, 20U }, |
| { PPC::R21, 21U }, |
| { PPC::R22, 22U }, |
| { PPC::R23, 23U }, |
| { PPC::R24, 24U }, |
| { PPC::R25, 25U }, |
| { PPC::R26, 26U }, |
| { PPC::R27, 27U }, |
| { PPC::R28, 28U }, |
| { PPC::R29, 29U }, |
| { PPC::R30, 30U }, |
| { PPC::R31, 31U }, |
| { PPC::S0, 1200U }, |
| { PPC::S1, 1201U }, |
| { PPC::S2, 1202U }, |
| { PPC::S3, 1203U }, |
| { PPC::S4, 1204U }, |
| { PPC::S5, 1205U }, |
| { PPC::S6, 1206U }, |
| { PPC::S7, 1207U }, |
| { PPC::S8, 1208U }, |
| { PPC::S9, 1209U }, |
| { PPC::S10, 1210U }, |
| { PPC::S11, 1211U }, |
| { PPC::S12, 1212U }, |
| { PPC::S13, 1213U }, |
| { PPC::S14, 1214U }, |
| { PPC::S15, 1215U }, |
| { PPC::S16, 1216U }, |
| { PPC::S17, 1217U }, |
| { PPC::S18, 1218U }, |
| { PPC::S19, 1219U }, |
| { PPC::S20, 1220U }, |
| { PPC::S21, 1221U }, |
| { PPC::S22, 1222U }, |
| { PPC::S23, 1223U }, |
| { PPC::S24, 1224U }, |
| { PPC::S25, 1225U }, |
| { PPC::S26, 1226U }, |
| { PPC::S27, 1227U }, |
| { PPC::S28, 1228U }, |
| { PPC::S29, 1229U }, |
| { PPC::S30, 1230U }, |
| { PPC::S31, 1231U }, |
| { PPC::V0, 77U }, |
| { PPC::V1, 78U }, |
| { PPC::V2, 79U }, |
| { PPC::V3, 80U }, |
| { PPC::V4, 81U }, |
| { PPC::V5, 82U }, |
| { PPC::V6, 83U }, |
| { PPC::V7, 84U }, |
| { PPC::V8, 85U }, |
| { PPC::V9, 86U }, |
| { PPC::V10, 87U }, |
| { PPC::V11, 88U }, |
| { PPC::V12, 89U }, |
| { PPC::V13, 90U }, |
| { PPC::V14, 91U }, |
| { PPC::V15, 92U }, |
| { PPC::V16, 93U }, |
| { PPC::V17, 94U }, |
| { PPC::V18, 95U }, |
| { PPC::V19, 96U }, |
| { PPC::V20, 97U }, |
| { PPC::V21, 98U }, |
| { PPC::V22, 99U }, |
| { PPC::V23, 100U }, |
| { PPC::V24, 101U }, |
| { PPC::V25, 102U }, |
| { PPC::V26, 103U }, |
| { PPC::V27, 104U }, |
| { PPC::V28, 105U }, |
| { PPC::V29, 106U }, |
| { PPC::V30, 107U }, |
| { PPC::V31, 108U }, |
| { PPC::VF0, 77U }, |
| { PPC::VF1, 78U }, |
| { PPC::VF2, 79U }, |
| { PPC::VF3, 80U }, |
| { PPC::VF4, 81U }, |
| { PPC::VF5, 82U }, |
| { PPC::VF6, 83U }, |
| { PPC::VF7, 84U }, |
| { PPC::VF8, 85U }, |
| { PPC::VF9, 86U }, |
| { PPC::VF10, 87U }, |
| { PPC::VF11, 88U }, |
| { PPC::VF12, 89U }, |
| { PPC::VF13, 90U }, |
| { PPC::VF14, 91U }, |
| { PPC::VF15, 92U }, |
| { PPC::VF16, 93U }, |
| { PPC::VF17, 94U }, |
| { PPC::VF18, 95U }, |
| { PPC::VF19, 96U }, |
| { PPC::VF20, 97U }, |
| { PPC::VF21, 98U }, |
| { PPC::VF22, 99U }, |
| { PPC::VF23, 100U }, |
| { PPC::VF24, 101U }, |
| { PPC::VF25, 102U }, |
| { PPC::VF26, 103U }, |
| { PPC::VF27, 104U }, |
| { PPC::VF28, 105U }, |
| { PPC::VF29, 106U }, |
| { PPC::VF30, 107U }, |
| { PPC::VF31, 108U }, |
| { PPC::VSL0, 32U }, |
| { PPC::VSL1, 33U }, |
| { PPC::VSL2, 34U }, |
| { PPC::VSL3, 35U }, |
| { PPC::VSL4, 36U }, |
| { PPC::VSL5, 37U }, |
| { PPC::VSL6, 38U }, |
| { PPC::VSL7, 39U }, |
| { PPC::VSL8, 40U }, |
| { PPC::VSL9, 41U }, |
| { PPC::VSL10, 42U }, |
| { PPC::VSL11, 43U }, |
| { PPC::VSL12, 44U }, |
| { PPC::VSL13, 45U }, |
| { PPC::VSL14, 46U }, |
| { PPC::VSL15, 47U }, |
| { PPC::VSL16, 48U }, |
| { PPC::VSL17, 49U }, |
| { PPC::VSL18, 50U }, |
| { PPC::VSL19, 51U }, |
| { PPC::VSL20, 52U }, |
| { PPC::VSL21, 53U }, |
| { PPC::VSL22, 54U }, |
| { PPC::VSL23, 55U }, |
| { PPC::VSL24, 56U }, |
| { PPC::VSL25, 57U }, |
| { PPC::VSL26, 58U }, |
| { PPC::VSL27, 59U }, |
| { PPC::VSL28, 60U }, |
| { PPC::VSL29, 61U }, |
| { PPC::VSL30, 62U }, |
| { PPC::VSL31, 63U }, |
| { PPC::X0, -2U }, |
| { PPC::X1, -2U }, |
| { PPC::X2, -2U }, |
| { PPC::X3, -2U }, |
| { PPC::X4, -2U }, |
| { PPC::X5, -2U }, |
| { PPC::X6, -2U }, |
| { PPC::X7, -2U }, |
| { PPC::X8, -2U }, |
| { PPC::X9, -2U }, |
| { PPC::X10, -2U }, |
| { PPC::X11, -2U }, |
| { PPC::X12, -2U }, |
| { PPC::X13, -2U }, |
| { PPC::X14, -2U }, |
| { PPC::X15, -2U }, |
| { PPC::X16, -2U }, |
| { PPC::X17, -2U }, |
| { PPC::X18, -2U }, |
| { PPC::X19, -2U }, |
| { PPC::X20, -2U }, |
| { PPC::X21, -2U }, |
| { PPC::X22, -2U }, |
| { PPC::X23, -2U }, |
| { PPC::X24, -2U }, |
| { PPC::X25, -2U }, |
| { PPC::X26, -2U }, |
| { PPC::X27, -2U }, |
| { PPC::X28, -2U }, |
| { PPC::X29, -2U }, |
| { PPC::X30, -2U }, |
| { PPC::X31, -2U }, |
| { PPC::ZERO8, -2U }, |
| }; |
| extern const unsigned PPCEHFlavour1L2DwarfSize = array_lengthof(PPCEHFlavour1L2Dwarf); |
| |
| extern const uint16_t PPCRegEncodingTable[] = { |
| 0, |
| 0, |
| 1, |
| 9, |
| 0, |
| 8, |
| 0, |
| 512, |
| 256, |
| 1, |
| 0, |
| 0, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 9, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 28, |
| 29, |
| 30, |
| 31, |
| 0, |
| 8, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 28, |
| 29, |
| 30, |
| 31, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 28, |
| 29, |
| 30, |
| 31, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 28, |
| 29, |
| 30, |
| 31, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 28, |
| 29, |
| 30, |
| 31, |
| 32, |
| 33, |
| 34, |
| 35, |
| 36, |
| 37, |
| 38, |
| 39, |
| 40, |
| 41, |
| 42, |
| 43, |
| 44, |
| 45, |
| 46, |
| 47, |
| 48, |
| 49, |
| 50, |
| 51, |
| 52, |
| 53, |
| 54, |
| 55, |
| 56, |
| 57, |
| 58, |
| 59, |
| 60, |
| 61, |
| 62, |
| 63, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 28, |
| 29, |
| 30, |
| 31, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 28, |
| 29, |
| 30, |
| 31, |
| 0, |
| 2, |
| 6, |
| 10, |
| 14, |
| 18, |
| 22, |
| 26, |
| 30, |
| 1, |
| 5, |
| 9, |
| 13, |
| 17, |
| 21, |
| 25, |
| 29, |
| 0, |
| 4, |
| 8, |
| 12, |
| 16, |
| 20, |
| 24, |
| 28, |
| 3, |
| 7, |
| 11, |
| 15, |
| 19, |
| 23, |
| 27, |
| 31, |
| }; |
| static inline void InitPPCMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { |
| RI->InitMCRegisterInfo(PPCRegDesc, 344, RA, PC, PPCMCRegisterClasses, 36, PPCRegUnitRoots, 171, PPCRegDiffLists, PPCLaneMaskLists, PPCRegStrings, PPCRegClassStrings, PPCSubRegIdxLists, 7, |
| PPCSubRegIdxRanges, PPCRegEncodingTable); |
| |
| switch (DwarfFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| RI->mapDwarfRegsToLLVMRegs(PPCDwarfFlavour0Dwarf2L, PPCDwarfFlavour0Dwarf2LSize, false); |
| break; |
| case 1: |
| RI->mapDwarfRegsToLLVMRegs(PPCDwarfFlavour1Dwarf2L, PPCDwarfFlavour1Dwarf2LSize, false); |
| break; |
| } |
| switch (EHFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| RI->mapDwarfRegsToLLVMRegs(PPCEHFlavour0Dwarf2L, PPCEHFlavour0Dwarf2LSize, true); |
| break; |
| case 1: |
| RI->mapDwarfRegsToLLVMRegs(PPCEHFlavour1Dwarf2L, PPCEHFlavour1Dwarf2LSize, true); |
| break; |
| } |
| switch (DwarfFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| RI->mapLLVMRegsToDwarfRegs(PPCDwarfFlavour0L2Dwarf, PPCDwarfFlavour0L2DwarfSize, false); |
| break; |
| case 1: |
| RI->mapLLVMRegsToDwarfRegs(PPCDwarfFlavour1L2Dwarf, PPCDwarfFlavour1L2DwarfSize, false); |
| break; |
| } |
| switch (EHFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| RI->mapLLVMRegsToDwarfRegs(PPCEHFlavour0L2Dwarf, PPCEHFlavour0L2DwarfSize, true); |
| break; |
| case 1: |
| RI->mapLLVMRegsToDwarfRegs(PPCEHFlavour1L2Dwarf, PPCEHFlavour1L2DwarfSize, true); |
| break; |
| } |
| } |
| |
| } // end namespace llvm |
| |
| #endif // GET_REGINFO_MC_DESC |
| |
| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Register Information Header Fragment *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| |
| #ifdef GET_REGINFO_HEADER |
| #undef GET_REGINFO_HEADER |
| |
| #include "llvm/CodeGen/TargetRegisterInfo.h" |
| |
| namespace llvm { |
| |
| class PPCFrameLowering; |
| |
| struct PPCGenRegisterInfo : public TargetRegisterInfo { |
| explicit PPCGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0, |
| unsigned PC = 0, unsigned HwMode = 0); |
| unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override; |
| LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; |
| LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; |
| const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override; |
| const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override; |
| unsigned getRegUnitWeight(unsigned RegUnit) const override; |
| unsigned getNumRegPressureSets() const override; |
| const char *getRegPressureSetName(unsigned Idx) const override; |
| unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override; |
| const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override; |
| const int *getRegUnitPressureSets(unsigned RegUnit) const override; |
| ArrayRef<const char *> getRegMaskNames() const override; |
| ArrayRef<const uint32_t *> getRegMasks() const override; |
| /// Devirtualized TargetFrameLowering. |
| static const PPCFrameLowering *getFrameLowering( |
| const MachineFunction &MF); |
| }; |
| |
| namespace PPC { // Register classes |
| extern const TargetRegisterClass VSSRCRegClass; |
| extern const TargetRegisterClass GPRCRegClass; |
| extern const TargetRegisterClass GPRC_NOR0RegClass; |
| extern const TargetRegisterClass SPE4RCRegClass; |
| extern const TargetRegisterClass GPRC_and_GPRC_NOR0RegClass; |
| extern const TargetRegisterClass CRBITRCRegClass; |
| extern const TargetRegisterClass F4RCRegClass; |
| extern const TargetRegisterClass CRRCRegClass; |
| extern const TargetRegisterClass CARRYRCRegClass; |
| extern const TargetRegisterClass CRRC0RegClass; |
| extern const TargetRegisterClass CTRRCRegClass; |
| extern const TargetRegisterClass VRSAVERCRegClass; |
| extern const TargetRegisterClass SPILLTOVSRRCRegClass; |
| extern const TargetRegisterClass VSFRCRegClass; |
| extern const TargetRegisterClass G8RCRegClass; |
| extern const TargetRegisterClass G8RC_NOX0RegClass; |
| extern const TargetRegisterClass SPILLTOVSRRC_and_VSFRCRegClass; |
| extern const TargetRegisterClass G8RC_and_G8RC_NOX0RegClass; |
| extern const TargetRegisterClass F8RCRegClass; |
| extern const TargetRegisterClass SPERCRegClass; |
| extern const TargetRegisterClass VFRCRegClass; |
| extern const TargetRegisterClass SPERC_with_sub_32_in_GPRC_NOR0RegClass; |
| extern const TargetRegisterClass SPILLTOVSRRC_and_VFRCRegClass; |
| extern const TargetRegisterClass SPILLTOVSRRC_and_F4RCRegClass; |
| extern const TargetRegisterClass CTRRC8RegClass; |
| extern const TargetRegisterClass VSRCRegClass; |
| extern const TargetRegisterClass VSRC_with_sub_64_in_SPILLTOVSRRCRegClass; |
| extern const TargetRegisterClass QSRCRegClass; |
| extern const TargetRegisterClass VRRCRegClass; |
| extern const TargetRegisterClass VSLRCRegClass; |
| extern const TargetRegisterClass VRRC_with_sub_64_in_SPILLTOVSRRCRegClass; |
| extern const TargetRegisterClass QSRC_with_sub_64_in_SPILLTOVSRRCRegClass; |
| extern const TargetRegisterClass VSLRC_with_sub_64_in_SPILLTOVSRRCRegClass; |
| extern const TargetRegisterClass QBRCRegClass; |
| extern const TargetRegisterClass QFRCRegClass; |
| extern const TargetRegisterClass QBRC_with_sub_64_in_SPILLTOVSRRCRegClass; |
| } // end namespace PPC |
| |
| } // end namespace llvm |
| |
| #endif // GET_REGINFO_HEADER |
| |
| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Target Register and Register Classes Information *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| |
| #ifdef GET_REGINFO_TARGET_DESC |
| #undef GET_REGINFO_TARGET_DESC |
| |
| namespace llvm { |
| |
| extern const MCRegisterClass PPCMCRegisterClasses[]; |
| |
| static const MVT::SimpleValueType VTLists[] = { |
| /* 0 */ MVT::i1, MVT::Other, |
| /* 2 */ MVT::i32, MVT::Other, |
| /* 4 */ MVT::i64, MVT::Other, |
| /* 6 */ MVT::f32, MVT::Other, |
| /* 8 */ MVT::i64, MVT::f64, MVT::Other, |
| /* 11 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v1i128, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::Other, |
| /* 20 */ MVT::v4i1, MVT::Other, |
| /* 22 */ MVT::v4i32, MVT::v4f32, MVT::v2f64, MVT::v2i64, MVT::Other, |
| /* 27 */ MVT::v4f32, MVT::Other, |
| /* 29 */ MVT::v4f64, MVT::Other, |
| }; |
| |
| static const char *const SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_eq", "sub_gt", "sub_lt", "sub_un", "" }; |
| |
| |
| static const LaneBitmask SubRegIndexLaneMaskTable[] = { |
| LaneBitmask::getAll(), |
| LaneBitmask(0x00000001), // sub_32 |
| LaneBitmask(0x00000002), // sub_64 |
| LaneBitmask(0x00000004), // sub_eq |
| LaneBitmask(0x00000008), // sub_gt |
| LaneBitmask(0x00000010), // sub_lt |
| LaneBitmask(0x00000020), // sub_un |
| }; |
| |
| |
| |
| static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = { |
| // Mode = 0 (Default) |
| { 32, 32, 32, VTLists+6 }, // VSSRC |
| { 32, 32, 32, VTLists+2 }, // GPRC |
| { 32, 32, 32, VTLists+2 }, // GPRC_NOR0 |
| { 32, 32, 32, VTLists+6 }, // SPE4RC |
| { 32, 32, 32, VTLists+6 }, // GPRC_and_GPRC_NOR0 |
| { 32, 32, 32, VTLists+0 }, // CRBITRC |
| { 32, 32, 32, VTLists+6 }, // F4RC |
| { 32, 32, 32, VTLists+2 }, // CRRC |
| { 32, 32, 32, VTLists+2 }, // CARRYRC |
| { 32, 32, 32, VTLists+2 }, // CRRC0 |
| { 32, 32, 32, VTLists+2 }, // CTRRC |
| { 32, 32, 32, VTLists+2 }, // VRSAVERC |
| { 64, 64, 64, VTLists+8 }, // SPILLTOVSRRC |
| { 64, 64, 64, VTLists+9 }, // VSFRC |
| { 64, 64, 64, VTLists+4 }, // G8RC |
| { 64, 64, 64, VTLists+4 }, // G8RC_NOX0 |
| { 64, 64, 64, VTLists+9 }, // SPILLTOVSRRC_and_VSFRC |
| { 64, 64, 64, VTLists+4 }, // G8RC_and_G8RC_NOX0 |
| { 64, 64, 64, VTLists+9 }, // F8RC |
| { 64, 64, 64, VTLists+9 }, // SPERC |
| { 64, 64, 64, VTLists+9 }, // VFRC |
| { 64, 64, 64, VTLists+9 }, // SPERC_with_sub_32_in_GPRC_NOR0 |
| { 64, 64, 64, VTLists+9 }, // SPILLTOVSRRC_and_VFRC |
| { 64, 64, 64, VTLists+9 }, // SPILLTOVSRRC_and_F4RC |
| { 64, 64, 64, VTLists+4 }, // CTRRC8 |
| { 128, 128, 128, VTLists+22 }, // VSRC |
| { 128, 128, 128, VTLists+22 }, // VSRC_with_sub_64_in_SPILLTOVSRRC |
| { 128, 128, 128, VTLists+27 }, // QSRC |
| { 128, 128, 128, VTLists+11 }, // VRRC |
| { 128, 128, 128, VTLists+22 }, // VSLRC |
| { 128, 128, 128, VTLists+11 }, // VRRC_with_sub_64_in_SPILLTOVSRRC |
| { 128, 128, 128, VTLists+27 }, // QSRC_with_sub_64_in_SPILLTOVSRRC |
| { 128, 128, 128, VTLists+22 }, // VSLRC_with_sub_64_in_SPILLTOVSRRC |
| { 256, 256, 256, VTLists+20 }, // QBRC |
| { 256, 256, 256, VTLists+29 }, // QFRC |
| { 256, 256, 256, VTLists+29 }, // QBRC_with_sub_64_in_SPILLTOVSRRC |
| }; |
| |
| static const TargetRegisterClass *const NullRegClasses[] = { nullptr }; |
| |
| static const uint32_t VSSRCSubClassMask[] = { |
| 0x00d52041, 0x00000000, |
| 0xfe000000, 0x0000000f, // sub_64 |
| }; |
| |
| static const uint32_t GPRCSubClassMask[] = { |
| 0x0000001a, 0x00000000, |
| 0x002a4000, 0x00000000, // sub_32 |
| }; |
| |
| static const uint32_t GPRC_NOR0SubClassMask[] = { |
| 0x00000014, 0x00000000, |
| 0x00228000, 0x00000000, // sub_32 |
| }; |
| |
| static const uint32_t SPE4RCSubClassMask[] = { |
| 0x00000018, 0x00000000, |
| 0x002a4000, 0x00000000, // sub_32 |
| }; |
| |
| static const uint32_t GPRC_and_GPRC_NOR0SubClassMask[] = { |
| 0x00000010, 0x00000000, |
| 0x00220000, 0x00000000, // sub_32 |
| }; |
| |
| static const uint32_t CRBITRCSubClassMask[] = { |
| 0x00000020, 0x00000000, |
| 0x00000280, 0x00000000, // sub_eq |
| 0x00000280, 0x00000000, // sub_gt |
| 0x00000280, 0x00000000, // sub_lt |
| 0x00000280, 0x00000000, // sub_un |
| }; |
| |
| static const uint32_t F4RCSubClassMask[] = { |
| 0x00840040, 0x00000000, |
| 0xa8000000, 0x0000000f, // sub_64 |
| }; |
| |
| static const uint32_t CRRCSubClassMask[] = { |
| 0x00000280, 0x00000000, |
| }; |
| |
| static const uint32_t CARRYRCSubClassMask[] = { |
| 0x00000100, 0x00000000, |
| }; |
| |
| static const uint32_t CRRC0SubClassMask[] = { |
| 0x00000200, 0x00000000, |
| }; |
| |
| static const uint32_t CTRRCSubClassMask[] = { |
| 0x00000400, 0x00000000, |
| }; |
| |
| static const uint32_t VRSAVERCSubClassMask[] = { |
| 0x00000800, 0x00000000, |
| }; |
| |
| static const uint32_t SPILLTOVSRRCSubClassMask[] = { |
| 0x00c35000, 0x00000000, |
| 0xc4000000, 0x00000009, // sub_64 |
| }; |
| |
| static const uint32_t VSFRCSubClassMask[] = { |
| 0x00d52000, 0x00000000, |
| 0xfe000000, 0x0000000f, // sub_64 |
| }; |
| |
| static const uint32_t G8RCSubClassMask[] = { |
| 0x00024000, 0x00000000, |
| }; |
| |
| static const uint32_t G8RC_NOX0SubClassMask[] = { |
| 0x00028000, 0x00000000, |
| }; |
| |
| static const uint32_t SPILLTOVSRRC_and_VSFRCSubClassMask[] = { |
| 0x00c10000, 0x00000000, |
| 0xc4000000, 0x00000009, // sub_64 |
| }; |
| |
| static const uint32_t G8RC_and_G8RC_NOX0SubClassMask[] = { |
| 0x00020000, 0x00000000, |
| }; |
| |
| static const uint32_t F8RCSubClassMask[] = { |
| 0x00840000, 0x00000000, |
| 0xa8000000, 0x0000000f, // sub_64 |
| }; |
| |
| static const uint32_t SPERCSubClassMask[] = { |
| 0x00280000, 0x00000000, |
| }; |
| |
| static const uint32_t VFRCSubClassMask[] = { |
| 0x00500000, 0x00000000, |
| 0x50000000, 0x00000000, // sub_64 |
| }; |
| |
| static const uint32_t SPERC_with_sub_32_in_GPRC_NOR0SubClassMask[] = { |
| 0x00200000, 0x00000000, |
| }; |
| |
| static const uint32_t SPILLTOVSRRC_and_VFRCSubClassMask[] = { |
| 0x00400000, 0x00000000, |
| 0x40000000, 0x00000000, // sub_64 |
| }; |
| |
| static const uint32_t SPILLTOVSRRC_and_F4RCSubClassMask[] = { |
| 0x00800000, 0x00000000, |
| 0x80000000, 0x00000009, // sub_64 |
| }; |
| |
| static const uint32_t CTRRC8SubClassMask[] = { |
| 0x01000000, 0x00000000, |
| }; |
| |
| static const uint32_t VSRCSubClassMask[] = { |
| 0x76000000, 0x00000001, |
| }; |
| |
| static const uint32_t VSRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = { |
| 0x44000000, 0x00000001, |
| }; |
| |
| static const uint32_t QSRCSubClassMask[] = { |
| 0x88000000, 0x0000000e, |
| }; |
| |
| static const uint32_t VRRCSubClassMask[] = { |
| 0x50000000, 0x00000000, |
| }; |
| |
| static const uint32_t VSLRCSubClassMask[] = { |
| 0x20000000, 0x00000001, |
| }; |
| |
| static const uint32_t VRRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = { |
| 0x40000000, 0x00000000, |
| }; |
| |
| static const uint32_t QSRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = { |
| 0x80000000, 0x00000008, |
| }; |
| |
| static const uint32_t VSLRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = { |
| 0x00000000, 0x00000001, |
| }; |
| |
| static const uint32_t QBRCSubClassMask[] = { |
| 0x00000000, 0x0000000e, |
| }; |
| |
| static const uint32_t QFRCSubClassMask[] = { |
| 0x00000000, 0x0000000e, |
| }; |
| |
| static const uint32_t QBRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = { |
| 0x00000000, 0x00000008, |
| }; |
| |
| static const uint16_t SuperRegIdxSeqs[] = { |
| /* 0 */ 1, 0, |
| /* 2 */ 2, 0, |
| /* 4 */ 3, 4, 5, 6, 0, |
| }; |
| |
| static const TargetRegisterClass *const SPE4RCSuperclasses[] = { |
| &PPC::GPRCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPRC_and_GPRC_NOR0Superclasses[] = { |
| &PPC::GPRCRegClass, |
| &PPC::GPRC_NOR0RegClass, |
| &PPC::SPE4RCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const F4RCSuperclasses[] = { |
| &PPC::VSSRCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const CRRC0Superclasses[] = { |
| &PPC::CRRCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const VSFRCSuperclasses[] = { |
| &PPC::VSSRCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const G8RCSuperclasses[] = { |
| &PPC::SPILLTOVSRRCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const SPILLTOVSRRC_and_VSFRCSuperclasses[] = { |
| &PPC::VSSRCRegClass, |
| &PPC::SPILLTOVSRRCRegClass, |
| &PPC::VSFRCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const G8RC_and_G8RC_NOX0Superclasses[] = { |
| &PPC::SPILLTOVSRRCRegClass, |
| &PPC::G8RCRegClass, |
| &PPC::G8RC_NOX0RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const F8RCSuperclasses[] = { |
| &PPC::VSSRCRegClass, |
| &PPC::F4RCRegClass, |
| &PPC::VSFRCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const VFRCSuperclasses[] = { |
| &PPC::VSSRCRegClass, |
| &PPC::VSFRCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const SPERC_with_sub_32_in_GPRC_NOR0Superclasses[] = { |
| &PPC::SPERCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const SPILLTOVSRRC_and_VFRCSuperclasses[] = { |
| &PPC::VSSRCRegClass, |
| &PPC::SPILLTOVSRRCRegClass, |
| &PPC::VSFRCRegClass, |
| &PPC::SPILLTOVSRRC_and_VSFRCRegClass, |
| &PPC::VFRCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const SPILLTOVSRRC_and_F4RCSuperclasses[] = { |
| &PPC::VSSRCRegClass, |
| &PPC::F4RCRegClass, |
| &PPC::SPILLTOVSRRCRegClass, |
| &PPC::VSFRCRegClass, |
| &PPC::SPILLTOVSRRC_and_VSFRCRegClass, |
| &PPC::F8RCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const VSRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = { |
| &PPC::VSRCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const VRRCSuperclasses[] = { |
| &PPC::VSRCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const VSLRCSuperclasses[] = { |
| &PPC::VSRCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const VRRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = { |
| &PPC::VSRCRegClass, |
| &PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClass, |
| &PPC::VRRCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const QSRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = { |
| &PPC::QSRCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const VSLRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = { |
| &PPC::VSRCRegClass, |
| &PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClass, |
| &PPC::VSLRCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const QBRCSuperclasses[] = { |
| &PPC::QSRCRegClass, |
| &PPC::QFRCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const QFRCSuperclasses[] = { |
| &PPC::QSRCRegClass, |
| &PPC::QBRCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const QBRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = { |
| &PPC::QSRCRegClass, |
| &PPC::QSRC_with_sub_64_in_SPILLTOVSRRCRegClass, |
| &PPC::QBRCRegClass, |
| &PPC::QFRCRegClass, |
| nullptr |
| }; |
| |
| |
| static inline unsigned GPRCAltOrderSelect(const MachineFunction &MF) { |
| const PPCSubtarget &S = MF.getSubtarget<PPCSubtarget>(); |
| return S.isPPC64() && S.isSVR4ABI(); |
| } |
| |
| static ArrayRef<MCPhysReg> GPRCGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R0, PPC::R1, PPC::FP, PPC::BP, PPC::R2 }; |
| const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRCRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = GPRCAltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned GPRC_NOR0AltOrderSelect(const MachineFunction &MF) { |
| const PPCSubtarget &S = MF.getSubtarget<PPCSubtarget>(); |
| return S.isPPC64() && S.isSVR4ABI(); |
| } |
| |
| static ArrayRef<MCPhysReg> GPRC_NOR0GetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, PPC::ZERO, PPC::R2 }; |
| const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRC_NOR0RegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = GPRC_NOR0AltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned G8RCAltOrderSelect(const MachineFunction &MF) { |
| const PPCSubtarget &S = MF.getSubtarget<PPCSubtarget>(); |
| return S.isPPC64() && S.isSVR4ABI(); |
| } |
| |
| static ArrayRef<MCPhysReg> G8RCGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8, PPC::X2 }; |
| const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RCRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = G8RCAltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned G8RC_NOX0AltOrderSelect(const MachineFunction &MF) { |
| const PPCSubtarget &S = MF.getSubtarget<PPCSubtarget>(); |
| return S.isPPC64() && S.isSVR4ABI(); |
| } |
| |
| static ArrayRef<MCPhysReg> G8RC_NOX0GetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::ZERO8, PPC::X2 }; |
| const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RC_NOX0RegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = G8RC_NOX0AltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned G8RC_and_G8RC_NOX0AltOrderSelect(const MachineFunction &MF) { |
| const PPCSubtarget &S = MF.getSubtarget<PPCSubtarget>(); |
| return S.isPPC64() && S.isSVR4ABI(); |
| } |
| |
| static ArrayRef<MCPhysReg> G8RC_and_G8RC_NOX0GetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::X2 }; |
| const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RC_and_G8RC_NOX0RegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = G8RC_and_G8RC_NOX0AltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| namespace PPC { // Register class instances |
| extern const TargetRegisterClass VSSRCRegClass = { |
| &PPCMCRegisterClasses[VSSRCRegClassID], |
| VSSRCSubClassMask, |
| SuperRegIdxSeqs + 2, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRCRegClass = { |
| &PPCMCRegisterClasses[GPRCRegClassID], |
| GPRCSubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| GPRCGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass GPRC_NOR0RegClass = { |
| &PPCMCRegisterClasses[GPRC_NOR0RegClassID], |
| GPRC_NOR0SubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| GPRC_NOR0GetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass SPE4RCRegClass = { |
| &PPCMCRegisterClasses[SPE4RCRegClassID], |
| SPE4RCSubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| SPE4RCSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRC_and_GPRC_NOR0RegClass = { |
| &PPCMCRegisterClasses[GPRC_and_GPRC_NOR0RegClassID], |
| GPRC_and_GPRC_NOR0SubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPRC_and_GPRC_NOR0Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass CRBITRCRegClass = { |
| &PPCMCRegisterClasses[CRBITRCRegClassID], |
| CRBITRCSubClassMask, |
| SuperRegIdxSeqs + 4, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass F4RCRegClass = { |
| &PPCMCRegisterClasses[F4RCRegClassID], |
| F4RCSubClassMask, |
| SuperRegIdxSeqs + 2, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| F4RCSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass CRRCRegClass = { |
| &PPCMCRegisterClasses[CRRCRegClassID], |
| CRRCSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x0000003C), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass CARRYRCRegClass = { |
| &PPCMCRegisterClasses[CARRYRCRegClassID], |
| CARRYRCSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass CRRC0RegClass = { |
| &PPCMCRegisterClasses[CRRC0RegClassID], |
| CRRC0SubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x0000003C), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| CRRC0Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass CTRRCRegClass = { |
| &PPCMCRegisterClasses[CTRRCRegClassID], |
| CTRRCSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass VRSAVERCRegClass = { |
| &PPCMCRegisterClasses[VRSAVERCRegClassID], |
| VRSAVERCSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass SPILLTOVSRRCRegClass = { |
| &PPCMCRegisterClasses[SPILLTOVSRRCRegClassID], |
| SPILLTOVSRRCSubClassMask, |
| SuperRegIdxSeqs + 2, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass VSFRCRegClass = { |
| &PPCMCRegisterClasses[VSFRCRegClassID], |
| VSFRCSubClassMask, |
| SuperRegIdxSeqs + 2, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| VSFRCSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass G8RCRegClass = { |
| &PPCMCRegisterClasses[G8RCRegClassID], |
| G8RCSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| G8RCSuperclasses, |
| G8RCGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass G8RC_NOX0RegClass = { |
| &PPCMCRegisterClasses[G8RC_NOX0RegClassID], |
| G8RC_NOX0SubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| G8RC_NOX0GetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass SPILLTOVSRRC_and_VSFRCRegClass = { |
| &PPCMCRegisterClasses[SPILLTOVSRRC_and_VSFRCRegClassID], |
| SPILLTOVSRRC_and_VSFRCSubClassMask, |
| SuperRegIdxSeqs + 2, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| SPILLTOVSRRC_and_VSFRCSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass G8RC_and_G8RC_NOX0RegClass = { |
| &PPCMCRegisterClasses[G8RC_and_G8RC_NOX0RegClassID], |
| G8RC_and_G8RC_NOX0SubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| G8RC_and_G8RC_NOX0Superclasses, |
| G8RC_and_G8RC_NOX0GetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass F8RCRegClass = { |
| &PPCMCRegisterClasses[F8RCRegClassID], |
| F8RCSubClassMask, |
| SuperRegIdxSeqs + 2, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| F8RCSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass SPERCRegClass = { |
| &PPCMCRegisterClasses[SPERCRegClassID], |
| SPERCSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass VFRCRegClass = { |
| &PPCMCRegisterClasses[VFRCRegClassID], |
| VFRCSubClassMask, |
| SuperRegIdxSeqs + 2, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| VFRCSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass SPERC_with_sub_32_in_GPRC_NOR0RegClass = { |
| &PPCMCRegisterClasses[SPERC_with_sub_32_in_GPRC_NOR0RegClassID], |
| SPERC_with_sub_32_in_GPRC_NOR0SubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| SPERC_with_sub_32_in_GPRC_NOR0Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass SPILLTOVSRRC_and_VFRCRegClass = { |
| &PPCMCRegisterClasses[SPILLTOVSRRC_and_VFRCRegClassID], |
| SPILLTOVSRRC_and_VFRCSubClassMask, |
| SuperRegIdxSeqs + 2, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| SPILLTOVSRRC_and_VFRCSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass SPILLTOVSRRC_and_F4RCRegClass = { |
| &PPCMCRegisterClasses[SPILLTOVSRRC_and_F4RCRegClassID], |
| SPILLTOVSRRC_and_F4RCSubClassMask, |
| SuperRegIdxSeqs + 2, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| SPILLTOVSRRC_and_F4RCSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass CTRRC8RegClass = { |
| &PPCMCRegisterClasses[CTRRC8RegClassID], |
| CTRRC8SubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass VSRCRegClass = { |
| &PPCMCRegisterClasses[VSRCRegClassID], |
| VSRCSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000002), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass VSRC_with_sub_64_in_SPILLTOVSRRCRegClass = { |
| &PPCMCRegisterClasses[VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID], |
| VSRC_with_sub_64_in_SPILLTOVSRRCSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000002), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| VSRC_with_sub_64_in_SPILLTOVSRRCSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass QSRCRegClass = { |
| &PPCMCRegisterClasses[QSRCRegClassID], |
| QSRCSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000002), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass VRRCRegClass = { |
| &PPCMCRegisterClasses[VRRCRegClassID], |
| VRRCSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000002), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| VRRCSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass VSLRCRegClass = { |
| &PPCMCRegisterClasses[VSLRCRegClassID], |
| VSLRCSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000002), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| VSLRCSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass VRRC_with_sub_64_in_SPILLTOVSRRCRegClass = { |
| &PPCMCRegisterClasses[VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID], |
| VRRC_with_sub_64_in_SPILLTOVSRRCSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000002), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| VRRC_with_sub_64_in_SPILLTOVSRRCSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass QSRC_with_sub_64_in_SPILLTOVSRRCRegClass = { |
| &PPCMCRegisterClasses[QSRC_with_sub_64_in_SPILLTOVSRRCRegClassID], |
| QSRC_with_sub_64_in_SPILLTOVSRRCSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000002), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| QSRC_with_sub_64_in_SPILLTOVSRRCSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass VSLRC_with_sub_64_in_SPILLTOVSRRCRegClass = { |
| &PPCMCRegisterClasses[VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID], |
| VSLRC_with_sub_64_in_SPILLTOVSRRCSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000002), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| VSLRC_with_sub_64_in_SPILLTOVSRRCSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass QBRCRegClass = { |
| &PPCMCRegisterClasses[QBRCRegClassID], |
| QBRCSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000002), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| QBRCSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass QFRCRegClass = { |
| &PPCMCRegisterClasses[QFRCRegClassID], |
| QFRCSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000002), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| QFRCSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass QBRC_with_sub_64_in_SPILLTOVSRRCRegClass = { |
| &PPCMCRegisterClasses[QBRC_with_sub_64_in_SPILLTOVSRRCRegClassID], |
| QBRC_with_sub_64_in_SPILLTOVSRRCSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000002), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| QBRC_with_sub_64_in_SPILLTOVSRRCSuperclasses, |
| nullptr |
| }; |
| |
| } // end namespace PPC |
| |
| namespace { |
| const TargetRegisterClass* const RegisterClasses[] = { |
| &PPC::VSSRCRegClass, |
| &PPC::GPRCRegClass, |
| &PPC::GPRC_NOR0RegClass, |
| &PPC::SPE4RCRegClass, |
| &PPC::GPRC_and_GPRC_NOR0RegClass, |
| &PPC::CRBITRCRegClass, |
| &PPC::F4RCRegClass, |
| &PPC::CRRCRegClass, |
| &PPC::CARRYRCRegClass, |
| &PPC::CRRC0RegClass, |
| &PPC::CTRRCRegClass, |
| &PPC::VRSAVERCRegClass, |
| &PPC::SPILLTOVSRRCRegClass, |
| &PPC::VSFRCRegClass, |
| &PPC::G8RCRegClass, |
| &PPC::G8RC_NOX0RegClass, |
| &PPC::SPILLTOVSRRC_and_VSFRCRegClass, |
| &PPC::G8RC_and_G8RC_NOX0RegClass, |
| &PPC::F8RCRegClass, |
| &PPC::SPERCRegClass, |
| &PPC::VFRCRegClass, |
| &PPC::SPERC_with_sub_32_in_GPRC_NOR0RegClass, |
| &PPC::SPILLTOVSRRC_and_VFRCRegClass, |
| &PPC::SPILLTOVSRRC_and_F4RCRegClass, |
| &PPC::CTRRC8RegClass, |
| &PPC::VSRCRegClass, |
| &PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClass, |
| &PPC::QSRCRegClass, |
| &PPC::VRRCRegClass, |
| &PPC::VSLRCRegClass, |
| &PPC::VRRC_with_sub_64_in_SPILLTOVSRRCRegClass, |
| &PPC::QSRC_with_sub_64_in_SPILLTOVSRRCRegClass, |
| &PPC::VSLRC_with_sub_64_in_SPILLTOVSRRCRegClass, |
| &PPC::QBRCRegClass, |
| &PPC::QFRCRegClass, |
| &PPC::QBRC_with_sub_64_in_SPILLTOVSRRCRegClass, |
| }; |
| } // end anonymous namespace |
| |
| static const TargetRegisterInfoDesc PPCRegInfoDesc[] = { // Extra Descriptors |
| { 0, false }, |
| { 0, true }, |
| { 0, true }, |
| { 0, false }, |
| { 0, true }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, false }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, false }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| }; |
| unsigned PPCGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const { |
| static const uint8_t Rows[1][6] = { |
| { 0, 0, 0, 0, 0, 0, }, |
| }; |
| |
| --IdxA; assert(IdxA < 6); |
| --IdxB; assert(IdxB < 6); |
| return Rows[0][IdxB]; |
| } |
| |
| struct MaskRolOp { |
| LaneBitmask Mask; |
| uint8_t RotateLeft; |
| }; |
| static const MaskRolOp LaneMaskComposeSequences[] = { |
| { LaneBitmask(0xFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0 |
| { LaneBitmask(0xFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2 |
| { LaneBitmask(0xFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4 |
| { LaneBitmask(0xFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6 |
| { LaneBitmask(0xFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 8 |
| { LaneBitmask(0xFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 } // Sequence 10 |
| }; |
| static const MaskRolOp *const CompositeSequences[] = { |
| &LaneMaskComposeSequences[0], // to sub_32 |
| &LaneMaskComposeSequences[2], // to sub_64 |
| &LaneMaskComposeSequences[4], // to sub_eq |
| &LaneMaskComposeSequences[6], // to sub_gt |
| &LaneMaskComposeSequences[8], // to sub_lt |
| &LaneMaskComposeSequences[10] // to sub_un |
| }; |
| |
| LaneBitmask PPCGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { |
| --IdxA; assert(IdxA < 6 && "Subregister index out of bounds"); |
| LaneBitmask Result; |
| for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) { |
| LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger(); |
| if (unsigned S = Ops->RotateLeft) |
| Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S))); |
| else |
| Result |= LaneBitmask(M); |
| } |
| return Result; |
| } |
| |
| LaneBitmask PPCGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { |
| LaneMask &= getSubRegIndexLaneMask(IdxA); |
| --IdxA; assert(IdxA < 6 && "Subregister index out of bounds"); |
| LaneBitmask Result; |
| for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) { |
| LaneBitmask::Type M = LaneMask.getAsInteger(); |
| if (unsigned S = Ops->RotateLeft) |
| Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S))); |
| else |
| Result |= LaneBitmask(M); |
| } |
| return Result; |
| } |
| |
| const TargetRegisterClass *PPCGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { |
| static const uint8_t Table[36][6] = { |
| { // VSSRC |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // GPRC |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // GPRC_NOR0 |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // SPE4RC |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // GPRC_and_GPRC_NOR0 |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // CRBITRC |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // F4RC |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // CRRC |
| 0, // sub_32 |
| 0, // sub_64 |
| 8, // sub_eq -> CRRC |
| 8, // sub_gt -> CRRC |
| 8, // sub_lt -> CRRC |
| 8, // sub_un -> CRRC |
| }, |
| { // CARRYRC |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // CRRC0 |
| 0, // sub_32 |
| 0, // sub_64 |
| 10, // sub_eq -> CRRC0 |
| 10, // sub_gt -> CRRC0 |
| 10, // sub_lt -> CRRC0 |
| 10, // sub_un -> CRRC0 |
| }, |
| { // CTRRC |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // VRSAVERC |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // SPILLTOVSRRC |
| 15, // sub_32 -> G8RC |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // VSFRC |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // G8RC |
| 15, // sub_32 -> G8RC |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // G8RC_NOX0 |
| 16, // sub_32 -> G8RC_NOX0 |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // SPILLTOVSRRC_and_VSFRC |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // G8RC_and_G8RC_NOX0 |
| 18, // sub_32 -> G8RC_and_G8RC_NOX0 |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // F8RC |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // SPERC |
| 20, // sub_32 -> SPERC |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // VFRC |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // SPERC_with_sub_32_in_GPRC_NOR0 |
| 22, // sub_32 -> SPERC_with_sub_32_in_GPRC_NOR0 |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // SPILLTOVSRRC_and_VFRC |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // SPILLTOVSRRC_and_F4RC |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // CTRRC8 |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // VSRC |
| 0, // sub_32 |
| 26, // sub_64 -> VSRC |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // VSRC_with_sub_64_in_SPILLTOVSRRC |
| 0, // sub_32 |
| 27, // sub_64 -> VSRC_with_sub_64_in_SPILLTOVSRRC |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // QSRC |
| 0, // sub_32 |
| 28, // sub_64 -> QSRC |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // VRRC |
| 0, // sub_32 |
| 29, // sub_64 -> VRRC |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // VSLRC |
| 0, // sub_32 |
| 30, // sub_64 -> VSLRC |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // VRRC_with_sub_64_in_SPILLTOVSRRC |
| 0, // sub_32 |
| 31, // sub_64 -> VRRC_with_sub_64_in_SPILLTOVSRRC |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // QSRC_with_sub_64_in_SPILLTOVSRRC |
| 0, // sub_32 |
| 32, // sub_64 -> QSRC_with_sub_64_in_SPILLTOVSRRC |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // VSLRC_with_sub_64_in_SPILLTOVSRRC |
| 0, // sub_32 |
| 33, // sub_64 -> VSLRC_with_sub_64_in_SPILLTOVSRRC |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // QBRC |
| 0, // sub_32 |
| 34, // sub_64 -> QBRC |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // QFRC |
| 0, // sub_32 |
| 35, // sub_64 -> QFRC |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| { // QBRC_with_sub_64_in_SPILLTOVSRRC |
| 0, // sub_32 |
| 36, // sub_64 -> QBRC_with_sub_64_in_SPILLTOVSRRC |
| 0, // sub_eq |
| 0, // sub_gt |
| 0, // sub_lt |
| 0, // sub_un |
| }, |
| }; |
| assert(RC && "Missing regclass"); |
| if (!Idx) return RC; |
| --Idx; |
| assert(Idx < 6 && "Bad subreg"); |
| unsigned TV = Table[RC->getID()][Idx]; |
| return TV ? getRegClass(TV - 1) : nullptr; |
| } |
| |
| /// Get the weight in units of pressure for this register class. |
| const RegClassWeight &PPCGenRegisterInfo:: |
| getRegClassWeight(const TargetRegisterClass *RC) const { |
| static const RegClassWeight RCWeightTable[] = { |
| {1, 64}, // VSSRC |
| {1, 34}, // GPRC |
| {1, 34}, // GPRC_NOR0 |
| {1, 34}, // SPE4RC |
| {1, 33}, // GPRC_and_GPRC_NOR0 |
| {1, 32}, // CRBITRC |
| {1, 32}, // F4RC |
| {4, 32}, // CRRC |
| {1, 1}, // CARRYRC |
| {4, 4}, // CRRC0 |
| {0, 0}, // CTRRC |
| {1, 1}, // VRSAVERC |
| {1, 68}, // SPILLTOVSRRC |
| {1, 64}, // VSFRC |
| {1, 34}, // G8RC |
| {1, 34}, // G8RC_NOX0 |
| {1, 34}, // SPILLTOVSRRC_and_VSFRC |
| {1, 33}, // G8RC_and_G8RC_NOX0 |
| {1, 32}, // F8RC |
| {1, 32}, // SPERC |
| {1, 32}, // VFRC |
| {1, 31}, // SPERC_with_sub_32_in_GPRC_NOR0 |
| {1, 20}, // SPILLTOVSRRC_and_VFRC |
| {1, 14}, // SPILLTOVSRRC_and_F4RC |
| {0, 0}, // CTRRC8 |
| {1, 64}, // VSRC |
| {1, 34}, // VSRC_with_sub_64_in_SPILLTOVSRRC |
| {1, 32}, // QSRC |
| {1, 32}, // VRRC |
| {1, 32}, // VSLRC |
| {1, 20}, // VRRC_with_sub_64_in_SPILLTOVSRRC |
| {1, 14}, // QSRC_with_sub_64_in_SPILLTOVSRRC |
| {1, 14}, // VSLRC_with_sub_64_in_SPILLTOVSRRC |
| {1, 32}, // QBRC |
| {1, 32}, // QFRC |
| {1, 14}, // QBRC_with_sub_64_in_SPILLTOVSRRC |
| }; |
| return RCWeightTable[RC->getID()]; |
| } |
| |
| /// Get the weight in units of pressure for this register unit. |
| unsigned PPCGenRegisterInfo:: |
| getRegUnitWeight(unsigned RegUnit) const { |
| assert(RegUnit < 171 && "invalid register unit"); |
| // All register units have unit weight. |
| return 1; |
| } |
| |
| |
| // Get the number of dimensions of register pressure. |
| unsigned PPCGenRegisterInfo::getNumRegPressureSets() const { |
| return 17; |
| } |
| |
| // Get the name of this register unit pressure set. |
| const char *PPCGenRegisterInfo:: |
| getRegPressureSetName(unsigned Idx) const { |
| static const char *const PressureNameTable[] = { |
| "CARRYRC", |
| "VRSAVERC", |
| "CRRC0", |
| "SPILLTOVSRRC_and_F4RC", |
| "SPILLTOVSRRC_and_VFRC", |
| "CRBITRC", |
| "F4RC", |
| "VFRC", |
| "SPILLTOVSRRC_and_VSFRC", |
| "GPRC", |
| "SPILLTOVSRRC_and_VSFRC+VFRC", |
| "F4RC+SPILLTOVSRRC_and_VSFRC", |
| "VSSRC", |
| "SPILLTOVSRRC", |
| "SPILLTOVSRRC+VFRC", |
| "F4RC+SPILLTOVSRRC", |
| "VSSRC+SPILLTOVSRRC", |
| }; |
| return PressureNameTable[Idx]; |
| } |
| |
| // Get the register unit pressure limit for this dimension. |
| // This limit must be adjusted dynamically for reserved registers. |
| unsigned PPCGenRegisterInfo:: |
| getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const { |
| static const uint8_t PressureLimitTable[] = { |
| 1, // 0: CARRYRC |
| 1, // 1: VRSAVERC |
| 4, // 2: CRRC0 |
| 14, // 3: SPILLTOVSRRC_and_F4RC |
| 20, // 4: SPILLTOVSRRC_and_VFRC |
| 32, // 5: CRBITRC |
| 32, // 6: F4RC |
| 32, // 7: VFRC |
| 34, // 8: SPILLTOVSRRC_and_VSFRC |
| 35, // 9: GPRC |
| 46, // 10: SPILLTOVSRRC_and_VSFRC+VFRC |
| 52, // 11: F4RC+SPILLTOVSRRC_and_VSFRC |
| 64, // 12: VSSRC |
| 69, // 13: SPILLTOVSRRC |
| 80, // 14: SPILLTOVSRRC+VFRC |
| 86, // 15: F4RC+SPILLTOVSRRC |
| 98, // 16: VSSRC+SPILLTOVSRRC |
| }; |
| return PressureLimitTable[Idx]; |
| } |
| |
| /// Table of pressure sets per register class or unit. |
| static const int RCSetsTable[] = { |
| /* 0 */ 0, -1, |
| /* 2 */ 1, -1, |
| /* 4 */ 2, 5, -1, |
| /* 7 */ 9, 13, -1, |
| /* 10 */ 12, 16, -1, |
| /* 13 */ 7, 10, 12, 14, 16, -1, |
| /* 19 */ 6, 11, 12, 15, 16, -1, |
| /* 25 */ 9, 13, 14, 15, 16, -1, |
| /* 31 */ 3, 6, 8, 10, 11, 12, 13, 14, 15, 16, -1, |
| /* 42 */ 4, 7, 8, 10, 11, 12, 13, 14, 15, 16, -1, |
| }; |
| |
| /// Get the dimensions of register pressure impacted by this register class. |
| /// Returns a -1 terminated array of pressure set IDs |
| const int* PPCGenRegisterInfo:: |
| getRegClassPressureSets(const TargetRegisterClass *RC) const { |
| static const uint8_t RCSetStartTable[] = { |
| 10,25,7,25,25,5,19,5,0,4,1,2,26,10,25,7,33,25,19,25,13,25,42,31,1,10,33,19,13,19,42,31,31,19,19,31,}; |
| return &RCSetsTable[RCSetStartTable[RC->getID()]]; |
| } |
| |
| /// Get the dimensions of register pressure impacted by this register unit. |
| /// Returns a -1 terminated array of pressure set IDs |
| const int* PPCGenRegisterInfo:: |
| getRegUnitPressureSets(unsigned RegUnit) const { |
| assert(RegUnit < 171 && "invalid register unit"); |
| static const uint8_t RUSetStartTable[] = { |
| 25,0,1,25,1,1,1,2,7,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,1,31,31,31,31,31,31,31,31,31,31,31,31,31,31,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,1,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,13,13,13,13,13,13,13,13,13,13,13,13,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,}; |
| return &RCSetsTable[RUSetStartTable[RegUnit]]; |
| } |
| |
| extern const MCRegisterDesc PPCRegDesc[]; |
| extern const MCPhysReg PPCRegDiffLists[]; |
| extern const LaneBitmask PPCLaneMaskLists[]; |
| extern const char PPCRegStrings[]; |
| extern const char PPCRegClassStrings[]; |
| extern const MCPhysReg PPCRegUnitRoots[][2]; |
| extern const uint16_t PPCSubRegIdxLists[]; |
| extern const MCRegisterInfo::SubRegCoveredBits PPCSubRegIdxRanges[]; |
| extern const uint16_t PPCRegEncodingTable[]; |
| // PPC Dwarf<->LLVM register mappings. |
| extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0Dwarf2L[]; |
| extern const unsigned PPCDwarfFlavour0Dwarf2LSize; |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1Dwarf2L[]; |
| extern const unsigned PPCDwarfFlavour1Dwarf2LSize; |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0Dwarf2L[]; |
| extern const unsigned PPCEHFlavour0Dwarf2LSize; |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1Dwarf2L[]; |
| extern const unsigned PPCEHFlavour1Dwarf2LSize; |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0L2Dwarf[]; |
| extern const unsigned PPCDwarfFlavour0L2DwarfSize; |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1L2Dwarf[]; |
| extern const unsigned PPCDwarfFlavour1L2DwarfSize; |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0L2Dwarf[]; |
| extern const unsigned PPCEHFlavour0L2DwarfSize; |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1L2Dwarf[]; |
| extern const unsigned PPCEHFlavour1L2DwarfSize; |
| |
| PPCGenRegisterInfo:: |
| PPCGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, |
| unsigned PC, unsigned HwMode) |
| : TargetRegisterInfo(PPCRegInfoDesc, RegisterClasses, RegisterClasses+36, |
| SubRegIndexNameTable, SubRegIndexLaneMaskTable, |
| LaneBitmask(0xFFFFFFC0), RegClassInfos, HwMode) { |
| InitMCRegisterInfo(PPCRegDesc, 344, RA, PC, |
| PPCMCRegisterClasses, 36, |
| PPCRegUnitRoots, |
| 171, |
| PPCRegDiffLists, |
| PPCLaneMaskLists, |
| PPCRegStrings, |
| PPCRegClassStrings, |
| PPCSubRegIdxLists, |
| 7, |
| PPCSubRegIdxRanges, |
| PPCRegEncodingTable); |
| |
| switch (DwarfFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| mapDwarfRegsToLLVMRegs(PPCDwarfFlavour0Dwarf2L, PPCDwarfFlavour0Dwarf2LSize, false); |
| break; |
| case 1: |
| mapDwarfRegsToLLVMRegs(PPCDwarfFlavour1Dwarf2L, PPCDwarfFlavour1Dwarf2LSize, false); |
| break; |
| } |
| switch (EHFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| mapDwarfRegsToLLVMRegs(PPCEHFlavour0Dwarf2L, PPCEHFlavour0Dwarf2LSize, true); |
| break; |
| case 1: |
| mapDwarfRegsToLLVMRegs(PPCEHFlavour1Dwarf2L, PPCEHFlavour1Dwarf2LSize, true); |
| break; |
| } |
| switch (DwarfFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| mapLLVMRegsToDwarfRegs(PPCDwarfFlavour0L2Dwarf, PPCDwarfFlavour0L2DwarfSize, false); |
| break; |
| case 1: |
| mapLLVMRegsToDwarfRegs(PPCDwarfFlavour1L2Dwarf, PPCDwarfFlavour1L2DwarfSize, false); |
| break; |
| } |
| switch (EHFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| mapLLVMRegsToDwarfRegs(PPCEHFlavour0L2Dwarf, PPCEHFlavour0L2DwarfSize, true); |
| break; |
| case 1: |
| mapLLVMRegsToDwarfRegs(PPCEHFlavour1L2Dwarf, PPCEHFlavour1L2DwarfSize, true); |
| break; |
| } |
| } |
| |
| static const MCPhysReg CSR_64_AllRegs_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 }; |
| static const uint32_t CSR_64_AllRegs_RegMask[] = { 0xffeff000, 0x001fffff, 0xfc800000, 0x007fffe3, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfc800000, 0xff7fffe3, 0x00ffffff, }; |
| static const MCPhysReg CSR_64_AllRegs_Altivec_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 }; |
| static const uint32_t CSR_64_AllRegs_Altivec_RegMask[] = { 0xffeff000, 0x001fffff, 0xfc800000, 0x007fffe3, 0xff800000, 0xffffffff, 0x007fffff, 0x00000000, 0xfc800000, 0xff7fffe3, 0x00ffffff, }; |
| static const MCPhysReg CSR_64_AllRegs_VSX_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, 0 }; |
| static const uint32_t CSR_64_AllRegs_VSX_RegMask[] = { 0xffeff000, 0x001fffff, 0xfc800000, 0x007fffe3, 0xff800000, 0xffffffff, 0xffffffff, 0x007fffff, 0xfc800000, 0xff7fffe3, 0x00ffffff, }; |
| static const MCPhysReg CSR_Altivec_SaveList[] = { PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 }; |
| static const uint32_t CSR_Altivec_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x007ff800, 0x007ff800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; |
| static const MCPhysReg CSR_Darwin32_SaveList[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, 0 }; |
| static const uint32_t CSR_Darwin32_RegMask[] = { 0x0001c000, 0x001ffff8, 0x00000000, 0x007ffff0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x1c000000, 0x001c1c1c, }; |
| static const MCPhysReg CSR_Darwin32_Altivec_SaveList[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 }; |
| static const uint32_t CSR_Darwin32_Altivec_RegMask[] = { 0x0001c000, 0x001ffff8, 0x00000000, 0x007ffff0, 0x00000000, 0x007ff800, 0x007ff800, 0x00000000, 0x00000000, 0x1c000000, 0x001c1c1c, }; |
| static const MCPhysReg CSR_Darwin64_SaveList[] = { PPC::X13, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, 0 }; |
| static const uint32_t CSR_Darwin64_RegMask[] = { 0x0001c000, 0x001ffff8, 0x00000000, 0x007ffff0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x1c7ffff0, 0x001c1c1c, }; |
| static const MCPhysReg CSR_Darwin64_Altivec_SaveList[] = { PPC::X13, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 }; |
| static const uint32_t CSR_Darwin64_Altivec_RegMask[] = { 0x0001c000, 0x001ffff8, 0x00000000, 0x007ffff0, 0x00000000, 0x007ff800, 0x007ff800, 0x00000000, 0x00000000, 0x1c7ffff0, 0x001c1c1c, }; |
| static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 }; |
| static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; |
| static const MCPhysReg CSR_SPE_SaveList[] = { PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, PPC::S30, PPC::S31, 0 }; |
| static const uint32_t CSR_SPE_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x007fffe0, 0x007fffe0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; |
| static const MCPhysReg CSR_SRV464_TLS_PE_SaveList[] = { 0 }; |
| static const uint32_t CSR_SRV464_TLS_PE_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; |
| static const MCPhysReg CSR_SVR32_ColdCC_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 }; |
| static const uint32_t CSR_SVR32_ColdCC_RegMask[] = { 0xffaff000, 0x001fffff, 0xf8000000, 0x007fffe3, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff000000, 0x00ffffff, }; |
| static const MCPhysReg CSR_SVR32_ColdCC_Altivec_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 }; |
| static const uint32_t CSR_SVR32_ColdCC_Altivec_RegMask[] = { 0xffaff000, 0x001fffff, 0xf8000000, 0x007fffe3, 0xfd800000, 0xfdffffff, 0x007fffff, 0x00000000, 0x00000000, 0xff000000, 0x00ffffff, }; |
| static const MCPhysReg CSR_SVR432_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, 0 }; |
| static const uint32_t CSR_SVR432_RegMask[] = { 0x0001c000, 0x001ffff8, 0x00000000, 0x007fffe0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x1c000000, 0x001c1c1c, }; |
| static const MCPhysReg CSR_SVR432_Altivec_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 }; |
| static const uint32_t CSR_SVR432_Altivec_RegMask[] = { 0x0001c000, 0x001ffff8, 0x00000000, 0x007fffe0, 0x00000000, 0x007ff800, 0x007ff800, 0x00000000, 0x00000000, 0x1c000000, 0x001c1c1c, }; |
| static const MCPhysReg CSR_SVR432_COMM_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, 0 }; |
| static const uint32_t CSR_SVR432_COMM_RegMask[] = { 0x0001c000, 0x00000000, 0x00000000, 0x007fffe0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x1c000000, 0x001c1c1c, }; |
| static const MCPhysReg CSR_SVR432_SPE_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, PPC::S30, PPC::S31, 0 }; |
| static const uint32_t CSR_SVR432_SPE_RegMask[] = { 0x0001c000, 0x00000000, 0x00000000, 0x007fffe0, 0x007fffe0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x1c000000, 0x001c1c1c, }; |
| static const MCPhysReg CSR_SVR464_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, 0 }; |
| static const uint32_t CSR_SVR464_RegMask[] = { 0x0001c000, 0x001ffff8, 0x00000000, 0x007fffe0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x1c7fffe0, 0x001c1c1c, }; |
| static const MCPhysReg CSR_SVR464_Altivec_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 }; |
| static const uint32_t CSR_SVR464_Altivec_RegMask[] = { 0x0001c000, 0x001ffff8, 0x00000000, 0x007fffe0, 0x00000000, 0x007ff800, 0x007ff800, 0x00000000, 0x00000000, 0x1c7fffe0, 0x001c1c1c, }; |
| static const MCPhysReg CSR_SVR464_Altivec_ViaCopy_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 }; |
| static const uint32_t CSR_SVR464_Altivec_ViaCopy_RegMask[] = { 0x0001c000, 0x001ffff8, 0x00000000, 0x007fffe0, 0x00000000, 0x007ff800, 0x007ff800, 0x00000000, 0x00000000, 0x1c7fffe0, 0x001c1c1c, }; |
| static const MCPhysReg CSR_SVR464_R2_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::X2, 0 }; |
| static const uint32_t CSR_SVR464_R2_RegMask[] = { 0x0001c000, 0x001ffff8, 0x02000000, 0x007fffe0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02000000, 0x1c7fffe0, 0x001c1c1c, }; |
| static const MCPhysReg CSR_SVR464_R2_Altivec_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::X2, 0 }; |
| static const uint32_t CSR_SVR464_R2_Altivec_RegMask[] = { 0x0001c000, 0x001ffff8, 0x02000000, 0x007fffe0, 0x00000000, 0x007ff800, 0x007ff800, 0x00000000, 0x02000000, 0x1c7fffe0, 0x001c1c1c, }; |
| static const MCPhysReg CSR_SVR464_R2_Altivec_ViaCopy_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::X2, 0 }; |
| static const uint32_t CSR_SVR464_R2_Altivec_ViaCopy_RegMask[] = { 0x0001c000, 0x001ffff8, 0x02000000, 0x007fffe0, 0x00000000, 0x007ff800, 0x007ff800, 0x00000000, 0x02000000, 0x1c7fffe0, 0x001c1c1c, }; |
| static const MCPhysReg CSR_SVR464_R2_ViaCopy_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::X2, 0 }; |
| static const uint32_t CSR_SVR464_R2_ViaCopy_RegMask[] = { 0x0001c000, 0x001ffff8, 0x02000000, 0x007fffe0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02000000, 0x1c7fffe0, 0x001c1c1c, }; |
| static const MCPhysReg CSR_SVR464_ViaCopy_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, 0 }; |
| static const uint32_t CSR_SVR464_ViaCopy_RegMask[] = { 0x0001c000, 0x001ffff8, 0x00000000, 0x007fffe0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x1c7fffe0, 0x001c1c1c, }; |
| static const MCPhysReg CSR_SVR64_ColdCC_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 }; |
| static const uint32_t CSR_SVR64_ColdCC_RegMask[] = { 0xffaff000, 0x001fffff, 0xf8000000, 0x007fffe3, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf8000000, 0xff7fffe3, 0x00ffffff, }; |
| static const MCPhysReg CSR_SVR64_ColdCC_Altivec_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 }; |
| static const uint32_t CSR_SVR64_ColdCC_Altivec_RegMask[] = { 0xffaff000, 0x001fffff, 0xf8000000, 0x007fffe3, 0xfd800000, 0xfdffffff, 0x007fffff, 0x00000000, 0xf8000000, 0xff7fffe3, 0x00ffffff, }; |
| static const MCPhysReg CSR_SVR64_ColdCC_R2_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::X2, 0 }; |
| static const uint32_t CSR_SVR64_ColdCC_R2_RegMask[] = { 0xffaff000, 0x001fffff, 0xfa000000, 0x007fffe3, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfa000000, 0xff7fffe3, 0x00ffffff, }; |
| static const MCPhysReg CSR_SVR64_ColdCC_R2_Altivec_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::X2, 0 }; |
| static const uint32_t CSR_SVR64_ColdCC_R2_Altivec_RegMask[] = { 0xffaff000, 0x001fffff, 0xfa000000, 0x007fffe3, 0xfd800000, 0xfdffffff, 0x007fffff, 0x00000000, 0xfa000000, 0xff7fffe3, 0x00ffffff, }; |
| |
| |
| ArrayRef<const uint32_t *> PPCGenRegisterInfo::getRegMasks() const { |
| static const uint32_t *const Masks[] = { |
| CSR_64_AllRegs_RegMask, |
| CSR_64_AllRegs_Altivec_RegMask, |
| CSR_64_AllRegs_VSX_RegMask, |
| CSR_Altivec_RegMask, |
| CSR_Darwin32_RegMask, |
| CSR_Darwin32_Altivec_RegMask, |
| CSR_Darwin64_RegMask, |
| CSR_Darwin64_Altivec_RegMask, |
| CSR_NoRegs_RegMask, |
| CSR_SPE_RegMask, |
| CSR_SRV464_TLS_PE_RegMask, |
| CSR_SVR32_ColdCC_RegMask, |
| CSR_SVR32_ColdCC_Altivec_RegMask, |
| CSR_SVR432_RegMask, |
| CSR_SVR432_Altivec_RegMask, |
| CSR_SVR432_COMM_RegMask, |
| CSR_SVR432_SPE_RegMask, |
| CSR_SVR464_RegMask, |
| CSR_SVR464_Altivec_RegMask, |
| CSR_SVR464_Altivec_ViaCopy_RegMask, |
| CSR_SVR464_R2_RegMask, |
| CSR_SVR464_R2_Altivec_RegMask, |
| CSR_SVR464_R2_Altivec_ViaCopy_RegMask, |
| CSR_SVR464_R2_ViaCopy_RegMask, |
| CSR_SVR464_ViaCopy_RegMask, |
| CSR_SVR64_ColdCC_RegMask, |
| CSR_SVR64_ColdCC_Altivec_RegMask, |
| CSR_SVR64_ColdCC_R2_RegMask, |
| CSR_SVR64_ColdCC_R2_Altivec_RegMask, |
| }; |
| return makeArrayRef(Masks); |
| } |
| |
| ArrayRef<const char *> PPCGenRegisterInfo::getRegMaskNames() const { |
| static const char *const Names[] = { |
| "CSR_64_AllRegs", |
| "CSR_64_AllRegs_Altivec", |
| "CSR_64_AllRegs_VSX", |
| "CSR_Altivec", |
| "CSR_Darwin32", |
| "CSR_Darwin32_Altivec", |
| "CSR_Darwin64", |
| "CSR_Darwin64_Altivec", |
| "CSR_NoRegs", |
| "CSR_SPE", |
| "CSR_SRV464_TLS_PE", |
| "CSR_SVR32_ColdCC", |
| "CSR_SVR32_ColdCC_Altivec", |
| "CSR_SVR432", |
| "CSR_SVR432_Altivec", |
| "CSR_SVR432_COMM", |
| "CSR_SVR432_SPE", |
| "CSR_SVR464", |
| "CSR_SVR464_Altivec", |
| "CSR_SVR464_Altivec_ViaCopy", |
| "CSR_SVR464_R2", |
| "CSR_SVR464_R2_Altivec", |
| "CSR_SVR464_R2_Altivec_ViaCopy", |
| "CSR_SVR464_R2_ViaCopy", |
| "CSR_SVR464_ViaCopy", |
| "CSR_SVR64_ColdCC", |
| "CSR_SVR64_ColdCC_Altivec", |
| "CSR_SVR64_ColdCC_R2", |
| "CSR_SVR64_ColdCC_R2_Altivec", |
| }; |
| return makeArrayRef(Names); |
| } |
| |
| const PPCFrameLowering * |
| PPCGenRegisterInfo::getFrameLowering(const MachineFunction &MF) { |
| return static_cast<const PPCFrameLowering *>( |
| MF.getSubtarget().getFrameLowering()); |
| } |
| |
| } // end namespace llvm |
| |
| #endif // GET_REGINFO_TARGET_DESC |
| |