| //===- subzero/src/IceInstX8664.def - X-macros for x86-64 insts -*- C++ -*-===// |
| // |
| // The Subzero Code Generator |
| // |
| // This file is distributed under the University of Illinois Open Source |
| // License. See LICENSE.TXT for details. |
| // |
| //===----------------------------------------------------------------------===// |
| // |
| // This file defines properties of lowered x86-64 instructions in the |
| // form of x-macros. |
| // |
| //===----------------------------------------------------------------------===// |
| |
| #ifndef SUBZERO_SRC_ICEINSTX8664_DEF |
| #define SUBZERO_SRC_ICEINSTX8664_DEF |
| |
| // NOTE: we use the 32bit register names for two reasons: |
| // (1) it makes it easier to implement the x86 assembler template. |
| // (2) when generating code, subzero defaults to using 32 bit registers, |
| // so using the 32 bit register name would hopefully make this design |
| // more explicit. |
| // NOTE: esp is not considered isInt, to avoid register allocating it. |
| #define REGX8664_GPR_TABLE \ |
| /* val, encode, name64, name, name16, name8, scratch, preserved, stackptr, \ |
| frameptr, isInt, isFP */ \ |
| X(Reg_eax, = 0, "rax", "eax" , "ax" , "al" , 1, 0, 0, 0, 1, 0) \ |
| X(Reg_ecx, = 1, "rcx", "ecx" , "cx" , "cl" , 1, 0, 0, 0, 1, 0) \ |
| X(Reg_edx, = 2, "rdx", "edx" , "dx" , "dl" , 1, 0, 0, 0, 1, 0) \ |
| X(Reg_ebx, = 3, "rbx", "ebx" , "bx" , "bl" , 0, 1, 0, 0, 1, 0) \ |
| X(Reg_esp, = 4, "rsp", "esp" , "sp" , "spl" , 0, 0, 1, 0, 0, 0) \ |
| X(Reg_ebp, = 5, "rbp", "ebp" , "bp" , "bpl" , 0, 0, 0, 1, 1, 0) \ |
| X(Reg_esi, = 6, "rsi", "esi" , "si" , "sil" , 1, 0, 0, 0, 1, 0) \ |
| X(Reg_edi, = 7, "rdi", "edi" , "di" , "dil" , 1, 0, 0, 0, 1, 0) \ |
| X(Reg_r8d, = 8, "r8" , "r8d" , "r8w", "r8l" , 1, 0, 0, 0, 1, 0) \ |
| X(Reg_r9d, = 9, "r9" , "r9d" , "r9w", "r9l" , 1, 0, 0, 0, 1, 0) \ |
| X(Reg_r10d, = 10, "r10", "r10d", "r10w", "r10l", 1, 0, 0, 0, 1, 0) \ |
| X(Reg_r11d, = 11, "r11", "r11d", "r11w", "r11l", 1, 0, 0, 0, 1, 0) \ |
| X(Reg_r12d, = 12, "r12", "r12d", "r12w", "r12l", 0, 1, 0, 0, 1, 0) \ |
| X(Reg_r13d, = 13, "r13", "r13d", "r13w", "r12l", 0, 1, 0, 0, 1, 0) \ |
| X(Reg_r14d, = 14, "r14", "r14d", "r14w", "r14l", 0, 1, 0, 0, 1, 0) \ |
| X(Reg_r15d, = 15, "r15", "r15d", "r15w", "r15l", 0, 1, 0, 0, 1, 0) |
| |
| #define REGX8664_XMM_TABLE \ |
| /* val, encode, name64, name, name16, name8, scratch, preserved, stackptr, \ |
| frameptr, isInt, isFP */ \ |
| X(Reg_xmm0, = 0, "xmm0" , "", "", "", 1, 0, 0, 0, 0, 1) \ |
| X(Reg_xmm1, = 1, "xmm1" , "", "", "", 1, 0, 0, 0, 0, 1) \ |
| X(Reg_xmm2, = 2, "xmm2" , "", "", "", 1, 0, 0, 0, 0, 1) \ |
| X(Reg_xmm3, = 3, "xmm3" , "", "", "", 1, 0, 0, 0, 0, 1) \ |
| X(Reg_xmm4, = 4, "xmm4" , "", "", "", 1, 0, 0, 0, 0, 1) \ |
| X(Reg_xmm5, = 5, "xmm5" , "", "", "", 1, 0, 0, 0, 0, 1) \ |
| X(Reg_xmm6, = 6, "xmm6" , "", "", "", 1, 0, 0, 0, 0, 1) \ |
| X(Reg_xmm7, = 7, "xmm7" , "", "", "", 1, 0, 0, 0, 0, 1) \ |
| X(Reg_xmm8, = 8, "xmm8" , "", "", "", 1, 0, 0, 0, 0, 1) \ |
| X(Reg_xmm9, = 9, "xmm9" , "", "", "", 1, 0, 0, 0, 0, 1) \ |
| X(Reg_xmm10, = 10, "xmm10", "", "", "", 1, 0, 0, 0, 0, 1) \ |
| X(Reg_xmm11, = 11, "xmm11", "", "", "", 1, 0, 0, 0, 0, 1) \ |
| X(Reg_xmm12, = 12, "xmm12", "", "", "", 1, 0, 0, 0, 0, 1) \ |
| X(Reg_xmm13, = 13, "xmm13", "", "", "", 1, 0, 0, 0, 0, 1) \ |
| X(Reg_xmm14, = 14, "xmm14", "", "", "", 1, 0, 0, 0, 0, 1) \ |
| X(Reg_xmm15, = 15, "xmm15", "", "", "", 1, 0, 0, 0, 0, 1) |
| //#define X(val, encode, name, name32, name16, name8, scratch, preserved, |
| // stackptr, frameptr, isI8, isInt, isFP) |
| |
| // We also provide a combined table, so that there is a namespace where |
| // all of the registers are considered and have distinct numberings. |
| // This is in contrast to the above, where the "encode" is based on how |
| // the register numbers will be encoded in binaries and values can overlap. |
| // We don't want the register allocator choosing Reg_ah, in particular |
| // for lowering insertelement to pinsrb where internally we use an |
| // 8-bit operand but externally pinsrb uses a 32-bit register, in |
| // which Reg_ah doesn't map to eax. |
| #define REGX8664_TABLE \ |
| /* val, encode, name64, name, name16, name8, scratch, preserved, \ |
| stackptr, frameptr, isInt, isFP */ \ |
| REGX8664_GPR_TABLE \ |
| X(Reg_ah, = Reg_rax + 4, "?ah", "?ah", "?ah", "ah", 0, 0, 0, 0, 0, 0) \ |
| REGX8664_XMM_TABLE |
| //#define X(val, encode, name, name32, name16, name8, scratch, preserved, |
| // stackptr, frameptr, isI8, isInt, isFP) |
| |
| #define REGX8664_TABLE_BOUNDS \ |
| /* val , init */ \ |
| X(Reg_GPR_First, = Reg_eax ) \ |
| X(Reg_GPR_Last , = Reg_r15d ) \ |
| X(Reg_XMM_First, = Reg_xmm0 ) \ |
| X(Reg_XMM_Last , = Reg_xmm15) |
| // define X(val, init) |
| |
| // We also need the encodings for the Byte registers (other info overlaps |
| // what is in the REGX8664_GPR_TABLE). We don't expose the ah, ch, dh, |
| // bh registers to keep register selection simple. |
| #define REGX8664_BYTEREG_TABLE \ |
| /* val , encode */ \ |
| X(Reg_al , = 0) \ |
| X(Reg_cl , = 1) \ |
| X(Reg_dl , = 2) \ |
| X(Reg_bl , = 3) \ |
| X(Reg_spl , = 4) \ |
| X(Reg_bpl , = 5) \ |
| X(Reg_sil , = 6) \ |
| X(Reg_dil , = 7) \ |
| X(Reg_r8l , = 8) \ |
| X(Reg_r9l , = 9) \ |
| X(Reg_r10l, = 10) \ |
| X(Reg_r11l, = 11) \ |
| X(Reg_r12l, = 12) \ |
| X(Reg_r13l, = 13) \ |
| X(Reg_r14l, = 14) \ |
| X(Reg_r15l, = 15) |
| //#define X(val, encode) |
| |
| #define ICEINSTX8664BR_TABLE \ |
| /* enum value, encode, opposite, dump, emit */ \ |
| X(Br_o , = 0, Br_no , "o" , "jo" ) \ |
| X(Br_no , = 1, Br_o , "no", "jno") \ |
| X(Br_b , = 2, Br_ae , "b" , "jb" ) \ |
| X(Br_ae , = 3, Br_b , "ae", "jae") \ |
| X(Br_e , = 4, Br_ne , "e" , "je" ) \ |
| X(Br_ne , = 5, Br_e , "ne", "jne") \ |
| X(Br_be , = 6, Br_a , "be", "jbe") \ |
| X(Br_a , = 7, Br_be , "a" , "ja" ) \ |
| X(Br_s , = 8, Br_ns , "s" , "js" ) \ |
| X(Br_ns , = 9, Br_s , "ns", "jns") \ |
| X(Br_p , = 10, Br_np , "p" , "jp" ) \ |
| X(Br_np , = 11, Br_p , "np", "jnp") \ |
| X(Br_l , = 12, Br_ge , "l" , "jl" ) \ |
| X(Br_ge , = 13, Br_l , "ge", "jge") \ |
| X(Br_le , = 14, Br_g , "le", "jle") \ |
| X(Br_g , = 15, Br_le , "g" , "jg") |
| //#define X(tag, encode, opp, dump, emit) |
| |
| #define ICEINSTX8664CMPPS_TABLE \ |
| /* enum value, emit */ \ |
| X(Cmpps_eq , "eq" ) \ |
| X(Cmpps_lt , "lt" ) \ |
| X(Cmpps_le , "le" ) \ |
| X(Cmpps_unord, "unord") \ |
| X(Cmpps_neq , "neq" ) \ |
| X(Cmpps_nlt , "nlt" ) \ |
| X(Cmpps_nle , "nle" ) \ |
| X(Cmpps_ord , "ord" ) |
| //#define X(tag, emit) |
| |
| #define ICETYPEX8664_TABLE \ |
| /* tag , element type, cvt , sdss, pack, width, fld */ \ |
| X(IceType_void , IceType_void, "?" , "" , "" , "" , "" ) \ |
| X(IceType_i1 , IceType_void, "si", "" , "" , "b" , "" ) \ |
| X(IceType_i8 , IceType_void, "si", "" , "" , "b" , "" ) \ |
| X(IceType_i16 , IceType_void, "si", "" , "" , "w" , "" ) \ |
| X(IceType_i32 , IceType_void, "si", "" , "" , "l" , "" ) \ |
| X(IceType_i64 , IceType_void, "si", "" , "" , "q" , "" ) \ |
| X(IceType_f32 , IceType_void, "ss", "ss", "d" , "" , "s") \ |
| X(IceType_f64 , IceType_void, "sd", "sd", "q" , "" , "l") \ |
| X(IceType_v4i1 , IceType_i32 , "?" , "" , "d" , "" , "" ) \ |
| X(IceType_v8i1 , IceType_i16 , "?" , "" , "w" , "" , "" ) \ |
| X(IceType_v16i1, IceType_i8 , "?" , "" , "b" , "" , "" ) \ |
| X(IceType_v16i8, IceType_i8 , "?" , "" , "b" , "" , "" ) \ |
| X(IceType_v8i16, IceType_i16 , "?" , "" , "w" , "" , "" ) \ |
| X(IceType_v4i32, IceType_i32 , "dq", "" , "d" , "" , "" ) \ |
| X(IceType_v4f32, IceType_f32 , "ps", "" , "d" , "" , "" ) |
| //#define X(tag, elementty, cvt, sdss, pack, width, fld) |
| |
| #endif // SUBZERO_SRC_ICEINSTX8664_DEF |
