Fix EmitImageWrite using wrong active lane mask
EmiteImageWrite() was writing to inactive lanes, which was causing
several tests to fail. state->activeStoresAndAtomicsMask() returns
the proper lane mask.
Bug: b/184063472
Tests: dEQP-VK.glsl.builtin_var.fragdepth.*
Change-Id: I24882cb963ed30052c4774318e1267041c89ee02
Reviewed-on: https://swiftshader-review.googlesource.com/c/SwiftShader/+/54368
Tested-by: Sean Risser <srisser@google.com>
Commit-Queue: Sean Risser <srisser@google.com>
Reviewed-by: Alexis Hétu <sugoi@google.com>
Reviewed-by: Nicolas Capens <nicolascapens@google.com>
diff --git a/src/Pipeline/SpirvShaderImage.cpp b/src/Pipeline/SpirvShaderImage.cpp
index 3b22014..067eaea 100644
--- a/src/Pipeline/SpirvShaderImage.cpp
+++ b/src/Pipeline/SpirvShaderImage.cpp
@@ -1234,14 +1234,14 @@
{
for(auto i = 0; i < texelSize / 4; i++)
{
- texelPtr.Store(packed[i], robustness, state->activeLaneMask());
+ texelPtr.Store(packed[i], robustness, state->activeStoresAndAtomicsMask());
texelPtr += sizeof(float);
}
}
else if(texelSize == 2)
{
SIMD::Int offsets = texelPtr.offsets();
- SIMD::Int mask = state->activeLaneMask() & texelPtr.isInBounds(2, robustness);
+ SIMD::Int mask = state->activeStoresAndAtomicsMask() & texelPtr.isInBounds(2, robustness);
for(int i = 0; i < SIMD::Width; i++)
{
@@ -1254,7 +1254,7 @@
else if(texelSize == 1)
{
SIMD::Int offsets = texelPtr.offsets();
- SIMD::Int mask = state->activeLaneMask() & texelPtr.isInBounds(1, robustness);
+ SIMD::Int mask = state->activeStoresAndAtomicsMask() & texelPtr.isInBounds(1, robustness);
for(int i = 0; i < SIMD::Width; i++)
{
