| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Target Register Enum Values *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| |
| #ifdef GET_REGINFO_ENUM |
| #undef GET_REGINFO_ENUM |
| |
| namespace llvm { |
| |
| class MCRegisterClass; |
| extern const MCRegisterClass ARMMCRegisterClasses[]; |
| |
| namespace ARM { |
| enum { |
| NoRegister, |
| APSR = 1, |
| APSR_NZCV = 2, |
| CPSR = 3, |
| FPCXTNS = 4, |
| FPCXTS = 5, |
| FPEXC = 6, |
| FPINST = 7, |
| FPSCR = 8, |
| FPSCR_NZCV = 9, |
| FPSCR_NZCVQC = 10, |
| FPSID = 11, |
| ITSTATE = 12, |
| LR = 13, |
| PC = 14, |
| SP = 15, |
| SPSR = 16, |
| VPR = 17, |
| ZR = 18, |
| D0 = 19, |
| D1 = 20, |
| D2 = 21, |
| D3 = 22, |
| D4 = 23, |
| D5 = 24, |
| D6 = 25, |
| D7 = 26, |
| D8 = 27, |
| D9 = 28, |
| D10 = 29, |
| D11 = 30, |
| D12 = 31, |
| D13 = 32, |
| D14 = 33, |
| D15 = 34, |
| D16 = 35, |
| D17 = 36, |
| D18 = 37, |
| D19 = 38, |
| D20 = 39, |
| D21 = 40, |
| D22 = 41, |
| D23 = 42, |
| D24 = 43, |
| D25 = 44, |
| D26 = 45, |
| D27 = 46, |
| D28 = 47, |
| D29 = 48, |
| D30 = 49, |
| D31 = 50, |
| FPINST2 = 51, |
| MVFR0 = 52, |
| MVFR1 = 53, |
| MVFR2 = 54, |
| P0 = 55, |
| Q0 = 56, |
| Q1 = 57, |
| Q2 = 58, |
| Q3 = 59, |
| Q4 = 60, |
| Q5 = 61, |
| Q6 = 62, |
| Q7 = 63, |
| Q8 = 64, |
| Q9 = 65, |
| Q10 = 66, |
| Q11 = 67, |
| Q12 = 68, |
| Q13 = 69, |
| Q14 = 70, |
| Q15 = 71, |
| R0 = 72, |
| R1 = 73, |
| R2 = 74, |
| R3 = 75, |
| R4 = 76, |
| R5 = 77, |
| R6 = 78, |
| R7 = 79, |
| R8 = 80, |
| R9 = 81, |
| R10 = 82, |
| R11 = 83, |
| R12 = 84, |
| S0 = 85, |
| S1 = 86, |
| S2 = 87, |
| S3 = 88, |
| S4 = 89, |
| S5 = 90, |
| S6 = 91, |
| S7 = 92, |
| S8 = 93, |
| S9 = 94, |
| S10 = 95, |
| S11 = 96, |
| S12 = 97, |
| S13 = 98, |
| S14 = 99, |
| S15 = 100, |
| S16 = 101, |
| S17 = 102, |
| S18 = 103, |
| S19 = 104, |
| S20 = 105, |
| S21 = 106, |
| S22 = 107, |
| S23 = 108, |
| S24 = 109, |
| S25 = 110, |
| S26 = 111, |
| S27 = 112, |
| S28 = 113, |
| S29 = 114, |
| S30 = 115, |
| S31 = 116, |
| D0_D2 = 117, |
| D1_D3 = 118, |
| D2_D4 = 119, |
| D3_D5 = 120, |
| D4_D6 = 121, |
| D5_D7 = 122, |
| D6_D8 = 123, |
| D7_D9 = 124, |
| D8_D10 = 125, |
| D9_D11 = 126, |
| D10_D12 = 127, |
| D11_D13 = 128, |
| D12_D14 = 129, |
| D13_D15 = 130, |
| D14_D16 = 131, |
| D15_D17 = 132, |
| D16_D18 = 133, |
| D17_D19 = 134, |
| D18_D20 = 135, |
| D19_D21 = 136, |
| D20_D22 = 137, |
| D21_D23 = 138, |
| D22_D24 = 139, |
| D23_D25 = 140, |
| D24_D26 = 141, |
| D25_D27 = 142, |
| D26_D28 = 143, |
| D27_D29 = 144, |
| D28_D30 = 145, |
| D29_D31 = 146, |
| Q0_Q1 = 147, |
| Q1_Q2 = 148, |
| Q2_Q3 = 149, |
| Q3_Q4 = 150, |
| Q4_Q5 = 151, |
| Q5_Q6 = 152, |
| Q6_Q7 = 153, |
| Q7_Q8 = 154, |
| Q8_Q9 = 155, |
| Q9_Q10 = 156, |
| Q10_Q11 = 157, |
| Q11_Q12 = 158, |
| Q12_Q13 = 159, |
| Q13_Q14 = 160, |
| Q14_Q15 = 161, |
| Q0_Q1_Q2_Q3 = 162, |
| Q1_Q2_Q3_Q4 = 163, |
| Q2_Q3_Q4_Q5 = 164, |
| Q3_Q4_Q5_Q6 = 165, |
| Q4_Q5_Q6_Q7 = 166, |
| Q5_Q6_Q7_Q8 = 167, |
| Q6_Q7_Q8_Q9 = 168, |
| Q7_Q8_Q9_Q10 = 169, |
| Q8_Q9_Q10_Q11 = 170, |
| Q9_Q10_Q11_Q12 = 171, |
| Q10_Q11_Q12_Q13 = 172, |
| Q11_Q12_Q13_Q14 = 173, |
| Q12_Q13_Q14_Q15 = 174, |
| R0_R1 = 175, |
| R2_R3 = 176, |
| R4_R5 = 177, |
| R6_R7 = 178, |
| R8_R9 = 179, |
| R10_R11 = 180, |
| R12_SP = 181, |
| D0_D1_D2 = 182, |
| D1_D2_D3 = 183, |
| D2_D3_D4 = 184, |
| D3_D4_D5 = 185, |
| D4_D5_D6 = 186, |
| D5_D6_D7 = 187, |
| D6_D7_D8 = 188, |
| D7_D8_D9 = 189, |
| D8_D9_D10 = 190, |
| D9_D10_D11 = 191, |
| D10_D11_D12 = 192, |
| D11_D12_D13 = 193, |
| D12_D13_D14 = 194, |
| D13_D14_D15 = 195, |
| D14_D15_D16 = 196, |
| D15_D16_D17 = 197, |
| D16_D17_D18 = 198, |
| D17_D18_D19 = 199, |
| D18_D19_D20 = 200, |
| D19_D20_D21 = 201, |
| D20_D21_D22 = 202, |
| D21_D22_D23 = 203, |
| D22_D23_D24 = 204, |
| D23_D24_D25 = 205, |
| D24_D25_D26 = 206, |
| D25_D26_D27 = 207, |
| D26_D27_D28 = 208, |
| D27_D28_D29 = 209, |
| D28_D29_D30 = 210, |
| D29_D30_D31 = 211, |
| D0_D2_D4 = 212, |
| D1_D3_D5 = 213, |
| D2_D4_D6 = 214, |
| D3_D5_D7 = 215, |
| D4_D6_D8 = 216, |
| D5_D7_D9 = 217, |
| D6_D8_D10 = 218, |
| D7_D9_D11 = 219, |
| D8_D10_D12 = 220, |
| D9_D11_D13 = 221, |
| D10_D12_D14 = 222, |
| D11_D13_D15 = 223, |
| D12_D14_D16 = 224, |
| D13_D15_D17 = 225, |
| D14_D16_D18 = 226, |
| D15_D17_D19 = 227, |
| D16_D18_D20 = 228, |
| D17_D19_D21 = 229, |
| D18_D20_D22 = 230, |
| D19_D21_D23 = 231, |
| D20_D22_D24 = 232, |
| D21_D23_D25 = 233, |
| D22_D24_D26 = 234, |
| D23_D25_D27 = 235, |
| D24_D26_D28 = 236, |
| D25_D27_D29 = 237, |
| D26_D28_D30 = 238, |
| D27_D29_D31 = 239, |
| D0_D2_D4_D6 = 240, |
| D1_D3_D5_D7 = 241, |
| D2_D4_D6_D8 = 242, |
| D3_D5_D7_D9 = 243, |
| D4_D6_D8_D10 = 244, |
| D5_D7_D9_D11 = 245, |
| D6_D8_D10_D12 = 246, |
| D7_D9_D11_D13 = 247, |
| D8_D10_D12_D14 = 248, |
| D9_D11_D13_D15 = 249, |
| D10_D12_D14_D16 = 250, |
| D11_D13_D15_D17 = 251, |
| D12_D14_D16_D18 = 252, |
| D13_D15_D17_D19 = 253, |
| D14_D16_D18_D20 = 254, |
| D15_D17_D19_D21 = 255, |
| D16_D18_D20_D22 = 256, |
| D17_D19_D21_D23 = 257, |
| D18_D20_D22_D24 = 258, |
| D19_D21_D23_D25 = 259, |
| D20_D22_D24_D26 = 260, |
| D21_D23_D25_D27 = 261, |
| D22_D24_D26_D28 = 262, |
| D23_D25_D27_D29 = 263, |
| D24_D26_D28_D30 = 264, |
| D25_D27_D29_D31 = 265, |
| D1_D2 = 266, |
| D3_D4 = 267, |
| D5_D6 = 268, |
| D7_D8 = 269, |
| D9_D10 = 270, |
| D11_D12 = 271, |
| D13_D14 = 272, |
| D15_D16 = 273, |
| D17_D18 = 274, |
| D19_D20 = 275, |
| D21_D22 = 276, |
| D23_D24 = 277, |
| D25_D26 = 278, |
| D27_D28 = 279, |
| D29_D30 = 280, |
| D1_D2_D3_D4 = 281, |
| D3_D4_D5_D6 = 282, |
| D5_D6_D7_D8 = 283, |
| D7_D8_D9_D10 = 284, |
| D9_D10_D11_D12 = 285, |
| D11_D12_D13_D14 = 286, |
| D13_D14_D15_D16 = 287, |
| D15_D16_D17_D18 = 288, |
| D17_D18_D19_D20 = 289, |
| D19_D20_D21_D22 = 290, |
| D21_D22_D23_D24 = 291, |
| D23_D24_D25_D26 = 292, |
| D25_D26_D27_D28 = 293, |
| D27_D28_D29_D30 = 294, |
| NUM_TARGET_REGS // 295 |
| }; |
| } // end namespace ARM |
| |
| // Register classes |
| |
| namespace ARM { |
| enum { |
| HPRRegClassID = 0, |
| FPWithVPRRegClassID = 1, |
| SPRRegClassID = 2, |
| FPWithVPR_with_ssub_0RegClassID = 3, |
| GPRRegClassID = 4, |
| GPRwithAPSRRegClassID = 5, |
| GPRwithZRRegClassID = 6, |
| SPR_8RegClassID = 7, |
| GPRnopcRegClassID = 8, |
| GPRwithAPSRnospRegClassID = 9, |
| GPRwithZRnospRegClassID = 10, |
| rGPRRegClassID = 11, |
| tGPRwithpcRegClassID = 12, |
| FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID = 13, |
| hGPRRegClassID = 14, |
| tGPRRegClassID = 15, |
| tGPREvenRegClassID = 16, |
| GPRnopc_and_hGPRRegClassID = 17, |
| GPRwithAPSRnosp_and_hGPRRegClassID = 18, |
| tGPROddRegClassID = 19, |
| tcGPRRegClassID = 20, |
| hGPR_and_tGPREvenRegClassID = 21, |
| tGPR_and_tGPREvenRegClassID = 22, |
| tGPR_and_tGPROddRegClassID = 23, |
| tGPR_and_tcGPRRegClassID = 24, |
| tGPREven_and_tcGPRRegClassID = 25, |
| hGPR_and_tGPROddRegClassID = 26, |
| tGPREven_and_tGPR_and_tcGPRRegClassID = 27, |
| tGPROdd_and_tcGPRRegClassID = 28, |
| CCRRegClassID = 29, |
| GPRlrRegClassID = 30, |
| GPRspRegClassID = 31, |
| VCCRRegClassID = 32, |
| cl_FPSCR_NZCVRegClassID = 33, |
| hGPR_and_tGPRwithpcRegClassID = 34, |
| hGPR_and_tcGPRRegClassID = 35, |
| DPRRegClassID = 36, |
| DPR_VFP2RegClassID = 37, |
| DPR_8RegClassID = 38, |
| GPRPairRegClassID = 39, |
| GPRPairnospRegClassID = 40, |
| GPRPair_with_gsub_0_in_tGPRRegClassID = 41, |
| GPRPair_with_gsub_0_in_hGPRRegClassID = 42, |
| GPRPair_with_gsub_0_in_tcGPRRegClassID = 43, |
| GPRPair_with_gsub_1_in_tcGPRRegClassID = 44, |
| GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClassID = 45, |
| GPRPair_with_gsub_1_in_GPRspRegClassID = 46, |
| DPairSpcRegClassID = 47, |
| DPairSpc_with_ssub_0RegClassID = 48, |
| DPairSpc_with_ssub_4RegClassID = 49, |
| DPairSpc_with_dsub_0_in_DPR_8RegClassID = 50, |
| DPairSpc_with_dsub_2_in_DPR_8RegClassID = 51, |
| DPairRegClassID = 52, |
| DPair_with_ssub_0RegClassID = 53, |
| QPRRegClassID = 54, |
| DPair_with_ssub_2RegClassID = 55, |
| DPair_with_dsub_0_in_DPR_8RegClassID = 56, |
| MQPRRegClassID = 57, |
| QPR_VFP2RegClassID = 58, |
| DPair_with_dsub_1_in_DPR_8RegClassID = 59, |
| QPR_8RegClassID = 60, |
| DTripleRegClassID = 61, |
| DTripleSpcRegClassID = 62, |
| DTripleSpc_with_ssub_0RegClassID = 63, |
| DTriple_with_ssub_0RegClassID = 64, |
| DTriple_with_qsub_0_in_QPRRegClassID = 65, |
| DTriple_with_ssub_2RegClassID = 66, |
| DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 67, |
| DTripleSpc_with_ssub_4RegClassID = 68, |
| DTriple_with_ssub_4RegClassID = 69, |
| DTripleSpc_with_ssub_8RegClassID = 70, |
| DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 71, |
| DTriple_with_dsub_0_in_DPR_8RegClassID = 72, |
| DTriple_with_qsub_0_in_MQPRRegClassID = 73, |
| DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 74, |
| DTriple_with_dsub_1_in_DPR_8RegClassID = 75, |
| DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 76, |
| DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID = 77, |
| DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 78, |
| DTriple_with_dsub_2_in_DPR_8RegClassID = 79, |
| DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 80, |
| DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 81, |
| DTriple_with_qsub_0_in_QPR_8RegClassID = 82, |
| DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRRegClassID = 83, |
| DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 84, |
| DQuadSpcRegClassID = 85, |
| DQuadSpc_with_ssub_0RegClassID = 86, |
| DQuadSpc_with_ssub_4RegClassID = 87, |
| DQuadSpc_with_ssub_8RegClassID = 88, |
| DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 89, |
| DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 90, |
| DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 91, |
| DQuadRegClassID = 92, |
| DQuad_with_ssub_0RegClassID = 93, |
| DQuad_with_ssub_2RegClassID = 94, |
| QQPRRegClassID = 95, |
| DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 96, |
| DQuad_with_ssub_4RegClassID = 97, |
| DQuad_with_ssub_6RegClassID = 98, |
| DQuad_with_dsub_0_in_DPR_8RegClassID = 99, |
| DQuad_with_qsub_0_in_MQPRRegClassID = 100, |
| DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 101, |
| DQuad_with_dsub_1_in_DPR_8RegClassID = 102, |
| DQuad_with_qsub_1_in_MQPRRegClassID = 103, |
| DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 104, |
| DQuad_with_dsub_2_in_DPR_8RegClassID = 105, |
| DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 106, |
| DQuad_with_dsub_3_in_DPR_8RegClassID = 107, |
| DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 108, |
| DQuad_with_qsub_0_in_QPR_8RegClassID = 109, |
| DQuad_with_qsub_1_in_QPR_8RegClassID = 110, |
| DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 111, |
| DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 112, |
| QQQQPRRegClassID = 113, |
| QQQQPR_with_ssub_0RegClassID = 114, |
| QQQQPR_with_ssub_4RegClassID = 115, |
| QQQQPR_with_ssub_8RegClassID = 116, |
| QQQQPR_with_ssub_12RegClassID = 117, |
| QQQQPR_with_dsub_0_in_DPR_8RegClassID = 118, |
| QQQQPR_with_dsub_2_in_DPR_8RegClassID = 119, |
| QQQQPR_with_dsub_4_in_DPR_8RegClassID = 120, |
| QQQQPR_with_dsub_6_in_DPR_8RegClassID = 121, |
| |
| }; |
| } // end namespace ARM |
| |
| |
| // Register alternate name indices |
| |
| namespace ARM { |
| enum { |
| NoRegAltName, // 0 |
| RegNamesRaw, // 1 |
| NUM_TARGET_REG_ALT_NAMES = 2 |
| }; |
| } // end namespace ARM |
| |
| |
| // Subregister indices |
| |
| namespace ARM { |
| enum { |
| NoSubRegister, |
| dsub_0, // 1 |
| dsub_1, // 2 |
| dsub_2, // 3 |
| dsub_3, // 4 |
| dsub_4, // 5 |
| dsub_5, // 6 |
| dsub_6, // 7 |
| dsub_7, // 8 |
| gsub_0, // 9 |
| gsub_1, // 10 |
| qqsub_0, // 11 |
| qqsub_1, // 12 |
| qsub_0, // 13 |
| qsub_1, // 14 |
| qsub_2, // 15 |
| qsub_3, // 16 |
| ssub_0, // 17 |
| ssub_1, // 18 |
| ssub_2, // 19 |
| ssub_3, // 20 |
| ssub_4, // 21 |
| ssub_5, // 22 |
| ssub_6, // 23 |
| ssub_7, // 24 |
| ssub_8, // 25 |
| ssub_9, // 26 |
| ssub_10, // 27 |
| ssub_11, // 28 |
| ssub_12, // 29 |
| ssub_13, // 30 |
| dsub_7_then_ssub_0, // 31 |
| dsub_7_then_ssub_1, // 32 |
| ssub_0_ssub_1_ssub_4_ssub_5, // 33 |
| ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5, // 34 |
| ssub_2_ssub_3_ssub_6_ssub_7, // 35 |
| ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, // 36 |
| ssub_2_ssub_3_ssub_4_ssub_5, // 37 |
| ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9, // 38 |
| ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, // 39 |
| ssub_2_ssub_3_ssub_6_ssub_7_dsub_5, // 40 |
| ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7, // 41 |
| ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, // 42 |
| ssub_4_ssub_5_ssub_8_ssub_9, // 43 |
| ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, // 44 |
| ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, // 45 |
| ssub_6_ssub_7_dsub_5, // 46 |
| ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, // 47 |
| ssub_6_ssub_7_dsub_5_dsub_7, // 48 |
| ssub_6_ssub_7_ssub_8_ssub_9, // 49 |
| ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 50 |
| ssub_8_ssub_9_ssub_12_ssub_13, // 51 |
| ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 52 |
| dsub_5_dsub_7, // 53 |
| dsub_5_ssub_12_ssub_13_dsub_7, // 54 |
| dsub_5_ssub_12_ssub_13, // 55 |
| ssub_4_ssub_5_ssub_6_ssub_7_qsub_2, // 56 |
| NUM_TARGET_SUBREGS |
| }; |
| } // end namespace ARM |
| |
| } // end namespace llvm |
| |
| #endif // GET_REGINFO_ENUM |
| |
| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* MC Register Information *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| |
| #ifdef GET_REGINFO_MC_DESC |
| #undef GET_REGINFO_MC_DESC |
| |
| namespace llvm { |
| |
| extern const MCPhysReg ARMRegDiffLists[] = { |
| /* 0 */ 64905, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, |
| /* 17 */ 37, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, |
| /* 32 */ 41, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, |
| /* 45 */ 45, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, |
| /* 56 */ 64431, 1, 1, 1, 1, 1, 1, 1, 0, |
| /* 65 */ 64965, 1, 1, 1, 1, 1, 1, 1, 0, |
| /* 74 */ 65245, 1, 1, 1, 1, 1, 1, 1, 0, |
| /* 83 */ 43, 1, 1, 1, 1, 1, 1, 0, |
| /* 91 */ 45, 1, 1, 1, 1, 1, 0, |
| /* 98 */ 65189, 1, 1, 1, 1, 1, 0, |
| /* 105 */ 45, 1, 1, 1, 1, 0, |
| /* 111 */ 47, 1, 1, 1, 1, 0, |
| /* 117 */ 47, 1, 1, 1, 0, |
| /* 122 */ 64491, 1, 1, 1, 0, |
| /* 127 */ 65008, 1, 1, 1, 0, |
| /* 132 */ 65275, 1, 1, 1, 0, |
| /* 137 */ 65329, 1, 1, 1, 0, |
| /* 142 */ 13, 1, 1, 0, |
| /* 146 */ 47, 1, 1, 0, |
| /* 150 */ 65387, 1, 1, 0, |
| /* 154 */ 137, 65489, 48, 65489, 12, 121, 65416, 1, 1, 0, |
| /* 164 */ 136, 65490, 47, 65490, 12, 121, 65416, 1, 1, 0, |
| /* 174 */ 135, 65491, 46, 65491, 12, 121, 65416, 1, 1, 0, |
| /* 184 */ 134, 65492, 45, 65492, 12, 121, 65416, 1, 1, 0, |
| /* 194 */ 133, 65493, 44, 65493, 12, 121, 65416, 1, 1, 0, |
| /* 204 */ 132, 65494, 43, 65494, 12, 121, 65416, 1, 1, 0, |
| /* 214 */ 131, 65495, 42, 65495, 12, 121, 65416, 1, 1, 0, |
| /* 224 */ 130, 65496, 41, 65496, 12, 121, 65416, 1, 1, 0, |
| /* 234 */ 129, 65497, 40, 65497, 12, 121, 65416, 1, 1, 0, |
| /* 244 */ 128, 65498, 39, 65498, 12, 121, 65416, 1, 1, 0, |
| /* 254 */ 65489, 133, 65416, 1, 1, 0, |
| /* 260 */ 65490, 133, 65416, 1, 1, 0, |
| /* 266 */ 65491, 133, 65416, 1, 1, 0, |
| /* 272 */ 65492, 133, 65416, 1, 1, 0, |
| /* 278 */ 65493, 133, 65416, 1, 1, 0, |
| /* 284 */ 65494, 133, 65416, 1, 1, 0, |
| /* 290 */ 65495, 133, 65416, 1, 1, 0, |
| /* 296 */ 65496, 133, 65416, 1, 1, 0, |
| /* 302 */ 65497, 133, 65416, 1, 1, 0, |
| /* 308 */ 65498, 133, 65416, 1, 1, 0, |
| /* 314 */ 127, 65499, 38, 65499, 133, 65416, 1, 1, 0, |
| /* 323 */ 65073, 1, 3, 1, 3, 1, 3, 1, 0, |
| /* 332 */ 65129, 1, 3, 1, 3, 1, 0, |
| /* 339 */ 65319, 1, 3, 1, 0, |
| /* 344 */ 13, 1, 0, |
| /* 347 */ 14, 1, 0, |
| /* 350 */ 66, 1, 0, |
| /* 353 */ 65499, 66, 1, 65470, 67, 1, 0, |
| /* 360 */ 65290, 67, 1, 65469, 68, 1, 0, |
| /* 367 */ 65438, 66, 1, 65471, 68, 1, 0, |
| /* 374 */ 65500, 68, 1, 65468, 69, 1, 0, |
| /* 381 */ 65438, 67, 1, 65470, 69, 1, 0, |
| /* 388 */ 65291, 69, 1, 65467, 70, 1, 0, |
| /* 395 */ 65438, 68, 1, 65469, 70, 1, 0, |
| /* 402 */ 65501, 70, 1, 65466, 71, 1, 0, |
| /* 409 */ 65438, 69, 1, 65468, 71, 1, 0, |
| /* 416 */ 65292, 71, 1, 65465, 72, 1, 0, |
| /* 423 */ 65438, 70, 1, 65467, 72, 1, 0, |
| /* 430 */ 65502, 72, 1, 65464, 73, 1, 0, |
| /* 437 */ 65438, 71, 1, 65466, 73, 1, 0, |
| /* 444 */ 65293, 73, 1, 65463, 74, 1, 0, |
| /* 451 */ 65438, 72, 1, 65465, 74, 1, 0, |
| /* 458 */ 65503, 74, 1, 65462, 75, 1, 0, |
| /* 465 */ 65438, 73, 1, 65464, 75, 1, 0, |
| /* 472 */ 65294, 75, 1, 65461, 76, 1, 0, |
| /* 479 */ 65438, 74, 1, 65463, 76, 1, 0, |
| /* 486 */ 65504, 76, 1, 65460, 77, 1, 0, |
| /* 493 */ 65438, 75, 1, 65462, 77, 1, 0, |
| /* 500 */ 65295, 77, 1, 65459, 78, 1, 0, |
| /* 507 */ 65438, 76, 1, 65461, 78, 1, 0, |
| /* 514 */ 65505, 78, 1, 65458, 79, 1, 0, |
| /* 521 */ 65438, 77, 1, 65460, 79, 1, 0, |
| /* 528 */ 65296, 79, 1, 65457, 80, 1, 0, |
| /* 535 */ 65438, 78, 1, 65459, 80, 1, 0, |
| /* 542 */ 65506, 80, 1, 65456, 81, 1, 0, |
| /* 549 */ 65438, 79, 1, 65458, 81, 1, 0, |
| /* 556 */ 65038, 1, 0, |
| /* 559 */ 65256, 1, 0, |
| /* 562 */ 65298, 1, 0, |
| /* 565 */ 65299, 1, 0, |
| /* 568 */ 65300, 1, 0, |
| /* 571 */ 65301, 1, 0, |
| /* 574 */ 65302, 1, 0, |
| /* 577 */ 65303, 1, 0, |
| /* 580 */ 65304, 1, 0, |
| /* 583 */ 65453, 1, 65499, 133, 1, 65416, 1, 0, |
| /* 591 */ 138, 65488, 49, 65488, 12, 121, 65416, 1, 0, |
| /* 600 */ 65488, 13, 121, 65416, 1, 0, |
| /* 606 */ 65489, 13, 121, 65416, 1, 0, |
| /* 612 */ 65490, 13, 121, 65416, 1, 0, |
| /* 618 */ 65491, 13, 121, 65416, 1, 0, |
| /* 624 */ 65492, 13, 121, 65416, 1, 0, |
| /* 630 */ 65493, 13, 121, 65416, 1, 0, |
| /* 636 */ 65494, 13, 121, 65416, 1, 0, |
| /* 642 */ 65495, 13, 121, 65416, 1, 0, |
| /* 648 */ 65496, 13, 121, 65416, 1, 0, |
| /* 654 */ 65497, 13, 121, 65416, 1, 0, |
| /* 660 */ 65498, 13, 121, 65416, 1, 0, |
| /* 666 */ 65464, 1, 65488, 133, 65416, 121, 65416, 1, 0, |
| /* 675 */ 65463, 1, 65489, 133, 65416, 121, 65416, 1, 0, |
| /* 684 */ 65462, 1, 65490, 133, 65416, 121, 65416, 1, 0, |
| /* 693 */ 65461, 1, 65491, 133, 65416, 121, 65416, 1, 0, |
| /* 702 */ 65460, 1, 65492, 133, 65416, 121, 65416, 1, 0, |
| /* 711 */ 65459, 1, 65493, 133, 65416, 121, 65416, 1, 0, |
| /* 720 */ 65458, 1, 65494, 133, 65416, 121, 65416, 1, 0, |
| /* 729 */ 65457, 1, 65495, 133, 65416, 121, 65416, 1, 0, |
| /* 738 */ 65456, 1, 65496, 133, 65416, 121, 65416, 1, 0, |
| /* 747 */ 65455, 1, 65497, 133, 65416, 121, 65416, 1, 0, |
| /* 756 */ 65454, 1, 65498, 133, 65416, 121, 65416, 1, 0, |
| /* 765 */ 65488, 133, 65416, 1, 0, |
| /* 770 */ 65499, 134, 65416, 1, 0, |
| /* 775 */ 126, 65500, 37, 65500, 133, 65417, 1, 0, |
| /* 783 */ 65433, 1, 0, |
| /* 786 */ 65434, 1, 0, |
| /* 789 */ 65435, 1, 0, |
| /* 792 */ 65436, 1, 0, |
| /* 795 */ 65437, 1, 0, |
| /* 798 */ 65438, 1, 0, |
| /* 801 */ 65457, 1, 0, |
| /* 804 */ 65507, 1, 0, |
| /* 807 */ 65508, 1, 0, |
| /* 810 */ 65509, 1, 0, |
| /* 813 */ 65510, 1, 0, |
| /* 816 */ 65511, 1, 0, |
| /* 819 */ 65512, 1, 0, |
| /* 822 */ 65513, 1, 0, |
| /* 825 */ 65514, 1, 0, |
| /* 828 */ 65515, 1, 0, |
| /* 831 */ 65073, 1, 3, 1, 3, 1, 2, 0, |
| /* 839 */ 65129, 1, 3, 1, 2, 0, |
| /* 845 */ 65319, 1, 2, 0, |
| /* 849 */ 65073, 1, 3, 1, 2, 2, 0, |
| /* 856 */ 65129, 1, 2, 2, 0, |
| /* 861 */ 65073, 1, 2, 2, 2, 0, |
| /* 867 */ 65329, 2, 2, 2, 0, |
| /* 872 */ 65073, 1, 3, 2, 2, 0, |
| /* 878 */ 65357, 2, 2, 0, |
| /* 882 */ 65073, 1, 3, 1, 3, 2, 0, |
| /* 889 */ 65129, 1, 3, 2, 0, |
| /* 894 */ 65343, 77, 1, 65460, 79, 1, 65458, 81, 1, 12, 2, 0, |
| /* 906 */ 65343, 76, 1, 65461, 78, 1, 65459, 80, 1, 13, 2, 0, |
| /* 918 */ 65343, 75, 1, 65462, 77, 1, 65460, 79, 1, 14, 2, 0, |
| /* 930 */ 65343, 74, 1, 65463, 76, 1, 65461, 78, 1, 15, 2, 0, |
| /* 942 */ 65343, 73, 1, 65464, 75, 1, 65462, 77, 1, 16, 2, 0, |
| /* 954 */ 65343, 72, 1, 65465, 74, 1, 65463, 76, 1, 17, 2, 0, |
| /* 966 */ 65343, 71, 1, 65466, 73, 1, 65464, 75, 1, 18, 2, 0, |
| /* 978 */ 65343, 70, 1, 65467, 72, 1, 65465, 74, 1, 19, 2, 0, |
| /* 990 */ 65343, 69, 1, 65468, 71, 1, 65466, 73, 1, 20, 2, 0, |
| /* 1002 */ 65343, 68, 1, 65469, 70, 1, 65467, 72, 1, 21, 2, 0, |
| /* 1014 */ 65343, 67, 1, 65470, 69, 1, 65468, 71, 1, 22, 2, 0, |
| /* 1026 */ 65343, 66, 1, 65471, 68, 1, 65469, 70, 1, 23, 2, 0, |
| /* 1038 */ 65343, 2, 2, 94, 2, 0, |
| /* 1044 */ 65343, 81, 1, 65456, 2, 94, 2, 0, |
| /* 1052 */ 65343, 80, 1, 65457, 2, 94, 2, 0, |
| /* 1060 */ 65343, 79, 1, 65458, 81, 1, 65456, 94, 2, 0, |
| /* 1070 */ 65343, 78, 1, 65459, 80, 1, 65457, 94, 2, 0, |
| /* 1080 */ 65438, 2, 0, |
| /* 1083 */ 65452, 2, 0, |
| /* 1086 */ 65073, 1, 3, 1, 3, 1, 3, 0, |
| /* 1094 */ 65129, 1, 3, 1, 3, 0, |
| /* 1100 */ 65319, 1, 3, 0, |
| /* 1104 */ 7, 0, |
| /* 1106 */ 140, 65486, 13, 0, |
| /* 1110 */ 14, 0, |
| /* 1112 */ 126, 65501, 15, 0, |
| /* 1116 */ 13, 69, 0, |
| /* 1119 */ 65445, 65513, 1, 23, 65514, 1, 95, 65, 65472, 65, 69, 0, |
| /* 1131 */ 65445, 65512, 1, 24, 65513, 1, 95, 65, 65472, 65, 70, 0, |
| /* 1143 */ 65445, 65511, 1, 25, 65512, 1, 95, 65, 65472, 65, 71, 0, |
| /* 1155 */ 65445, 65510, 1, 26, 65511, 1, 95, 65, 65472, 65, 72, 0, |
| /* 1167 */ 65445, 65509, 1, 27, 65510, 1, 95, 65, 65472, 65, 73, 0, |
| /* 1179 */ 65445, 65508, 1, 28, 65509, 1, 95, 65, 65472, 65, 74, 0, |
| /* 1191 */ 65445, 65507, 1, 29, 65508, 1, 95, 65, 65472, 65, 75, 0, |
| /* 1203 */ 65445, 65506, 80, 1, 65456, 81, 1, 65484, 65507, 1, 95, 65, 65472, 65, 76, 0, |
| /* 1219 */ 65445, 65505, 78, 1, 65458, 79, 1, 65487, 65506, 80, 1, 65456, 81, 1, 13, 65, 65472, 65, 77, 0, |
| /* 1239 */ 65445, 65504, 76, 1, 65460, 77, 1, 65490, 65505, 78, 1, 65458, 79, 1, 15, 65, 65472, 65, 78, 0, |
| /* 1259 */ 65445, 65503, 74, 1, 65462, 75, 1, 65493, 65504, 76, 1, 65460, 77, 1, 17, 65, 65472, 65, 79, 0, |
| /* 1279 */ 65445, 65502, 72, 1, 65464, 73, 1, 65496, 65503, 74, 1, 65462, 75, 1, 19, 65, 65472, 65, 80, 0, |
| /* 1299 */ 65445, 65501, 70, 1, 65466, 71, 1, 65499, 65502, 72, 1, 65464, 73, 1, 21, 65, 65472, 65, 81, 0, |
| /* 1319 */ 65445, 65500, 68, 1, 65468, 69, 1, 65502, 65501, 70, 1, 65466, 71, 1, 23, 65, 65472, 65, 82, 0, |
| /* 1339 */ 65445, 65499, 66, 1, 65470, 67, 1, 65505, 65500, 68, 1, 65468, 69, 1, 25, 65, 65472, 65, 83, 0, |
| /* 1359 */ 97, 0, |
| /* 1361 */ 98, 0, |
| /* 1363 */ 99, 0, |
| /* 1365 */ 100, 0, |
| /* 1367 */ 101, 0, |
| /* 1369 */ 102, 0, |
| /* 1371 */ 103, 0, |
| /* 1373 */ 65373, 1, 1, 21, 75, 135, 0, |
| /* 1380 */ 65373, 1, 1, 22, 74, 136, 0, |
| /* 1387 */ 65373, 1, 1, 23, 73, 137, 0, |
| /* 1394 */ 65373, 1, 1, 24, 72, 138, 0, |
| /* 1401 */ 65373, 1, 1, 25, 71, 139, 0, |
| /* 1408 */ 65373, 1, 1, 26, 70, 140, 0, |
| /* 1415 */ 65373, 1, 1, 27, 69, 141, 0, |
| /* 1422 */ 65373, 80, 1, 65456, 81, 1, 65455, 28, 68, 142, 0, |
| /* 1433 */ 65373, 78, 1, 65458, 79, 1, 65457, 80, 1, 65484, 67, 143, 0, |
| /* 1446 */ 65373, 76, 1, 65460, 77, 1, 65459, 78, 1, 65487, 66, 144, 0, |
| /* 1459 */ 65373, 74, 1, 65462, 75, 1, 65461, 76, 1, 65490, 65, 145, 0, |
| /* 1472 */ 65373, 72, 1, 65464, 73, 1, 65463, 74, 1, 65493, 64, 146, 0, |
| /* 1485 */ 65373, 70, 1, 65466, 71, 1, 65465, 72, 1, 65496, 63, 147, 0, |
| /* 1498 */ 65373, 68, 1, 65468, 69, 1, 65467, 70, 1, 65499, 62, 148, 0, |
| /* 1511 */ 65373, 66, 1, 65470, 67, 1, 65469, 68, 1, 65502, 61, 149, 0, |
| /* 1524 */ 166, 0, |
| /* 1526 */ 65288, 1, 1, 1, 230, 1, 65400, 65, 65472, 65, 65396, 0, |
| /* 1538 */ 65287, 1, 1, 1, 231, 1, 65399, 65, 65472, 65, 65397, 0, |
| /* 1550 */ 65286, 1, 1, 1, 232, 1, 65398, 65, 65472, 65, 65398, 0, |
| /* 1562 */ 65285, 1, 1, 1, 233, 1, 65397, 65, 65472, 65, 65399, 0, |
| /* 1574 */ 65284, 1, 1, 1, 234, 1, 65396, 65, 65472, 65, 65400, 0, |
| /* 1586 */ 65283, 1, 1, 1, 235, 1, 65395, 65, 65472, 65, 65401, 0, |
| /* 1598 */ 65521, 65445, 65511, 1, 25, 65512, 1, 95, 65, 65472, 65, 71, 65419, 65445, 65513, 1, 23, 65514, 1, 95, 65, 65472, 65, 69, 65492, 28, 65509, 28, 28, 65386, 65, 30, 65442, 65, 30, 40, 15, 65402, 0, |
| /* 1637 */ 65521, 65445, 65510, 1, 26, 65511, 1, 95, 65, 65472, 65, 72, 65419, 65445, 65512, 1, 24, 65513, 1, 95, 65, 65472, 65, 70, 65491, 28, 65509, 28, 29, 65385, 65, 30, 65442, 65, 30, 41, 15, 65402, 0, |
| /* 1676 */ 65521, 65445, 65509, 1, 27, 65510, 1, 95, 65, 65472, 65, 73, 65419, 65445, 65511, 1, 25, 65512, 1, 95, 65, 65472, 65, 71, 65490, 28, 65509, 28, 30, 65384, 65, 30, 65442, 65, 30, 42, 15, 65402, 0, |
| /* 1715 */ 65521, 65445, 65508, 1, 28, 65509, 1, 95, 65, 65472, 65, 74, 65419, 65445, 65510, 1, 26, 65511, 1, 95, 65, 65472, 65, 72, 65489, 28, 65509, 28, 31, 65383, 65, 30, 65442, 65, 30, 43, 15, 65402, 0, |
| /* 1754 */ 65521, 65445, 65507, 1, 29, 65508, 1, 95, 65, 65472, 65, 75, 65419, 65445, 65509, 1, 27, 65510, 1, 95, 65, 65472, 65, 73, 65488, 28, 65509, 28, 32, 65382, 65, 30, 65442, 65, 30, 44, 15, 65402, 0, |
| /* 1793 */ 65521, 65445, 65506, 80, 1, 65456, 81, 1, 65484, 65507, 1, 95, 65, 65472, 65, 76, 65419, 65445, 65508, 1, 28, 65509, 1, 95, 65, 65472, 65, 74, 65487, 28, 65509, 28, 33, 65381, 65, 30, 65442, 65, 30, 45, 15, 65402, 0, |
| /* 1836 */ 65521, 65445, 65505, 78, 1, 65458, 79, 1, 65487, 65506, 80, 1, 65456, 81, 1, 13, 65, 65472, 65, 77, 65419, 65445, 65507, 1, 29, 65508, 1, 95, 65, 65472, 65, 75, 65486, 28, 65509, 28, 34, 65380, 65, 30, 65442, 65, 30, 46, 15, 65402, 0, |
| /* 1883 */ 65521, 65445, 65504, 76, 1, 65460, 77, 1, 65490, 65505, 78, 1, 65458, 79, 1, 15, 65, 65472, 65, 78, 65419, 65445, 65506, 80, 1, 65456, 81, 1, 65484, 65507, 1, 95, 65, 65472, 65, 76, 65485, 28, 65509, 28, 35, 65379, 65, 30, 65442, 65, 30, 47, 15, 65402, 0, |
| /* 1934 */ 65521, 65445, 65503, 74, 1, 65462, 75, 1, 65493, 65504, 76, 1, 65460, 77, 1, 17, 65, 65472, 65, 79, 65419, 65445, 65505, 78, 1, 65458, 79, 1, 65487, 65506, 80, 1, 65456, 81, 1, 13, 65, 65472, 65, 77, 65484, 28, 65509, 28, 36, 65378, 65, 30, 65442, 65, 30, 48, 15, 65402, 0, |
| /* 1989 */ 65521, 65445, 65502, 72, 1, 65464, 73, 1, 65496, 65503, 74, 1, 65462, 75, 1, 19, 65, 65472, 65, 80, 65419, 65445, 65504, 76, 1, 65460, 77, 1, 65490, 65505, 78, 1, 65458, 79, 1, 15, 65, 65472, 65, 78, 65483, 28, 65509, 28, 37, 65377, 65, 30, 65442, 65, 30, 49, 15, 65402, 0, |
| /* 2044 */ 65521, 65445, 65501, 70, 1, 65466, 71, 1, 65499, 65502, 72, 1, 65464, 73, 1, 21, 65, 65472, 65, 81, 65419, 65445, 65503, 74, 1, 65462, 75, 1, 65493, 65504, 76, 1, 65460, 77, 1, 17, 65, 65472, 65, 79, 65482, 28, 65509, 28, 38, 65376, 65, 30, 65442, 65, 30, 50, 15, 65402, 0, |
| /* 2099 */ 65521, 65445, 65500, 68, 1, 65468, 69, 1, 65502, 65501, 70, 1, 65466, 71, 1, 23, 65, 65472, 65, 82, 65419, 65445, 65502, 72, 1, 65464, 73, 1, 65496, 65503, 74, 1, 65462, 75, 1, 19, 65, 65472, 65, 80, 65481, 28, 65509, 28, 39, 65375, 65, 30, 65442, 65, 30, 51, 15, 65402, 0, |
| /* 2154 */ 65521, 65445, 65499, 66, 1, 65470, 67, 1, 65505, 65500, 68, 1, 65468, 69, 1, 25, 65, 65472, 65, 83, 65419, 65445, 65501, 70, 1, 65466, 71, 1, 65499, 65502, 72, 1, 65464, 73, 1, 21, 65, 65472, 65, 81, 65480, 28, 65509, 28, 40, 65374, 65, 30, 65442, 65, 30, 52, 15, 65402, 0, |
| /* 2209 */ 65282, 81, 1, 65455, 1, 1, 236, 1, 65394, 65, 65472, 65, 65402, 0, |
| /* 2223 */ 65281, 79, 1, 65457, 80, 1, 65456, 81, 1, 65455, 237, 1, 65393, 65, 65472, 65, 65403, 0, |
| /* 2241 */ 65280, 77, 1, 65459, 78, 1, 65458, 79, 1, 65457, 80, 1, 157, 1, 65392, 65, 65472, 65, 65404, 0, |
| /* 2261 */ 65279, 75, 1, 65461, 76, 1, 65460, 77, 1, 65459, 78, 1, 160, 1, 65391, 65, 65472, 65, 65405, 0, |
| /* 2281 */ 65278, 73, 1, 65463, 74, 1, 65462, 75, 1, 65461, 76, 1, 163, 1, 65390, 65, 65472, 65, 65406, 0, |
| /* 2301 */ 65277, 71, 1, 65465, 72, 1, 65464, 73, 1, 65463, 74, 1, 166, 1, 65389, 65, 65472, 65, 65407, 0, |
| /* 2321 */ 65276, 69, 1, 65467, 70, 1, 65466, 71, 1, 65465, 72, 1, 169, 1, 65388, 65, 65472, 65, 65408, 0, |
| /* 2341 */ 65275, 67, 1, 65469, 68, 1, 65468, 69, 1, 65467, 70, 1, 172, 1, 65387, 65, 65472, 65, 65409, 0, |
| /* 2361 */ 23, 73, 2, 63, 65488, 120, 65465, 1, 65487, 75, 26, 65447, 65, 26, 30, 65416, 66, 26, 29, 65416, 0, |
| /* 2382 */ 22, 74, 2, 63, 65487, 120, 65466, 1, 65486, 76, 26, 65446, 66, 26, 29, 65416, 0, |
| /* 2399 */ 65, 65487, 77, 26, 65446, 66, 26, 29, 65416, 0, |
| /* 2409 */ 23, 73, 2, 134, 65465, 1, 65487, 50, 65487, 75, 26, 31, 65416, 65, 26, 30, 65416, 0, |
| /* 2427 */ 22, 74, 135, 65466, 1, 65486, 77, 26, 30, 65416, 0, |
| /* 2438 */ 65, 65487, 77, 26, 30, 65416, 0, |
| /* 2445 */ 139, 65487, 50, 65487, 12, 121, 65416, 0, |
| /* 2453 */ 65487, 13, 121, 65416, 0, |
| /* 2458 */ 65465, 1, 65487, 133, 65416, 121, 65416, 0, |
| /* 2466 */ 65466, 1, 65486, 133, 65416, 0, |
| /* 2472 */ 65487, 133, 65416, 0, |
| /* 2476 */ 65468, 36, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0, |
| /* 2488 */ 65469, 36, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0, |
| /* 2500 */ 65, 65500, 66, 28, 40, 65417, 0, |
| /* 2507 */ 65452, 1, 65500, 134, 65417, 0, |
| /* 2513 */ 65315, 75, 1, 65462, 77, 1, 65460, 79, 1, 65458, 81, 1, 10, 95, 65443, 95, 65443, 0, |
| /* 2531 */ 65315, 74, 1, 65463, 76, 1, 65461, 78, 1, 65459, 80, 1, 11, 95, 65443, 95, 65443, 0, |
| /* 2549 */ 65315, 73, 1, 65464, 75, 1, 65462, 77, 1, 65460, 79, 1, 12, 95, 65443, 95, 65443, 0, |
| /* 2567 */ 65315, 72, 1, 65465, 74, 1, 65463, 76, 1, 65461, 78, 1, 13, 95, 65443, 95, 65443, 0, |
| /* 2585 */ 65315, 71, 1, 65466, 73, 1, 65464, 75, 1, 65462, 77, 1, 14, 95, 65443, 95, 65443, 0, |
| /* 2603 */ 65315, 70, 1, 65467, 72, 1, 65465, 74, 1, 65463, 76, 1, 15, 95, 65443, 95, 65443, 0, |
| /* 2621 */ 65315, 69, 1, 65468, 71, 1, 65466, 73, 1, 65464, 75, 1, 16, 95, 65443, 95, 65443, 0, |
| /* 2639 */ 65315, 68, 1, 65469, 70, 1, 65467, 72, 1, 65465, 74, 1, 17, 95, 65443, 95, 65443, 0, |
| /* 2657 */ 65315, 67, 1, 65470, 69, 1, 65468, 71, 1, 65466, 73, 1, 18, 95, 65443, 95, 65443, 0, |
| /* 2675 */ 65315, 66, 1, 65471, 68, 1, 65469, 70, 1, 65467, 72, 1, 19, 95, 65443, 95, 65443, 0, |
| /* 2693 */ 65315, 2, 2, 2, 92, 95, 65443, 95, 65443, 0, |
| /* 2703 */ 65315, 81, 1, 65456, 2, 2, 92, 95, 65443, 95, 65443, 0, |
| /* 2715 */ 65315, 80, 1, 65457, 2, 2, 92, 95, 65443, 95, 65443, 0, |
| /* 2727 */ 65315, 79, 1, 65458, 81, 1, 65456, 2, 92, 95, 65443, 95, 65443, 0, |
| /* 2741 */ 65315, 78, 1, 65459, 80, 1, 65457, 2, 92, 95, 65443, 95, 65443, 0, |
| /* 2755 */ 65315, 77, 1, 65460, 79, 1, 65458, 81, 1, 65456, 92, 95, 65443, 95, 65443, 0, |
| /* 2771 */ 65315, 76, 1, 65461, 78, 1, 65459, 80, 1, 65457, 92, 95, 65443, 95, 65443, 0, |
| /* 2787 */ 21, 75, 65, 65486, 78, 26, 65445, 0, |
| /* 2795 */ 24, 72, 2, 63, 65489, 120, 65464, 1, 65488, 74, 26, 65448, 64, 26, 31, 65416, 65, 26, 30, 65416, 92, 65445, 0, |
| /* 2818 */ 65, 65488, 76, 26, 65447, 65, 26, 30, 65416, 92, 65445, 0, |
| /* 2830 */ 26, 65446, 92, 65445, 0, |
| /* 2835 */ 24, 72, 2, 135, 65464, 1, 65488, 49, 65488, 74, 26, 32, 65416, 64, 26, 31, 65416, 65, 26, 65446, 0, |
| /* 2856 */ 65, 65488, 76, 26, 31, 65416, 65, 26, 65446, 0, |
| /* 2866 */ 25, 71, 2, 63, 65490, 120, 65463, 1, 65489, 73, 26, 65449, 63, 26, 32, 65416, 64, 26, 31, 65416, 91, 65446, 0, |
| /* 2889 */ 65, 65489, 75, 26, 65448, 64, 26, 31, 65416, 91, 65446, 0, |
| /* 2901 */ 25, 71, 2, 136, 65463, 1, 65489, 48, 65489, 73, 26, 33, 65416, 63, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0, |
| /* 2924 */ 65, 65489, 75, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0, |
| /* 2936 */ 26, 70, 2, 63, 65491, 120, 65462, 1, 65490, 72, 26, 65450, 62, 26, 33, 65416, 63, 26, 32, 65416, 90, 65447, 0, |
| /* 2959 */ 65, 65490, 74, 26, 65449, 63, 26, 32, 65416, 90, 65447, 0, |
| /* 2971 */ 26, 70, 2, 137, 65462, 1, 65490, 47, 65490, 72, 26, 34, 65416, 62, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0, |
| /* 2994 */ 65, 65490, 74, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0, |
| /* 3006 */ 27, 69, 2, 63, 65492, 120, 65461, 1, 65491, 71, 26, 65451, 61, 26, 34, 65416, 62, 26, 33, 65416, 89, 65448, 0, |
| /* 3029 */ 65, 65491, 73, 26, 65450, 62, 26, 33, 65416, 89, 65448, 0, |
| /* 3041 */ 27, 69, 2, 138, 65461, 1, 65491, 46, 65491, 71, 26, 35, 65416, 61, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0, |
| /* 3064 */ 65, 65491, 73, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0, |
| /* 3076 */ 28, 68, 2, 63, 65493, 120, 65460, 1, 65492, 70, 26, 65452, 60, 26, 35, 65416, 61, 26, 34, 65416, 88, 65449, 0, |
| /* 3099 */ 65, 65492, 72, 26, 65451, 61, 26, 34, 65416, 88, 65449, 0, |
| /* 3111 */ 28, 68, 2, 139, 65460, 1, 65492, 45, 65492, 70, 26, 36, 65416, 60, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0, |
| /* 3134 */ 65, 65492, 72, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0, |
| /* 3146 */ 65454, 29, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0, |
| /* 3170 */ 65455, 29, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0, |
| /* 3194 */ 65, 65493, 71, 26, 65452, 60, 26, 35, 65416, 87, 65450, 0, |
| /* 3206 */ 29, 67, 2, 140, 65459, 1, 65493, 44, 65493, 69, 26, 37, 65416, 59, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0, |
| /* 3229 */ 65, 65493, 71, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0, |
| /* 3241 */ 65456, 30, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0, |
| /* 3265 */ 65457, 30, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0, |
| /* 3289 */ 65, 65494, 70, 26, 65453, 59, 26, 36, 65416, 86, 65451, 0, |
| /* 3301 */ 65455, 30, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, |
| /* 3325 */ 65456, 30, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, |
| /* 3349 */ 65, 65494, 70, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0, |
| /* 3361 */ 65458, 31, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0, |
| /* 3385 */ 65459, 31, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0, |
| /* 3409 */ 65, 65495, 69, 26, 65454, 58, 26, 37, 65416, 85, 65452, 0, |
| /* 3421 */ 65457, 31, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, |
| /* 3445 */ 65458, 31, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, |
| /* 3469 */ 65, 65495, 69, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0, |
| /* 3481 */ 65460, 32, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0, |
| /* 3505 */ 65461, 32, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0, |
| /* 3529 */ 65, 65496, 68, 26, 65455, 57, 26, 38, 65416, 84, 65453, 0, |
| /* 3541 */ 65459, 32, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, |
| /* 3565 */ 65460, 32, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, |
| /* 3589 */ 65, 65496, 68, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0, |
| /* 3601 */ 65462, 33, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0, |
| /* 3625 */ 65463, 33, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0, |
| /* 3649 */ 65, 65497, 67, 26, 65456, 56, 26, 39, 65416, 83, 65454, 0, |
| /* 3661 */ 65461, 33, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, |
| /* 3685 */ 65462, 33, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, |
| /* 3709 */ 65, 65497, 67, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0, |
| /* 3721 */ 65297, 81, 1, 65455, 0, |
| /* 3726 */ 65464, 34, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0, |
| /* 3748 */ 65465, 34, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0, |
| /* 3770 */ 65, 65498, 66, 26, 65457, 55, 26, 40, 65416, 82, 65455, 0, |
| /* 3782 */ 65463, 34, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, |
| /* 3806 */ 65464, 34, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, |
| /* 3830 */ 65, 65498, 66, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0, |
| /* 3842 */ 65438, 81, 1, 65456, 0, |
| /* 3847 */ 65466, 35, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0, |
| /* 3866 */ 65467, 35, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0, |
| /* 3885 */ 65, 65499, 65, 2, 26, 41, 65416, 81, 65456, 0, |
| /* 3895 */ 65465, 35, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0, |
| /* 3917 */ 65466, 35, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0, |
| /* 3939 */ 65, 65499, 65, 26, 42, 65416, 54, 26, 65457, 81, 65456, 0, |
| /* 3951 */ 65438, 80, 1, 65457, 0, |
| /* 3956 */ 28, 65457, 0, |
| /* 3959 */ 65467, 36, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, |
| /* 3977 */ 65468, 36, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, |
| /* 3995 */ 65, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0, |
| /* 4005 */ 26, 65458, 80, 65457, 0, |
| /* 4010 */ 65469, 37, 61, 65, 65501, 65, 28, 65458, 0, |
| /* 4019 */ 65470, 37, 61, 65, 65501, 65, 28, 65458, 0, |
| /* 4028 */ 65373, 1, 1, 230, 65402, 65461, 0, |
| /* 4035 */ 65373, 1, 1, 231, 65401, 65462, 0, |
| /* 4042 */ 65373, 1, 1, 232, 65400, 65463, 0, |
| /* 4049 */ 65373, 1, 1, 233, 65399, 65464, 0, |
| /* 4056 */ 65373, 1, 1, 234, 65398, 65465, 0, |
| /* 4063 */ 65373, 1, 1, 235, 65397, 65466, 0, |
| /* 4070 */ 65373, 1, 1, 236, 65396, 65467, 0, |
| /* 4077 */ 65439, 65467, 0, |
| /* 4080 */ 65373, 81, 1, 65455, 1, 237, 65395, 65468, 0, |
| /* 4089 */ 65373, 79, 1, 65457, 80, 1, 65456, 81, 1, 156, 65394, 65469, 0, |
| /* 4102 */ 65373, 77, 1, 65459, 78, 1, 65458, 79, 1, 159, 65393, 65470, 0, |
| /* 4115 */ 65373, 75, 1, 65461, 76, 1, 65460, 77, 1, 162, 65392, 65471, 0, |
| /* 4128 */ 65373, 73, 1, 65463, 74, 1, 65462, 75, 1, 165, 65391, 65472, 0, |
| /* 4141 */ 65373, 71, 1, 65465, 72, 1, 65464, 73, 1, 168, 65390, 65473, 0, |
| /* 4154 */ 65373, 69, 1, 65467, 70, 1, 65466, 71, 1, 171, 65389, 65474, 0, |
| /* 4167 */ 65373, 67, 1, 65469, 68, 1, 65468, 69, 1, 174, 65388, 65475, 0, |
| /* 4180 */ 65534, 0, |
| /* 4182 */ 65535, 0, |
| }; |
| |
| extern const LaneBitmask ARMLaneMaskLists[] = { |
| /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(), |
| /* 2 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask::getAll(), |
| /* 5 */ LaneBitmask(0x00000001), LaneBitmask(0x00000002), LaneBitmask::getAll(), |
| /* 8 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask::getAll(), |
| /* 11 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(), |
| /* 16 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask::getAll(), |
| /* 20 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask::getAll(), |
| /* 23 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask::getAll(), |
| /* 28 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask::getAll(), |
| /* 35 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask::getAll(), |
| /* 39 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask::getAll(), |
| /* 42 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask::getAll(), |
| /* 48 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask::getAll(), |
| /* 53 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask::getAll(), |
| /* 57 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask::getAll(), |
| /* 66 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000300), LaneBitmask::getAll(), |
| /* 74 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(), |
| /* 81 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(), |
| /* 87 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask::getAll(), |
| /* 92 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask::getAll(), |
| /* 99 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000C00), LaneBitmask::getAll(), |
| /* 105 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask::getAll(), |
| /* 110 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask::getAll(), |
| /* 114 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00004000), LaneBitmask(0x00008000), LaneBitmask::getAll(), |
| /* 123 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x0000C000), LaneBitmask::getAll(), |
| /* 131 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(), |
| /* 138 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(), |
| /* 144 */ LaneBitmask(0x0000000C), LaneBitmask(0x000000C0), LaneBitmask(0x00000C00), LaneBitmask(0x0000C000), LaneBitmask::getAll(), |
| /* 149 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00001000), LaneBitmask(0x00002000), LaneBitmask(0x00004000), LaneBitmask(0x00008000), LaneBitmask(0x00010000), LaneBitmask(0x00020000), LaneBitmask::getAll(), |
| /* 166 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000400), LaneBitmask(0x00000800), LaneBitmask(0x00001000), LaneBitmask(0x00002000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(), |
| /* 181 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x00000040), LaneBitmask(0x00000080), LaneBitmask(0x00000100), LaneBitmask(0x00000200), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(), |
| /* 194 */ LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(), |
| /* 205 */ LaneBitmask(0x0000000C), LaneBitmask(0x00000030), LaneBitmask(0x000000C0), LaneBitmask(0x00000300), LaneBitmask(0x00000C00), LaneBitmask(0x00003000), LaneBitmask(0x0000C000), LaneBitmask(0x00030000), LaneBitmask::getAll(), |
| }; |
| |
| extern const uint16_t ARMSubRegIdxLists[] = { |
| /* 0 */ 1, 2, 0, |
| /* 3 */ 1, 17, 18, 2, 0, |
| /* 8 */ 1, 3, 0, |
| /* 11 */ 1, 17, 18, 3, 0, |
| /* 16 */ 9, 10, 0, |
| /* 19 */ 17, 18, 0, |
| /* 22 */ 1, 17, 18, 2, 19, 20, 0, |
| /* 29 */ 1, 17, 18, 3, 21, 22, 0, |
| /* 36 */ 1, 2, 3, 13, 33, 37, 0, |
| /* 43 */ 1, 17, 18, 2, 3, 13, 33, 37, 0, |
| /* 52 */ 1, 17, 18, 2, 19, 20, 3, 13, 33, 37, 0, |
| /* 63 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 13, 33, 37, 0, |
| /* 76 */ 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 0, |
| /* 88 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 0, |
| /* 104 */ 1, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0, |
| /* 116 */ 1, 17, 18, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0, |
| /* 130 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 13, 14, 33, 34, 35, 36, 37, 0, |
| /* 148 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 23, 24, 13, 14, 33, 34, 35, 36, 37, 0, |
| /* 168 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 0, |
| /* 188 */ 1, 3, 5, 33, 43, 0, |
| /* 194 */ 1, 17, 18, 3, 5, 33, 43, 0, |
| /* 202 */ 1, 17, 18, 3, 21, 22, 5, 33, 43, 0, |
| /* 212 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 33, 43, 0, |
| /* 224 */ 1, 3, 5, 7, 33, 38, 43, 45, 51, 0, |
| /* 234 */ 1, 17, 18, 3, 5, 7, 33, 38, 43, 45, 51, 0, |
| /* 246 */ 1, 17, 18, 3, 21, 22, 5, 7, 33, 38, 43, 45, 51, 0, |
| /* 260 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 33, 38, 43, 45, 51, 0, |
| /* 276 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 29, 30, 33, 38, 43, 45, 51, 0, |
| /* 294 */ 11, 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, |
| /* 333 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, |
| /* 376 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, |
| /* 423 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, |
| /* 474 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 29, 30, 8, 31, 32, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0, |
| }; |
| |
| extern const MCRegisterInfo::SubRegCoveredBits ARMSubRegIdxRanges[] = { |
| { 65535, 65535 }, |
| { 0, 64 }, // dsub_0 |
| { 64, 64 }, // dsub_1 |
| { 128, 64 }, // dsub_2 |
| { 192, 64 }, // dsub_3 |
| { 256, 64 }, // dsub_4 |
| { 320, 64 }, // dsub_5 |
| { 384, 64 }, // dsub_6 |
| { 448, 64 }, // dsub_7 |
| { 0, 32 }, // gsub_0 |
| { 32, 32 }, // gsub_1 |
| { 0, 256 }, // qqsub_0 |
| { 256, 256 }, // qqsub_1 |
| { 0, 128 }, // qsub_0 |
| { 128, 128 }, // qsub_1 |
| { 256, 128 }, // qsub_2 |
| { 384, 128 }, // qsub_3 |
| { 0, 32 }, // ssub_0 |
| { 32, 32 }, // ssub_1 |
| { 64, 32 }, // ssub_2 |
| { 96, 32 }, // ssub_3 |
| { 128, 32 }, // ssub_4 |
| { 160, 32 }, // ssub_5 |
| { 192, 32 }, // ssub_6 |
| { 224, 32 }, // ssub_7 |
| { 256, 32 }, // ssub_8 |
| { 288, 32 }, // ssub_9 |
| { 320, 32 }, // ssub_10 |
| { 352, 32 }, // ssub_11 |
| { 384, 32 }, // ssub_12 |
| { 416, 32 }, // ssub_13 |
| { 448, 32 }, // dsub_7_then_ssub_0 |
| { 480, 32 }, // dsub_7_then_ssub_1 |
| { 65535, 128 }, // ssub_0_ssub_1_ssub_4_ssub_5 |
| { 0, 192 }, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| { 65535, 128 }, // ssub_2_ssub_3_ssub_6_ssub_7 |
| { 64, 192 }, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| { 64, 128 }, // ssub_2_ssub_3_ssub_4_ssub_5 |
| { 65535, 192 }, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| { 65535, 256 }, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| { 65535, 192 }, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| { 65535, 256 }, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| { 64, 256 }, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| { 65535, 128 }, // ssub_4_ssub_5_ssub_8_ssub_9 |
| { 128, 192 }, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| { 65535, 192 }, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| { 65535, 128 }, // ssub_6_ssub_7_dsub_5 |
| { 192, 192 }, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| { 65535, 192 }, // ssub_6_ssub_7_dsub_5_dsub_7 |
| { 192, 128 }, // ssub_6_ssub_7_ssub_8_ssub_9 |
| { 192, 256 }, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| { 65535, 128 }, // ssub_8_ssub_9_ssub_12_ssub_13 |
| { 256, 192 }, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| { 65535, 128 }, // dsub_5_dsub_7 |
| { 320, 192 }, // dsub_5_ssub_12_ssub_13_dsub_7 |
| { 320, 128 }, // dsub_5_ssub_12_ssub_13 |
| { 128, 256 }, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }; |
| |
| extern const char ARMRegStrings[] = { |
| /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0, |
| /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0, |
| /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0, |
| /* 39 */ 'R', '1', '0', 0, |
| /* 43 */ 'S', '1', '0', 0, |
| /* 47 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0, |
| /* 63 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0, |
| /* 79 */ 'S', '2', '0', 0, |
| /* 83 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0, |
| /* 99 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0, |
| /* 115 */ 'S', '3', '0', 0, |
| /* 119 */ 'D', '0', 0, |
| /* 122 */ 'P', '0', 0, |
| /* 125 */ 'Q', '0', 0, |
| /* 128 */ 'M', 'V', 'F', 'R', '0', 0, |
| /* 134 */ 'S', '0', 0, |
| /* 137 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0, |
| /* 148 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0, |
| /* 161 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0, |
| /* 175 */ 'R', '1', '0', '_', 'R', '1', '1', 0, |
| /* 183 */ 'S', '1', '1', 0, |
| /* 187 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0, |
| /* 199 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0, |
| /* 215 */ 'S', '2', '1', 0, |
| /* 219 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0, |
| /* 231 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0, |
| /* 247 */ 'S', '3', '1', 0, |
| /* 251 */ 'D', '1', 0, |
| /* 254 */ 'Q', '0', '_', 'Q', '1', 0, |
| /* 260 */ 'M', 'V', 'F', 'R', '1', 0, |
| /* 266 */ 'R', '0', '_', 'R', '1', 0, |
| /* 272 */ 'S', '1', 0, |
| /* 275 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0, |
| /* 289 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0, |
| /* 304 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0, |
| /* 319 */ 'R', '1', '2', 0, |
| /* 323 */ 'S', '1', '2', 0, |
| /* 327 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0, |
| /* 343 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0, |
| /* 359 */ 'S', '2', '2', 0, |
| /* 363 */ 'D', '0', '_', 'D', '2', 0, |
| /* 369 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0, |
| /* 378 */ 'Q', '1', '_', 'Q', '2', 0, |
| /* 384 */ 'M', 'V', 'F', 'R', '2', 0, |
| /* 390 */ 'S', '2', 0, |
| /* 393 */ 'F', 'P', 'I', 'N', 'S', 'T', '2', 0, |
| /* 401 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0, |
| /* 415 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0, |
| /* 427 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0, |
| /* 443 */ 'S', '1', '3', 0, |
| /* 447 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0, |
| /* 463 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0, |
| /* 475 */ 'S', '2', '3', 0, |
| /* 479 */ 'D', '1', '_', 'D', '3', 0, |
| /* 485 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0, |
| /* 494 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0, |
| /* 506 */ 'R', '2', '_', 'R', '3', 0, |
| /* 512 */ 'S', '3', 0, |
| /* 515 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0, |
| /* 530 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0, |
| /* 546 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0, |
| /* 562 */ 'S', '1', '4', 0, |
| /* 566 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0, |
| /* 582 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0, |
| /* 598 */ 'S', '2', '4', 0, |
| /* 602 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0, |
| /* 611 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0, |
| /* 623 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0, |
| /* 635 */ 'R', '4', 0, |
| /* 638 */ 'S', '4', 0, |
| /* 641 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0, |
| /* 656 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0, |
| /* 668 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0, |
| /* 684 */ 'S', '1', '5', 0, |
| /* 688 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0, |
| /* 704 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0, |
| /* 716 */ 'S', '2', '5', 0, |
| /* 720 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0, |
| /* 729 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0, |
| /* 738 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0, |
| /* 750 */ 'R', '4', '_', 'R', '5', 0, |
| /* 756 */ 'S', '5', 0, |
| /* 759 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0, |
| /* 775 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0, |
| /* 791 */ 'S', '1', '6', 0, |
| /* 795 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0, |
| /* 811 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0, |
| /* 827 */ 'S', '2', '6', 0, |
| /* 831 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0, |
| /* 843 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0, |
| /* 855 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0, |
| /* 867 */ 'R', '6', 0, |
| /* 870 */ 'S', '6', 0, |
| /* 873 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0, |
| /* 889 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0, |
| /* 901 */ 'S', '1', '7', 0, |
| /* 905 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0, |
| /* 921 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0, |
| /* 933 */ 'S', '2', '7', 0, |
| /* 937 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0, |
| /* 949 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0, |
| /* 958 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0, |
| /* 970 */ 'R', '6', '_', 'R', '7', 0, |
| /* 976 */ 'S', '7', 0, |
| /* 979 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0, |
| /* 995 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0, |
| /* 1011 */ 'S', '1', '8', 0, |
| /* 1015 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0, |
| /* 1031 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0, |
| /* 1047 */ 'S', '2', '8', 0, |
| /* 1051 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0, |
| /* 1063 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0, |
| /* 1075 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0, |
| /* 1087 */ 'R', '8', 0, |
| /* 1090 */ 'S', '8', 0, |
| /* 1093 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0, |
| /* 1109 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0, |
| /* 1121 */ 'S', '1', '9', 0, |
| /* 1125 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0, |
| /* 1141 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0, |
| /* 1153 */ 'S', '2', '9', 0, |
| /* 1157 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0, |
| /* 1169 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0, |
| /* 1178 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0, |
| /* 1190 */ 'R', '8', '_', 'R', '9', 0, |
| /* 1196 */ 'S', '9', 0, |
| /* 1199 */ 'P', 'C', 0, |
| /* 1202 */ 'F', 'P', 'S', 'C', 'R', '_', 'N', 'Z', 'C', 'V', 'Q', 'C', 0, |
| /* 1215 */ 'F', 'P', 'E', 'X', 'C', 0, |
| /* 1221 */ 'F', 'P', 'S', 'I', 'D', 0, |
| /* 1227 */ 'I', 'T', 'S', 'T', 'A', 'T', 'E', 0, |
| /* 1235 */ 'R', '1', '2', '_', 'S', 'P', 0, |
| /* 1242 */ 'F', 'P', 'S', 'C', 'R', 0, |
| /* 1248 */ 'L', 'R', 0, |
| /* 1251 */ 'V', 'P', 'R', 0, |
| /* 1255 */ 'A', 'P', 'S', 'R', 0, |
| /* 1260 */ 'C', 'P', 'S', 'R', 0, |
| /* 1265 */ 'S', 'P', 'S', 'R', 0, |
| /* 1270 */ 'Z', 'R', 0, |
| /* 1273 */ 'F', 'P', 'C', 'X', 'T', 'N', 'S', 0, |
| /* 1281 */ 'F', 'P', 'C', 'X', 'T', 'S', 0, |
| /* 1288 */ 'F', 'P', 'I', 'N', 'S', 'T', 0, |
| /* 1295 */ 'F', 'P', 'S', 'C', 'R', '_', 'N', 'Z', 'C', 'V', 0, |
| /* 1306 */ 'A', 'P', 'S', 'R', '_', 'N', 'Z', 'C', 'V', 0, |
| }; |
| |
| extern const MCRegisterDesc ARMRegDesc[] = { // Descriptors |
| { 12, 0, 0, 0, 0, 0 }, |
| { 1255, 16, 16, 2, 66913, 0 }, |
| { 1306, 16, 16, 2, 66913, 0 }, |
| { 1260, 16, 16, 2, 66913, 0 }, |
| { 1273, 16, 16, 2, 66913, 0 }, |
| { 1281, 16, 16, 2, 66913, 0 }, |
| { 1215, 16, 16, 2, 66913, 0 }, |
| { 1288, 16, 16, 2, 66913, 0 }, |
| { 1242, 16, 16, 2, 17664, 0 }, |
| { 1295, 16, 16, 2, 17664, 0 }, |
| { 1202, 16, 16, 2, 66881, 0 }, |
| { 1221, 16, 16, 2, 66881, 0 }, |
| { 1227, 16, 16, 2, 66881, 0 }, |
| { 1248, 16, 16, 2, 66881, 0 }, |
| { 1199, 16, 16, 2, 66881, 0 }, |
| { 1239, 16, 1524, 2, 66881, 0 }, |
| { 1265, 16, 16, 2, 66881, 0 }, |
| { 1251, 16, 16, 2, 66881, 0 }, |
| { 1270, 16, 16, 2, 66881, 0 }, |
| { 119, 350, 4011, 19, 13250, 8 }, |
| { 251, 357, 2477, 19, 13250, 8 }, |
| { 366, 364, 3960, 19, 13250, 8 }, |
| { 482, 378, 3848, 19, 13250, 8 }, |
| { 608, 392, 3896, 19, 13250, 8 }, |
| { 726, 406, 3727, 19, 13250, 8 }, |
| { 840, 420, 3783, 19, 13250, 8 }, |
| { 946, 434, 3602, 19, 13250, 8 }, |
| { 1060, 448, 3662, 19, 13250, 8 }, |
| { 1166, 462, 3482, 19, 13250, 8 }, |
| { 9, 476, 3542, 19, 13250, 8 }, |
| { 144, 490, 3362, 19, 13250, 8 }, |
| { 285, 504, 3422, 19, 13250, 8 }, |
| { 411, 518, 3242, 19, 13250, 8 }, |
| { 526, 532, 3302, 19, 13250, 8 }, |
| { 652, 546, 3147, 19, 13250, 8 }, |
| { 771, 16, 3206, 2, 17761, 0 }, |
| { 885, 16, 3076, 2, 17761, 0 }, |
| { 991, 16, 3111, 2, 17761, 0 }, |
| { 1105, 16, 3006, 2, 17761, 0 }, |
| { 59, 16, 3041, 2, 17761, 0 }, |
| { 195, 16, 2936, 2, 17761, 0 }, |
| { 339, 16, 2971, 2, 17761, 0 }, |
| { 459, 16, 2866, 2, 17761, 0 }, |
| { 578, 16, 2901, 2, 17761, 0 }, |
| { 700, 16, 2795, 2, 17761, 0 }, |
| { 807, 16, 2835, 2, 17761, 0 }, |
| { 917, 16, 2361, 2, 17761, 0 }, |
| { 1027, 16, 2409, 2, 17761, 0 }, |
| { 1137, 16, 2382, 2, 17761, 0 }, |
| { 95, 16, 2427, 2, 17761, 0 }, |
| { 227, 16, 2787, 2, 17761, 0 }, |
| { 393, 16, 16, 2, 17761, 0 }, |
| { 128, 16, 16, 2, 17761, 0 }, |
| { 260, 16, 16, 2, 17761, 0 }, |
| { 384, 16, 16, 2, 17761, 0 }, |
| { 122, 16, 16, 2, 17761, 0 }, |
| { 125, 353, 1112, 22, 2196, 11 }, |
| { 257, 374, 775, 22, 2196, 11 }, |
| { 381, 402, 314, 22, 2196, 11 }, |
| { 503, 430, 244, 22, 2196, 11 }, |
| { 632, 458, 234, 22, 2196, 11 }, |
| { 747, 486, 224, 22, 2196, 11 }, |
| { 864, 514, 214, 22, 2196, 11 }, |
| { 967, 542, 204, 22, 2196, 11 }, |
| { 1084, 804, 194, 0, 12818, 20 }, |
| { 1187, 807, 184, 0, 12818, 20 }, |
| { 35, 810, 174, 0, 12818, 20 }, |
| { 171, 813, 164, 0, 12818, 20 }, |
| { 315, 816, 154, 0, 12818, 20 }, |
| { 439, 819, 591, 0, 12818, 20 }, |
| { 558, 822, 2445, 0, 12818, 20 }, |
| { 680, 825, 1106, 0, 12818, 20 }, |
| { 131, 16, 1371, 2, 66881, 0 }, |
| { 263, 16, 1369, 2, 66881, 0 }, |
| { 387, 16, 1369, 2, 66881, 0 }, |
| { 509, 16, 1367, 2, 66881, 0 }, |
| { 635, 16, 1367, 2, 66881, 0 }, |
| { 753, 16, 1365, 2, 66881, 0 }, |
| { 867, 16, 1365, 2, 66881, 0 }, |
| { 973, 16, 1363, 2, 66881, 0 }, |
| { 1087, 16, 1363, 2, 66881, 0 }, |
| { 1193, 16, 1361, 2, 66881, 0 }, |
| { 39, 16, 1361, 2, 66881, 0 }, |
| { 179, 16, 1359, 2, 66881, 0 }, |
| { 319, 16, 1359, 2, 66881, 0 }, |
| { 134, 16, 4019, 2, 65393, 0 }, |
| { 272, 16, 4010, 2, 65393, 0 }, |
| { 390, 16, 2488, 2, 65393, 0 }, |
| { 512, 16, 2476, 2, 65393, 0 }, |
| { 638, 16, 3977, 2, 65393, 0 }, |
| { 756, 16, 3959, 2, 65393, 0 }, |
| { 870, 16, 3866, 2, 65393, 0 }, |
| { 976, 16, 3847, 2, 65393, 0 }, |
| { 1090, 16, 3917, 2, 65393, 0 }, |
| { 1196, 16, 3895, 2, 65393, 0 }, |
| { 43, 16, 3748, 2, 65393, 0 }, |
| { 183, 16, 3726, 2, 65393, 0 }, |
| { 323, 16, 3806, 2, 65393, 0 }, |
| { 443, 16, 3782, 2, 65393, 0 }, |
| { 562, 16, 3625, 2, 65393, 0 }, |
| { 684, 16, 3601, 2, 65393, 0 }, |
| { 791, 16, 3685, 2, 65393, 0 }, |
| { 901, 16, 3661, 2, 65393, 0 }, |
| { 1011, 16, 3505, 2, 65393, 0 }, |
| { 1121, 16, 3481, 2, 65393, 0 }, |
| { 79, 16, 3565, 2, 65393, 0 }, |
| { 215, 16, 3541, 2, 65393, 0 }, |
| { 359, 16, 3385, 2, 65393, 0 }, |
| { 475, 16, 3361, 2, 65393, 0 }, |
| { 598, 16, 3445, 2, 65393, 0 }, |
| { 716, 16, 3421, 2, 65393, 0 }, |
| { 827, 16, 3265, 2, 65393, 0 }, |
| { 933, 16, 3241, 2, 65393, 0 }, |
| { 1047, 16, 3325, 2, 65393, 0 }, |
| { 1153, 16, 3301, 2, 65393, 0 }, |
| { 115, 16, 3170, 2, 65393, 0 }, |
| { 247, 16, 3146, 2, 65393, 0 }, |
| { 363, 367, 4013, 29, 5426, 23 }, |
| { 479, 381, 2500, 29, 5426, 23 }, |
| { 605, 395, 3995, 29, 5426, 23 }, |
| { 723, 409, 3885, 29, 5426, 23 }, |
| { 837, 423, 3939, 29, 5426, 23 }, |
| { 943, 437, 3770, 29, 5426, 23 }, |
| { 1057, 451, 3830, 29, 5426, 23 }, |
| { 1163, 465, 3649, 29, 5426, 23 }, |
| { 6, 479, 3709, 29, 5426, 23 }, |
| { 154, 493, 3529, 29, 5426, 23 }, |
| { 281, 507, 3589, 29, 5426, 23 }, |
| { 407, 521, 3409, 29, 5426, 23 }, |
| { 522, 535, 3469, 29, 5426, 23 }, |
| { 648, 549, 3289, 29, 5426, 23 }, |
| { 767, 3951, 3349, 11, 17602, 35 }, |
| { 881, 3842, 3194, 11, 13522, 35 }, |
| { 987, 1080, 3229, 8, 17329, 39 }, |
| { 1101, 1080, 3099, 8, 17329, 39 }, |
| { 55, 1080, 3134, 8, 17329, 39 }, |
| { 207, 1080, 3029, 8, 17329, 39 }, |
| { 335, 1080, 3064, 8, 17329, 39 }, |
| { 455, 1080, 2959, 8, 17329, 39 }, |
| { 574, 1080, 2994, 8, 17329, 39 }, |
| { 696, 1080, 2889, 8, 17329, 39 }, |
| { 803, 1080, 2924, 8, 17329, 39 }, |
| { 913, 1080, 2818, 8, 17329, 39 }, |
| { 1023, 1080, 2856, 8, 17329, 39 }, |
| { 1133, 1080, 2399, 8, 17329, 39 }, |
| { 91, 1080, 2438, 8, 17329, 39 }, |
| { 239, 1080, 2789, 8, 17329, 39 }, |
| { 254, 1339, 1114, 168, 1044, 57 }, |
| { 378, 1319, 347, 168, 1044, 57 }, |
| { 500, 1299, 142, 168, 1044, 57 }, |
| { 629, 1279, 142, 168, 1044, 57 }, |
| { 744, 1259, 142, 168, 1044, 57 }, |
| { 861, 1239, 142, 168, 1044, 57 }, |
| { 964, 1219, 142, 168, 1044, 57 }, |
| { 1081, 1203, 142, 88, 1456, 74 }, |
| { 1184, 1191, 142, 76, 2114, 87 }, |
| { 32, 1179, 142, 76, 2114, 87 }, |
| { 167, 1167, 142, 76, 2114, 87 }, |
| { 311, 1155, 142, 76, 2114, 87 }, |
| { 435, 1143, 142, 76, 2114, 87 }, |
| { 554, 1131, 344, 76, 2114, 87 }, |
| { 676, 1119, 1108, 76, 2114, 87 }, |
| { 494, 2154, 16, 474, 4, 149 }, |
| { 623, 2099, 16, 474, 4, 149 }, |
| { 738, 2044, 16, 474, 4, 149 }, |
| { 855, 1989, 16, 474, 4, 149 }, |
| { 958, 1934, 16, 474, 4, 149 }, |
| { 1075, 1883, 16, 423, 272, 166 }, |
| { 1178, 1836, 16, 376, 512, 181 }, |
| { 26, 1793, 16, 333, 720, 194 }, |
| { 161, 1754, 16, 294, 1186, 205 }, |
| { 304, 1715, 16, 294, 1186, 205 }, |
| { 427, 1676, 16, 294, 1186, 205 }, |
| { 546, 1637, 16, 294, 1186, 205 }, |
| { 668, 1598, 16, 294, 1186, 205 }, |
| { 266, 783, 16, 16, 8946, 5 }, |
| { 506, 786, 16, 16, 8946, 5 }, |
| { 750, 789, 16, 16, 8946, 5 }, |
| { 970, 792, 16, 16, 8946, 5 }, |
| { 1190, 795, 16, 16, 8946, 5 }, |
| { 175, 798, 16, 16, 8946, 5 }, |
| { 1235, 4077, 16, 16, 17856, 2 }, |
| { 369, 1511, 1113, 63, 1570, 28 }, |
| { 485, 4167, 2509, 63, 1570, 28 }, |
| { 614, 1498, 778, 63, 1570, 28 }, |
| { 729, 4154, 770, 63, 1570, 28 }, |
| { 846, 1485, 317, 63, 1570, 28 }, |
| { 949, 4141, 660, 63, 1570, 28 }, |
| { 1066, 1472, 308, 63, 1570, 28 }, |
| { 1169, 4128, 654, 63, 1570, 28 }, |
| { 16, 1459, 302, 63, 1570, 28 }, |
| { 137, 4115, 648, 63, 1570, 28 }, |
| { 292, 1446, 296, 63, 1570, 28 }, |
| { 415, 4102, 642, 63, 1570, 28 }, |
| { 534, 1433, 290, 63, 1570, 28 }, |
| { 656, 4089, 636, 63, 1570, 28 }, |
| { 779, 1422, 284, 52, 1680, 42 }, |
| { 889, 4080, 630, 43, 1872, 48 }, |
| { 999, 1415, 278, 36, 2401, 53 }, |
| { 1109, 4070, 624, 36, 2401, 53 }, |
| { 67, 1408, 272, 36, 2401, 53 }, |
| { 187, 4063, 618, 36, 2401, 53 }, |
| { 347, 1401, 266, 36, 2401, 53 }, |
| { 463, 4056, 612, 36, 2401, 53 }, |
| { 586, 1394, 260, 36, 2401, 53 }, |
| { 704, 4049, 606, 36, 2401, 53 }, |
| { 815, 1387, 254, 36, 2401, 53 }, |
| { 921, 4042, 600, 36, 2401, 53 }, |
| { 1035, 1380, 765, 36, 2401, 53 }, |
| { 1141, 4035, 2453, 36, 2401, 53 }, |
| { 103, 1373, 2472, 36, 2401, 53 }, |
| { 219, 4028, 1107, 36, 2401, 53 }, |
| { 602, 1026, 4016, 212, 5314, 92 }, |
| { 720, 1014, 3956, 212, 5314, 92 }, |
| { 834, 1002, 4005, 212, 5314, 92 }, |
| { 940, 990, 3912, 212, 5314, 92 }, |
| { 1054, 978, 3912, 212, 5314, 92 }, |
| { 1160, 966, 3801, 212, 5314, 92 }, |
| { 3, 954, 3801, 212, 5314, 92 }, |
| { 151, 942, 3680, 212, 5314, 92 }, |
| { 278, 930, 3680, 212, 5314, 92 }, |
| { 404, 918, 3560, 212, 5314, 92 }, |
| { 518, 906, 3560, 212, 5314, 92 }, |
| { 644, 894, 3440, 212, 5314, 92 }, |
| { 763, 1070, 3440, 202, 17506, 99 }, |
| { 877, 1060, 3320, 202, 13426, 99 }, |
| { 983, 1052, 3320, 194, 14226, 105 }, |
| { 1097, 1044, 3224, 194, 13698, 105 }, |
| { 51, 1038, 3224, 188, 14049, 110 }, |
| { 203, 1038, 3129, 188, 14049, 110 }, |
| { 331, 1038, 3129, 188, 14049, 110 }, |
| { 451, 1038, 3059, 188, 14049, 110 }, |
| { 570, 1038, 3059, 188, 14049, 110 }, |
| { 692, 1038, 2989, 188, 14049, 110 }, |
| { 799, 1038, 2989, 188, 14049, 110 }, |
| { 909, 1038, 2919, 188, 14049, 110 }, |
| { 1019, 1038, 2919, 188, 14049, 110 }, |
| { 1129, 1038, 2830, 188, 14049, 110 }, |
| { 87, 1038, 2853, 188, 14049, 110 }, |
| { 235, 1038, 2792, 188, 14049, 110 }, |
| { 831, 2675, 4017, 276, 5170, 114 }, |
| { 937, 2657, 3954, 276, 5170, 114 }, |
| { 1051, 2639, 3954, 276, 5170, 114 }, |
| { 1157, 2621, 3845, 276, 5170, 114 }, |
| { 0, 2603, 3845, 276, 5170, 114 }, |
| { 148, 2585, 3724, 276, 5170, 114 }, |
| { 275, 2567, 3724, 276, 5170, 114 }, |
| { 401, 2549, 3623, 276, 5170, 114 }, |
| { 515, 2531, 3623, 276, 5170, 114 }, |
| { 641, 2513, 3503, 276, 5170, 114 }, |
| { 759, 2771, 3503, 260, 17378, 123 }, |
| { 873, 2755, 3383, 260, 13298, 123 }, |
| { 979, 2741, 3383, 246, 14114, 131 }, |
| { 1093, 2727, 3263, 246, 13586, 131 }, |
| { 47, 2715, 3263, 234, 13954, 138 }, |
| { 199, 2703, 3168, 234, 13778, 138 }, |
| { 327, 2693, 3168, 224, 13873, 144 }, |
| { 447, 2693, 3097, 224, 13873, 144 }, |
| { 566, 2693, 3097, 224, 13873, 144 }, |
| { 688, 2693, 3027, 224, 13873, 144 }, |
| { 795, 2693, 3027, 224, 13873, 144 }, |
| { 905, 2693, 2957, 224, 13873, 144 }, |
| { 1015, 2693, 2957, 224, 13873, 144 }, |
| { 1125, 2693, 2854, 224, 13873, 144 }, |
| { 83, 2693, 2854, 224, 13873, 144 }, |
| { 231, 2693, 2793, 224, 13873, 144 }, |
| { 372, 360, 2507, 22, 1956, 11 }, |
| { 617, 388, 583, 22, 1956, 11 }, |
| { 849, 416, 756, 22, 1956, 11 }, |
| { 1069, 444, 747, 22, 1956, 11 }, |
| { 19, 472, 738, 22, 1956, 11 }, |
| { 296, 500, 729, 22, 1956, 11 }, |
| { 538, 528, 720, 22, 1956, 11 }, |
| { 783, 3721, 711, 3, 2336, 16 }, |
| { 1003, 562, 702, 0, 8898, 20 }, |
| { 71, 565, 693, 0, 8898, 20 }, |
| { 351, 568, 684, 0, 8898, 20 }, |
| { 590, 571, 675, 0, 8898, 20 }, |
| { 819, 574, 666, 0, 8898, 20 }, |
| { 1039, 577, 2458, 0, 8898, 20 }, |
| { 107, 580, 2466, 0, 8898, 20 }, |
| { 611, 2341, 2486, 148, 900, 57 }, |
| { 843, 2321, 588, 148, 900, 57 }, |
| { 1063, 2301, 588, 148, 900, 57 }, |
| { 13, 2281, 588, 148, 900, 57 }, |
| { 289, 2261, 588, 148, 900, 57 }, |
| { 530, 2241, 588, 148, 900, 57 }, |
| { 775, 2223, 588, 130, 1328, 66 }, |
| { 995, 2209, 588, 116, 1776, 81 }, |
| { 63, 1586, 588, 104, 2034, 87 }, |
| { 343, 1574, 588, 104, 2034, 87 }, |
| { 582, 1562, 588, 104, 2034, 87 }, |
| { 811, 1550, 588, 104, 2034, 87 }, |
| { 1031, 1538, 588, 104, 2034, 87 }, |
| { 99, 1526, 2380, 104, 2034, 87 }, |
| }; |
| |
| extern const MCPhysReg ARMRegUnitRoots[][2] = { |
| { ARM::APSR }, |
| { ARM::APSR_NZCV }, |
| { ARM::CPSR }, |
| { ARM::FPCXTNS }, |
| { ARM::FPCXTS }, |
| { ARM::FPEXC }, |
| { ARM::FPINST }, |
| { ARM::FPSCR, ARM::FPSCR_NZCV }, |
| { ARM::FPSCR_NZCVQC }, |
| { ARM::FPSID }, |
| { ARM::ITSTATE }, |
| { ARM::LR }, |
| { ARM::PC }, |
| { ARM::SP }, |
| { ARM::SPSR }, |
| { ARM::VPR }, |
| { ARM::ZR }, |
| { ARM::S0 }, |
| { ARM::S1 }, |
| { ARM::S2 }, |
| { ARM::S3 }, |
| { ARM::S4 }, |
| { ARM::S5 }, |
| { ARM::S6 }, |
| { ARM::S7 }, |
| { ARM::S8 }, |
| { ARM::S9 }, |
| { ARM::S10 }, |
| { ARM::S11 }, |
| { ARM::S12 }, |
| { ARM::S13 }, |
| { ARM::S14 }, |
| { ARM::S15 }, |
| { ARM::S16 }, |
| { ARM::S17 }, |
| { ARM::S18 }, |
| { ARM::S19 }, |
| { ARM::S20 }, |
| { ARM::S21 }, |
| { ARM::S22 }, |
| { ARM::S23 }, |
| { ARM::S24 }, |
| { ARM::S25 }, |
| { ARM::S26 }, |
| { ARM::S27 }, |
| { ARM::S28 }, |
| { ARM::S29 }, |
| { ARM::S30 }, |
| { ARM::S31 }, |
| { ARM::D16 }, |
| { ARM::D17 }, |
| { ARM::D18 }, |
| { ARM::D19 }, |
| { ARM::D20 }, |
| { ARM::D21 }, |
| { ARM::D22 }, |
| { ARM::D23 }, |
| { ARM::D24 }, |
| { ARM::D25 }, |
| { ARM::D26 }, |
| { ARM::D27 }, |
| { ARM::D28 }, |
| { ARM::D29 }, |
| { ARM::D30 }, |
| { ARM::D31 }, |
| { ARM::FPINST2 }, |
| { ARM::MVFR0 }, |
| { ARM::MVFR1 }, |
| { ARM::MVFR2 }, |
| { ARM::P0 }, |
| { ARM::R0 }, |
| { ARM::R1 }, |
| { ARM::R2 }, |
| { ARM::R3 }, |
| { ARM::R4 }, |
| { ARM::R5 }, |
| { ARM::R6 }, |
| { ARM::R7 }, |
| { ARM::R8 }, |
| { ARM::R9 }, |
| { ARM::R10 }, |
| { ARM::R11 }, |
| { ARM::R12 }, |
| }; |
| |
| namespace { // Register classes... |
| // HPR Register Class... |
| const MCPhysReg HPR[] = { |
| ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31, |
| }; |
| |
| // HPR Bit set. |
| const uint8_t HPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, |
| }; |
| |
| // FPWithVPR Register Class... |
| const MCPhysReg FPWithVPR[] = { |
| ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::VPR, |
| }; |
| |
| // FPWithVPR Bit set. |
| const uint8_t FPWithVPRBits[] = { |
| 0x00, 0x00, 0xfa, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, |
| }; |
| |
| // SPR Register Class... |
| const MCPhysReg SPR[] = { |
| ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, ARM::S16, ARM::S17, ARM::S18, ARM::S19, ARM::S20, ARM::S21, ARM::S22, ARM::S23, ARM::S24, ARM::S25, ARM::S26, ARM::S27, ARM::S28, ARM::S29, ARM::S30, ARM::S31, |
| }; |
| |
| // SPR Bit set. |
| const uint8_t SPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, |
| }; |
| |
| // FPWithVPR_with_ssub_0 Register Class... |
| const MCPhysReg FPWithVPR_with_ssub_0[] = { |
| ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, |
| }; |
| |
| // FPWithVPR_with_ssub_0 Bit set. |
| const uint8_t FPWithVPR_with_ssub_0Bits[] = { |
| 0x00, 0x00, 0xf8, 0xff, 0x07, |
| }; |
| |
| // GPR Register Class... |
| const MCPhysReg GPR[] = { |
| ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC, |
| }; |
| |
| // GPR Bit set. |
| const uint8_t GPRBits[] = { |
| 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, |
| }; |
| |
| // GPRwithAPSR Register Class... |
| const MCPhysReg GPRwithAPSR[] = { |
| ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::APSR_NZCV, |
| }; |
| |
| // GPRwithAPSR Bit set. |
| const uint8_t GPRwithAPSRBits[] = { |
| 0x04, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, |
| }; |
| |
| // GPRwithZR Register Class... |
| const MCPhysReg GPRwithZR[] = { |
| ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::ZR, |
| }; |
| |
| // GPRwithZR Bit set. |
| const uint8_t GPRwithZRBits[] = { |
| 0x00, 0xa0, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, |
| }; |
| |
| // SPR_8 Register Class... |
| const MCPhysReg SPR_8[] = { |
| ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, ARM::S12, ARM::S13, ARM::S14, ARM::S15, |
| }; |
| |
| // SPR_8 Bit set. |
| const uint8_t SPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, |
| }; |
| |
| // GPRnopc Register Class... |
| const MCPhysReg GPRnopc[] = { |
| ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, |
| }; |
| |
| // GPRnopc Bit set. |
| const uint8_t GPRnopcBits[] = { |
| 0x00, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, |
| }; |
| |
| // GPRwithAPSRnosp Register Class... |
| const MCPhysReg GPRwithAPSRnosp[] = { |
| ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::APSR, |
| }; |
| |
| // GPRwithAPSRnosp Bit set. |
| const uint8_t GPRwithAPSRnospBits[] = { |
| 0x02, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, |
| }; |
| |
| // GPRwithZRnosp Register Class... |
| const MCPhysReg GPRwithZRnosp[] = { |
| ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::ZR, |
| }; |
| |
| // GPRwithZRnosp Bit set. |
| const uint8_t GPRwithZRnospBits[] = { |
| 0x00, 0x20, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, |
| }; |
| |
| // rGPR Register Class... |
| const MCPhysReg rGPR[] = { |
| ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, |
| }; |
| |
| // rGPR Bit set. |
| const uint8_t rGPRBits[] = { |
| 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, |
| }; |
| |
| // tGPRwithpc Register Class... |
| const MCPhysReg tGPRwithpc[] = { |
| ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::PC, |
| }; |
| |
| // tGPRwithpc Bit set. |
| const uint8_t tGPRwithpcBits[] = { |
| 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, |
| }; |
| |
| // FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 Register Class... |
| const MCPhysReg FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8[] = { |
| ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, |
| }; |
| |
| // FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 Bit set. |
| const uint8_t FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits[] = { |
| 0x00, 0x00, 0xf8, 0x07, |
| }; |
| |
| // hGPR Register Class... |
| const MCPhysReg hGPR[] = { |
| ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC, |
| }; |
| |
| // hGPR Bit set. |
| const uint8_t hGPRBits[] = { |
| 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, |
| }; |
| |
| // tGPR Register Class... |
| const MCPhysReg tGPR[] = { |
| ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, |
| }; |
| |
| // tGPR Bit set. |
| const uint8_t tGPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, |
| }; |
| |
| // tGPREven Register Class... |
| const MCPhysReg tGPREven[] = { |
| ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, ARM::R12, ARM::LR, |
| }; |
| |
| // tGPREven Bit set. |
| const uint8_t tGPREvenBits[] = { |
| 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15, |
| }; |
| |
| // GPRnopc_and_hGPR Register Class... |
| const MCPhysReg GPRnopc_and_hGPR[] = { |
| ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, |
| }; |
| |
| // GPRnopc_and_hGPR Bit set. |
| const uint8_t GPRnopc_and_hGPRBits[] = { |
| 0x00, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, |
| }; |
| |
| // GPRwithAPSRnosp_and_hGPR Register Class... |
| const MCPhysReg GPRwithAPSRnosp_and_hGPR[] = { |
| ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, |
| }; |
| |
| // GPRwithAPSRnosp_and_hGPR Bit set. |
| const uint8_t GPRwithAPSRnosp_and_hGPRBits[] = { |
| 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, |
| }; |
| |
| // tGPROdd Register Class... |
| const MCPhysReg tGPROdd[] = { |
| ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, |
| }; |
| |
| // tGPROdd Bit set. |
| const uint8_t tGPROddBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x0a, |
| }; |
| |
| // tcGPR Register Class... |
| const MCPhysReg tcGPR[] = { |
| ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12, |
| }; |
| |
| // tcGPR Bit set. |
| const uint8_t tcGPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x10, |
| }; |
| |
| // hGPR_and_tGPREven Register Class... |
| const MCPhysReg hGPR_and_tGPREven[] = { |
| ARM::R8, ARM::R10, ARM::R12, ARM::LR, |
| }; |
| |
| // hGPR_and_tGPREven Bit set. |
| const uint8_t hGPR_and_tGPREvenBits[] = { |
| 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, |
| }; |
| |
| // tGPR_and_tGPREven Register Class... |
| const MCPhysReg tGPR_and_tGPREven[] = { |
| ARM::R0, ARM::R2, ARM::R4, ARM::R6, |
| }; |
| |
| // tGPR_and_tGPREven Bit set. |
| const uint8_t tGPR_and_tGPREvenBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, |
| }; |
| |
| // tGPR_and_tGPROdd Register Class... |
| const MCPhysReg tGPR_and_tGPROdd[] = { |
| ARM::R1, ARM::R3, ARM::R5, ARM::R7, |
| }; |
| |
| // tGPR_and_tGPROdd Bit set. |
| const uint8_t tGPR_and_tGPROddBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, |
| }; |
| |
| // tGPR_and_tcGPR Register Class... |
| const MCPhysReg tGPR_and_tcGPR[] = { |
| ARM::R0, ARM::R1, ARM::R2, ARM::R3, |
| }; |
| |
| // tGPR_and_tcGPR Bit set. |
| const uint8_t tGPR_and_tcGPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, |
| }; |
| |
| // tGPREven_and_tcGPR Register Class... |
| const MCPhysReg tGPREven_and_tcGPR[] = { |
| ARM::R0, ARM::R2, ARM::R12, |
| }; |
| |
| // tGPREven_and_tcGPR Bit set. |
| const uint8_t tGPREven_and_tcGPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x10, |
| }; |
| |
| // hGPR_and_tGPROdd Register Class... |
| const MCPhysReg hGPR_and_tGPROdd[] = { |
| ARM::R9, ARM::R11, |
| }; |
| |
| // hGPR_and_tGPROdd Bit set. |
| const uint8_t hGPR_and_tGPROddBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, |
| }; |
| |
| // tGPREven_and_tGPR_and_tcGPR Register Class... |
| const MCPhysReg tGPREven_and_tGPR_and_tcGPR[] = { |
| ARM::R0, ARM::R2, |
| }; |
| |
| // tGPREven_and_tGPR_and_tcGPR Bit set. |
| const uint8_t tGPREven_and_tGPR_and_tcGPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, |
| }; |
| |
| // tGPROdd_and_tcGPR Register Class... |
| const MCPhysReg tGPROdd_and_tcGPR[] = { |
| ARM::R1, ARM::R3, |
| }; |
| |
| // tGPROdd_and_tcGPR Bit set. |
| const uint8_t tGPROdd_and_tcGPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, |
| }; |
| |
| // CCR Register Class... |
| const MCPhysReg CCR[] = { |
| ARM::CPSR, |
| }; |
| |
| // CCR Bit set. |
| const uint8_t CCRBits[] = { |
| 0x08, |
| }; |
| |
| // GPRlr Register Class... |
| const MCPhysReg GPRlr[] = { |
| ARM::LR, |
| }; |
| |
| // GPRlr Bit set. |
| const uint8_t GPRlrBits[] = { |
| 0x00, 0x20, |
| }; |
| |
| // GPRsp Register Class... |
| const MCPhysReg GPRsp[] = { |
| ARM::SP, |
| }; |
| |
| // GPRsp Bit set. |
| const uint8_t GPRspBits[] = { |
| 0x00, 0x80, |
| }; |
| |
| // VCCR Register Class... |
| const MCPhysReg VCCR[] = { |
| ARM::VPR, |
| }; |
| |
| // VCCR Bit set. |
| const uint8_t VCCRBits[] = { |
| 0x00, 0x00, 0x02, |
| }; |
| |
| // cl_FPSCR_NZCV Register Class... |
| const MCPhysReg cl_FPSCR_NZCV[] = { |
| ARM::FPSCR_NZCV, |
| }; |
| |
| // cl_FPSCR_NZCV Bit set. |
| const uint8_t cl_FPSCR_NZCVBits[] = { |
| 0x00, 0x02, |
| }; |
| |
| // hGPR_and_tGPRwithpc Register Class... |
| const MCPhysReg hGPR_and_tGPRwithpc[] = { |
| ARM::PC, |
| }; |
| |
| // hGPR_and_tGPRwithpc Bit set. |
| const uint8_t hGPR_and_tGPRwithpcBits[] = { |
| 0x00, 0x40, |
| }; |
| |
| // hGPR_and_tcGPR Register Class... |
| const MCPhysReg hGPR_and_tcGPR[] = { |
| ARM::R12, |
| }; |
| |
| // hGPR_and_tcGPR Bit set. |
| const uint8_t hGPR_and_tcGPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, |
| }; |
| |
| // DPR Register Class... |
| const MCPhysReg DPR[] = { |
| ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, |
| }; |
| |
| // DPR Bit set. |
| const uint8_t DPRBits[] = { |
| 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
| }; |
| |
| // DPR_VFP2 Register Class... |
| const MCPhysReg DPR_VFP2[] = { |
| ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, |
| }; |
| |
| // DPR_VFP2 Bit set. |
| const uint8_t DPR_VFP2Bits[] = { |
| 0x00, 0x00, 0xf8, 0xff, 0x07, |
| }; |
| |
| // DPR_8 Register Class... |
| const MCPhysReg DPR_8[] = { |
| ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, |
| }; |
| |
| // DPR_8 Bit set. |
| const uint8_t DPR_8Bits[] = { |
| 0x00, 0x00, 0xf8, 0x07, |
| }; |
| |
| // GPRPair Register Class... |
| const MCPhysReg GPRPair[] = { |
| ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, ARM::R12_SP, |
| }; |
| |
| // GPRPair Bit set. |
| const uint8_t GPRPairBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, |
| }; |
| |
| // GPRPairnosp Register Class... |
| const MCPhysReg GPRPairnosp[] = { |
| ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, ARM::R8_R9, ARM::R10_R11, |
| }; |
| |
| // GPRPairnosp Bit set. |
| const uint8_t GPRPairnospBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, |
| }; |
| |
| // GPRPair_with_gsub_0_in_tGPR Register Class... |
| const MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = { |
| ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, |
| }; |
| |
| // GPRPair_with_gsub_0_in_tGPR Bit set. |
| const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, |
| }; |
| |
| // GPRPair_with_gsub_0_in_hGPR Register Class... |
| const MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = { |
| ARM::R8_R9, ARM::R10_R11, ARM::R12_SP, |
| }; |
| |
| // GPRPair_with_gsub_0_in_hGPR Bit set. |
| const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, |
| }; |
| |
| // GPRPair_with_gsub_0_in_tcGPR Register Class... |
| const MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = { |
| ARM::R0_R1, ARM::R2_R3, ARM::R12_SP, |
| }; |
| |
| // GPRPair_with_gsub_0_in_tcGPR Bit set. |
| const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x21, |
| }; |
| |
| // GPRPair_with_gsub_1_in_tcGPR Register Class... |
| const MCPhysReg GPRPair_with_gsub_1_in_tcGPR[] = { |
| ARM::R0_R1, ARM::R2_R3, |
| }; |
| |
| // GPRPair_with_gsub_1_in_tcGPR Bit set. |
| const uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, |
| }; |
| |
| // GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR Register Class... |
| const MCPhysReg GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR[] = { |
| ARM::R8_R9, ARM::R10_R11, |
| }; |
| |
| // GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR Bit set. |
| const uint8_t GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, |
| }; |
| |
| // GPRPair_with_gsub_1_in_GPRsp Register Class... |
| const MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = { |
| ARM::R12_SP, |
| }; |
| |
| // GPRPair_with_gsub_1_in_GPRsp Bit set. |
| const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, |
| }; |
| |
| // DPairSpc Register Class... |
| const MCPhysReg DPairSpc[] = { |
| ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, ARM::D28_D30, ARM::D29_D31, |
| }; |
| |
| // DPairSpc Bit set. |
| const uint8_t DPairSpcBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x07, |
| }; |
| |
| // DPairSpc_with_ssub_0 Register Class... |
| const MCPhysReg DPairSpc_with_ssub_0[] = { |
| ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, |
| }; |
| |
| // DPairSpc_with_ssub_0 Bit set. |
| const uint8_t DPairSpc_with_ssub_0Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, |
| }; |
| |
| // DPairSpc_with_ssub_4 Register Class... |
| const MCPhysReg DPairSpc_with_ssub_4[] = { |
| ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, ARM::D12_D14, ARM::D13_D15, |
| }; |
| |
| // DPairSpc_with_ssub_4 Bit set. |
| const uint8_t DPairSpc_with_ssub_4Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, |
| }; |
| |
| // DPairSpc_with_dsub_0_in_DPR_8 Register Class... |
| const MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = { |
| ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, |
| }; |
| |
| // DPairSpc_with_dsub_0_in_DPR_8 Bit set. |
| const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, |
| }; |
| |
| // DPairSpc_with_dsub_2_in_DPR_8 Register Class... |
| const MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = { |
| ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, ARM::D4_D6, ARM::D5_D7, |
| }; |
| |
| // DPairSpc_with_dsub_2_in_DPR_8 Bit set. |
| const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, |
| }; |
| |
| // DPair Register Class... |
| const MCPhysReg DPair[] = { |
| ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, ARM::Q15, |
| }; |
| |
| // DPair Bit set. |
| const uint8_t DPairBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x01, |
| }; |
| |
| // DPair_with_ssub_0 Register Class... |
| const MCPhysReg DPair_with_ssub_0[] = { |
| ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, |
| }; |
| |
| // DPair_with_ssub_0 Bit set. |
| const uint8_t DPair_with_ssub_0Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, |
| }; |
| |
| // QPR Register Class... |
| const MCPhysReg QPR[] = { |
| ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, |
| }; |
| |
| // QPR Bit set. |
| const uint8_t QPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, |
| }; |
| |
| // DPair_with_ssub_2 Register Class... |
| const MCPhysReg DPair_with_ssub_2[] = { |
| ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, ARM::Q6, ARM::D13_D14, ARM::Q7, |
| }; |
| |
| // DPair_with_ssub_2 Bit set. |
| const uint8_t DPair_with_ssub_2Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, |
| }; |
| |
| // DPair_with_dsub_0_in_DPR_8 Register Class... |
| const MCPhysReg DPair_with_dsub_0_in_DPR_8[] = { |
| ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, ARM::D7_D8, |
| }; |
| |
| // DPair_with_dsub_0_in_DPR_8 Bit set. |
| const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, |
| }; |
| |
| // MQPR Register Class... |
| const MCPhysReg MQPR[] = { |
| ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, |
| }; |
| |
| // MQPR Bit set. |
| const uint8_t MQPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, |
| }; |
| |
| // QPR_VFP2 Register Class... |
| const MCPhysReg QPR_VFP2[] = { |
| ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, |
| }; |
| |
| // QPR_VFP2 Bit set. |
| const uint8_t QPR_VFP2Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, |
| }; |
| |
| // DPair_with_dsub_1_in_DPR_8 Register Class... |
| const MCPhysReg DPair_with_dsub_1_in_DPR_8[] = { |
| ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, ARM::Q3, |
| }; |
| |
| // DPair_with_dsub_1_in_DPR_8 Bit set. |
| const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, |
| }; |
| |
| // QPR_8 Register Class... |
| const MCPhysReg QPR_8[] = { |
| ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, |
| }; |
| |
| // QPR_8 Bit set. |
| const uint8_t QPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, |
| }; |
| |
| // DTriple Register Class... |
| const MCPhysReg DTriple[] = { |
| ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, ARM::D16_D17_D18, ARM::D17_D18_D19, ARM::D18_D19_D20, ARM::D19_D20_D21, ARM::D20_D21_D22, ARM::D21_D22_D23, ARM::D22_D23_D24, ARM::D23_D24_D25, ARM::D24_D25_D26, ARM::D25_D26_D27, ARM::D26_D27_D28, ARM::D27_D28_D29, ARM::D28_D29_D30, ARM::D29_D30_D31, |
| }; |
| |
| // DTriple Bit set. |
| const uint8_t DTripleBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x0f, |
| }; |
| |
| // DTripleSpc Register Class... |
| const MCPhysReg DTripleSpc[] = { |
| ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31, |
| }; |
| |
| // DTripleSpc Bit set. |
| const uint8_t DTripleSpcBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, |
| }; |
| |
| // DTripleSpc_with_ssub_0 Register Class... |
| const MCPhysReg DTripleSpc_with_ssub_0[] = { |
| ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, |
| }; |
| |
| // DTripleSpc_with_ssub_0 Bit set. |
| const uint8_t DTripleSpc_with_ssub_0Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, |
| }; |
| |
| // DTriple_with_ssub_0 Register Class... |
| const MCPhysReg DTriple_with_ssub_0[] = { |
| ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, ARM::D15_D16_D17, |
| }; |
| |
| // DTriple_with_ssub_0 Bit set. |
| const uint8_t DTriple_with_ssub_0Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, |
| }; |
| |
| // DTriple_with_qsub_0_in_QPR Register Class... |
| const MCPhysReg DTriple_with_qsub_0_in_QPR[] = { |
| ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, ARM::D16_D17_D18, ARM::D18_D19_D20, ARM::D20_D21_D22, ARM::D22_D23_D24, ARM::D24_D25_D26, ARM::D26_D27_D28, ARM::D28_D29_D30, |
| }; |
| |
| // DTriple_with_qsub_0_in_QPR Bit set. |
| const uint8_t DTriple_with_qsub_0_in_QPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x55, 0x55, 0x55, 0x05, |
| }; |
| |
| // DTriple_with_ssub_2 Register Class... |
| const MCPhysReg DTriple_with_ssub_2[] = { |
| ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, ARM::D14_D15_D16, |
| }; |
| |
| // DTriple_with_ssub_2 Bit set. |
| const uint8_t DTriple_with_ssub_2Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, |
| }; |
| |
| // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... |
| const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { |
| ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, ARM::D17_D18_D19, ARM::D19_D20_D21, ARM::D21_D22_D23, ARM::D23_D24_D25, ARM::D25_D26_D27, ARM::D27_D28_D29, ARM::D29_D30_D31, |
| }; |
| |
| // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. |
| const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0x0a, |
| }; |
| |
| // DTripleSpc_with_ssub_4 Register Class... |
| const MCPhysReg DTripleSpc_with_ssub_4[] = { |
| ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, |
| }; |
| |
| // DTripleSpc_with_ssub_4 Bit set. |
| const uint8_t DTripleSpc_with_ssub_4Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, |
| }; |
| |
| // DTriple_with_ssub_4 Register Class... |
| const MCPhysReg DTriple_with_ssub_4[] = { |
| ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, ARM::D8_D9_D10, ARM::D9_D10_D11, ARM::D10_D11_D12, ARM::D11_D12_D13, ARM::D12_D13_D14, ARM::D13_D14_D15, |
| }; |
| |
| // DTriple_with_ssub_4 Bit set. |
| const uint8_t DTriple_with_ssub_4Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, |
| }; |
| |
| // DTripleSpc_with_ssub_8 Register Class... |
| const MCPhysReg DTripleSpc_with_ssub_8[] = { |
| ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, |
| }; |
| |
| // DTripleSpc_with_ssub_8 Bit set. |
| const uint8_t DTripleSpc_with_ssub_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, |
| }; |
| |
| // DTripleSpc_with_dsub_0_in_DPR_8 Register Class... |
| const MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = { |
| ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, |
| }; |
| |
| // DTripleSpc_with_dsub_0_in_DPR_8 Bit set. |
| const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, |
| }; |
| |
| // DTriple_with_dsub_0_in_DPR_8 Register Class... |
| const MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = { |
| ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, ARM::D7_D8_D9, |
| }; |
| |
| // DTriple_with_dsub_0_in_DPR_8 Bit set. |
| const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, |
| }; |
| |
| // DTriple_with_qsub_0_in_MQPR Register Class... |
| const MCPhysReg DTriple_with_qsub_0_in_MQPR[] = { |
| ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, ARM::D14_D15_D16, |
| }; |
| |
| // DTriple_with_qsub_0_in_MQPR Bit set. |
| const uint8_t DTriple_with_qsub_0_in_MQPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x55, 0x15, |
| }; |
| |
| // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... |
| const MCPhysReg DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { |
| ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, ARM::D15_D16_D17, |
| }; |
| |
| // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. |
| const uint8_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x2a, |
| }; |
| |
| // DTriple_with_dsub_1_in_DPR_8 Register Class... |
| const MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = { |
| ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, ARM::D6_D7_D8, |
| }; |
| |
| // DTriple_with_dsub_1_in_DPR_8 Bit set. |
| const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, |
| }; |
| |
| // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class... |
| const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = { |
| ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, ARM::D9_D10_D11, ARM::D11_D12_D13, ARM::D13_D14_D15, |
| }; |
| |
| // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. |
| const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x0a, |
| }; |
| |
| // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR Register Class... |
| const MCPhysReg DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR[] = { |
| ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, ARM::D8_D9_D10, ARM::D10_D11_D12, ARM::D12_D13_D14, |
| }; |
| |
| // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR Bit set. |
| const uint8_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x55, 0x05, |
| }; |
| |
| // DTripleSpc_with_dsub_2_in_DPR_8 Register Class... |
| const MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = { |
| ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, |
| }; |
| |
| // DTripleSpc_with_dsub_2_in_DPR_8 Bit set. |
| const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, |
| }; |
| |
| // DTriple_with_dsub_2_in_DPR_8 Register Class... |
| const MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = { |
| ARM::D0_D1_D2, ARM::D1_D2_D3, ARM::D2_D3_D4, ARM::D3_D4_D5, ARM::D4_D5_D6, ARM::D5_D6_D7, |
| }; |
| |
| // DTriple_with_dsub_2_in_DPR_8 Bit set. |
| const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, |
| }; |
| |
| // DTripleSpc_with_dsub_4_in_DPR_8 Register Class... |
| const MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = { |
| ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, |
| }; |
| |
| // DTripleSpc_with_dsub_4_in_DPR_8 Bit set. |
| const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, |
| }; |
| |
| // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class... |
| const MCPhysReg DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = { |
| ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, ARM::D7_D8_D9, |
| }; |
| |
| // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. |
| const uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2a, |
| }; |
| |
| // DTriple_with_qsub_0_in_QPR_8 Register Class... |
| const MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = { |
| ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, ARM::D6_D7_D8, |
| }; |
| |
| // DTriple_with_qsub_0_in_QPR_8 Bit set. |
| const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x15, |
| }; |
| |
| // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR Register Class... |
| const MCPhysReg DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR[] = { |
| ARM::D0_D1_D2, ARM::D2_D3_D4, ARM::D4_D5_D6, |
| }; |
| |
| // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR Bit set. |
| const uint8_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, |
| }; |
| |
| // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class... |
| const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = { |
| ARM::D1_D2_D3, ARM::D3_D4_D5, ARM::D5_D6_D7, |
| }; |
| |
| // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set. |
| const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0a, |
| }; |
| |
| // DQuadSpc Register Class... |
| const MCPhysReg DQuadSpc[] = { |
| ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, ARM::D16_D18_D20, ARM::D17_D19_D21, ARM::D18_D20_D22, ARM::D19_D21_D23, ARM::D20_D22_D24, ARM::D21_D23_D25, ARM::D22_D24_D26, ARM::D23_D25_D27, ARM::D24_D26_D28, ARM::D25_D27_D29, ARM::D26_D28_D30, ARM::D27_D29_D31, |
| }; |
| |
| // DQuadSpc Bit set. |
| const uint8_t DQuadSpcBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, |
| }; |
| |
| // DQuadSpc_with_ssub_0 Register Class... |
| const MCPhysReg DQuadSpc_with_ssub_0[] = { |
| ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, ARM::D14_D16_D18, ARM::D15_D17_D19, |
| }; |
| |
| // DQuadSpc_with_ssub_0 Bit set. |
| const uint8_t DQuadSpc_with_ssub_0Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, |
| }; |
| |
| // DQuadSpc_with_ssub_4 Register Class... |
| const MCPhysReg DQuadSpc_with_ssub_4[] = { |
| ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, ARM::D12_D14_D16, ARM::D13_D15_D17, |
| }; |
| |
| // DQuadSpc_with_ssub_4 Bit set. |
| const uint8_t DQuadSpc_with_ssub_4Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, |
| }; |
| |
| // DQuadSpc_with_ssub_8 Register Class... |
| const MCPhysReg DQuadSpc_with_ssub_8[] = { |
| ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, ARM::D8_D10_D12, ARM::D9_D11_D13, ARM::D10_D12_D14, ARM::D11_D13_D15, |
| }; |
| |
| // DQuadSpc_with_ssub_8 Bit set. |
| const uint8_t DQuadSpc_with_ssub_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, |
| }; |
| |
| // DQuadSpc_with_dsub_0_in_DPR_8 Register Class... |
| const MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = { |
| ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, ARM::D6_D8_D10, ARM::D7_D9_D11, |
| }; |
| |
| // DQuadSpc_with_dsub_0_in_DPR_8 Bit set. |
| const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, |
| }; |
| |
| // DQuadSpc_with_dsub_2_in_DPR_8 Register Class... |
| const MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = { |
| ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, ARM::D4_D6_D8, ARM::D5_D7_D9, |
| }; |
| |
| // DQuadSpc_with_dsub_2_in_DPR_8 Bit set. |
| const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, |
| }; |
| |
| // DQuadSpc_with_dsub_4_in_DPR_8 Register Class... |
| const MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = { |
| ARM::D0_D2_D4, ARM::D1_D3_D5, ARM::D2_D4_D6, ARM::D3_D5_D7, |
| }; |
| |
| // DQuadSpc_with_dsub_4_in_DPR_8 Bit set. |
| const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, |
| }; |
| |
| // DQuad Register Class... |
| const MCPhysReg DQuad[] = { |
| ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, ARM::Q8_Q9, ARM::D17_D18_D19_D20, ARM::Q9_Q10, ARM::D19_D20_D21_D22, ARM::Q10_Q11, ARM::D21_D22_D23_D24, ARM::Q11_Q12, ARM::D23_D24_D25_D26, ARM::Q12_Q13, ARM::D25_D26_D27_D28, ARM::Q13_Q14, ARM::D27_D28_D29_D30, ARM::Q14_Q15, |
| }; |
| |
| // DQuad Bit set. |
| const uint8_t DQuadBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, |
| }; |
| |
| // DQuad_with_ssub_0 Register Class... |
| const MCPhysReg DQuad_with_ssub_0[] = { |
| ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, ARM::D15_D16_D17_D18, |
| }; |
| |
| // DQuad_with_ssub_0 Bit set. |
| const uint8_t DQuad_with_ssub_0Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, |
| }; |
| |
| // DQuad_with_ssub_2 Register Class... |
| const MCPhysReg DQuad_with_ssub_2[] = { |
| ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, ARM::Q7_Q8, |
| }; |
| |
| // DQuad_with_ssub_2 Bit set. |
| const uint8_t DQuad_with_ssub_2Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, |
| }; |
| |
| // QQPR Register Class... |
| const MCPhysReg QQPR[] = { |
| ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, ARM::Q8_Q9, ARM::Q9_Q10, ARM::Q10_Q11, ARM::Q11_Q12, ARM::Q12_Q13, ARM::Q13_Q14, ARM::Q14_Q15, |
| }; |
| |
| // QQPR Bit set. |
| const uint8_t QQPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, |
| }; |
| |
| // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... |
| const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { |
| ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, ARM::D17_D18_D19_D20, ARM::D19_D20_D21_D22, ARM::D21_D22_D23_D24, ARM::D23_D24_D25_D26, ARM::D25_D26_D27_D28, ARM::D27_D28_D29_D30, |
| }; |
| |
| // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. |
| const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, |
| }; |
| |
| // DQuad_with_ssub_4 Register Class... |
| const MCPhysReg DQuad_with_ssub_4[] = { |
| ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, ARM::D13_D14_D15_D16, |
| }; |
| |
| // DQuad_with_ssub_4 Bit set. |
| const uint8_t DQuad_with_ssub_4Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, |
| }; |
| |
| // DQuad_with_ssub_6 Register Class... |
| const MCPhysReg DQuad_with_ssub_6[] = { |
| ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, ARM::Q4_Q5, ARM::D9_D10_D11_D12, ARM::Q5_Q6, ARM::D11_D12_D13_D14, ARM::Q6_Q7, |
| }; |
| |
| // DQuad_with_ssub_6 Bit set. |
| const uint8_t DQuad_with_ssub_6Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, |
| }; |
| |
| // DQuad_with_dsub_0_in_DPR_8 Register Class... |
| const MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = { |
| ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, ARM::D7_D8_D9_D10, |
| }; |
| |
| // DQuad_with_dsub_0_in_DPR_8 Bit set. |
| const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, |
| }; |
| |
| // DQuad_with_qsub_0_in_MQPR Register Class... |
| const MCPhysReg DQuad_with_qsub_0_in_MQPR[] = { |
| ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8, |
| }; |
| |
| // DQuad_with_qsub_0_in_MQPR Bit set. |
| const uint8_t DQuad_with_qsub_0_in_MQPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, |
| }; |
| |
| // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class... |
| const MCPhysReg DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = { |
| ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, ARM::D15_D16_D17_D18, |
| }; |
| |
| // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set. |
| const uint8_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, |
| }; |
| |
| // DQuad_with_dsub_1_in_DPR_8 Register Class... |
| const MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = { |
| ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, ARM::Q3_Q4, |
| }; |
| |
| // DQuad_with_dsub_1_in_DPR_8 Bit set. |
| const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, |
| }; |
| |
| // DQuad_with_qsub_1_in_MQPR Register Class... |
| const MCPhysReg DQuad_with_qsub_1_in_MQPR[] = { |
| ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, |
| }; |
| |
| // DQuad_with_qsub_1_in_MQPR Bit set. |
| const uint8_t DQuad_with_qsub_1_in_MQPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, |
| }; |
| |
| // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class... |
| const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = { |
| ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, ARM::D13_D14_D15_D16, |
| }; |
| |
| // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. |
| const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, |
| }; |
| |
| // DQuad_with_dsub_2_in_DPR_8 Register Class... |
| const MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = { |
| ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, ARM::D5_D6_D7_D8, |
| }; |
| |
| // DQuad_with_dsub_2_in_DPR_8 Bit set. |
| const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, |
| }; |
| |
| // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class... |
| const MCPhysReg DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = { |
| ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, ARM::D9_D10_D11_D12, ARM::D11_D12_D13_D14, |
| }; |
| |
| // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. |
| const uint8_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, |
| }; |
| |
| // DQuad_with_dsub_3_in_DPR_8 Register Class... |
| const MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = { |
| ARM::Q0_Q1, ARM::D1_D2_D3_D4, ARM::Q1_Q2, ARM::D3_D4_D5_D6, ARM::Q2_Q3, |
| }; |
| |
| // DQuad_with_dsub_3_in_DPR_8 Bit set. |
| const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, |
| }; |
| |
| // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class... |
| const MCPhysReg DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = { |
| ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, ARM::D7_D8_D9_D10, |
| }; |
| |
| // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. |
| const uint8_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, |
| }; |
| |
| // DQuad_with_qsub_0_in_QPR_8 Register Class... |
| const MCPhysReg DQuad_with_qsub_0_in_QPR_8[] = { |
| ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, |
| }; |
| |
| // DQuad_with_qsub_0_in_QPR_8 Bit set. |
| const uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, |
| }; |
| |
| // DQuad_with_qsub_1_in_QPR_8 Register Class... |
| const MCPhysReg DQuad_with_qsub_1_in_QPR_8[] = { |
| ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, |
| }; |
| |
| // DQuad_with_qsub_1_in_QPR_8 Bit set. |
| const uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, |
| }; |
| |
| // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class... |
| const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = { |
| ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, ARM::D5_D6_D7_D8, |
| }; |
| |
| // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set. |
| const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, |
| }; |
| |
| // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class... |
| const MCPhysReg DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = { |
| ARM::D1_D2_D3_D4, ARM::D3_D4_D5_D6, |
| }; |
| |
| // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set. |
| const uint8_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, |
| }; |
| |
| // QQQQPR Register Class... |
| const MCPhysReg QQQQPR[] = { |
| ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, ARM::Q8_Q9_Q10_Q11, ARM::Q9_Q10_Q11_Q12, ARM::Q10_Q11_Q12_Q13, ARM::Q11_Q12_Q13_Q14, ARM::Q12_Q13_Q14_Q15, |
| }; |
| |
| // QQQQPR Bit set. |
| const uint8_t QQQQPRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, |
| }; |
| |
| // QQQQPR_with_ssub_0 Register Class... |
| const MCPhysReg QQQQPR_with_ssub_0[] = { |
| ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10, |
| }; |
| |
| // QQQQPR_with_ssub_0 Bit set. |
| const uint8_t QQQQPR_with_ssub_0Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, |
| }; |
| |
| // QQQQPR_with_ssub_4 Register Class... |
| const MCPhysReg QQQQPR_with_ssub_4[] = { |
| ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, |
| }; |
| |
| // QQQQPR_with_ssub_4 Bit set. |
| const uint8_t QQQQPR_with_ssub_4Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, |
| }; |
| |
| // QQQQPR_with_ssub_8 Register Class... |
| const MCPhysReg QQQQPR_with_ssub_8[] = { |
| ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, |
| }; |
| |
| // QQQQPR_with_ssub_8 Bit set. |
| const uint8_t QQQQPR_with_ssub_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, |
| }; |
| |
| // QQQQPR_with_ssub_12 Register Class... |
| const MCPhysReg QQQQPR_with_ssub_12[] = { |
| ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, |
| }; |
| |
| // QQQQPR_with_ssub_12 Bit set. |
| const uint8_t QQQQPR_with_ssub_12Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, |
| }; |
| |
| // QQQQPR_with_dsub_0_in_DPR_8 Register Class... |
| const MCPhysReg QQQQPR_with_dsub_0_in_DPR_8[] = { |
| ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, |
| }; |
| |
| // QQQQPR_with_dsub_0_in_DPR_8 Bit set. |
| const uint8_t QQQQPR_with_dsub_0_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, |
| }; |
| |
| // QQQQPR_with_dsub_2_in_DPR_8 Register Class... |
| const MCPhysReg QQQQPR_with_dsub_2_in_DPR_8[] = { |
| ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, |
| }; |
| |
| // QQQQPR_with_dsub_2_in_DPR_8 Bit set. |
| const uint8_t QQQQPR_with_dsub_2_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, |
| }; |
| |
| // QQQQPR_with_dsub_4_in_DPR_8 Register Class... |
| const MCPhysReg QQQQPR_with_dsub_4_in_DPR_8[] = { |
| ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, |
| }; |
| |
| // QQQQPR_with_dsub_4_in_DPR_8 Bit set. |
| const uint8_t QQQQPR_with_dsub_4_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, |
| }; |
| |
| // QQQQPR_with_dsub_6_in_DPR_8 Register Class... |
| const MCPhysReg QQQQPR_with_dsub_6_in_DPR_8[] = { |
| ARM::Q0_Q1_Q2_Q3, |
| }; |
| |
| // QQQQPR_with_dsub_6_in_DPR_8 Bit set. |
| const uint8_t QQQQPR_with_dsub_6_in_DPR_8Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, |
| }; |
| |
| } // end anonymous namespace |
| |
| extern const char ARMRegClassStrings[] = { |
| /* 0 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0, |
| /* 19 */ 'F', 'P', 'W', 'i', 't', 'h', 'V', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0, |
| /* 41 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0, |
| /* 62 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0, |
| /* 85 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0, |
| /* 106 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0, |
| /* 124 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0, |
| /* 144 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', 0, |
| /* 162 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '1', '2', 0, |
| /* 182 */ 'D', 'P', 'R', '_', 'V', 'F', 'P', '2', 0, |
| /* 191 */ 'Q', 'P', 'R', '_', 'V', 'F', 'P', '2', 0, |
| /* 200 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0, |
| /* 218 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0, |
| /* 238 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', 0, |
| /* 256 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0, |
| /* 275 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0, |
| /* 296 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0, |
| /* 319 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0, |
| /* 340 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0, |
| /* 358 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', 0, |
| /* 378 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '6', 0, |
| /* 396 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 424 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 454 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 486 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 516 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 543 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 572 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 599 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 626 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 655 */ 'D', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 682 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 710 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 740 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 772 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 802 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 829 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 858 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '3', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 885 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 913 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 943 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '4', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 975 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '6', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', 0, |
| /* 1003 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0, |
| /* 1030 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0, |
| /* 1059 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0, |
| /* 1086 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0, |
| /* 1134 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', '_', '8', 0, |
| /* 1184 */ 'F', 'P', 'W', 'i', 't', 'h', 'V', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'S', 'P', 'R', '_', '8', 0, |
| /* 1227 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0, |
| /* 1246 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0, |
| /* 1267 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '8', 0, |
| /* 1290 */ 'V', 'C', 'C', 'R', 0, |
| /* 1295 */ 'D', 'P', 'R', 0, |
| /* 1299 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0, |
| /* 1314 */ 't', 'G', 'P', 'R', 'E', 'v', 'e', 'n', '_', 'a', 'n', 'd', '_', 't', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0, |
| /* 1342 */ 't', 'G', 'P', 'R', 'O', 'd', 'd', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0, |
| /* 1360 */ 't', 'G', 'P', 'R', 'E', 'v', 'e', 'n', '_', 'a', 'n', 'd', '_', 't', 'c', 'G', 'P', 'R', 0, |
| /* 1379 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', 0, |
| /* 1408 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', 0, |
| /* 1437 */ 'G', 'P', 'R', 'n', 'o', 'p', 'c', '_', 'a', 'n', 'd', '_', 'h', 'G', 'P', 'R', 0, |
| /* 1454 */ 'G', 'P', 'R', 'w', 'i', 't', 'h', 'A', 'P', 'S', 'R', 'n', 'o', 's', 'p', '_', 'a', 'n', 'd', '_', 'h', 'G', 'P', 'R', 0, |
| /* 1479 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', 'n', 'o', 's', 'p', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'h', 'G', 'P', 'R', 0, |
| /* 1523 */ 'r', 'G', 'P', 'R', 0, |
| /* 1528 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 't', 'G', 'P', 'R', 0, |
| /* 1556 */ 'H', 'P', 'R', 0, |
| /* 1560 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'M', 'Q', 'P', 'R', 0, |
| /* 1586 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '4', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'M', 'Q', 'P', 'R', 0, |
| /* 1638 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '2', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'M', 'Q', 'P', 'R', 0, |
| /* 1699 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'M', 'Q', 'P', 'R', 0, |
| /* 1725 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '6', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'M', 'Q', 'P', 'R', 0, |
| /* 1794 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'M', 'Q', 'P', 'R', 0, |
| /* 1872 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '3', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'M', 'Q', 'P', 'R', 0, |
| /* 1950 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'd', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'D', 'P', 'R', '_', '8', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'M', 'Q', 'P', 'R', 0, |
| /* 2032 */ 'Q', 'Q', 'Q', 'Q', 'P', 'R', 0, |
| /* 2039 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '_', '0', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0, |
| /* 2066 */ 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'a', 'n', 'd', '_', 'D', 'Q', 'u', 'a', 'd', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0, |
| /* 2134 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '0', '_', 'a', 'n', 'd', '_', 'D', 'T', 'r', 'i', 'p', 'l', 'e', '_', 'w', 'i', 't', 'h', '_', 's', 's', 'u', 'b', '_', '2', '_', 's', 's', 'u', 'b', '_', '3', '_', 's', 's', 'u', 'b', '_', '4', '_', 's', 's', 'u', 'b', '_', '5', '_', 'i', 'n', '_', 'Q', 'P', 'R', 0, |
| /* 2206 */ 'S', 'P', 'R', 0, |
| /* 2210 */ 'F', 'P', 'W', 'i', 't', 'h', 'V', 'P', 'R', 0, |
| /* 2220 */ 'G', 'P', 'R', 'w', 'i', 't', 'h', 'A', 'P', 'S', 'R', 0, |
| /* 2232 */ 'G', 'P', 'R', 'w', 'i', 't', 'h', 'Z', 'R', 0, |
| /* 2242 */ 'c', 'l', '_', 'F', 'P', 'S', 'C', 'R', '_', 'N', 'Z', 'C', 'V', 0, |
| /* 2256 */ 'D', 'Q', 'u', 'a', 'd', 'S', 'p', 'c', 0, |
| /* 2265 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 'S', 'p', 'c', 0, |
| /* 2276 */ 'D', 'P', 'a', 'i', 'r', 'S', 'p', 'c', 0, |
| /* 2285 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'G', 'P', 'R', 'w', 'i', 't', 'h', 'p', 'c', 0, |
| /* 2305 */ 'G', 'P', 'R', 'n', 'o', 'p', 'c', 0, |
| /* 2313 */ 'D', 'Q', 'u', 'a', 'd', 0, |
| /* 2319 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'G', 'P', 'R', 'O', 'd', 'd', 0, |
| /* 2336 */ 't', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'G', 'P', 'R', 'O', 'd', 'd', 0, |
| /* 2353 */ 'D', 'T', 'r', 'i', 'p', 'l', 'e', 0, |
| /* 2361 */ 'h', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'G', 'P', 'R', 'E', 'v', 'e', 'n', 0, |
| /* 2379 */ 't', 'G', 'P', 'R', '_', 'a', 'n', 'd', '_', 't', 'G', 'P', 'R', 'E', 'v', 'e', 'n', 0, |
| /* 2397 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', '_', 'w', 'i', 't', 'h', '_', 'g', 's', 'u', 'b', '_', '1', '_', 'i', 'n', '_', 'G', 'P', 'R', 's', 'p', 0, |
| /* 2426 */ 'G', 'P', 'R', 'w', 'i', 't', 'h', 'A', 'P', 'S', 'R', 'n', 'o', 's', 'p', 0, |
| /* 2442 */ 'G', 'P', 'R', 'w', 'i', 't', 'h', 'Z', 'R', 'n', 'o', 's', 'p', 0, |
| /* 2456 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', 'n', 'o', 's', 'p', 0, |
| /* 2468 */ 'D', 'P', 'a', 'i', 'r', 0, |
| /* 2474 */ 'G', 'P', 'R', 'P', 'a', 'i', 'r', 0, |
| /* 2482 */ 'G', 'P', 'R', 'l', 'r', 0, |
| }; |
| |
| extern const MCRegisterClass ARMMCRegisterClasses[] = { |
| { HPR, HPRBits, 1556, 32, sizeof(HPRBits), ARM::HPRRegClassID, 1, true }, |
| { FPWithVPR, FPWithVPRBits, 2210, 65, sizeof(FPWithVPRBits), ARM::FPWithVPRRegClassID, 1, false }, |
| { SPR, SPRBits, 2206, 32, sizeof(SPRBits), ARM::SPRRegClassID, 1, true }, |
| { FPWithVPR_with_ssub_0, FPWithVPR_with_ssub_0Bits, 19, 16, sizeof(FPWithVPR_with_ssub_0Bits), ARM::FPWithVPR_with_ssub_0RegClassID, 1, false }, |
| { GPR, GPRBits, 1310, 16, sizeof(GPRBits), ARM::GPRRegClassID, 1, true }, |
| { GPRwithAPSR, GPRwithAPSRBits, 2220, 16, sizeof(GPRwithAPSRBits), ARM::GPRwithAPSRRegClassID, 1, true }, |
| { GPRwithZR, GPRwithZRBits, 2232, 16, sizeof(GPRwithZRBits), ARM::GPRwithZRRegClassID, 1, true }, |
| { SPR_8, SPR_8Bits, 1221, 16, sizeof(SPR_8Bits), ARM::SPR_8RegClassID, 1, true }, |
| { GPRnopc, GPRnopcBits, 2305, 15, sizeof(GPRnopcBits), ARM::GPRnopcRegClassID, 1, true }, |
| { GPRwithAPSRnosp, GPRwithAPSRnospBits, 2426, 15, sizeof(GPRwithAPSRnospBits), ARM::GPRwithAPSRnospRegClassID, 1, false }, |
| { GPRwithZRnosp, GPRwithZRnospBits, 2442, 15, sizeof(GPRwithZRnospBits), ARM::GPRwithZRnospRegClassID, 1, true }, |
| { rGPR, rGPRBits, 1523, 14, sizeof(rGPRBits), ARM::rGPRRegClassID, 1, true }, |
| { tGPRwithpc, tGPRwithpcBits, 2294, 9, sizeof(tGPRwithpcBits), ARM::tGPRwithpcRegClassID, 1, true }, |
| { FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8, FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits, 1184, 8, sizeof(FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits), ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID, 1, false }, |
| { hGPR, hGPRBits, 1449, 8, sizeof(hGPRBits), ARM::hGPRRegClassID, 1, true }, |
| { tGPR, tGPRBits, 1551, 8, sizeof(tGPRBits), ARM::tGPRRegClassID, 1, true }, |
| { tGPREven, tGPREvenBits, 2370, 8, sizeof(tGPREvenBits), ARM::tGPREvenRegClassID, 1, true }, |
| { GPRnopc_and_hGPR, GPRnopc_and_hGPRBits, 1437, 7, sizeof(GPRnopc_and_hGPRBits), ARM::GPRnopc_and_hGPRRegClassID, 1, true }, |
| { GPRwithAPSRnosp_and_hGPR, GPRwithAPSRnosp_and_hGPRBits, 1454, 6, sizeof(GPRwithAPSRnosp_and_hGPRBits), ARM::GPRwithAPSRnosp_and_hGPRRegClassID, 1, true }, |
| { tGPROdd, tGPROddBits, 2328, 6, sizeof(tGPROddBits), ARM::tGPROddRegClassID, 1, true }, |
| { tcGPR, tcGPRBits, 1308, 5, sizeof(tcGPRBits), ARM::tcGPRRegClassID, 1, true }, |
| { hGPR_and_tGPREven, hGPR_and_tGPREvenBits, 2361, 4, sizeof(hGPR_and_tGPREvenBits), ARM::hGPR_and_tGPREvenRegClassID, 1, true }, |
| { tGPR_and_tGPREven, tGPR_and_tGPREvenBits, 2379, 4, sizeof(tGPR_and_tGPREvenBits), ARM::tGPR_and_tGPREvenRegClassID, 1, true }, |
| { tGPR_and_tGPROdd, tGPR_and_tGPROddBits, 2336, 4, sizeof(tGPR_and_tGPROddBits), ARM::tGPR_and_tGPROddRegClassID, 1, true }, |
| { tGPR_and_tcGPR, tGPR_and_tcGPRBits, 1327, 4, sizeof(tGPR_and_tcGPRBits), ARM::tGPR_and_tcGPRRegClassID, 1, true }, |
| { tGPREven_and_tcGPR, tGPREven_and_tcGPRBits, 1360, 3, sizeof(tGPREven_and_tcGPRBits), ARM::tGPREven_and_tcGPRRegClassID, 1, true }, |
| { hGPR_and_tGPROdd, hGPR_and_tGPROddBits, 2319, 2, sizeof(hGPR_and_tGPROddBits), ARM::hGPR_and_tGPROddRegClassID, 1, true }, |
| { tGPREven_and_tGPR_and_tcGPR, tGPREven_and_tGPR_and_tcGPRBits, 1314, 2, sizeof(tGPREven_and_tGPR_and_tcGPRBits), ARM::tGPREven_and_tGPR_and_tcGPRRegClassID, 1, true }, |
| { tGPROdd_and_tcGPR, tGPROdd_and_tcGPRBits, 1342, 2, sizeof(tGPROdd_and_tcGPRBits), ARM::tGPROdd_and_tcGPRRegClassID, 1, true }, |
| { CCR, CCRBits, 1291, 1, sizeof(CCRBits), ARM::CCRRegClassID, -1, false }, |
| { GPRlr, GPRlrBits, 2482, 1, sizeof(GPRlrBits), ARM::GPRlrRegClassID, 1, true }, |
| { GPRsp, GPRspBits, 2420, 1, sizeof(GPRspBits), ARM::GPRspRegClassID, 1, true }, |
| { VCCR, VCCRBits, 1290, 1, sizeof(VCCRBits), ARM::VCCRRegClassID, 1, true }, |
| { cl_FPSCR_NZCV, cl_FPSCR_NZCVBits, 2242, 1, sizeof(cl_FPSCR_NZCVBits), ARM::cl_FPSCR_NZCVRegClassID, 1, true }, |
| { hGPR_and_tGPRwithpc, hGPR_and_tGPRwithpcBits, 2285, 1, sizeof(hGPR_and_tGPRwithpcBits), ARM::hGPR_and_tGPRwithpcRegClassID, 1, true }, |
| { hGPR_and_tcGPR, hGPR_and_tcGPRBits, 1299, 1, sizeof(hGPR_and_tcGPRBits), ARM::hGPR_and_tcGPRRegClassID, 1, true }, |
| { DPR, DPRBits, 1295, 32, sizeof(DPRBits), ARM::DPRRegClassID, 1, true }, |
| { DPR_VFP2, DPR_VFP2Bits, 182, 16, sizeof(DPR_VFP2Bits), ARM::DPR_VFP2RegClassID, 1, true }, |
| { DPR_8, DPR_8Bits, 418, 8, sizeof(DPR_8Bits), ARM::DPR_8RegClassID, 1, true }, |
| { GPRPair, GPRPairBits, 2474, 7, sizeof(GPRPairBits), ARM::GPRPairRegClassID, 1, true }, |
| { GPRPairnosp, GPRPairnospBits, 2456, 6, sizeof(GPRPairnospBits), ARM::GPRPairnospRegClassID, 1, true }, |
| { GPRPair_with_gsub_0_in_tGPR, GPRPair_with_gsub_0_in_tGPRBits, 1528, 4, sizeof(GPRPair_with_gsub_0_in_tGPRBits), ARM::GPRPair_with_gsub_0_in_tGPRRegClassID, 1, true }, |
| { GPRPair_with_gsub_0_in_hGPR, GPRPair_with_gsub_0_in_hGPRBits, 1495, 3, sizeof(GPRPair_with_gsub_0_in_hGPRBits), ARM::GPRPair_with_gsub_0_in_hGPRRegClassID, 1, true }, |
| { GPRPair_with_gsub_0_in_tcGPR, GPRPair_with_gsub_0_in_tcGPRBits, 1379, 3, sizeof(GPRPair_with_gsub_0_in_tcGPRBits), ARM::GPRPair_with_gsub_0_in_tcGPRRegClassID, 1, true }, |
| { GPRPair_with_gsub_1_in_tcGPR, GPRPair_with_gsub_1_in_tcGPRBits, 1408, 2, sizeof(GPRPair_with_gsub_1_in_tcGPRBits), ARM::GPRPair_with_gsub_1_in_tcGPRRegClassID, 1, true }, |
| { GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR, GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits, 1479, 2, sizeof(GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits), ARM::GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClassID, 1, true }, |
| { GPRPair_with_gsub_1_in_GPRsp, GPRPair_with_gsub_1_in_GPRspBits, 2397, 1, sizeof(GPRPair_with_gsub_1_in_GPRspBits), ARM::GPRPair_with_gsub_1_in_GPRspRegClassID, 1, true }, |
| { DPairSpc, DPairSpcBits, 2276, 30, sizeof(DPairSpcBits), ARM::DPairSpcRegClassID, 1, true }, |
| { DPairSpc_with_ssub_0, DPairSpc_with_ssub_0Bits, 85, 16, sizeof(DPairSpc_with_ssub_0Bits), ARM::DPairSpc_with_ssub_0RegClassID, 1, true }, |
| { DPairSpc_with_ssub_4, DPairSpc_with_ssub_4Bits, 319, 14, sizeof(DPairSpc_with_ssub_4Bits), ARM::DPairSpc_with_ssub_4RegClassID, 1, true }, |
| { DPairSpc_with_dsub_0_in_DPR_8, DPairSpc_with_dsub_0_in_DPR_8Bits, 486, 8, sizeof(DPairSpc_with_dsub_0_in_DPR_8Bits), ARM::DPairSpc_with_dsub_0_in_DPR_8RegClassID, 1, true }, |
| { DPairSpc_with_dsub_2_in_DPR_8, DPairSpc_with_dsub_2_in_DPR_8Bits, 772, 6, sizeof(DPairSpc_with_dsub_2_in_DPR_8Bits), ARM::DPairSpc_with_dsub_2_in_DPR_8RegClassID, 1, true }, |
| { DPair, DPairBits, 2468, 31, sizeof(DPairBits), ARM::DPairRegClassID, 1, true }, |
| { DPair_with_ssub_0, DPair_with_ssub_0Bits, 144, 16, sizeof(DPair_with_ssub_0Bits), ARM::DPair_with_ssub_0RegClassID, 1, true }, |
| { QPR, QPRBits, 1582, 16, sizeof(QPRBits), ARM::QPRRegClassID, 1, true }, |
| { DPair_with_ssub_2, DPair_with_ssub_2Bits, 238, 15, sizeof(DPair_with_ssub_2Bits), ARM::DPair_with_ssub_2RegClassID, 1, true }, |
| { DPair_with_dsub_0_in_DPR_8, DPair_with_dsub_0_in_DPR_8Bits, 572, 8, sizeof(DPair_with_dsub_0_in_DPR_8Bits), ARM::DPair_with_dsub_0_in_DPR_8RegClassID, 1, true }, |
| { MQPR, MQPRBits, 1581, 8, sizeof(MQPRBits), ARM::MQPRRegClassID, 1, true }, |
| { QPR_VFP2, QPR_VFP2Bits, 191, 8, sizeof(QPR_VFP2Bits), ARM::QPR_VFP2RegClassID, 1, true }, |
| { DPair_with_dsub_1_in_DPR_8, DPair_with_dsub_1_in_DPR_8Bits, 655, 7, sizeof(DPair_with_dsub_1_in_DPR_8Bits), ARM::DPair_with_dsub_1_in_DPR_8RegClassID, 1, true }, |
| { QPR_8, QPR_8Bits, 1024, 4, sizeof(QPR_8Bits), ARM::QPR_8RegClassID, 1, true }, |
| { DTriple, DTripleBits, 2353, 30, sizeof(DTripleBits), ARM::DTripleRegClassID, 1, true }, |
| { DTripleSpc, DTripleSpcBits, 2265, 28, sizeof(DTripleSpcBits), ARM::DTripleSpcRegClassID, 1, true }, |
| { DTripleSpc_with_ssub_0, DTripleSpc_with_ssub_0Bits, 62, 16, sizeof(DTripleSpc_with_ssub_0Bits), ARM::DTripleSpc_with_ssub_0RegClassID, 1, true }, |
| { DTriple_with_ssub_0, DTriple_with_ssub_0Bits, 124, 16, sizeof(DTriple_with_ssub_0Bits), ARM::DTriple_with_ssub_0RegClassID, 1, true }, |
| { DTriple_with_qsub_0_in_QPR, DTriple_with_qsub_0_in_QPRBits, 2039, 15, sizeof(DTriple_with_qsub_0_in_QPRBits), ARM::DTriple_with_qsub_0_in_QPRRegClassID, 1, true }, |
| { DTriple_with_ssub_2, DTriple_with_ssub_2Bits, 218, 15, sizeof(DTriple_with_ssub_2Bits), ARM::DTriple_with_ssub_2RegClassID, 1, true }, |
| { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2158, 15, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true }, |
| { DTripleSpc_with_ssub_4, DTripleSpc_with_ssub_4Bits, 296, 14, sizeof(DTripleSpc_with_ssub_4Bits), ARM::DTripleSpc_with_ssub_4RegClassID, 1, true }, |
| { DTriple_with_ssub_4, DTriple_with_ssub_4Bits, 358, 14, sizeof(DTriple_with_ssub_4Bits), ARM::DTriple_with_ssub_4RegClassID, 1, true }, |
| { DTripleSpc_with_ssub_8, DTripleSpc_with_ssub_8Bits, 1267, 12, sizeof(DTripleSpc_with_ssub_8Bits), ARM::DTripleSpc_with_ssub_8RegClassID, 1, true }, |
| { DTripleSpc_with_dsub_0_in_DPR_8, DTripleSpc_with_dsub_0_in_DPR_8Bits, 454, 8, sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClassID, 1, true }, |
| { DTriple_with_dsub_0_in_DPR_8, DTriple_with_dsub_0_in_DPR_8Bits, 543, 8, sizeof(DTriple_with_dsub_0_in_DPR_8Bits), ARM::DTriple_with_dsub_0_in_DPR_8RegClassID, 1, true }, |
| { DTriple_with_qsub_0_in_MQPR, DTriple_with_qsub_0_in_MQPRBits, 1610, 8, sizeof(DTriple_with_qsub_0_in_MQPRBits), ARM::DTriple_with_qsub_0_in_MQPRRegClassID, 1, true }, |
| { DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2134, 8, sizeof(DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true }, |
| { DTriple_with_dsub_1_in_DPR_8, DTriple_with_dsub_1_in_DPR_8Bits, 626, 7, sizeof(DTriple_with_dsub_1_in_DPR_8Bits), ARM::DTriple_with_dsub_1_in_DPR_8RegClassID, 1, true }, |
| { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, 1983, 7, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, 1, true }, |
| { DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR, DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits, 1586, 7, sizeof(DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits), ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID, 1, true }, |
| { DTripleSpc_with_dsub_2_in_DPR_8, DTripleSpc_with_dsub_2_in_DPR_8Bits, 740, 6, sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClassID, 1, true }, |
| { DTriple_with_dsub_2_in_DPR_8, DTriple_with_dsub_2_in_DPR_8Bits, 829, 6, sizeof(DTriple_with_dsub_2_in_DPR_8Bits), ARM::DTriple_with_dsub_2_in_DPR_8RegClassID, 1, true }, |
| { DTripleSpc_with_dsub_4_in_DPR_8, DTripleSpc_with_dsub_4_in_DPR_8Bits, 943, 4, sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits), ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClassID, 1, true }, |
| { DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, 1950, 4, sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, 1, true }, |
| { DTriple_with_qsub_0_in_QPR_8, DTriple_with_qsub_0_in_QPR_8Bits, 1030, 4, sizeof(DTriple_with_qsub_0_in_QPR_8Bits), ARM::DTriple_with_qsub_0_in_QPR_8RegClassID, 1, true }, |
| { DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR, DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRBits, 1638, 3, sizeof(DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRBits), ARM::DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRRegClassID, 1, true }, |
| { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, 1134, 3, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits), ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID, 1, true }, |
| { DQuadSpc, DQuadSpcBits, 2256, 28, sizeof(DQuadSpcBits), ARM::DQuadSpcRegClassID, 1, true }, |
| { DQuadSpc_with_ssub_0, DQuadSpc_with_ssub_0Bits, 41, 16, sizeof(DQuadSpc_with_ssub_0Bits), ARM::DQuadSpc_with_ssub_0RegClassID, 1, true }, |
| { DQuadSpc_with_ssub_4, DQuadSpc_with_ssub_4Bits, 275, 14, sizeof(DQuadSpc_with_ssub_4Bits), ARM::DQuadSpc_with_ssub_4RegClassID, 1, true }, |
| { DQuadSpc_with_ssub_8, DQuadSpc_with_ssub_8Bits, 1246, 12, sizeof(DQuadSpc_with_ssub_8Bits), ARM::DQuadSpc_with_ssub_8RegClassID, 1, true }, |
| { DQuadSpc_with_dsub_0_in_DPR_8, DQuadSpc_with_dsub_0_in_DPR_8Bits, 424, 8, sizeof(DQuadSpc_with_dsub_0_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClassID, 1, true }, |
| { DQuadSpc_with_dsub_2_in_DPR_8, DQuadSpc_with_dsub_2_in_DPR_8Bits, 710, 6, sizeof(DQuadSpc_with_dsub_2_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClassID, 1, true }, |
| { DQuadSpc_with_dsub_4_in_DPR_8, DQuadSpc_with_dsub_4_in_DPR_8Bits, 913, 4, sizeof(DQuadSpc_with_dsub_4_in_DPR_8Bits), ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClassID, 1, true }, |
| { DQuad, DQuadBits, 2313, 29, sizeof(DQuadBits), ARM::DQuadRegClassID, 1, true }, |
| { DQuad_with_ssub_0, DQuad_with_ssub_0Bits, 106, 16, sizeof(DQuad_with_ssub_0Bits), ARM::DQuad_with_ssub_0RegClassID, 1, true }, |
| { DQuad_with_ssub_2, DQuad_with_ssub_2Bits, 200, 15, sizeof(DQuad_with_ssub_2Bits), ARM::DQuad_with_ssub_2RegClassID, 1, true }, |
| { QQPR, QQPRBits, 2034, 15, sizeof(QQPRBits), ARM::QQPRRegClassID, 1, true }, |
| { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2088, 14, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true }, |
| { DQuad_with_ssub_4, DQuad_with_ssub_4Bits, 340, 14, sizeof(DQuad_with_ssub_4Bits), ARM::DQuad_with_ssub_4RegClassID, 1, true }, |
| { DQuad_with_ssub_6, DQuad_with_ssub_6Bits, 378, 13, sizeof(DQuad_with_ssub_6Bits), ARM::DQuad_with_ssub_6RegClassID, 1, true }, |
| { DQuad_with_dsub_0_in_DPR_8, DQuad_with_dsub_0_in_DPR_8Bits, 516, 8, sizeof(DQuad_with_dsub_0_in_DPR_8Bits), ARM::DQuad_with_dsub_0_in_DPR_8RegClassID, 1, true }, |
| { DQuad_with_qsub_0_in_MQPR, DQuad_with_qsub_0_in_MQPRBits, 1560, 8, sizeof(DQuad_with_qsub_0_in_MQPRBits), ARM::DQuad_with_qsub_0_in_MQPRRegClassID, 1, true }, |
| { DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, 2066, 8, sizeof(DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits), ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID, 1, true }, |
| { DQuad_with_dsub_1_in_DPR_8, DQuad_with_dsub_1_in_DPR_8Bits, 599, 7, sizeof(DQuad_with_dsub_1_in_DPR_8Bits), ARM::DQuad_with_dsub_1_in_DPR_8RegClassID, 1, true }, |
| { DQuad_with_qsub_1_in_MQPR, DQuad_with_qsub_1_in_MQPRBits, 1699, 7, sizeof(DQuad_with_qsub_1_in_MQPRBits), ARM::DQuad_with_qsub_1_in_MQPRRegClassID, 1, true }, |
| { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, 1747, 7, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, 1, true }, |
| { DQuad_with_dsub_2_in_DPR_8, DQuad_with_dsub_2_in_DPR_8Bits, 802, 6, sizeof(DQuad_with_dsub_2_in_DPR_8Bits), ARM::DQuad_with_dsub_2_in_DPR_8RegClassID, 1, true }, |
| { DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, 1725, 6, sizeof(DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, 1, true }, |
| { DQuad_with_dsub_3_in_DPR_8, DQuad_with_dsub_3_in_DPR_8Bits, 858, 5, sizeof(DQuad_with_dsub_3_in_DPR_8Bits), ARM::DQuad_with_dsub_3_in_DPR_8RegClassID, 1, true }, |
| { DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, 1794, 4, sizeof(DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, 1, true }, |
| { DQuad_with_qsub_0_in_QPR_8, DQuad_with_qsub_0_in_QPR_8Bits, 1003, 4, sizeof(DQuad_with_qsub_0_in_QPR_8Bits), ARM::DQuad_with_qsub_0_in_QPR_8RegClassID, 1, true }, |
| { DQuad_with_qsub_1_in_QPR_8, DQuad_with_qsub_1_in_QPR_8Bits, 1059, 3, sizeof(DQuad_with_qsub_1_in_QPR_8Bits), ARM::DQuad_with_qsub_1_in_QPR_8RegClassID, 1, true }, |
| { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, 1086, 3, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits), ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID, 1, true }, |
| { DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, 1872, 2, sizeof(DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits), ARM::DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID, 1, true }, |
| { QQQQPR, QQQQPRBits, 2032, 13, sizeof(QQQQPRBits), ARM::QQQQPRRegClassID, 1, true }, |
| { QQQQPR_with_ssub_0, QQQQPR_with_ssub_0Bits, 0, 8, sizeof(QQQQPR_with_ssub_0Bits), ARM::QQQQPR_with_ssub_0RegClassID, 1, true }, |
| { QQQQPR_with_ssub_4, QQQQPR_with_ssub_4Bits, 256, 7, sizeof(QQQQPR_with_ssub_4Bits), ARM::QQQQPR_with_ssub_4RegClassID, 1, true }, |
| { QQQQPR_with_ssub_8, QQQQPR_with_ssub_8Bits, 1227, 6, sizeof(QQQQPR_with_ssub_8Bits), ARM::QQQQPR_with_ssub_8RegClassID, 1, true }, |
| { QQQQPR_with_ssub_12, QQQQPR_with_ssub_12Bits, 162, 5, sizeof(QQQQPR_with_ssub_12Bits), ARM::QQQQPR_with_ssub_12RegClassID, 1, true }, |
| { QQQQPR_with_dsub_0_in_DPR_8, QQQQPR_with_dsub_0_in_DPR_8Bits, 396, 4, sizeof(QQQQPR_with_dsub_0_in_DPR_8Bits), ARM::QQQQPR_with_dsub_0_in_DPR_8RegClassID, 1, true }, |
| { QQQQPR_with_dsub_2_in_DPR_8, QQQQPR_with_dsub_2_in_DPR_8Bits, 682, 3, sizeof(QQQQPR_with_dsub_2_in_DPR_8Bits), ARM::QQQQPR_with_dsub_2_in_DPR_8RegClassID, 1, true }, |
| { QQQQPR_with_dsub_4_in_DPR_8, QQQQPR_with_dsub_4_in_DPR_8Bits, 885, 2, sizeof(QQQQPR_with_dsub_4_in_DPR_8Bits), ARM::QQQQPR_with_dsub_4_in_DPR_8RegClassID, 1, true }, |
| { QQQQPR_with_dsub_6_in_DPR_8, QQQQPR_with_dsub_6_in_DPR_8Bits, 975, 1, sizeof(QQQQPR_with_dsub_6_in_DPR_8Bits), ARM::QQQQPR_with_dsub_6_in_DPR_8RegClassID, 1, true }, |
| }; |
| |
| // ARM Dwarf<->LLVM register mappings. |
| extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0Dwarf2L[] = { |
| { 0U, ARM::R0 }, |
| { 1U, ARM::R1 }, |
| { 2U, ARM::R2 }, |
| { 3U, ARM::R3 }, |
| { 4U, ARM::R4 }, |
| { 5U, ARM::R5 }, |
| { 6U, ARM::R6 }, |
| { 7U, ARM::R7 }, |
| { 8U, ARM::R8 }, |
| { 9U, ARM::R9 }, |
| { 10U, ARM::R10 }, |
| { 11U, ARM::R11 }, |
| { 12U, ARM::R12 }, |
| { 13U, ARM::SP }, |
| { 14U, ARM::LR }, |
| { 15U, ARM::ZR }, |
| { 256U, ARM::D0 }, |
| { 257U, ARM::D1 }, |
| { 258U, ARM::D2 }, |
| { 259U, ARM::D3 }, |
| { 260U, ARM::D4 }, |
| { 261U, ARM::D5 }, |
| { 262U, ARM::D6 }, |
| { 263U, ARM::D7 }, |
| { 264U, ARM::D8 }, |
| { 265U, ARM::D9 }, |
| { 266U, ARM::D10 }, |
| { 267U, ARM::D11 }, |
| { 268U, ARM::D12 }, |
| { 269U, ARM::D13 }, |
| { 270U, ARM::D14 }, |
| { 271U, ARM::D15 }, |
| { 272U, ARM::D16 }, |
| { 273U, ARM::D17 }, |
| { 274U, ARM::D18 }, |
| { 275U, ARM::D19 }, |
| { 276U, ARM::D20 }, |
| { 277U, ARM::D21 }, |
| { 278U, ARM::D22 }, |
| { 279U, ARM::D23 }, |
| { 280U, ARM::D24 }, |
| { 281U, ARM::D25 }, |
| { 282U, ARM::D26 }, |
| { 283U, ARM::D27 }, |
| { 284U, ARM::D28 }, |
| { 285U, ARM::D29 }, |
| { 286U, ARM::D30 }, |
| { 287U, ARM::D31 }, |
| }; |
| extern const unsigned ARMDwarfFlavour0Dwarf2LSize = array_lengthof(ARMDwarfFlavour0Dwarf2L); |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0Dwarf2L[] = { |
| { 0U, ARM::R0 }, |
| { 1U, ARM::R1 }, |
| { 2U, ARM::R2 }, |
| { 3U, ARM::R3 }, |
| { 4U, ARM::R4 }, |
| { 5U, ARM::R5 }, |
| { 6U, ARM::R6 }, |
| { 7U, ARM::R7 }, |
| { 8U, ARM::R8 }, |
| { 9U, ARM::R9 }, |
| { 10U, ARM::R10 }, |
| { 11U, ARM::R11 }, |
| { 12U, ARM::R12 }, |
| { 13U, ARM::SP }, |
| { 14U, ARM::LR }, |
| { 15U, ARM::ZR }, |
| { 256U, ARM::D0 }, |
| { 257U, ARM::D1 }, |
| { 258U, ARM::D2 }, |
| { 259U, ARM::D3 }, |
| { 260U, ARM::D4 }, |
| { 261U, ARM::D5 }, |
| { 262U, ARM::D6 }, |
| { 263U, ARM::D7 }, |
| { 264U, ARM::D8 }, |
| { 265U, ARM::D9 }, |
| { 266U, ARM::D10 }, |
| { 267U, ARM::D11 }, |
| { 268U, ARM::D12 }, |
| { 269U, ARM::D13 }, |
| { 270U, ARM::D14 }, |
| { 271U, ARM::D15 }, |
| { 272U, ARM::D16 }, |
| { 273U, ARM::D17 }, |
| { 274U, ARM::D18 }, |
| { 275U, ARM::D19 }, |
| { 276U, ARM::D20 }, |
| { 277U, ARM::D21 }, |
| { 278U, ARM::D22 }, |
| { 279U, ARM::D23 }, |
| { 280U, ARM::D24 }, |
| { 281U, ARM::D25 }, |
| { 282U, ARM::D26 }, |
| { 283U, ARM::D27 }, |
| { 284U, ARM::D28 }, |
| { 285U, ARM::D29 }, |
| { 286U, ARM::D30 }, |
| { 287U, ARM::D31 }, |
| }; |
| extern const unsigned ARMEHFlavour0Dwarf2LSize = array_lengthof(ARMEHFlavour0Dwarf2L); |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0L2Dwarf[] = { |
| { ARM::LR, 14U }, |
| { ARM::PC, 15U }, |
| { ARM::SP, 13U }, |
| { ARM::ZR, 15U }, |
| { ARM::D0, 256U }, |
| { ARM::D1, 257U }, |
| { ARM::D2, 258U }, |
| { ARM::D3, 259U }, |
| { ARM::D4, 260U }, |
| { ARM::D5, 261U }, |
| { ARM::D6, 262U }, |
| { ARM::D7, 263U }, |
| { ARM::D8, 264U }, |
| { ARM::D9, 265U }, |
| { ARM::D10, 266U }, |
| { ARM::D11, 267U }, |
| { ARM::D12, 268U }, |
| { ARM::D13, 269U }, |
| { ARM::D14, 270U }, |
| { ARM::D15, 271U }, |
| { ARM::D16, 272U }, |
| { ARM::D17, 273U }, |
| { ARM::D18, 274U }, |
| { ARM::D19, 275U }, |
| { ARM::D20, 276U }, |
| { ARM::D21, 277U }, |
| { ARM::D22, 278U }, |
| { ARM::D23, 279U }, |
| { ARM::D24, 280U }, |
| { ARM::D25, 281U }, |
| { ARM::D26, 282U }, |
| { ARM::D27, 283U }, |
| { ARM::D28, 284U }, |
| { ARM::D29, 285U }, |
| { ARM::D30, 286U }, |
| { ARM::D31, 287U }, |
| { ARM::R0, 0U }, |
| { ARM::R1, 1U }, |
| { ARM::R2, 2U }, |
| { ARM::R3, 3U }, |
| { ARM::R4, 4U }, |
| { ARM::R5, 5U }, |
| { ARM::R6, 6U }, |
| { ARM::R7, 7U }, |
| { ARM::R8, 8U }, |
| { ARM::R9, 9U }, |
| { ARM::R10, 10U }, |
| { ARM::R11, 11U }, |
| { ARM::R12, 12U }, |
| }; |
| extern const unsigned ARMDwarfFlavour0L2DwarfSize = array_lengthof(ARMDwarfFlavour0L2Dwarf); |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0L2Dwarf[] = { |
| { ARM::LR, 14U }, |
| { ARM::PC, 15U }, |
| { ARM::SP, 13U }, |
| { ARM::ZR, 15U }, |
| { ARM::D0, 256U }, |
| { ARM::D1, 257U }, |
| { ARM::D2, 258U }, |
| { ARM::D3, 259U }, |
| { ARM::D4, 260U }, |
| { ARM::D5, 261U }, |
| { ARM::D6, 262U }, |
| { ARM::D7, 263U }, |
| { ARM::D8, 264U }, |
| { ARM::D9, 265U }, |
| { ARM::D10, 266U }, |
| { ARM::D11, 267U }, |
| { ARM::D12, 268U }, |
| { ARM::D13, 269U }, |
| { ARM::D14, 270U }, |
| { ARM::D15, 271U }, |
| { ARM::D16, 272U }, |
| { ARM::D17, 273U }, |
| { ARM::D18, 274U }, |
| { ARM::D19, 275U }, |
| { ARM::D20, 276U }, |
| { ARM::D21, 277U }, |
| { ARM::D22, 278U }, |
| { ARM::D23, 279U }, |
| { ARM::D24, 280U }, |
| { ARM::D25, 281U }, |
| { ARM::D26, 282U }, |
| { ARM::D27, 283U }, |
| { ARM::D28, 284U }, |
| { ARM::D29, 285U }, |
| { ARM::D30, 286U }, |
| { ARM::D31, 287U }, |
| { ARM::R0, 0U }, |
| { ARM::R1, 1U }, |
| { ARM::R2, 2U }, |
| { ARM::R3, 3U }, |
| { ARM::R4, 4U }, |
| { ARM::R5, 5U }, |
| { ARM::R6, 6U }, |
| { ARM::R7, 7U }, |
| { ARM::R8, 8U }, |
| { ARM::R9, 9U }, |
| { ARM::R10, 10U }, |
| { ARM::R11, 11U }, |
| { ARM::R12, 12U }, |
| }; |
| extern const unsigned ARMEHFlavour0L2DwarfSize = array_lengthof(ARMEHFlavour0L2Dwarf); |
| |
| extern const uint16_t ARMRegEncodingTable[] = { |
| 0, |
| 15, |
| 15, |
| 0, |
| 14, |
| 15, |
| 8, |
| 9, |
| 3, |
| 3, |
| 2, |
| 0, |
| 4, |
| 14, |
| 15, |
| 13, |
| 2, |
| 32, |
| 15, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 28, |
| 29, |
| 30, |
| 31, |
| 10, |
| 7, |
| 6, |
| 5, |
| 13, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 28, |
| 29, |
| 30, |
| 31, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 28, |
| 29, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 0, |
| 2, |
| 4, |
| 6, |
| 8, |
| 10, |
| 12, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 28, |
| 29, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 1, |
| 3, |
| 5, |
| 7, |
| 9, |
| 11, |
| 13, |
| 15, |
| 17, |
| 19, |
| 21, |
| 23, |
| 25, |
| 27, |
| 29, |
| 1, |
| 3, |
| 5, |
| 7, |
| 9, |
| 11, |
| 13, |
| 15, |
| 17, |
| 19, |
| 21, |
| 23, |
| 25, |
| 27, |
| }; |
| static inline void InitARMMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { |
| RI->InitMCRegisterInfo(ARMRegDesc, 295, RA, PC, ARMMCRegisterClasses, 122, ARMRegUnitRoots, 83, ARMRegDiffLists, ARMLaneMaskLists, ARMRegStrings, ARMRegClassStrings, ARMSubRegIdxLists, 57, |
| ARMSubRegIdxRanges, ARMRegEncodingTable); |
| |
| switch (DwarfFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| RI->mapDwarfRegsToLLVMRegs(ARMDwarfFlavour0Dwarf2L, ARMDwarfFlavour0Dwarf2LSize, false); |
| break; |
| } |
| switch (EHFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| RI->mapDwarfRegsToLLVMRegs(ARMEHFlavour0Dwarf2L, ARMEHFlavour0Dwarf2LSize, true); |
| break; |
| } |
| switch (DwarfFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| RI->mapLLVMRegsToDwarfRegs(ARMDwarfFlavour0L2Dwarf, ARMDwarfFlavour0L2DwarfSize, false); |
| break; |
| } |
| switch (EHFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| RI->mapLLVMRegsToDwarfRegs(ARMEHFlavour0L2Dwarf, ARMEHFlavour0L2DwarfSize, true); |
| break; |
| } |
| } |
| |
| } // end namespace llvm |
| |
| #endif // GET_REGINFO_MC_DESC |
| |
| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Register Information Header Fragment *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| |
| #ifdef GET_REGINFO_HEADER |
| #undef GET_REGINFO_HEADER |
| |
| #include "llvm/CodeGen/TargetRegisterInfo.h" |
| |
| namespace llvm { |
| |
| class ARMFrameLowering; |
| |
| struct ARMGenRegisterInfo : public TargetRegisterInfo { |
| explicit ARMGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0, |
| unsigned PC = 0, unsigned HwMode = 0); |
| unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override; |
| LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; |
| LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; |
| const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override; |
| const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override; |
| unsigned getRegUnitWeight(unsigned RegUnit) const override; |
| unsigned getNumRegPressureSets() const override; |
| const char *getRegPressureSetName(unsigned Idx) const override; |
| unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override; |
| const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override; |
| const int *getRegUnitPressureSets(unsigned RegUnit) const override; |
| ArrayRef<const char *> getRegMaskNames() const override; |
| ArrayRef<const uint32_t *> getRegMasks() const override; |
| /// Devirtualized TargetFrameLowering. |
| static const ARMFrameLowering *getFrameLowering( |
| const MachineFunction &MF); |
| }; |
| |
| namespace ARM { // Register classes |
| extern const TargetRegisterClass HPRRegClass; |
| extern const TargetRegisterClass FPWithVPRRegClass; |
| extern const TargetRegisterClass SPRRegClass; |
| extern const TargetRegisterClass FPWithVPR_with_ssub_0RegClass; |
| extern const TargetRegisterClass GPRRegClass; |
| extern const TargetRegisterClass GPRwithAPSRRegClass; |
| extern const TargetRegisterClass GPRwithZRRegClass; |
| extern const TargetRegisterClass SPR_8RegClass; |
| extern const TargetRegisterClass GPRnopcRegClass; |
| extern const TargetRegisterClass GPRwithAPSRnospRegClass; |
| extern const TargetRegisterClass GPRwithZRnospRegClass; |
| extern const TargetRegisterClass rGPRRegClass; |
| extern const TargetRegisterClass tGPRwithpcRegClass; |
| extern const TargetRegisterClass FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClass; |
| extern const TargetRegisterClass hGPRRegClass; |
| extern const TargetRegisterClass tGPRRegClass; |
| extern const TargetRegisterClass tGPREvenRegClass; |
| extern const TargetRegisterClass GPRnopc_and_hGPRRegClass; |
| extern const TargetRegisterClass GPRwithAPSRnosp_and_hGPRRegClass; |
| extern const TargetRegisterClass tGPROddRegClass; |
| extern const TargetRegisterClass tcGPRRegClass; |
| extern const TargetRegisterClass hGPR_and_tGPREvenRegClass; |
| extern const TargetRegisterClass tGPR_and_tGPREvenRegClass; |
| extern const TargetRegisterClass tGPR_and_tGPROddRegClass; |
| extern const TargetRegisterClass tGPR_and_tcGPRRegClass; |
| extern const TargetRegisterClass tGPREven_and_tcGPRRegClass; |
| extern const TargetRegisterClass hGPR_and_tGPROddRegClass; |
| extern const TargetRegisterClass tGPREven_and_tGPR_and_tcGPRRegClass; |
| extern const TargetRegisterClass tGPROdd_and_tcGPRRegClass; |
| extern const TargetRegisterClass CCRRegClass; |
| extern const TargetRegisterClass GPRlrRegClass; |
| extern const TargetRegisterClass GPRspRegClass; |
| extern const TargetRegisterClass VCCRRegClass; |
| extern const TargetRegisterClass cl_FPSCR_NZCVRegClass; |
| extern const TargetRegisterClass hGPR_and_tGPRwithpcRegClass; |
| extern const TargetRegisterClass hGPR_and_tcGPRRegClass; |
| extern const TargetRegisterClass DPRRegClass; |
| extern const TargetRegisterClass DPR_VFP2RegClass; |
| extern const TargetRegisterClass DPR_8RegClass; |
| extern const TargetRegisterClass GPRPairRegClass; |
| extern const TargetRegisterClass GPRPairnospRegClass; |
| extern const TargetRegisterClass GPRPair_with_gsub_0_in_tGPRRegClass; |
| extern const TargetRegisterClass GPRPair_with_gsub_0_in_hGPRRegClass; |
| extern const TargetRegisterClass GPRPair_with_gsub_0_in_tcGPRRegClass; |
| extern const TargetRegisterClass GPRPair_with_gsub_1_in_tcGPRRegClass; |
| extern const TargetRegisterClass GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClass; |
| extern const TargetRegisterClass GPRPair_with_gsub_1_in_GPRspRegClass; |
| extern const TargetRegisterClass DPairSpcRegClass; |
| extern const TargetRegisterClass DPairSpc_with_ssub_0RegClass; |
| extern const TargetRegisterClass DPairSpc_with_ssub_4RegClass; |
| extern const TargetRegisterClass DPairSpc_with_dsub_0_in_DPR_8RegClass; |
| extern const TargetRegisterClass DPairSpc_with_dsub_2_in_DPR_8RegClass; |
| extern const TargetRegisterClass DPairRegClass; |
| extern const TargetRegisterClass DPair_with_ssub_0RegClass; |
| extern const TargetRegisterClass QPRRegClass; |
| extern const TargetRegisterClass DPair_with_ssub_2RegClass; |
| extern const TargetRegisterClass DPair_with_dsub_0_in_DPR_8RegClass; |
| extern const TargetRegisterClass MQPRRegClass; |
| extern const TargetRegisterClass QPR_VFP2RegClass; |
| extern const TargetRegisterClass DPair_with_dsub_1_in_DPR_8RegClass; |
| extern const TargetRegisterClass QPR_8RegClass; |
| extern const TargetRegisterClass DTripleRegClass; |
| extern const TargetRegisterClass DTripleSpcRegClass; |
| extern const TargetRegisterClass DTripleSpc_with_ssub_0RegClass; |
| extern const TargetRegisterClass DTriple_with_ssub_0RegClass; |
| extern const TargetRegisterClass DTriple_with_qsub_0_in_QPRRegClass; |
| extern const TargetRegisterClass DTriple_with_ssub_2RegClass; |
| extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass; |
| extern const TargetRegisterClass DTripleSpc_with_ssub_4RegClass; |
| extern const TargetRegisterClass DTriple_with_ssub_4RegClass; |
| extern const TargetRegisterClass DTripleSpc_with_ssub_8RegClass; |
| extern const TargetRegisterClass DTripleSpc_with_dsub_0_in_DPR_8RegClass; |
| extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8RegClass; |
| extern const TargetRegisterClass DTriple_with_qsub_0_in_MQPRRegClass; |
| extern const TargetRegisterClass DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass; |
| extern const TargetRegisterClass DTriple_with_dsub_1_in_DPR_8RegClass; |
| extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass; |
| extern const TargetRegisterClass DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClass; |
| extern const TargetRegisterClass DTripleSpc_with_dsub_2_in_DPR_8RegClass; |
| extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8RegClass; |
| extern const TargetRegisterClass DTripleSpc_with_dsub_4_in_DPR_8RegClass; |
| extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass; |
| extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_8RegClass; |
| extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRRegClass; |
| extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass; |
| extern const TargetRegisterClass DQuadSpcRegClass; |
| extern const TargetRegisterClass DQuadSpc_with_ssub_0RegClass; |
| extern const TargetRegisterClass DQuadSpc_with_ssub_4RegClass; |
| extern const TargetRegisterClass DQuadSpc_with_ssub_8RegClass; |
| extern const TargetRegisterClass DQuadSpc_with_dsub_0_in_DPR_8RegClass; |
| extern const TargetRegisterClass DQuadSpc_with_dsub_2_in_DPR_8RegClass; |
| extern const TargetRegisterClass DQuadSpc_with_dsub_4_in_DPR_8RegClass; |
| extern const TargetRegisterClass DQuadRegClass; |
| extern const TargetRegisterClass DQuad_with_ssub_0RegClass; |
| extern const TargetRegisterClass DQuad_with_ssub_2RegClass; |
| extern const TargetRegisterClass QQPRRegClass; |
| extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass; |
| extern const TargetRegisterClass DQuad_with_ssub_4RegClass; |
| extern const TargetRegisterClass DQuad_with_ssub_6RegClass; |
| extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8RegClass; |
| extern const TargetRegisterClass DQuad_with_qsub_0_in_MQPRRegClass; |
| extern const TargetRegisterClass DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass; |
| extern const TargetRegisterClass DQuad_with_dsub_1_in_DPR_8RegClass; |
| extern const TargetRegisterClass DQuad_with_qsub_1_in_MQPRRegClass; |
| extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass; |
| extern const TargetRegisterClass DQuad_with_dsub_2_in_DPR_8RegClass; |
| extern const TargetRegisterClass DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass; |
| extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8RegClass; |
| extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass; |
| extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_8RegClass; |
| extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_8RegClass; |
| extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass; |
| extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass; |
| extern const TargetRegisterClass QQQQPRRegClass; |
| extern const TargetRegisterClass QQQQPR_with_ssub_0RegClass; |
| extern const TargetRegisterClass QQQQPR_with_ssub_4RegClass; |
| extern const TargetRegisterClass QQQQPR_with_ssub_8RegClass; |
| extern const TargetRegisterClass QQQQPR_with_ssub_12RegClass; |
| extern const TargetRegisterClass QQQQPR_with_dsub_0_in_DPR_8RegClass; |
| extern const TargetRegisterClass QQQQPR_with_dsub_2_in_DPR_8RegClass; |
| extern const TargetRegisterClass QQQQPR_with_dsub_4_in_DPR_8RegClass; |
| extern const TargetRegisterClass QQQQPR_with_dsub_6_in_DPR_8RegClass; |
| } // end namespace ARM |
| |
| } // end namespace llvm |
| |
| #endif // GET_REGINFO_HEADER |
| |
| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Target Register and Register Classes Information *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| |
| #ifdef GET_REGINFO_TARGET_DESC |
| #undef GET_REGINFO_TARGET_DESC |
| |
| namespace llvm { |
| |
| extern const MCRegisterClass ARMMCRegisterClasses[]; |
| |
| static const MVT::SimpleValueType VTLists[] = { |
| /* 0 */ MVT::i32, MVT::Other, |
| /* 2 */ MVT::f16, MVT::Other, |
| /* 4 */ MVT::f32, MVT::Other, |
| /* 6 */ MVT::i32, MVT::v16i1, MVT::v8i1, MVT::v4i1, MVT::Other, |
| /* 11 */ MVT::v2i64, MVT::Other, |
| /* 13 */ MVT::v4i64, MVT::Other, |
| /* 15 */ MVT::v8i64, MVT::Other, |
| /* 17 */ MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64, MVT::v2f32, MVT::v4f16, MVT::Other, |
| /* 25 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::Other, |
| /* 33 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::Other, |
| /* 40 */ MVT::Untyped, MVT::Other, |
| }; |
| |
| static const char *const SubRegIndexNameTable[] = { "dsub_0", "dsub_1", "dsub_2", "dsub_3", "dsub_4", "dsub_5", "dsub_6", "dsub_7", "gsub_0", "gsub_1", "qqsub_0", "qqsub_1", "qsub_0", "qsub_1", "qsub_2", "qsub_3", "ssub_0", "ssub_1", "ssub_2", "ssub_3", "ssub_4", "ssub_5", "ssub_6", "ssub_7", "ssub_8", "ssub_9", "ssub_10", "ssub_11", "ssub_12", "ssub_13", "dsub_7_then_ssub_0", "dsub_7_then_ssub_1", "ssub_0_ssub_1_ssub_4_ssub_5", "ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5", "ssub_2_ssub_3_ssub_6_ssub_7", "ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7", "ssub_2_ssub_3_ssub_4_ssub_5", "ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9", "ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13", "ssub_2_ssub_3_ssub_6_ssub_7_dsub_5", "ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7", "ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9", "ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13", "ssub_6_ssub_7_dsub_5", "ssub_6_ssub_7_ssub_8_ssub_9_dsub_5", "ssub_6_ssub_7_dsub_5_dsub_7", "ssub_6_ssub_7_ssub_8_ssub_9", "ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13", "ssub_8_ssub_9_ssub_12_ssub_13", "ssub_8_ssub_9_dsub_5_ssub_12_ssub_13", "dsub_5_dsub_7", "dsub_5_ssub_12_ssub_13_dsub_7", "dsub_5_ssub_12_ssub_13", "ssub_4_ssub_5_ssub_6_ssub_7_qsub_2", "" }; |
| |
| |
| static const LaneBitmask SubRegIndexLaneMaskTable[] = { |
| LaneBitmask::getAll(), |
| LaneBitmask(0x0000000C), // dsub_0 |
| LaneBitmask(0x00000030), // dsub_1 |
| LaneBitmask(0x000000C0), // dsub_2 |
| LaneBitmask(0x00000300), // dsub_3 |
| LaneBitmask(0x00000C00), // dsub_4 |
| LaneBitmask(0x00003000), // dsub_5 |
| LaneBitmask(0x0000C000), // dsub_6 |
| LaneBitmask(0x00030000), // dsub_7 |
| LaneBitmask(0x00000001), // gsub_0 |
| LaneBitmask(0x00000002), // gsub_1 |
| LaneBitmask(0x000003FC), // qqsub_0 |
| LaneBitmask(0x0003FC00), // qqsub_1 |
| LaneBitmask(0x0000003C), // qsub_0 |
| LaneBitmask(0x000003C0), // qsub_1 |
| LaneBitmask(0x00003C00), // qsub_2 |
| LaneBitmask(0x0003C000), // qsub_3 |
| LaneBitmask(0x00000004), // ssub_0 |
| LaneBitmask(0x00000008), // ssub_1 |
| LaneBitmask(0x00000010), // ssub_2 |
| LaneBitmask(0x00000020), // ssub_3 |
| LaneBitmask(0x00000040), // ssub_4 |
| LaneBitmask(0x00000080), // ssub_5 |
| LaneBitmask(0x00000100), // ssub_6 |
| LaneBitmask(0x00000200), // ssub_7 |
| LaneBitmask(0x00000400), // ssub_8 |
| LaneBitmask(0x00000800), // ssub_9 |
| LaneBitmask(0x00001000), // ssub_10 |
| LaneBitmask(0x00002000), // ssub_11 |
| LaneBitmask(0x00004000), // ssub_12 |
| LaneBitmask(0x00008000), // ssub_13 |
| LaneBitmask(0x00010000), // dsub_7_then_ssub_0 |
| LaneBitmask(0x00020000), // dsub_7_then_ssub_1 |
| LaneBitmask(0x000000CC), // ssub_0_ssub_1_ssub_4_ssub_5 |
| LaneBitmask(0x000000FC), // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| LaneBitmask(0x00000330), // ssub_2_ssub_3_ssub_6_ssub_7 |
| LaneBitmask(0x000003F0), // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| LaneBitmask(0x000000F0), // ssub_2_ssub_3_ssub_4_ssub_5 |
| LaneBitmask(0x00000CCC), // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| LaneBitmask(0x0000CCCC), // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| LaneBitmask(0x00003330), // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| LaneBitmask(0x00033330), // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| LaneBitmask(0x00000FF0), // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| LaneBitmask(0x00000CC0), // ssub_4_ssub_5_ssub_8_ssub_9 |
| LaneBitmask(0x00000FC0), // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| LaneBitmask(0x0000CCC0), // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| LaneBitmask(0x00003300), // ssub_6_ssub_7_dsub_5 |
| LaneBitmask(0x00003F00), // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| LaneBitmask(0x00033300), // ssub_6_ssub_7_dsub_5_dsub_7 |
| LaneBitmask(0x00000F00), // ssub_6_ssub_7_ssub_8_ssub_9 |
| LaneBitmask(0x0000FF00), // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| LaneBitmask(0x0000CC00), // ssub_8_ssub_9_ssub_12_ssub_13 |
| LaneBitmask(0x0000FC00), // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| LaneBitmask(0x00033000), // dsub_5_dsub_7 |
| LaneBitmask(0x0003F000), // dsub_5_ssub_12_ssub_13_dsub_7 |
| LaneBitmask(0x0000F000), // dsub_5_ssub_12_ssub_13 |
| LaneBitmask(0x00003FC0), // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }; |
| |
| |
| |
| static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = { |
| // Mode = 0 (Default) |
| { 16, 16, 32, VTLists+2 }, // HPR |
| { 32, 32, 32, VTLists+4 }, // FPWithVPR |
| { 32, 32, 32, VTLists+4 }, // SPR |
| { 32, 32, 32, VTLists+4 }, // FPWithVPR_with_ssub_0 |
| { 32, 32, 32, VTLists+0 }, // GPR |
| { 32, 32, 32, VTLists+0 }, // GPRwithAPSR |
| { 32, 32, 32, VTLists+0 }, // GPRwithZR |
| { 32, 32, 32, VTLists+4 }, // SPR_8 |
| { 32, 32, 32, VTLists+0 }, // GPRnopc |
| { 32, 32, 32, VTLists+0 }, // GPRwithAPSRnosp |
| { 32, 32, 32, VTLists+0 }, // GPRwithZRnosp |
| { 32, 32, 32, VTLists+0 }, // rGPR |
| { 32, 32, 32, VTLists+0 }, // tGPRwithpc |
| { 32, 32, 32, VTLists+4 }, // FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 |
| { 32, 32, 32, VTLists+0 }, // hGPR |
| { 32, 32, 32, VTLists+0 }, // tGPR |
| { 32, 32, 32, VTLists+0 }, // tGPREven |
| { 32, 32, 32, VTLists+0 }, // GPRnopc_and_hGPR |
| { 32, 32, 32, VTLists+0 }, // GPRwithAPSRnosp_and_hGPR |
| { 32, 32, 32, VTLists+0 }, // tGPROdd |
| { 32, 32, 32, VTLists+0 }, // tcGPR |
| { 32, 32, 32, VTLists+0 }, // hGPR_and_tGPREven |
| { 32, 32, 32, VTLists+0 }, // tGPR_and_tGPREven |
| { 32, 32, 32, VTLists+0 }, // tGPR_and_tGPROdd |
| { 32, 32, 32, VTLists+0 }, // tGPR_and_tcGPR |
| { 32, 32, 32, VTLists+0 }, // tGPREven_and_tcGPR |
| { 32, 32, 32, VTLists+0 }, // hGPR_and_tGPROdd |
| { 32, 32, 32, VTLists+0 }, // tGPREven_and_tGPR_and_tcGPR |
| { 32, 32, 32, VTLists+0 }, // tGPROdd_and_tcGPR |
| { 32, 32, 32, VTLists+0 }, // CCR |
| { 32, 32, 32, VTLists+0 }, // GPRlr |
| { 32, 32, 32, VTLists+0 }, // GPRsp |
| { 32, 32, 32, VTLists+6 }, // VCCR |
| { 32, 32, 32, VTLists+0 }, // cl_FPSCR_NZCV |
| { 32, 32, 32, VTLists+0 }, // hGPR_and_tGPRwithpc |
| { 32, 32, 32, VTLists+0 }, // hGPR_and_tcGPR |
| { 64, 64, 64, VTLists+17 }, // DPR |
| { 64, 64, 64, VTLists+17 }, // DPR_VFP2 |
| { 64, 64, 64, VTLists+17 }, // DPR_8 |
| { 64, 64, 64, VTLists+40 }, // GPRPair |
| { 64, 64, 64, VTLists+40 }, // GPRPairnosp |
| { 64, 64, 64, VTLists+40 }, // GPRPair_with_gsub_0_in_tGPR |
| { 64, 64, 64, VTLists+40 }, // GPRPair_with_gsub_0_in_hGPR |
| { 64, 64, 64, VTLists+40 }, // GPRPair_with_gsub_0_in_tcGPR |
| { 64, 64, 64, VTLists+40 }, // GPRPair_with_gsub_1_in_tcGPR |
| { 64, 64, 64, VTLists+40 }, // GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR |
| { 64, 64, 64, VTLists+40 }, // GPRPair_with_gsub_1_in_GPRsp |
| { 128, 128, 64, VTLists+11 }, // DPairSpc |
| { 128, 128, 64, VTLists+11 }, // DPairSpc_with_ssub_0 |
| { 128, 128, 64, VTLists+11 }, // DPairSpc_with_ssub_4 |
| { 128, 128, 64, VTLists+11 }, // DPairSpc_with_dsub_0_in_DPR_8 |
| { 128, 128, 64, VTLists+11 }, // DPairSpc_with_dsub_2_in_DPR_8 |
| { 128, 128, 128, VTLists+33 }, // DPair |
| { 128, 128, 128, VTLists+33 }, // DPair_with_ssub_0 |
| { 128, 128, 128, VTLists+25 }, // QPR |
| { 128, 128, 128, VTLists+33 }, // DPair_with_ssub_2 |
| { 128, 128, 128, VTLists+33 }, // DPair_with_dsub_0_in_DPR_8 |
| { 128, 128, 128, VTLists+25 }, // MQPR |
| { 128, 128, 128, VTLists+33 }, // QPR_VFP2 |
| { 128, 128, 128, VTLists+33 }, // DPair_with_dsub_1_in_DPR_8 |
| { 128, 128, 128, VTLists+33 }, // QPR_8 |
| { 192, 192, 64, VTLists+40 }, // DTriple |
| { 192, 192, 64, VTLists+40 }, // DTripleSpc |
| { 192, 192, 64, VTLists+40 }, // DTripleSpc_with_ssub_0 |
| { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_0 |
| { 192, 192, 64, VTLists+40 }, // DTriple_with_qsub_0_in_QPR |
| { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_2 |
| { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| { 192, 192, 64, VTLists+40 }, // DTripleSpc_with_ssub_4 |
| { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_4 |
| { 192, 192, 64, VTLists+40 }, // DTripleSpc_with_ssub_8 |
| { 192, 192, 64, VTLists+40 }, // DTripleSpc_with_dsub_0_in_DPR_8 |
| { 192, 192, 64, VTLists+40 }, // DTriple_with_dsub_0_in_DPR_8 |
| { 192, 192, 64, VTLists+40 }, // DTriple_with_qsub_0_in_MQPR |
| { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| { 192, 192, 64, VTLists+40 }, // DTriple_with_dsub_1_in_DPR_8 |
| { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR |
| { 192, 192, 64, VTLists+40 }, // DTripleSpc_with_dsub_2_in_DPR_8 |
| { 192, 192, 64, VTLists+40 }, // DTriple_with_dsub_2_in_DPR_8 |
| { 192, 192, 64, VTLists+40 }, // DTripleSpc_with_dsub_4_in_DPR_8 |
| { 192, 192, 64, VTLists+40 }, // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| { 192, 192, 64, VTLists+40 }, // DTriple_with_qsub_0_in_QPR_8 |
| { 192, 192, 64, VTLists+40 }, // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR |
| { 192, 192, 64, VTLists+40 }, // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| { 256, 256, 64, VTLists+13 }, // DQuadSpc |
| { 256, 256, 64, VTLists+13 }, // DQuadSpc_with_ssub_0 |
| { 256, 256, 64, VTLists+13 }, // DQuadSpc_with_ssub_4 |
| { 256, 256, 64, VTLists+13 }, // DQuadSpc_with_ssub_8 |
| { 256, 256, 64, VTLists+13 }, // DQuadSpc_with_dsub_0_in_DPR_8 |
| { 256, 256, 64, VTLists+13 }, // DQuadSpc_with_dsub_2_in_DPR_8 |
| { 256, 256, 64, VTLists+13 }, // DQuadSpc_with_dsub_4_in_DPR_8 |
| { 256, 256, 256, VTLists+13 }, // DQuad |
| { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_0 |
| { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_2 |
| { 256, 256, 256, VTLists+13 }, // QQPR |
| { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_4 |
| { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_6 |
| { 256, 256, 256, VTLists+13 }, // DQuad_with_dsub_0_in_DPR_8 |
| { 256, 256, 256, VTLists+13 }, // DQuad_with_qsub_0_in_MQPR |
| { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| { 256, 256, 256, VTLists+13 }, // DQuad_with_dsub_1_in_DPR_8 |
| { 256, 256, 256, VTLists+13 }, // DQuad_with_qsub_1_in_MQPR |
| { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| { 256, 256, 256, VTLists+13 }, // DQuad_with_dsub_2_in_DPR_8 |
| { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| { 256, 256, 256, VTLists+13 }, // DQuad_with_dsub_3_in_DPR_8 |
| { 256, 256, 256, VTLists+13 }, // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| { 256, 256, 256, VTLists+13 }, // DQuad_with_qsub_0_in_QPR_8 |
| { 256, 256, 256, VTLists+13 }, // DQuad_with_qsub_1_in_QPR_8 |
| { 256, 256, 256, VTLists+13 }, // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| { 256, 256, 256, VTLists+13 }, // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| { 512, 512, 256, VTLists+15 }, // QQQQPR |
| { 512, 512, 256, VTLists+15 }, // QQQQPR_with_ssub_0 |
| { 512, 512, 256, VTLists+15 }, // QQQQPR_with_ssub_4 |
| { 512, 512, 256, VTLists+15 }, // QQQQPR_with_ssub_8 |
| { 512, 512, 256, VTLists+15 }, // QQQQPR_with_ssub_12 |
| { 512, 512, 256, VTLists+15 }, // QQQQPR_with_dsub_0_in_DPR_8 |
| { 512, 512, 256, VTLists+15 }, // QQQQPR_with_dsub_2_in_DPR_8 |
| { 512, 512, 256, VTLists+15 }, // QQQQPR_with_dsub_4_in_DPR_8 |
| { 512, 512, 256, VTLists+15 }, // QQQQPR_with_dsub_6_in_DPR_8 |
| }; |
| |
| static const TargetRegisterClass *const NullRegClasses[] = { nullptr }; |
| |
| static const uint32_t HPRSubClassMask[] = { |
| 0x00000085, 0x00000000, 0x00000000, 0x00000000, |
| 0x00002008, 0x9faf0060, 0x6fdffff5, 0x03fdfffe, // ssub_0 |
| 0x00002008, 0x9faf0060, 0x6fdffff5, 0x03fdfffe, // ssub_1 |
| 0x00000000, 0x1f800000, 0x401ebb24, 0x03fdffde, // ssub_2 |
| 0x00000000, 0x1f800000, 0x401ebb24, 0x03fdffde, // ssub_3 |
| 0x00000000, 0x000e0000, 0x0f9ff9f0, 0x03f9ffce, // ssub_4 |
| 0x00000000, 0x000e0000, 0x0f9ff9f0, 0x03f9ffce, // ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // ssub_6 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // ssub_7 |
| 0x00000000, 0x00000000, 0x0f0140c0, 0x03f00000, // ssub_8 |
| 0x00000000, 0x00000000, 0x0f0140c0, 0x03f00000, // ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_10 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_11 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_12 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_7_then_ssub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_7_then_ssub_1 |
| }; |
| |
| static const uint32_t FPWithVPRSubClassMask[] = { |
| 0x0000208e, 0x00000071, 0x00000000, 0x00000000, |
| 0x00000000, 0xffff8000, 0xffffffff, 0x03ffffff, // dsub_0 |
| 0x00000000, 0x3ff00000, 0xf01ebf2f, 0x03ffffff, // dsub_1 |
| 0x00000000, 0xe00f8000, 0xffffffff, 0x03ffffff, // dsub_2 |
| 0x00000000, 0x00000000, 0xf0000000, 0x03ffffff, // dsub_3 |
| 0x00000000, 0xc0000000, 0x0fe140d0, 0x03fe0000, // dsub_4 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // dsub_6 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // dsub_7 |
| 0x00002008, 0x9faf0060, 0x6fdffff5, 0x03fdfffe, // ssub_0 |
| 0x00002008, 0x9faf0060, 0x6fdffff5, 0x03fdfffe, // ssub_1 |
| 0x00000000, 0x1f800000, 0x401ebb24, 0x03fdffde, // ssub_2 |
| 0x00000000, 0x1f800000, 0x401ebb24, 0x03fdffde, // ssub_3 |
| 0x00000000, 0x000e0000, 0x0f9ff9f0, 0x03f9ffce, // ssub_4 |
| 0x00000000, 0x000e0000, 0x0f9ff9f0, 0x03f9ffce, // ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // ssub_6 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // ssub_7 |
| 0x00000000, 0x00000000, 0x0f0140c0, 0x03f00000, // ssub_8 |
| 0x00000000, 0x00000000, 0x0f0140c0, 0x03f00000, // ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_10 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_11 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_12 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_7_then_ssub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_7_then_ssub_1 |
| }; |
| |
| static const uint32_t SPRSubClassMask[] = { |
| 0x00000084, 0x00000000, 0x00000000, 0x00000000, |
| 0x00002008, 0x9faf0060, 0x6fdffff5, 0x03fdfffe, // ssub_0 |
| 0x00002008, 0x9faf0060, 0x6fdffff5, 0x03fdfffe, // ssub_1 |
| 0x00000000, 0x1f800000, 0x401ebb24, 0x03fdffde, // ssub_2 |
| 0x00000000, 0x1f800000, 0x401ebb24, 0x03fdffde, // ssub_3 |
| 0x00000000, 0x000e0000, 0x0f9ff9f0, 0x03f9ffce, // ssub_4 |
| 0x00000000, 0x000e0000, 0x0f9ff9f0, 0x03f9ffce, // ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // ssub_6 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // ssub_7 |
| 0x00000000, 0x00000000, 0x0f0140c0, 0x03f00000, // ssub_8 |
| 0x00000000, 0x00000000, 0x0f0140c0, 0x03f00000, // ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_10 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_11 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_12 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_7_then_ssub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_7_then_ssub_1 |
| }; |
| |
| static const uint32_t FPWithVPR_with_ssub_0SubClassMask[] = { |
| 0x00002008, 0x00000060, 0x00000000, 0x00000000, |
| 0x00000000, 0x9faf0000, 0x6fdffff5, 0x03fdfffe, // dsub_0 |
| 0x00000000, 0x1f800000, 0x401ebb24, 0x03fdffde, // dsub_1 |
| 0x00000000, 0x000e0000, 0x0f9ff9f0, 0x03f9ffce, // dsub_2 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // dsub_3 |
| 0x00000000, 0x00000000, 0x0f0140c0, 0x03f00000, // dsub_4 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_6 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_7 |
| }; |
| |
| static const uint32_t GPRSubClassMask[] = { |
| 0xdfffd910, 0x0000000c, 0x00000000, 0x00000000, |
| 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_0 |
| 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_1 |
| }; |
| |
| static const uint32_t GPRwithAPSRSubClassMask[] = { |
| 0xdfff8920, 0x00000008, 0x00000000, 0x00000000, |
| 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_0 |
| 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_1 |
| }; |
| |
| static const uint32_t GPRwithZRSubClassMask[] = { |
| 0xdfff8d40, 0x00000008, 0x00000000, 0x00000000, |
| 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_0 |
| 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_1 |
| }; |
| |
| static const uint32_t SPR_8SubClassMask[] = { |
| 0x00000080, 0x00000000, 0x00000000, 0x00000000, |
| 0x00002000, 0x190c0040, 0x0e1fc980, 0x03c1fa48, // ssub_0 |
| 0x00002000, 0x190c0040, 0x0e1fc980, 0x03c1fa48, // ssub_1 |
| 0x00000000, 0x18000000, 0x001c8800, 0x03c1ea40, // ssub_2 |
| 0x00000000, 0x18000000, 0x001c8800, 0x03c1ea40, // ssub_3 |
| 0x00000000, 0x00080000, 0x0c19c000, 0x0381ca00, // ssub_4 |
| 0x00000000, 0x00080000, 0x0c19c000, 0x0381ca00, // ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03814800, // ssub_6 |
| 0x00000000, 0x00000000, 0x00000000, 0x03814800, // ssub_7 |
| 0x00000000, 0x00000000, 0x08010000, 0x03000000, // ssub_8 |
| 0x00000000, 0x00000000, 0x08010000, 0x03000000, // ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_10 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_11 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_12 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_7_then_ssub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_7_then_ssub_1 |
| }; |
| |
| static const uint32_t GPRnopcSubClassMask[] = { |
| 0xdfff8900, 0x00000008, 0x00000000, 0x00000000, |
| 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_0 |
| 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_1 |
| }; |
| |
| static const uint32_t GPRwithAPSRnospSubClassMask[] = { |
| 0x5ffd8a00, 0x00000008, 0x00000000, 0x00000000, |
| 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_0 |
| 0x00000000, 0x00003300, 0x00000000, 0x00000000, // gsub_1 |
| }; |
| |
| static const uint32_t GPRwithZRnospSubClassMask[] = { |
| 0x5ffd8c00, 0x00000008, 0x00000000, 0x00000000, |
| 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_0 |
| 0x00000000, 0x00003300, 0x00000000, 0x00000000, // gsub_1 |
| }; |
| |
| static const uint32_t rGPRSubClassMask[] = { |
| 0x5ffd8800, 0x00000008, 0x00000000, 0x00000000, |
| 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_0 |
| 0x00000000, 0x00003300, 0x00000000, 0x00000000, // gsub_1 |
| }; |
| |
| static const uint32_t tGPRwithpcSubClassMask[] = { |
| 0x19c09000, 0x00000004, 0x00000000, 0x00000000, |
| 0x00000000, 0x00001200, 0x00000000, 0x00000000, // gsub_0 |
| 0x00000000, 0x00001200, 0x00000000, 0x00000000, // gsub_1 |
| }; |
| |
| static const uint32_t FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8SubClassMask[] = { |
| 0x00002000, 0x00000040, 0x00000000, 0x00000000, |
| 0x00000000, 0x190c0000, 0x0e1fc980, 0x03c1fa48, // dsub_0 |
| 0x00000000, 0x18000000, 0x001c8800, 0x03c1ea40, // dsub_1 |
| 0x00000000, 0x00080000, 0x0c19c000, 0x0381ca00, // dsub_2 |
| 0x00000000, 0x00000000, 0x00000000, 0x03814800, // dsub_3 |
| 0x00000000, 0x00000000, 0x08010000, 0x03000000, // dsub_4 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_6 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_7 |
| }; |
| |
| static const uint32_t hGPRSubClassMask[] = { |
| 0xc4264000, 0x0000000c, 0x00000000, 0x00000000, |
| 0x00000000, 0x00006400, 0x00000000, 0x00000000, // gsub_0 |
| 0x00000000, 0x00006400, 0x00000000, 0x00000000, // gsub_1 |
| }; |
| |
| static const uint32_t tGPRSubClassMask[] = { |
| 0x19c08000, 0x00000000, 0x00000000, 0x00000000, |
| 0x00000000, 0x00001200, 0x00000000, 0x00000000, // gsub_0 |
| 0x00000000, 0x00001200, 0x00000000, 0x00000000, // gsub_1 |
| }; |
| |
| static const uint32_t tGPREvenSubClassMask[] = { |
| 0x4a610000, 0x00000008, 0x00000000, 0x00000000, |
| 0x00000000, 0x00007f80, 0x00000000, 0x00000000, // gsub_0 |
| }; |
| |
| static const uint32_t GPRnopc_and_hGPRSubClassMask[] = { |
| 0xc4260000, 0x00000008, 0x00000000, 0x00000000, |
| 0x00000000, 0x00006400, 0x00000000, 0x00000000, // gsub_0 |
| 0x00000000, 0x00006400, 0x00000000, 0x00000000, // gsub_1 |
| }; |
| |
| static const uint32_t GPRwithAPSRnosp_and_hGPRSubClassMask[] = { |
| 0x44240000, 0x00000008, 0x00000000, 0x00000000, |
| 0x00000000, 0x00006400, 0x00000000, 0x00000000, // gsub_0 |
| 0x00000000, 0x00002000, 0x00000000, 0x00000000, // gsub_1 |
| }; |
| |
| static const uint32_t tGPROddSubClassMask[] = { |
| 0x14880000, 0x00000000, 0x00000000, 0x00000000, |
| 0x00000000, 0x00003300, 0x00000000, 0x00000000, // gsub_1 |
| }; |
| |
| static const uint32_t tcGPRSubClassMask[] = { |
| 0x1b100000, 0x00000008, 0x00000000, 0x00000000, |
| 0x00000000, 0x00005800, 0x00000000, 0x00000000, // gsub_0 |
| 0x00000000, 0x00001000, 0x00000000, 0x00000000, // gsub_1 |
| }; |
| |
| static const uint32_t hGPR_and_tGPREvenSubClassMask[] = { |
| 0x40200000, 0x00000008, 0x00000000, 0x00000000, |
| 0x00000000, 0x00006400, 0x00000000, 0x00000000, // gsub_0 |
| }; |
| |
| static const uint32_t tGPR_and_tGPREvenSubClassMask[] = { |
| 0x08400000, 0x00000000, 0x00000000, 0x00000000, |
| 0x00000000, 0x00001200, 0x00000000, 0x00000000, // gsub_0 |
| }; |
| |
| static const uint32_t tGPR_and_tGPROddSubClassMask[] = { |
| 0x10800000, 0x00000000, 0x00000000, 0x00000000, |
| 0x00000000, 0x00001200, 0x00000000, 0x00000000, // gsub_1 |
| }; |
| |
| static const uint32_t tGPR_and_tcGPRSubClassMask[] = { |
| 0x19000000, 0x00000000, 0x00000000, 0x00000000, |
| 0x00000000, 0x00001000, 0x00000000, 0x00000000, // gsub_0 |
| 0x00000000, 0x00001000, 0x00000000, 0x00000000, // gsub_1 |
| }; |
| |
| static const uint32_t tGPREven_and_tcGPRSubClassMask[] = { |
| 0x0a000000, 0x00000008, 0x00000000, 0x00000000, |
| 0x00000000, 0x00005800, 0x00000000, 0x00000000, // gsub_0 |
| }; |
| |
| static const uint32_t hGPR_and_tGPROddSubClassMask[] = { |
| 0x04000000, 0x00000000, 0x00000000, 0x00000000, |
| 0x00000000, 0x00002000, 0x00000000, 0x00000000, // gsub_1 |
| }; |
| |
| static const uint32_t tGPREven_and_tGPR_and_tcGPRSubClassMask[] = { |
| 0x08000000, 0x00000000, 0x00000000, 0x00000000, |
| 0x00000000, 0x00001000, 0x00000000, 0x00000000, // gsub_0 |
| }; |
| |
| static const uint32_t tGPROdd_and_tcGPRSubClassMask[] = { |
| 0x10000000, 0x00000000, 0x00000000, 0x00000000, |
| 0x00000000, 0x00001000, 0x00000000, 0x00000000, // gsub_1 |
| }; |
| |
| static const uint32_t CCRSubClassMask[] = { |
| 0x20000000, 0x00000000, 0x00000000, 0x00000000, |
| }; |
| |
| static const uint32_t GPRlrSubClassMask[] = { |
| 0x40000000, 0x00000000, 0x00000000, 0x00000000, |
| }; |
| |
| static const uint32_t GPRspSubClassMask[] = { |
| 0x80000000, 0x00000000, 0x00000000, 0x00000000, |
| 0x00000000, 0x00004000, 0x00000000, 0x00000000, // gsub_1 |
| }; |
| |
| static const uint32_t VCCRSubClassMask[] = { |
| 0x00000000, 0x00000001, 0x00000000, 0x00000000, |
| }; |
| |
| static const uint32_t cl_FPSCR_NZCVSubClassMask[] = { |
| 0x00000000, 0x00000002, 0x00000000, 0x00000000, |
| }; |
| |
| static const uint32_t hGPR_and_tGPRwithpcSubClassMask[] = { |
| 0x00000000, 0x00000004, 0x00000000, 0x00000000, |
| }; |
| |
| static const uint32_t hGPR_and_tcGPRSubClassMask[] = { |
| 0x00000000, 0x00000008, 0x00000000, 0x00000000, |
| 0x00000000, 0x00004000, 0x00000000, 0x00000000, // gsub_0 |
| }; |
| |
| static const uint32_t DPRSubClassMask[] = { |
| 0x00000000, 0x00000070, 0x00000000, 0x00000000, |
| 0x00000000, 0xffff8000, 0xffffffff, 0x03ffffff, // dsub_0 |
| 0x00000000, 0x3ff00000, 0xf01ebf2f, 0x03ffffff, // dsub_1 |
| 0x00000000, 0xe00f8000, 0xffffffff, 0x03ffffff, // dsub_2 |
| 0x00000000, 0x00000000, 0xf0000000, 0x03ffffff, // dsub_3 |
| 0x00000000, 0xc0000000, 0x0fe140d0, 0x03fe0000, // dsub_4 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // dsub_6 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // dsub_7 |
| }; |
| |
| static const uint32_t DPR_VFP2SubClassMask[] = { |
| 0x00000000, 0x00000060, 0x00000000, 0x00000000, |
| 0x00000000, 0x9faf0000, 0x6fdffff5, 0x03fdfffe, // dsub_0 |
| 0x00000000, 0x1f800000, 0x401ebb24, 0x03fdffde, // dsub_1 |
| 0x00000000, 0x000e0000, 0x0f9ff9f0, 0x03f9ffce, // dsub_2 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // dsub_3 |
| 0x00000000, 0x00000000, 0x0f0140c0, 0x03f00000, // dsub_4 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_6 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_7 |
| }; |
| |
| static const uint32_t DPR_8SubClassMask[] = { |
| 0x00000000, 0x00000040, 0x00000000, 0x00000000, |
| 0x00000000, 0x190c0000, 0x0e1fc980, 0x03c1fa48, // dsub_0 |
| 0x00000000, 0x18000000, 0x001c8800, 0x03c1ea40, // dsub_1 |
| 0x00000000, 0x00080000, 0x0c19c000, 0x0381ca00, // dsub_2 |
| 0x00000000, 0x00000000, 0x00000000, 0x03814800, // dsub_3 |
| 0x00000000, 0x00000000, 0x08010000, 0x03000000, // dsub_4 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_6 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_7 |
| }; |
| |
| static const uint32_t GPRPairSubClassMask[] = { |
| 0x00000000, 0x00007f80, 0x00000000, 0x00000000, |
| }; |
| |
| static const uint32_t GPRPairnospSubClassMask[] = { |
| 0x00000000, 0x00003300, 0x00000000, 0x00000000, |
| }; |
| |
| static const uint32_t GPRPair_with_gsub_0_in_tGPRSubClassMask[] = { |
| 0x00000000, 0x00001200, 0x00000000, 0x00000000, |
| }; |
| |
| static const uint32_t GPRPair_with_gsub_0_in_hGPRSubClassMask[] = { |
| 0x00000000, 0x00006400, 0x00000000, 0x00000000, |
| }; |
| |
| static const uint32_t GPRPair_with_gsub_0_in_tcGPRSubClassMask[] = { |
| 0x00000000, 0x00005800, 0x00000000, 0x00000000, |
| }; |
| |
| static const uint32_t GPRPair_with_gsub_1_in_tcGPRSubClassMask[] = { |
| 0x00000000, 0x00001000, 0x00000000, 0x00000000, |
| }; |
| |
| static const uint32_t GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRSubClassMask[] = { |
| 0x00000000, 0x00002000, 0x00000000, 0x00000000, |
| }; |
| |
| static const uint32_t GPRPair_with_gsub_1_in_GPRspSubClassMask[] = { |
| 0x00000000, 0x00004000, 0x00000000, 0x00000000, |
| }; |
| |
| static const uint32_t DPairSpcSubClassMask[] = { |
| 0x00000000, 0x000f8000, 0x00000000, 0x00000000, |
| 0x00000000, 0xe0000000, 0xffffffff, 0x03ffffff, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0xf0000000, 0x03ffffff, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0x00000000, 0xc0000000, 0x0fe140d0, 0x03fe0000, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_6_ssub_7_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // dsub_5_dsub_7 |
| }; |
| |
| static const uint32_t DPairSpc_with_ssub_0SubClassMask[] = { |
| 0x00000000, 0x000f0000, 0x00000000, 0x00000000, |
| 0x00000000, 0x80000000, 0x6fdffff5, 0x03fdfffe, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x40000000, 0x03fdffde, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x0f8140d0, 0x03f80000, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_6_ssub_7_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // dsub_5_dsub_7 |
| }; |
| |
| static const uint32_t DPairSpc_with_ssub_4SubClassMask[] = { |
| 0x00000000, 0x000e0000, 0x00000000, 0x00000000, |
| 0x00000000, 0x00000000, 0x0f9ff9f0, 0x03f9ffce, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x0f0140c0, 0x03f00000, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_6_ssub_7_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_5_dsub_7 |
| }; |
| |
| static const uint32_t DPairSpc_with_dsub_0_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x000c0000, 0x00000000, 0x00000000, |
| 0x00000000, 0x00000000, 0x0e1fc980, 0x03c1fa48, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03c1ea40, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x0c014000, 0x03800000, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_6_ssub_7_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // dsub_5_dsub_7 |
| }; |
| |
| static const uint32_t DPairSpc_with_dsub_2_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x00080000, 0x00000000, 0x00000000, |
| 0x00000000, 0x00000000, 0x0c19c000, 0x0381ca00, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03814800, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x08010000, 0x03000000, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_6_ssub_7_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_5_dsub_7 |
| }; |
| |
| static const uint32_t DPairSubClassMask[] = { |
| 0x00000000, 0x1ff00000, 0x00000000, 0x00000000, |
| 0x00000000, 0x20000000, 0xf01ebf2f, 0x03ffffff, // qsub_0 |
| 0x00000000, 0x00000000, 0xf0000000, 0x03ffffff, // qsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // qsub_2 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // qsub_3 |
| 0x00000000, 0x20000000, 0xf01ebf2f, 0x03ffffff, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // dsub_5_ssub_12_ssub_13 |
| }; |
| |
| static const uint32_t DPair_with_ssub_0SubClassMask[] = { |
| 0x00000000, 0x1fa00000, 0x00000000, 0x00000000, |
| 0x00000000, 0x00000000, 0x601ebf25, 0x03fdfffe, // qsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f9ffce, // qsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // qsub_2 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // qsub_3 |
| 0x00000000, 0x00000000, 0x401ebb24, 0x03fdffde, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // dsub_5_ssub_12_ssub_13 |
| }; |
| |
| static const uint32_t QPRSubClassMask[] = { |
| 0x00000000, 0x16400000, 0x00000000, 0x00000000, |
| 0x00000000, 0x00000000, 0x800c2202, 0x03fe6090, // qsub_0 |
| 0x00000000, 0x00000000, 0x80000000, 0x03fe6090, // qsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // qsub_2 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // qsub_3 |
| 0x00000000, 0x00000000, 0x00121408, 0x00019521, // ssub_2_ssub_3_ssub_4_ssub_5 |
| }; |
| |
| static const uint32_t DPair_with_ssub_2SubClassMask[] = { |
| 0x00000000, 0x1f800000, 0x00000000, 0x00000000, |
| 0x00000000, 0x00000000, 0x401ebb24, 0x03fdffde, // qsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // qsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // qsub_2 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // qsub_3 |
| 0x00000000, 0x00000000, 0x001eb920, 0x03f9ffce, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_5_ssub_12_ssub_13 |
| }; |
| |
| static const uint32_t DPair_with_dsub_0_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x19000000, 0x00000000, 0x00000000, |
| 0x00000000, 0x00000000, 0x001e8900, 0x03c1fa48, // qsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x0381ca00, // qsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // qsub_2 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // qsub_3 |
| 0x00000000, 0x00000000, 0x001c8800, 0x03c1ea40, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // dsub_5_ssub_12_ssub_13 |
| }; |
| |
| static const uint32_t MQPRSubClassMask[] = { |
| 0x00000000, 0x16000000, 0x00000000, 0x00000000, |
| 0x00000000, 0x00000000, 0x000c2200, 0x03fc6090, // qsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f86080, // qsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // qsub_2 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // qsub_3 |
| 0x00000000, 0x00000000, 0x00121000, 0x00019500, // ssub_2_ssub_3_ssub_4_ssub_5 |
| }; |
| |
| static const uint32_t QPR_VFP2SubClassMask[] = { |
| 0x00000000, 0x16000000, 0x00000000, 0x00000000, |
| 0x00000000, 0x00000000, 0x000c2200, 0x03fc6090, // qsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f86080, // qsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // qsub_2 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // qsub_3 |
| 0x00000000, 0x00000000, 0x00121000, 0x00019500, // ssub_2_ssub_3_ssub_4_ssub_5 |
| }; |
| |
| static const uint32_t DPair_with_dsub_1_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x18000000, 0x00000000, 0x00000000, |
| 0x00000000, 0x00000000, 0x001c8800, 0x03c1ea40, // qsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x03814800, // qsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // qsub_2 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // qsub_3 |
| 0x00000000, 0x00000000, 0x00188000, 0x0381ca00, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_5_ssub_12_ssub_13 |
| }; |
| |
| static const uint32_t QPR_8SubClassMask[] = { |
| 0x00000000, 0x10000000, 0x00000000, 0x00000000, |
| 0x00000000, 0x00000000, 0x000c0000, 0x03c06000, // qsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x03804000, // qsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // qsub_2 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // qsub_3 |
| 0x00000000, 0x00000000, 0x00100000, 0x00018000, // ssub_2_ssub_3_ssub_4_ssub_5 |
| }; |
| |
| static const uint32_t DTripleSubClassMask[] = { |
| 0x00000000, 0x20000000, 0x001ebf2f, 0x00000000, |
| 0x00000000, 0x00000000, 0xf0000000, 0x03ffffff, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0xf0000000, 0x03ffffff, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // dsub_5_ssub_12_ssub_13_dsub_7 |
| }; |
| |
| static const uint32_t DTripleSpcSubClassMask[] = { |
| 0x00000000, 0xc0000000, 0x0fe140d0, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_6_ssub_7_dsub_5_dsub_7 |
| }; |
| |
| static const uint32_t DTripleSpc_with_ssub_0SubClassMask[] = { |
| 0x00000000, 0x80000000, 0x0fc140d0, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03fc0000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fc0000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_6_ssub_7_dsub_5_dsub_7 |
| }; |
| |
| static const uint32_t DTriple_with_ssub_0SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x001ebf25, 0x00000000, |
| 0x00000000, 0x00000000, 0x60000000, 0x03fdfffe, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x40000000, 0x03fdffde, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // dsub_5_ssub_12_ssub_13_dsub_7 |
| }; |
| |
| static const uint32_t DTriple_with_qsub_0_in_QPRSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x000c2202, 0x00000000, |
| 0x00000000, 0x00000000, 0x80000000, 0x03fe6090, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x00019521, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| }; |
| |
| static const uint32_t DTriple_with_ssub_2SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x001ebb24, 0x00000000, |
| 0x00000000, 0x00000000, 0x40000000, 0x03fdffde, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f9ffce, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_5_ssub_12_ssub_13_dsub_7 |
| }; |
| |
| static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00121408, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x00019521, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x80000000, 0x03fe6090, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // dsub_5_ssub_12_ssub_13_dsub_7 |
| }; |
| |
| static const uint32_t DTripleSpc_with_ssub_4SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x0f8140d0, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_6_ssub_7_dsub_5_dsub_7 |
| }; |
| |
| static const uint32_t DTriple_with_ssub_4SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x001eb920, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03f9ffce, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f9fecc, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_5_ssub_12_ssub_13_dsub_7 |
| }; |
| |
| static const uint32_t DTripleSpc_with_ssub_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x0f0140c0, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_6_ssub_7_dsub_5_dsub_7 |
| }; |
| |
| static const uint32_t DTripleSpc_with_dsub_0_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x0e014080, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03c00000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03c00000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_6_ssub_7_dsub_5_dsub_7 |
| }; |
| |
| static const uint32_t DTriple_with_dsub_0_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x001e8900, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03c1fa48, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03c1ea40, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // dsub_5_ssub_12_ssub_13_dsub_7 |
| }; |
| |
| static const uint32_t DTriple_with_qsub_0_in_MQPRSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x000c2200, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03fc6090, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x00019500, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| }; |
| |
| static const uint32_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00121400, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x00019520, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fc6090, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // dsub_5_ssub_12_ssub_13_dsub_7 |
| }; |
| |
| static const uint32_t DTriple_with_dsub_1_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x001c8800, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03c1ea40, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x0381ca00, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_5_ssub_12_ssub_13_dsub_7 |
| }; |
| |
| static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00121000, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x00019500, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f86080, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // dsub_5_ssub_12_ssub_13_dsub_7 |
| }; |
| |
| static const uint32_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x000c2000, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03f86080, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x00019400, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| }; |
| |
| static const uint32_t DTripleSpc_with_dsub_2_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x0c014000, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_6_ssub_7_dsub_5_dsub_7 |
| }; |
| |
| static const uint32_t DTriple_with_dsub_2_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00188000, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x0381ca00, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03814800, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_5_ssub_12_ssub_13_dsub_7 |
| }; |
| |
| static const uint32_t DTripleSpc_with_dsub_4_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x08010000, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_6_ssub_7_dsub_5_dsub_7 |
| }; |
| |
| static const uint32_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00120000, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x00019000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03c06000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // dsub_5_ssub_12_ssub_13_dsub_7 |
| }; |
| |
| static const uint32_t DTriple_with_qsub_0_in_QPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x000c0000, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03c06000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x00018000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| }; |
| |
| static const uint32_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00080000, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03804000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x00010000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| }; |
| |
| static const uint32_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00100000, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x00018000, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03804000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // dsub_5_ssub_12_ssub_13_dsub_7 |
| }; |
| |
| static const uint32_t DQuadSpcSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x0fe00000, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_6_ssub_7_dsub_5_dsub_7 |
| }; |
| |
| static const uint32_t DQuadSpc_with_ssub_0SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x0fc00000, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03fc0000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fc0000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_6_ssub_7_dsub_5_dsub_7 |
| }; |
| |
| static const uint32_t DQuadSpc_with_ssub_4SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x0f800000, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_6_ssub_7_dsub_5_dsub_7 |
| }; |
| |
| static const uint32_t DQuadSpc_with_ssub_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x0f000000, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_6_ssub_7_dsub_5_dsub_7 |
| }; |
| |
| static const uint32_t DQuadSpc_with_dsub_0_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x0e000000, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03c00000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03c00000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_6_ssub_7_dsub_5_dsub_7 |
| }; |
| |
| static const uint32_t DQuadSpc_with_dsub_2_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x0c000000, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_6_ssub_7_dsub_5_dsub_7 |
| }; |
| |
| static const uint32_t DQuadSpc_with_dsub_4_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x08000000, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_6_ssub_7_dsub_5_dsub_7 |
| }; |
| |
| static const uint32_t DQuadSubClassMask[] = { |
| 0x00000000, 0x00000000, 0xf0000000, 0x0001ffff, |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // qqsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // qqsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }; |
| |
| static const uint32_t DQuad_with_ssub_0SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x60000000, 0x0001fffe, |
| 0x00000000, 0x00000000, 0x00000000, 0x03fc0000, // qqsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // qqsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fc0000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }; |
| |
| static const uint32_t DQuad_with_ssub_2SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x40000000, 0x0001ffde, |
| 0x00000000, 0x00000000, 0x00000000, 0x03fc0000, // qqsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // qqsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }; |
| |
| static const uint32_t QQPRSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x80000000, 0x00006090, |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // qqsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // qqsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }; |
| |
| static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x00019521, |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| }; |
| |
| static const uint32_t DQuad_with_ssub_4SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x0001ffce, |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // qqsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // qqsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }; |
| |
| static const uint32_t DQuad_with_ssub_6SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x0001fecc, |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // qqsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // qqsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }; |
| |
| static const uint32_t DQuad_with_dsub_0_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x0001fa48, |
| 0x00000000, 0x00000000, 0x00000000, 0x03c00000, // qqsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // qqsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03c00000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }; |
| |
| static const uint32_t DQuad_with_qsub_0_in_MQPRSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x00006090, |
| 0x00000000, 0x00000000, 0x00000000, 0x03fc0000, // qqsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // qqsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }; |
| |
| static const uint32_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x00019520, |
| 0x00000000, 0x00000000, 0x00000000, 0x03fc0000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| }; |
| |
| static const uint32_t DQuad_with_dsub_1_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x0001ea40, |
| 0x00000000, 0x00000000, 0x00000000, 0x03c00000, // qqsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // qqsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }; |
| |
| static const uint32_t DQuad_with_qsub_1_in_MQPRSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x00006080, |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // qqsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // qqsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }; |
| |
| static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x00019500, |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| }; |
| |
| static const uint32_t DQuad_with_dsub_2_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x0001ca00, |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // qqsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // qqsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }; |
| |
| static const uint32_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x00019400, |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| }; |
| |
| static const uint32_t DQuad_with_dsub_3_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x00014800, |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // qqsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // qqsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }; |
| |
| static const uint32_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x00019000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03c00000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| }; |
| |
| static const uint32_t DQuad_with_qsub_0_in_QPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x00006000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03c00000, // qqsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // qqsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }; |
| |
| static const uint32_t DQuad_with_qsub_1_in_QPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x00004000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // qqsub_0 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // qqsub_1 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }; |
| |
| static const uint32_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x00018000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| }; |
| |
| static const uint32_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x00010000, |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| }; |
| |
| static const uint32_t QQQQPRSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x03fe0000, |
| }; |
| |
| static const uint32_t QQQQPR_with_ssub_0SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x03fc0000, |
| }; |
| |
| static const uint32_t QQQQPR_with_ssub_4SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x03f80000, |
| }; |
| |
| static const uint32_t QQQQPR_with_ssub_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x03f00000, |
| }; |
| |
| static const uint32_t QQQQPR_with_ssub_12SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x03e00000, |
| }; |
| |
| static const uint32_t QQQQPR_with_dsub_0_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x03c00000, |
| }; |
| |
| static const uint32_t QQQQPR_with_dsub_2_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x03800000, |
| }; |
| |
| static const uint32_t QQQQPR_with_dsub_4_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x03000000, |
| }; |
| |
| static const uint32_t QQQQPR_with_dsub_6_in_DPR_8SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000000, 0x02000000, |
| }; |
| |
| static const uint16_t SuperRegIdxSeqs[] = { |
| /* 0 */ 1, 2, 3, 4, 5, 6, 7, 8, 0, |
| /* 9 */ 9, 0, |
| /* 11 */ 9, 10, 0, |
| /* 14 */ 1, 2, 3, 4, 5, 6, 7, 8, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 0, |
| /* 39 */ 13, 14, 15, 16, 37, 0, |
| /* 45 */ 38, 40, 45, 48, 0, |
| /* 50 */ 42, 50, 0, |
| /* 53 */ 34, 36, 44, 52, 0, |
| /* 58 */ 33, 35, 43, 46, 51, 53, 0, |
| /* 65 */ 34, 36, 47, 54, 0, |
| /* 70 */ 34, 36, 44, 47, 52, 54, 0, |
| /* 77 */ 13, 14, 15, 16, 37, 49, 55, 0, |
| /* 85 */ 11, 12, 56, 0, |
| /* 89 */ 11, 12, 42, 50, 56, 0, |
| }; |
| |
| static const TargetRegisterClass *const SPRSuperclasses[] = { |
| &ARM::HPRRegClass, |
| &ARM::FPWithVPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const FPWithVPR_with_ssub_0Superclasses[] = { |
| &ARM::FPWithVPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const SPR_8Superclasses[] = { |
| &ARM::HPRRegClass, |
| &ARM::FPWithVPRRegClass, |
| &ARM::SPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPRnopcSuperclasses[] = { |
| &ARM::GPRRegClass, |
| &ARM::GPRwithAPSRRegClass, |
| &ARM::GPRwithZRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPRwithZRnospSuperclasses[] = { |
| &ARM::GPRwithZRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const rGPRSuperclasses[] = { |
| &ARM::GPRRegClass, |
| &ARM::GPRwithAPSRRegClass, |
| &ARM::GPRwithZRRegClass, |
| &ARM::GPRnopcRegClass, |
| &ARM::GPRwithAPSRnospRegClass, |
| &ARM::GPRwithZRnospRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const tGPRwithpcSuperclasses[] = { |
| &ARM::GPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Superclasses[] = { |
| &ARM::FPWithVPRRegClass, |
| &ARM::FPWithVPR_with_ssub_0RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const hGPRSuperclasses[] = { |
| &ARM::GPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const tGPRSuperclasses[] = { |
| &ARM::GPRRegClass, |
| &ARM::GPRwithAPSRRegClass, |
| &ARM::GPRwithZRRegClass, |
| &ARM::GPRnopcRegClass, |
| &ARM::GPRwithAPSRnospRegClass, |
| &ARM::GPRwithZRnospRegClass, |
| &ARM::rGPRRegClass, |
| &ARM::tGPRwithpcRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const tGPREvenSuperclasses[] = { |
| &ARM::GPRRegClass, |
| &ARM::GPRwithAPSRRegClass, |
| &ARM::GPRwithZRRegClass, |
| &ARM::GPRnopcRegClass, |
| &ARM::GPRwithAPSRnospRegClass, |
| &ARM::GPRwithZRnospRegClass, |
| &ARM::rGPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPRnopc_and_hGPRSuperclasses[] = { |
| &ARM::GPRRegClass, |
| &ARM::GPRwithAPSRRegClass, |
| &ARM::GPRwithZRRegClass, |
| &ARM::GPRnopcRegClass, |
| &ARM::hGPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPRwithAPSRnosp_and_hGPRSuperclasses[] = { |
| &ARM::GPRRegClass, |
| &ARM::GPRwithAPSRRegClass, |
| &ARM::GPRwithZRRegClass, |
| &ARM::GPRnopcRegClass, |
| &ARM::GPRwithAPSRnospRegClass, |
| &ARM::GPRwithZRnospRegClass, |
| &ARM::rGPRRegClass, |
| &ARM::hGPRRegClass, |
| &ARM::GPRnopc_and_hGPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const tGPROddSuperclasses[] = { |
| &ARM::GPRRegClass, |
| &ARM::GPRwithAPSRRegClass, |
| &ARM::GPRwithZRRegClass, |
| &ARM::GPRnopcRegClass, |
| &ARM::GPRwithAPSRnospRegClass, |
| &ARM::GPRwithZRnospRegClass, |
| &ARM::rGPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const tcGPRSuperclasses[] = { |
| &ARM::GPRRegClass, |
| &ARM::GPRwithAPSRRegClass, |
| &ARM::GPRwithZRRegClass, |
| &ARM::GPRnopcRegClass, |
| &ARM::GPRwithAPSRnospRegClass, |
| &ARM::GPRwithZRnospRegClass, |
| &ARM::rGPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const hGPR_and_tGPREvenSuperclasses[] = { |
| &ARM::GPRRegClass, |
| &ARM::GPRwithAPSRRegClass, |
| &ARM::GPRwithZRRegClass, |
| &ARM::GPRnopcRegClass, |
| &ARM::GPRwithAPSRnospRegClass, |
| &ARM::GPRwithZRnospRegClass, |
| &ARM::rGPRRegClass, |
| &ARM::hGPRRegClass, |
| &ARM::tGPREvenRegClass, |
| &ARM::GPRnopc_and_hGPRRegClass, |
| &ARM::GPRwithAPSRnosp_and_hGPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const tGPR_and_tGPREvenSuperclasses[] = { |
| &ARM::GPRRegClass, |
| &ARM::GPRwithAPSRRegClass, |
| &ARM::GPRwithZRRegClass, |
| &ARM::GPRnopcRegClass, |
| &ARM::GPRwithAPSRnospRegClass, |
| &ARM::GPRwithZRnospRegClass, |
| &ARM::rGPRRegClass, |
| &ARM::tGPRwithpcRegClass, |
| &ARM::tGPRRegClass, |
| &ARM::tGPREvenRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const tGPR_and_tGPROddSuperclasses[] = { |
| &ARM::GPRRegClass, |
| &ARM::GPRwithAPSRRegClass, |
| &ARM::GPRwithZRRegClass, |
| &ARM::GPRnopcRegClass, |
| &ARM::GPRwithAPSRnospRegClass, |
| &ARM::GPRwithZRnospRegClass, |
| &ARM::rGPRRegClass, |
| &ARM::tGPRwithpcRegClass, |
| &ARM::tGPRRegClass, |
| &ARM::tGPROddRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const tGPR_and_tcGPRSuperclasses[] = { |
| &ARM::GPRRegClass, |
| &ARM::GPRwithAPSRRegClass, |
| &ARM::GPRwithZRRegClass, |
| &ARM::GPRnopcRegClass, |
| &ARM::GPRwithAPSRnospRegClass, |
| &ARM::GPRwithZRnospRegClass, |
| &ARM::rGPRRegClass, |
| &ARM::tGPRwithpcRegClass, |
| &ARM::tGPRRegClass, |
| &ARM::tcGPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const tGPREven_and_tcGPRSuperclasses[] = { |
| &ARM::GPRRegClass, |
| &ARM::GPRwithAPSRRegClass, |
| &ARM::GPRwithZRRegClass, |
| &ARM::GPRnopcRegClass, |
| &ARM::GPRwithAPSRnospRegClass, |
| &ARM::GPRwithZRnospRegClass, |
| &ARM::rGPRRegClass, |
| &ARM::tGPREvenRegClass, |
| &ARM::tcGPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const hGPR_and_tGPROddSuperclasses[] = { |
| &ARM::GPRRegClass, |
| &ARM::GPRwithAPSRRegClass, |
| &ARM::GPRwithZRRegClass, |
| &ARM::GPRnopcRegClass, |
| &ARM::GPRwithAPSRnospRegClass, |
| &ARM::GPRwithZRnospRegClass, |
| &ARM::rGPRRegClass, |
| &ARM::hGPRRegClass, |
| &ARM::GPRnopc_and_hGPRRegClass, |
| &ARM::GPRwithAPSRnosp_and_hGPRRegClass, |
| &ARM::tGPROddRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const tGPREven_and_tGPR_and_tcGPRSuperclasses[] = { |
| &ARM::GPRRegClass, |
| &ARM::GPRwithAPSRRegClass, |
| &ARM::GPRwithZRRegClass, |
| &ARM::GPRnopcRegClass, |
| &ARM::GPRwithAPSRnospRegClass, |
| &ARM::GPRwithZRnospRegClass, |
| &ARM::rGPRRegClass, |
| &ARM::tGPRwithpcRegClass, |
| &ARM::tGPRRegClass, |
| &ARM::tGPREvenRegClass, |
| &ARM::tcGPRRegClass, |
| &ARM::tGPR_and_tGPREvenRegClass, |
| &ARM::tGPR_and_tcGPRRegClass, |
| &ARM::tGPREven_and_tcGPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const tGPROdd_and_tcGPRSuperclasses[] = { |
| &ARM::GPRRegClass, |
| &ARM::GPRwithAPSRRegClass, |
| &ARM::GPRwithZRRegClass, |
| &ARM::GPRnopcRegClass, |
| &ARM::GPRwithAPSRnospRegClass, |
| &ARM::GPRwithZRnospRegClass, |
| &ARM::rGPRRegClass, |
| &ARM::tGPRwithpcRegClass, |
| &ARM::tGPRRegClass, |
| &ARM::tGPROddRegClass, |
| &ARM::tcGPRRegClass, |
| &ARM::tGPR_and_tGPROddRegClass, |
| &ARM::tGPR_and_tcGPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPRlrSuperclasses[] = { |
| &ARM::GPRRegClass, |
| &ARM::GPRwithAPSRRegClass, |
| &ARM::GPRwithZRRegClass, |
| &ARM::GPRnopcRegClass, |
| &ARM::GPRwithAPSRnospRegClass, |
| &ARM::GPRwithZRnospRegClass, |
| &ARM::rGPRRegClass, |
| &ARM::hGPRRegClass, |
| &ARM::tGPREvenRegClass, |
| &ARM::GPRnopc_and_hGPRRegClass, |
| &ARM::GPRwithAPSRnosp_and_hGPRRegClass, |
| &ARM::hGPR_and_tGPREvenRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPRspSuperclasses[] = { |
| &ARM::GPRRegClass, |
| &ARM::GPRwithAPSRRegClass, |
| &ARM::GPRwithZRRegClass, |
| &ARM::GPRnopcRegClass, |
| &ARM::hGPRRegClass, |
| &ARM::GPRnopc_and_hGPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const VCCRSuperclasses[] = { |
| &ARM::FPWithVPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const hGPR_and_tGPRwithpcSuperclasses[] = { |
| &ARM::GPRRegClass, |
| &ARM::tGPRwithpcRegClass, |
| &ARM::hGPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const hGPR_and_tcGPRSuperclasses[] = { |
| &ARM::GPRRegClass, |
| &ARM::GPRwithAPSRRegClass, |
| &ARM::GPRwithZRRegClass, |
| &ARM::GPRnopcRegClass, |
| &ARM::GPRwithAPSRnospRegClass, |
| &ARM::GPRwithZRnospRegClass, |
| &ARM::rGPRRegClass, |
| &ARM::hGPRRegClass, |
| &ARM::tGPREvenRegClass, |
| &ARM::GPRnopc_and_hGPRRegClass, |
| &ARM::GPRwithAPSRnosp_and_hGPRRegClass, |
| &ARM::tcGPRRegClass, |
| &ARM::hGPR_and_tGPREvenRegClass, |
| &ARM::tGPREven_and_tcGPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DPRSuperclasses[] = { |
| &ARM::FPWithVPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DPR_VFP2Superclasses[] = { |
| &ARM::FPWithVPRRegClass, |
| &ARM::FPWithVPR_with_ssub_0RegClass, |
| &ARM::DPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DPR_8Superclasses[] = { |
| &ARM::FPWithVPRRegClass, |
| &ARM::FPWithVPR_with_ssub_0RegClass, |
| &ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClass, |
| &ARM::DPRRegClass, |
| &ARM::DPR_VFP2RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPRPairnospSuperclasses[] = { |
| &ARM::GPRPairRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPRPair_with_gsub_0_in_tGPRSuperclasses[] = { |
| &ARM::GPRPairRegClass, |
| &ARM::GPRPairnospRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPRPair_with_gsub_0_in_hGPRSuperclasses[] = { |
| &ARM::GPRPairRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPRPair_with_gsub_0_in_tcGPRSuperclasses[] = { |
| &ARM::GPRPairRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPRPair_with_gsub_1_in_tcGPRSuperclasses[] = { |
| &ARM::GPRPairRegClass, |
| &ARM::GPRPairnospRegClass, |
| &ARM::GPRPair_with_gsub_0_in_tGPRRegClass, |
| &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRSuperclasses[] = { |
| &ARM::GPRPairRegClass, |
| &ARM::GPRPairnospRegClass, |
| &ARM::GPRPair_with_gsub_0_in_hGPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPRPair_with_gsub_1_in_GPRspSuperclasses[] = { |
| &ARM::GPRPairRegClass, |
| &ARM::GPRPair_with_gsub_0_in_hGPRRegClass, |
| &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DPairSpc_with_ssub_0Superclasses[] = { |
| &ARM::DPairSpcRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DPairSpc_with_ssub_4Superclasses[] = { |
| &ARM::DPairSpcRegClass, |
| &ARM::DPairSpc_with_ssub_0RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DPairSpc_with_dsub_0_in_DPR_8Superclasses[] = { |
| &ARM::DPairSpcRegClass, |
| &ARM::DPairSpc_with_ssub_0RegClass, |
| &ARM::DPairSpc_with_ssub_4RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DPairSpc_with_dsub_2_in_DPR_8Superclasses[] = { |
| &ARM::DPairSpcRegClass, |
| &ARM::DPairSpc_with_ssub_0RegClass, |
| &ARM::DPairSpc_with_ssub_4RegClass, |
| &ARM::DPairSpc_with_dsub_0_in_DPR_8RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DPair_with_ssub_0Superclasses[] = { |
| &ARM::DPairRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const QPRSuperclasses[] = { |
| &ARM::DPairRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DPair_with_ssub_2Superclasses[] = { |
| &ARM::DPairRegClass, |
| &ARM::DPair_with_ssub_0RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DPair_with_dsub_0_in_DPR_8Superclasses[] = { |
| &ARM::DPairRegClass, |
| &ARM::DPair_with_ssub_0RegClass, |
| &ARM::DPair_with_ssub_2RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const MQPRSuperclasses[] = { |
| &ARM::DPairRegClass, |
| &ARM::DPair_with_ssub_0RegClass, |
| &ARM::QPRRegClass, |
| &ARM::DPair_with_ssub_2RegClass, |
| &ARM::QPR_VFP2RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const QPR_VFP2Superclasses[] = { |
| &ARM::DPairRegClass, |
| &ARM::DPair_with_ssub_0RegClass, |
| &ARM::QPRRegClass, |
| &ARM::DPair_with_ssub_2RegClass, |
| &ARM::MQPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DPair_with_dsub_1_in_DPR_8Superclasses[] = { |
| &ARM::DPairRegClass, |
| &ARM::DPair_with_ssub_0RegClass, |
| &ARM::DPair_with_ssub_2RegClass, |
| &ARM::DPair_with_dsub_0_in_DPR_8RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const QPR_8Superclasses[] = { |
| &ARM::DPairRegClass, |
| &ARM::DPair_with_ssub_0RegClass, |
| &ARM::QPRRegClass, |
| &ARM::DPair_with_ssub_2RegClass, |
| &ARM::DPair_with_dsub_0_in_DPR_8RegClass, |
| &ARM::MQPRRegClass, |
| &ARM::QPR_VFP2RegClass, |
| &ARM::DPair_with_dsub_1_in_DPR_8RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTripleSpc_with_ssub_0Superclasses[] = { |
| &ARM::DTripleSpcRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTriple_with_ssub_0Superclasses[] = { |
| &ARM::DTripleRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPRSuperclasses[] = { |
| &ARM::DTripleRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTriple_with_ssub_2Superclasses[] = { |
| &ARM::DTripleRegClass, |
| &ARM::DTriple_with_ssub_0RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = { |
| &ARM::DTripleRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTripleSpc_with_ssub_4Superclasses[] = { |
| &ARM::DTripleSpcRegClass, |
| &ARM::DTripleSpc_with_ssub_0RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTriple_with_ssub_4Superclasses[] = { |
| &ARM::DTripleRegClass, |
| &ARM::DTriple_with_ssub_0RegClass, |
| &ARM::DTriple_with_ssub_2RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTripleSpc_with_ssub_8Superclasses[] = { |
| &ARM::DTripleSpcRegClass, |
| &ARM::DTripleSpc_with_ssub_0RegClass, |
| &ARM::DTripleSpc_with_ssub_4RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTripleSpc_with_dsub_0_in_DPR_8Superclasses[] = { |
| &ARM::DTripleSpcRegClass, |
| &ARM::DTripleSpc_with_ssub_0RegClass, |
| &ARM::DTripleSpc_with_ssub_4RegClass, |
| &ARM::DTripleSpc_with_ssub_8RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTriple_with_dsub_0_in_DPR_8Superclasses[] = { |
| &ARM::DTripleRegClass, |
| &ARM::DTriple_with_ssub_0RegClass, |
| &ARM::DTriple_with_ssub_2RegClass, |
| &ARM::DTriple_with_ssub_4RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTriple_with_qsub_0_in_MQPRSuperclasses[] = { |
| &ARM::DTripleRegClass, |
| &ARM::DTriple_with_ssub_0RegClass, |
| &ARM::DTriple_with_qsub_0_in_QPRRegClass, |
| &ARM::DTriple_with_ssub_2RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = { |
| &ARM::DTripleRegClass, |
| &ARM::DTriple_with_ssub_0RegClass, |
| &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTriple_with_dsub_1_in_DPR_8Superclasses[] = { |
| &ARM::DTripleRegClass, |
| &ARM::DTriple_with_ssub_0RegClass, |
| &ARM::DTriple_with_ssub_2RegClass, |
| &ARM::DTriple_with_ssub_4RegClass, |
| &ARM::DTriple_with_dsub_0_in_DPR_8RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses[] = { |
| &ARM::DTripleRegClass, |
| &ARM::DTriple_with_ssub_0RegClass, |
| &ARM::DTriple_with_ssub_2RegClass, |
| &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| &ARM::DTriple_with_ssub_4RegClass, |
| &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRSuperclasses[] = { |
| &ARM::DTripleRegClass, |
| &ARM::DTriple_with_ssub_0RegClass, |
| &ARM::DTriple_with_qsub_0_in_QPRRegClass, |
| &ARM::DTriple_with_ssub_2RegClass, |
| &ARM::DTriple_with_ssub_4RegClass, |
| &ARM::DTriple_with_qsub_0_in_MQPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTripleSpc_with_dsub_2_in_DPR_8Superclasses[] = { |
| &ARM::DTripleSpcRegClass, |
| &ARM::DTripleSpc_with_ssub_0RegClass, |
| &ARM::DTripleSpc_with_ssub_4RegClass, |
| &ARM::DTripleSpc_with_ssub_8RegClass, |
| &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTriple_with_dsub_2_in_DPR_8Superclasses[] = { |
| &ARM::DTripleRegClass, |
| &ARM::DTriple_with_ssub_0RegClass, |
| &ARM::DTriple_with_ssub_2RegClass, |
| &ARM::DTriple_with_ssub_4RegClass, |
| &ARM::DTriple_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DTriple_with_dsub_1_in_DPR_8RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTripleSpc_with_dsub_4_in_DPR_8Superclasses[] = { |
| &ARM::DTripleSpcRegClass, |
| &ARM::DTripleSpc_with_ssub_0RegClass, |
| &ARM::DTripleSpc_with_ssub_4RegClass, |
| &ARM::DTripleSpc_with_ssub_8RegClass, |
| &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses[] = { |
| &ARM::DTripleRegClass, |
| &ARM::DTriple_with_ssub_0RegClass, |
| &ARM::DTriple_with_ssub_2RegClass, |
| &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| &ARM::DTriple_with_ssub_4RegClass, |
| &ARM::DTriple_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPR_8Superclasses[] = { |
| &ARM::DTripleRegClass, |
| &ARM::DTriple_with_ssub_0RegClass, |
| &ARM::DTriple_with_qsub_0_in_QPRRegClass, |
| &ARM::DTriple_with_ssub_2RegClass, |
| &ARM::DTriple_with_ssub_4RegClass, |
| &ARM::DTriple_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DTriple_with_qsub_0_in_MQPRRegClass, |
| &ARM::DTriple_with_dsub_1_in_DPR_8RegClass, |
| &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRSuperclasses[] = { |
| &ARM::DTripleRegClass, |
| &ARM::DTriple_with_ssub_0RegClass, |
| &ARM::DTriple_with_qsub_0_in_QPRRegClass, |
| &ARM::DTriple_with_ssub_2RegClass, |
| &ARM::DTriple_with_ssub_4RegClass, |
| &ARM::DTriple_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DTriple_with_qsub_0_in_MQPRRegClass, |
| &ARM::DTriple_with_dsub_1_in_DPR_8RegClass, |
| &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClass, |
| &ARM::DTriple_with_dsub_2_in_DPR_8RegClass, |
| &ARM::DTriple_with_qsub_0_in_QPR_8RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses[] = { |
| &ARM::DTripleRegClass, |
| &ARM::DTriple_with_ssub_0RegClass, |
| &ARM::DTriple_with_ssub_2RegClass, |
| &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| &ARM::DTriple_with_ssub_4RegClass, |
| &ARM::DTriple_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| &ARM::DTriple_with_dsub_1_in_DPR_8RegClass, |
| &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, |
| &ARM::DTriple_with_dsub_2_in_DPR_8RegClass, |
| &ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuadSpcSuperclasses[] = { |
| &ARM::DTripleSpcRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuadSpc_with_ssub_0Superclasses[] = { |
| &ARM::DTripleSpcRegClass, |
| &ARM::DTripleSpc_with_ssub_0RegClass, |
| &ARM::DQuadSpcRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuadSpc_with_ssub_4Superclasses[] = { |
| &ARM::DTripleSpcRegClass, |
| &ARM::DTripleSpc_with_ssub_0RegClass, |
| &ARM::DTripleSpc_with_ssub_4RegClass, |
| &ARM::DQuadSpcRegClass, |
| &ARM::DQuadSpc_with_ssub_0RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuadSpc_with_ssub_8Superclasses[] = { |
| &ARM::DTripleSpcRegClass, |
| &ARM::DTripleSpc_with_ssub_0RegClass, |
| &ARM::DTripleSpc_with_ssub_4RegClass, |
| &ARM::DTripleSpc_with_ssub_8RegClass, |
| &ARM::DQuadSpcRegClass, |
| &ARM::DQuadSpc_with_ssub_0RegClass, |
| &ARM::DQuadSpc_with_ssub_4RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuadSpc_with_dsub_0_in_DPR_8Superclasses[] = { |
| &ARM::DTripleSpcRegClass, |
| &ARM::DTripleSpc_with_ssub_0RegClass, |
| &ARM::DTripleSpc_with_ssub_4RegClass, |
| &ARM::DTripleSpc_with_ssub_8RegClass, |
| &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DQuadSpcRegClass, |
| &ARM::DQuadSpc_with_ssub_0RegClass, |
| &ARM::DQuadSpc_with_ssub_4RegClass, |
| &ARM::DQuadSpc_with_ssub_8RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuadSpc_with_dsub_2_in_DPR_8Superclasses[] = { |
| &ARM::DTripleSpcRegClass, |
| &ARM::DTripleSpc_with_ssub_0RegClass, |
| &ARM::DTripleSpc_with_ssub_4RegClass, |
| &ARM::DTripleSpc_with_ssub_8RegClass, |
| &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass, |
| &ARM::DQuadSpcRegClass, |
| &ARM::DQuadSpc_with_ssub_0RegClass, |
| &ARM::DQuadSpc_with_ssub_4RegClass, |
| &ARM::DQuadSpc_with_ssub_8RegClass, |
| &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuadSpc_with_dsub_4_in_DPR_8Superclasses[] = { |
| &ARM::DTripleSpcRegClass, |
| &ARM::DTripleSpc_with_ssub_0RegClass, |
| &ARM::DTripleSpc_with_ssub_4RegClass, |
| &ARM::DTripleSpc_with_ssub_8RegClass, |
| &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass, |
| &ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClass, |
| &ARM::DQuadSpcRegClass, |
| &ARM::DQuadSpc_with_ssub_0RegClass, |
| &ARM::DQuadSpc_with_ssub_4RegClass, |
| &ARM::DQuadSpc_with_ssub_8RegClass, |
| &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuad_with_ssub_0Superclasses[] = { |
| &ARM::DQuadRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuad_with_ssub_2Superclasses[] = { |
| &ARM::DQuadRegClass, |
| &ARM::DQuad_with_ssub_0RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const QQPRSuperclasses[] = { |
| &ARM::DQuadRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = { |
| &ARM::DQuadRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuad_with_ssub_4Superclasses[] = { |
| &ARM::DQuadRegClass, |
| &ARM::DQuad_with_ssub_0RegClass, |
| &ARM::DQuad_with_ssub_2RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuad_with_ssub_6Superclasses[] = { |
| &ARM::DQuadRegClass, |
| &ARM::DQuad_with_ssub_0RegClass, |
| &ARM::DQuad_with_ssub_2RegClass, |
| &ARM::DQuad_with_ssub_4RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuad_with_dsub_0_in_DPR_8Superclasses[] = { |
| &ARM::DQuadRegClass, |
| &ARM::DQuad_with_ssub_0RegClass, |
| &ARM::DQuad_with_ssub_2RegClass, |
| &ARM::DQuad_with_ssub_4RegClass, |
| &ARM::DQuad_with_ssub_6RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuad_with_qsub_0_in_MQPRSuperclasses[] = { |
| &ARM::DQuadRegClass, |
| &ARM::DQuad_with_ssub_0RegClass, |
| &ARM::DQuad_with_ssub_2RegClass, |
| &ARM::QQPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = { |
| &ARM::DQuadRegClass, |
| &ARM::DQuad_with_ssub_0RegClass, |
| &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuad_with_dsub_1_in_DPR_8Superclasses[] = { |
| &ARM::DQuadRegClass, |
| &ARM::DQuad_with_ssub_0RegClass, |
| &ARM::DQuad_with_ssub_2RegClass, |
| &ARM::DQuad_with_ssub_4RegClass, |
| &ARM::DQuad_with_ssub_6RegClass, |
| &ARM::DQuad_with_dsub_0_in_DPR_8RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuad_with_qsub_1_in_MQPRSuperclasses[] = { |
| &ARM::DQuadRegClass, |
| &ARM::DQuad_with_ssub_0RegClass, |
| &ARM::DQuad_with_ssub_2RegClass, |
| &ARM::QQPRRegClass, |
| &ARM::DQuad_with_ssub_4RegClass, |
| &ARM::DQuad_with_ssub_6RegClass, |
| &ARM::DQuad_with_qsub_0_in_MQPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses[] = { |
| &ARM::DQuadRegClass, |
| &ARM::DQuad_with_ssub_0RegClass, |
| &ARM::DQuad_with_ssub_2RegClass, |
| &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| &ARM::DQuad_with_ssub_4RegClass, |
| &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuad_with_dsub_2_in_DPR_8Superclasses[] = { |
| &ARM::DQuadRegClass, |
| &ARM::DQuad_with_ssub_0RegClass, |
| &ARM::DQuad_with_ssub_2RegClass, |
| &ARM::DQuad_with_ssub_4RegClass, |
| &ARM::DQuad_with_ssub_6RegClass, |
| &ARM::DQuad_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DQuad_with_dsub_1_in_DPR_8RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses[] = { |
| &ARM::DQuadRegClass, |
| &ARM::DQuad_with_ssub_0RegClass, |
| &ARM::DQuad_with_ssub_2RegClass, |
| &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| &ARM::DQuad_with_ssub_4RegClass, |
| &ARM::DQuad_with_ssub_6RegClass, |
| &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuad_with_dsub_3_in_DPR_8Superclasses[] = { |
| &ARM::DQuadRegClass, |
| &ARM::DQuad_with_ssub_0RegClass, |
| &ARM::DQuad_with_ssub_2RegClass, |
| &ARM::DQuad_with_ssub_4RegClass, |
| &ARM::DQuad_with_ssub_6RegClass, |
| &ARM::DQuad_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DQuad_with_dsub_1_in_DPR_8RegClass, |
| &ARM::DQuad_with_dsub_2_in_DPR_8RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses[] = { |
| &ARM::DQuadRegClass, |
| &ARM::DQuad_with_ssub_0RegClass, |
| &ARM::DQuad_with_ssub_2RegClass, |
| &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| &ARM::DQuad_with_ssub_4RegClass, |
| &ARM::DQuad_with_ssub_6RegClass, |
| &ARM::DQuad_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, |
| &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuad_with_qsub_0_in_QPR_8Superclasses[] = { |
| &ARM::DQuadRegClass, |
| &ARM::DQuad_with_ssub_0RegClass, |
| &ARM::DQuad_with_ssub_2RegClass, |
| &ARM::QQPRRegClass, |
| &ARM::DQuad_with_ssub_4RegClass, |
| &ARM::DQuad_with_ssub_6RegClass, |
| &ARM::DQuad_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DQuad_with_qsub_0_in_MQPRRegClass, |
| &ARM::DQuad_with_dsub_1_in_DPR_8RegClass, |
| &ARM::DQuad_with_qsub_1_in_MQPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuad_with_qsub_1_in_QPR_8Superclasses[] = { |
| &ARM::DQuadRegClass, |
| &ARM::DQuad_with_ssub_0RegClass, |
| &ARM::DQuad_with_ssub_2RegClass, |
| &ARM::QQPRRegClass, |
| &ARM::DQuad_with_ssub_4RegClass, |
| &ARM::DQuad_with_ssub_6RegClass, |
| &ARM::DQuad_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DQuad_with_qsub_0_in_MQPRRegClass, |
| &ARM::DQuad_with_dsub_1_in_DPR_8RegClass, |
| &ARM::DQuad_with_qsub_1_in_MQPRRegClass, |
| &ARM::DQuad_with_dsub_2_in_DPR_8RegClass, |
| &ARM::DQuad_with_dsub_3_in_DPR_8RegClass, |
| &ARM::DQuad_with_qsub_0_in_QPR_8RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses[] = { |
| &ARM::DQuadRegClass, |
| &ARM::DQuad_with_ssub_0RegClass, |
| &ARM::DQuad_with_ssub_2RegClass, |
| &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| &ARM::DQuad_with_ssub_4RegClass, |
| &ARM::DQuad_with_ssub_6RegClass, |
| &ARM::DQuad_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| &ARM::DQuad_with_dsub_1_in_DPR_8RegClass, |
| &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, |
| &ARM::DQuad_with_dsub_2_in_DPR_8RegClass, |
| &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, |
| &ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses[] = { |
| &ARM::DQuadRegClass, |
| &ARM::DQuad_with_ssub_0RegClass, |
| &ARM::DQuad_with_ssub_2RegClass, |
| &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| &ARM::DQuad_with_ssub_4RegClass, |
| &ARM::DQuad_with_ssub_6RegClass, |
| &ARM::DQuad_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| &ARM::DQuad_with_dsub_1_in_DPR_8RegClass, |
| &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, |
| &ARM::DQuad_with_dsub_2_in_DPR_8RegClass, |
| &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, |
| &ARM::DQuad_with_dsub_3_in_DPR_8RegClass, |
| &ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, |
| &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const QQQQPR_with_ssub_0Superclasses[] = { |
| &ARM::QQQQPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const QQQQPR_with_ssub_4Superclasses[] = { |
| &ARM::QQQQPRRegClass, |
| &ARM::QQQQPR_with_ssub_0RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const QQQQPR_with_ssub_8Superclasses[] = { |
| &ARM::QQQQPRRegClass, |
| &ARM::QQQQPR_with_ssub_0RegClass, |
| &ARM::QQQQPR_with_ssub_4RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const QQQQPR_with_ssub_12Superclasses[] = { |
| &ARM::QQQQPRRegClass, |
| &ARM::QQQQPR_with_ssub_0RegClass, |
| &ARM::QQQQPR_with_ssub_4RegClass, |
| &ARM::QQQQPR_with_ssub_8RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const QQQQPR_with_dsub_0_in_DPR_8Superclasses[] = { |
| &ARM::QQQQPRRegClass, |
| &ARM::QQQQPR_with_ssub_0RegClass, |
| &ARM::QQQQPR_with_ssub_4RegClass, |
| &ARM::QQQQPR_with_ssub_8RegClass, |
| &ARM::QQQQPR_with_ssub_12RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const QQQQPR_with_dsub_2_in_DPR_8Superclasses[] = { |
| &ARM::QQQQPRRegClass, |
| &ARM::QQQQPR_with_ssub_0RegClass, |
| &ARM::QQQQPR_with_ssub_4RegClass, |
| &ARM::QQQQPR_with_ssub_8RegClass, |
| &ARM::QQQQPR_with_ssub_12RegClass, |
| &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const QQQQPR_with_dsub_4_in_DPR_8Superclasses[] = { |
| &ARM::QQQQPRRegClass, |
| &ARM::QQQQPR_with_ssub_0RegClass, |
| &ARM::QQQQPR_with_ssub_4RegClass, |
| &ARM::QQQQPR_with_ssub_8RegClass, |
| &ARM::QQQQPR_with_ssub_12RegClass, |
| &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass, |
| &ARM::QQQQPR_with_dsub_2_in_DPR_8RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const QQQQPR_with_dsub_6_in_DPR_8Superclasses[] = { |
| &ARM::QQQQPRRegClass, |
| &ARM::QQQQPR_with_ssub_0RegClass, |
| &ARM::QQQQPR_with_ssub_4RegClass, |
| &ARM::QQQQPR_with_ssub_8RegClass, |
| &ARM::QQQQPR_with_ssub_12RegClass, |
| &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass, |
| &ARM::QQQQPR_with_dsub_2_in_DPR_8RegClass, |
| &ARM::QQQQPR_with_dsub_4_in_DPR_8RegClass, |
| nullptr |
| }; |
| |
| |
| static inline unsigned HPRAltOrderSelect(const MachineFunction &MF) { |
| return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(); |
| } |
| |
| static ArrayRef<MCPhysReg> HPRGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::S0, ARM::S2, ARM::S4, ARM::S6, ARM::S8, ARM::S10, ARM::S12, ARM::S14, ARM::S16, ARM::S18, ARM::S20, ARM::S22, ARM::S24, ARM::S26, ARM::S28, ARM::S30, ARM::S1, ARM::S3, ARM::S5, ARM::S7, ARM::S9, ARM::S11, ARM::S13, ARM::S15, ARM::S17, ARM::S19, ARM::S21, ARM::S23, ARM::S25, ARM::S27, ARM::S29, ARM::S31 }; |
| static const MCPhysReg AltOrder2[] = { ARM::S0, ARM::S4, ARM::S8, ARM::S12, ARM::S16, ARM::S20, ARM::S24, ARM::S28, ARM::S2, ARM::S6, ARM::S10, ARM::S14, ARM::S18, ARM::S22, ARM::S26, ARM::S30, ARM::S1, ARM::S5, ARM::S9, ARM::S13, ARM::S17, ARM::S21, ARM::S25, ARM::S29, ARM::S3, ARM::S7, ARM::S11, ARM::S15, ARM::S19, ARM::S23, ARM::S27, ARM::S31 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::HPRRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1), |
| makeArrayRef(AltOrder2) |
| }; |
| const unsigned Select = HPRAltOrderSelect(MF); |
| assert(Select < 3); |
| return Order[Select]; |
| } |
| |
| static inline unsigned SPRAltOrderSelect(const MachineFunction &MF) { |
| return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(); |
| } |
| |
| static ArrayRef<MCPhysReg> SPRGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::S0, ARM::S2, ARM::S4, ARM::S6, ARM::S8, ARM::S10, ARM::S12, ARM::S14, ARM::S16, ARM::S18, ARM::S20, ARM::S22, ARM::S24, ARM::S26, ARM::S28, ARM::S30, ARM::S1, ARM::S3, ARM::S5, ARM::S7, ARM::S9, ARM::S11, ARM::S13, ARM::S15, ARM::S17, ARM::S19, ARM::S21, ARM::S23, ARM::S25, ARM::S27, ARM::S29, ARM::S31 }; |
| static const MCPhysReg AltOrder2[] = { ARM::S0, ARM::S4, ARM::S8, ARM::S12, ARM::S16, ARM::S20, ARM::S24, ARM::S28, ARM::S2, ARM::S6, ARM::S10, ARM::S14, ARM::S18, ARM::S22, ARM::S26, ARM::S30, ARM::S1, ARM::S5, ARM::S9, ARM::S13, ARM::S17, ARM::S21, ARM::S25, ARM::S29, ARM::S3, ARM::S7, ARM::S11, ARM::S15, ARM::S19, ARM::S23, ARM::S27, ARM::S31 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::SPRRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1), |
| makeArrayRef(AltOrder2) |
| }; |
| const unsigned Select = SPRAltOrderSelect(MF); |
| assert(Select < 3); |
| return Order[Select]; |
| } |
| |
| static inline unsigned GPRAltOrderSelect(const MachineFunction &MF) { |
| return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF); |
| } |
| |
| static ArrayRef<MCPhysReg> GPRGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::PC }; |
| static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 }; |
| static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP, ARM::PC }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1), |
| makeArrayRef(AltOrder2), |
| makeArrayRef(AltOrder3) |
| }; |
| const unsigned Select = GPRAltOrderSelect(MF); |
| assert(Select < 4); |
| return Order[Select]; |
| } |
| |
| static inline unsigned GPRwithAPSRAltOrderSelect(const MachineFunction &MF) { |
| return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only(); |
| } |
| |
| static ArrayRef<MCPhysReg> GPRwithAPSRGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP }; |
| static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRwithAPSRRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1), |
| makeArrayRef(AltOrder2) |
| }; |
| const unsigned Select = GPRwithAPSRAltOrderSelect(MF); |
| assert(Select < 3); |
| return Order[Select]; |
| } |
| |
| static inline unsigned GPRwithZRAltOrderSelect(const MachineFunction &MF) { |
| return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only(); |
| } |
| |
| static ArrayRef<MCPhysReg> GPRwithZRGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::ZR }; |
| static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRwithZRRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1), |
| makeArrayRef(AltOrder2) |
| }; |
| const unsigned Select = GPRwithZRAltOrderSelect(MF); |
| assert(Select < 3); |
| return Order[Select]; |
| } |
| |
| static inline unsigned GPRnopcAltOrderSelect(const MachineFunction &MF) { |
| return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF); |
| } |
| |
| static ArrayRef<MCPhysReg> GPRnopcGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP }; |
| static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 }; |
| static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRnopcRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1), |
| makeArrayRef(AltOrder2), |
| makeArrayRef(AltOrder3) |
| }; |
| const unsigned Select = GPRnopcAltOrderSelect(MF); |
| assert(Select < 4); |
| return Order[Select]; |
| } |
| |
| static inline unsigned GPRwithZRnospAltOrderSelect(const MachineFunction &MF) { |
| return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only(); |
| } |
| |
| static ArrayRef<MCPhysReg> GPRwithZRnospGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::ZR }; |
| static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRwithZRnospRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1), |
| makeArrayRef(AltOrder2) |
| }; |
| const unsigned Select = GPRwithZRnospAltOrderSelect(MF); |
| assert(Select < 3); |
| return Order[Select]; |
| } |
| |
| static inline unsigned rGPRAltOrderSelect(const MachineFunction &MF) { |
| return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF); |
| } |
| |
| static ArrayRef<MCPhysReg> rGPRGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12 }; |
| static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 }; |
| static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::rGPRRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1), |
| makeArrayRef(AltOrder2), |
| makeArrayRef(AltOrder3) |
| }; |
| const unsigned Select = rGPRAltOrderSelect(MF); |
| assert(Select < 4); |
| return Order[Select]; |
| } |
| |
| static inline unsigned tGPREvenAltOrderSelect(const MachineFunction &MF) { |
| return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); |
| } |
| |
| static ArrayRef<MCPhysReg> tGPREvenGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R2, ARM::R4, ARM::R6 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPREvenRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = tGPREvenAltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned tGPROddAltOrderSelect(const MachineFunction &MF) { |
| return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); |
| } |
| |
| static ArrayRef<MCPhysReg> tGPROddGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::R1, ARM::R3, ARM::R5, ARM::R7 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPROddRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = tGPROddAltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned tcGPRAltOrderSelect(const MachineFunction &MF) { |
| return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); |
| } |
| |
| static ArrayRef<MCPhysReg> tcGPRGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tcGPRRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = tcGPRAltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned tGPR_and_tGPREvenAltOrderSelect(const MachineFunction &MF) { |
| return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); |
| } |
| |
| static ArrayRef<MCPhysReg> tGPR_and_tGPREvenGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R2, ARM::R4, ARM::R6 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPR_and_tGPREvenRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = tGPR_and_tGPREvenAltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned tGPR_and_tGPROddAltOrderSelect(const MachineFunction &MF) { |
| return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); |
| } |
| |
| static ArrayRef<MCPhysReg> tGPR_and_tGPROddGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::R1, ARM::R3, ARM::R5, ARM::R7 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPR_and_tGPROddRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = tGPR_and_tGPROddAltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned tGPR_and_tcGPRAltOrderSelect(const MachineFunction &MF) { |
| return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); |
| } |
| |
| static ArrayRef<MCPhysReg> tGPR_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPR_and_tcGPRRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = tGPR_and_tcGPRAltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned tGPREven_and_tcGPRAltOrderSelect(const MachineFunction &MF) { |
| return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); |
| } |
| |
| static ArrayRef<MCPhysReg> tGPREven_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R2 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPREven_and_tcGPRRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = tGPREven_and_tcGPRAltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned hGPR_and_tGPROddAltOrderSelect(const MachineFunction &MF) { |
| return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); |
| } |
| |
| static ArrayRef<MCPhysReg> hGPR_and_tGPROddGetRawAllocationOrder(const MachineFunction &MF) { |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::hGPR_and_tGPROddRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| ArrayRef<MCPhysReg>() |
| }; |
| const unsigned Select = hGPR_and_tGPROddAltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned tGPREven_and_tGPR_and_tcGPRAltOrderSelect(const MachineFunction &MF) { |
| return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); |
| } |
| |
| static ArrayRef<MCPhysReg> tGPREven_and_tGPR_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R2 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPREven_and_tGPR_and_tcGPRRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = tGPREven_and_tGPR_and_tcGPRAltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned tGPROdd_and_tcGPRAltOrderSelect(const MachineFunction &MF) { |
| return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); |
| } |
| |
| static ArrayRef<MCPhysReg> tGPROdd_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::R1, ARM::R3 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::tGPROdd_and_tcGPRRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = tGPROdd_and_tcGPRAltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned hGPR_and_tcGPRAltOrderSelect(const MachineFunction &MF) { |
| return MF.getSubtarget<ARMSubtarget>().isThumb1Only(); |
| } |
| |
| static ArrayRef<MCPhysReg> hGPR_and_tcGPRGetRawAllocationOrder(const MachineFunction &MF) { |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::hGPR_and_tcGPRRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| ArrayRef<MCPhysReg>() |
| }; |
| const unsigned Select = hGPR_and_tcGPRAltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned DPRAltOrderSelect(const MachineFunction &MF) { |
| return 1 + MF.getSubtarget<ARMSubtarget>().useStride4VFPs(); |
| } |
| |
| static ArrayRef<MCPhysReg> DPRGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15 }; |
| static const MCPhysReg AltOrder2[] = { ARM::D16, ARM::D18, ARM::D20, ARM::D22, ARM::D24, ARM::D26, ARM::D28, ARM::D30, ARM::D0, ARM::D2, ARM::D4, ARM::D6, ARM::D8, ARM::D10, ARM::D12, ARM::D14, ARM::D17, ARM::D19, ARM::D21, ARM::D23, ARM::D25, ARM::D27, ARM::D29, ARM::D31, ARM::D1, ARM::D3, ARM::D5, ARM::D7, ARM::D9, ARM::D11, ARM::D13, ARM::D15 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPRRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1), |
| makeArrayRef(AltOrder2) |
| }; |
| const unsigned Select = DPRAltOrderSelect(MF); |
| assert(Select < 3); |
| return Order[Select]; |
| } |
| |
| static inline unsigned DPairAltOrderSelect(const MachineFunction &MF) { |
| return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps(); |
| } |
| |
| static ArrayRef<MCPhysReg> DPairGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D17_D18, ARM::D19_D20, ARM::D21_D22, ARM::D23_D24, ARM::D25_D26, ARM::D27_D28, ARM::D29_D30, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14, ARM::D15_D16 }; |
| static const MCPhysReg AltOrder2[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14, ARM::D15_D16 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPairRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1), |
| makeArrayRef(AltOrder2) |
| }; |
| const unsigned Select = DPairAltOrderSelect(MF); |
| assert(Select < 3); |
| return Order[Select]; |
| } |
| |
| static inline unsigned DPair_with_ssub_0AltOrderSelect(const MachineFunction &MF) { |
| return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps(); |
| } |
| |
| static ArrayRef<MCPhysReg> DPair_with_ssub_0GetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14, ARM::D15_D16 }; |
| static const MCPhysReg AltOrder2[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14, ARM::D15_D16 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_ssub_0RegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1), |
| makeArrayRef(AltOrder2) |
| }; |
| const unsigned Select = DPair_with_ssub_0AltOrderSelect(MF); |
| assert(Select < 3); |
| return Order[Select]; |
| } |
| |
| static inline unsigned QPRAltOrderSelect(const MachineFunction &MF) { |
| return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps(); |
| } |
| |
| static ArrayRef<MCPhysReg> QPRGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7 }; |
| static const MCPhysReg AltOrder2[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QPRRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1), |
| makeArrayRef(AltOrder2) |
| }; |
| const unsigned Select = QPRAltOrderSelect(MF); |
| assert(Select < 3); |
| return Order[Select]; |
| } |
| |
| static inline unsigned DPair_with_ssub_2AltOrderSelect(const MachineFunction &MF) { |
| return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps(); |
| } |
| |
| static ArrayRef<MCPhysReg> DPair_with_ssub_2GetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14 }; |
| static const MCPhysReg AltOrder2[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8, ARM::D9_D10, ARM::D11_D12, ARM::D13_D14 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_ssub_2RegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1), |
| makeArrayRef(AltOrder2) |
| }; |
| const unsigned Select = DPair_with_ssub_2AltOrderSelect(MF); |
| assert(Select < 3); |
| return Order[Select]; |
| } |
| |
| static inline unsigned DPair_with_dsub_0_in_DPR_8AltOrderSelect(const MachineFunction &MF) { |
| return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps(); |
| } |
| |
| static ArrayRef<MCPhysReg> DPair_with_dsub_0_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8 }; |
| static const MCPhysReg AltOrder2[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6, ARM::D7_D8 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_dsub_0_in_DPR_8RegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1), |
| makeArrayRef(AltOrder2) |
| }; |
| const unsigned Select = DPair_with_dsub_0_in_DPR_8AltOrderSelect(MF); |
| assert(Select < 3); |
| return Order[Select]; |
| } |
| |
| static inline unsigned DPair_with_dsub_1_in_DPR_8AltOrderSelect(const MachineFunction &MF) { |
| return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps(); |
| } |
| |
| static ArrayRef<MCPhysReg> DPair_with_dsub_1_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6 }; |
| static const MCPhysReg AltOrder2[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::D1_D2, ARM::D3_D4, ARM::D5_D6 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DPair_with_dsub_1_in_DPR_8RegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1), |
| makeArrayRef(AltOrder2) |
| }; |
| const unsigned Select = DPair_with_dsub_1_in_DPR_8AltOrderSelect(MF); |
| assert(Select < 3); |
| return Order[Select]; |
| } |
| |
| static inline unsigned QQPRAltOrderSelect(const MachineFunction &MF) { return 1; } |
| |
| static ArrayRef<MCPhysReg> QQPRGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::Q8_Q9, ARM::Q9_Q10, ARM::Q10_Q11, ARM::Q11_Q12, ARM::Q12_Q13, ARM::Q13_Q14, ARM::Q14_Q15, ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQPRRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = QQPRAltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned DQuad_with_qsub_0_in_MQPRAltOrderSelect(const MachineFunction &MF) { return 1; } |
| |
| static ArrayRef<MCPhysReg> DQuad_with_qsub_0_in_MQPRGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7, ARM::Q7_Q8 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_0_in_MQPRRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = DQuad_with_qsub_0_in_MQPRAltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned DQuad_with_qsub_1_in_MQPRAltOrderSelect(const MachineFunction &MF) { return 1; } |
| |
| static ArrayRef<MCPhysReg> DQuad_with_qsub_1_in_MQPRGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_1_in_MQPRRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = DQuad_with_qsub_1_in_MQPRAltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned DQuad_with_qsub_0_in_QPR_8AltOrderSelect(const MachineFunction &MF) { return 1; } |
| |
| static ArrayRef<MCPhysReg> DQuad_with_qsub_0_in_QPR_8GetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_0_in_QPR_8RegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = DQuad_with_qsub_0_in_QPR_8AltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned DQuad_with_qsub_1_in_QPR_8AltOrderSelect(const MachineFunction &MF) { return 1; } |
| |
| static ArrayRef<MCPhysReg> DQuad_with_qsub_1_in_QPR_8GetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::DQuad_with_qsub_1_in_QPR_8RegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = DQuad_with_qsub_1_in_QPR_8AltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned QQQQPRAltOrderSelect(const MachineFunction &MF) { return 1; } |
| |
| static ArrayRef<MCPhysReg> QQQQPRGetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::Q8_Q9_Q10_Q11, ARM::Q9_Q10_Q11_Q12, ARM::Q10_Q11_Q12_Q13, ARM::Q11_Q12_Q13_Q14, ARM::Q12_Q13_Q14_Q15, ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPRRegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = QQQQPRAltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned QQQQPR_with_ssub_0AltOrderSelect(const MachineFunction &MF) { return 1; } |
| |
| static ArrayRef<MCPhysReg> QQQQPR_with_ssub_0GetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9, ARM::Q7_Q8_Q9_Q10 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_0RegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = QQQQPR_with_ssub_0AltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned QQQQPR_with_ssub_4AltOrderSelect(const MachineFunction &MF) { return 1; } |
| |
| static ArrayRef<MCPhysReg> QQQQPR_with_ssub_4GetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8, ARM::Q6_Q7_Q8_Q9 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_4RegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = QQQQPR_with_ssub_4AltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned QQQQPR_with_ssub_8AltOrderSelect(const MachineFunction &MF) { return 1; } |
| |
| static ArrayRef<MCPhysReg> QQQQPR_with_ssub_8GetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7, ARM::Q5_Q6_Q7_Q8 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_8RegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = QQQQPR_with_ssub_8AltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned QQQQPR_with_ssub_12AltOrderSelect(const MachineFunction &MF) { return 1; } |
| |
| static ArrayRef<MCPhysReg> QQQQPR_with_ssub_12GetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_ssub_12RegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = QQQQPR_with_ssub_12AltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned QQQQPR_with_dsub_0_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; } |
| |
| static ArrayRef<MCPhysReg> QQQQPR_with_dsub_0_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, ARM::Q3_Q4_Q5_Q6 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_0_in_DPR_8RegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = QQQQPR_with_dsub_0_in_DPR_8AltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned QQQQPR_with_dsub_2_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; } |
| |
| static ArrayRef<MCPhysReg> QQQQPR_with_dsub_2_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_2_in_DPR_8RegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = QQQQPR_with_dsub_2_in_DPR_8AltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned QQQQPR_with_dsub_4_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; } |
| |
| static ArrayRef<MCPhysReg> QQQQPR_with_dsub_4_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_4_in_DPR_8RegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = QQQQPR_with_dsub_4_in_DPR_8AltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| static inline unsigned QQQQPR_with_dsub_6_in_DPR_8AltOrderSelect(const MachineFunction &MF) { return 1; } |
| |
| static ArrayRef<MCPhysReg> QQQQPR_with_dsub_6_in_DPR_8GetRawAllocationOrder(const MachineFunction &MF) { |
| static const MCPhysReg AltOrder1[] = { ARM::Q0_Q1_Q2_Q3 }; |
| const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::QQQQPR_with_dsub_6_in_DPR_8RegClassID]; |
| const ArrayRef<MCPhysReg> Order[] = { |
| makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| makeArrayRef(AltOrder1) |
| }; |
| const unsigned Select = QQQQPR_with_dsub_6_in_DPR_8AltOrderSelect(MF); |
| assert(Select < 2); |
| return Order[Select]; |
| } |
| |
| namespace ARM { // Register class instances |
| extern const TargetRegisterClass HPRRegClass = { |
| &ARMMCRegisterClasses[HPRRegClassID], |
| HPRSubClassMask, |
| SuperRegIdxSeqs + 22, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| HPRGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass FPWithVPRRegClass = { |
| &ARMMCRegisterClasses[FPWithVPRRegClassID], |
| FPWithVPRSubClassMask, |
| SuperRegIdxSeqs + 14, |
| LaneBitmask(0x0000000C), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass SPRRegClass = { |
| &ARMMCRegisterClasses[SPRRegClassID], |
| SPRSubClassMask, |
| SuperRegIdxSeqs + 22, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| SPRSuperclasses, |
| SPRGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass FPWithVPR_with_ssub_0RegClass = { |
| &ARMMCRegisterClasses[FPWithVPR_with_ssub_0RegClassID], |
| FPWithVPR_with_ssub_0SubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x0000000C), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| FPWithVPR_with_ssub_0Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRRegClass = { |
| &ARMMCRegisterClasses[GPRRegClassID], |
| GPRSubClassMask, |
| SuperRegIdxSeqs + 11, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| NullRegClasses, |
| GPRGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass GPRwithAPSRRegClass = { |
| &ARMMCRegisterClasses[GPRwithAPSRRegClassID], |
| GPRwithAPSRSubClassMask, |
| SuperRegIdxSeqs + 11, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| NullRegClasses, |
| GPRwithAPSRGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass GPRwithZRRegClass = { |
| &ARMMCRegisterClasses[GPRwithZRRegClassID], |
| GPRwithZRSubClassMask, |
| SuperRegIdxSeqs + 11, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| NullRegClasses, |
| GPRwithZRGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass SPR_8RegClass = { |
| &ARMMCRegisterClasses[SPR_8RegClassID], |
| SPR_8SubClassMask, |
| SuperRegIdxSeqs + 22, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| SPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRnopcRegClass = { |
| &ARMMCRegisterClasses[GPRnopcRegClassID], |
| GPRnopcSubClassMask, |
| SuperRegIdxSeqs + 11, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| GPRnopcSuperclasses, |
| GPRnopcGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass GPRwithAPSRnospRegClass = { |
| &ARMMCRegisterClasses[GPRwithAPSRnospRegClassID], |
| GPRwithAPSRnospSubClassMask, |
| SuperRegIdxSeqs + 11, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRwithZRnospRegClass = { |
| &ARMMCRegisterClasses[GPRwithZRnospRegClassID], |
| GPRwithZRnospSubClassMask, |
| SuperRegIdxSeqs + 11, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| GPRwithZRnospSuperclasses, |
| GPRwithZRnospGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass rGPRRegClass = { |
| &ARMMCRegisterClasses[rGPRRegClassID], |
| rGPRSubClassMask, |
| SuperRegIdxSeqs + 11, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| rGPRSuperclasses, |
| rGPRGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass tGPRwithpcRegClass = { |
| &ARMMCRegisterClasses[tGPRwithpcRegClassID], |
| tGPRwithpcSubClassMask, |
| SuperRegIdxSeqs + 11, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| tGPRwithpcSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClass = { |
| &ARMMCRegisterClasses[FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID], |
| FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8SubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x0000000C), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass hGPRRegClass = { |
| &ARMMCRegisterClasses[hGPRRegClassID], |
| hGPRSubClassMask, |
| SuperRegIdxSeqs + 11, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| hGPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass tGPRRegClass = { |
| &ARMMCRegisterClasses[tGPRRegClassID], |
| tGPRSubClassMask, |
| SuperRegIdxSeqs + 11, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| tGPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass tGPREvenRegClass = { |
| &ARMMCRegisterClasses[tGPREvenRegClassID], |
| tGPREvenSubClassMask, |
| SuperRegIdxSeqs + 9, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| tGPREvenSuperclasses, |
| tGPREvenGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass GPRnopc_and_hGPRRegClass = { |
| &ARMMCRegisterClasses[GPRnopc_and_hGPRRegClassID], |
| GPRnopc_and_hGPRSubClassMask, |
| SuperRegIdxSeqs + 11, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| GPRnopc_and_hGPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRwithAPSRnosp_and_hGPRRegClass = { |
| &ARMMCRegisterClasses[GPRwithAPSRnosp_and_hGPRRegClassID], |
| GPRwithAPSRnosp_and_hGPRSubClassMask, |
| SuperRegIdxSeqs + 11, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| GPRwithAPSRnosp_and_hGPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass tGPROddRegClass = { |
| &ARMMCRegisterClasses[tGPROddRegClassID], |
| tGPROddSubClassMask, |
| SuperRegIdxSeqs + 12, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| tGPROddSuperclasses, |
| tGPROddGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass tcGPRRegClass = { |
| &ARMMCRegisterClasses[tcGPRRegClassID], |
| tcGPRSubClassMask, |
| SuperRegIdxSeqs + 11, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| tcGPRSuperclasses, |
| tcGPRGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass hGPR_and_tGPREvenRegClass = { |
| &ARMMCRegisterClasses[hGPR_and_tGPREvenRegClassID], |
| hGPR_and_tGPREvenSubClassMask, |
| SuperRegIdxSeqs + 9, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| hGPR_and_tGPREvenSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass tGPR_and_tGPREvenRegClass = { |
| &ARMMCRegisterClasses[tGPR_and_tGPREvenRegClassID], |
| tGPR_and_tGPREvenSubClassMask, |
| SuperRegIdxSeqs + 9, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| tGPR_and_tGPREvenSuperclasses, |
| tGPR_and_tGPREvenGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass tGPR_and_tGPROddRegClass = { |
| &ARMMCRegisterClasses[tGPR_and_tGPROddRegClassID], |
| tGPR_and_tGPROddSubClassMask, |
| SuperRegIdxSeqs + 12, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| tGPR_and_tGPROddSuperclasses, |
| tGPR_and_tGPROddGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass tGPR_and_tcGPRRegClass = { |
| &ARMMCRegisterClasses[tGPR_and_tcGPRRegClassID], |
| tGPR_and_tcGPRSubClassMask, |
| SuperRegIdxSeqs + 11, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| tGPR_and_tcGPRSuperclasses, |
| tGPR_and_tcGPRGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass tGPREven_and_tcGPRRegClass = { |
| &ARMMCRegisterClasses[tGPREven_and_tcGPRRegClassID], |
| tGPREven_and_tcGPRSubClassMask, |
| SuperRegIdxSeqs + 9, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| tGPREven_and_tcGPRSuperclasses, |
| tGPREven_and_tcGPRGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass hGPR_and_tGPROddRegClass = { |
| &ARMMCRegisterClasses[hGPR_and_tGPROddRegClassID], |
| hGPR_and_tGPROddSubClassMask, |
| SuperRegIdxSeqs + 12, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| hGPR_and_tGPROddSuperclasses, |
| hGPR_and_tGPROddGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass tGPREven_and_tGPR_and_tcGPRRegClass = { |
| &ARMMCRegisterClasses[tGPREven_and_tGPR_and_tcGPRRegClassID], |
| tGPREven_and_tGPR_and_tcGPRSubClassMask, |
| SuperRegIdxSeqs + 9, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| tGPREven_and_tGPR_and_tcGPRSuperclasses, |
| tGPREven_and_tGPR_and_tcGPRGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass tGPROdd_and_tcGPRRegClass = { |
| &ARMMCRegisterClasses[tGPROdd_and_tcGPRRegClassID], |
| tGPROdd_and_tcGPRSubClassMask, |
| SuperRegIdxSeqs + 12, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| tGPROdd_and_tcGPRSuperclasses, |
| tGPROdd_and_tcGPRGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass CCRRegClass = { |
| &ARMMCRegisterClasses[CCRRegClassID], |
| CCRSubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRlrRegClass = { |
| &ARMMCRegisterClasses[GPRlrRegClassID], |
| GPRlrSubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| GPRlrSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRspRegClass = { |
| &ARMMCRegisterClasses[GPRspRegClassID], |
| GPRspSubClassMask, |
| SuperRegIdxSeqs + 12, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| GPRspSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass VCCRRegClass = { |
| &ARMMCRegisterClasses[VCCRRegClassID], |
| VCCRSubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| VCCRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass cl_FPSCR_NZCVRegClass = { |
| &ARMMCRegisterClasses[cl_FPSCR_NZCVRegClassID], |
| cl_FPSCR_NZCVSubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass hGPR_and_tGPRwithpcRegClass = { |
| &ARMMCRegisterClasses[hGPR_and_tGPRwithpcRegClassID], |
| hGPR_and_tGPRwithpcSubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| hGPR_and_tGPRwithpcSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass hGPR_and_tcGPRRegClass = { |
| &ARMMCRegisterClasses[hGPR_and_tcGPRRegClassID], |
| hGPR_and_tcGPRSubClassMask, |
| SuperRegIdxSeqs + 9, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| hGPR_and_tcGPRSuperclasses, |
| hGPR_and_tcGPRGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass DPRRegClass = { |
| &ARMMCRegisterClasses[DPRRegClassID], |
| DPRSubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x0000000C), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| DPRSuperclasses, |
| DPRGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass DPR_VFP2RegClass = { |
| &ARMMCRegisterClasses[DPR_VFP2RegClassID], |
| DPR_VFP2SubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x0000000C), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DPR_VFP2Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DPR_8RegClass = { |
| &ARMMCRegisterClasses[DPR_8RegClassID], |
| DPR_8SubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x0000000C), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRPairRegClass = { |
| &ARMMCRegisterClasses[GPRPairRegClassID], |
| GPRPairSubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x00000003), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRPairnospRegClass = { |
| &ARMMCRegisterClasses[GPRPairnospRegClassID], |
| GPRPairnospSubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x00000003), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| GPRPairnospSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRPair_with_gsub_0_in_tGPRRegClass = { |
| &ARMMCRegisterClasses[GPRPair_with_gsub_0_in_tGPRRegClassID], |
| GPRPair_with_gsub_0_in_tGPRSubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x00000003), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| GPRPair_with_gsub_0_in_tGPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRPair_with_gsub_0_in_hGPRRegClass = { |
| &ARMMCRegisterClasses[GPRPair_with_gsub_0_in_hGPRRegClassID], |
| GPRPair_with_gsub_0_in_hGPRSubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x00000003), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| GPRPair_with_gsub_0_in_hGPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRPair_with_gsub_0_in_tcGPRRegClass = { |
| &ARMMCRegisterClasses[GPRPair_with_gsub_0_in_tcGPRRegClassID], |
| GPRPair_with_gsub_0_in_tcGPRSubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x00000003), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| GPRPair_with_gsub_0_in_tcGPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRPair_with_gsub_1_in_tcGPRRegClass = { |
| &ARMMCRegisterClasses[GPRPair_with_gsub_1_in_tcGPRRegClassID], |
| GPRPair_with_gsub_1_in_tcGPRSubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x00000003), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| GPRPair_with_gsub_1_in_tcGPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClass = { |
| &ARMMCRegisterClasses[GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClassID], |
| GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRSubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x00000003), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRPair_with_gsub_1_in_GPRspRegClass = { |
| &ARMMCRegisterClasses[GPRPair_with_gsub_1_in_GPRspRegClassID], |
| GPRPair_with_gsub_1_in_GPRspSubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x00000003), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| GPRPair_with_gsub_1_in_GPRspSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DPairSpcRegClass = { |
| &ARMMCRegisterClasses[DPairSpcRegClassID], |
| DPairSpcSubClassMask, |
| SuperRegIdxSeqs + 58, |
| LaneBitmask(0x000000CC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DPairSpc_with_ssub_0RegClass = { |
| &ARMMCRegisterClasses[DPairSpc_with_ssub_0RegClassID], |
| DPairSpc_with_ssub_0SubClassMask, |
| SuperRegIdxSeqs + 58, |
| LaneBitmask(0x000000CC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DPairSpc_with_ssub_0Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DPairSpc_with_ssub_4RegClass = { |
| &ARMMCRegisterClasses[DPairSpc_with_ssub_4RegClassID], |
| DPairSpc_with_ssub_4SubClassMask, |
| SuperRegIdxSeqs + 58, |
| LaneBitmask(0x000000CC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DPairSpc_with_ssub_4Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DPairSpc_with_dsub_0_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[DPairSpc_with_dsub_0_in_DPR_8RegClassID], |
| DPairSpc_with_dsub_0_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 58, |
| LaneBitmask(0x000000CC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DPairSpc_with_dsub_0_in_DPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DPairSpc_with_dsub_2_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[DPairSpc_with_dsub_2_in_DPR_8RegClassID], |
| DPairSpc_with_dsub_2_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 58, |
| LaneBitmask(0x000000CC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DPairSpc_with_dsub_2_in_DPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DPairRegClass = { |
| &ARMMCRegisterClasses[DPairRegClassID], |
| DPairSubClassMask, |
| SuperRegIdxSeqs + 77, |
| LaneBitmask(0x0000003C), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| NullRegClasses, |
| DPairGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass DPair_with_ssub_0RegClass = { |
| &ARMMCRegisterClasses[DPair_with_ssub_0RegClassID], |
| DPair_with_ssub_0SubClassMask, |
| SuperRegIdxSeqs + 77, |
| LaneBitmask(0x0000003C), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DPair_with_ssub_0Superclasses, |
| DPair_with_ssub_0GetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass QPRRegClass = { |
| &ARMMCRegisterClasses[QPRRegClassID], |
| QPRSubClassMask, |
| SuperRegIdxSeqs + 39, |
| LaneBitmask(0x0000003C), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| QPRSuperclasses, |
| QPRGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass DPair_with_ssub_2RegClass = { |
| &ARMMCRegisterClasses[DPair_with_ssub_2RegClassID], |
| DPair_with_ssub_2SubClassMask, |
| SuperRegIdxSeqs + 77, |
| LaneBitmask(0x0000003C), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DPair_with_ssub_2Superclasses, |
| DPair_with_ssub_2GetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass DPair_with_dsub_0_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[DPair_with_dsub_0_in_DPR_8RegClassID], |
| DPair_with_dsub_0_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 77, |
| LaneBitmask(0x0000003C), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DPair_with_dsub_0_in_DPR_8Superclasses, |
| DPair_with_dsub_0_in_DPR_8GetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass MQPRRegClass = { |
| &ARMMCRegisterClasses[MQPRRegClassID], |
| MQPRSubClassMask, |
| SuperRegIdxSeqs + 39, |
| LaneBitmask(0x0000003C), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| MQPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass QPR_VFP2RegClass = { |
| &ARMMCRegisterClasses[QPR_VFP2RegClassID], |
| QPR_VFP2SubClassMask, |
| SuperRegIdxSeqs + 39, |
| LaneBitmask(0x0000003C), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| QPR_VFP2Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DPair_with_dsub_1_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[DPair_with_dsub_1_in_DPR_8RegClassID], |
| DPair_with_dsub_1_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 77, |
| LaneBitmask(0x0000003C), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DPair_with_dsub_1_in_DPR_8Superclasses, |
| DPair_with_dsub_1_in_DPR_8GetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass QPR_8RegClass = { |
| &ARMMCRegisterClasses[QPR_8RegClassID], |
| QPR_8SubClassMask, |
| SuperRegIdxSeqs + 39, |
| LaneBitmask(0x0000003C), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| QPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTripleRegClass = { |
| &ARMMCRegisterClasses[DTripleRegClassID], |
| DTripleSubClassMask, |
| SuperRegIdxSeqs + 70, |
| LaneBitmask(0x000000FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTripleSpcRegClass = { |
| &ARMMCRegisterClasses[DTripleSpcRegClassID], |
| DTripleSpcSubClassMask, |
| SuperRegIdxSeqs + 45, |
| LaneBitmask(0x00000CCC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTripleSpc_with_ssub_0RegClass = { |
| &ARMMCRegisterClasses[DTripleSpc_with_ssub_0RegClassID], |
| DTripleSpc_with_ssub_0SubClassMask, |
| SuperRegIdxSeqs + 45, |
| LaneBitmask(0x00000CCC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTripleSpc_with_ssub_0Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTriple_with_ssub_0RegClass = { |
| &ARMMCRegisterClasses[DTriple_with_ssub_0RegClassID], |
| DTriple_with_ssub_0SubClassMask, |
| SuperRegIdxSeqs + 70, |
| LaneBitmask(0x000000FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTriple_with_ssub_0Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTriple_with_qsub_0_in_QPRRegClass = { |
| &ARMMCRegisterClasses[DTriple_with_qsub_0_in_QPRRegClassID], |
| DTriple_with_qsub_0_in_QPRSubClassMask, |
| SuperRegIdxSeqs + 53, |
| LaneBitmask(0x000000FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTriple_with_qsub_0_in_QPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTriple_with_ssub_2RegClass = { |
| &ARMMCRegisterClasses[DTriple_with_ssub_2RegClassID], |
| DTriple_with_ssub_2SubClassMask, |
| SuperRegIdxSeqs + 70, |
| LaneBitmask(0x000000FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTriple_with_ssub_2Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = { |
| &ARMMCRegisterClasses[DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID], |
| DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask, |
| SuperRegIdxSeqs + 65, |
| LaneBitmask(0x000000FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTripleSpc_with_ssub_4RegClass = { |
| &ARMMCRegisterClasses[DTripleSpc_with_ssub_4RegClassID], |
| DTripleSpc_with_ssub_4SubClassMask, |
| SuperRegIdxSeqs + 45, |
| LaneBitmask(0x00000CCC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTripleSpc_with_ssub_4Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTriple_with_ssub_4RegClass = { |
| &ARMMCRegisterClasses[DTriple_with_ssub_4RegClassID], |
| DTriple_with_ssub_4SubClassMask, |
| SuperRegIdxSeqs + 70, |
| LaneBitmask(0x000000FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTriple_with_ssub_4Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTripleSpc_with_ssub_8RegClass = { |
| &ARMMCRegisterClasses[DTripleSpc_with_ssub_8RegClassID], |
| DTripleSpc_with_ssub_8SubClassMask, |
| SuperRegIdxSeqs + 45, |
| LaneBitmask(0x00000CCC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTripleSpc_with_ssub_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTripleSpc_with_dsub_0_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[DTripleSpc_with_dsub_0_in_DPR_8RegClassID], |
| DTripleSpc_with_dsub_0_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 45, |
| LaneBitmask(0x00000CCC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTripleSpc_with_dsub_0_in_DPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[DTriple_with_dsub_0_in_DPR_8RegClassID], |
| DTriple_with_dsub_0_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 70, |
| LaneBitmask(0x000000FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTriple_with_dsub_0_in_DPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTriple_with_qsub_0_in_MQPRRegClass = { |
| &ARMMCRegisterClasses[DTriple_with_qsub_0_in_MQPRRegClassID], |
| DTriple_with_qsub_0_in_MQPRSubClassMask, |
| SuperRegIdxSeqs + 53, |
| LaneBitmask(0x000000FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTriple_with_qsub_0_in_MQPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = { |
| &ARMMCRegisterClasses[DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID], |
| DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask, |
| SuperRegIdxSeqs + 65, |
| LaneBitmask(0x000000FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTriple_with_dsub_1_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[DTriple_with_dsub_1_in_DPR_8RegClassID], |
| DTriple_with_dsub_1_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 70, |
| LaneBitmask(0x000000FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTriple_with_dsub_1_in_DPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass = { |
| &ARMMCRegisterClasses[DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID], |
| DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask, |
| SuperRegIdxSeqs + 65, |
| LaneBitmask(0x000000FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClass = { |
| &ARMMCRegisterClasses[DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID], |
| DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRSubClassMask, |
| SuperRegIdxSeqs + 53, |
| LaneBitmask(0x000000FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTripleSpc_with_dsub_2_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[DTripleSpc_with_dsub_2_in_DPR_8RegClassID], |
| DTripleSpc_with_dsub_2_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 45, |
| LaneBitmask(0x00000CCC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTripleSpc_with_dsub_2_in_DPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[DTriple_with_dsub_2_in_DPR_8RegClassID], |
| DTriple_with_dsub_2_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 70, |
| LaneBitmask(0x000000FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTriple_with_dsub_2_in_DPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTripleSpc_with_dsub_4_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[DTripleSpc_with_dsub_4_in_DPR_8RegClassID], |
| DTripleSpc_with_dsub_4_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 45, |
| LaneBitmask(0x00000CCC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTripleSpc_with_dsub_4_in_DPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass = { |
| &ARMMCRegisterClasses[DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID], |
| DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask, |
| SuperRegIdxSeqs + 65, |
| LaneBitmask(0x000000FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_8RegClass = { |
| &ARMMCRegisterClasses[DTriple_with_qsub_0_in_QPR_8RegClassID], |
| DTriple_with_qsub_0_in_QPR_8SubClassMask, |
| SuperRegIdxSeqs + 53, |
| LaneBitmask(0x000000FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTriple_with_qsub_0_in_QPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRRegClass = { |
| &ARMMCRegisterClasses[DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRRegClassID], |
| DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRSubClassMask, |
| SuperRegIdxSeqs + 53, |
| LaneBitmask(0x000000FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass = { |
| &ARMMCRegisterClasses[DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID], |
| DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask, |
| SuperRegIdxSeqs + 65, |
| LaneBitmask(0x000000FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuadSpcRegClass = { |
| &ARMMCRegisterClasses[DQuadSpcRegClassID], |
| DQuadSpcSubClassMask, |
| SuperRegIdxSeqs + 45, |
| LaneBitmask(0x00000CCC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuadSpcSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuadSpc_with_ssub_0RegClass = { |
| &ARMMCRegisterClasses[DQuadSpc_with_ssub_0RegClassID], |
| DQuadSpc_with_ssub_0SubClassMask, |
| SuperRegIdxSeqs + 45, |
| LaneBitmask(0x00000CCC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuadSpc_with_ssub_0Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuadSpc_with_ssub_4RegClass = { |
| &ARMMCRegisterClasses[DQuadSpc_with_ssub_4RegClassID], |
| DQuadSpc_with_ssub_4SubClassMask, |
| SuperRegIdxSeqs + 45, |
| LaneBitmask(0x00000CCC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuadSpc_with_ssub_4Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuadSpc_with_ssub_8RegClass = { |
| &ARMMCRegisterClasses[DQuadSpc_with_ssub_8RegClassID], |
| DQuadSpc_with_ssub_8SubClassMask, |
| SuperRegIdxSeqs + 45, |
| LaneBitmask(0x00000CCC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuadSpc_with_ssub_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuadSpc_with_dsub_0_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[DQuadSpc_with_dsub_0_in_DPR_8RegClassID], |
| DQuadSpc_with_dsub_0_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 45, |
| LaneBitmask(0x00000CCC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuadSpc_with_dsub_0_in_DPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuadSpc_with_dsub_2_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[DQuadSpc_with_dsub_2_in_DPR_8RegClassID], |
| DQuadSpc_with_dsub_2_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 45, |
| LaneBitmask(0x00000CCC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuadSpc_with_dsub_2_in_DPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuadSpc_with_dsub_4_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[DQuadSpc_with_dsub_4_in_DPR_8RegClassID], |
| DQuadSpc_with_dsub_4_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 45, |
| LaneBitmask(0x00000CCC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuadSpc_with_dsub_4_in_DPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuadRegClass = { |
| &ARMMCRegisterClasses[DQuadRegClassID], |
| DQuadSubClassMask, |
| SuperRegIdxSeqs + 89, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuad_with_ssub_0RegClass = { |
| &ARMMCRegisterClasses[DQuad_with_ssub_0RegClassID], |
| DQuad_with_ssub_0SubClassMask, |
| SuperRegIdxSeqs + 89, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuad_with_ssub_0Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuad_with_ssub_2RegClass = { |
| &ARMMCRegisterClasses[DQuad_with_ssub_2RegClassID], |
| DQuad_with_ssub_2SubClassMask, |
| SuperRegIdxSeqs + 89, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuad_with_ssub_2Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass QQPRRegClass = { |
| &ARMMCRegisterClasses[QQPRRegClassID], |
| QQPRSubClassMask, |
| SuperRegIdxSeqs + 85, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| QQPRSuperclasses, |
| QQPRGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = { |
| &ARMMCRegisterClasses[DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID], |
| DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask, |
| SuperRegIdxSeqs + 50, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuad_with_ssub_4RegClass = { |
| &ARMMCRegisterClasses[DQuad_with_ssub_4RegClassID], |
| DQuad_with_ssub_4SubClassMask, |
| SuperRegIdxSeqs + 89, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuad_with_ssub_4Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuad_with_ssub_6RegClass = { |
| &ARMMCRegisterClasses[DQuad_with_ssub_6RegClassID], |
| DQuad_with_ssub_6SubClassMask, |
| SuperRegIdxSeqs + 89, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuad_with_ssub_6Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[DQuad_with_dsub_0_in_DPR_8RegClassID], |
| DQuad_with_dsub_0_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 89, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuad_with_dsub_0_in_DPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuad_with_qsub_0_in_MQPRRegClass = { |
| &ARMMCRegisterClasses[DQuad_with_qsub_0_in_MQPRRegClassID], |
| DQuad_with_qsub_0_in_MQPRSubClassMask, |
| SuperRegIdxSeqs + 85, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuad_with_qsub_0_in_MQPRSuperclasses, |
| DQuad_with_qsub_0_in_MQPRGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = { |
| &ARMMCRegisterClasses[DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID], |
| DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSubClassMask, |
| SuperRegIdxSeqs + 50, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuad_with_dsub_1_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[DQuad_with_dsub_1_in_DPR_8RegClassID], |
| DQuad_with_dsub_1_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 89, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuad_with_dsub_1_in_DPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuad_with_qsub_1_in_MQPRRegClass = { |
| &ARMMCRegisterClasses[DQuad_with_qsub_1_in_MQPRRegClassID], |
| DQuad_with_qsub_1_in_MQPRSubClassMask, |
| SuperRegIdxSeqs + 85, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuad_with_qsub_1_in_MQPRSuperclasses, |
| DQuad_with_qsub_1_in_MQPRGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass = { |
| &ARMMCRegisterClasses[DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID], |
| DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask, |
| SuperRegIdxSeqs + 50, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuad_with_dsub_2_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[DQuad_with_dsub_2_in_DPR_8RegClassID], |
| DQuad_with_dsub_2_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 89, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuad_with_dsub_2_in_DPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass = { |
| &ARMMCRegisterClasses[DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID], |
| DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask, |
| SuperRegIdxSeqs + 50, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[DQuad_with_dsub_3_in_DPR_8RegClassID], |
| DQuad_with_dsub_3_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 89, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuad_with_dsub_3_in_DPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass = { |
| &ARMMCRegisterClasses[DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID], |
| DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask, |
| SuperRegIdxSeqs + 50, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_8RegClass = { |
| &ARMMCRegisterClasses[DQuad_with_qsub_0_in_QPR_8RegClassID], |
| DQuad_with_qsub_0_in_QPR_8SubClassMask, |
| SuperRegIdxSeqs + 85, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuad_with_qsub_0_in_QPR_8Superclasses, |
| DQuad_with_qsub_0_in_QPR_8GetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_8RegClass = { |
| &ARMMCRegisterClasses[DQuad_with_qsub_1_in_QPR_8RegClassID], |
| DQuad_with_qsub_1_in_QPR_8SubClassMask, |
| SuperRegIdxSeqs + 85, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuad_with_qsub_1_in_QPR_8Superclasses, |
| DQuad_with_qsub_1_in_QPR_8GetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass = { |
| &ARMMCRegisterClasses[DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID], |
| DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8SubClassMask, |
| SuperRegIdxSeqs + 50, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass = { |
| &ARMMCRegisterClasses[DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID], |
| DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSubClassMask, |
| SuperRegIdxSeqs + 50, |
| LaneBitmask(0x000003FC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass QQQQPRRegClass = { |
| &ARMMCRegisterClasses[QQQQPRRegClassID], |
| QQQQPRSubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x0003FFFC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| NullRegClasses, |
| QQQQPRGetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass QQQQPR_with_ssub_0RegClass = { |
| &ARMMCRegisterClasses[QQQQPR_with_ssub_0RegClassID], |
| QQQQPR_with_ssub_0SubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x0003FFFC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| QQQQPR_with_ssub_0Superclasses, |
| QQQQPR_with_ssub_0GetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass QQQQPR_with_ssub_4RegClass = { |
| &ARMMCRegisterClasses[QQQQPR_with_ssub_4RegClassID], |
| QQQQPR_with_ssub_4SubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x0003FFFC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| QQQQPR_with_ssub_4Superclasses, |
| QQQQPR_with_ssub_4GetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass QQQQPR_with_ssub_8RegClass = { |
| &ARMMCRegisterClasses[QQQQPR_with_ssub_8RegClassID], |
| QQQQPR_with_ssub_8SubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x0003FFFC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| QQQQPR_with_ssub_8Superclasses, |
| QQQQPR_with_ssub_8GetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass QQQQPR_with_ssub_12RegClass = { |
| &ARMMCRegisterClasses[QQQQPR_with_ssub_12RegClassID], |
| QQQQPR_with_ssub_12SubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x0003FFFC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| QQQQPR_with_ssub_12Superclasses, |
| QQQQPR_with_ssub_12GetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass QQQQPR_with_dsub_0_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[QQQQPR_with_dsub_0_in_DPR_8RegClassID], |
| QQQQPR_with_dsub_0_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x0003FFFC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| QQQQPR_with_dsub_0_in_DPR_8Superclasses, |
| QQQQPR_with_dsub_0_in_DPR_8GetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass QQQQPR_with_dsub_2_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[QQQQPR_with_dsub_2_in_DPR_8RegClassID], |
| QQQQPR_with_dsub_2_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x0003FFFC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| QQQQPR_with_dsub_2_in_DPR_8Superclasses, |
| QQQQPR_with_dsub_2_in_DPR_8GetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass QQQQPR_with_dsub_4_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[QQQQPR_with_dsub_4_in_DPR_8RegClassID], |
| QQQQPR_with_dsub_4_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x0003FFFC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| QQQQPR_with_dsub_4_in_DPR_8Superclasses, |
| QQQQPR_with_dsub_4_in_DPR_8GetRawAllocationOrder |
| }; |
| |
| extern const TargetRegisterClass QQQQPR_with_dsub_6_in_DPR_8RegClass = { |
| &ARMMCRegisterClasses[QQQQPR_with_dsub_6_in_DPR_8RegClassID], |
| QQQQPR_with_dsub_6_in_DPR_8SubClassMask, |
| SuperRegIdxSeqs + 8, |
| LaneBitmask(0x0003FFFC), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| QQQQPR_with_dsub_6_in_DPR_8Superclasses, |
| QQQQPR_with_dsub_6_in_DPR_8GetRawAllocationOrder |
| }; |
| |
| } // end namespace ARM |
| |
| namespace { |
| const TargetRegisterClass* const RegisterClasses[] = { |
| &ARM::HPRRegClass, |
| &ARM::FPWithVPRRegClass, |
| &ARM::SPRRegClass, |
| &ARM::FPWithVPR_with_ssub_0RegClass, |
| &ARM::GPRRegClass, |
| &ARM::GPRwithAPSRRegClass, |
| &ARM::GPRwithZRRegClass, |
| &ARM::SPR_8RegClass, |
| &ARM::GPRnopcRegClass, |
| &ARM::GPRwithAPSRnospRegClass, |
| &ARM::GPRwithZRnospRegClass, |
| &ARM::rGPRRegClass, |
| &ARM::tGPRwithpcRegClass, |
| &ARM::FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClass, |
| &ARM::hGPRRegClass, |
| &ARM::tGPRRegClass, |
| &ARM::tGPREvenRegClass, |
| &ARM::GPRnopc_and_hGPRRegClass, |
| &ARM::GPRwithAPSRnosp_and_hGPRRegClass, |
| &ARM::tGPROddRegClass, |
| &ARM::tcGPRRegClass, |
| &ARM::hGPR_and_tGPREvenRegClass, |
| &ARM::tGPR_and_tGPREvenRegClass, |
| &ARM::tGPR_and_tGPROddRegClass, |
| &ARM::tGPR_and_tcGPRRegClass, |
| &ARM::tGPREven_and_tcGPRRegClass, |
| &ARM::hGPR_and_tGPROddRegClass, |
| &ARM::tGPREven_and_tGPR_and_tcGPRRegClass, |
| &ARM::tGPROdd_and_tcGPRRegClass, |
| &ARM::CCRRegClass, |
| &ARM::GPRlrRegClass, |
| &ARM::GPRspRegClass, |
| &ARM::VCCRRegClass, |
| &ARM::cl_FPSCR_NZCVRegClass, |
| &ARM::hGPR_and_tGPRwithpcRegClass, |
| &ARM::hGPR_and_tcGPRRegClass, |
| &ARM::DPRRegClass, |
| &ARM::DPR_VFP2RegClass, |
| &ARM::DPR_8RegClass, |
| &ARM::GPRPairRegClass, |
| &ARM::GPRPairnospRegClass, |
| &ARM::GPRPair_with_gsub_0_in_tGPRRegClass, |
| &ARM::GPRPair_with_gsub_0_in_hGPRRegClass, |
| &ARM::GPRPair_with_gsub_0_in_tcGPRRegClass, |
| &ARM::GPRPair_with_gsub_1_in_tcGPRRegClass, |
| &ARM::GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClass, |
| &ARM::GPRPair_with_gsub_1_in_GPRspRegClass, |
| &ARM::DPairSpcRegClass, |
| &ARM::DPairSpc_with_ssub_0RegClass, |
| &ARM::DPairSpc_with_ssub_4RegClass, |
| &ARM::DPairSpc_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DPairSpc_with_dsub_2_in_DPR_8RegClass, |
| &ARM::DPairRegClass, |
| &ARM::DPair_with_ssub_0RegClass, |
| &ARM::QPRRegClass, |
| &ARM::DPair_with_ssub_2RegClass, |
| &ARM::DPair_with_dsub_0_in_DPR_8RegClass, |
| &ARM::MQPRRegClass, |
| &ARM::QPR_VFP2RegClass, |
| &ARM::DPair_with_dsub_1_in_DPR_8RegClass, |
| &ARM::QPR_8RegClass, |
| &ARM::DTripleRegClass, |
| &ARM::DTripleSpcRegClass, |
| &ARM::DTripleSpc_with_ssub_0RegClass, |
| &ARM::DTriple_with_ssub_0RegClass, |
| &ARM::DTriple_with_qsub_0_in_QPRRegClass, |
| &ARM::DTriple_with_ssub_2RegClass, |
| &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| &ARM::DTripleSpc_with_ssub_4RegClass, |
| &ARM::DTriple_with_ssub_4RegClass, |
| &ARM::DTripleSpc_with_ssub_8RegClass, |
| &ARM::DTripleSpc_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DTriple_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DTriple_with_qsub_0_in_MQPRRegClass, |
| &ARM::DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| &ARM::DTriple_with_dsub_1_in_DPR_8RegClass, |
| &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, |
| &ARM::DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClass, |
| &ARM::DTripleSpc_with_dsub_2_in_DPR_8RegClass, |
| &ARM::DTriple_with_dsub_2_in_DPR_8RegClass, |
| &ARM::DTripleSpc_with_dsub_4_in_DPR_8RegClass, |
| &ARM::DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, |
| &ARM::DTriple_with_qsub_0_in_QPR_8RegClass, |
| &ARM::DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRRegClass, |
| &ARM::DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass, |
| &ARM::DQuadSpcRegClass, |
| &ARM::DQuadSpc_with_ssub_0RegClass, |
| &ARM::DQuadSpc_with_ssub_4RegClass, |
| &ARM::DQuadSpc_with_ssub_8RegClass, |
| &ARM::DQuadSpc_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DQuadSpc_with_dsub_2_in_DPR_8RegClass, |
| &ARM::DQuadSpc_with_dsub_4_in_DPR_8RegClass, |
| &ARM::DQuadRegClass, |
| &ARM::DQuad_with_ssub_0RegClass, |
| &ARM::DQuad_with_ssub_2RegClass, |
| &ARM::QQPRRegClass, |
| &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| &ARM::DQuad_with_ssub_4RegClass, |
| &ARM::DQuad_with_ssub_6RegClass, |
| &ARM::DQuad_with_dsub_0_in_DPR_8RegClass, |
| &ARM::DQuad_with_qsub_0_in_MQPRRegClass, |
| &ARM::DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass, |
| &ARM::DQuad_with_dsub_1_in_DPR_8RegClass, |
| &ARM::DQuad_with_qsub_1_in_MQPRRegClass, |
| &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, |
| &ARM::DQuad_with_dsub_2_in_DPR_8RegClass, |
| &ARM::DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, |
| &ARM::DQuad_with_dsub_3_in_DPR_8RegClass, |
| &ARM::DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, |
| &ARM::DQuad_with_qsub_0_in_QPR_8RegClass, |
| &ARM::DQuad_with_qsub_1_in_QPR_8RegClass, |
| &ARM::DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass, |
| &ARM::DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass, |
| &ARM::QQQQPRRegClass, |
| &ARM::QQQQPR_with_ssub_0RegClass, |
| &ARM::QQQQPR_with_ssub_4RegClass, |
| &ARM::QQQQPR_with_ssub_8RegClass, |
| &ARM::QQQQPR_with_ssub_12RegClass, |
| &ARM::QQQQPR_with_dsub_0_in_DPR_8RegClass, |
| &ARM::QQQQPR_with_dsub_2_in_DPR_8RegClass, |
| &ARM::QQQQPR_with_dsub_4_in_DPR_8RegClass, |
| &ARM::QQQQPR_with_dsub_6_in_DPR_8RegClass, |
| }; |
| } // end anonymous namespace |
| |
| static const TargetRegisterInfoDesc ARMRegInfoDesc[] = { // Extra Descriptors |
| { 0, false }, |
| { 0, false }, |
| { 0, true }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, true }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 1, true }, |
| { 1, true }, |
| { 1, true }, |
| { 0, false }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 1, true }, |
| { 1, true }, |
| { 1, true }, |
| { 1, true }, |
| { 1, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 1, true }, |
| { 1, true }, |
| { 1, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| }; |
| unsigned ARMGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const { |
| static const uint8_t RowMap[56] = { |
| 0, 1, 2, 3, 4, 5, 6, 7, 0, 0, 0, 4, 0, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 5, 5, 5, 2, |
| }; |
| static const uint8_t Rows[8][56] = { |
| { ARM::dsub_0, ARM::dsub_1, ARM::dsub_2, ARM::dsub_3, ARM::dsub_4, 0, ARM::dsub_6, 0, 0, 0, 0, 0, ARM::qsub_0, ARM::qsub_1, 0, 0, ARM::ssub_0, ARM::ssub_1, ARM::ssub_2, ARM::ssub_3, ARM::ssub_4, ARM::ssub_5, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, 0, 0, ARM::ssub_12, ARM::ssub_13, 0, 0, ARM::ssub_0_ssub_1_ssub_4_ssub_5, ARM::ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_2_ssub_3_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9, 0, 0, 0, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, ARM::ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, }, |
| { ARM::dsub_1, ARM::dsub_2, ARM::dsub_3, ARM::dsub_4, ARM::dsub_5, 0, ARM::dsub_7, 0, 0, 0, 0, 0, ARM::ssub_2_ssub_3_ssub_4_ssub_5, ARM::ssub_6_ssub_7_ssub_8_ssub_9, 0, 0, ARM::ssub_2, ARM::ssub_3, ARM::ssub_4, ARM::ssub_5, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, ARM::ssub_10, ARM::ssub_11, 0, 0, ARM::dsub_7_then_ssub_0, ARM::dsub_7_then_ssub_1, 0, 0, ARM::ssub_2_ssub_3_ssub_6_ssub_7, ARM::ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, ARM::ssub_4_ssub_5_ssub_8_ssub_9, ARM::ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, ARM::qsub_1, ARM::ssub_2_ssub_3_ssub_6_ssub_7_dsub_5, 0, 0, 0, 0, ARM::ssub_6_ssub_7_dsub_5, 0, ARM::ssub_6_ssub_7_dsub_5_dsub_7, 0, 0, 0, 0, 0, ARM::dsub_5_dsub_7, 0, 0, 0, 0, 0, }, |
| { ARM::dsub_2, ARM::dsub_3, ARM::dsub_4, ARM::dsub_5, ARM::dsub_6, 0, 0, 0, 0, 0, 0, 0, ARM::qsub_1, ARM::qsub_2, 0, 0, ARM::ssub_4, ARM::ssub_5, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, ARM::ssub_10, ARM::ssub_11, ARM::ssub_12, ARM::ssub_13, 0, 0, 0, 0, 0, 0, ARM::ssub_4_ssub_5_ssub_8_ssub_9, ARM::ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, ARM::ssub_6_ssub_7_dsub_5, ARM::ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, ARM::ssub_6_ssub_7_ssub_8_ssub_9, 0, 0, 0, 0, 0, ARM::ssub_8_ssub_9_ssub_12_ssub_13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, |
| { ARM::dsub_3, ARM::dsub_4, ARM::dsub_5, ARM::dsub_6, ARM::dsub_7, 0, 0, 0, 0, 0, 0, 0, ARM::ssub_6_ssub_7_ssub_8_ssub_9, ARM::dsub_5_ssub_12_ssub_13, 0, 0, ARM::ssub_6, ARM::ssub_7, ARM::ssub_8, ARM::ssub_9, ARM::ssub_10, ARM::ssub_11, ARM::ssub_12, ARM::ssub_13, ARM::dsub_7_then_ssub_0, ARM::dsub_7_then_ssub_1, 0, 0, 0, 0, 0, 0, ARM::ssub_6_ssub_7_dsub_5, ARM::ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, ARM::ssub_8_ssub_9_ssub_12_ssub_13, ARM::ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, ARM::qsub_2, 0, 0, 0, 0, 0, ARM::dsub_5_dsub_7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, |
| { ARM::dsub_4, ARM::dsub_5, ARM::dsub_6, ARM::dsub_7, 0, 0, 0, 0, 0, 0, 0, 0, ARM::qsub_2, ARM::qsub_3, 0, 0, ARM::ssub_8, ARM::ssub_9, ARM::ssub_10, ARM::ssub_11, ARM::ssub_12, ARM::ssub_13, ARM::dsub_7_then_ssub_0, ARM::dsub_7_then_ssub_1, 0, 0, 0, 0, 0, 0, 0, 0, ARM::ssub_8_ssub_9_ssub_12_ssub_13, ARM::ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, ARM::dsub_5_dsub_7, ARM::dsub_5_ssub_12_ssub_13_dsub_7, ARM::dsub_5_ssub_12_ssub_13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, |
| { ARM::dsub_5, ARM::dsub_6, ARM::dsub_7, 0, 0, 0, 0, 0, 0, 0, 0, 0, ARM::dsub_5_ssub_12_ssub_13, 0, 0, 0, ARM::ssub_10, ARM::ssub_11, ARM::ssub_12, ARM::ssub_13, ARM::dsub_7_then_ssub_0, ARM::dsub_7_then_ssub_1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ARM::dsub_5_dsub_7, 0, 0, 0, ARM::qsub_3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, |
| { ARM::dsub_6, ARM::dsub_7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ARM::ssub_12, ARM::ssub_13, ARM::dsub_7_then_ssub_0, ARM::dsub_7_then_ssub_1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, |
| { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ARM::dsub_7_then_ssub_0, ARM::dsub_7_then_ssub_1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, |
| }; |
| |
| --IdxA; assert(IdxA < 56); |
| --IdxB; assert(IdxB < 56); |
| return Rows[RowMap[IdxA]][IdxB]; |
| } |
| |
| struct MaskRolOp { |
| LaneBitmask Mask; |
| uint8_t RotateLeft; |
| }; |
| static const MaskRolOp LaneMaskComposeSequences[] = { |
| { LaneBitmask(0xFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0 |
| { LaneBitmask(0xFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 2 |
| { LaneBitmask(0xFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 4 |
| { LaneBitmask(0xFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 }, // Sequence 6 |
| { LaneBitmask(0xFFFFFFFF), 8 }, { LaneBitmask::getNone(), 0 }, // Sequence 8 |
| { LaneBitmask(0xFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 }, // Sequence 10 |
| { LaneBitmask(0xFFFFFFFF), 12 }, { LaneBitmask::getNone(), 0 }, // Sequence 12 |
| { LaneBitmask(0xFFFFFFFF), 14 }, { LaneBitmask::getNone(), 0 }, // Sequence 14 |
| { LaneBitmask(0xFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 16 |
| { LaneBitmask(0xFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 18 |
| { LaneBitmask(0xFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 20 |
| { LaneBitmask(0xFFFFFFFF), 7 }, { LaneBitmask::getNone(), 0 }, // Sequence 22 |
| { LaneBitmask(0xFFFFFFFF), 9 }, { LaneBitmask::getNone(), 0 }, // Sequence 24 |
| { LaneBitmask(0xFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 }, // Sequence 26 |
| { LaneBitmask(0xFFFFFFFF), 13 }, { LaneBitmask::getNone(), 0 }, // Sequence 28 |
| { LaneBitmask(0xFFFFFFFF), 15 }, { LaneBitmask::getNone(), 0 }, // Sequence 30 |
| { LaneBitmask(0xFFFFFFFF), 16 }, { LaneBitmask::getNone(), 0 }, // Sequence 32 |
| { LaneBitmask(0xFFFFFFFF), 17 }, { LaneBitmask::getNone(), 0 } // Sequence 34 |
| }; |
| static const MaskRolOp *const CompositeSequences[] = { |
| &LaneMaskComposeSequences[0], // to dsub_0 |
| &LaneMaskComposeSequences[2], // to dsub_1 |
| &LaneMaskComposeSequences[4], // to dsub_2 |
| &LaneMaskComposeSequences[6], // to dsub_3 |
| &LaneMaskComposeSequences[8], // to dsub_4 |
| &LaneMaskComposeSequences[10], // to dsub_5 |
| &LaneMaskComposeSequences[12], // to dsub_6 |
| &LaneMaskComposeSequences[14], // to dsub_7 |
| &LaneMaskComposeSequences[0], // to gsub_0 |
| &LaneMaskComposeSequences[16], // to gsub_1 |
| &LaneMaskComposeSequences[0], // to qqsub_0 |
| &LaneMaskComposeSequences[8], // to qqsub_1 |
| &LaneMaskComposeSequences[0], // to qsub_0 |
| &LaneMaskComposeSequences[4], // to qsub_1 |
| &LaneMaskComposeSequences[8], // to qsub_2 |
| &LaneMaskComposeSequences[12], // to qsub_3 |
| &LaneMaskComposeSequences[2], // to ssub_0 |
| &LaneMaskComposeSequences[18], // to ssub_1 |
| &LaneMaskComposeSequences[4], // to ssub_2 |
| &LaneMaskComposeSequences[20], // to ssub_3 |
| &LaneMaskComposeSequences[6], // to ssub_4 |
| &LaneMaskComposeSequences[22], // to ssub_5 |
| &LaneMaskComposeSequences[8], // to ssub_6 |
| &LaneMaskComposeSequences[24], // to ssub_7 |
| &LaneMaskComposeSequences[10], // to ssub_8 |
| &LaneMaskComposeSequences[26], // to ssub_9 |
| &LaneMaskComposeSequences[12], // to ssub_10 |
| &LaneMaskComposeSequences[28], // to ssub_11 |
| &LaneMaskComposeSequences[14], // to ssub_12 |
| &LaneMaskComposeSequences[30], // to ssub_13 |
| &LaneMaskComposeSequences[32], // to dsub_7_then_ssub_0 |
| &LaneMaskComposeSequences[34], // to dsub_7_then_ssub_1 |
| &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_4_ssub_5 |
| &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_6_ssub_7 |
| &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_4_ssub_5 |
| &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| &LaneMaskComposeSequences[0], // to ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| &LaneMaskComposeSequences[2], // to ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| &LaneMaskComposeSequences[4], // to ssub_4_ssub_5_ssub_8_ssub_9 |
| &LaneMaskComposeSequences[4], // to ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| &LaneMaskComposeSequences[4], // to ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_dsub_5 |
| &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_dsub_5_dsub_7 |
| &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_ssub_8_ssub_9 |
| &LaneMaskComposeSequences[6], // to ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| &LaneMaskComposeSequences[8], // to ssub_8_ssub_9_ssub_12_ssub_13 |
| &LaneMaskComposeSequences[8], // to ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| &LaneMaskComposeSequences[10], // to dsub_5_dsub_7 |
| &LaneMaskComposeSequences[10], // to dsub_5_ssub_12_ssub_13_dsub_7 |
| &LaneMaskComposeSequences[10], // to dsub_5_ssub_12_ssub_13 |
| &LaneMaskComposeSequences[4] // to ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }; |
| |
| LaneBitmask ARMGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { |
| --IdxA; assert(IdxA < 56 && "Subregister index out of bounds"); |
| LaneBitmask Result; |
| for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) { |
| LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger(); |
| if (unsigned S = Ops->RotateLeft) |
| Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S))); |
| else |
| Result |= LaneBitmask(M); |
| } |
| return Result; |
| } |
| |
| LaneBitmask ARMGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { |
| LaneMask &= getSubRegIndexLaneMask(IdxA); |
| --IdxA; assert(IdxA < 56 && "Subregister index out of bounds"); |
| LaneBitmask Result; |
| for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) { |
| LaneBitmask::Type M = LaneMask.getAsInteger(); |
| if (unsigned S = Ops->RotateLeft) |
| Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S))); |
| else |
| Result |= LaneBitmask(M); |
| } |
| return Result; |
| } |
| |
| const TargetRegisterClass *ARMGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { |
| static const uint8_t Table[122][56] = { |
| { // HPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // FPWithVPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 4, // ssub_0 -> FPWithVPR_with_ssub_0 |
| 4, // ssub_1 -> FPWithVPR_with_ssub_0 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // SPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // FPWithVPR_with_ssub_0 |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 4, // ssub_0 -> FPWithVPR_with_ssub_0 |
| 4, // ssub_1 -> FPWithVPR_with_ssub_0 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // GPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // GPRwithAPSR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // GPRwithZR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // SPR_8 |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // GPRnopc |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // GPRwithAPSRnosp |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // GPRwithZRnosp |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // rGPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // tGPRwithpc |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 14, // ssub_0 -> FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 |
| 14, // ssub_1 -> FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // hGPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // tGPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // tGPREven |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // GPRnopc_and_hGPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // GPRwithAPSRnosp_and_hGPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // tGPROdd |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // tcGPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // hGPR_and_tGPREven |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // tGPR_and_tGPREven |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // tGPR_and_tGPROdd |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // tGPR_and_tcGPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // tGPREven_and_tcGPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // hGPR_and_tGPROdd |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // tGPREven_and_tGPR_and_tcGPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // tGPROdd_and_tcGPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // CCR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // GPRlr |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // GPRsp |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // VCCR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // cl_FPSCR_NZCV |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // hGPR_and_tGPRwithpc |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // hGPR_and_tcGPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 38, // ssub_0 -> DPR_VFP2 |
| 38, // ssub_1 -> DPR_VFP2 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DPR_VFP2 |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 38, // ssub_0 -> DPR_VFP2 |
| 38, // ssub_1 -> DPR_VFP2 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DPR_8 |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 39, // ssub_0 -> DPR_8 |
| 39, // ssub_1 -> DPR_8 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // GPRPair |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 40, // gsub_0 -> GPRPair |
| 40, // gsub_1 -> GPRPair |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // GPRPairnosp |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 41, // gsub_0 -> GPRPairnosp |
| 41, // gsub_1 -> GPRPairnosp |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // GPRPair_with_gsub_0_in_tGPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 42, // gsub_0 -> GPRPair_with_gsub_0_in_tGPR |
| 42, // gsub_1 -> GPRPair_with_gsub_0_in_tGPR |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // GPRPair_with_gsub_0_in_hGPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 43, // gsub_0 -> GPRPair_with_gsub_0_in_hGPR |
| 43, // gsub_1 -> GPRPair_with_gsub_0_in_hGPR |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // GPRPair_with_gsub_0_in_tcGPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 44, // gsub_0 -> GPRPair_with_gsub_0_in_tcGPR |
| 44, // gsub_1 -> GPRPair_with_gsub_0_in_tcGPR |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // GPRPair_with_gsub_1_in_tcGPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 45, // gsub_0 -> GPRPair_with_gsub_1_in_tcGPR |
| 45, // gsub_1 -> GPRPair_with_gsub_1_in_tcGPR |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 46, // gsub_0 -> GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR |
| 46, // gsub_1 -> GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // GPRPair_with_gsub_1_in_GPRsp |
| 0, // dsub_0 |
| 0, // dsub_1 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 47, // gsub_0 -> GPRPair_with_gsub_1_in_GPRsp |
| 47, // gsub_1 -> GPRPair_with_gsub_1_in_GPRsp |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 0, // ssub_0 |
| 0, // ssub_1 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DPairSpc |
| 48, // dsub_0 -> DPairSpc |
| 0, // dsub_1 |
| 48, // dsub_2 -> DPairSpc |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 49, // ssub_0 -> DPairSpc_with_ssub_0 |
| 49, // ssub_1 -> DPairSpc_with_ssub_0 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 50, // ssub_4 -> DPairSpc_with_ssub_4 |
| 50, // ssub_5 -> DPairSpc_with_ssub_4 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DPairSpc_with_ssub_0 |
| 49, // dsub_0 -> DPairSpc_with_ssub_0 |
| 0, // dsub_1 |
| 49, // dsub_2 -> DPairSpc_with_ssub_0 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 49, // ssub_0 -> DPairSpc_with_ssub_0 |
| 49, // ssub_1 -> DPairSpc_with_ssub_0 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 50, // ssub_4 -> DPairSpc_with_ssub_4 |
| 50, // ssub_5 -> DPairSpc_with_ssub_4 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DPairSpc_with_ssub_4 |
| 50, // dsub_0 -> DPairSpc_with_ssub_4 |
| 0, // dsub_1 |
| 50, // dsub_2 -> DPairSpc_with_ssub_4 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 50, // ssub_0 -> DPairSpc_with_ssub_4 |
| 50, // ssub_1 -> DPairSpc_with_ssub_4 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 50, // ssub_4 -> DPairSpc_with_ssub_4 |
| 50, // ssub_5 -> DPairSpc_with_ssub_4 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DPairSpc_with_dsub_0_in_DPR_8 |
| 51, // dsub_0 -> DPairSpc_with_dsub_0_in_DPR_8 |
| 0, // dsub_1 |
| 51, // dsub_2 -> DPairSpc_with_dsub_0_in_DPR_8 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 51, // ssub_0 -> DPairSpc_with_dsub_0_in_DPR_8 |
| 51, // ssub_1 -> DPairSpc_with_dsub_0_in_DPR_8 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 51, // ssub_4 -> DPairSpc_with_dsub_0_in_DPR_8 |
| 51, // ssub_5 -> DPairSpc_with_dsub_0_in_DPR_8 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DPairSpc_with_dsub_2_in_DPR_8 |
| 52, // dsub_0 -> DPairSpc_with_dsub_2_in_DPR_8 |
| 0, // dsub_1 |
| 52, // dsub_2 -> DPairSpc_with_dsub_2_in_DPR_8 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 52, // ssub_0 -> DPairSpc_with_dsub_2_in_DPR_8 |
| 52, // ssub_1 -> DPairSpc_with_dsub_2_in_DPR_8 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 52, // ssub_4 -> DPairSpc_with_dsub_2_in_DPR_8 |
| 52, // ssub_5 -> DPairSpc_with_dsub_2_in_DPR_8 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DPair |
| 53, // dsub_0 -> DPair |
| 53, // dsub_1 -> DPair |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 54, // ssub_0 -> DPair_with_ssub_0 |
| 54, // ssub_1 -> DPair_with_ssub_0 |
| 56, // ssub_2 -> DPair_with_ssub_2 |
| 56, // ssub_3 -> DPair_with_ssub_2 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DPair_with_ssub_0 |
| 54, // dsub_0 -> DPair_with_ssub_0 |
| 54, // dsub_1 -> DPair_with_ssub_0 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 54, // ssub_0 -> DPair_with_ssub_0 |
| 54, // ssub_1 -> DPair_with_ssub_0 |
| 56, // ssub_2 -> DPair_with_ssub_2 |
| 56, // ssub_3 -> DPair_with_ssub_2 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // QPR |
| 55, // dsub_0 -> QPR |
| 55, // dsub_1 -> QPR |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 58, // ssub_0 -> MQPR |
| 58, // ssub_1 -> MQPR |
| 58, // ssub_2 -> MQPR |
| 58, // ssub_3 -> MQPR |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DPair_with_ssub_2 |
| 56, // dsub_0 -> DPair_with_ssub_2 |
| 56, // dsub_1 -> DPair_with_ssub_2 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 56, // ssub_0 -> DPair_with_ssub_2 |
| 56, // ssub_1 -> DPair_with_ssub_2 |
| 56, // ssub_2 -> DPair_with_ssub_2 |
| 56, // ssub_3 -> DPair_with_ssub_2 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DPair_with_dsub_0_in_DPR_8 |
| 57, // dsub_0 -> DPair_with_dsub_0_in_DPR_8 |
| 57, // dsub_1 -> DPair_with_dsub_0_in_DPR_8 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 57, // ssub_0 -> DPair_with_dsub_0_in_DPR_8 |
| 57, // ssub_1 -> DPair_with_dsub_0_in_DPR_8 |
| 57, // ssub_2 -> DPair_with_dsub_0_in_DPR_8 |
| 57, // ssub_3 -> DPair_with_dsub_0_in_DPR_8 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // MQPR |
| 58, // dsub_0 -> MQPR |
| 58, // dsub_1 -> MQPR |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 58, // ssub_0 -> MQPR |
| 58, // ssub_1 -> MQPR |
| 58, // ssub_2 -> MQPR |
| 58, // ssub_3 -> MQPR |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // QPR_VFP2 |
| 59, // dsub_0 -> QPR_VFP2 |
| 59, // dsub_1 -> QPR_VFP2 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 59, // ssub_0 -> QPR_VFP2 |
| 59, // ssub_1 -> QPR_VFP2 |
| 59, // ssub_2 -> QPR_VFP2 |
| 59, // ssub_3 -> QPR_VFP2 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DPair_with_dsub_1_in_DPR_8 |
| 60, // dsub_0 -> DPair_with_dsub_1_in_DPR_8 |
| 60, // dsub_1 -> DPair_with_dsub_1_in_DPR_8 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 60, // ssub_0 -> DPair_with_dsub_1_in_DPR_8 |
| 60, // ssub_1 -> DPair_with_dsub_1_in_DPR_8 |
| 60, // ssub_2 -> DPair_with_dsub_1_in_DPR_8 |
| 60, // ssub_3 -> DPair_with_dsub_1_in_DPR_8 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // QPR_8 |
| 61, // dsub_0 -> QPR_8 |
| 61, // dsub_1 -> QPR_8 |
| 0, // dsub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 61, // ssub_0 -> QPR_8 |
| 61, // ssub_1 -> QPR_8 |
| 61, // ssub_2 -> QPR_8 |
| 61, // ssub_3 -> QPR_8 |
| 0, // ssub_4 |
| 0, // ssub_5 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTriple |
| 62, // dsub_0 -> DTriple |
| 62, // dsub_1 -> DTriple |
| 62, // dsub_2 -> DTriple |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 62, // qsub_0 -> DTriple |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 65, // ssub_0 -> DTriple_with_ssub_0 |
| 65, // ssub_1 -> DTriple_with_ssub_0 |
| 67, // ssub_2 -> DTriple_with_ssub_2 |
| 67, // ssub_3 -> DTriple_with_ssub_2 |
| 70, // ssub_4 -> DTriple_with_ssub_4 |
| 70, // ssub_5 -> DTriple_with_ssub_4 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 62, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 62, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTripleSpc |
| 63, // dsub_0 -> DTripleSpc |
| 0, // dsub_1 |
| 63, // dsub_2 -> DTripleSpc |
| 0, // dsub_3 |
| 63, // dsub_4 -> DTripleSpc |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 64, // ssub_0 -> DTripleSpc_with_ssub_0 |
| 64, // ssub_1 -> DTripleSpc_with_ssub_0 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 69, // ssub_4 -> DTripleSpc_with_ssub_4 |
| 69, // ssub_5 -> DTripleSpc_with_ssub_4 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 71, // ssub_8 -> DTripleSpc_with_ssub_8 |
| 71, // ssub_9 -> DTripleSpc_with_ssub_8 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 63, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 63, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTripleSpc_with_ssub_0 |
| 64, // dsub_0 -> DTripleSpc_with_ssub_0 |
| 0, // dsub_1 |
| 64, // dsub_2 -> DTripleSpc_with_ssub_0 |
| 0, // dsub_3 |
| 64, // dsub_4 -> DTripleSpc_with_ssub_0 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 64, // ssub_0 -> DTripleSpc_with_ssub_0 |
| 64, // ssub_1 -> DTripleSpc_with_ssub_0 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 69, // ssub_4 -> DTripleSpc_with_ssub_4 |
| 69, // ssub_5 -> DTripleSpc_with_ssub_4 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 71, // ssub_8 -> DTripleSpc_with_ssub_8 |
| 71, // ssub_9 -> DTripleSpc_with_ssub_8 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 64, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_ssub_0 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 64, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_ssub_0 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTriple_with_ssub_0 |
| 65, // dsub_0 -> DTriple_with_ssub_0 |
| 65, // dsub_1 -> DTriple_with_ssub_0 |
| 65, // dsub_2 -> DTriple_with_ssub_0 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 65, // qsub_0 -> DTriple_with_ssub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 65, // ssub_0 -> DTriple_with_ssub_0 |
| 65, // ssub_1 -> DTriple_with_ssub_0 |
| 67, // ssub_2 -> DTriple_with_ssub_2 |
| 67, // ssub_3 -> DTriple_with_ssub_2 |
| 70, // ssub_4 -> DTriple_with_ssub_4 |
| 70, // ssub_5 -> DTriple_with_ssub_4 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 65, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_0 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 65, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_0 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTriple_with_qsub_0_in_QPR |
| 66, // dsub_0 -> DTriple_with_qsub_0_in_QPR |
| 66, // dsub_1 -> DTriple_with_qsub_0_in_QPR |
| 66, // dsub_2 -> DTriple_with_qsub_0_in_QPR |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 66, // qsub_0 -> DTriple_with_qsub_0_in_QPR |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 74, // ssub_0 -> DTriple_with_qsub_0_in_MQPR |
| 74, // ssub_1 -> DTriple_with_qsub_0_in_MQPR |
| 74, // ssub_2 -> DTriple_with_qsub_0_in_MQPR |
| 74, // ssub_3 -> DTriple_with_qsub_0_in_MQPR |
| 78, // ssub_4 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR |
| 78, // ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 66, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 66, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTriple_with_ssub_2 |
| 67, // dsub_0 -> DTriple_with_ssub_2 |
| 67, // dsub_1 -> DTriple_with_ssub_2 |
| 67, // dsub_2 -> DTriple_with_ssub_2 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 67, // qsub_0 -> DTriple_with_ssub_2 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 67, // ssub_0 -> DTriple_with_ssub_2 |
| 67, // ssub_1 -> DTriple_with_ssub_2 |
| 67, // ssub_2 -> DTriple_with_ssub_2 |
| 67, // ssub_3 -> DTriple_with_ssub_2 |
| 70, // ssub_4 -> DTriple_with_ssub_4 |
| 70, // ssub_5 -> DTriple_with_ssub_4 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 67, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 67, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 68, // dsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 68, // dsub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 68, // dsub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 68, // qsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 75, // ssub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 75, // ssub_1 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 77, // ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 77, // ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 77, // ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 77, // ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 68, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 68, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTripleSpc_with_ssub_4 |
| 69, // dsub_0 -> DTripleSpc_with_ssub_4 |
| 0, // dsub_1 |
| 69, // dsub_2 -> DTripleSpc_with_ssub_4 |
| 0, // dsub_3 |
| 69, // dsub_4 -> DTripleSpc_with_ssub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 69, // ssub_0 -> DTripleSpc_with_ssub_4 |
| 69, // ssub_1 -> DTripleSpc_with_ssub_4 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 69, // ssub_4 -> DTripleSpc_with_ssub_4 |
| 69, // ssub_5 -> DTripleSpc_with_ssub_4 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 71, // ssub_8 -> DTripleSpc_with_ssub_8 |
| 71, // ssub_9 -> DTripleSpc_with_ssub_8 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 69, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_ssub_4 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 69, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_ssub_4 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTriple_with_ssub_4 |
| 70, // dsub_0 -> DTriple_with_ssub_4 |
| 70, // dsub_1 -> DTriple_with_ssub_4 |
| 70, // dsub_2 -> DTriple_with_ssub_4 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 70, // qsub_0 -> DTriple_with_ssub_4 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 70, // ssub_0 -> DTriple_with_ssub_4 |
| 70, // ssub_1 -> DTriple_with_ssub_4 |
| 70, // ssub_2 -> DTriple_with_ssub_4 |
| 70, // ssub_3 -> DTriple_with_ssub_4 |
| 70, // ssub_4 -> DTriple_with_ssub_4 |
| 70, // ssub_5 -> DTriple_with_ssub_4 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 70, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_4 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 70, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_4 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTripleSpc_with_ssub_8 |
| 71, // dsub_0 -> DTripleSpc_with_ssub_8 |
| 0, // dsub_1 |
| 71, // dsub_2 -> DTripleSpc_with_ssub_8 |
| 0, // dsub_3 |
| 71, // dsub_4 -> DTripleSpc_with_ssub_8 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 71, // ssub_0 -> DTripleSpc_with_ssub_8 |
| 71, // ssub_1 -> DTripleSpc_with_ssub_8 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 71, // ssub_4 -> DTripleSpc_with_ssub_8 |
| 71, // ssub_5 -> DTripleSpc_with_ssub_8 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 71, // ssub_8 -> DTripleSpc_with_ssub_8 |
| 71, // ssub_9 -> DTripleSpc_with_ssub_8 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 71, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_ssub_8 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 71, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_ssub_8 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTripleSpc_with_dsub_0_in_DPR_8 |
| 72, // dsub_0 -> DTripleSpc_with_dsub_0_in_DPR_8 |
| 0, // dsub_1 |
| 72, // dsub_2 -> DTripleSpc_with_dsub_0_in_DPR_8 |
| 0, // dsub_3 |
| 72, // dsub_4 -> DTripleSpc_with_dsub_0_in_DPR_8 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 72, // ssub_0 -> DTripleSpc_with_dsub_0_in_DPR_8 |
| 72, // ssub_1 -> DTripleSpc_with_dsub_0_in_DPR_8 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 72, // ssub_4 -> DTripleSpc_with_dsub_0_in_DPR_8 |
| 72, // ssub_5 -> DTripleSpc_with_dsub_0_in_DPR_8 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 72, // ssub_8 -> DTripleSpc_with_dsub_0_in_DPR_8 |
| 72, // ssub_9 -> DTripleSpc_with_dsub_0_in_DPR_8 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 72, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_dsub_0_in_DPR_8 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 72, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_dsub_0_in_DPR_8 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTriple_with_dsub_0_in_DPR_8 |
| 73, // dsub_0 -> DTriple_with_dsub_0_in_DPR_8 |
| 73, // dsub_1 -> DTriple_with_dsub_0_in_DPR_8 |
| 73, // dsub_2 -> DTriple_with_dsub_0_in_DPR_8 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 73, // qsub_0 -> DTriple_with_dsub_0_in_DPR_8 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 73, // ssub_0 -> DTriple_with_dsub_0_in_DPR_8 |
| 73, // ssub_1 -> DTriple_with_dsub_0_in_DPR_8 |
| 73, // ssub_2 -> DTriple_with_dsub_0_in_DPR_8 |
| 73, // ssub_3 -> DTriple_with_dsub_0_in_DPR_8 |
| 73, // ssub_4 -> DTriple_with_dsub_0_in_DPR_8 |
| 73, // ssub_5 -> DTriple_with_dsub_0_in_DPR_8 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 73, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 73, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTriple_with_qsub_0_in_MQPR |
| 74, // dsub_0 -> DTriple_with_qsub_0_in_MQPR |
| 74, // dsub_1 -> DTriple_with_qsub_0_in_MQPR |
| 74, // dsub_2 -> DTriple_with_qsub_0_in_MQPR |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 74, // qsub_0 -> DTriple_with_qsub_0_in_MQPR |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 74, // ssub_0 -> DTriple_with_qsub_0_in_MQPR |
| 74, // ssub_1 -> DTriple_with_qsub_0_in_MQPR |
| 74, // ssub_2 -> DTriple_with_qsub_0_in_MQPR |
| 74, // ssub_3 -> DTriple_with_qsub_0_in_MQPR |
| 78, // ssub_4 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR |
| 78, // ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 74, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_MQPR |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 74, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_MQPR |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 75, // dsub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 75, // dsub_1 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 75, // dsub_2 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 75, // qsub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 75, // ssub_0 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 75, // ssub_1 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 77, // ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 77, // ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 77, // ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 77, // ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 75, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 75, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTriple_with_dsub_1_in_DPR_8 |
| 76, // dsub_0 -> DTriple_with_dsub_1_in_DPR_8 |
| 76, // dsub_1 -> DTriple_with_dsub_1_in_DPR_8 |
| 76, // dsub_2 -> DTriple_with_dsub_1_in_DPR_8 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 76, // qsub_0 -> DTriple_with_dsub_1_in_DPR_8 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 76, // ssub_0 -> DTriple_with_dsub_1_in_DPR_8 |
| 76, // ssub_1 -> DTriple_with_dsub_1_in_DPR_8 |
| 76, // ssub_2 -> DTriple_with_dsub_1_in_DPR_8 |
| 76, // ssub_3 -> DTriple_with_dsub_1_in_DPR_8 |
| 76, // ssub_4 -> DTriple_with_dsub_1_in_DPR_8 |
| 76, // ssub_5 -> DTriple_with_dsub_1_in_DPR_8 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 76, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_1_in_DPR_8 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 76, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_1_in_DPR_8 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 77, // dsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 77, // dsub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 77, // dsub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 77, // qsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 77, // ssub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 77, // ssub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 77, // ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 77, // ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 77, // ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 77, // ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 77, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 77, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR |
| 78, // dsub_0 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR |
| 78, // dsub_1 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR |
| 78, // dsub_2 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 78, // qsub_0 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 78, // ssub_0 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR |
| 78, // ssub_1 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR |
| 78, // ssub_2 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR |
| 78, // ssub_3 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR |
| 78, // ssub_4 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR |
| 78, // ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 78, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 78, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTripleSpc_with_dsub_2_in_DPR_8 |
| 79, // dsub_0 -> DTripleSpc_with_dsub_2_in_DPR_8 |
| 0, // dsub_1 |
| 79, // dsub_2 -> DTripleSpc_with_dsub_2_in_DPR_8 |
| 0, // dsub_3 |
| 79, // dsub_4 -> DTripleSpc_with_dsub_2_in_DPR_8 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 79, // ssub_0 -> DTripleSpc_with_dsub_2_in_DPR_8 |
| 79, // ssub_1 -> DTripleSpc_with_dsub_2_in_DPR_8 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 79, // ssub_4 -> DTripleSpc_with_dsub_2_in_DPR_8 |
| 79, // ssub_5 -> DTripleSpc_with_dsub_2_in_DPR_8 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 79, // ssub_8 -> DTripleSpc_with_dsub_2_in_DPR_8 |
| 79, // ssub_9 -> DTripleSpc_with_dsub_2_in_DPR_8 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 79, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_dsub_2_in_DPR_8 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 79, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_dsub_2_in_DPR_8 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTriple_with_dsub_2_in_DPR_8 |
| 80, // dsub_0 -> DTriple_with_dsub_2_in_DPR_8 |
| 80, // dsub_1 -> DTriple_with_dsub_2_in_DPR_8 |
| 80, // dsub_2 -> DTriple_with_dsub_2_in_DPR_8 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 80, // qsub_0 -> DTriple_with_dsub_2_in_DPR_8 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 80, // ssub_0 -> DTriple_with_dsub_2_in_DPR_8 |
| 80, // ssub_1 -> DTriple_with_dsub_2_in_DPR_8 |
| 80, // ssub_2 -> DTriple_with_dsub_2_in_DPR_8 |
| 80, // ssub_3 -> DTriple_with_dsub_2_in_DPR_8 |
| 80, // ssub_4 -> DTriple_with_dsub_2_in_DPR_8 |
| 80, // ssub_5 -> DTriple_with_dsub_2_in_DPR_8 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 80, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 80, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTripleSpc_with_dsub_4_in_DPR_8 |
| 81, // dsub_0 -> DTripleSpc_with_dsub_4_in_DPR_8 |
| 0, // dsub_1 |
| 81, // dsub_2 -> DTripleSpc_with_dsub_4_in_DPR_8 |
| 0, // dsub_3 |
| 81, // dsub_4 -> DTripleSpc_with_dsub_4_in_DPR_8 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 81, // ssub_0 -> DTripleSpc_with_dsub_4_in_DPR_8 |
| 81, // ssub_1 -> DTripleSpc_with_dsub_4_in_DPR_8 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 81, // ssub_4 -> DTripleSpc_with_dsub_4_in_DPR_8 |
| 81, // ssub_5 -> DTripleSpc_with_dsub_4_in_DPR_8 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 81, // ssub_8 -> DTripleSpc_with_dsub_4_in_DPR_8 |
| 81, // ssub_9 -> DTripleSpc_with_dsub_4_in_DPR_8 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 81, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTripleSpc_with_dsub_4_in_DPR_8 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 81, // ssub_4_ssub_5_ssub_8_ssub_9 -> DTripleSpc_with_dsub_4_in_DPR_8 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 82, // dsub_0 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 82, // dsub_1 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 82, // dsub_2 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 82, // qsub_0 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 82, // ssub_0 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 82, // ssub_1 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 82, // ssub_2 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 82, // ssub_3 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 82, // ssub_4 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 82, // ssub_5 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 82, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 82, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTriple_with_qsub_0_in_QPR_8 |
| 83, // dsub_0 -> DTriple_with_qsub_0_in_QPR_8 |
| 83, // dsub_1 -> DTriple_with_qsub_0_in_QPR_8 |
| 83, // dsub_2 -> DTriple_with_qsub_0_in_QPR_8 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 83, // qsub_0 -> DTriple_with_qsub_0_in_QPR_8 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 83, // ssub_0 -> DTriple_with_qsub_0_in_QPR_8 |
| 83, // ssub_1 -> DTriple_with_qsub_0_in_QPR_8 |
| 83, // ssub_2 -> DTriple_with_qsub_0_in_QPR_8 |
| 83, // ssub_3 -> DTriple_with_qsub_0_in_QPR_8 |
| 83, // ssub_4 -> DTriple_with_qsub_0_in_QPR_8 |
| 83, // ssub_5 -> DTriple_with_qsub_0_in_QPR_8 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 83, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR_8 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 83, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_qsub_0_in_QPR_8 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR |
| 84, // dsub_0 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR |
| 84, // dsub_1 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR |
| 84, // dsub_2 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 84, // qsub_0 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 84, // ssub_0 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR |
| 84, // ssub_1 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR |
| 84, // ssub_2 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR |
| 84, // ssub_3 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR |
| 84, // ssub_4 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR |
| 84, // ssub_5 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 84, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 84, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 85, // dsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 85, // dsub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 85, // dsub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 0, // dsub_3 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 85, // qsub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 85, // ssub_0 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 85, // ssub_1 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 85, // ssub_2 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 85, // ssub_3 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 85, // ssub_4 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 85, // ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 85, // ssub_0_ssub_1_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 85, // ssub_2_ssub_3_ssub_4_ssub_5 -> DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuadSpc |
| 86, // dsub_0 -> DQuadSpc |
| 0, // dsub_1 |
| 86, // dsub_2 -> DQuadSpc |
| 0, // dsub_3 |
| 86, // dsub_4 -> DQuadSpc |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 87, // ssub_0 -> DQuadSpc_with_ssub_0 |
| 87, // ssub_1 -> DQuadSpc_with_ssub_0 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 88, // ssub_4 -> DQuadSpc_with_ssub_4 |
| 88, // ssub_5 -> DQuadSpc_with_ssub_4 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 89, // ssub_8 -> DQuadSpc_with_ssub_8 |
| 89, // ssub_9 -> DQuadSpc_with_ssub_8 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 86, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 86, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuadSpc_with_ssub_0 |
| 87, // dsub_0 -> DQuadSpc_with_ssub_0 |
| 0, // dsub_1 |
| 87, // dsub_2 -> DQuadSpc_with_ssub_0 |
| 0, // dsub_3 |
| 87, // dsub_4 -> DQuadSpc_with_ssub_0 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 87, // ssub_0 -> DQuadSpc_with_ssub_0 |
| 87, // ssub_1 -> DQuadSpc_with_ssub_0 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 88, // ssub_4 -> DQuadSpc_with_ssub_4 |
| 88, // ssub_5 -> DQuadSpc_with_ssub_4 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 89, // ssub_8 -> DQuadSpc_with_ssub_8 |
| 89, // ssub_9 -> DQuadSpc_with_ssub_8 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 87, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_ssub_0 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 87, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_ssub_0 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuadSpc_with_ssub_4 |
| 88, // dsub_0 -> DQuadSpc_with_ssub_4 |
| 0, // dsub_1 |
| 88, // dsub_2 -> DQuadSpc_with_ssub_4 |
| 0, // dsub_3 |
| 88, // dsub_4 -> DQuadSpc_with_ssub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 88, // ssub_0 -> DQuadSpc_with_ssub_4 |
| 88, // ssub_1 -> DQuadSpc_with_ssub_4 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 88, // ssub_4 -> DQuadSpc_with_ssub_4 |
| 88, // ssub_5 -> DQuadSpc_with_ssub_4 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 89, // ssub_8 -> DQuadSpc_with_ssub_8 |
| 89, // ssub_9 -> DQuadSpc_with_ssub_8 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 88, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_ssub_4 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 88, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_ssub_4 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuadSpc_with_ssub_8 |
| 89, // dsub_0 -> DQuadSpc_with_ssub_8 |
| 0, // dsub_1 |
| 89, // dsub_2 -> DQuadSpc_with_ssub_8 |
| 0, // dsub_3 |
| 89, // dsub_4 -> DQuadSpc_with_ssub_8 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 89, // ssub_0 -> DQuadSpc_with_ssub_8 |
| 89, // ssub_1 -> DQuadSpc_with_ssub_8 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 89, // ssub_4 -> DQuadSpc_with_ssub_8 |
| 89, // ssub_5 -> DQuadSpc_with_ssub_8 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 89, // ssub_8 -> DQuadSpc_with_ssub_8 |
| 89, // ssub_9 -> DQuadSpc_with_ssub_8 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 89, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_ssub_8 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 89, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_ssub_8 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuadSpc_with_dsub_0_in_DPR_8 |
| 90, // dsub_0 -> DQuadSpc_with_dsub_0_in_DPR_8 |
| 0, // dsub_1 |
| 90, // dsub_2 -> DQuadSpc_with_dsub_0_in_DPR_8 |
| 0, // dsub_3 |
| 90, // dsub_4 -> DQuadSpc_with_dsub_0_in_DPR_8 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 90, // ssub_0 -> DQuadSpc_with_dsub_0_in_DPR_8 |
| 90, // ssub_1 -> DQuadSpc_with_dsub_0_in_DPR_8 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 90, // ssub_4 -> DQuadSpc_with_dsub_0_in_DPR_8 |
| 90, // ssub_5 -> DQuadSpc_with_dsub_0_in_DPR_8 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 90, // ssub_8 -> DQuadSpc_with_dsub_0_in_DPR_8 |
| 90, // ssub_9 -> DQuadSpc_with_dsub_0_in_DPR_8 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 90, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_dsub_0_in_DPR_8 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 90, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_dsub_0_in_DPR_8 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuadSpc_with_dsub_2_in_DPR_8 |
| 91, // dsub_0 -> DQuadSpc_with_dsub_2_in_DPR_8 |
| 0, // dsub_1 |
| 91, // dsub_2 -> DQuadSpc_with_dsub_2_in_DPR_8 |
| 0, // dsub_3 |
| 91, // dsub_4 -> DQuadSpc_with_dsub_2_in_DPR_8 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 91, // ssub_0 -> DQuadSpc_with_dsub_2_in_DPR_8 |
| 91, // ssub_1 -> DQuadSpc_with_dsub_2_in_DPR_8 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 91, // ssub_4 -> DQuadSpc_with_dsub_2_in_DPR_8 |
| 91, // ssub_5 -> DQuadSpc_with_dsub_2_in_DPR_8 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 91, // ssub_8 -> DQuadSpc_with_dsub_2_in_DPR_8 |
| 91, // ssub_9 -> DQuadSpc_with_dsub_2_in_DPR_8 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 91, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_dsub_2_in_DPR_8 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 91, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_dsub_2_in_DPR_8 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuadSpc_with_dsub_4_in_DPR_8 |
| 92, // dsub_0 -> DQuadSpc_with_dsub_4_in_DPR_8 |
| 0, // dsub_1 |
| 92, // dsub_2 -> DQuadSpc_with_dsub_4_in_DPR_8 |
| 0, // dsub_3 |
| 92, // dsub_4 -> DQuadSpc_with_dsub_4_in_DPR_8 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 0, // qsub_0 |
| 0, // qsub_1 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 92, // ssub_0 -> DQuadSpc_with_dsub_4_in_DPR_8 |
| 92, // ssub_1 -> DQuadSpc_with_dsub_4_in_DPR_8 |
| 0, // ssub_2 |
| 0, // ssub_3 |
| 92, // ssub_4 -> DQuadSpc_with_dsub_4_in_DPR_8 |
| 92, // ssub_5 -> DQuadSpc_with_dsub_4_in_DPR_8 |
| 0, // ssub_6 |
| 0, // ssub_7 |
| 92, // ssub_8 -> DQuadSpc_with_dsub_4_in_DPR_8 |
| 92, // ssub_9 -> DQuadSpc_with_dsub_4_in_DPR_8 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 92, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuadSpc_with_dsub_4_in_DPR_8 |
| 0, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 92, // ssub_4_ssub_5_ssub_8_ssub_9 -> DQuadSpc_with_dsub_4_in_DPR_8 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuad |
| 93, // dsub_0 -> DQuad |
| 93, // dsub_1 -> DQuad |
| 93, // dsub_2 -> DQuad |
| 93, // dsub_3 -> DQuad |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 93, // qsub_0 -> DQuad |
| 93, // qsub_1 -> DQuad |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 94, // ssub_0 -> DQuad_with_ssub_0 |
| 94, // ssub_1 -> DQuad_with_ssub_0 |
| 95, // ssub_2 -> DQuad_with_ssub_2 |
| 95, // ssub_3 -> DQuad_with_ssub_2 |
| 98, // ssub_4 -> DQuad_with_ssub_4 |
| 98, // ssub_5 -> DQuad_with_ssub_4 |
| 99, // ssub_6 -> DQuad_with_ssub_6 |
| 99, // ssub_7 -> DQuad_with_ssub_6 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 93, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad |
| 93, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad |
| 93, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad |
| 93, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad |
| 93, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuad_with_ssub_0 |
| 94, // dsub_0 -> DQuad_with_ssub_0 |
| 94, // dsub_1 -> DQuad_with_ssub_0 |
| 94, // dsub_2 -> DQuad_with_ssub_0 |
| 94, // dsub_3 -> DQuad_with_ssub_0 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 94, // qsub_0 -> DQuad_with_ssub_0 |
| 94, // qsub_1 -> DQuad_with_ssub_0 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 94, // ssub_0 -> DQuad_with_ssub_0 |
| 94, // ssub_1 -> DQuad_with_ssub_0 |
| 95, // ssub_2 -> DQuad_with_ssub_2 |
| 95, // ssub_3 -> DQuad_with_ssub_2 |
| 98, // ssub_4 -> DQuad_with_ssub_4 |
| 98, // ssub_5 -> DQuad_with_ssub_4 |
| 99, // ssub_6 -> DQuad_with_ssub_6 |
| 99, // ssub_7 -> DQuad_with_ssub_6 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 94, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_0 |
| 94, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_0 |
| 94, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_0 |
| 94, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_0 |
| 94, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_0 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuad_with_ssub_2 |
| 95, // dsub_0 -> DQuad_with_ssub_2 |
| 95, // dsub_1 -> DQuad_with_ssub_2 |
| 95, // dsub_2 -> DQuad_with_ssub_2 |
| 95, // dsub_3 -> DQuad_with_ssub_2 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 95, // qsub_0 -> DQuad_with_ssub_2 |
| 95, // qsub_1 -> DQuad_with_ssub_2 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 95, // ssub_0 -> DQuad_with_ssub_2 |
| 95, // ssub_1 -> DQuad_with_ssub_2 |
| 95, // ssub_2 -> DQuad_with_ssub_2 |
| 95, // ssub_3 -> DQuad_with_ssub_2 |
| 98, // ssub_4 -> DQuad_with_ssub_4 |
| 98, // ssub_5 -> DQuad_with_ssub_4 |
| 99, // ssub_6 -> DQuad_with_ssub_6 |
| 99, // ssub_7 -> DQuad_with_ssub_6 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 95, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_2 |
| 95, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2 |
| 95, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_2 |
| 95, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_2 |
| 95, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // QQPR |
| 96, // dsub_0 -> QQPR |
| 96, // dsub_1 -> QQPR |
| 96, // dsub_2 -> QQPR |
| 96, // dsub_3 -> QQPR |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 96, // qsub_0 -> QQPR |
| 96, // qsub_1 -> QQPR |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 101, // ssub_0 -> DQuad_with_qsub_0_in_MQPR |
| 101, // ssub_1 -> DQuad_with_qsub_0_in_MQPR |
| 101, // ssub_2 -> DQuad_with_qsub_0_in_MQPR |
| 101, // ssub_3 -> DQuad_with_qsub_0_in_MQPR |
| 104, // ssub_4 -> DQuad_with_qsub_1_in_MQPR |
| 104, // ssub_5 -> DQuad_with_qsub_1_in_MQPR |
| 104, // ssub_6 -> DQuad_with_qsub_1_in_MQPR |
| 104, // ssub_7 -> DQuad_with_qsub_1_in_MQPR |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 96, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQPR |
| 96, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQPR |
| 96, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQPR |
| 96, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQPR |
| 96, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQPR |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 97, // dsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 97, // dsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 97, // dsub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 97, // dsub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 97, // qsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 97, // qsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 102, // ssub_0 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 102, // ssub_1 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 105, // ssub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 105, // ssub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 105, // ssub_4 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 105, // ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // ssub_6 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 97, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 97, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 97, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 97, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 97, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuad_with_ssub_4 |
| 98, // dsub_0 -> DQuad_with_ssub_4 |
| 98, // dsub_1 -> DQuad_with_ssub_4 |
| 98, // dsub_2 -> DQuad_with_ssub_4 |
| 98, // dsub_3 -> DQuad_with_ssub_4 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 98, // qsub_0 -> DQuad_with_ssub_4 |
| 98, // qsub_1 -> DQuad_with_ssub_4 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 98, // ssub_0 -> DQuad_with_ssub_4 |
| 98, // ssub_1 -> DQuad_with_ssub_4 |
| 98, // ssub_2 -> DQuad_with_ssub_4 |
| 98, // ssub_3 -> DQuad_with_ssub_4 |
| 98, // ssub_4 -> DQuad_with_ssub_4 |
| 98, // ssub_5 -> DQuad_with_ssub_4 |
| 99, // ssub_6 -> DQuad_with_ssub_6 |
| 99, // ssub_7 -> DQuad_with_ssub_6 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 98, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_4 |
| 98, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_4 |
| 98, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_4 |
| 98, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_4 |
| 98, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_4 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuad_with_ssub_6 |
| 99, // dsub_0 -> DQuad_with_ssub_6 |
| 99, // dsub_1 -> DQuad_with_ssub_6 |
| 99, // dsub_2 -> DQuad_with_ssub_6 |
| 99, // dsub_3 -> DQuad_with_ssub_6 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 99, // qsub_0 -> DQuad_with_ssub_6 |
| 99, // qsub_1 -> DQuad_with_ssub_6 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 99, // ssub_0 -> DQuad_with_ssub_6 |
| 99, // ssub_1 -> DQuad_with_ssub_6 |
| 99, // ssub_2 -> DQuad_with_ssub_6 |
| 99, // ssub_3 -> DQuad_with_ssub_6 |
| 99, // ssub_4 -> DQuad_with_ssub_6 |
| 99, // ssub_5 -> DQuad_with_ssub_6 |
| 99, // ssub_6 -> DQuad_with_ssub_6 |
| 99, // ssub_7 -> DQuad_with_ssub_6 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 99, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_6 |
| 99, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_6 |
| 99, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_6 |
| 99, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_6 |
| 99, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_6 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuad_with_dsub_0_in_DPR_8 |
| 100, // dsub_0 -> DQuad_with_dsub_0_in_DPR_8 |
| 100, // dsub_1 -> DQuad_with_dsub_0_in_DPR_8 |
| 100, // dsub_2 -> DQuad_with_dsub_0_in_DPR_8 |
| 100, // dsub_3 -> DQuad_with_dsub_0_in_DPR_8 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 100, // qsub_0 -> DQuad_with_dsub_0_in_DPR_8 |
| 100, // qsub_1 -> DQuad_with_dsub_0_in_DPR_8 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 100, // ssub_0 -> DQuad_with_dsub_0_in_DPR_8 |
| 100, // ssub_1 -> DQuad_with_dsub_0_in_DPR_8 |
| 100, // ssub_2 -> DQuad_with_dsub_0_in_DPR_8 |
| 100, // ssub_3 -> DQuad_with_dsub_0_in_DPR_8 |
| 100, // ssub_4 -> DQuad_with_dsub_0_in_DPR_8 |
| 100, // ssub_5 -> DQuad_with_dsub_0_in_DPR_8 |
| 100, // ssub_6 -> DQuad_with_dsub_0_in_DPR_8 |
| 100, // ssub_7 -> DQuad_with_dsub_0_in_DPR_8 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 100, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8 |
| 100, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8 |
| 100, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_0_in_DPR_8 |
| 100, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_0_in_DPR_8 |
| 100, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuad_with_qsub_0_in_MQPR |
| 101, // dsub_0 -> DQuad_with_qsub_0_in_MQPR |
| 101, // dsub_1 -> DQuad_with_qsub_0_in_MQPR |
| 101, // dsub_2 -> DQuad_with_qsub_0_in_MQPR |
| 101, // dsub_3 -> DQuad_with_qsub_0_in_MQPR |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 101, // qsub_0 -> DQuad_with_qsub_0_in_MQPR |
| 101, // qsub_1 -> DQuad_with_qsub_0_in_MQPR |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 101, // ssub_0 -> DQuad_with_qsub_0_in_MQPR |
| 101, // ssub_1 -> DQuad_with_qsub_0_in_MQPR |
| 101, // ssub_2 -> DQuad_with_qsub_0_in_MQPR |
| 101, // ssub_3 -> DQuad_with_qsub_0_in_MQPR |
| 104, // ssub_4 -> DQuad_with_qsub_1_in_MQPR |
| 104, // ssub_5 -> DQuad_with_qsub_1_in_MQPR |
| 104, // ssub_6 -> DQuad_with_qsub_1_in_MQPR |
| 104, // ssub_7 -> DQuad_with_qsub_1_in_MQPR |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 101, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_MQPR |
| 101, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_MQPR |
| 101, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_qsub_0_in_MQPR |
| 101, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_qsub_0_in_MQPR |
| 101, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_MQPR |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 102, // dsub_0 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 102, // dsub_1 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 102, // dsub_2 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 102, // dsub_3 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 102, // qsub_0 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 102, // qsub_1 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 102, // ssub_0 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 102, // ssub_1 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 105, // ssub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 105, // ssub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 105, // ssub_4 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 105, // ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // ssub_6 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 102, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 102, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 102, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 102, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 102, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuad_with_dsub_1_in_DPR_8 |
| 103, // dsub_0 -> DQuad_with_dsub_1_in_DPR_8 |
| 103, // dsub_1 -> DQuad_with_dsub_1_in_DPR_8 |
| 103, // dsub_2 -> DQuad_with_dsub_1_in_DPR_8 |
| 103, // dsub_3 -> DQuad_with_dsub_1_in_DPR_8 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 103, // qsub_0 -> DQuad_with_dsub_1_in_DPR_8 |
| 103, // qsub_1 -> DQuad_with_dsub_1_in_DPR_8 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 103, // ssub_0 -> DQuad_with_dsub_1_in_DPR_8 |
| 103, // ssub_1 -> DQuad_with_dsub_1_in_DPR_8 |
| 103, // ssub_2 -> DQuad_with_dsub_1_in_DPR_8 |
| 103, // ssub_3 -> DQuad_with_dsub_1_in_DPR_8 |
| 103, // ssub_4 -> DQuad_with_dsub_1_in_DPR_8 |
| 103, // ssub_5 -> DQuad_with_dsub_1_in_DPR_8 |
| 103, // ssub_6 -> DQuad_with_dsub_1_in_DPR_8 |
| 103, // ssub_7 -> DQuad_with_dsub_1_in_DPR_8 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 103, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_1_in_DPR_8 |
| 103, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_1_in_DPR_8 |
| 103, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_1_in_DPR_8 |
| 103, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_1_in_DPR_8 |
| 103, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_1_in_DPR_8 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuad_with_qsub_1_in_MQPR |
| 104, // dsub_0 -> DQuad_with_qsub_1_in_MQPR |
| 104, // dsub_1 -> DQuad_with_qsub_1_in_MQPR |
| 104, // dsub_2 -> DQuad_with_qsub_1_in_MQPR |
| 104, // dsub_3 -> DQuad_with_qsub_1_in_MQPR |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 104, // qsub_0 -> DQuad_with_qsub_1_in_MQPR |
| 104, // qsub_1 -> DQuad_with_qsub_1_in_MQPR |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 104, // ssub_0 -> DQuad_with_qsub_1_in_MQPR |
| 104, // ssub_1 -> DQuad_with_qsub_1_in_MQPR |
| 104, // ssub_2 -> DQuad_with_qsub_1_in_MQPR |
| 104, // ssub_3 -> DQuad_with_qsub_1_in_MQPR |
| 104, // ssub_4 -> DQuad_with_qsub_1_in_MQPR |
| 104, // ssub_5 -> DQuad_with_qsub_1_in_MQPR |
| 104, // ssub_6 -> DQuad_with_qsub_1_in_MQPR |
| 104, // ssub_7 -> DQuad_with_qsub_1_in_MQPR |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 104, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_MQPR |
| 104, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_MQPR |
| 104, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_qsub_1_in_MQPR |
| 104, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_qsub_1_in_MQPR |
| 104, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_MQPR |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 105, // dsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 105, // dsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 105, // dsub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 105, // dsub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 105, // qsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 105, // qsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 105, // ssub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 105, // ssub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 105, // ssub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 105, // ssub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 105, // ssub_4 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 105, // ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // ssub_6 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 105, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 105, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 105, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 105, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 105, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuad_with_dsub_2_in_DPR_8 |
| 106, // dsub_0 -> DQuad_with_dsub_2_in_DPR_8 |
| 106, // dsub_1 -> DQuad_with_dsub_2_in_DPR_8 |
| 106, // dsub_2 -> DQuad_with_dsub_2_in_DPR_8 |
| 106, // dsub_3 -> DQuad_with_dsub_2_in_DPR_8 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 106, // qsub_0 -> DQuad_with_dsub_2_in_DPR_8 |
| 106, // qsub_1 -> DQuad_with_dsub_2_in_DPR_8 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 106, // ssub_0 -> DQuad_with_dsub_2_in_DPR_8 |
| 106, // ssub_1 -> DQuad_with_dsub_2_in_DPR_8 |
| 106, // ssub_2 -> DQuad_with_dsub_2_in_DPR_8 |
| 106, // ssub_3 -> DQuad_with_dsub_2_in_DPR_8 |
| 106, // ssub_4 -> DQuad_with_dsub_2_in_DPR_8 |
| 106, // ssub_5 -> DQuad_with_dsub_2_in_DPR_8 |
| 106, // ssub_6 -> DQuad_with_dsub_2_in_DPR_8 |
| 106, // ssub_7 -> DQuad_with_dsub_2_in_DPR_8 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 106, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_2_in_DPR_8 |
| 106, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_2_in_DPR_8 |
| 106, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_2_in_DPR_8 |
| 106, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_2_in_DPR_8 |
| 106, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_2_in_DPR_8 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // dsub_0 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // dsub_1 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // dsub_2 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // dsub_3 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 107, // qsub_0 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // qsub_1 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 107, // ssub_0 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // ssub_1 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // ssub_2 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // ssub_3 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // ssub_4 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // ssub_5 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // ssub_6 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 107, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 107, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuad_with_dsub_3_in_DPR_8 |
| 108, // dsub_0 -> DQuad_with_dsub_3_in_DPR_8 |
| 108, // dsub_1 -> DQuad_with_dsub_3_in_DPR_8 |
| 108, // dsub_2 -> DQuad_with_dsub_3_in_DPR_8 |
| 108, // dsub_3 -> DQuad_with_dsub_3_in_DPR_8 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 108, // qsub_0 -> DQuad_with_dsub_3_in_DPR_8 |
| 108, // qsub_1 -> DQuad_with_dsub_3_in_DPR_8 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 108, // ssub_0 -> DQuad_with_dsub_3_in_DPR_8 |
| 108, // ssub_1 -> DQuad_with_dsub_3_in_DPR_8 |
| 108, // ssub_2 -> DQuad_with_dsub_3_in_DPR_8 |
| 108, // ssub_3 -> DQuad_with_dsub_3_in_DPR_8 |
| 108, // ssub_4 -> DQuad_with_dsub_3_in_DPR_8 |
| 108, // ssub_5 -> DQuad_with_dsub_3_in_DPR_8 |
| 108, // ssub_6 -> DQuad_with_dsub_3_in_DPR_8 |
| 108, // ssub_7 -> DQuad_with_dsub_3_in_DPR_8 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 108, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8 |
| 108, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8 |
| 108, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_3_in_DPR_8 |
| 108, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_3_in_DPR_8 |
| 108, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 109, // dsub_0 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 109, // dsub_1 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 109, // dsub_2 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 109, // dsub_3 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 109, // qsub_0 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 109, // qsub_1 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 109, // ssub_0 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 109, // ssub_1 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 109, // ssub_2 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 109, // ssub_3 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 109, // ssub_4 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 109, // ssub_5 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 109, // ssub_6 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 109, // ssub_7 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 109, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 109, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 109, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 109, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 109, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuad_with_qsub_0_in_QPR_8 |
| 110, // dsub_0 -> DQuad_with_qsub_0_in_QPR_8 |
| 110, // dsub_1 -> DQuad_with_qsub_0_in_QPR_8 |
| 110, // dsub_2 -> DQuad_with_qsub_0_in_QPR_8 |
| 110, // dsub_3 -> DQuad_with_qsub_0_in_QPR_8 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 110, // qsub_0 -> DQuad_with_qsub_0_in_QPR_8 |
| 110, // qsub_1 -> DQuad_with_qsub_0_in_QPR_8 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 110, // ssub_0 -> DQuad_with_qsub_0_in_QPR_8 |
| 110, // ssub_1 -> DQuad_with_qsub_0_in_QPR_8 |
| 110, // ssub_2 -> DQuad_with_qsub_0_in_QPR_8 |
| 110, // ssub_3 -> DQuad_with_qsub_0_in_QPR_8 |
| 110, // ssub_4 -> DQuad_with_qsub_0_in_QPR_8 |
| 110, // ssub_5 -> DQuad_with_qsub_0_in_QPR_8 |
| 110, // ssub_6 -> DQuad_with_qsub_0_in_QPR_8 |
| 110, // ssub_7 -> DQuad_with_qsub_0_in_QPR_8 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 110, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_8 |
| 110, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_8 |
| 110, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_qsub_0_in_QPR_8 |
| 110, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_qsub_0_in_QPR_8 |
| 110, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_0_in_QPR_8 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuad_with_qsub_1_in_QPR_8 |
| 111, // dsub_0 -> DQuad_with_qsub_1_in_QPR_8 |
| 111, // dsub_1 -> DQuad_with_qsub_1_in_QPR_8 |
| 111, // dsub_2 -> DQuad_with_qsub_1_in_QPR_8 |
| 111, // dsub_3 -> DQuad_with_qsub_1_in_QPR_8 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 111, // qsub_0 -> DQuad_with_qsub_1_in_QPR_8 |
| 111, // qsub_1 -> DQuad_with_qsub_1_in_QPR_8 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 111, // ssub_0 -> DQuad_with_qsub_1_in_QPR_8 |
| 111, // ssub_1 -> DQuad_with_qsub_1_in_QPR_8 |
| 111, // ssub_2 -> DQuad_with_qsub_1_in_QPR_8 |
| 111, // ssub_3 -> DQuad_with_qsub_1_in_QPR_8 |
| 111, // ssub_4 -> DQuad_with_qsub_1_in_QPR_8 |
| 111, // ssub_5 -> DQuad_with_qsub_1_in_QPR_8 |
| 111, // ssub_6 -> DQuad_with_qsub_1_in_QPR_8 |
| 111, // ssub_7 -> DQuad_with_qsub_1_in_QPR_8 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 111, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_8 |
| 111, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_8 |
| 111, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_qsub_1_in_QPR_8 |
| 111, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_qsub_1_in_QPR_8 |
| 111, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_qsub_1_in_QPR_8 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 112, // dsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 112, // dsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 112, // dsub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 112, // dsub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 112, // qsub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 112, // qsub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 112, // ssub_0 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 112, // ssub_1 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 112, // ssub_2 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 112, // ssub_3 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 112, // ssub_4 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 112, // ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 112, // ssub_6 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 112, // ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 112, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 112, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 112, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 112, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 112, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 113, // dsub_0 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 113, // dsub_1 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 113, // dsub_2 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 113, // dsub_3 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // dsub_4 |
| 0, // dsub_5 |
| 0, // dsub_6 |
| 0, // dsub_7 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 0, // qqsub_0 |
| 0, // qqsub_1 |
| 113, // qsub_0 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 113, // qsub_1 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // qsub_2 |
| 0, // qsub_3 |
| 113, // ssub_0 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 113, // ssub_1 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 113, // ssub_2 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 113, // ssub_3 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 113, // ssub_4 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 113, // ssub_5 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 113, // ssub_6 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 113, // ssub_7 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // ssub_8 |
| 0, // ssub_9 |
| 0, // ssub_10 |
| 0, // ssub_11 |
| 0, // ssub_12 |
| 0, // ssub_13 |
| 0, // dsub_7_then_ssub_0 |
| 0, // dsub_7_then_ssub_1 |
| 113, // ssub_0_ssub_1_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 113, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 113, // ssub_2_ssub_3_ssub_6_ssub_7 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 113, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 113, // ssub_2_ssub_3_ssub_4_ssub_5 -> DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 |
| 0, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_6_ssub_7_dsub_5 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 |
| 0, // ssub_6_ssub_7_dsub_5_dsub_7 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9 |
| 0, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_ssub_12_ssub_13 |
| 0, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 |
| 0, // dsub_5_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13_dsub_7 |
| 0, // dsub_5_ssub_12_ssub_13 |
| 0, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 |
| }, |
| { // QQQQPR |
| 114, // dsub_0 -> QQQQPR |
| 114, // dsub_1 -> QQQQPR |
| 114, // dsub_2 -> QQQQPR |
| 114, // dsub_3 -> QQQQPR |
| 114, // dsub_4 -> QQQQPR |
| 114, // dsub_5 -> QQQQPR |
| 114, // dsub_6 -> QQQQPR |
| 114, // dsub_7 -> QQQQPR |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 114, // qqsub_0 -> QQQQPR |
| 114, // qqsub_1 -> QQQQPR |
| 114, // qsub_0 -> QQQQPR |
| 114, // qsub_1 -> QQQQPR |
| 114, // qsub_2 -> QQQQPR |
| 114, // qsub_3 -> QQQQPR |
| 115, // ssub_0 -> QQQQPR_with_ssub_0 |
| 115, // ssub_1 -> QQQQPR_with_ssub_0 |
| 115, // ssub_2 -> QQQQPR_with_ssub_0 |
| 115, // ssub_3 -> QQQQPR_with_ssub_0 |
| 116, // ssub_4 -> QQQQPR_with_ssub_4 |
| 116, // ssub_5 -> QQQQPR_with_ssub_4 |
| 116, // ssub_6 -> QQQQPR_with_ssub_4 |
| 116, // ssub_7 -> QQQQPR_with_ssub_4 |
| 117, // ssub_8 -> QQQQPR_with_ssub_8 |
| 117, // ssub_9 -> QQQQPR_with_ssub_8 |
| 117, // ssub_10 -> QQQQPR_with_ssub_8 |
| 117, // ssub_11 -> QQQQPR_with_ssub_8 |
| 118, // ssub_12 -> QQQQPR_with_ssub_12 |
| 118, // ssub_13 -> QQQQPR_with_ssub_12 |
| 118, // dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12 |
| 118, // dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12 |
| 114, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR |
| 114, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR |
| 114, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR |
| 114, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR |
| 114, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR |
| 114, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR |
| 114, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR |
| 114, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR |
| 114, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR |
| 114, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR |
| 114, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR |
| 114, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR |
| 114, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR |
| 114, // ssub_6_ssub_7_dsub_5 -> QQQQPR |
| 114, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR |
| 114, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR |
| 114, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR |
| 114, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR |
| 114, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR |
| 114, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR |
| 114, // dsub_5_dsub_7 -> QQQQPR |
| 114, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR |
| 114, // dsub_5_ssub_12_ssub_13 -> QQQQPR |
| 114, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR |
| }, |
| { // QQQQPR_with_ssub_0 |
| 115, // dsub_0 -> QQQQPR_with_ssub_0 |
| 115, // dsub_1 -> QQQQPR_with_ssub_0 |
| 115, // dsub_2 -> QQQQPR_with_ssub_0 |
| 115, // dsub_3 -> QQQQPR_with_ssub_0 |
| 115, // dsub_4 -> QQQQPR_with_ssub_0 |
| 115, // dsub_5 -> QQQQPR_with_ssub_0 |
| 115, // dsub_6 -> QQQQPR_with_ssub_0 |
| 115, // dsub_7 -> QQQQPR_with_ssub_0 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 115, // qqsub_0 -> QQQQPR_with_ssub_0 |
| 115, // qqsub_1 -> QQQQPR_with_ssub_0 |
| 115, // qsub_0 -> QQQQPR_with_ssub_0 |
| 115, // qsub_1 -> QQQQPR_with_ssub_0 |
| 115, // qsub_2 -> QQQQPR_with_ssub_0 |
| 115, // qsub_3 -> QQQQPR_with_ssub_0 |
| 115, // ssub_0 -> QQQQPR_with_ssub_0 |
| 115, // ssub_1 -> QQQQPR_with_ssub_0 |
| 115, // ssub_2 -> QQQQPR_with_ssub_0 |
| 115, // ssub_3 -> QQQQPR_with_ssub_0 |
| 116, // ssub_4 -> QQQQPR_with_ssub_4 |
| 116, // ssub_5 -> QQQQPR_with_ssub_4 |
| 116, // ssub_6 -> QQQQPR_with_ssub_4 |
| 116, // ssub_7 -> QQQQPR_with_ssub_4 |
| 117, // ssub_8 -> QQQQPR_with_ssub_8 |
| 117, // ssub_9 -> QQQQPR_with_ssub_8 |
| 117, // ssub_10 -> QQQQPR_with_ssub_8 |
| 117, // ssub_11 -> QQQQPR_with_ssub_8 |
| 118, // ssub_12 -> QQQQPR_with_ssub_12 |
| 118, // ssub_13 -> QQQQPR_with_ssub_12 |
| 118, // dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12 |
| 118, // dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12 |
| 115, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_ssub_0 |
| 115, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_0 |
| 115, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_ssub_0 |
| 115, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_ssub_0 |
| 115, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_0 |
| 115, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_0 |
| 115, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_0 |
| 115, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_0 |
| 115, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_0 |
| 115, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_0 |
| 115, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_0 |
| 115, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_0 |
| 115, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_0 |
| 115, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_0 |
| 115, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_ssub_0 |
| 115, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_0 |
| 115, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_0 |
| 115, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_0 |
| 115, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_0 |
| 115, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_0 |
| 115, // dsub_5_dsub_7 -> QQQQPR_with_ssub_0 |
| 115, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_ssub_0 |
| 115, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_0 |
| 115, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_ssub_0 |
| }, |
| { // QQQQPR_with_ssub_4 |
| 116, // dsub_0 -> QQQQPR_with_ssub_4 |
| 116, // dsub_1 -> QQQQPR_with_ssub_4 |
| 116, // dsub_2 -> QQQQPR_with_ssub_4 |
| 116, // dsub_3 -> QQQQPR_with_ssub_4 |
| 116, // dsub_4 -> QQQQPR_with_ssub_4 |
| 116, // dsub_5 -> QQQQPR_with_ssub_4 |
| 116, // dsub_6 -> QQQQPR_with_ssub_4 |
| 116, // dsub_7 -> QQQQPR_with_ssub_4 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 116, // qqsub_0 -> QQQQPR_with_ssub_4 |
| 116, // qqsub_1 -> QQQQPR_with_ssub_4 |
| 116, // qsub_0 -> QQQQPR_with_ssub_4 |
| 116, // qsub_1 -> QQQQPR_with_ssub_4 |
| 116, // qsub_2 -> QQQQPR_with_ssub_4 |
| 116, // qsub_3 -> QQQQPR_with_ssub_4 |
| 116, // ssub_0 -> QQQQPR_with_ssub_4 |
| 116, // ssub_1 -> QQQQPR_with_ssub_4 |
| 116, // ssub_2 -> QQQQPR_with_ssub_4 |
| 116, // ssub_3 -> QQQQPR_with_ssub_4 |
| 116, // ssub_4 -> QQQQPR_with_ssub_4 |
| 116, // ssub_5 -> QQQQPR_with_ssub_4 |
| 116, // ssub_6 -> QQQQPR_with_ssub_4 |
| 116, // ssub_7 -> QQQQPR_with_ssub_4 |
| 117, // ssub_8 -> QQQQPR_with_ssub_8 |
| 117, // ssub_9 -> QQQQPR_with_ssub_8 |
| 117, // ssub_10 -> QQQQPR_with_ssub_8 |
| 117, // ssub_11 -> QQQQPR_with_ssub_8 |
| 118, // ssub_12 -> QQQQPR_with_ssub_12 |
| 118, // ssub_13 -> QQQQPR_with_ssub_12 |
| 118, // dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12 |
| 118, // dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12 |
| 116, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_ssub_4 |
| 116, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_4 |
| 116, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_ssub_4 |
| 116, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_ssub_4 |
| 116, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_4 |
| 116, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_4 |
| 116, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_4 |
| 116, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_4 |
| 116, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_4 |
| 116, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_4 |
| 116, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_4 |
| 116, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_4 |
| 116, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_4 |
| 116, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_4 |
| 116, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_ssub_4 |
| 116, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_4 |
| 116, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_4 |
| 116, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_4 |
| 116, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_4 |
| 116, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_4 |
| 116, // dsub_5_dsub_7 -> QQQQPR_with_ssub_4 |
| 116, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_ssub_4 |
| 116, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_4 |
| 116, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_ssub_4 |
| }, |
| { // QQQQPR_with_ssub_8 |
| 117, // dsub_0 -> QQQQPR_with_ssub_8 |
| 117, // dsub_1 -> QQQQPR_with_ssub_8 |
| 117, // dsub_2 -> QQQQPR_with_ssub_8 |
| 117, // dsub_3 -> QQQQPR_with_ssub_8 |
| 117, // dsub_4 -> QQQQPR_with_ssub_8 |
| 117, // dsub_5 -> QQQQPR_with_ssub_8 |
| 117, // dsub_6 -> QQQQPR_with_ssub_8 |
| 117, // dsub_7 -> QQQQPR_with_ssub_8 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 117, // qqsub_0 -> QQQQPR_with_ssub_8 |
| 117, // qqsub_1 -> QQQQPR_with_ssub_8 |
| 117, // qsub_0 -> QQQQPR_with_ssub_8 |
| 117, // qsub_1 -> QQQQPR_with_ssub_8 |
| 117, // qsub_2 -> QQQQPR_with_ssub_8 |
| 117, // qsub_3 -> QQQQPR_with_ssub_8 |
| 117, // ssub_0 -> QQQQPR_with_ssub_8 |
| 117, // ssub_1 -> QQQQPR_with_ssub_8 |
| 117, // ssub_2 -> QQQQPR_with_ssub_8 |
| 117, // ssub_3 -> QQQQPR_with_ssub_8 |
| 117, // ssub_4 -> QQQQPR_with_ssub_8 |
| 117, // ssub_5 -> QQQQPR_with_ssub_8 |
| 117, // ssub_6 -> QQQQPR_with_ssub_8 |
| 117, // ssub_7 -> QQQQPR_with_ssub_8 |
| 117, // ssub_8 -> QQQQPR_with_ssub_8 |
| 117, // ssub_9 -> QQQQPR_with_ssub_8 |
| 117, // ssub_10 -> QQQQPR_with_ssub_8 |
| 117, // ssub_11 -> QQQQPR_with_ssub_8 |
| 118, // ssub_12 -> QQQQPR_with_ssub_12 |
| 118, // ssub_13 -> QQQQPR_with_ssub_12 |
| 118, // dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12 |
| 118, // dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12 |
| 117, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_ssub_8 |
| 117, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_8 |
| 117, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_ssub_8 |
| 117, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_ssub_8 |
| 117, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_8 |
| 117, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_8 |
| 117, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_8 |
| 117, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_8 |
| 117, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_8 |
| 117, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_8 |
| 117, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_8 |
| 117, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_8 |
| 117, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_8 |
| 117, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_8 |
| 117, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_ssub_8 |
| 117, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_8 |
| 117, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_8 |
| 117, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_8 |
| 117, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_8 |
| 117, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_8 |
| 117, // dsub_5_dsub_7 -> QQQQPR_with_ssub_8 |
| 117, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_ssub_8 |
| 117, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_8 |
| 117, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_ssub_8 |
| }, |
| { // QQQQPR_with_ssub_12 |
| 118, // dsub_0 -> QQQQPR_with_ssub_12 |
| 118, // dsub_1 -> QQQQPR_with_ssub_12 |
| 118, // dsub_2 -> QQQQPR_with_ssub_12 |
| 118, // dsub_3 -> QQQQPR_with_ssub_12 |
| 118, // dsub_4 -> QQQQPR_with_ssub_12 |
| 118, // dsub_5 -> QQQQPR_with_ssub_12 |
| 118, // dsub_6 -> QQQQPR_with_ssub_12 |
| 118, // dsub_7 -> QQQQPR_with_ssub_12 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 118, // qqsub_0 -> QQQQPR_with_ssub_12 |
| 118, // qqsub_1 -> QQQQPR_with_ssub_12 |
| 118, // qsub_0 -> QQQQPR_with_ssub_12 |
| 118, // qsub_1 -> QQQQPR_with_ssub_12 |
| 118, // qsub_2 -> QQQQPR_with_ssub_12 |
| 118, // qsub_3 -> QQQQPR_with_ssub_12 |
| 118, // ssub_0 -> QQQQPR_with_ssub_12 |
| 118, // ssub_1 -> QQQQPR_with_ssub_12 |
| 118, // ssub_2 -> QQQQPR_with_ssub_12 |
| 118, // ssub_3 -> QQQQPR_with_ssub_12 |
| 118, // ssub_4 -> QQQQPR_with_ssub_12 |
| 118, // ssub_5 -> QQQQPR_with_ssub_12 |
| 118, // ssub_6 -> QQQQPR_with_ssub_12 |
| 118, // ssub_7 -> QQQQPR_with_ssub_12 |
| 118, // ssub_8 -> QQQQPR_with_ssub_12 |
| 118, // ssub_9 -> QQQQPR_with_ssub_12 |
| 118, // ssub_10 -> QQQQPR_with_ssub_12 |
| 118, // ssub_11 -> QQQQPR_with_ssub_12 |
| 118, // ssub_12 -> QQQQPR_with_ssub_12 |
| 118, // ssub_13 -> QQQQPR_with_ssub_12 |
| 118, // dsub_7_then_ssub_0 -> QQQQPR_with_ssub_12 |
| 118, // dsub_7_then_ssub_1 -> QQQQPR_with_ssub_12 |
| 118, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_ssub_12 |
| 118, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_12 |
| 118, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_ssub_12 |
| 118, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_ssub_12 |
| 118, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_ssub_12 |
| 118, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_12 |
| 118, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_12 |
| 118, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_12 |
| 118, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_12 |
| 118, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_12 |
| 118, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_ssub_12 |
| 118, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_12 |
| 118, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_12 |
| 118, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_ssub_12 |
| 118, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_ssub_12 |
| 118, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_ssub_12 |
| 118, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_ssub_12 |
| 118, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_12 |
| 118, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_ssub_12 |
| 118, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_12 |
| 118, // dsub_5_dsub_7 -> QQQQPR_with_ssub_12 |
| 118, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_ssub_12 |
| 118, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_ssub_12 |
| 118, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_ssub_12 |
| }, |
| { // QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // dsub_0 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // dsub_1 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // dsub_2 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // dsub_3 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // dsub_4 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // dsub_5 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // dsub_6 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 119, // qqsub_0 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // qqsub_1 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // qsub_0 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // qsub_1 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // qsub_2 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // qsub_3 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_0 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_1 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_2 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_3 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_4 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_5 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_6 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_7 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_8 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_10 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_11 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_12 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // dsub_7_then_ssub_0 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // dsub_7_then_ssub_1 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // dsub_5_dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_0_in_DPR_8 |
| 119, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_dsub_0_in_DPR_8 |
| }, |
| { // QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // dsub_0 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // dsub_1 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // dsub_2 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // dsub_3 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // dsub_4 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // dsub_5 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // dsub_6 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 120, // qqsub_0 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // qqsub_1 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // qsub_0 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // qsub_1 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // qsub_2 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // qsub_3 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_0 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_1 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_2 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_3 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_4 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_5 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_6 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_7 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_8 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_10 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_11 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_12 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // dsub_7_then_ssub_0 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // dsub_7_then_ssub_1 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // dsub_5_dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_2_in_DPR_8 |
| 120, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_dsub_2_in_DPR_8 |
| }, |
| { // QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // dsub_0 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // dsub_1 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // dsub_2 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // dsub_3 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // dsub_4 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // dsub_5 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // dsub_6 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 121, // qqsub_0 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // qqsub_1 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // qsub_0 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // qsub_1 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // qsub_2 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // qsub_3 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_0 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_1 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_2 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_3 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_4 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_5 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_6 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_7 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_8 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_10 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_11 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_12 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // dsub_7_then_ssub_0 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // dsub_7_then_ssub_1 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // dsub_5_dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_4_in_DPR_8 |
| 121, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_dsub_4_in_DPR_8 |
| }, |
| { // QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // dsub_0 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // dsub_1 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // dsub_2 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // dsub_3 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // dsub_4 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // dsub_5 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // dsub_6 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 0, // gsub_0 |
| 0, // gsub_1 |
| 122, // qqsub_0 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // qqsub_1 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // qsub_0 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // qsub_1 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // qsub_2 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // qsub_3 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_0 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_1 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_2 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_3 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_4 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_5 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_6 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_7 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_8 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_10 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_11 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_12 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // dsub_7_then_ssub_0 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // dsub_7_then_ssub_1 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_0_ssub_1_ssub_4_ssub_5 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_2_ssub_3_ssub_6_ssub_7 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_2_ssub_3_ssub_4_ssub_5 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_4_ssub_5_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_6_ssub_7_dsub_5 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_6_ssub_7_dsub_5_dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_6_ssub_7_ssub_8_ssub_9 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_8_ssub_9_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_8_ssub_9_dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // dsub_5_dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // dsub_5_ssub_12_ssub_13_dsub_7 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // dsub_5_ssub_12_ssub_13 -> QQQQPR_with_dsub_6_in_DPR_8 |
| 122, // ssub_4_ssub_5_ssub_6_ssub_7_qsub_2 -> QQQQPR_with_dsub_6_in_DPR_8 |
| }, |
| }; |
| assert(RC && "Missing regclass"); |
| if (!Idx) return RC; |
| --Idx; |
| assert(Idx < 56 && "Bad subreg"); |
| unsigned TV = Table[RC->getID()][Idx]; |
| return TV ? getRegClass(TV - 1) : nullptr; |
| } |
| |
| /// Get the weight in units of pressure for this register class. |
| const RegClassWeight &ARMGenRegisterInfo:: |
| getRegClassWeight(const TargetRegisterClass *RC) const { |
| static const RegClassWeight RCWeightTable[] = { |
| {1, 32}, // HPR |
| {1, 65}, // FPWithVPR |
| {1, 32}, // SPR |
| {2, 32}, // FPWithVPR_with_ssub_0 |
| {1, 16}, // GPR |
| {1, 16}, // GPRwithAPSR |
| {1, 16}, // GPRwithZR |
| {1, 16}, // SPR_8 |
| {1, 15}, // GPRnopc |
| {0, 14}, // GPRwithAPSRnosp |
| {1, 15}, // GPRwithZRnosp |
| {1, 14}, // rGPR |
| {1, 9}, // tGPRwithpc |
| {2, 16}, // FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 |
| {1, 8}, // hGPR |
| {1, 8}, // tGPR |
| {1, 8}, // tGPREven |
| {1, 7}, // GPRnopc_and_hGPR |
| {1, 6}, // GPRwithAPSRnosp_and_hGPR |
| {1, 6}, // tGPROdd |
| {1, 5}, // tcGPR |
| {1, 4}, // hGPR_and_tGPREven |
| {1, 4}, // tGPR_and_tGPREven |
| {1, 4}, // tGPR_and_tGPROdd |
| {1, 4}, // tGPR_and_tcGPR |
| {1, 3}, // tGPREven_and_tcGPR |
| {1, 2}, // hGPR_and_tGPROdd |
| {1, 2}, // tGPREven_and_tGPR_and_tcGPR |
| {1, 2}, // tGPROdd_and_tcGPR |
| {0, 0}, // CCR |
| {1, 1}, // GPRlr |
| {1, 1}, // GPRsp |
| {1, 1}, // VCCR |
| {1, 1}, // cl_FPSCR_NZCV |
| {1, 1}, // hGPR_and_tGPRwithpc |
| {1, 1}, // hGPR_and_tcGPR |
| {2, 64}, // DPR |
| {2, 32}, // DPR_VFP2 |
| {2, 16}, // DPR_8 |
| {2, 14}, // GPRPair |
| {2, 12}, // GPRPairnosp |
| {2, 8}, // GPRPair_with_gsub_0_in_tGPR |
| {2, 6}, // GPRPair_with_gsub_0_in_hGPR |
| {2, 6}, // GPRPair_with_gsub_0_in_tcGPR |
| {2, 4}, // GPRPair_with_gsub_1_in_tcGPR |
| {2, 4}, // GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR |
| {2, 2}, // GPRPair_with_gsub_1_in_GPRsp |
| {4, 64}, // DPairSpc |
| {4, 36}, // DPairSpc_with_ssub_0 |
| {4, 32}, // DPairSpc_with_ssub_4 |
| {4, 20}, // DPairSpc_with_dsub_0_in_DPR_8 |
| {4, 16}, // DPairSpc_with_dsub_2_in_DPR_8 |
| {4, 64}, // DPair |
| {4, 34}, // DPair_with_ssub_0 |
| {4, 64}, // QPR |
| {4, 32}, // DPair_with_ssub_2 |
| {4, 18}, // DPair_with_dsub_0_in_DPR_8 |
| {4, 32}, // MQPR |
| {4, 32}, // QPR_VFP2 |
| {4, 16}, // DPair_with_dsub_1_in_DPR_8 |
| {4, 16}, // QPR_8 |
| {6, 64}, // DTriple |
| {6, 64}, // DTripleSpc |
| {6, 40}, // DTripleSpc_with_ssub_0 |
| {6, 36}, // DTriple_with_ssub_0 |
| {6, 62}, // DTriple_with_qsub_0_in_QPR |
| {6, 34}, // DTriple_with_ssub_2 |
| {6, 62}, // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| {6, 36}, // DTripleSpc_with_ssub_4 |
| {6, 32}, // DTriple_with_ssub_4 |
| {6, 32}, // DTripleSpc_with_ssub_8 |
| {6, 24}, // DTripleSpc_with_dsub_0_in_DPR_8 |
| {6, 20}, // DTriple_with_dsub_0_in_DPR_8 |
| {6, 34}, // DTriple_with_qsub_0_in_MQPR |
| {6, 34}, // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| {6, 18}, // DTriple_with_dsub_1_in_DPR_8 |
| {6, 30}, // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| {6, 30}, // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR |
| {6, 20}, // DTripleSpc_with_dsub_2_in_DPR_8 |
| {6, 16}, // DTriple_with_dsub_2_in_DPR_8 |
| {6, 16}, // DTripleSpc_with_dsub_4_in_DPR_8 |
| {6, 18}, // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| {6, 18}, // DTriple_with_qsub_0_in_QPR_8 |
| {6, 14}, // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR |
| {6, 14}, // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| {6, 64}, // DQuadSpc |
| {6, 40}, // DQuadSpc_with_ssub_0 |
| {6, 36}, // DQuadSpc_with_ssub_4 |
| {6, 32}, // DQuadSpc_with_ssub_8 |
| {6, 24}, // DQuadSpc_with_dsub_0_in_DPR_8 |
| {6, 20}, // DQuadSpc_with_dsub_2_in_DPR_8 |
| {6, 16}, // DQuadSpc_with_dsub_4_in_DPR_8 |
| {8, 64}, // DQuad |
| {8, 38}, // DQuad_with_ssub_0 |
| {8, 36}, // DQuad_with_ssub_2 |
| {8, 64}, // QQPR |
| {8, 60}, // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| {8, 34}, // DQuad_with_ssub_4 |
| {8, 32}, // DQuad_with_ssub_6 |
| {8, 22}, // DQuad_with_dsub_0_in_DPR_8 |
| {8, 36}, // DQuad_with_qsub_0_in_MQPR |
| {8, 36}, // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| {8, 20}, // DQuad_with_dsub_1_in_DPR_8 |
| {8, 32}, // DQuad_with_qsub_1_in_MQPR |
| {8, 32}, // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| {8, 18}, // DQuad_with_dsub_2_in_DPR_8 |
| {8, 28}, // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| {8, 16}, // DQuad_with_dsub_3_in_DPR_8 |
| {8, 20}, // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| {8, 20}, // DQuad_with_qsub_0_in_QPR_8 |
| {8, 16}, // DQuad_with_qsub_1_in_QPR_8 |
| {8, 16}, // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 |
| {8, 12}, // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| {16, 64}, // QQQQPR |
| {16, 44}, // QQQQPR_with_ssub_0 |
| {16, 40}, // QQQQPR_with_ssub_4 |
| {16, 36}, // QQQQPR_with_ssub_8 |
| {16, 32}, // QQQQPR_with_ssub_12 |
| {16, 28}, // QQQQPR_with_dsub_0_in_DPR_8 |
| {16, 24}, // QQQQPR_with_dsub_2_in_DPR_8 |
| {16, 20}, // QQQQPR_with_dsub_4_in_DPR_8 |
| {16, 16}, // QQQQPR_with_dsub_6_in_DPR_8 |
| }; |
| return RCWeightTable[RC->getID()]; |
| } |
| |
| /// Get the weight in units of pressure for this register unit. |
| unsigned ARMGenRegisterInfo:: |
| getRegUnitWeight(unsigned RegUnit) const { |
| assert(RegUnit < 83 && "invalid register unit"); |
| static const uint8_t RUWeightTable[] = { |
| 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; |
| return RUWeightTable[RegUnit]; |
| } |
| |
| |
| // Get the number of dimensions of register pressure. |
| unsigned ARMGenRegisterInfo::getNumRegPressureSets() const { |
| return 34; |
| } |
| |
| // Get the name of this register unit pressure set. |
| const char *ARMGenRegisterInfo:: |
| getRegPressureSetName(unsigned Idx) const { |
| static const char *const PressureNameTable[] = { |
| "GPRlr", |
| "VCCR", |
| "cl_FPSCR_NZCV", |
| "hGPR_and_tGPRwithpc", |
| "GPRsp", |
| "tGPR_and_tGPREven", |
| "tGPROdd", |
| "hGPR", |
| "tcGPR", |
| "tGPROdd+tcGPR", |
| "tGPR", |
| "tGPR+tcGPR", |
| "tGPREven", |
| "hGPR+tGPREven", |
| "hGPR+tGPROdd", |
| "hGPR+tcGPR", |
| "tGPR+tGPREven", |
| "GPR", |
| "GPRwithZR", |
| "GPRwithAPSR+GPRwithZR", |
| "DQuad_with_dsub_0_in_DPR_8", |
| "DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR", |
| "HPR", |
| "DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR", |
| "DPair_with_ssub_0", |
| "DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR", |
| "DPairSpc_with_ssub_0", |
| "DQuad_with_ssub_0", |
| "DTripleSpc_with_ssub_0", |
| "QQQQPR_with_ssub_0", |
| "DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR", |
| "DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR", |
| "DTriple_with_qsub_0_in_QPR", |
| "DPR", |
| }; |
| return PressureNameTable[Idx]; |
| } |
| |
| // Get the register unit pressure limit for this dimension. |
| // This limit must be adjusted dynamically for reserved registers. |
| unsigned ARMGenRegisterInfo:: |
| getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const { |
| static const uint8_t PressureLimitTable[] = { |
| 1, // 0: GPRlr |
| 1, // 1: VCCR |
| 1, // 2: cl_FPSCR_NZCV |
| 1, // 3: hGPR_and_tGPRwithpc |
| 2, // 4: GPRsp |
| 4, // 5: tGPR_and_tGPREven |
| 6, // 6: tGPROdd |
| 8, // 7: hGPR |
| 8, // 8: tcGPR |
| 10, // 9: tGPROdd+tcGPR |
| 11, // 10: tGPR |
| 11, // 11: tGPR+tcGPR |
| 11, // 12: tGPREven |
| 12, // 13: hGPR+tGPREven |
| 12, // 14: hGPR+tGPROdd |
| 12, // 15: hGPR+tcGPR |
| 13, // 16: tGPR+tGPREven |
| 17, // 17: GPR |
| 17, // 18: GPRwithZR |
| 17, // 19: GPRwithAPSR+GPRwithZR |
| 24, // 20: DQuad_with_dsub_0_in_DPR_8 |
| 32, // 21: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR |
| 32, // 22: HPR |
| 34, // 23: DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 34, // 24: DPair_with_ssub_0 |
| 36, // 25: DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 36, // 26: DPairSpc_with_ssub_0 |
| 38, // 27: DQuad_with_ssub_0 |
| 40, // 28: DTripleSpc_with_ssub_0 |
| 44, // 29: QQQQPR_with_ssub_0 |
| 60, // 30: DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 62, // 31: DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR |
| 62, // 32: DTriple_with_qsub_0_in_QPR |
| 64, // 33: DPR |
| }; |
| return PressureLimitTable[Idx]; |
| } |
| |
| /// Table of pressure sets per register class or unit. |
| static const int RCSetsTable[] = { |
| /* 0 */ 1, -1, |
| /* 2 */ 2, -1, |
| /* 4 */ 7, 13, 14, 15, 17, 18, -1, |
| /* 11 */ 10, 11, 16, 17, 18, -1, |
| /* 17 */ 3, 7, 10, 11, 13, 14, 15, 16, 17, 18, -1, |
| /* 28 */ 17, 19, -1, |
| /* 31 */ 6, 9, 10, 14, 17, 18, 19, -1, |
| /* 39 */ 8, 9, 11, 12, 15, 17, 18, 19, -1, |
| /* 48 */ 7, 13, 14, 15, 17, 18, 19, -1, |
| /* 56 */ 6, 7, 9, 10, 13, 14, 15, 17, 18, 19, -1, |
| /* 67 */ 4, 7, 8, 9, 11, 12, 13, 14, 15, 17, 18, 19, -1, |
| /* 80 */ 10, 11, 16, 17, 18, 19, -1, |
| /* 87 */ 5, 8, 10, 11, 12, 13, 16, 17, 18, 19, -1, |
| /* 98 */ 6, 9, 10, 11, 14, 16, 17, 18, 19, -1, |
| /* 108 */ 8, 9, 11, 12, 15, 16, 17, 18, 19, -1, |
| /* 118 */ 8, 9, 10, 11, 12, 15, 16, 17, 18, 19, -1, |
| /* 129 */ 8, 9, 11, 12, 13, 15, 16, 17, 18, 19, -1, |
| /* 140 */ 5, 8, 9, 10, 11, 12, 13, 15, 16, 17, 18, 19, -1, |
| /* 153 */ 6, 8, 9, 10, 11, 12, 14, 15, 16, 17, 18, 19, -1, |
| /* 166 */ 0, 7, 12, 13, 14, 15, 16, 17, 18, 19, -1, |
| /* 177 */ 4, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19, -1, |
| /* 191 */ 31, 33, -1, |
| /* 194 */ 20, 22, 24, 26, 27, 28, 29, 32, 33, -1, |
| /* 204 */ 25, 27, 28, 29, 30, 31, 32, 33, -1, |
| /* 213 */ 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, -1, |
| /* 224 */ 21, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, -1, |
| /* 237 */ 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, -1, |
| }; |
| |
| /// Get the dimensions of register pressure impacted by this register class. |
| /// Returns a -1 terminated array of pressure set IDs |
| const int* ARMGenRegisterInfo:: |
| getRegClassPressureSets(const TargetRegisterClass *RC) const { |
| static const uint8_t RCSetStartTable[] = { |
| 195,1,195,1,8,28,36,194,35,1,36,35,11,1,4,80,91,48,48,31,108,167,87,98,118,129,56,140,153,1,166,67,0,2,17,177,192,195,194,35,35,80,48,39,118,48,67,192,197,195,194,194,192,196,192,195,194,195,195,194,194,192,192,199,197,201,196,191,197,195,195,194,194,196,213,194,238,195,194,194,194,237,194,194,237,192,199,197,195,194,194,194,192,198,197,192,208,196,195,194,197,204,194,195,224,194,238,194,237,194,194,237,237,192,200,199,197,195,195,194,194,194,}; |
| return &RCSetsTable[RCSetStartTable[RC->getID()]]; |
| } |
| |
| /// Get the dimensions of register pressure impacted by this register unit. |
| /// Returns a -1 terminated array of pressure set IDs |
| const int* ARMGenRegisterInfo:: |
| getRegUnitPressureSets(unsigned RegUnit) const { |
| assert(RegUnit < 83 && "invalid register unit"); |
| static const uint8_t RUSetStartTable[] = { |
| 1,28,1,1,1,1,1,2,1,1,1,166,17,67,1,0,36,194,194,237,237,237,237,237,237,237,237,237,237,237,237,237,237,237,237,237,237,237,237,237,237,238,238,238,238,238,238,238,238,224,213,204,206,207,207,208,208,208,208,208,208,208,208,208,191,1,1,1,1,1,140,153,140,153,87,98,87,98,167,56,167,56,177,}; |
| return &RCSetsTable[RUSetStartTable[RegUnit]]; |
| } |
| |
| extern const MCRegisterDesc ARMRegDesc[]; |
| extern const MCPhysReg ARMRegDiffLists[]; |
| extern const LaneBitmask ARMLaneMaskLists[]; |
| extern const char ARMRegStrings[]; |
| extern const char ARMRegClassStrings[]; |
| extern const MCPhysReg ARMRegUnitRoots[][2]; |
| extern const uint16_t ARMSubRegIdxLists[]; |
| extern const MCRegisterInfo::SubRegCoveredBits ARMSubRegIdxRanges[]; |
| extern const uint16_t ARMRegEncodingTable[]; |
| // ARM Dwarf<->LLVM register mappings. |
| extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0Dwarf2L[]; |
| extern const unsigned ARMDwarfFlavour0Dwarf2LSize; |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0Dwarf2L[]; |
| extern const unsigned ARMEHFlavour0Dwarf2LSize; |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair ARMDwarfFlavour0L2Dwarf[]; |
| extern const unsigned ARMDwarfFlavour0L2DwarfSize; |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair ARMEHFlavour0L2Dwarf[]; |
| extern const unsigned ARMEHFlavour0L2DwarfSize; |
| |
| ARMGenRegisterInfo:: |
| ARMGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, |
| unsigned PC, unsigned HwMode) |
| : TargetRegisterInfo(ARMRegInfoDesc, RegisterClasses, RegisterClasses+122, |
| SubRegIndexNameTable, SubRegIndexLaneMaskTable, |
| LaneBitmask(0xFFFFFFFF), RegClassInfos, HwMode) { |
| InitMCRegisterInfo(ARMRegDesc, 295, RA, PC, |
| ARMMCRegisterClasses, 122, |
| ARMRegUnitRoots, |
| 83, |
| ARMRegDiffLists, |
| ARMLaneMaskLists, |
| ARMRegStrings, |
| ARMRegClassStrings, |
| ARMSubRegIdxLists, |
| 57, |
| ARMSubRegIdxRanges, |
| ARMRegEncodingTable); |
| |
| switch (DwarfFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| mapDwarfRegsToLLVMRegs(ARMDwarfFlavour0Dwarf2L, ARMDwarfFlavour0Dwarf2LSize, false); |
| break; |
| } |
| switch (EHFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| mapDwarfRegsToLLVMRegs(ARMEHFlavour0Dwarf2L, ARMEHFlavour0Dwarf2LSize, true); |
| break; |
| } |
| switch (DwarfFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| mapLLVMRegsToDwarfRegs(ARMDwarfFlavour0L2Dwarf, ARMDwarfFlavour0L2DwarfSize, false); |
| break; |
| } |
| switch (EHFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| mapLLVMRegsToDwarfRegs(ARMEHFlavour0L2Dwarf, ARMEHFlavour0L2DwarfSize, true); |
| break; |
| } |
| } |
| |
| static const MCPhysReg CSR_AAPCS_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 }; |
| static const uint32_t CSR_AAPCS_RegMask[] = { 0xf8002000, 0xf0000007, 0x000ff000, 0xe01fffe0, 0x03800007, 0xc01e0040, 0xf000000f, 0x03000000, 0x6001c000, 0x00000000, }; |
| static const MCPhysReg CSR_AAPCS_SplitPush_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 }; |
| static const uint32_t CSR_AAPCS_SplitPush_RegMask[] = { 0xf8002000, 0xf0000007, 0x000ff000, 0xe01fffe0, 0x03800007, 0xc01e0040, 0xf000000f, 0x03000000, 0x6001c000, 0x00000000, }; |
| static const MCPhysReg CSR_AAPCS_SplitPush_SwiftError_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R9, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 }; |
| static const uint32_t CSR_AAPCS_SplitPush_SwiftError_RegMask[] = { 0xf8002000, 0xf0000007, 0x000ef000, 0xe01fffe0, 0x03800007, 0xc0160040, 0xf000000f, 0x03000000, 0x6001c000, 0x00000000, }; |
| static const MCPhysReg CSR_AAPCS_SwiftError_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 }; |
| static const uint32_t CSR_AAPCS_SwiftError_RegMask[] = { 0xf8002000, 0xf0000007, 0x000ef000, 0xe01fffe0, 0x03800007, 0xc0160040, 0xf000000f, 0x03000000, 0x6001c000, 0x00000000, }; |
| static const MCPhysReg CSR_AAPCS_ThisReturn_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R0, 0 }; |
| static const uint32_t CSR_AAPCS_ThisReturn_RegMask[] = { 0xf8002000, 0xf0000007, 0x000ff100, 0xe01fffe0, 0x03800007, 0xc01e0040, 0xf000000f, 0x03000000, 0x6001c000, 0x00000000, }; |
| static const MCPhysReg CSR_FIQ_SaveList[] = { ARM::LR, ARM::R11, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::R0, 0 }; |
| static const uint32_t CSR_FIQ_RegMask[] = { 0x00002000, 0x00000000, 0x0008ff00, 0x00000000, 0x00000000, 0x00078000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; |
| static const MCPhysReg CSR_FPRegs_SaveList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10, ARM::D11, ARM::D12, ARM::D13, ARM::D14, ARM::D15, ARM::D16, ARM::D17, ARM::D18, ARM::D19, ARM::D20, ARM::D21, ARM::D22, ARM::D23, ARM::D24, ARM::D25, ARM::D26, ARM::D27, ARM::D28, ARM::D29, ARM::D30, ARM::D31, 0 }; |
| static const uint32_t CSR_FPRegs_RegMask[] = { 0xfff80000, 0xff07ffff, 0xffe000ff, 0xffffffff, 0xffffffff, 0xffc07fff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0000007f, }; |
| static const MCPhysReg CSR_GenericInt_SaveList[] = { ARM::LR, ARM::R12, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::R0, 0 }; |
| static const uint32_t CSR_GenericInt_RegMask[] = { 0x00002000, 0x00000000, 0x001fff00, 0x00000000, 0x00000000, 0x001f8000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; |
| static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 }; |
| static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; |
| static const MCPhysReg CSR_Win_AAPCS_CFGuard_Check_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 }; |
| static const uint32_t CSR_Win_AAPCS_CFGuard_Check_RegMask[] = { 0xfff82000, 0xff000007, 0xffeff000, 0xffffffff, 0x03f80007, 0xffde007c, 0xfff0000f, 0x03ff0000, 0x7e01fc00, 0x00000000, }; |
| static const MCPhysReg CSR_iOS_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 }; |
| static const uint32_t CSR_iOS_RegMask[] = { 0xf8002000, 0xf0000007, 0x000df000, 0xe01fffe0, 0x03800007, 0xc0160040, 0xf000000f, 0x03000000, 0x6001c000, 0x00000000, }; |
| static const MCPhysReg CSR_iOS_CXX_TLS_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R12, ARM::R9, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 }; |
| static const uint32_t CSR_iOS_CXX_TLS_RegMask[] = { 0xfff82000, 0xff07ffff, 0xfffffeff, 0xffffffff, 0xffffffff, 0xffdf7fff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0000007f, }; |
| static const MCPhysReg CSR_iOS_CXX_TLS_PE_SaveList[] = { ARM::LR, ARM::R12, ARM::R11, ARM::R7, ARM::R5, ARM::R4, 0 }; |
| static const uint32_t CSR_iOS_CXX_TLS_PE_RegMask[] = { 0x00002000, 0x00000000, 0x0018b000, 0x00000000, 0x00000000, 0x00020000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; |
| static const MCPhysReg CSR_iOS_CXX_TLS_ViaCopy_SaveList[] = { ARM::R6, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R9, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 }; |
| static const uint32_t CSR_iOS_CXX_TLS_ViaCopy_RegMask[] = { 0xfff80000, 0xff07ffff, 0xffe74eff, 0xffffffff, 0xffffffff, 0xffc97fff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0000007f, }; |
| static const MCPhysReg CSR_iOS_SwiftError_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, 0 }; |
| static const uint32_t CSR_iOS_SwiftError_RegMask[] = { 0xf8002000, 0xf0000007, 0x000cf000, 0xe01fffe0, 0x03800007, 0xc0160040, 0xf000000f, 0x03000000, 0x6001c000, 0x00000000, }; |
| static const MCPhysReg CSR_iOS_TLSCall_SaveList[] = { ARM::LR, ARM::SP, ARM::R11, ARM::R10, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::D31, ARM::D30, ARM::D29, ARM::D28, ARM::D27, ARM::D26, ARM::D25, ARM::D24, ARM::D23, ARM::D22, ARM::D21, ARM::D20, ARM::D19, ARM::D18, ARM::D17, ARM::D16, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::D7, ARM::D6, ARM::D5, ARM::D4, ARM::D3, ARM::D2, ARM::D1, ARM::D0, 0 }; |
| static const uint32_t CSR_iOS_TLSCall_RegMask[] = { 0xfff8a000, 0xff07ffff, 0xffedfeff, 0xffffffff, 0xffffffff, 0xffd77fff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0000007f, }; |
| static const MCPhysReg CSR_iOS_ThisReturn_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R0, 0 }; |
| static const uint32_t CSR_iOS_ThisReturn_RegMask[] = { 0xf8002000, 0xf0000007, 0x000df100, 0xe01fffe0, 0x03800007, 0xc0160040, 0xf000000f, 0x03000000, 0x6001c000, 0x00000000, }; |
| |
| |
| ArrayRef<const uint32_t *> ARMGenRegisterInfo::getRegMasks() const { |
| static const uint32_t *const Masks[] = { |
| CSR_AAPCS_RegMask, |
| CSR_AAPCS_SplitPush_RegMask, |
| CSR_AAPCS_SplitPush_SwiftError_RegMask, |
| CSR_AAPCS_SwiftError_RegMask, |
| CSR_AAPCS_ThisReturn_RegMask, |
| CSR_FIQ_RegMask, |
| CSR_FPRegs_RegMask, |
| CSR_GenericInt_RegMask, |
| CSR_NoRegs_RegMask, |
| CSR_Win_AAPCS_CFGuard_Check_RegMask, |
| CSR_iOS_RegMask, |
| CSR_iOS_CXX_TLS_RegMask, |
| CSR_iOS_CXX_TLS_PE_RegMask, |
| CSR_iOS_CXX_TLS_ViaCopy_RegMask, |
| CSR_iOS_SwiftError_RegMask, |
| CSR_iOS_TLSCall_RegMask, |
| CSR_iOS_ThisReturn_RegMask, |
| }; |
| return makeArrayRef(Masks); |
| } |
| |
| ArrayRef<const char *> ARMGenRegisterInfo::getRegMaskNames() const { |
| static const char *const Names[] = { |
| "CSR_AAPCS", |
| "CSR_AAPCS_SplitPush", |
| "CSR_AAPCS_SplitPush_SwiftError", |
| "CSR_AAPCS_SwiftError", |
| "CSR_AAPCS_ThisReturn", |
| "CSR_FIQ", |
| "CSR_FPRegs", |
| "CSR_GenericInt", |
| "CSR_NoRegs", |
| "CSR_Win_AAPCS_CFGuard_Check", |
| "CSR_iOS", |
| "CSR_iOS_CXX_TLS", |
| "CSR_iOS_CXX_TLS_PE", |
| "CSR_iOS_CXX_TLS_ViaCopy", |
| "CSR_iOS_SwiftError", |
| "CSR_iOS_TLSCall", |
| "CSR_iOS_ThisReturn", |
| }; |
| return makeArrayRef(Names); |
| } |
| |
| const ARMFrameLowering * |
| ARMGenRegisterInfo::getFrameLowering(const MachineFunction &MF) { |
| return static_cast<const ARMFrameLowering *>( |
| MF.getSubtarget().getFrameLowering()); |
| } |
| |
| } // end namespace llvm |
| |
| #endif // GET_REGINFO_TARGET_DESC |
| |