| //===- TableGen'erated file -------------------------------------*- C++ -*-===// | |
| // | |
| // Target Instruction Enum Values | |
| // | |
| // Automatically generated file, do not edit! | |
| // | |
| //===----------------------------------------------------------------------===// | |
| #ifdef GET_INSTRINFO_ENUM | |
| #undef GET_INSTRINFO_ENUM | |
| namespace llvm { | |
| namespace X86 { | |
| enum { | |
| PHI = 0, | |
| INLINEASM = 1, | |
| PROLOG_LABEL = 2, | |
| EH_LABEL = 3, | |
| GC_LABEL = 4, | |
| KILL = 5, | |
| EXTRACT_SUBREG = 6, | |
| INSERT_SUBREG = 7, | |
| IMPLICIT_DEF = 8, | |
| SUBREG_TO_REG = 9, | |
| COPY_TO_REGCLASS = 10, | |
| DBG_VALUE = 11, | |
| REG_SEQUENCE = 12, | |
| COPY = 13, | |
| AAA = 14, | |
| AAD8i8 = 15, | |
| AAM8i8 = 16, | |
| AAS = 17, | |
| ABS_F = 18, | |
| ABS_Fp32 = 19, | |
| ABS_Fp64 = 20, | |
| ABS_Fp80 = 21, | |
| ACQUIRE_MOV16rm = 22, | |
| ACQUIRE_MOV32rm = 23, | |
| ACQUIRE_MOV64rm = 24, | |
| ACQUIRE_MOV8rm = 25, | |
| ADC16i16 = 26, | |
| ADC16mi = 27, | |
| ADC16mi8 = 28, | |
| ADC16mr = 29, | |
| ADC16ri = 30, | |
| ADC16ri8 = 31, | |
| ADC16rm = 32, | |
| ADC16rr = 33, | |
| ADC16rr_REV = 34, | |
| ADC32i32 = 35, | |
| ADC32mi = 36, | |
| ADC32mi8 = 37, | |
| ADC32mr = 38, | |
| ADC32ri = 39, | |
| ADC32ri8 = 40, | |
| ADC32rm = 41, | |
| ADC32rr = 42, | |
| ADC32rr_REV = 43, | |
| ADC64i32 = 44, | |
| ADC64mi32 = 45, | |
| ADC64mi8 = 46, | |
| ADC64mr = 47, | |
| ADC64ri32 = 48, | |
| ADC64ri8 = 49, | |
| ADC64rm = 50, | |
| ADC64rr = 51, | |
| ADC64rr_REV = 52, | |
| ADC8i8 = 53, | |
| ADC8mi = 54, | |
| ADC8mr = 55, | |
| ADC8ri = 56, | |
| ADC8rm = 57, | |
| ADC8rr = 58, | |
| ADC8rr_REV = 59, | |
| ADD16i16 = 60, | |
| ADD16mi = 61, | |
| ADD16mi8 = 62, | |
| ADD16mr = 63, | |
| ADD16ri = 64, | |
| ADD16ri8 = 65, | |
| ADD16ri8_DB = 66, | |
| ADD16ri_DB = 67, | |
| ADD16rm = 68, | |
| ADD16rr = 69, | |
| ADD16rr_DB = 70, | |
| ADD16rr_REV = 71, | |
| ADD32i32 = 72, | |
| ADD32mi = 73, | |
| ADD32mi8 = 74, | |
| ADD32mr = 75, | |
| ADD32ri = 76, | |
| ADD32ri8 = 77, | |
| ADD32ri8_DB = 78, | |
| ADD32ri_DB = 79, | |
| ADD32rm = 80, | |
| ADD32rr = 81, | |
| ADD32rr_DB = 82, | |
| ADD32rr_REV = 83, | |
| ADD64i32 = 84, | |
| ADD64mi32 = 85, | |
| ADD64mi8 = 86, | |
| ADD64mr = 87, | |
| ADD64ri32 = 88, | |
| ADD64ri32_DB = 89, | |
| ADD64ri8 = 90, | |
| ADD64ri8_DB = 91, | |
| ADD64rm = 92, | |
| ADD64rr = 93, | |
| ADD64rr_DB = 94, | |
| ADD64rr_REV = 95, | |
| ADD8i8 = 96, | |
| ADD8mi = 97, | |
| ADD8mr = 98, | |
| ADD8ri = 99, | |
| ADD8rm = 100, | |
| ADD8rr = 101, | |
| ADD8rr_REV = 102, | |
| ADDPDrm = 103, | |
| ADDPDrr = 104, | |
| ADDPSrm = 105, | |
| ADDPSrr = 106, | |
| ADDSDrm = 107, | |
| ADDSDrm_Int = 108, | |
| ADDSDrr = 109, | |
| ADDSDrr_Int = 110, | |
| ADDSSrm = 111, | |
| ADDSSrm_Int = 112, | |
| ADDSSrr = 113, | |
| ADDSSrr_Int = 114, | |
| ADDSUBPDrm = 115, | |
| ADDSUBPDrr = 116, | |
| ADDSUBPSrm = 117, | |
| ADDSUBPSrr = 118, | |
| ADD_F32m = 119, | |
| ADD_F64m = 120, | |
| ADD_FI16m = 121, | |
| ADD_FI32m = 122, | |
| ADD_FPrST0 = 123, | |
| ADD_FST0r = 124, | |
| ADD_Fp32 = 125, | |
| ADD_Fp32m = 126, | |
| ADD_Fp64 = 127, | |
| ADD_Fp64m = 128, | |
| ADD_Fp64m32 = 129, | |
| ADD_Fp80 = 130, | |
| ADD_Fp80m32 = 131, | |
| ADD_Fp80m64 = 132, | |
| ADD_FpI16m32 = 133, | |
| ADD_FpI16m64 = 134, | |
| ADD_FpI16m80 = 135, | |
| ADD_FpI32m32 = 136, | |
| ADD_FpI32m64 = 137, | |
| ADD_FpI32m80 = 138, | |
| ADD_FrST0 = 139, | |
| ADJCALLSTACKDOWN32 = 140, | |
| ADJCALLSTACKDOWN64 = 141, | |
| ADJCALLSTACKUP32 = 142, | |
| ADJCALLSTACKUP64 = 143, | |
| AESDECLASTrm = 144, | |
| AESDECLASTrr = 145, | |
| AESDECrm = 146, | |
| AESDECrr = 147, | |
| AESENCLASTrm = 148, | |
| AESENCLASTrr = 149, | |
| AESENCrm = 150, | |
| AESENCrr = 151, | |
| AESIMCrm = 152, | |
| AESIMCrr = 153, | |
| AESKEYGENASSIST128rm = 154, | |
| AESKEYGENASSIST128rr = 155, | |
| AND16i16 = 156, | |
| AND16mi = 157, | |
| AND16mi8 = 158, | |
| AND16mr = 159, | |
| AND16ri = 160, | |
| AND16ri8 = 161, | |
| AND16rm = 162, | |
| AND16rr = 163, | |
| AND16rr_REV = 164, | |
| AND32i32 = 165, | |
| AND32mi = 166, | |
| AND32mi8 = 167, | |
| AND32mr = 168, | |
| AND32ri = 169, | |
| AND32ri8 = 170, | |
| AND32rm = 171, | |
| AND32rr = 172, | |
| AND32rr_REV = 173, | |
| AND64i32 = 174, | |
| AND64mi32 = 175, | |
| AND64mi8 = 176, | |
| AND64mr = 177, | |
| AND64ri32 = 178, | |
| AND64ri8 = 179, | |
| AND64rm = 180, | |
| AND64rr = 181, | |
| AND64rr_REV = 182, | |
| AND8i8 = 183, | |
| AND8mi = 184, | |
| AND8mr = 185, | |
| AND8ri = 186, | |
| AND8rm = 187, | |
| AND8rr = 188, | |
| AND8rr_REV = 189, | |
| ANDN32rm = 190, | |
| ANDN32rr = 191, | |
| ANDN64rm = 192, | |
| ANDN64rr = 193, | |
| ANDNPDrm = 194, | |
| ANDNPDrr = 195, | |
| ANDNPSrm = 196, | |
| ANDNPSrr = 197, | |
| ANDPDrm = 198, | |
| ANDPDrr = 199, | |
| ANDPSrm = 200, | |
| ANDPSrr = 201, | |
| ARPL16mr = 202, | |
| ARPL16rr = 203, | |
| ATOMADD6432 = 204, | |
| ATOMAND16 = 205, | |
| ATOMAND32 = 206, | |
| ATOMAND64 = 207, | |
| ATOMAND6432 = 208, | |
| ATOMAND8 = 209, | |
| ATOMMAX16 = 210, | |
| ATOMMAX32 = 211, | |
| ATOMMAX64 = 212, | |
| ATOMMIN16 = 213, | |
| ATOMMIN32 = 214, | |
| ATOMMIN64 = 215, | |
| ATOMNAND16 = 216, | |
| ATOMNAND32 = 217, | |
| ATOMNAND64 = 218, | |
| ATOMNAND6432 = 219, | |
| ATOMNAND8 = 220, | |
| ATOMOR16 = 221, | |
| ATOMOR32 = 222, | |
| ATOMOR64 = 223, | |
| ATOMOR6432 = 224, | |
| ATOMOR8 = 225, | |
| ATOMSUB6432 = 226, | |
| ATOMSWAP6432 = 227, | |
| ATOMUMAX16 = 228, | |
| ATOMUMAX32 = 229, | |
| ATOMUMAX64 = 230, | |
| ATOMUMIN16 = 231, | |
| ATOMUMIN32 = 232, | |
| ATOMUMIN64 = 233, | |
| ATOMXOR16 = 234, | |
| ATOMXOR32 = 235, | |
| ATOMXOR64 = 236, | |
| ATOMXOR6432 = 237, | |
| ATOMXOR8 = 238, | |
| AVX_SET0PDY = 239, | |
| AVX_SET0PSY = 240, | |
| AVX_SETALLONES = 241, | |
| BLENDPDrmi = 242, | |
| BLENDPDrri = 243, | |
| BLENDPSrmi = 244, | |
| BLENDPSrri = 245, | |
| BLENDVPDrm0 = 246, | |
| BLENDVPDrr0 = 247, | |
| BLENDVPSrm0 = 248, | |
| BLENDVPSrr0 = 249, | |
| BOUNDS16rm = 250, | |
| BOUNDS32rm = 251, | |
| BSF16rm = 252, | |
| BSF16rr = 253, | |
| BSF32rm = 254, | |
| BSF32rr = 255, | |
| BSF64rm = 256, | |
| BSF64rr = 257, | |
| BSR16rm = 258, | |
| BSR16rr = 259, | |
| BSR32rm = 260, | |
| BSR32rr = 261, | |
| BSR64rm = 262, | |
| BSR64rr = 263, | |
| BSWAP32r = 264, | |
| BSWAP64r = 265, | |
| BT16mi8 = 266, | |
| BT16mr = 267, | |
| BT16ri8 = 268, | |
| BT16rr = 269, | |
| BT32mi8 = 270, | |
| BT32mr = 271, | |
| BT32ri8 = 272, | |
| BT32rr = 273, | |
| BT64mi8 = 274, | |
| BT64mr = 275, | |
| BT64ri8 = 276, | |
| BT64rr = 277, | |
| BTC16mi8 = 278, | |
| BTC16mr = 279, | |
| BTC16ri8 = 280, | |
| BTC16rr = 281, | |
| BTC32mi8 = 282, | |
| BTC32mr = 283, | |
| BTC32ri8 = 284, | |
| BTC32rr = 285, | |
| BTC64mi8 = 286, | |
| BTC64mr = 287, | |
| BTC64ri8 = 288, | |
| BTC64rr = 289, | |
| BTR16mi8 = 290, | |
| BTR16mr = 291, | |
| BTR16ri8 = 292, | |
| BTR16rr = 293, | |
| BTR32mi8 = 294, | |
| BTR32mr = 295, | |
| BTR32ri8 = 296, | |
| BTR32rr = 297, | |
| BTR64mi8 = 298, | |
| BTR64mr = 299, | |
| BTR64ri8 = 300, | |
| BTR64rr = 301, | |
| BTS16mi8 = 302, | |
| BTS16mr = 303, | |
| BTS16ri8 = 304, | |
| BTS16rr = 305, | |
| BTS32mi8 = 306, | |
| BTS32mr = 307, | |
| BTS32ri8 = 308, | |
| BTS32rr = 309, | |
| BTS64mi8 = 310, | |
| BTS64mr = 311, | |
| BTS64ri8 = 312, | |
| BTS64rr = 313, | |
| CALL32m = 314, | |
| CALL32r = 315, | |
| CALL64m = 316, | |
| CALL64pcrel32 = 317, | |
| CALL64r = 318, | |
| CALLpcrel16 = 319, | |
| CALLpcrel32 = 320, | |
| CBW = 321, | |
| CDQ = 322, | |
| CDQE = 323, | |
| CHS_F = 324, | |
| CHS_Fp32 = 325, | |
| CHS_Fp64 = 326, | |
| CHS_Fp80 = 327, | |
| CLC = 328, | |
| CLD = 329, | |
| CLFLUSH = 330, | |
| CLI = 331, | |
| CLTS = 332, | |
| CMC = 333, | |
| CMOVA16rm = 334, | |
| CMOVA16rr = 335, | |
| CMOVA32rm = 336, | |
| CMOVA32rr = 337, | |
| CMOVA64rm = 338, | |
| CMOVA64rr = 339, | |
| CMOVAE16rm = 340, | |
| CMOVAE16rr = 341, | |
| CMOVAE32rm = 342, | |
| CMOVAE32rr = 343, | |
| CMOVAE64rm = 344, | |
| CMOVAE64rr = 345, | |
| CMOVB16rm = 346, | |
| CMOVB16rr = 347, | |
| CMOVB32rm = 348, | |
| CMOVB32rr = 349, | |
| CMOVB64rm = 350, | |
| CMOVB64rr = 351, | |
| CMOVBE16rm = 352, | |
| CMOVBE16rr = 353, | |
| CMOVBE32rm = 354, | |
| CMOVBE32rr = 355, | |
| CMOVBE64rm = 356, | |
| CMOVBE64rr = 357, | |
| CMOVBE_F = 358, | |
| CMOVBE_Fp32 = 359, | |
| CMOVBE_Fp64 = 360, | |
| CMOVBE_Fp80 = 361, | |
| CMOVB_F = 362, | |
| CMOVB_Fp32 = 363, | |
| CMOVB_Fp64 = 364, | |
| CMOVB_Fp80 = 365, | |
| CMOVE16rm = 366, | |
| CMOVE16rr = 367, | |
| CMOVE32rm = 368, | |
| CMOVE32rr = 369, | |
| CMOVE64rm = 370, | |
| CMOVE64rr = 371, | |
| CMOVE_F = 372, | |
| CMOVE_Fp32 = 373, | |
| CMOVE_Fp64 = 374, | |
| CMOVE_Fp80 = 375, | |
| CMOVG16rm = 376, | |
| CMOVG16rr = 377, | |
| CMOVG32rm = 378, | |
| CMOVG32rr = 379, | |
| CMOVG64rm = 380, | |
| CMOVG64rr = 381, | |
| CMOVGE16rm = 382, | |
| CMOVGE16rr = 383, | |
| CMOVGE32rm = 384, | |
| CMOVGE32rr = 385, | |
| CMOVGE64rm = 386, | |
| CMOVGE64rr = 387, | |
| CMOVL16rm = 388, | |
| CMOVL16rr = 389, | |
| CMOVL32rm = 390, | |
| CMOVL32rr = 391, | |
| CMOVL64rm = 392, | |
| CMOVL64rr = 393, | |
| CMOVLE16rm = 394, | |
| CMOVLE16rr = 395, | |
| CMOVLE32rm = 396, | |
| CMOVLE32rr = 397, | |
| CMOVLE64rm = 398, | |
| CMOVLE64rr = 399, | |
| CMOVNBE_F = 400, | |
| CMOVNBE_Fp32 = 401, | |
| CMOVNBE_Fp64 = 402, | |
| CMOVNBE_Fp80 = 403, | |
| CMOVNB_F = 404, | |
| CMOVNB_Fp32 = 405, | |
| CMOVNB_Fp64 = 406, | |
| CMOVNB_Fp80 = 407, | |
| CMOVNE16rm = 408, | |
| CMOVNE16rr = 409, | |
| CMOVNE32rm = 410, | |
| CMOVNE32rr = 411, | |
| CMOVNE64rm = 412, | |
| CMOVNE64rr = 413, | |
| CMOVNE_F = 414, | |
| CMOVNE_Fp32 = 415, | |
| CMOVNE_Fp64 = 416, | |
| CMOVNE_Fp80 = 417, | |
| CMOVNO16rm = 418, | |
| CMOVNO16rr = 419, | |
| CMOVNO32rm = 420, | |
| CMOVNO32rr = 421, | |
| CMOVNO64rm = 422, | |
| CMOVNO64rr = 423, | |
| CMOVNP16rm = 424, | |
| CMOVNP16rr = 425, | |
| CMOVNP32rm = 426, | |
| CMOVNP32rr = 427, | |
| CMOVNP64rm = 428, | |
| CMOVNP64rr = 429, | |
| CMOVNP_F = 430, | |
| CMOVNP_Fp32 = 431, | |
| CMOVNP_Fp64 = 432, | |
| CMOVNP_Fp80 = 433, | |
| CMOVNS16rm = 434, | |
| CMOVNS16rr = 435, | |
| CMOVNS32rm = 436, | |
| CMOVNS32rr = 437, | |
| CMOVNS64rm = 438, | |
| CMOVNS64rr = 439, | |
| CMOVO16rm = 440, | |
| CMOVO16rr = 441, | |
| CMOVO32rm = 442, | |
| CMOVO32rr = 443, | |
| CMOVO64rm = 444, | |
| CMOVO64rr = 445, | |
| CMOVP16rm = 446, | |
| CMOVP16rr = 447, | |
| CMOVP32rm = 448, | |
| CMOVP32rr = 449, | |
| CMOVP64rm = 450, | |
| CMOVP64rr = 451, | |
| CMOVP_F = 452, | |
| CMOVP_Fp32 = 453, | |
| CMOVP_Fp64 = 454, | |
| CMOVP_Fp80 = 455, | |
| CMOVS16rm = 456, | |
| CMOVS16rr = 457, | |
| CMOVS32rm = 458, | |
| CMOVS32rr = 459, | |
| CMOVS64rm = 460, | |
| CMOVS64rr = 461, | |
| CMOV_FR32 = 462, | |
| CMOV_FR64 = 463, | |
| CMOV_GR16 = 464, | |
| CMOV_GR32 = 465, | |
| CMOV_GR8 = 466, | |
| CMOV_RFP32 = 467, | |
| CMOV_RFP64 = 468, | |
| CMOV_RFP80 = 469, | |
| CMOV_V2F64 = 470, | |
| CMOV_V2I64 = 471, | |
| CMOV_V4F32 = 472, | |
| CMOV_V4F64 = 473, | |
| CMOV_V4I64 = 474, | |
| CMOV_V8F32 = 475, | |
| CMP16i16 = 476, | |
| CMP16mi = 477, | |
| CMP16mi8 = 478, | |
| CMP16mr = 479, | |
| CMP16ri = 480, | |
| CMP16ri8 = 481, | |
| CMP16rm = 482, | |
| CMP16rr = 483, | |
| CMP16rr_REV = 484, | |
| CMP32i32 = 485, | |
| CMP32mi = 486, | |
| CMP32mi8 = 487, | |
| CMP32mr = 488, | |
| CMP32ri = 489, | |
| CMP32ri8 = 490, | |
| CMP32rm = 491, | |
| CMP32rr = 492, | |
| CMP32rr_REV = 493, | |
| CMP64i32 = 494, | |
| CMP64mi32 = 495, | |
| CMP64mi8 = 496, | |
| CMP64mr = 497, | |
| CMP64ri32 = 498, | |
| CMP64ri8 = 499, | |
| CMP64rm = 500, | |
| CMP64rr = 501, | |
| CMP64rr_REV = 502, | |
| CMP8i8 = 503, | |
| CMP8mi = 504, | |
| CMP8mr = 505, | |
| CMP8ri = 506, | |
| CMP8rm = 507, | |
| CMP8rr = 508, | |
| CMP8rr_REV = 509, | |
| CMPPDrmi = 510, | |
| CMPPDrmi_alt = 511, | |
| CMPPDrri = 512, | |
| CMPPDrri_alt = 513, | |
| CMPPSrmi = 514, | |
| CMPPSrmi_alt = 515, | |
| CMPPSrri = 516, | |
| CMPPSrri_alt = 517, | |
| CMPS16 = 518, | |
| CMPS32 = 519, | |
| CMPS64 = 520, | |
| CMPS8 = 521, | |
| CMPSDrm = 522, | |
| CMPSDrm_alt = 523, | |
| CMPSDrr = 524, | |
| CMPSDrr_alt = 525, | |
| CMPSSrm = 526, | |
| CMPSSrm_alt = 527, | |
| CMPSSrr = 528, | |
| CMPSSrr_alt = 529, | |
| CMPXCHG16B = 530, | |
| CMPXCHG16rm = 531, | |
| CMPXCHG16rr = 532, | |
| CMPXCHG32rm = 533, | |
| CMPXCHG32rr = 534, | |
| CMPXCHG64rm = 535, | |
| CMPXCHG64rr = 536, | |
| CMPXCHG8B = 537, | |
| CMPXCHG8rm = 538, | |
| CMPXCHG8rr = 539, | |
| COMISDrm = 540, | |
| COMISDrr = 541, | |
| COMISSrm = 542, | |
| COMISSrr = 543, | |
| COMP_FST0r = 544, | |
| COM_FIPr = 545, | |
| COM_FIr = 546, | |
| COM_FST0r = 547, | |
| COS_F = 548, | |
| COS_Fp32 = 549, | |
| COS_Fp64 = 550, | |
| COS_Fp80 = 551, | |
| CPUID = 552, | |
| CQO = 553, | |
| CRC32r32m16 = 554, | |
| CRC32r32m32 = 555, | |
| CRC32r32m8 = 556, | |
| CRC32r32r16 = 557, | |
| CRC32r32r32 = 558, | |
| CRC32r32r8 = 559, | |
| CRC32r64m64 = 560, | |
| CRC32r64m8 = 561, | |
| CRC32r64r64 = 562, | |
| CRC32r64r8 = 563, | |
| CS_PREFIX = 564, | |
| CVTDQ2PDrm = 565, | |
| CVTDQ2PDrr = 566, | |
| CVTDQ2PSrm = 567, | |
| CVTDQ2PSrr = 568, | |
| CVTPD2DQrm = 569, | |
| CVTPD2DQrr = 570, | |
| CVTPD2PSrm = 571, | |
| CVTPD2PSrr = 572, | |
| CVTPS2DQrm = 573, | |
| CVTPS2DQrr = 574, | |
| CVTPS2PDrm = 575, | |
| CVTPS2PDrr = 576, | |
| CVTSD2SI64rm = 577, | |
| CVTSD2SI64rr = 578, | |
| CVTSD2SIrm = 579, | |
| CVTSD2SIrr = 580, | |
| CVTSD2SSrm = 581, | |
| CVTSD2SSrr = 582, | |
| CVTSI2SD64rm = 583, | |
| CVTSI2SD64rr = 584, | |
| CVTSI2SDrm = 585, | |
| CVTSI2SDrr = 586, | |
| CVTSI2SS64rm = 587, | |
| CVTSI2SS64rr = 588, | |
| CVTSI2SSrm = 589, | |
| CVTSI2SSrr = 590, | |
| CVTSS2SDrm = 591, | |
| CVTSS2SDrr = 592, | |
| CVTSS2SI64rm = 593, | |
| CVTSS2SI64rr = 594, | |
| CVTSS2SIrm = 595, | |
| CVTSS2SIrr = 596, | |
| CVTTPD2DQrm = 597, | |
| CVTTPD2DQrr = 598, | |
| CVTTPS2DQrm = 599, | |
| CVTTPS2DQrr = 600, | |
| CVTTSD2SI64rm = 601, | |
| CVTTSD2SI64rr = 602, | |
| CVTTSD2SIrm = 603, | |
| CVTTSD2SIrr = 604, | |
| CVTTSS2SI64rm = 605, | |
| CVTTSS2SI64rr = 606, | |
| CVTTSS2SIrm = 607, | |
| CVTTSS2SIrr = 608, | |
| CWD = 609, | |
| CWDE = 610, | |
| DAA = 611, | |
| DAS = 612, | |
| DATA16_PREFIX = 613, | |
| DEC16m = 614, | |
| DEC16r = 615, | |
| DEC32m = 616, | |
| DEC32r = 617, | |
| DEC64_16m = 618, | |
| DEC64_16r = 619, | |
| DEC64_32m = 620, | |
| DEC64_32r = 621, | |
| DEC64m = 622, | |
| DEC64r = 623, | |
| DEC8m = 624, | |
| DEC8r = 625, | |
| DIV16m = 626, | |
| DIV16r = 627, | |
| DIV32m = 628, | |
| DIV32r = 629, | |
| DIV64m = 630, | |
| DIV64r = 631, | |
| DIV8m = 632, | |
| DIV8r = 633, | |
| DIVPDrm = 634, | |
| DIVPDrr = 635, | |
| DIVPSrm = 636, | |
| DIVPSrr = 637, | |
| DIVR_F32m = 638, | |
| DIVR_F64m = 639, | |
| DIVR_FI16m = 640, | |
| DIVR_FI32m = 641, | |
| DIVR_FPrST0 = 642, | |
| DIVR_FST0r = 643, | |
| DIVR_Fp32m = 644, | |
| DIVR_Fp64m = 645, | |
| DIVR_Fp64m32 = 646, | |
| DIVR_Fp80m32 = 647, | |
| DIVR_Fp80m64 = 648, | |
| DIVR_FpI16m32 = 649, | |
| DIVR_FpI16m64 = 650, | |
| DIVR_FpI16m80 = 651, | |
| DIVR_FpI32m32 = 652, | |
| DIVR_FpI32m64 = 653, | |
| DIVR_FpI32m80 = 654, | |
| DIVR_FrST0 = 655, | |
| DIVSDrm = 656, | |
| DIVSDrm_Int = 657, | |
| DIVSDrr = 658, | |
| DIVSDrr_Int = 659, | |
| DIVSSrm = 660, | |
| DIVSSrm_Int = 661, | |
| DIVSSrr = 662, | |
| DIVSSrr_Int = 663, | |
| DIV_F32m = 664, | |
| DIV_F64m = 665, | |
| DIV_FI16m = 666, | |
| DIV_FI32m = 667, | |
| DIV_FPrST0 = 668, | |
| DIV_FST0r = 669, | |
| DIV_Fp32 = 670, | |
| DIV_Fp32m = 671, | |
| DIV_Fp64 = 672, | |
| DIV_Fp64m = 673, | |
| DIV_Fp64m32 = 674, | |
| DIV_Fp80 = 675, | |
| DIV_Fp80m32 = 676, | |
| DIV_Fp80m64 = 677, | |
| DIV_FpI16m32 = 678, | |
| DIV_FpI16m64 = 679, | |
| DIV_FpI16m80 = 680, | |
| DIV_FpI32m32 = 681, | |
| DIV_FpI32m64 = 682, | |
| DIV_FpI32m80 = 683, | |
| DIV_FrST0 = 684, | |
| DPPDrmi = 685, | |
| DPPDrri = 686, | |
| DPPSrmi = 687, | |
| DPPSrri = 688, | |
| DS_PREFIX = 689, | |
| EH_RETURN = 690, | |
| EH_RETURN64 = 691, | |
| ENTER = 692, | |
| ES_PREFIX = 693, | |
| EXTRACTPSmr = 694, | |
| EXTRACTPSrr = 695, | |
| F2XM1 = 696, | |
| FARCALL16i = 697, | |
| FARCALL16m = 698, | |
| FARCALL32i = 699, | |
| FARCALL32m = 700, | |
| FARCALL64 = 701, | |
| FARJMP16i = 702, | |
| FARJMP16m = 703, | |
| FARJMP32i = 704, | |
| FARJMP32m = 705, | |
| FARJMP64 = 706, | |
| FBLDm = 707, | |
| FBSTPm = 708, | |
| FCOM32m = 709, | |
| FCOM64m = 710, | |
| FCOMP32m = 711, | |
| FCOMP64m = 712, | |
| FCOMPP = 713, | |
| FDECSTP = 714, | |
| FEMMS = 715, | |
| FFREE = 716, | |
| FICOM16m = 717, | |
| FICOM32m = 718, | |
| FICOMP16m = 719, | |
| FICOMP32m = 720, | |
| FINCSTP = 721, | |
| FLDCW16m = 722, | |
| FLDENVm = 723, | |
| FLDL2E = 724, | |
| FLDL2T = 725, | |
| FLDLG2 = 726, | |
| FLDLN2 = 727, | |
| FLDPI = 728, | |
| FNCLEX = 729, | |
| FNINIT = 730, | |
| FNOP = 731, | |
| FNSTCW16m = 732, | |
| FNSTSW8r = 733, | |
| FNSTSWm = 734, | |
| FP32_TO_INT16_IN_MEM = 735, | |
| FP32_TO_INT32_IN_MEM = 736, | |
| FP32_TO_INT64_IN_MEM = 737, | |
| FP64_TO_INT16_IN_MEM = 738, | |
| FP64_TO_INT32_IN_MEM = 739, | |
| FP64_TO_INT64_IN_MEM = 740, | |
| FP80_TO_INT16_IN_MEM = 741, | |
| FP80_TO_INT32_IN_MEM = 742, | |
| FP80_TO_INT64_IN_MEM = 743, | |
| FPATAN = 744, | |
| FPREM = 745, | |
| FPREM1 = 746, | |
| FPTAN = 747, | |
| FRNDINT = 748, | |
| FRSTORm = 749, | |
| FSAVEm = 750, | |
| FSCALE = 751, | |
| FSINCOS = 752, | |
| FSTENVm = 753, | |
| FS_PREFIX = 754, | |
| FXAM = 755, | |
| FXRSTOR = 756, | |
| FXRSTOR64 = 757, | |
| FXSAVE = 758, | |
| FXSAVE64 = 759, | |
| FXTRACT = 760, | |
| FYL2X = 761, | |
| FYL2XP1 = 762, | |
| FpPOP_RETVAL = 763, | |
| FsANDNPDrm = 764, | |
| FsANDNPDrr = 765, | |
| FsANDNPSrm = 766, | |
| FsANDNPSrr = 767, | |
| FsANDPDrm = 768, | |
| FsANDPDrr = 769, | |
| FsANDPSrm = 770, | |
| FsANDPSrr = 771, | |
| FsFLD0SD = 772, | |
| FsFLD0SS = 773, | |
| FsMOVAPDrm = 774, | |
| FsMOVAPDrr = 775, | |
| FsMOVAPSrm = 776, | |
| FsMOVAPSrr = 777, | |
| FsORPDrm = 778, | |
| FsORPDrr = 779, | |
| FsORPSrm = 780, | |
| FsORPSrr = 781, | |
| FsVMOVAPDrm = 782, | |
| FsVMOVAPDrr = 783, | |
| FsVMOVAPSrm = 784, | |
| FsVMOVAPSrr = 785, | |
| FsXORPDrm = 786, | |
| FsXORPDrr = 787, | |
| FsXORPSrm = 788, | |
| FsXORPSrr = 789, | |
| GS_PREFIX = 790, | |
| HADDPDrm = 791, | |
| HADDPDrr = 792, | |
| HADDPSrm = 793, | |
| HADDPSrr = 794, | |
| HLT = 795, | |
| HSUBPDrm = 796, | |
| HSUBPDrr = 797, | |
| HSUBPSrm = 798, | |
| HSUBPSrr = 799, | |
| IDIV16m = 800, | |
| IDIV16r = 801, | |
| IDIV32m = 802, | |
| IDIV32r = 803, | |
| IDIV64m = 804, | |
| IDIV64r = 805, | |
| IDIV8m = 806, | |
| IDIV8r = 807, | |
| ILD_F16m = 808, | |
| ILD_F32m = 809, | |
| ILD_F64m = 810, | |
| ILD_Fp16m32 = 811, | |
| ILD_Fp16m64 = 812, | |
| ILD_Fp16m80 = 813, | |
| ILD_Fp32m32 = 814, | |
| ILD_Fp32m64 = 815, | |
| ILD_Fp32m80 = 816, | |
| ILD_Fp64m32 = 817, | |
| ILD_Fp64m64 = 818, | |
| ILD_Fp64m80 = 819, | |
| IMUL16m = 820, | |
| IMUL16r = 821, | |
| IMUL16rm = 822, | |
| IMUL16rmi = 823, | |
| IMUL16rmi8 = 824, | |
| IMUL16rr = 825, | |
| IMUL16rri = 826, | |
| IMUL16rri8 = 827, | |
| IMUL32m = 828, | |
| IMUL32r = 829, | |
| IMUL32rm = 830, | |
| IMUL32rmi = 831, | |
| IMUL32rmi8 = 832, | |
| IMUL32rr = 833, | |
| IMUL32rri = 834, | |
| IMUL32rri8 = 835, | |
| IMUL64m = 836, | |
| IMUL64r = 837, | |
| IMUL64rm = 838, | |
| IMUL64rmi32 = 839, | |
| IMUL64rmi8 = 840, | |
| IMUL64rr = 841, | |
| IMUL64rri32 = 842, | |
| IMUL64rri8 = 843, | |
| IMUL8m = 844, | |
| IMUL8r = 845, | |
| IN16 = 846, | |
| IN16ri = 847, | |
| IN16rr = 848, | |
| IN32 = 849, | |
| IN32ri = 850, | |
| IN32rr = 851, | |
| IN8 = 852, | |
| IN8ri = 853, | |
| IN8rr = 854, | |
| INC16m = 855, | |
| INC16r = 856, | |
| INC32m = 857, | |
| INC32r = 858, | |
| INC64_16m = 859, | |
| INC64_16r = 860, | |
| INC64_32m = 861, | |
| INC64_32r = 862, | |
| INC64m = 863, | |
| INC64r = 864, | |
| INC8m = 865, | |
| INC8r = 866, | |
| INSERTPSrm = 867, | |
| INSERTPSrr = 868, | |
| INT = 869, | |
| INT3 = 870, | |
| INTO = 871, | |
| INVD = 872, | |
| INVEPT32 = 873, | |
| INVEPT64 = 874, | |
| INVLPG = 875, | |
| INVVPID32 = 876, | |
| INVVPID64 = 877, | |
| IRET16 = 878, | |
| IRET32 = 879, | |
| IRET64 = 880, | |
| ISTT_FP16m = 881, | |
| ISTT_FP32m = 882, | |
| ISTT_FP64m = 883, | |
| ISTT_Fp16m32 = 884, | |
| ISTT_Fp16m64 = 885, | |
| ISTT_Fp16m80 = 886, | |
| ISTT_Fp32m32 = 887, | |
| ISTT_Fp32m64 = 888, | |
| ISTT_Fp32m80 = 889, | |
| ISTT_Fp64m32 = 890, | |
| ISTT_Fp64m64 = 891, | |
| ISTT_Fp64m80 = 892, | |
| IST_F16m = 893, | |
| IST_F32m = 894, | |
| IST_FP16m = 895, | |
| IST_FP32m = 896, | |
| IST_FP64m = 897, | |
| IST_Fp16m32 = 898, | |
| IST_Fp16m64 = 899, | |
| IST_Fp16m80 = 900, | |
| IST_Fp32m32 = 901, | |
| IST_Fp32m64 = 902, | |
| IST_Fp32m80 = 903, | |
| IST_Fp64m32 = 904, | |
| IST_Fp64m64 = 905, | |
| IST_Fp64m80 = 906, | |
| Int_CMPSDrm = 907, | |
| Int_CMPSDrr = 908, | |
| Int_CMPSSrm = 909, | |
| Int_CMPSSrr = 910, | |
| Int_COMISDrm = 911, | |
| Int_COMISDrr = 912, | |
| Int_COMISSrm = 913, | |
| Int_COMISSrr = 914, | |
| Int_CVTDQ2PDrm = 915, | |
| Int_CVTDQ2PDrr = 916, | |
| Int_CVTDQ2PSrm = 917, | |
| Int_CVTDQ2PSrr = 918, | |
| Int_CVTPD2DQrm = 919, | |
| Int_CVTPD2DQrr = 920, | |
| Int_CVTPD2PSrm = 921, | |
| Int_CVTPD2PSrr = 922, | |
| Int_CVTPS2DQrm = 923, | |
| Int_CVTPS2DQrr = 924, | |
| Int_CVTPS2PDrm = 925, | |
| Int_CVTPS2PDrr = 926, | |
| Int_CVTSD2SSrm = 927, | |
| Int_CVTSD2SSrr = 928, | |
| Int_CVTSI2SD64rm = 929, | |
| Int_CVTSI2SD64rr = 930, | |
| Int_CVTSI2SDrm = 931, | |
| Int_CVTSI2SDrr = 932, | |
| Int_CVTSI2SS64rm = 933, | |
| Int_CVTSI2SS64rr = 934, | |
| Int_CVTSI2SSrm = 935, | |
| Int_CVTSI2SSrr = 936, | |
| Int_CVTSS2SDrm = 937, | |
| Int_CVTSS2SDrr = 938, | |
| Int_CVTTSD2SI64rm = 939, | |
| Int_CVTTSD2SI64rr = 940, | |
| Int_CVTTSD2SIrm = 941, | |
| Int_CVTTSD2SIrr = 942, | |
| Int_CVTTSS2SI64rm = 943, | |
| Int_CVTTSS2SI64rr = 944, | |
| Int_CVTTSS2SIrm = 945, | |
| Int_CVTTSS2SIrr = 946, | |
| Int_MemBarrier = 947, | |
| Int_MemBarrierNoSSE64 = 948, | |
| Int_UCOMISDrm = 949, | |
| Int_UCOMISDrr = 950, | |
| Int_UCOMISSrm = 951, | |
| Int_UCOMISSrr = 952, | |
| Int_VCMPSDrm = 953, | |
| Int_VCMPSDrr = 954, | |
| Int_VCMPSSrm = 955, | |
| Int_VCMPSSrr = 956, | |
| Int_VCOMISDrm = 957, | |
| Int_VCOMISDrr = 958, | |
| Int_VCOMISSrm = 959, | |
| Int_VCOMISSrr = 960, | |
| Int_VCVTDQ2PDrm = 961, | |
| Int_VCVTDQ2PDrr = 962, | |
| Int_VCVTDQ2PSrm = 963, | |
| Int_VCVTDQ2PSrr = 964, | |
| Int_VCVTPD2DQrm = 965, | |
| Int_VCVTPD2DQrr = 966, | |
| Int_VCVTPD2PSrm = 967, | |
| Int_VCVTPD2PSrr = 968, | |
| Int_VCVTPS2DQrm = 969, | |
| Int_VCVTPS2DQrr = 970, | |
| Int_VCVTPS2PDrm = 971, | |
| Int_VCVTPS2PDrr = 972, | |
| Int_VCVTSD2SI64rm = 973, | |
| Int_VCVTSD2SI64rr = 974, | |
| Int_VCVTSD2SIrm = 975, | |
| Int_VCVTSD2SIrr = 976, | |
| Int_VCVTSD2SSrm = 977, | |
| Int_VCVTSD2SSrr = 978, | |
| Int_VCVTSI2SD64rm = 979, | |
| Int_VCVTSI2SD64rr = 980, | |
| Int_VCVTSI2SDrm = 981, | |
| Int_VCVTSI2SDrr = 982, | |
| Int_VCVTSI2SS64rm = 983, | |
| Int_VCVTSI2SS64rr = 984, | |
| Int_VCVTSI2SSrm = 985, | |
| Int_VCVTSI2SSrr = 986, | |
| Int_VCVTSS2SDrm = 987, | |
| Int_VCVTSS2SDrr = 988, | |
| Int_VCVTTPS2DQrm = 989, | |
| Int_VCVTTPS2DQrr = 990, | |
| Int_VCVTTSD2SI64rm = 991, | |
| Int_VCVTTSD2SI64rr = 992, | |
| Int_VCVTTSD2SIrm = 993, | |
| Int_VCVTTSD2SIrr = 994, | |
| Int_VCVTTSS2SI64rm = 995, | |
| Int_VCVTTSS2SI64rr = 996, | |
| Int_VCVTTSS2SIrm = 997, | |
| Int_VCVTTSS2SIrr = 998, | |
| Int_VUCOMISDrm = 999, | |
| Int_VUCOMISDrr = 1000, | |
| Int_VUCOMISSrm = 1001, | |
| Int_VUCOMISSrr = 1002, | |
| JAE_1 = 1003, | |
| JAE_4 = 1004, | |
| JA_1 = 1005, | |
| JA_4 = 1006, | |
| JBE_1 = 1007, | |
| JBE_4 = 1008, | |
| JB_1 = 1009, | |
| JB_4 = 1010, | |
| JCXZ = 1011, | |
| JECXZ_32 = 1012, | |
| JECXZ_64 = 1013, | |
| JE_1 = 1014, | |
| JE_4 = 1015, | |
| JGE_1 = 1016, | |
| JGE_4 = 1017, | |
| JG_1 = 1018, | |
| JG_4 = 1019, | |
| JLE_1 = 1020, | |
| JLE_4 = 1021, | |
| JL_1 = 1022, | |
| JL_4 = 1023, | |
| JMP32m = 1024, | |
| JMP32r = 1025, | |
| JMP64m = 1026, | |
| JMP64pcrel32 = 1027, | |
| JMP64r = 1028, | |
| JMP_1 = 1029, | |
| JMP_4 = 1030, | |
| JNE_1 = 1031, | |
| JNE_4 = 1032, | |
| JNO_1 = 1033, | |
| JNO_4 = 1034, | |
| JNP_1 = 1035, | |
| JNP_4 = 1036, | |
| JNS_1 = 1037, | |
| JNS_4 = 1038, | |
| JO_1 = 1039, | |
| JO_4 = 1040, | |
| JP_1 = 1041, | |
| JP_4 = 1042, | |
| JRCXZ = 1043, | |
| JS_1 = 1044, | |
| JS_4 = 1045, | |
| LAHF = 1046, | |
| LAR16rm = 1047, | |
| LAR16rr = 1048, | |
| LAR32rm = 1049, | |
| LAR32rr = 1050, | |
| LAR64rm = 1051, | |
| LAR64rr = 1052, | |
| LCMPXCHG16 = 1053, | |
| LCMPXCHG16B = 1054, | |
| LCMPXCHG32 = 1055, | |
| LCMPXCHG64 = 1056, | |
| LCMPXCHG8 = 1057, | |
| LCMPXCHG8B = 1058, | |
| LDDQUrm = 1059, | |
| LDMXCSR = 1060, | |
| LDS16rm = 1061, | |
| LDS32rm = 1062, | |
| LD_F0 = 1063, | |
| LD_F1 = 1064, | |
| LD_F32m = 1065, | |
| LD_F64m = 1066, | |
| LD_F80m = 1067, | |
| LD_Fp032 = 1068, | |
| LD_Fp064 = 1069, | |
| LD_Fp080 = 1070, | |
| LD_Fp132 = 1071, | |
| LD_Fp164 = 1072, | |
| LD_Fp180 = 1073, | |
| LD_Fp32m = 1074, | |
| LD_Fp32m64 = 1075, | |
| LD_Fp32m80 = 1076, | |
| LD_Fp64m = 1077, | |
| LD_Fp64m80 = 1078, | |
| LD_Fp80m = 1079, | |
| LD_Frr = 1080, | |
| LEA16r = 1081, | |
| LEA32r = 1082, | |
| LEA64_32r = 1083, | |
| LEA64r = 1084, | |
| LEAVE = 1085, | |
| LEAVE64 = 1086, | |
| LES16rm = 1087, | |
| LES32rm = 1088, | |
| LFENCE = 1089, | |
| LFS16rm = 1090, | |
| LFS32rm = 1091, | |
| LFS64rm = 1092, | |
| LGDT16m = 1093, | |
| LGDTm = 1094, | |
| LGS16rm = 1095, | |
| LGS32rm = 1096, | |
| LGS64rm = 1097, | |
| LIDT16m = 1098, | |
| LIDTm = 1099, | |
| LLDT16m = 1100, | |
| LLDT16r = 1101, | |
| LMSW16m = 1102, | |
| LMSW16r = 1103, | |
| LOCK_ADD16mi = 1104, | |
| LOCK_ADD16mi8 = 1105, | |
| LOCK_ADD16mr = 1106, | |
| LOCK_ADD32mi = 1107, | |
| LOCK_ADD32mi8 = 1108, | |
| LOCK_ADD32mr = 1109, | |
| LOCK_ADD64mi32 = 1110, | |
| LOCK_ADD64mi8 = 1111, | |
| LOCK_ADD64mr = 1112, | |
| LOCK_ADD8mi = 1113, | |
| LOCK_ADD8mr = 1114, | |
| LOCK_AND16mi = 1115, | |
| LOCK_AND16mi8 = 1116, | |
| LOCK_AND16mr = 1117, | |
| LOCK_AND32mi = 1118, | |
| LOCK_AND32mi8 = 1119, | |
| LOCK_AND32mr = 1120, | |
| LOCK_AND64mi32 = 1121, | |
| LOCK_AND64mi8 = 1122, | |
| LOCK_AND64mr = 1123, | |
| LOCK_AND8mi = 1124, | |
| LOCK_AND8mr = 1125, | |
| LOCK_DEC16m = 1126, | |
| LOCK_DEC32m = 1127, | |
| LOCK_DEC64m = 1128, | |
| LOCK_DEC8m = 1129, | |
| LOCK_INC16m = 1130, | |
| LOCK_INC32m = 1131, | |
| LOCK_INC64m = 1132, | |
| LOCK_INC8m = 1133, | |
| LOCK_OR16mi = 1134, | |
| LOCK_OR16mi8 = 1135, | |
| LOCK_OR16mr = 1136, | |
| LOCK_OR32mi = 1137, | |
| LOCK_OR32mi8 = 1138, | |
| LOCK_OR32mr = 1139, | |
| LOCK_OR64mi32 = 1140, | |
| LOCK_OR64mi8 = 1141, | |
| LOCK_OR64mr = 1142, | |
| LOCK_OR8mi = 1143, | |
| LOCK_OR8mr = 1144, | |
| LOCK_PREFIX = 1145, | |
| LOCK_SUB16mi = 1146, | |
| LOCK_SUB16mi8 = 1147, | |
| LOCK_SUB16mr = 1148, | |
| LOCK_SUB32mi = 1149, | |
| LOCK_SUB32mi8 = 1150, | |
| LOCK_SUB32mr = 1151, | |
| LOCK_SUB64mi32 = 1152, | |
| LOCK_SUB64mi8 = 1153, | |
| LOCK_SUB64mr = 1154, | |
| LOCK_SUB8mi = 1155, | |
| LOCK_SUB8mr = 1156, | |
| LOCK_XOR16mi = 1157, | |
| LOCK_XOR16mi8 = 1158, | |
| LOCK_XOR16mr = 1159, | |
| LOCK_XOR32mi = 1160, | |
| LOCK_XOR32mi8 = 1161, | |
| LOCK_XOR32mr = 1162, | |
| LOCK_XOR64mi32 = 1163, | |
| LOCK_XOR64mi8 = 1164, | |
| LOCK_XOR64mr = 1165, | |
| LOCK_XOR8mi = 1166, | |
| LOCK_XOR8mr = 1167, | |
| LODSB = 1168, | |
| LODSD = 1169, | |
| LODSQ = 1170, | |
| LODSW = 1171, | |
| LOOP = 1172, | |
| LOOPE = 1173, | |
| LOOPNE = 1174, | |
| LRETI = 1175, | |
| LRETIW = 1176, | |
| LRETL = 1177, | |
| LRETQ = 1178, | |
| LSL16rm = 1179, | |
| LSL16rr = 1180, | |
| LSL32rm = 1181, | |
| LSL32rr = 1182, | |
| LSL64rm = 1183, | |
| LSL64rr = 1184, | |
| LSS16rm = 1185, | |
| LSS32rm = 1186, | |
| LSS64rm = 1187, | |
| LTRm = 1188, | |
| LTRr = 1189, | |
| LXADD16 = 1190, | |
| LXADD32 = 1191, | |
| LXADD64 = 1192, | |
| LXADD8 = 1193, | |
| LZCNT16rm = 1194, | |
| LZCNT16rr = 1195, | |
| LZCNT32rm = 1196, | |
| LZCNT32rr = 1197, | |
| LZCNT64rm = 1198, | |
| LZCNT64rr = 1199, | |
| MASKMOVDQU = 1200, | |
| MASKMOVDQU64 = 1201, | |
| MAXPDrm = 1202, | |
| MAXPDrm_Int = 1203, | |
| MAXPDrr = 1204, | |
| MAXPDrr_Int = 1205, | |
| MAXPSrm = 1206, | |
| MAXPSrm_Int = 1207, | |
| MAXPSrr = 1208, | |
| MAXPSrr_Int = 1209, | |
| MAXSDrm = 1210, | |
| MAXSDrm_Int = 1211, | |
| MAXSDrr = 1212, | |
| MAXSDrr_Int = 1213, | |
| MAXSSrm = 1214, | |
| MAXSSrm_Int = 1215, | |
| MAXSSrr = 1216, | |
| MAXSSrr_Int = 1217, | |
| MFENCE = 1218, | |
| MINPDrm = 1219, | |
| MINPDrm_Int = 1220, | |
| MINPDrr = 1221, | |
| MINPDrr_Int = 1222, | |
| MINPSrm = 1223, | |
| MINPSrm_Int = 1224, | |
| MINPSrr = 1225, | |
| MINPSrr_Int = 1226, | |
| MINSDrm = 1227, | |
| MINSDrm_Int = 1228, | |
| MINSDrr = 1229, | |
| MINSDrr_Int = 1230, | |
| MINSSrm = 1231, | |
| MINSSrm_Int = 1232, | |
| MINSSrr = 1233, | |
| MINSSrr_Int = 1234, | |
| MMX_CVTPD2PIirm = 1235, | |
| MMX_CVTPD2PIirr = 1236, | |
| MMX_CVTPI2PDirm = 1237, | |
| MMX_CVTPI2PDirr = 1238, | |
| MMX_CVTPI2PSirm = 1239, | |
| MMX_CVTPI2PSirr = 1240, | |
| MMX_CVTPS2PIirm = 1241, | |
| MMX_CVTPS2PIirr = 1242, | |
| MMX_CVTTPD2PIirm = 1243, | |
| MMX_CVTTPD2PIirr = 1244, | |
| MMX_CVTTPS2PIirm = 1245, | |
| MMX_CVTTPS2PIirr = 1246, | |
| MMX_EMMS = 1247, | |
| MMX_MASKMOVQ = 1248, | |
| MMX_MASKMOVQ64 = 1249, | |
| MMX_MOVD64from64rr = 1250, | |
| MMX_MOVD64grr = 1251, | |
| MMX_MOVD64mr = 1252, | |
| MMX_MOVD64rm = 1253, | |
| MMX_MOVD64rr = 1254, | |
| MMX_MOVD64rrv164 = 1255, | |
| MMX_MOVD64to64rr = 1256, | |
| MMX_MOVDQ2Qrr = 1257, | |
| MMX_MOVFR642Qrr = 1258, | |
| MMX_MOVNTQmr = 1259, | |
| MMX_MOVQ2DQrr = 1260, | |
| MMX_MOVQ2FR64rr = 1261, | |
| MMX_MOVQ64mr = 1262, | |
| MMX_MOVQ64rm = 1263, | |
| MMX_MOVQ64rr = 1264, | |
| MMX_MOVZDI2PDIrm = 1265, | |
| MMX_MOVZDI2PDIrr = 1266, | |
| MMX_PABSBrm64 = 1267, | |
| MMX_PABSBrr64 = 1268, | |
| MMX_PABSDrm64 = 1269, | |
| MMX_PABSDrr64 = 1270, | |
| MMX_PABSWrm64 = 1271, | |
| MMX_PABSWrr64 = 1272, | |
| MMX_PACKSSDWirm = 1273, | |
| MMX_PACKSSDWirr = 1274, | |
| MMX_PACKSSWBirm = 1275, | |
| MMX_PACKSSWBirr = 1276, | |
| MMX_PACKUSWBirm = 1277, | |
| MMX_PACKUSWBirr = 1278, | |
| MMX_PADDBirm = 1279, | |
| MMX_PADDBirr = 1280, | |
| MMX_PADDDirm = 1281, | |
| MMX_PADDDirr = 1282, | |
| MMX_PADDQirm = 1283, | |
| MMX_PADDQirr = 1284, | |
| MMX_PADDSBirm = 1285, | |
| MMX_PADDSBirr = 1286, | |
| MMX_PADDSWirm = 1287, | |
| MMX_PADDSWirr = 1288, | |
| MMX_PADDUSBirm = 1289, | |
| MMX_PADDUSBirr = 1290, | |
| MMX_PADDUSWirm = 1291, | |
| MMX_PADDUSWirr = 1292, | |
| MMX_PADDWirm = 1293, | |
| MMX_PADDWirr = 1294, | |
| MMX_PALIGNR64irm = 1295, | |
| MMX_PALIGNR64irr = 1296, | |
| MMX_PANDNirm = 1297, | |
| MMX_PANDNirr = 1298, | |
| MMX_PANDirm = 1299, | |
| MMX_PANDirr = 1300, | |
| MMX_PAVGBirm = 1301, | |
| MMX_PAVGBirr = 1302, | |
| MMX_PAVGWirm = 1303, | |
| MMX_PAVGWirr = 1304, | |
| MMX_PCMPEQBirm = 1305, | |
| MMX_PCMPEQBirr = 1306, | |
| MMX_PCMPEQDirm = 1307, | |
| MMX_PCMPEQDirr = 1308, | |
| MMX_PCMPEQWirm = 1309, | |
| MMX_PCMPEQWirr = 1310, | |
| MMX_PCMPGTBirm = 1311, | |
| MMX_PCMPGTBirr = 1312, | |
| MMX_PCMPGTDirm = 1313, | |
| MMX_PCMPGTDirr = 1314, | |
| MMX_PCMPGTWirm = 1315, | |
| MMX_PCMPGTWirr = 1316, | |
| MMX_PEXTRWirri = 1317, | |
| MMX_PHADDSWrm64 = 1318, | |
| MMX_PHADDSWrr64 = 1319, | |
| MMX_PHADDWrm64 = 1320, | |
| MMX_PHADDWrr64 = 1321, | |
| MMX_PHADDrm64 = 1322, | |
| MMX_PHADDrr64 = 1323, | |
| MMX_PHSUBDrm64 = 1324, | |
| MMX_PHSUBDrr64 = 1325, | |
| MMX_PHSUBSWrm64 = 1326, | |
| MMX_PHSUBSWrr64 = 1327, | |
| MMX_PHSUBWrm64 = 1328, | |
| MMX_PHSUBWrr64 = 1329, | |
| MMX_PINSRWirmi = 1330, | |
| MMX_PINSRWirri = 1331, | |
| MMX_PMADDUBSWrm64 = 1332, | |
| MMX_PMADDUBSWrr64 = 1333, | |
| MMX_PMADDWDirm = 1334, | |
| MMX_PMADDWDirr = 1335, | |
| MMX_PMAXSWirm = 1336, | |
| MMX_PMAXSWirr = 1337, | |
| MMX_PMAXUBirm = 1338, | |
| MMX_PMAXUBirr = 1339, | |
| MMX_PMINSWirm = 1340, | |
| MMX_PMINSWirr = 1341, | |
| MMX_PMINUBirm = 1342, | |
| MMX_PMINUBirr = 1343, | |
| MMX_PMOVMSKBrr = 1344, | |
| MMX_PMULHRSWrm64 = 1345, | |
| MMX_PMULHRSWrr64 = 1346, | |
| MMX_PMULHUWirm = 1347, | |
| MMX_PMULHUWirr = 1348, | |
| MMX_PMULHWirm = 1349, | |
| MMX_PMULHWirr = 1350, | |
| MMX_PMULLWirm = 1351, | |
| MMX_PMULLWirr = 1352, | |
| MMX_PMULUDQirm = 1353, | |
| MMX_PMULUDQirr = 1354, | |
| MMX_PORirm = 1355, | |
| MMX_PORirr = 1356, | |
| MMX_PSADBWirm = 1357, | |
| MMX_PSADBWirr = 1358, | |
| MMX_PSHUFBrm64 = 1359, | |
| MMX_PSHUFBrr64 = 1360, | |
| MMX_PSHUFWmi = 1361, | |
| MMX_PSHUFWri = 1362, | |
| MMX_PSIGNBrm64 = 1363, | |
| MMX_PSIGNBrr64 = 1364, | |
| MMX_PSIGNDrm64 = 1365, | |
| MMX_PSIGNDrr64 = 1366, | |
| MMX_PSIGNWrm64 = 1367, | |
| MMX_PSIGNWrr64 = 1368, | |
| MMX_PSLLDri = 1369, | |
| MMX_PSLLDrm = 1370, | |
| MMX_PSLLDrr = 1371, | |
| MMX_PSLLQri = 1372, | |
| MMX_PSLLQrm = 1373, | |
| MMX_PSLLQrr = 1374, | |
| MMX_PSLLWri = 1375, | |
| MMX_PSLLWrm = 1376, | |
| MMX_PSLLWrr = 1377, | |
| MMX_PSRADri = 1378, | |
| MMX_PSRADrm = 1379, | |
| MMX_PSRADrr = 1380, | |
| MMX_PSRAWri = 1381, | |
| MMX_PSRAWrm = 1382, | |
| MMX_PSRAWrr = 1383, | |
| MMX_PSRLDri = 1384, | |
| MMX_PSRLDrm = 1385, | |
| MMX_PSRLDrr = 1386, | |
| MMX_PSRLQri = 1387, | |
| MMX_PSRLQrm = 1388, | |
| MMX_PSRLQrr = 1389, | |
| MMX_PSRLWri = 1390, | |
| MMX_PSRLWrm = 1391, | |
| MMX_PSRLWrr = 1392, | |
| MMX_PSUBBirm = 1393, | |
| MMX_PSUBBirr = 1394, | |
| MMX_PSUBDirm = 1395, | |
| MMX_PSUBDirr = 1396, | |
| MMX_PSUBQirm = 1397, | |
| MMX_PSUBQirr = 1398, | |
| MMX_PSUBSBirm = 1399, | |
| MMX_PSUBSBirr = 1400, | |
| MMX_PSUBSWirm = 1401, | |
| MMX_PSUBSWirr = 1402, | |
| MMX_PSUBUSBirm = 1403, | |
| MMX_PSUBUSBirr = 1404, | |
| MMX_PSUBUSWirm = 1405, | |
| MMX_PSUBUSWirr = 1406, | |
| MMX_PSUBWirm = 1407, | |
| MMX_PSUBWirr = 1408, | |
| MMX_PUNPCKHBWirm = 1409, | |
| MMX_PUNPCKHBWirr = 1410, | |
| MMX_PUNPCKHDQirm = 1411, | |
| MMX_PUNPCKHDQirr = 1412, | |
| MMX_PUNPCKHWDirm = 1413, | |
| MMX_PUNPCKHWDirr = 1414, | |
| MMX_PUNPCKLBWirm = 1415, | |
| MMX_PUNPCKLBWirr = 1416, | |
| MMX_PUNPCKLDQirm = 1417, | |
| MMX_PUNPCKLDQirr = 1418, | |
| MMX_PUNPCKLWDirm = 1419, | |
| MMX_PUNPCKLWDirr = 1420, | |
| MMX_PXORirm = 1421, | |
| MMX_PXORirr = 1422, | |
| MONITOR = 1423, | |
| MONITORrrr = 1424, | |
| MONTMUL = 1425, | |
| MOV16ao16 = 1426, | |
| MOV16mi = 1427, | |
| MOV16mr = 1428, | |
| MOV16ms = 1429, | |
| MOV16o16a = 1430, | |
| MOV16r0 = 1431, | |
| MOV16ri = 1432, | |
| MOV16rm = 1433, | |
| MOV16rr = 1434, | |
| MOV16rr_REV = 1435, | |
| MOV16rs = 1436, | |
| MOV16sm = 1437, | |
| MOV16sr = 1438, | |
| MOV32ao32 = 1439, | |
| MOV32cr = 1440, | |
| MOV32dr = 1441, | |
| MOV32mi = 1442, | |
| MOV32mr = 1443, | |
| MOV32ms = 1444, | |
| MOV32o32a = 1445, | |
| MOV32r0 = 1446, | |
| MOV32rc = 1447, | |
| MOV32rd = 1448, | |
| MOV32ri = 1449, | |
| MOV32rm = 1450, | |
| MOV32rr = 1451, | |
| MOV32rr_REV = 1452, | |
| MOV32rs = 1453, | |
| MOV32sm = 1454, | |
| MOV32sr = 1455, | |
| MOV64cr = 1456, | |
| MOV64dr = 1457, | |
| MOV64mi32 = 1458, | |
| MOV64mr = 1459, | |
| MOV64ms = 1460, | |
| MOV64r0 = 1461, | |
| MOV64rc = 1462, | |
| MOV64rd = 1463, | |
| MOV64ri = 1464, | |
| MOV64ri32 = 1465, | |
| MOV64ri64i32 = 1466, | |
| MOV64rm = 1467, | |
| MOV64rr = 1468, | |
| MOV64rr_REV = 1469, | |
| MOV64rs = 1470, | |
| MOV64sm = 1471, | |
| MOV64sr = 1472, | |
| MOV64toPQIrr = 1473, | |
| MOV64toSDrm = 1474, | |
| MOV64toSDrr = 1475, | |
| MOV8ao8 = 1476, | |
| MOV8mi = 1477, | |
| MOV8mr = 1478, | |
| MOV8mr_NOREX = 1479, | |
| MOV8o8a = 1480, | |
| MOV8r0 = 1481, | |
| MOV8ri = 1482, | |
| MOV8rm = 1483, | |
| MOV8rm_NOREX = 1484, | |
| MOV8rr = 1485, | |
| MOV8rr_NOREX = 1486, | |
| MOV8rr_REV = 1487, | |
| MOVAPDmr = 1488, | |
| MOVAPDrm = 1489, | |
| MOVAPDrr = 1490, | |
| MOVAPDrr_REV = 1491, | |
| MOVAPSmr = 1492, | |
| MOVAPSrm = 1493, | |
| MOVAPSrr = 1494, | |
| MOVAPSrr_REV = 1495, | |
| MOVBE16mr = 1496, | |
| MOVBE16rm = 1497, | |
| MOVBE32mr = 1498, | |
| MOVBE32rm = 1499, | |
| MOVBE64mr = 1500, | |
| MOVBE64rm = 1501, | |
| MOVDDUPrm = 1502, | |
| MOVDDUPrr = 1503, | |
| MOVDI2PDIrm = 1504, | |
| MOVDI2PDIrr = 1505, | |
| MOVDI2SSrm = 1506, | |
| MOVDI2SSrr = 1507, | |
| MOVDQAmr = 1508, | |
| MOVDQArm = 1509, | |
| MOVDQArr = 1510, | |
| MOVDQArr_REV = 1511, | |
| MOVDQUmr = 1512, | |
| MOVDQUmr_Int = 1513, | |
| MOVDQUrm = 1514, | |
| MOVDQUrr = 1515, | |
| MOVDQUrr_REV = 1516, | |
| MOVHLPSrr = 1517, | |
| MOVHPDmr = 1518, | |
| MOVHPDrm = 1519, | |
| MOVHPSmr = 1520, | |
| MOVHPSrm = 1521, | |
| MOVLHPSrr = 1522, | |
| MOVLPDmr = 1523, | |
| MOVLPDrm = 1524, | |
| MOVLPSmr = 1525, | |
| MOVLPSrm = 1526, | |
| MOVLQ128mr = 1527, | |
| MOVMSKPDrr32 = 1528, | |
| MOVMSKPDrr64 = 1529, | |
| MOVMSKPSrr32 = 1530, | |
| MOVMSKPSrr64 = 1531, | |
| MOVNTDQArm = 1532, | |
| MOVNTDQ_64mr = 1533, | |
| MOVNTDQmr = 1534, | |
| MOVNTI_64mr = 1535, | |
| MOVNTImr = 1536, | |
| MOVNTPDmr = 1537, | |
| MOVNTPSmr = 1538, | |
| MOVPC32r = 1539, | |
| MOVPDI2DImr = 1540, | |
| MOVPDI2DIrr = 1541, | |
| MOVPQI2QImr = 1542, | |
| MOVPQIto64rr = 1543, | |
| MOVQI2PQIrm = 1544, | |
| MOVQxrxr = 1545, | |
| MOVSB = 1546, | |
| MOVSD = 1547, | |
| MOVSDmr = 1548, | |
| MOVSDrm = 1549, | |
| MOVSDrr = 1550, | |
| MOVSDrr_REV = 1551, | |
| MOVSDto64mr = 1552, | |
| MOVSDto64rr = 1553, | |
| MOVSHDUPrm = 1554, | |
| MOVSHDUPrr = 1555, | |
| MOVSLDUPrm = 1556, | |
| MOVSLDUPrr = 1557, | |
| MOVSQ = 1558, | |
| MOVSS2DImr = 1559, | |
| MOVSS2DIrr = 1560, | |
| MOVSSmr = 1561, | |
| MOVSSrm = 1562, | |
| MOVSSrr = 1563, | |
| MOVSSrr_REV = 1564, | |
| MOVSW = 1565, | |
| MOVSX16rm8 = 1566, | |
| MOVSX16rr8 = 1567, | |
| MOVSX32rm16 = 1568, | |
| MOVSX32rm8 = 1569, | |
| MOVSX32rr16 = 1570, | |
| MOVSX32rr8 = 1571, | |
| MOVSX64rm16 = 1572, | |
| MOVSX64rm32 = 1573, | |
| MOVSX64rm8 = 1574, | |
| MOVSX64rr16 = 1575, | |
| MOVSX64rr32 = 1576, | |
| MOVSX64rr8 = 1577, | |
| MOVUPDmr = 1578, | |
| MOVUPDrm = 1579, | |
| MOVUPDrr = 1580, | |
| MOVUPDrr_REV = 1581, | |
| MOVUPSmr = 1582, | |
| MOVUPSrm = 1583, | |
| MOVUPSrr = 1584, | |
| MOVUPSrr_REV = 1585, | |
| MOVZDI2PDIrm = 1586, | |
| MOVZDI2PDIrr = 1587, | |
| MOVZPQILo2PQIrm = 1588, | |
| MOVZPQILo2PQIrr = 1589, | |
| MOVZQI2PQIrm = 1590, | |
| MOVZQI2PQIrr = 1591, | |
| MOVZX16rm8 = 1592, | |
| MOVZX16rr8 = 1593, | |
| MOVZX32_NOREXrm8 = 1594, | |
| MOVZX32_NOREXrr8 = 1595, | |
| MOVZX32rm16 = 1596, | |
| MOVZX32rm8 = 1597, | |
| MOVZX32rr16 = 1598, | |
| MOVZX32rr8 = 1599, | |
| MOVZX64rm16 = 1600, | |
| MOVZX64rm16_Q = 1601, | |
| MOVZX64rm32 = 1602, | |
| MOVZX64rm8 = 1603, | |
| MOVZX64rm8_Q = 1604, | |
| MOVZX64rr16 = 1605, | |
| MOVZX64rr16_Q = 1606, | |
| MOVZX64rr32 = 1607, | |
| MOVZX64rr8 = 1608, | |
| MOVZX64rr8_Q = 1609, | |
| MPSADBWrmi = 1610, | |
| MPSADBWrri = 1611, | |
| MUL16m = 1612, | |
| MUL16r = 1613, | |
| MUL32m = 1614, | |
| MUL32r = 1615, | |
| MUL64m = 1616, | |
| MUL64r = 1617, | |
| MUL8m = 1618, | |
| MUL8r = 1619, | |
| MULPDrm = 1620, | |
| MULPDrr = 1621, | |
| MULPSrm = 1622, | |
| MULPSrr = 1623, | |
| MULSDrm = 1624, | |
| MULSDrm_Int = 1625, | |
| MULSDrr = 1626, | |
| MULSDrr_Int = 1627, | |
| MULSSrm = 1628, | |
| MULSSrm_Int = 1629, | |
| MULSSrr = 1630, | |
| MULSSrr_Int = 1631, | |
| MUL_F32m = 1632, | |
| MUL_F64m = 1633, | |
| MUL_FI16m = 1634, | |
| MUL_FI32m = 1635, | |
| MUL_FPrST0 = 1636, | |
| MUL_FST0r = 1637, | |
| MUL_Fp32 = 1638, | |
| MUL_Fp32m = 1639, | |
| MUL_Fp64 = 1640, | |
| MUL_Fp64m = 1641, | |
| MUL_Fp64m32 = 1642, | |
| MUL_Fp80 = 1643, | |
| MUL_Fp80m32 = 1644, | |
| MUL_Fp80m64 = 1645, | |
| MUL_FpI16m32 = 1646, | |
| MUL_FpI16m64 = 1647, | |
| MUL_FpI16m80 = 1648, | |
| MUL_FpI32m32 = 1649, | |
| MUL_FpI32m64 = 1650, | |
| MUL_FpI32m80 = 1651, | |
| MUL_FrST0 = 1652, | |
| MWAIT = 1653, | |
| MWAITrr = 1654, | |
| NEG16m = 1655, | |
| NEG16r = 1656, | |
| NEG32m = 1657, | |
| NEG32r = 1658, | |
| NEG64m = 1659, | |
| NEG64r = 1660, | |
| NEG8m = 1661, | |
| NEG8r = 1662, | |
| NOOP = 1663, | |
| NOOPL = 1664, | |
| NOOPW = 1665, | |
| NOT16m = 1666, | |
| NOT16r = 1667, | |
| NOT32m = 1668, | |
| NOT32r = 1669, | |
| NOT64m = 1670, | |
| NOT64r = 1671, | |
| NOT8m = 1672, | |
| NOT8r = 1673, | |
| OR16i16 = 1674, | |
| OR16mi = 1675, | |
| OR16mi8 = 1676, | |
| OR16mr = 1677, | |
| OR16ri = 1678, | |
| OR16ri8 = 1679, | |
| OR16rm = 1680, | |
| OR16rr = 1681, | |
| OR16rr_REV = 1682, | |
| OR32i32 = 1683, | |
| OR32mi = 1684, | |
| OR32mi8 = 1685, | |
| OR32mr = 1686, | |
| OR32mrLocked = 1687, | |
| OR32ri = 1688, | |
| OR32ri8 = 1689, | |
| OR32rm = 1690, | |
| OR32rr = 1691, | |
| OR32rr_REV = 1692, | |
| OR64i32 = 1693, | |
| OR64mi32 = 1694, | |
| OR64mi8 = 1695, | |
| OR64mr = 1696, | |
| OR64ri32 = 1697, | |
| OR64ri8 = 1698, | |
| OR64rm = 1699, | |
| OR64rr = 1700, | |
| OR64rr_REV = 1701, | |
| OR8i8 = 1702, | |
| OR8mi = 1703, | |
| OR8mr = 1704, | |
| OR8ri = 1705, | |
| OR8rm = 1706, | |
| OR8rr = 1707, | |
| OR8rr_REV = 1708, | |
| ORPDrm = 1709, | |
| ORPDrr = 1710, | |
| ORPSrm = 1711, | |
| ORPSrr = 1712, | |
| OUT16ir = 1713, | |
| OUT16rr = 1714, | |
| OUT32ir = 1715, | |
| OUT32rr = 1716, | |
| OUT8ir = 1717, | |
| OUT8rr = 1718, | |
| OUTSB = 1719, | |
| OUTSD = 1720, | |
| OUTSW = 1721, | |
| PABSBrm128 = 1722, | |
| PABSBrr128 = 1723, | |
| PABSDrm128 = 1724, | |
| PABSDrr128 = 1725, | |
| PABSWrm128 = 1726, | |
| PABSWrr128 = 1727, | |
| PACKSSDWrm = 1728, | |
| PACKSSDWrr = 1729, | |
| PACKSSWBrm = 1730, | |
| PACKSSWBrr = 1731, | |
| PACKUSDWrm = 1732, | |
| PACKUSDWrr = 1733, | |
| PACKUSWBrm = 1734, | |
| PACKUSWBrr = 1735, | |
| PADDBrm = 1736, | |
| PADDBrr = 1737, | |
| PADDDrm = 1738, | |
| PADDDrr = 1739, | |
| PADDQrm = 1740, | |
| PADDQrr = 1741, | |
| PADDSBrm = 1742, | |
| PADDSBrr = 1743, | |
| PADDSWrm = 1744, | |
| PADDSWrr = 1745, | |
| PADDUSBrm = 1746, | |
| PADDUSBrr = 1747, | |
| PADDUSWrm = 1748, | |
| PADDUSWrr = 1749, | |
| PADDWrm = 1750, | |
| PADDWrr = 1751, | |
| PALIGNR128rm = 1752, | |
| PALIGNR128rr = 1753, | |
| PANDNrm = 1754, | |
| PANDNrr = 1755, | |
| PANDrm = 1756, | |
| PANDrr = 1757, | |
| PAUSE = 1758, | |
| PAVGBrm = 1759, | |
| PAVGBrr = 1760, | |
| PAVGUSBrm = 1761, | |
| PAVGUSBrr = 1762, | |
| PAVGWrm = 1763, | |
| PAVGWrr = 1764, | |
| PBLENDVBrm0 = 1765, | |
| PBLENDVBrr0 = 1766, | |
| PBLENDWrmi = 1767, | |
| PBLENDWrri = 1768, | |
| PCLMULQDQrm = 1769, | |
| PCLMULQDQrr = 1770, | |
| PCMPEQBrm = 1771, | |
| PCMPEQBrr = 1772, | |
| PCMPEQDrm = 1773, | |
| PCMPEQDrr = 1774, | |
| PCMPEQQrm = 1775, | |
| PCMPEQQrr = 1776, | |
| PCMPEQWrm = 1777, | |
| PCMPEQWrr = 1778, | |
| PCMPESTRIArm = 1779, | |
| PCMPESTRIArr = 1780, | |
| PCMPESTRICrm = 1781, | |
| PCMPESTRICrr = 1782, | |
| PCMPESTRIOrm = 1783, | |
| PCMPESTRIOrr = 1784, | |
| PCMPESTRISrm = 1785, | |
| PCMPESTRISrr = 1786, | |
| PCMPESTRIZrm = 1787, | |
| PCMPESTRIZrr = 1788, | |
| PCMPESTRIrm = 1789, | |
| PCMPESTRIrr = 1790, | |
| PCMPESTRM128MEM = 1791, | |
| PCMPESTRM128REG = 1792, | |
| PCMPESTRM128rm = 1793, | |
| PCMPESTRM128rr = 1794, | |
| PCMPGTBrm = 1795, | |
| PCMPGTBrr = 1796, | |
| PCMPGTDrm = 1797, | |
| PCMPGTDrr = 1798, | |
| PCMPGTQrm = 1799, | |
| PCMPGTQrr = 1800, | |
| PCMPGTWrm = 1801, | |
| PCMPGTWrr = 1802, | |
| PCMPISTRIArm = 1803, | |
| PCMPISTRIArr = 1804, | |
| PCMPISTRICrm = 1805, | |
| PCMPISTRICrr = 1806, | |
| PCMPISTRIOrm = 1807, | |
| PCMPISTRIOrr = 1808, | |
| PCMPISTRISrm = 1809, | |
| PCMPISTRISrr = 1810, | |
| PCMPISTRIZrm = 1811, | |
| PCMPISTRIZrr = 1812, | |
| PCMPISTRIrm = 1813, | |
| PCMPISTRIrr = 1814, | |
| PCMPISTRM128MEM = 1815, | |
| PCMPISTRM128REG = 1816, | |
| PCMPISTRM128rm = 1817, | |
| PCMPISTRM128rr = 1818, | |
| PEXTRBmr = 1819, | |
| PEXTRBrr = 1820, | |
| PEXTRDmr = 1821, | |
| PEXTRDrr = 1822, | |
| PEXTRQmr = 1823, | |
| PEXTRQrr = 1824, | |
| PEXTRWmr = 1825, | |
| PEXTRWri = 1826, | |
| PF2IDrm = 1827, | |
| PF2IDrr = 1828, | |
| PF2IWrm = 1829, | |
| PF2IWrr = 1830, | |
| PFACCrm = 1831, | |
| PFACCrr = 1832, | |
| PFADDrm = 1833, | |
| PFADDrr = 1834, | |
| PFCMPEQrm = 1835, | |
| PFCMPEQrr = 1836, | |
| PFCMPGErm = 1837, | |
| PFCMPGErr = 1838, | |
| PFCMPGTrm = 1839, | |
| PFCMPGTrr = 1840, | |
| PFMAXrm = 1841, | |
| PFMAXrr = 1842, | |
| PFMINrm = 1843, | |
| PFMINrr = 1844, | |
| PFMULrm = 1845, | |
| PFMULrr = 1846, | |
| PFNACCrm = 1847, | |
| PFNACCrr = 1848, | |
| PFPNACCrm = 1849, | |
| PFPNACCrr = 1850, | |
| PFRCPIT1rm = 1851, | |
| PFRCPIT1rr = 1852, | |
| PFRCPIT2rm = 1853, | |
| PFRCPIT2rr = 1854, | |
| PFRCPrm = 1855, | |
| PFRCPrr = 1856, | |
| PFRSQIT1rm = 1857, | |
| PFRSQIT1rr = 1858, | |
| PFRSQRTrm = 1859, | |
| PFRSQRTrr = 1860, | |
| PFSUBRrm = 1861, | |
| PFSUBRrr = 1862, | |
| PFSUBrm = 1863, | |
| PFSUBrr = 1864, | |
| PHADDDrm128 = 1865, | |
| PHADDDrr128 = 1866, | |
| PHADDSWrm128 = 1867, | |
| PHADDSWrr128 = 1868, | |
| PHADDWrm128 = 1869, | |
| PHADDWrr128 = 1870, | |
| PHMINPOSUWrm128 = 1871, | |
| PHMINPOSUWrr128 = 1872, | |
| PHSUBDrm128 = 1873, | |
| PHSUBDrr128 = 1874, | |
| PHSUBSWrm128 = 1875, | |
| PHSUBSWrr128 = 1876, | |
| PHSUBWrm128 = 1877, | |
| PHSUBWrr128 = 1878, | |
| PI2FDrm = 1879, | |
| PI2FDrr = 1880, | |
| PI2FWrm = 1881, | |
| PI2FWrr = 1882, | |
| PINSRBrm = 1883, | |
| PINSRBrr = 1884, | |
| PINSRDrm = 1885, | |
| PINSRDrr = 1886, | |
| PINSRQrm = 1887, | |
| PINSRQrr = 1888, | |
| PINSRWrmi = 1889, | |
| PINSRWrri = 1890, | |
| PMADDUBSWrm128 = 1891, | |
| PMADDUBSWrr128 = 1892, | |
| PMADDWDrm = 1893, | |
| PMADDWDrr = 1894, | |
| PMAXSBrm = 1895, | |
| PMAXSBrr = 1896, | |
| PMAXSDrm = 1897, | |
| PMAXSDrr = 1898, | |
| PMAXSWrm = 1899, | |
| PMAXSWrr = 1900, | |
| PMAXUBrm = 1901, | |
| PMAXUBrr = 1902, | |
| PMAXUDrm = 1903, | |
| PMAXUDrr = 1904, | |
| PMAXUWrm = 1905, | |
| PMAXUWrr = 1906, | |
| PMINSBrm = 1907, | |
| PMINSBrr = 1908, | |
| PMINSDrm = 1909, | |
| PMINSDrr = 1910, | |
| PMINSWrm = 1911, | |
| PMINSWrr = 1912, | |
| PMINUBrm = 1913, | |
| PMINUBrr = 1914, | |
| PMINUDrm = 1915, | |
| PMINUDrr = 1916, | |
| PMINUWrm = 1917, | |
| PMINUWrr = 1918, | |
| PMOVMSKBrr = 1919, | |
| PMOVSXBDrm = 1920, | |
| PMOVSXBDrr = 1921, | |
| PMOVSXBQrm = 1922, | |
| PMOVSXBQrr = 1923, | |
| PMOVSXBWrm = 1924, | |
| PMOVSXBWrr = 1925, | |
| PMOVSXDQrm = 1926, | |
| PMOVSXDQrr = 1927, | |
| PMOVSXWDrm = 1928, | |
| PMOVSXWDrr = 1929, | |
| PMOVSXWQrm = 1930, | |
| PMOVSXWQrr = 1931, | |
| PMOVZXBDrm = 1932, | |
| PMOVZXBDrr = 1933, | |
| PMOVZXBQrm = 1934, | |
| PMOVZXBQrr = 1935, | |
| PMOVZXBWrm = 1936, | |
| PMOVZXBWrr = 1937, | |
| PMOVZXDQrm = 1938, | |
| PMOVZXDQrr = 1939, | |
| PMOVZXWDrm = 1940, | |
| PMOVZXWDrr = 1941, | |
| PMOVZXWQrm = 1942, | |
| PMOVZXWQrr = 1943, | |
| PMULDQrm = 1944, | |
| PMULDQrr = 1945, | |
| PMULHRSWrm128 = 1946, | |
| PMULHRSWrr128 = 1947, | |
| PMULHRWrm = 1948, | |
| PMULHRWrr = 1949, | |
| PMULHUWrm = 1950, | |
| PMULHUWrr = 1951, | |
| PMULHWrm = 1952, | |
| PMULHWrr = 1953, | |
| PMULLDrm = 1954, | |
| PMULLDrr = 1955, | |
| PMULLWrm = 1956, | |
| PMULLWrr = 1957, | |
| PMULUDQrm = 1958, | |
| PMULUDQrr = 1959, | |
| POP16r = 1960, | |
| POP16rmm = 1961, | |
| POP16rmr = 1962, | |
| POP32r = 1963, | |
| POP32rmm = 1964, | |
| POP32rmr = 1965, | |
| POP64r = 1966, | |
| POP64rmm = 1967, | |
| POP64rmr = 1968, | |
| POPA32 = 1969, | |
| POPCNT16rm = 1970, | |
| POPCNT16rr = 1971, | |
| POPCNT32rm = 1972, | |
| POPCNT32rr = 1973, | |
| POPCNT64rm = 1974, | |
| POPCNT64rr = 1975, | |
| POPDS16 = 1976, | |
| POPDS32 = 1977, | |
| POPES16 = 1978, | |
| POPES32 = 1979, | |
| POPF16 = 1980, | |
| POPF32 = 1981, | |
| POPF64 = 1982, | |
| POPFS16 = 1983, | |
| POPFS32 = 1984, | |
| POPFS64 = 1985, | |
| POPGS16 = 1986, | |
| POPGS32 = 1987, | |
| POPGS64 = 1988, | |
| POPSS16 = 1989, | |
| POPSS32 = 1990, | |
| PORrm = 1991, | |
| PORrr = 1992, | |
| PREFETCH = 1993, | |
| PREFETCHNTA = 1994, | |
| PREFETCHT0 = 1995, | |
| PREFETCHT1 = 1996, | |
| PREFETCHT2 = 1997, | |
| PREFETCHW = 1998, | |
| PSADBWrm = 1999, | |
| PSADBWrr = 2000, | |
| PSHUFBrm128 = 2001, | |
| PSHUFBrr128 = 2002, | |
| PSHUFDmi = 2003, | |
| PSHUFDri = 2004, | |
| PSHUFHWmi = 2005, | |
| PSHUFHWri = 2006, | |
| PSHUFLWmi = 2007, | |
| PSHUFLWri = 2008, | |
| PSIGNBrm128 = 2009, | |
| PSIGNBrr128 = 2010, | |
| PSIGNDrm128 = 2011, | |
| PSIGNDrr128 = 2012, | |
| PSIGNWrm128 = 2013, | |
| PSIGNWrr128 = 2014, | |
| PSLLDQri = 2015, | |
| PSLLDri = 2016, | |
| PSLLDrm = 2017, | |
| PSLLDrr = 2018, | |
| PSLLQri = 2019, | |
| PSLLQrm = 2020, | |
| PSLLQrr = 2021, | |
| PSLLWri = 2022, | |
| PSLLWrm = 2023, | |
| PSLLWrr = 2024, | |
| PSRADri = 2025, | |
| PSRADrm = 2026, | |
| PSRADrr = 2027, | |
| PSRAWri = 2028, | |
| PSRAWrm = 2029, | |
| PSRAWrr = 2030, | |
| PSRLDQri = 2031, | |
| PSRLDri = 2032, | |
| PSRLDrm = 2033, | |
| PSRLDrr = 2034, | |
| PSRLQri = 2035, | |
| PSRLQrm = 2036, | |
| PSRLQrr = 2037, | |
| PSRLWri = 2038, | |
| PSRLWrm = 2039, | |
| PSRLWrr = 2040, | |
| PSUBBrm = 2041, | |
| PSUBBrr = 2042, | |
| PSUBDrm = 2043, | |
| PSUBDrr = 2044, | |
| PSUBQrm = 2045, | |
| PSUBQrr = 2046, | |
| PSUBSBrm = 2047, | |
| PSUBSBrr = 2048, | |
| PSUBSWrm = 2049, | |
| PSUBSWrr = 2050, | |
| PSUBUSBrm = 2051, | |
| PSUBUSBrr = 2052, | |
| PSUBUSWrm = 2053, | |
| PSUBUSWrr = 2054, | |
| PSUBWrm = 2055, | |
| PSUBWrr = 2056, | |
| PSWAPDrm = 2057, | |
| PSWAPDrr = 2058, | |
| PTESTrm = 2059, | |
| PTESTrr = 2060, | |
| PUNPCKHBWrm = 2061, | |
| PUNPCKHBWrr = 2062, | |
| PUNPCKHDQrm = 2063, | |
| PUNPCKHDQrr = 2064, | |
| PUNPCKHQDQrm = 2065, | |
| PUNPCKHQDQrr = 2066, | |
| PUNPCKHWDrm = 2067, | |
| PUNPCKHWDrr = 2068, | |
| PUNPCKLBWrm = 2069, | |
| PUNPCKLBWrr = 2070, | |
| PUNPCKLDQrm = 2071, | |
| PUNPCKLDQrr = 2072, | |
| PUNPCKLQDQrm = 2073, | |
| PUNPCKLQDQrr = 2074, | |
| PUNPCKLWDrm = 2075, | |
| PUNPCKLWDrr = 2076, | |
| PUSH16r = 2077, | |
| PUSH16rmm = 2078, | |
| PUSH16rmr = 2079, | |
| PUSH32r = 2080, | |
| PUSH32rmm = 2081, | |
| PUSH32rmr = 2082, | |
| PUSH64i16 = 2083, | |
| PUSH64i32 = 2084, | |
| PUSH64i8 = 2085, | |
| PUSH64r = 2086, | |
| PUSH64rmm = 2087, | |
| PUSH64rmr = 2088, | |
| PUSHA32 = 2089, | |
| PUSHCS16 = 2090, | |
| PUSHCS32 = 2091, | |
| PUSHDS16 = 2092, | |
| PUSHDS32 = 2093, | |
| PUSHES16 = 2094, | |
| PUSHES32 = 2095, | |
| PUSHF16 = 2096, | |
| PUSHF32 = 2097, | |
| PUSHF64 = 2098, | |
| PUSHFS16 = 2099, | |
| PUSHFS32 = 2100, | |
| PUSHFS64 = 2101, | |
| PUSHGS16 = 2102, | |
| PUSHGS32 = 2103, | |
| PUSHGS64 = 2104, | |
| PUSHSS16 = 2105, | |
| PUSHSS32 = 2106, | |
| PUSHi16 = 2107, | |
| PUSHi32 = 2108, | |
| PUSHi8 = 2109, | |
| PXORrm = 2110, | |
| PXORrr = 2111, | |
| RCL16m1 = 2112, | |
| RCL16mCL = 2113, | |
| RCL16mi = 2114, | |
| RCL16r1 = 2115, | |
| RCL16rCL = 2116, | |
| RCL16ri = 2117, | |
| RCL32m1 = 2118, | |
| RCL32mCL = 2119, | |
| RCL32mi = 2120, | |
| RCL32r1 = 2121, | |
| RCL32rCL = 2122, | |
| RCL32ri = 2123, | |
| RCL64m1 = 2124, | |
| RCL64mCL = 2125, | |
| RCL64mi = 2126, | |
| RCL64r1 = 2127, | |
| RCL64rCL = 2128, | |
| RCL64ri = 2129, | |
| RCL8m1 = 2130, | |
| RCL8mCL = 2131, | |
| RCL8mi = 2132, | |
| RCL8r1 = 2133, | |
| RCL8rCL = 2134, | |
| RCL8ri = 2135, | |
| RCPPSm = 2136, | |
| RCPPSm_Int = 2137, | |
| RCPPSr = 2138, | |
| RCPPSr_Int = 2139, | |
| RCPSSm = 2140, | |
| RCPSSm_Int = 2141, | |
| RCPSSr = 2142, | |
| RCPSSr_Int = 2143, | |
| RCR16m1 = 2144, | |
| RCR16mCL = 2145, | |
| RCR16mi = 2146, | |
| RCR16r1 = 2147, | |
| RCR16rCL = 2148, | |
| RCR16ri = 2149, | |
| RCR32m1 = 2150, | |
| RCR32mCL = 2151, | |
| RCR32mi = 2152, | |
| RCR32r1 = 2153, | |
| RCR32rCL = 2154, | |
| RCR32ri = 2155, | |
| RCR64m1 = 2156, | |
| RCR64mCL = 2157, | |
| RCR64mi = 2158, | |
| RCR64r1 = 2159, | |
| RCR64rCL = 2160, | |
| RCR64ri = 2161, | |
| RCR8m1 = 2162, | |
| RCR8mCL = 2163, | |
| RCR8mi = 2164, | |
| RCR8r1 = 2165, | |
| RCR8rCL = 2166, | |
| RCR8ri = 2167, | |
| RDFSBASE = 2168, | |
| RDFSBASE64 = 2169, | |
| RDGSBASE = 2170, | |
| RDGSBASE64 = 2171, | |
| RDMSR = 2172, | |
| RDPMC = 2173, | |
| RDRAND16r = 2174, | |
| RDRAND32r = 2175, | |
| RDRAND64r = 2176, | |
| RDTSC = 2177, | |
| RDTSCP = 2178, | |
| RELEASE_MOV16mr = 2179, | |
| RELEASE_MOV32mr = 2180, | |
| RELEASE_MOV64mr = 2181, | |
| RELEASE_MOV8mr = 2182, | |
| REPNE_PREFIX = 2183, | |
| REP_MOVSB = 2184, | |
| REP_MOVSD = 2185, | |
| REP_MOVSQ = 2186, | |
| REP_MOVSW = 2187, | |
| REP_PREFIX = 2188, | |
| REP_STOSB = 2189, | |
| REP_STOSD = 2190, | |
| REP_STOSQ = 2191, | |
| REP_STOSW = 2192, | |
| RET = 2193, | |
| RETI = 2194, | |
| RETIW = 2195, | |
| REX64_PREFIX = 2196, | |
| ROL16m1 = 2197, | |
| ROL16mCL = 2198, | |
| ROL16mi = 2199, | |
| ROL16r1 = 2200, | |
| ROL16rCL = 2201, | |
| ROL16ri = 2202, | |
| ROL32m1 = 2203, | |
| ROL32mCL = 2204, | |
| ROL32mi = 2205, | |
| ROL32r1 = 2206, | |
| ROL32rCL = 2207, | |
| ROL32ri = 2208, | |
| ROL64m1 = 2209, | |
| ROL64mCL = 2210, | |
| ROL64mi = 2211, | |
| ROL64r1 = 2212, | |
| ROL64rCL = 2213, | |
| ROL64ri = 2214, | |
| ROL8m1 = 2215, | |
| ROL8mCL = 2216, | |
| ROL8mi = 2217, | |
| ROL8r1 = 2218, | |
| ROL8rCL = 2219, | |
| ROL8ri = 2220, | |
| ROR16m1 = 2221, | |
| ROR16mCL = 2222, | |
| ROR16mi = 2223, | |
| ROR16r1 = 2224, | |
| ROR16rCL = 2225, | |
| ROR16ri = 2226, | |
| ROR32m1 = 2227, | |
| ROR32mCL = 2228, | |
| ROR32mi = 2229, | |
| ROR32r1 = 2230, | |
| ROR32rCL = 2231, | |
| ROR32ri = 2232, | |
| ROR64m1 = 2233, | |
| ROR64mCL = 2234, | |
| ROR64mi = 2235, | |
| ROR64r1 = 2236, | |
| ROR64rCL = 2237, | |
| ROR64ri = 2238, | |
| ROR8m1 = 2239, | |
| ROR8mCL = 2240, | |
| ROR8mi = 2241, | |
| ROR8r1 = 2242, | |
| ROR8rCL = 2243, | |
| ROR8ri = 2244, | |
| ROUNDPDm = 2245, | |
| ROUNDPDr = 2246, | |
| ROUNDPSm = 2247, | |
| ROUNDPSr = 2248, | |
| ROUNDSDm = 2249, | |
| ROUNDSDr = 2250, | |
| ROUNDSSm = 2251, | |
| ROUNDSSr = 2252, | |
| RSM = 2253, | |
| RSQRTPSm = 2254, | |
| RSQRTPSm_Int = 2255, | |
| RSQRTPSr = 2256, | |
| RSQRTPSr_Int = 2257, | |
| RSQRTSSm = 2258, | |
| RSQRTSSm_Int = 2259, | |
| RSQRTSSr = 2260, | |
| RSQRTSSr_Int = 2261, | |
| SAHF = 2262, | |
| SAR16m1 = 2263, | |
| SAR16mCL = 2264, | |
| SAR16mi = 2265, | |
| SAR16r1 = 2266, | |
| SAR16rCL = 2267, | |
| SAR16ri = 2268, | |
| SAR32m1 = 2269, | |
| SAR32mCL = 2270, | |
| SAR32mi = 2271, | |
| SAR32r1 = 2272, | |
| SAR32rCL = 2273, | |
| SAR32ri = 2274, | |
| SAR64m1 = 2275, | |
| SAR64mCL = 2276, | |
| SAR64mi = 2277, | |
| SAR64r1 = 2278, | |
| SAR64rCL = 2279, | |
| SAR64ri = 2280, | |
| SAR8m1 = 2281, | |
| SAR8mCL = 2282, | |
| SAR8mi = 2283, | |
| SAR8r1 = 2284, | |
| SAR8rCL = 2285, | |
| SAR8ri = 2286, | |
| SBB16i16 = 2287, | |
| SBB16mi = 2288, | |
| SBB16mi8 = 2289, | |
| SBB16mr = 2290, | |
| SBB16ri = 2291, | |
| SBB16ri8 = 2292, | |
| SBB16rm = 2293, | |
| SBB16rr = 2294, | |
| SBB16rr_REV = 2295, | |
| SBB32i32 = 2296, | |
| SBB32mi = 2297, | |
| SBB32mi8 = 2298, | |
| SBB32mr = 2299, | |
| SBB32ri = 2300, | |
| SBB32ri8 = 2301, | |
| SBB32rm = 2302, | |
| SBB32rr = 2303, | |
| SBB32rr_REV = 2304, | |
| SBB64i32 = 2305, | |
| SBB64mi32 = 2306, | |
| SBB64mi8 = 2307, | |
| SBB64mr = 2308, | |
| SBB64ri32 = 2309, | |
| SBB64ri8 = 2310, | |
| SBB64rm = 2311, | |
| SBB64rr = 2312, | |
| SBB64rr_REV = 2313, | |
| SBB8i8 = 2314, | |
| SBB8mi = 2315, | |
| SBB8mr = 2316, | |
| SBB8ri = 2317, | |
| SBB8rm = 2318, | |
| SBB8rr = 2319, | |
| SBB8rr_REV = 2320, | |
| SCAS16 = 2321, | |
| SCAS32 = 2322, | |
| SCAS64 = 2323, | |
| SCAS8 = 2324, | |
| SEG_ALLOCA_32 = 2325, | |
| SEG_ALLOCA_64 = 2326, | |
| SETAEm = 2327, | |
| SETAEr = 2328, | |
| SETAm = 2329, | |
| SETAr = 2330, | |
| SETBEm = 2331, | |
| SETBEr = 2332, | |
| SETB_C16r = 2333, | |
| SETB_C32r = 2334, | |
| SETB_C64r = 2335, | |
| SETB_C8r = 2336, | |
| SETBm = 2337, | |
| SETBr = 2338, | |
| SETEm = 2339, | |
| SETEr = 2340, | |
| SETGEm = 2341, | |
| SETGEr = 2342, | |
| SETGm = 2343, | |
| SETGr = 2344, | |
| SETLEm = 2345, | |
| SETLEr = 2346, | |
| SETLm = 2347, | |
| SETLr = 2348, | |
| SETNEm = 2349, | |
| SETNEr = 2350, | |
| SETNOm = 2351, | |
| SETNOr = 2352, | |
| SETNPm = 2353, | |
| SETNPr = 2354, | |
| SETNSm = 2355, | |
| SETNSr = 2356, | |
| SETOm = 2357, | |
| SETOr = 2358, | |
| SETPm = 2359, | |
| SETPr = 2360, | |
| SETSm = 2361, | |
| SETSr = 2362, | |
| SFENCE = 2363, | |
| SGDT16m = 2364, | |
| SGDTm = 2365, | |
| SHL16m1 = 2366, | |
| SHL16mCL = 2367, | |
| SHL16mi = 2368, | |
| SHL16r1 = 2369, | |
| SHL16rCL = 2370, | |
| SHL16ri = 2371, | |
| SHL32m1 = 2372, | |
| SHL32mCL = 2373, | |
| SHL32mi = 2374, | |
| SHL32r1 = 2375, | |
| SHL32rCL = 2376, | |
| SHL32ri = 2377, | |
| SHL64m1 = 2378, | |
| SHL64mCL = 2379, | |
| SHL64mi = 2380, | |
| SHL64r1 = 2381, | |
| SHL64rCL = 2382, | |
| SHL64ri = 2383, | |
| SHL8m1 = 2384, | |
| SHL8mCL = 2385, | |
| SHL8mi = 2386, | |
| SHL8r1 = 2387, | |
| SHL8rCL = 2388, | |
| SHL8ri = 2389, | |
| SHLD16mrCL = 2390, | |
| SHLD16mri8 = 2391, | |
| SHLD16rrCL = 2392, | |
| SHLD16rri8 = 2393, | |
| SHLD32mrCL = 2394, | |
| SHLD32mri8 = 2395, | |
| SHLD32rrCL = 2396, | |
| SHLD32rri8 = 2397, | |
| SHLD64mrCL = 2398, | |
| SHLD64mri8 = 2399, | |
| SHLD64rrCL = 2400, | |
| SHLD64rri8 = 2401, | |
| SHR16m1 = 2402, | |
| SHR16mCL = 2403, | |
| SHR16mi = 2404, | |
| SHR16r1 = 2405, | |
| SHR16rCL = 2406, | |
| SHR16ri = 2407, | |
| SHR32m1 = 2408, | |
| SHR32mCL = 2409, | |
| SHR32mi = 2410, | |
| SHR32r1 = 2411, | |
| SHR32rCL = 2412, | |
| SHR32ri = 2413, | |
| SHR64m1 = 2414, | |
| SHR64mCL = 2415, | |
| SHR64mi = 2416, | |
| SHR64r1 = 2417, | |
| SHR64rCL = 2418, | |
| SHR64ri = 2419, | |
| SHR8m1 = 2420, | |
| SHR8mCL = 2421, | |
| SHR8mi = 2422, | |
| SHR8r1 = 2423, | |
| SHR8rCL = 2424, | |
| SHR8ri = 2425, | |
| SHRD16mrCL = 2426, | |
| SHRD16mri8 = 2427, | |
| SHRD16rrCL = 2428, | |
| SHRD16rri8 = 2429, | |
| SHRD32mrCL = 2430, | |
| SHRD32mri8 = 2431, | |
| SHRD32rrCL = 2432, | |
| SHRD32rri8 = 2433, | |
| SHRD64mrCL = 2434, | |
| SHRD64mri8 = 2435, | |
| SHRD64rrCL = 2436, | |
| SHRD64rri8 = 2437, | |
| SHUFPDrmi = 2438, | |
| SHUFPDrri = 2439, | |
| SHUFPSrmi = 2440, | |
| SHUFPSrri = 2441, | |
| SIDT16m = 2442, | |
| SIDTm = 2443, | |
| SIN_F = 2444, | |
| SIN_Fp32 = 2445, | |
| SIN_Fp64 = 2446, | |
| SIN_Fp80 = 2447, | |
| SLDT16m = 2448, | |
| SLDT16r = 2449, | |
| SLDT32r = 2450, | |
| SLDT64m = 2451, | |
| SLDT64r = 2452, | |
| SMSW16m = 2453, | |
| SMSW16r = 2454, | |
| SMSW32r = 2455, | |
| SMSW64r = 2456, | |
| SQRTPDm = 2457, | |
| SQRTPDm_Int = 2458, | |
| SQRTPDr = 2459, | |
| SQRTPDr_Int = 2460, | |
| SQRTPSm = 2461, | |
| SQRTPSm_Int = 2462, | |
| SQRTPSr = 2463, | |
| SQRTPSr_Int = 2464, | |
| SQRTSDm = 2465, | |
| SQRTSDm_Int = 2466, | |
| SQRTSDr = 2467, | |
| SQRTSDr_Int = 2468, | |
| SQRTSSm = 2469, | |
| SQRTSSm_Int = 2470, | |
| SQRTSSr = 2471, | |
| SQRTSSr_Int = 2472, | |
| SQRT_F = 2473, | |
| SQRT_Fp32 = 2474, | |
| SQRT_Fp64 = 2475, | |
| SQRT_Fp80 = 2476, | |
| SS_PREFIX = 2477, | |
| STC = 2478, | |
| STD = 2479, | |
| STI = 2480, | |
| STMXCSR = 2481, | |
| STOSB = 2482, | |
| STOSD = 2483, | |
| STOSQ = 2484, | |
| STOSW = 2485, | |
| STR16r = 2486, | |
| STR32r = 2487, | |
| STR64r = 2488, | |
| STRm = 2489, | |
| ST_F32m = 2490, | |
| ST_F64m = 2491, | |
| ST_FP32m = 2492, | |
| ST_FP64m = 2493, | |
| ST_FP80m = 2494, | |
| ST_FPrr = 2495, | |
| ST_Fp32m = 2496, | |
| ST_Fp64m = 2497, | |
| ST_Fp64m32 = 2498, | |
| ST_Fp80m32 = 2499, | |
| ST_Fp80m64 = 2500, | |
| ST_FpP32m = 2501, | |
| ST_FpP64m = 2502, | |
| ST_FpP64m32 = 2503, | |
| ST_FpP80m = 2504, | |
| ST_FpP80m32 = 2505, | |
| ST_FpP80m64 = 2506, | |
| ST_Frr = 2507, | |
| SUB16i16 = 2508, | |
| SUB16mi = 2509, | |
| SUB16mi8 = 2510, | |
| SUB16mr = 2511, | |
| SUB16ri = 2512, | |
| SUB16ri8 = 2513, | |
| SUB16rm = 2514, | |
| SUB16rr = 2515, | |
| SUB16rr_REV = 2516, | |
| SUB32i32 = 2517, | |
| SUB32mi = 2518, | |
| SUB32mi8 = 2519, | |
| SUB32mr = 2520, | |
| SUB32ri = 2521, | |
| SUB32ri8 = 2522, | |
| SUB32rm = 2523, | |
| SUB32rr = 2524, | |
| SUB32rr_REV = 2525, | |
| SUB64i32 = 2526, | |
| SUB64mi32 = 2527, | |
| SUB64mi8 = 2528, | |
| SUB64mr = 2529, | |
| SUB64ri32 = 2530, | |
| SUB64ri8 = 2531, | |
| SUB64rm = 2532, | |
| SUB64rr = 2533, | |
| SUB64rr_REV = 2534, | |
| SUB8i8 = 2535, | |
| SUB8mi = 2536, | |
| SUB8mr = 2537, | |
| SUB8ri = 2538, | |
| SUB8rm = 2539, | |
| SUB8rr = 2540, | |
| SUB8rr_REV = 2541, | |
| SUBPDrm = 2542, | |
| SUBPDrr = 2543, | |
| SUBPSrm = 2544, | |
| SUBPSrr = 2545, | |
| SUBR_F32m = 2546, | |
| SUBR_F64m = 2547, | |
| SUBR_FI16m = 2548, | |
| SUBR_FI32m = 2549, | |
| SUBR_FPrST0 = 2550, | |
| SUBR_FST0r = 2551, | |
| SUBR_Fp32m = 2552, | |
| SUBR_Fp64m = 2553, | |
| SUBR_Fp64m32 = 2554, | |
| SUBR_Fp80m32 = 2555, | |
| SUBR_Fp80m64 = 2556, | |
| SUBR_FpI16m32 = 2557, | |
| SUBR_FpI16m64 = 2558, | |
| SUBR_FpI16m80 = 2559, | |
| SUBR_FpI32m32 = 2560, | |
| SUBR_FpI32m64 = 2561, | |
| SUBR_FpI32m80 = 2562, | |
| SUBR_FrST0 = 2563, | |
| SUBSDrm = 2564, | |
| SUBSDrm_Int = 2565, | |
| SUBSDrr = 2566, | |
| SUBSDrr_Int = 2567, | |
| SUBSSrm = 2568, | |
| SUBSSrm_Int = 2569, | |
| SUBSSrr = 2570, | |
| SUBSSrr_Int = 2571, | |
| SUB_F32m = 2572, | |
| SUB_F64m = 2573, | |
| SUB_FI16m = 2574, | |
| SUB_FI32m = 2575, | |
| SUB_FPrST0 = 2576, | |
| SUB_FST0r = 2577, | |
| SUB_Fp32 = 2578, | |
| SUB_Fp32m = 2579, | |
| SUB_Fp64 = 2580, | |
| SUB_Fp64m = 2581, | |
| SUB_Fp64m32 = 2582, | |
| SUB_Fp80 = 2583, | |
| SUB_Fp80m32 = 2584, | |
| SUB_Fp80m64 = 2585, | |
| SUB_FpI16m32 = 2586, | |
| SUB_FpI16m64 = 2587, | |
| SUB_FpI16m80 = 2588, | |
| SUB_FpI32m32 = 2589, | |
| SUB_FpI32m64 = 2590, | |
| SUB_FpI32m80 = 2591, | |
| SUB_FrST0 = 2592, | |
| SWAPGS = 2593, | |
| SYSCALL = 2594, | |
| SYSENTER = 2595, | |
| SYSEXIT = 2596, | |
| SYSEXIT64 = 2597, | |
| SYSRETL = 2598, | |
| SYSRETQ = 2599, | |
| TAILJMPd = 2600, | |
| TAILJMPd64 = 2601, | |
| TAILJMPm = 2602, | |
| TAILJMPm64 = 2603, | |
| TAILJMPr = 2604, | |
| TAILJMPr64 = 2605, | |
| TCRETURNdi = 2606, | |
| TCRETURNdi64 = 2607, | |
| TCRETURNmi = 2608, | |
| TCRETURNmi64 = 2609, | |
| TCRETURNri = 2610, | |
| TCRETURNri64 = 2611, | |
| TEST16i16 = 2612, | |
| TEST16mi = 2613, | |
| TEST16ri = 2614, | |
| TEST16rm = 2615, | |
| TEST16rr = 2616, | |
| TEST32i32 = 2617, | |
| TEST32mi = 2618, | |
| TEST32ri = 2619, | |
| TEST32rm = 2620, | |
| TEST32rr = 2621, | |
| TEST64i32 = 2622, | |
| TEST64mi32 = 2623, | |
| TEST64ri32 = 2624, | |
| TEST64rm = 2625, | |
| TEST64rr = 2626, | |
| TEST8i8 = 2627, | |
| TEST8mi = 2628, | |
| TEST8ri = 2629, | |
| TEST8ri_NOREX = 2630, | |
| TEST8rm = 2631, | |
| TEST8rr = 2632, | |
| TLSCall_32 = 2633, | |
| TLSCall_64 = 2634, | |
| TLS_addr32 = 2635, | |
| TLS_addr64 = 2636, | |
| TRAP = 2637, | |
| TST_F = 2638, | |
| TST_Fp32 = 2639, | |
| TST_Fp64 = 2640, | |
| TST_Fp80 = 2641, | |
| TZCNT16rm = 2642, | |
| TZCNT16rr = 2643, | |
| TZCNT32rm = 2644, | |
| TZCNT32rr = 2645, | |
| TZCNT64rm = 2646, | |
| TZCNT64rr = 2647, | |
| UCOMISDrm = 2648, | |
| UCOMISDrr = 2649, | |
| UCOMISSrm = 2650, | |
| UCOMISSrr = 2651, | |
| UCOM_FIPr = 2652, | |
| UCOM_FIr = 2653, | |
| UCOM_FPPr = 2654, | |
| UCOM_FPr = 2655, | |
| UCOM_FpIr32 = 2656, | |
| UCOM_FpIr64 = 2657, | |
| UCOM_FpIr80 = 2658, | |
| UCOM_Fpr32 = 2659, | |
| UCOM_Fpr64 = 2660, | |
| UCOM_Fpr80 = 2661, | |
| UCOM_Fr = 2662, | |
| UD2B = 2663, | |
| UNPCKHPDrm = 2664, | |
| UNPCKHPDrr = 2665, | |
| UNPCKHPSrm = 2666, | |
| UNPCKHPSrr = 2667, | |
| UNPCKLPDrm = 2668, | |
| UNPCKLPDrr = 2669, | |
| UNPCKLPSrm = 2670, | |
| UNPCKLPSrr = 2671, | |
| VAARG_64 = 2672, | |
| VADDPDYrm = 2673, | |
| VADDPDYrr = 2674, | |
| VADDPDrm = 2675, | |
| VADDPDrr = 2676, | |
| VADDPSYrm = 2677, | |
| VADDPSYrr = 2678, | |
| VADDPSrm = 2679, | |
| VADDPSrr = 2680, | |
| VADDSDrm = 2681, | |
| VADDSDrm_Int = 2682, | |
| VADDSDrr = 2683, | |
| VADDSDrr_Int = 2684, | |
| VADDSSrm = 2685, | |
| VADDSSrm_Int = 2686, | |
| VADDSSrr = 2687, | |
| VADDSSrr_Int = 2688, | |
| VADDSUBPDYrm = 2689, | |
| VADDSUBPDYrr = 2690, | |
| VADDSUBPDrm = 2691, | |
| VADDSUBPDrr = 2692, | |
| VADDSUBPSYrm = 2693, | |
| VADDSUBPSYrr = 2694, | |
| VADDSUBPSrm = 2695, | |
| VADDSUBPSrr = 2696, | |
| VAESDECLASTrm = 2697, | |
| VAESDECLASTrr = 2698, | |
| VAESDECrm = 2699, | |
| VAESDECrr = 2700, | |
| VAESENCLASTrm = 2701, | |
| VAESENCLASTrr = 2702, | |
| VAESENCrm = 2703, | |
| VAESENCrr = 2704, | |
| VAESIMCrm = 2705, | |
| VAESIMCrr = 2706, | |
| VAESKEYGENASSIST128rm = 2707, | |
| VAESKEYGENASSIST128rr = 2708, | |
| VANDNPDYrm = 2709, | |
| VANDNPDYrr = 2710, | |
| VANDNPDrm = 2711, | |
| VANDNPDrr = 2712, | |
| VANDNPSYrm = 2713, | |
| VANDNPSYrr = 2714, | |
| VANDNPSrm = 2715, | |
| VANDNPSrr = 2716, | |
| VANDPDYrm = 2717, | |
| VANDPDYrr = 2718, | |
| VANDPDrm = 2719, | |
| VANDPDrr = 2720, | |
| VANDPSYrm = 2721, | |
| VANDPSYrr = 2722, | |
| VANDPSrm = 2723, | |
| VANDPSrr = 2724, | |
| VASTART_SAVE_XMM_REGS = 2725, | |
| VBLENDPDYrmi = 2726, | |
| VBLENDPDYrri = 2727, | |
| VBLENDPDrmi = 2728, | |
| VBLENDPDrri = 2729, | |
| VBLENDPSYrmi = 2730, | |
| VBLENDPSYrri = 2731, | |
| VBLENDPSrmi = 2732, | |
| VBLENDPSrri = 2733, | |
| VBLENDVPDYrm = 2734, | |
| VBLENDVPDYrr = 2735, | |
| VBLENDVPDrm = 2736, | |
| VBLENDVPDrr = 2737, | |
| VBLENDVPSYrm = 2738, | |
| VBLENDVPSYrr = 2739, | |
| VBLENDVPSrm = 2740, | |
| VBLENDVPSrr = 2741, | |
| VBROADCASTF128 = 2742, | |
| VBROADCASTSD = 2743, | |
| VBROADCASTSS = 2744, | |
| VBROADCASTSSY = 2745, | |
| VCMPPDYrmi = 2746, | |
| VCMPPDYrmi_alt = 2747, | |
| VCMPPDYrri = 2748, | |
| VCMPPDYrri_alt = 2749, | |
| VCMPPDrmi = 2750, | |
| VCMPPDrmi_alt = 2751, | |
| VCMPPDrri = 2752, | |
| VCMPPDrri_alt = 2753, | |
| VCMPPSYrmi = 2754, | |
| VCMPPSYrmi_alt = 2755, | |
| VCMPPSYrri = 2756, | |
| VCMPPSYrri_alt = 2757, | |
| VCMPPSrmi = 2758, | |
| VCMPPSrmi_alt = 2759, | |
| VCMPPSrri = 2760, | |
| VCMPPSrri_alt = 2761, | |
| VCMPSDrm = 2762, | |
| VCMPSDrm_alt = 2763, | |
| VCMPSDrr = 2764, | |
| VCMPSDrr_alt = 2765, | |
| VCMPSSrm = 2766, | |
| VCMPSSrm_alt = 2767, | |
| VCMPSSrr = 2768, | |
| VCMPSSrr_alt = 2769, | |
| VCOMISDrm = 2770, | |
| VCOMISDrr = 2771, | |
| VCOMISSrm = 2772, | |
| VCOMISSrr = 2773, | |
| VCVTDQ2PDYrm = 2774, | |
| VCVTDQ2PDYrr = 2775, | |
| VCVTDQ2PDrm = 2776, | |
| VCVTDQ2PDrr = 2777, | |
| VCVTDQ2PSYrm = 2778, | |
| VCVTDQ2PSYrr = 2779, | |
| VCVTDQ2PSrm = 2780, | |
| VCVTDQ2PSrr = 2781, | |
| VCVTPD2DQXrYr = 2782, | |
| VCVTPD2DQXrm = 2783, | |
| VCVTPD2DQXrr = 2784, | |
| VCVTPD2DQYrm = 2785, | |
| VCVTPD2DQYrr = 2786, | |
| VCVTPD2DQrr = 2787, | |
| VCVTPD2PSXrYr = 2788, | |
| VCVTPD2PSXrm = 2789, | |
| VCVTPD2PSXrr = 2790, | |
| VCVTPD2PSYrm = 2791, | |
| VCVTPD2PSYrr = 2792, | |
| VCVTPD2PSrr = 2793, | |
| VCVTPH2PSYrm = 2794, | |
| VCVTPH2PSYrr = 2795, | |
| VCVTPH2PSrm = 2796, | |
| VCVTPH2PSrr = 2797, | |
| VCVTPS2DQYrm = 2798, | |
| VCVTPS2DQYrr = 2799, | |
| VCVTPS2DQrm = 2800, | |
| VCVTPS2DQrr = 2801, | |
| VCVTPS2PDYrm = 2802, | |
| VCVTPS2PDYrr = 2803, | |
| VCVTPS2PDrm = 2804, | |
| VCVTPS2PDrr = 2805, | |
| VCVTPS2PHYmr = 2806, | |
| VCVTPS2PHYrr = 2807, | |
| VCVTPS2PHmr = 2808, | |
| VCVTPS2PHrr = 2809, | |
| VCVTSD2SI64rm = 2810, | |
| VCVTSD2SI64rr = 2811, | |
| VCVTSD2SIrm = 2812, | |
| VCVTSD2SIrr = 2813, | |
| VCVTSD2SSrm = 2814, | |
| VCVTSD2SSrr = 2815, | |
| VCVTSI2SD64rm = 2816, | |
| VCVTSI2SD64rr = 2817, | |
| VCVTSI2SDLrm = 2818, | |
| VCVTSI2SDLrr = 2819, | |
| VCVTSI2SDrm = 2820, | |
| VCVTSI2SDrr = 2821, | |
| VCVTSI2SS64rm = 2822, | |
| VCVTSI2SS64rr = 2823, | |
| VCVTSI2SSrm = 2824, | |
| VCVTSI2SSrr = 2825, | |
| VCVTSS2SDrm = 2826, | |
| VCVTSS2SDrr = 2827, | |
| VCVTSS2SI64rm = 2828, | |
| VCVTSS2SI64rr = 2829, | |
| VCVTSS2SIrm = 2830, | |
| VCVTSS2SIrr = 2831, | |
| VCVTTPD2DQXrYr = 2832, | |
| VCVTTPD2DQXrm = 2833, | |
| VCVTTPD2DQXrr = 2834, | |
| VCVTTPD2DQYrm = 2835, | |
| VCVTTPD2DQYrr = 2836, | |
| VCVTTPD2DQrm = 2837, | |
| VCVTTPD2DQrr = 2838, | |
| VCVTTPS2DQYrm = 2839, | |
| VCVTTPS2DQYrr = 2840, | |
| VCVTTPS2DQrm = 2841, | |
| VCVTTPS2DQrr = 2842, | |
| VCVTTSD2SI64rm = 2843, | |
| VCVTTSD2SI64rr = 2844, | |
| VCVTTSD2SIrm = 2845, | |
| VCVTTSD2SIrr = 2846, | |
| VCVTTSS2SI64rm = 2847, | |
| VCVTTSS2SI64rr = 2848, | |
| VCVTTSS2SIrm = 2849, | |
| VCVTTSS2SIrr = 2850, | |
| VDIVPDYrm = 2851, | |
| VDIVPDYrr = 2852, | |
| VDIVPDrm = 2853, | |
| VDIVPDrr = 2854, | |
| VDIVPSYrm = 2855, | |
| VDIVPSYrr = 2856, | |
| VDIVPSrm = 2857, | |
| VDIVPSrr = 2858, | |
| VDIVSDrm = 2859, | |
| VDIVSDrm_Int = 2860, | |
| VDIVSDrr = 2861, | |
| VDIVSDrr_Int = 2862, | |
| VDIVSSrm = 2863, | |
| VDIVSSrm_Int = 2864, | |
| VDIVSSrr = 2865, | |
| VDIVSSrr_Int = 2866, | |
| VDPPDrmi = 2867, | |
| VDPPDrri = 2868, | |
| VDPPSYrmi = 2869, | |
| VDPPSYrri = 2870, | |
| VDPPSrmi = 2871, | |
| VDPPSrri = 2872, | |
| VERRm = 2873, | |
| VERRr = 2874, | |
| VERWm = 2875, | |
| VERWr = 2876, | |
| VEXTRACTF128mr = 2877, | |
| VEXTRACTF128rr = 2878, | |
| VEXTRACTPSmr = 2879, | |
| VEXTRACTPSrr = 2880, | |
| VEXTRACTPSrr64 = 2881, | |
| VFMADDPDr132m = 2882, | |
| VFMADDPDr132mY = 2883, | |
| VFMADDPDr132r = 2884, | |
| VFMADDPDr132rY = 2885, | |
| VFMADDPDr213m = 2886, | |
| VFMADDPDr213mY = 2887, | |
| VFMADDPDr213r = 2888, | |
| VFMADDPDr213rY = 2889, | |
| VFMADDPDr231m = 2890, | |
| VFMADDPDr231mY = 2891, | |
| VFMADDPDr231r = 2892, | |
| VFMADDPDr231rY = 2893, | |
| VFMADDPSr132m = 2894, | |
| VFMADDPSr132mY = 2895, | |
| VFMADDPSr132r = 2896, | |
| VFMADDPSr132rY = 2897, | |
| VFMADDPSr213m = 2898, | |
| VFMADDPSr213mY = 2899, | |
| VFMADDPSr213r = 2900, | |
| VFMADDPSr213rY = 2901, | |
| VFMADDPSr231m = 2902, | |
| VFMADDPSr231mY = 2903, | |
| VFMADDPSr231r = 2904, | |
| VFMADDPSr231rY = 2905, | |
| VFMADDSUBPDr132m = 2906, | |
| VFMADDSUBPDr132mY = 2907, | |
| VFMADDSUBPDr132r = 2908, | |
| VFMADDSUBPDr132rY = 2909, | |
| VFMADDSUBPDr213m = 2910, | |
| VFMADDSUBPDr213mY = 2911, | |
| VFMADDSUBPDr213r = 2912, | |
| VFMADDSUBPDr213rY = 2913, | |
| VFMADDSUBPDr231m = 2914, | |
| VFMADDSUBPDr231mY = 2915, | |
| VFMADDSUBPDr231r = 2916, | |
| VFMADDSUBPDr231rY = 2917, | |
| VFMADDSUBPSr132m = 2918, | |
| VFMADDSUBPSr132mY = 2919, | |
| VFMADDSUBPSr132r = 2920, | |
| VFMADDSUBPSr132rY = 2921, | |
| VFMADDSUBPSr213m = 2922, | |
| VFMADDSUBPSr213mY = 2923, | |
| VFMADDSUBPSr213r = 2924, | |
| VFMADDSUBPSr213rY = 2925, | |
| VFMADDSUBPSr231m = 2926, | |
| VFMADDSUBPSr231mY = 2927, | |
| VFMADDSUBPSr231r = 2928, | |
| VFMADDSUBPSr231rY = 2929, | |
| VFMSUBADDPDr132m = 2930, | |
| VFMSUBADDPDr132mY = 2931, | |
| VFMSUBADDPDr132r = 2932, | |
| VFMSUBADDPDr132rY = 2933, | |
| VFMSUBADDPDr213m = 2934, | |
| VFMSUBADDPDr213mY = 2935, | |
| VFMSUBADDPDr213r = 2936, | |
| VFMSUBADDPDr213rY = 2937, | |
| VFMSUBADDPDr231m = 2938, | |
| VFMSUBADDPDr231mY = 2939, | |
| VFMSUBADDPDr231r = 2940, | |
| VFMSUBADDPDr231rY = 2941, | |
| VFMSUBADDPSr132m = 2942, | |
| VFMSUBADDPSr132mY = 2943, | |
| VFMSUBADDPSr132r = 2944, | |
| VFMSUBADDPSr132rY = 2945, | |
| VFMSUBADDPSr213m = 2946, | |
| VFMSUBADDPSr213mY = 2947, | |
| VFMSUBADDPSr213r = 2948, | |
| VFMSUBADDPSr213rY = 2949, | |
| VFMSUBADDPSr231m = 2950, | |
| VFMSUBADDPSr231mY = 2951, | |
| VFMSUBADDPSr231r = 2952, | |
| VFMSUBADDPSr231rY = 2953, | |
| VFMSUBPDr132m = 2954, | |
| VFMSUBPDr132mY = 2955, | |
| VFMSUBPDr132r = 2956, | |
| VFMSUBPDr132rY = 2957, | |
| VFMSUBPDr213m = 2958, | |
| VFMSUBPDr213mY = 2959, | |
| VFMSUBPDr213r = 2960, | |
| VFMSUBPDr213rY = 2961, | |
| VFMSUBPDr231m = 2962, | |
| VFMSUBPDr231mY = 2963, | |
| VFMSUBPDr231r = 2964, | |
| VFMSUBPDr231rY = 2965, | |
| VFMSUBPSr132m = 2966, | |
| VFMSUBPSr132mY = 2967, | |
| VFMSUBPSr132r = 2968, | |
| VFMSUBPSr132rY = 2969, | |
| VFMSUBPSr213m = 2970, | |
| VFMSUBPSr213mY = 2971, | |
| VFMSUBPSr213r = 2972, | |
| VFMSUBPSr213rY = 2973, | |
| VFMSUBPSr231m = 2974, | |
| VFMSUBPSr231mY = 2975, | |
| VFMSUBPSr231r = 2976, | |
| VFMSUBPSr231rY = 2977, | |
| VFNMADDPDr132m = 2978, | |
| VFNMADDPDr132mY = 2979, | |
| VFNMADDPDr132r = 2980, | |
| VFNMADDPDr132rY = 2981, | |
| VFNMADDPDr213m = 2982, | |
| VFNMADDPDr213mY = 2983, | |
| VFNMADDPDr213r = 2984, | |
| VFNMADDPDr213rY = 2985, | |
| VFNMADDPDr231m = 2986, | |
| VFNMADDPDr231mY = 2987, | |
| VFNMADDPDr231r = 2988, | |
| VFNMADDPDr231rY = 2989, | |
| VFNMADDPSr132m = 2990, | |
| VFNMADDPSr132mY = 2991, | |
| VFNMADDPSr132r = 2992, | |
| VFNMADDPSr132rY = 2993, | |
| VFNMADDPSr213m = 2994, | |
| VFNMADDPSr213mY = 2995, | |
| VFNMADDPSr213r = 2996, | |
| VFNMADDPSr213rY = 2997, | |
| VFNMADDPSr231m = 2998, | |
| VFNMADDPSr231mY = 2999, | |
| VFNMADDPSr231r = 3000, | |
| VFNMADDPSr231rY = 3001, | |
| VFNMSUBPDr132m = 3002, | |
| VFNMSUBPDr132mY = 3003, | |
| VFNMSUBPDr132r = 3004, | |
| VFNMSUBPDr132rY = 3005, | |
| VFNMSUBPDr213m = 3006, | |
| VFNMSUBPDr213mY = 3007, | |
| VFNMSUBPDr213r = 3008, | |
| VFNMSUBPDr213rY = 3009, | |
| VFNMSUBPDr231m = 3010, | |
| VFNMSUBPDr231mY = 3011, | |
| VFNMSUBPDr231r = 3012, | |
| VFNMSUBPDr231rY = 3013, | |
| VFNMSUBPSr132m = 3014, | |
| VFNMSUBPSr132mY = 3015, | |
| VFNMSUBPSr132r = 3016, | |
| VFNMSUBPSr132rY = 3017, | |
| VFNMSUBPSr213m = 3018, | |
| VFNMSUBPSr213mY = 3019, | |
| VFNMSUBPSr213r = 3020, | |
| VFNMSUBPSr213rY = 3021, | |
| VFNMSUBPSr231m = 3022, | |
| VFNMSUBPSr231mY = 3023, | |
| VFNMSUBPSr231r = 3024, | |
| VFNMSUBPSr231rY = 3025, | |
| VFsANDNPDrm = 3026, | |
| VFsANDNPDrr = 3027, | |
| VFsANDNPSrm = 3028, | |
| VFsANDNPSrr = 3029, | |
| VFsANDPDrm = 3030, | |
| VFsANDPDrr = 3031, | |
| VFsANDPSrm = 3032, | |
| VFsANDPSrr = 3033, | |
| VFsORPDrm = 3034, | |
| VFsORPDrr = 3035, | |
| VFsORPSrm = 3036, | |
| VFsORPSrr = 3037, | |
| VFsXORPDrm = 3038, | |
| VFsXORPDrr = 3039, | |
| VFsXORPSrm = 3040, | |
| VFsXORPSrr = 3041, | |
| VHADDPDYrm = 3042, | |
| VHADDPDYrr = 3043, | |
| VHADDPDrm = 3044, | |
| VHADDPDrr = 3045, | |
| VHADDPSYrm = 3046, | |
| VHADDPSYrr = 3047, | |
| VHADDPSrm = 3048, | |
| VHADDPSrr = 3049, | |
| VHSUBPDYrm = 3050, | |
| VHSUBPDYrr = 3051, | |
| VHSUBPDrm = 3052, | |
| VHSUBPDrr = 3053, | |
| VHSUBPSYrm = 3054, | |
| VHSUBPSYrr = 3055, | |
| VHSUBPSrm = 3056, | |
| VHSUBPSrr = 3057, | |
| VINSERTF128rm = 3058, | |
| VINSERTF128rr = 3059, | |
| VINSERTPSrm = 3060, | |
| VINSERTPSrr = 3061, | |
| VLDDQUYrm = 3062, | |
| VLDDQUrm = 3063, | |
| VLDMXCSR = 3064, | |
| VMASKMOVDQU = 3065, | |
| VMASKMOVDQU64 = 3066, | |
| VMASKMOVPDYmr = 3067, | |
| VMASKMOVPDYrm = 3068, | |
| VMASKMOVPDmr = 3069, | |
| VMASKMOVPDrm = 3070, | |
| VMASKMOVPSYmr = 3071, | |
| VMASKMOVPSYrm = 3072, | |
| VMASKMOVPSmr = 3073, | |
| VMASKMOVPSrm = 3074, | |
| VMAXPDYrm = 3075, | |
| VMAXPDYrm_Int = 3076, | |
| VMAXPDYrr = 3077, | |
| VMAXPDYrr_Int = 3078, | |
| VMAXPDrm = 3079, | |
| VMAXPDrm_Int = 3080, | |
| VMAXPDrr = 3081, | |
| VMAXPDrr_Int = 3082, | |
| VMAXPSYrm = 3083, | |
| VMAXPSYrm_Int = 3084, | |
| VMAXPSYrr = 3085, | |
| VMAXPSYrr_Int = 3086, | |
| VMAXPSrm = 3087, | |
| VMAXPSrm_Int = 3088, | |
| VMAXPSrr = 3089, | |
| VMAXPSrr_Int = 3090, | |
| VMAXSDrm = 3091, | |
| VMAXSDrm_Int = 3092, | |
| VMAXSDrr = 3093, | |
| VMAXSDrr_Int = 3094, | |
| VMAXSSrm = 3095, | |
| VMAXSSrm_Int = 3096, | |
| VMAXSSrr = 3097, | |
| VMAXSSrr_Int = 3098, | |
| VMCALL = 3099, | |
| VMCLEARm = 3100, | |
| VMINPDYrm = 3101, | |
| VMINPDYrm_Int = 3102, | |
| VMINPDYrr = 3103, | |
| VMINPDYrr_Int = 3104, | |
| VMINPDrm = 3105, | |
| VMINPDrm_Int = 3106, | |
| VMINPDrr = 3107, | |
| VMINPDrr_Int = 3108, | |
| VMINPSYrm = 3109, | |
| VMINPSYrm_Int = 3110, | |
| VMINPSYrr = 3111, | |
| VMINPSYrr_Int = 3112, | |
| VMINPSrm = 3113, | |
| VMINPSrm_Int = 3114, | |
| VMINPSrr = 3115, | |
| VMINPSrr_Int = 3116, | |
| VMINSDrm = 3117, | |
| VMINSDrm_Int = 3118, | |
| VMINSDrr = 3119, | |
| VMINSDrr_Int = 3120, | |
| VMINSSrm = 3121, | |
| VMINSSrm_Int = 3122, | |
| VMINSSrr = 3123, | |
| VMINSSrr_Int = 3124, | |
| VMLAUNCH = 3125, | |
| VMOV64toPQIrr = 3126, | |
| VMOV64toSDrm = 3127, | |
| VMOV64toSDrr = 3128, | |
| VMOVAPDYmr = 3129, | |
| VMOVAPDYrm = 3130, | |
| VMOVAPDYrr = 3131, | |
| VMOVAPDYrr_REV = 3132, | |
| VMOVAPDmr = 3133, | |
| VMOVAPDrm = 3134, | |
| VMOVAPDrr = 3135, | |
| VMOVAPDrr_REV = 3136, | |
| VMOVAPSYmr = 3137, | |
| VMOVAPSYrm = 3138, | |
| VMOVAPSYrr = 3139, | |
| VMOVAPSYrr_REV = 3140, | |
| VMOVAPSmr = 3141, | |
| VMOVAPSrm = 3142, | |
| VMOVAPSrr = 3143, | |
| VMOVAPSrr_REV = 3144, | |
| VMOVDDUPYrm = 3145, | |
| VMOVDDUPYrr = 3146, | |
| VMOVDDUPrm = 3147, | |
| VMOVDDUPrr = 3148, | |
| VMOVDI2PDIrm = 3149, | |
| VMOVDI2PDIrr = 3150, | |
| VMOVDI2SSrm = 3151, | |
| VMOVDI2SSrr = 3152, | |
| VMOVDQAYmr = 3153, | |
| VMOVDQAYrm = 3154, | |
| VMOVDQAYrr = 3155, | |
| VMOVDQAYrr_REV = 3156, | |
| VMOVDQAmr = 3157, | |
| VMOVDQArm = 3158, | |
| VMOVDQArr = 3159, | |
| VMOVDQArr_REV = 3160, | |
| VMOVDQUYmr = 3161, | |
| VMOVDQUYrm = 3162, | |
| VMOVDQUYrr = 3163, | |
| VMOVDQUYrr_REV = 3164, | |
| VMOVDQUmr = 3165, | |
| VMOVDQUmr_Int = 3166, | |
| VMOVDQUrm = 3167, | |
| VMOVDQUrr = 3168, | |
| VMOVDQUrr_REV = 3169, | |
| VMOVHLPSrr = 3170, | |
| VMOVHPDmr = 3171, | |
| VMOVHPDrm = 3172, | |
| VMOVHPSmr = 3173, | |
| VMOVHPSrm = 3174, | |
| VMOVLHPSrr = 3175, | |
| VMOVLPDmr = 3176, | |
| VMOVLPDrm = 3177, | |
| VMOVLPSmr = 3178, | |
| VMOVLPSrm = 3179, | |
| VMOVLQ128mr = 3180, | |
| VMOVMSKPDYr64r = 3181, | |
| VMOVMSKPDYrr32 = 3182, | |
| VMOVMSKPDYrr64 = 3183, | |
| VMOVMSKPDr64r = 3184, | |
| VMOVMSKPDrr32 = 3185, | |
| VMOVMSKPDrr64 = 3186, | |
| VMOVMSKPSYr64r = 3187, | |
| VMOVMSKPSYrr32 = 3188, | |
| VMOVMSKPSYrr64 = 3189, | |
| VMOVMSKPSr64r = 3190, | |
| VMOVMSKPSrr32 = 3191, | |
| VMOVMSKPSrr64 = 3192, | |
| VMOVNTDQArm = 3193, | |
| VMOVNTDQY_64mr = 3194, | |
| VMOVNTDQYmr = 3195, | |
| VMOVNTDQ_64mr = 3196, | |
| VMOVNTDQmr = 3197, | |
| VMOVNTPDYmr = 3198, | |
| VMOVNTPDmr = 3199, | |
| VMOVNTPSYmr = 3200, | |
| VMOVNTPSmr = 3201, | |
| VMOVPDI2DImr = 3202, | |
| VMOVPDI2DIrr = 3203, | |
| VMOVPQI2QImr = 3204, | |
| VMOVPQIto64rr = 3205, | |
| VMOVQI2PQIrm = 3206, | |
| VMOVQd64rr = 3207, | |
| VMOVQd64rr_alt = 3208, | |
| VMOVQs64rr = 3209, | |
| VMOVQxrxr = 3210, | |
| VMOVSDmr = 3211, | |
| VMOVSDrm = 3212, | |
| VMOVSDrr = 3213, | |
| VMOVSDrr_REV = 3214, | |
| VMOVSDto64mr = 3215, | |
| VMOVSDto64rr = 3216, | |
| VMOVSHDUPYrm = 3217, | |
| VMOVSHDUPYrr = 3218, | |
| VMOVSHDUPrm = 3219, | |
| VMOVSHDUPrr = 3220, | |
| VMOVSLDUPYrm = 3221, | |
| VMOVSLDUPYrr = 3222, | |
| VMOVSLDUPrm = 3223, | |
| VMOVSLDUPrr = 3224, | |
| VMOVSS2DImr = 3225, | |
| VMOVSS2DIrr = 3226, | |
| VMOVSSmr = 3227, | |
| VMOVSSrm = 3228, | |
| VMOVSSrr = 3229, | |
| VMOVSSrr_REV = 3230, | |
| VMOVUPDYmr = 3231, | |
| VMOVUPDYrm = 3232, | |
| VMOVUPDYrr = 3233, | |
| VMOVUPDYrr_REV = 3234, | |
| VMOVUPDmr = 3235, | |
| VMOVUPDrm = 3236, | |
| VMOVUPDrr = 3237, | |
| VMOVUPDrr_REV = 3238, | |
| VMOVUPSYmr = 3239, | |
| VMOVUPSYrm = 3240, | |
| VMOVUPSYrr = 3241, | |
| VMOVUPSYrr_REV = 3242, | |
| VMOVUPSmr = 3243, | |
| VMOVUPSrm = 3244, | |
| VMOVUPSrr = 3245, | |
| VMOVUPSrr_REV = 3246, | |
| VMOVZDI2PDIrm = 3247, | |
| VMOVZDI2PDIrr = 3248, | |
| VMOVZPQILo2PQIrm = 3249, | |
| VMOVZPQILo2PQIrr = 3250, | |
| VMOVZQI2PQIrm = 3251, | |
| VMOVZQI2PQIrr = 3252, | |
| VMPSADBWrmi = 3253, | |
| VMPSADBWrri = 3254, | |
| VMPTRLDm = 3255, | |
| VMPTRSTm = 3256, | |
| VMREAD32rm = 3257, | |
| VMREAD32rr = 3258, | |
| VMREAD64rm = 3259, | |
| VMREAD64rr = 3260, | |
| VMRESUME = 3261, | |
| VMULPDYrm = 3262, | |
| VMULPDYrr = 3263, | |
| VMULPDrm = 3264, | |
| VMULPDrr = 3265, | |
| VMULPSYrm = 3266, | |
| VMULPSYrr = 3267, | |
| VMULPSrm = 3268, | |
| VMULPSrr = 3269, | |
| VMULSDrm = 3270, | |
| VMULSDrm_Int = 3271, | |
| VMULSDrr = 3272, | |
| VMULSDrr_Int = 3273, | |
| VMULSSrm = 3274, | |
| VMULSSrm_Int = 3275, | |
| VMULSSrr = 3276, | |
| VMULSSrr_Int = 3277, | |
| VMWRITE32rm = 3278, | |
| VMWRITE32rr = 3279, | |
| VMWRITE64rm = 3280, | |
| VMWRITE64rr = 3281, | |
| VMXOFF = 3282, | |
| VMXON = 3283, | |
| VORPDYrm = 3284, | |
| VORPDYrr = 3285, | |
| VORPDrm = 3286, | |
| VORPDrr = 3287, | |
| VORPSYrm = 3288, | |
| VORPSYrr = 3289, | |
| VORPSrm = 3290, | |
| VORPSrr = 3291, | |
| VPABSBrm128 = 3292, | |
| VPABSBrr128 = 3293, | |
| VPABSDrm128 = 3294, | |
| VPABSDrr128 = 3295, | |
| VPABSWrm128 = 3296, | |
| VPABSWrr128 = 3297, | |
| VPACKSSDWrm = 3298, | |
| VPACKSSDWrr = 3299, | |
| VPACKSSWBrm = 3300, | |
| VPACKSSWBrr = 3301, | |
| VPACKUSDWrm = 3302, | |
| VPACKUSDWrr = 3303, | |
| VPACKUSWBrm = 3304, | |
| VPACKUSWBrr = 3305, | |
| VPADDBrm = 3306, | |
| VPADDBrr = 3307, | |
| VPADDDrm = 3308, | |
| VPADDDrr = 3309, | |
| VPADDQrm = 3310, | |
| VPADDQrr = 3311, | |
| VPADDSBrm = 3312, | |
| VPADDSBrr = 3313, | |
| VPADDSWrm = 3314, | |
| VPADDSWrr = 3315, | |
| VPADDUSBrm = 3316, | |
| VPADDUSBrr = 3317, | |
| VPADDUSWrm = 3318, | |
| VPADDUSWrr = 3319, | |
| VPADDWrm = 3320, | |
| VPADDWrr = 3321, | |
| VPALIGNR128rm = 3322, | |
| VPALIGNR128rr = 3323, | |
| VPANDNrm = 3324, | |
| VPANDNrr = 3325, | |
| VPANDrm = 3326, | |
| VPANDrr = 3327, | |
| VPAVGBrm = 3328, | |
| VPAVGBrr = 3329, | |
| VPAVGWrm = 3330, | |
| VPAVGWrr = 3331, | |
| VPBLENDVBrm = 3332, | |
| VPBLENDVBrr = 3333, | |
| VPBLENDWrmi = 3334, | |
| VPBLENDWrri = 3335, | |
| VPCLMULQDQrm = 3336, | |
| VPCLMULQDQrr = 3337, | |
| VPCMPEQBrm = 3338, | |
| VPCMPEQBrr = 3339, | |
| VPCMPEQDrm = 3340, | |
| VPCMPEQDrr = 3341, | |
| VPCMPEQQrm = 3342, | |
| VPCMPEQQrr = 3343, | |
| VPCMPEQWrm = 3344, | |
| VPCMPEQWrr = 3345, | |
| VPCMPESTRIArm = 3346, | |
| VPCMPESTRIArr = 3347, | |
| VPCMPESTRICrm = 3348, | |
| VPCMPESTRICrr = 3349, | |
| VPCMPESTRIOrm = 3350, | |
| VPCMPESTRIOrr = 3351, | |
| VPCMPESTRISrm = 3352, | |
| VPCMPESTRISrr = 3353, | |
| VPCMPESTRIZrm = 3354, | |
| VPCMPESTRIZrr = 3355, | |
| VPCMPESTRIrm = 3356, | |
| VPCMPESTRIrr = 3357, | |
| VPCMPESTRM128MEM = 3358, | |
| VPCMPESTRM128REG = 3359, | |
| VPCMPESTRM128rm = 3360, | |
| VPCMPESTRM128rr = 3361, | |
| VPCMPGTBrm = 3362, | |
| VPCMPGTBrr = 3363, | |
| VPCMPGTDrm = 3364, | |
| VPCMPGTDrr = 3365, | |
| VPCMPGTQrm = 3366, | |
| VPCMPGTQrr = 3367, | |
| VPCMPGTWrm = 3368, | |
| VPCMPGTWrr = 3369, | |
| VPCMPISTRIArm = 3370, | |
| VPCMPISTRIArr = 3371, | |
| VPCMPISTRICrm = 3372, | |
| VPCMPISTRICrr = 3373, | |
| VPCMPISTRIOrm = 3374, | |
| VPCMPISTRIOrr = 3375, | |
| VPCMPISTRISrm = 3376, | |
| VPCMPISTRISrr = 3377, | |
| VPCMPISTRIZrm = 3378, | |
| VPCMPISTRIZrr = 3379, | |
| VPCMPISTRIrm = 3380, | |
| VPCMPISTRIrr = 3381, | |
| VPCMPISTRM128MEM = 3382, | |
| VPCMPISTRM128REG = 3383, | |
| VPCMPISTRM128rm = 3384, | |
| VPCMPISTRM128rr = 3385, | |
| VPERM2F128rm = 3386, | |
| VPERM2F128rr = 3387, | |
| VPERMILPDYmi = 3388, | |
| VPERMILPDYri = 3389, | |
| VPERMILPDYrm = 3390, | |
| VPERMILPDYrr = 3391, | |
| VPERMILPDmi = 3392, | |
| VPERMILPDri = 3393, | |
| VPERMILPDrm = 3394, | |
| VPERMILPDrr = 3395, | |
| VPERMILPSYmi = 3396, | |
| VPERMILPSYri = 3397, | |
| VPERMILPSYrm = 3398, | |
| VPERMILPSYrr = 3399, | |
| VPERMILPSmi = 3400, | |
| VPERMILPSri = 3401, | |
| VPERMILPSrm = 3402, | |
| VPERMILPSrr = 3403, | |
| VPEXTRBmr = 3404, | |
| VPEXTRBrr = 3405, | |
| VPEXTRBrr64 = 3406, | |
| VPEXTRDmr = 3407, | |
| VPEXTRDrr = 3408, | |
| VPEXTRQmr = 3409, | |
| VPEXTRQrr = 3410, | |
| VPEXTRWmr = 3411, | |
| VPEXTRWri = 3412, | |
| VPHADDDrm128 = 3413, | |
| VPHADDDrr128 = 3414, | |
| VPHADDSWrm128 = 3415, | |
| VPHADDSWrr128 = 3416, | |
| VPHADDWrm128 = 3417, | |
| VPHADDWrr128 = 3418, | |
| VPHMINPOSUWrm128 = 3419, | |
| VPHMINPOSUWrr128 = 3420, | |
| VPHSUBDrm128 = 3421, | |
| VPHSUBDrr128 = 3422, | |
| VPHSUBSWrm128 = 3423, | |
| VPHSUBSWrr128 = 3424, | |
| VPHSUBWrm128 = 3425, | |
| VPHSUBWrr128 = 3426, | |
| VPINSRBrm = 3427, | |
| VPINSRBrr = 3428, | |
| VPINSRDrm = 3429, | |
| VPINSRDrr = 3430, | |
| VPINSRQrm = 3431, | |
| VPINSRQrr = 3432, | |
| VPINSRWrmi = 3433, | |
| VPINSRWrr64i = 3434, | |
| VPINSRWrri = 3435, | |
| VPMADDUBSWrm128 = 3436, | |
| VPMADDUBSWrr128 = 3437, | |
| VPMADDWDrm = 3438, | |
| VPMADDWDrr = 3439, | |
| VPMAXSBrm = 3440, | |
| VPMAXSBrr = 3441, | |
| VPMAXSDrm = 3442, | |
| VPMAXSDrr = 3443, | |
| VPMAXSWrm = 3444, | |
| VPMAXSWrr = 3445, | |
| VPMAXUBrm = 3446, | |
| VPMAXUBrr = 3447, | |
| VPMAXUDrm = 3448, | |
| VPMAXUDrr = 3449, | |
| VPMAXUWrm = 3450, | |
| VPMAXUWrr = 3451, | |
| VPMINSBrm = 3452, | |
| VPMINSBrr = 3453, | |
| VPMINSDrm = 3454, | |
| VPMINSDrr = 3455, | |
| VPMINSWrm = 3456, | |
| VPMINSWrr = 3457, | |
| VPMINUBrm = 3458, | |
| VPMINUBrr = 3459, | |
| VPMINUDrm = 3460, | |
| VPMINUDrr = 3461, | |
| VPMINUWrm = 3462, | |
| VPMINUWrr = 3463, | |
| VPMOVMSKBr64r = 3464, | |
| VPMOVMSKBrr = 3465, | |
| VPMOVSXBDrm = 3466, | |
| VPMOVSXBDrr = 3467, | |
| VPMOVSXBQrm = 3468, | |
| VPMOVSXBQrr = 3469, | |
| VPMOVSXBWrm = 3470, | |
| VPMOVSXBWrr = 3471, | |
| VPMOVSXDQrm = 3472, | |
| VPMOVSXDQrr = 3473, | |
| VPMOVSXWDrm = 3474, | |
| VPMOVSXWDrr = 3475, | |
| VPMOVSXWQrm = 3476, | |
| VPMOVSXWQrr = 3477, | |
| VPMOVZXBDrm = 3478, | |
| VPMOVZXBDrr = 3479, | |
| VPMOVZXBQrm = 3480, | |
| VPMOVZXBQrr = 3481, | |
| VPMOVZXBWrm = 3482, | |
| VPMOVZXBWrr = 3483, | |
| VPMOVZXDQrm = 3484, | |
| VPMOVZXDQrr = 3485, | |
| VPMOVZXWDrm = 3486, | |
| VPMOVZXWDrr = 3487, | |
| VPMOVZXWQrm = 3488, | |
| VPMOVZXWQrr = 3489, | |
| VPMULDQrm = 3490, | |
| VPMULDQrr = 3491, | |
| VPMULHRSWrm128 = 3492, | |
| VPMULHRSWrr128 = 3493, | |
| VPMULHUWrm = 3494, | |
| VPMULHUWrr = 3495, | |
| VPMULHWrm = 3496, | |
| VPMULHWrr = 3497, | |
| VPMULLDrm = 3498, | |
| VPMULLDrr = 3499, | |
| VPMULLWrm = 3500, | |
| VPMULLWrr = 3501, | |
| VPMULUDQrm = 3502, | |
| VPMULUDQrr = 3503, | |
| VPORrm = 3504, | |
| VPORrr = 3505, | |
| VPSADBWrm = 3506, | |
| VPSADBWrr = 3507, | |
| VPSHUFBrm128 = 3508, | |
| VPSHUFBrr128 = 3509, | |
| VPSHUFDmi = 3510, | |
| VPSHUFDri = 3511, | |
| VPSHUFHWmi = 3512, | |
| VPSHUFHWri = 3513, | |
| VPSHUFLWmi = 3514, | |
| VPSHUFLWri = 3515, | |
| VPSIGNBrm128 = 3516, | |
| VPSIGNBrr128 = 3517, | |
| VPSIGNDrm128 = 3518, | |
| VPSIGNDrr128 = 3519, | |
| VPSIGNWrm128 = 3520, | |
| VPSIGNWrr128 = 3521, | |
| VPSLLDQri = 3522, | |
| VPSLLDri = 3523, | |
| VPSLLDrm = 3524, | |
| VPSLLDrr = 3525, | |
| VPSLLQri = 3526, | |
| VPSLLQrm = 3527, | |
| VPSLLQrr = 3528, | |
| VPSLLWri = 3529, | |
| VPSLLWrm = 3530, | |
| VPSLLWrr = 3531, | |
| VPSRADri = 3532, | |
| VPSRADrm = 3533, | |
| VPSRADrr = 3534, | |
| VPSRAWri = 3535, | |
| VPSRAWrm = 3536, | |
| VPSRAWrr = 3537, | |
| VPSRLDQri = 3538, | |
| VPSRLDri = 3539, | |
| VPSRLDrm = 3540, | |
| VPSRLDrr = 3541, | |
| VPSRLQri = 3542, | |
| VPSRLQrm = 3543, | |
| VPSRLQrr = 3544, | |
| VPSRLWri = 3545, | |
| VPSRLWrm = 3546, | |
| VPSRLWrr = 3547, | |
| VPSUBBrm = 3548, | |
| VPSUBBrr = 3549, | |
| VPSUBDrm = 3550, | |
| VPSUBDrr = 3551, | |
| VPSUBQrm = 3552, | |
| VPSUBQrr = 3553, | |
| VPSUBSBrm = 3554, | |
| VPSUBSBrr = 3555, | |
| VPSUBSWrm = 3556, | |
| VPSUBSWrr = 3557, | |
| VPSUBUSBrm = 3558, | |
| VPSUBUSBrr = 3559, | |
| VPSUBUSWrm = 3560, | |
| VPSUBUSWrr = 3561, | |
| VPSUBWrm = 3562, | |
| VPSUBWrr = 3563, | |
| VPTESTYrm = 3564, | |
| VPTESTYrr = 3565, | |
| VPTESTrm = 3566, | |
| VPTESTrr = 3567, | |
| VPUNPCKHBWrm = 3568, | |
| VPUNPCKHBWrr = 3569, | |
| VPUNPCKHDQrm = 3570, | |
| VPUNPCKHDQrr = 3571, | |
| VPUNPCKHQDQrm = 3572, | |
| VPUNPCKHQDQrr = 3573, | |
| VPUNPCKHWDrm = 3574, | |
| VPUNPCKHWDrr = 3575, | |
| VPUNPCKLBWrm = 3576, | |
| VPUNPCKLBWrr = 3577, | |
| VPUNPCKLDQrm = 3578, | |
| VPUNPCKLDQrr = 3579, | |
| VPUNPCKLQDQrm = 3580, | |
| VPUNPCKLQDQrr = 3581, | |
| VPUNPCKLWDrm = 3582, | |
| VPUNPCKLWDrr = 3583, | |
| VPXORrm = 3584, | |
| VPXORrr = 3585, | |
| VRCPPSYm = 3586, | |
| VRCPPSYm_Int = 3587, | |
| VRCPPSYr = 3588, | |
| VRCPPSYr_Int = 3589, | |
| VRCPPSm = 3590, | |
| VRCPPSm_Int = 3591, | |
| VRCPPSr = 3592, | |
| VRCPPSr_Int = 3593, | |
| VRCPSSm = 3594, | |
| VRCPSSm_Int = 3595, | |
| VRCPSSr = 3596, | |
| VROUNDPDm = 3597, | |
| VROUNDPDm_AVX = 3598, | |
| VROUNDPDr = 3599, | |
| VROUNDPDr_AVX = 3600, | |
| VROUNDPSm = 3601, | |
| VROUNDPSm_AVX = 3602, | |
| VROUNDPSr = 3603, | |
| VROUNDPSr_AVX = 3604, | |
| VROUNDSDm = 3605, | |
| VROUNDSDm_AVX = 3606, | |
| VROUNDSDr = 3607, | |
| VROUNDSDr_AVX = 3608, | |
| VROUNDSSm = 3609, | |
| VROUNDSSm_AVX = 3610, | |
| VROUNDSSr = 3611, | |
| VROUNDSSr_AVX = 3612, | |
| VROUNDYPDm = 3613, | |
| VROUNDYPDm_AVX = 3614, | |
| VROUNDYPDr = 3615, | |
| VROUNDYPDr_AVX = 3616, | |
| VROUNDYPSm = 3617, | |
| VROUNDYPSm_AVX = 3618, | |
| VROUNDYPSr = 3619, | |
| VROUNDYPSr_AVX = 3620, | |
| VRSQRTPSYm = 3621, | |
| VRSQRTPSYm_Int = 3622, | |
| VRSQRTPSYr = 3623, | |
| VRSQRTPSYr_Int = 3624, | |
| VRSQRTPSm = 3625, | |
| VRSQRTPSm_Int = 3626, | |
| VRSQRTPSr = 3627, | |
| VRSQRTPSr_Int = 3628, | |
| VRSQRTSSm = 3629, | |
| VRSQRTSSm_Int = 3630, | |
| VRSQRTSSr = 3631, | |
| VSHUFPDYrmi = 3632, | |
| VSHUFPDYrri = 3633, | |
| VSHUFPDrmi = 3634, | |
| VSHUFPDrri = 3635, | |
| VSHUFPSYrmi = 3636, | |
| VSHUFPSYrri = 3637, | |
| VSHUFPSrmi = 3638, | |
| VSHUFPSrri = 3639, | |
| VSQRTPDYm = 3640, | |
| VSQRTPDYm_Int = 3641, | |
| VSQRTPDYr = 3642, | |
| VSQRTPDYr_Int = 3643, | |
| VSQRTPDm = 3644, | |
| VSQRTPDm_Int = 3645, | |
| VSQRTPDr = 3646, | |
| VSQRTPDr_Int = 3647, | |
| VSQRTPSYm = 3648, | |
| VSQRTPSYm_Int = 3649, | |
| VSQRTPSYr = 3650, | |
| VSQRTPSYr_Int = 3651, | |
| VSQRTPSm = 3652, | |
| VSQRTPSm_Int = 3653, | |
| VSQRTPSr = 3654, | |
| VSQRTPSr_Int = 3655, | |
| VSQRTSDm = 3656, | |
| VSQRTSDm_Int = 3657, | |
| VSQRTSDr = 3658, | |
| VSQRTSSm = 3659, | |
| VSQRTSSm_Int = 3660, | |
| VSQRTSSr = 3661, | |
| VSTMXCSR = 3662, | |
| VSUBPDYrm = 3663, | |
| VSUBPDYrr = 3664, | |
| VSUBPDrm = 3665, | |
| VSUBPDrr = 3666, | |
| VSUBPSYrm = 3667, | |
| VSUBPSYrr = 3668, | |
| VSUBPSrm = 3669, | |
| VSUBPSrr = 3670, | |
| VSUBSDrm = 3671, | |
| VSUBSDrm_Int = 3672, | |
| VSUBSDrr = 3673, | |
| VSUBSDrr_Int = 3674, | |
| VSUBSSrm = 3675, | |
| VSUBSSrm_Int = 3676, | |
| VSUBSSrr = 3677, | |
| VSUBSSrr_Int = 3678, | |
| VTESTPDYrm = 3679, | |
| VTESTPDYrr = 3680, | |
| VTESTPDrm = 3681, | |
| VTESTPDrr = 3682, | |
| VTESTPSYrm = 3683, | |
| VTESTPSYrr = 3684, | |
| VTESTPSrm = 3685, | |
| VTESTPSrr = 3686, | |
| VUCOMISDrm = 3687, | |
| VUCOMISDrr = 3688, | |
| VUCOMISSrm = 3689, | |
| VUCOMISSrr = 3690, | |
| VUNPCKHPDYrm = 3691, | |
| VUNPCKHPDYrr = 3692, | |
| VUNPCKHPDrm = 3693, | |
| VUNPCKHPDrr = 3694, | |
| VUNPCKHPSYrm = 3695, | |
| VUNPCKHPSYrr = 3696, | |
| VUNPCKHPSrm = 3697, | |
| VUNPCKHPSrr = 3698, | |
| VUNPCKLPDYrm = 3699, | |
| VUNPCKLPDYrr = 3700, | |
| VUNPCKLPDrm = 3701, | |
| VUNPCKLPDrr = 3702, | |
| VUNPCKLPSYrm = 3703, | |
| VUNPCKLPSYrr = 3704, | |
| VUNPCKLPSrm = 3705, | |
| VUNPCKLPSrr = 3706, | |
| VXORPDYrm = 3707, | |
| VXORPDYrr = 3708, | |
| VXORPDrm = 3709, | |
| VXORPDrr = 3710, | |
| VXORPSYrm = 3711, | |
| VXORPSYrr = 3712, | |
| VXORPSrm = 3713, | |
| VXORPSrr = 3714, | |
| VZEROALL = 3715, | |
| VZEROUPPER = 3716, | |
| V_SET0 = 3717, | |
| V_SETALLONES = 3718, | |
| W64ALLOCA = 3719, | |
| WAIT = 3720, | |
| WBINVD = 3721, | |
| WINCALL64m = 3722, | |
| WINCALL64pcrel32 = 3723, | |
| WINCALL64r = 3724, | |
| WIN_ALLOCA = 3725, | |
| WRFSBASE = 3726, | |
| WRFSBASE64 = 3727, | |
| WRGSBASE = 3728, | |
| WRGSBASE64 = 3729, | |
| WRMSR = 3730, | |
| XADD16rm = 3731, | |
| XADD16rr = 3732, | |
| XADD32rm = 3733, | |
| XADD32rr = 3734, | |
| XADD64rm = 3735, | |
| XADD64rr = 3736, | |
| XADD8rm = 3737, | |
| XADD8rr = 3738, | |
| XCHG16ar = 3739, | |
| XCHG16rm = 3740, | |
| XCHG16rr = 3741, | |
| XCHG32ar = 3742, | |
| XCHG32ar64 = 3743, | |
| XCHG32rm = 3744, | |
| XCHG32rr = 3745, | |
| XCHG64ar = 3746, | |
| XCHG64rm = 3747, | |
| XCHG64rr = 3748, | |
| XCHG8rm = 3749, | |
| XCHG8rr = 3750, | |
| XCH_F = 3751, | |
| XCRYPTCBC = 3752, | |
| XCRYPTCFB = 3753, | |
| XCRYPTCTR = 3754, | |
| XCRYPTECB = 3755, | |
| XCRYPTOFB = 3756, | |
| XGETBV = 3757, | |
| XLAT = 3758, | |
| XOR16i16 = 3759, | |
| XOR16mi = 3760, | |
| XOR16mi8 = 3761, | |
| XOR16mr = 3762, | |
| XOR16ri = 3763, | |
| XOR16ri8 = 3764, | |
| XOR16rm = 3765, | |
| XOR16rr = 3766, | |
| XOR16rr_REV = 3767, | |
| XOR32i32 = 3768, | |
| XOR32mi = 3769, | |
| XOR32mi8 = 3770, | |
| XOR32mr = 3771, | |
| XOR32ri = 3772, | |
| XOR32ri8 = 3773, | |
| XOR32rm = 3774, | |
| XOR32rr = 3775, | |
| XOR32rr_REV = 3776, | |
| XOR64i32 = 3777, | |
| XOR64mi32 = 3778, | |
| XOR64mi8 = 3779, | |
| XOR64mr = 3780, | |
| XOR64ri32 = 3781, | |
| XOR64ri8 = 3782, | |
| XOR64rm = 3783, | |
| XOR64rr = 3784, | |
| XOR64rr_REV = 3785, | |
| XOR8i8 = 3786, | |
| XOR8mi = 3787, | |
| XOR8mr = 3788, | |
| XOR8ri = 3789, | |
| XOR8rm = 3790, | |
| XOR8rr = 3791, | |
| XOR8rr_REV = 3792, | |
| XORPDrm = 3793, | |
| XORPDrr = 3794, | |
| XORPSrm = 3795, | |
| XORPSrr = 3796, | |
| XRSTOR = 3797, | |
| XRSTOR64 = 3798, | |
| XSAVE = 3799, | |
| XSAVE64 = 3800, | |
| XSAVEOPT = 3801, | |
| XSAVEOPT64 = 3802, | |
| XSETBV = 3803, | |
| XSHA1 = 3804, | |
| XSHA256 = 3805, | |
| XSTORE = 3806, | |
| INSTRUCTION_LIST_END = 3807 | |
| }; | |
| } | |
| } // End llvm namespace | |
| #endif // GET_INSTRINFO_ENUM | |
| //===- TableGen'erated file -------------------------------------*- C++ -*-===// | |
| // | |
| // Target Instruction Descriptors | |
| // | |
| // Automatically generated file, do not edit! | |
| // | |
| //===----------------------------------------------------------------------===// | |
| #ifdef GET_INSTRINFO_MC_DESC | |
| #undef GET_INSTRINFO_MC_DESC | |
| namespace llvm { | |
| static const unsigned ImplicitList1[] = { X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList2[] = { X86::AX, 0 }; | |
| static const unsigned ImplicitList3[] = { X86::EAX, 0 }; | |
| static const unsigned ImplicitList4[] = { X86::RAX, 0 }; | |
| static const unsigned ImplicitList5[] = { X86::AL, 0 }; | |
| static const unsigned ImplicitList6[] = { X86::ESP, 0 }; | |
| static const unsigned ImplicitList7[] = { X86::ESP, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList8[] = { X86::RSP, 0 }; | |
| static const unsigned ImplicitList9[] = { X86::RSP, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList10[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0 }; | |
| static const unsigned ImplicitList11[] = { X86::EFLAGS, X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0 }; | |
| static const unsigned ImplicitList12[] = { X86::XMM0, 0 }; | |
| static const unsigned ImplicitList13[] = { X86::EAX, X86::ECX, X86::EDX, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList14[] = { X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, X86::ST1, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList15[] = { X86::EAX, X86::EDX, 0 }; | |
| static const unsigned ImplicitList16[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, 0 }; | |
| static const unsigned ImplicitList17[] = { X86::RAX, X86::RDX, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList18[] = { X86::EAX, X86::EDX, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList19[] = { X86::RAX, X86::RDX, 0 }; | |
| static const unsigned ImplicitList20[] = { X86::AX, X86::DX, 0 }; | |
| static const unsigned ImplicitList21[] = { X86::AX, X86::DX, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList22[] = { X86::AL, X86::EFLAGS, X86::AX, 0 }; | |
| static const unsigned ImplicitList23[] = { X86::DX, 0 }; | |
| static const unsigned ImplicitList24[] = { X86::CX, 0 }; | |
| static const unsigned ImplicitList25[] = { X86::ECX, 0 }; | |
| static const unsigned ImplicitList26[] = { X86::RCX, 0 }; | |
| static const unsigned ImplicitList27[] = { X86::AH, 0 }; | |
| static const unsigned ImplicitList28[] = { X86::AX, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList29[] = { X86::EAX, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList30[] = { X86::RAX, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList31[] = { X86::AL, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList32[] = { X86::EBP, X86::ESP, 0 }; | |
| static const unsigned ImplicitList33[] = { X86::RBP, X86::RSP, 0 }; | |
| static const unsigned ImplicitList34[] = { X86::EDI, 0 }; | |
| static const unsigned ImplicitList35[] = { X86::RDI, 0 }; | |
| static const unsigned ImplicitList36[] = { X86::EAX, X86::ECX, X86::EDX, 0 }; | |
| static const unsigned ImplicitList37[] = { X86::RAX, X86::RSI, 0 }; | |
| static const unsigned ImplicitList38[] = { X86::RAX, X86::RDX, X86::RSI, 0 }; | |
| static const unsigned ImplicitList39[] = { X86::EDI, X86::ESI, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList40[] = { X86::EDI, X86::ESI, 0 }; | |
| static const unsigned ImplicitList41[] = { X86::ECX, X86::EAX, 0 }; | |
| static const unsigned ImplicitList42[] = { X86::DX, X86::AX, 0 }; | |
| static const unsigned ImplicitList43[] = { X86::DX, X86::EAX, 0 }; | |
| static const unsigned ImplicitList44[] = { X86::DX, X86::AL, 0 }; | |
| static const unsigned ImplicitList45[] = { X86::ECX, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList46[] = { X86::XMM0, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList47[] = { X86::EDI, X86::ESI, X86::EBP, X86::EBX, X86::EDX, X86::ECX, X86::EAX, X86::ESP, 0 }; | |
| static const unsigned ImplicitList48[] = { X86::CL, 0 }; | |
| static const unsigned ImplicitList49[] = { X86::RAX, X86::RCX, X86::RDX, 0 }; | |
| static const unsigned ImplicitList50[] = { X86::ECX, X86::EDI, X86::ESI, 0 }; | |
| static const unsigned ImplicitList51[] = { X86::RCX, X86::RDI, X86::RSI, 0 }; | |
| static const unsigned ImplicitList52[] = { X86::AL, X86::ECX, X86::EDI, 0 }; | |
| static const unsigned ImplicitList53[] = { X86::ECX, X86::EDI, 0 }; | |
| static const unsigned ImplicitList54[] = { X86::EAX, X86::ECX, X86::EDI, 0 }; | |
| static const unsigned ImplicitList55[] = { X86::RAX, X86::RCX, X86::RDI, 0 }; | |
| static const unsigned ImplicitList56[] = { X86::RCX, X86::RDI, 0 }; | |
| static const unsigned ImplicitList57[] = { X86::AX, X86::ECX, X86::EDI, 0 }; | |
| static const unsigned ImplicitList58[] = { X86::ESP, X86::EAX, 0 }; | |
| static const unsigned ImplicitList59[] = { X86::EAX, X86::ESP, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList60[] = { X86::RSP, X86::RAX, 0 }; | |
| static const unsigned ImplicitList61[] = { X86::RAX, X86::RSP, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList62[] = { X86::AL, X86::EDI, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList63[] = { X86::EAX, X86::EDI, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList64[] = { X86::RAX, X86::RCX, X86::RDI, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList65[] = { X86::AX, X86::EDI, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList66[] = { X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, X86::ST0, X86::ST1, X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList67[] = { X86::EAX, X86::ECX, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList68[] = { X86::RSP, X86::RDI, 0 }; | |
| static const unsigned ImplicitList69[] = { X86::ST0, 0 }; | |
| static const unsigned ImplicitList70[] = { X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 }; | |
| static const unsigned ImplicitList71[] = { X86::RAX, X86::R10, X86::R11, X86::RSP, X86::EFLAGS, 0 }; | |
| static const unsigned ImplicitList72[] = { X86::RBX, X86::RDX, X86::RSI, X86::RDI, 0 }; | |
| static const unsigned ImplicitList73[] = { X86::RSI, X86::RDI, 0 }; | |
| static const unsigned ImplicitList74[] = { X86::RDX, X86::RAX, 0 }; | |
| static const unsigned ImplicitList75[] = { X86::RDX, X86::RAX, X86::RCX, 0 }; | |
| static const unsigned ImplicitList76[] = { X86::RAX, X86::RSI, X86::RDI, 0 }; | |
| static const unsigned ImplicitList77[] = { X86::RDX, X86::RDI, 0 }; | |
| static const unsigned ImplicitList78[] = { X86::RAX, X86::RDI, 0 }; | |
| static const MCOperandInfo OperandInfo2[] = { { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo3[] = { { -1, 0, 0, MCOI::OPERAND_UNKNOWN }, { -1, 0, 0, MCOI::OPERAND_UNKNOWN }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo4[] = { { -1, 0, 0, MCOI::OPERAND_UNKNOWN }, { -1, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_UNKNOWN }, { -1, 0, 0, MCOI::OPERAND_UNKNOWN }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo5[] = { { -1, 0, 0, MCOI::OPERAND_UNKNOWN }, }; | |
| static const MCOperandInfo OperandInfo6[] = { { -1, 0, 0, MCOI::OPERAND_UNKNOWN }, { -1, 0, 0, MCOI::OPERAND_UNKNOWN }, { -1, 0, 0, MCOI::OPERAND_UNKNOWN }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo7[] = { { -1, 0, 0, MCOI::OPERAND_UNKNOWN }, { -1, 0, 0, MCOI::OPERAND_UNKNOWN }, }; | |
| static const MCOperandInfo OperandInfo8[] = { { X86::RFP32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo9[] = { { X86::RFP64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo10[] = { { X86::RFP80RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP80RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo11[] = { { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo12[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo13[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo14[] = { { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo15[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo16[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo17[] = { { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo18[] = { { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo19[] = { { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo20[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo21[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo22[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo23[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo24[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo25[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo26[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo27[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo28[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo29[] = { { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo30[] = { { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo31[] = { { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo32[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo33[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo34[] = { { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo35[] = { { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo36[] = { { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo37[] = { { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo38[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo39[] = { { X86::RSTRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo40[] = { { X86::RFP32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo41[] = { { X86::RFP32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo42[] = { { X86::RFP64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo43[] = { { X86::RFP64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo44[] = { { X86::RFP80RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP80RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP80RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo45[] = { { X86::RFP80RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP80RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo46[] = { { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo47[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo48[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo49[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo50[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo51[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo52[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo53[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo54[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo55[] = { { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo56[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, ((1 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo57[] = { { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo58[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo59[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo60[] = { { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo61[] = { { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo62[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo63[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo64[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo65[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo66[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo67[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo68[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo69[] = { { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo70[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo71[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo72[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo73[] = { { -1, 0, 0, MCOI::OPERAND_PCREL }, }; | |
| static const MCOperandInfo OperandInfo74[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo75[] = { { X86::RFP32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP32RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::RFP32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo76[] = { { X86::RFP64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::RFP64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo77[] = { { X86::RFP80RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP80RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::RFP80RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo78[] = { { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo79[] = { { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo80[] = { { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo81[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo82[] = { { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo83[] = { { X86::RFP32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo84[] = { { X86::RFP64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo85[] = { { X86::RFP80RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP80RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::RFP80RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo86[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo87[] = { { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo88[] = { { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo89[] = { { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo90[] = { { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo91[] = { { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo92[] = { { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo93[] = { { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo94[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo95[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo96[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo97[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo98[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo99[] = { { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo100[] = { { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo101[] = { { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo102[] = { { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo103[] = { { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo104[] = { { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo105[] = { { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo106[] = { { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo107[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo108[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo109[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo110[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo111[] = { { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo112[] = { { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR8RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo113[] = { { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo114[] = { { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo115[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo116[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo117[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::RFP32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo118[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::RFP64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo119[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::RFP80RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo120[] = { { X86::RFP80RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo121[] = { { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo122[] = { { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo123[] = { { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo124[] = { { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo125[] = { { X86::RFP32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo126[] = { { X86::RFP64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo127[] = { { X86::RFP80RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo128[] = { { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo129[] = { { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo130[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo131[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo132[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo133[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo134[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo135[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo136[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo137[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo138[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo139[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo140[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo141[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo142[] = { { X86::RFP32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo143[] = { { X86::RFP64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo144[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_UNKNOWN }, { -1, 0, 0, MCOI::OPERAND_UNKNOWN }, { X86::GR32_NOSPRegClassID, 0, 0, MCOI::OPERAND_UNKNOWN }, { -1, 0, 0, MCOI::OPERAND_UNKNOWN }, { -1, 0, 0, MCOI::OPERAND_UNKNOWN }, }; | |
| static const MCOperandInfo OperandInfo145[] = { { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo146[] = { { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo147[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo148[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo149[] = { { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo150[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo151[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo152[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo153[] = { { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo154[] = { { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo155[] = { { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo156[] = { { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo157[] = { { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo158[] = { { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo159[] = { { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo160[] = { { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo161[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo162[] = { { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo163[] = { { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo164[] = { { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo165[] = { { X86::VR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo166[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo167[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::SEGMENT_REGRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo168[] = { { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::SEGMENT_REGRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo169[] = { { X86::SEGMENT_REGRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo170[] = { { X86::SEGMENT_REGRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo171[] = { { X86::CONTROL_REGRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo172[] = { { X86::DEBUG_REGRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo173[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::CONTROL_REGRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo174[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::DEBUG_REGRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo175[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::SEGMENT_REGRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo176[] = { { X86::SEGMENT_REGRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo177[] = { { X86::CONTROL_REGRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo178[] = { { X86::DEBUG_REGRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo179[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::CONTROL_REGRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo180[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::DEBUG_REGRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo181[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::SEGMENT_REGRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo182[] = { { X86::SEGMENT_REGRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo183[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo184[] = { { X86::GR64_NOREXRegClassID, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR64_NOREX_NOSPRegClassID, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR8_NOREXRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo185[] = { { X86::GR8_NOREXRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64_NOREXRegClassID, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR64_NOREX_NOSPRegClassID, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo186[] = { { X86::GR8_NOREXRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR8_NOREXRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo187[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo188[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo189[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo190[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo191[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo192[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo193[] = { { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo194[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo195[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo196[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo197[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo198[] = { { X86::GR32_NOREXRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64_NOREXRegClassID, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR64_NOREX_NOSPRegClassID, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo199[] = { { X86::GR32_NOREXRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR8_NOREXRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo200[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo201[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo202[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo203[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo204[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo205[] = { { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::GR16RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo206[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo207[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo208[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo209[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, ((0 << 16) | (1 << MCOI::TIED_TO)), MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo210[] = { { X86::GR32_TCRegClassID, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR32_TCRegClassID, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo211[] = { { 2, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 2, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo212[] = { { X86::GR32_TCRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo213[] = { { 2, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_UNKNOWN }, }; | |
| static const MCOperandInfo OperandInfo214[] = { { -1, 0, 0, MCOI::OPERAND_PCREL }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo215[] = { { X86::GR32_TCRegClassID, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::GR32_TCRegClassID, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo216[] = { { 2, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 2, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo217[] = { { X86::GR32_TCRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo218[] = { { 2, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_UNKNOWN }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo219[] = { { X86::GR8_NOREXRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo220[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo221[] = { { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo222[] = { { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo223[] = { { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo224[] = { { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo225[] = { { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo226[] = { { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo227[] = { { X86::GR8RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo228[] = { { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo229[] = { { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo230[] = { { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo231[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo232[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo233[] = { { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo234[] = { { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo235[] = { { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo236[] = { { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo237[] = { { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo238[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo239[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo240[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo241[] = { { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo242[] = { { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo243[] = { { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo244[] = { { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo245[] = { { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo246[] = { { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo247[] = { { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, }; | |
| static const MCOperandInfo OperandInfo248[] = { { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo249[] = { { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo250[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo251[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo252[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo253[] = { { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo254[] = { { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo255[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo256[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::FR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo257[] = { { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo258[] = { { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR256RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo259[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR32RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo260[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { X86::GR64RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { -1, 0, 0, MCOI::OPERAND_IMMEDIATE }, }; | |
| static const MCOperandInfo OperandInfo261[] = { { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, { 0, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { 1, 0|(1<<MCOI::LookupPtrRegClass), 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { -1, 0, 0, MCOI::OPERAND_MEMORY }, { X86::VR128RegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| static const MCOperandInfo OperandInfo262[] = { { X86::GR32_NOAXRegClassID, 0, 0, MCOI::OPERAND_REGISTER }, }; | |
| MCInstrDesc X86Insts[] = { | |
| { 0, 0, 0, 0, 0, "PHI", 0|(1<<MCID::Pseudo)|(1<<MCID::Variadic)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, 0 }, // Inst #0 = PHI | |
| { 1, 0, 0, 0, 0, "INLINEASM", 0|(1<<MCID::Pseudo)|(1<<MCID::Variadic), 0x0ULL, NULL, NULL, 0 }, // Inst #1 = INLINEASM | |
| { 2, 1, 0, 0, 0, "PROLOG_LABEL", 0|(1<<MCID::Pseudo)|(1<<MCID::NotDuplicable)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo2 }, // Inst #2 = PROLOG_LABEL | |
| { 3, 1, 0, 0, 0, "EH_LABEL", 0|(1<<MCID::Pseudo)|(1<<MCID::NotDuplicable)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo2 }, // Inst #3 = EH_LABEL | |
| { 4, 1, 0, 0, 0, "GC_LABEL", 0|(1<<MCID::Pseudo)|(1<<MCID::NotDuplicable)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo2 }, // Inst #4 = GC_LABEL | |
| { 5, 0, 0, 0, 0, "KILL", 0|(1<<MCID::Pseudo)|(1<<MCID::Variadic), 0x0ULL, NULL, NULL, 0 }, // Inst #5 = KILL | |
| { 6, 3, 1, 0, 0, "EXTRACT_SUBREG", 0|(1<<MCID::Pseudo), 0x0ULL, NULL, NULL, OperandInfo3 }, // Inst #6 = EXTRACT_SUBREG | |
| { 7, 4, 1, 0, 0, "INSERT_SUBREG", 0|(1<<MCID::Pseudo), 0x0ULL, NULL, NULL, OperandInfo4 }, // Inst #7 = INSERT_SUBREG | |
| { 8, 1, 1, 0, 0, "IMPLICIT_DEF", 0|(1<<MCID::Pseudo)|(1<<MCID::Rematerializable)|(1<<MCID::CheapAsAMove), 0x0ULL, NULL, NULL, OperandInfo5 }, // Inst #8 = IMPLICIT_DEF | |
| { 9, 4, 1, 0, 0, "SUBREG_TO_REG", 0|(1<<MCID::Pseudo), 0x0ULL, NULL, NULL, OperandInfo6 }, // Inst #9 = SUBREG_TO_REG | |
| { 10, 3, 1, 0, 0, "COPY_TO_REGCLASS", 0|(1<<MCID::Pseudo)|(1<<MCID::CheapAsAMove), 0x0ULL, NULL, NULL, OperandInfo3 }, // Inst #10 = COPY_TO_REGCLASS | |
| { 11, 0, 0, 0, 0, "DBG_VALUE", 0|(1<<MCID::Pseudo)|(1<<MCID::Variadic), 0x0ULL, NULL, NULL, 0 }, // Inst #11 = DBG_VALUE | |
| { 12, 1, 1, 0, 0, "REG_SEQUENCE", 0|(1<<MCID::Pseudo)|(1<<MCID::Variadic)|(1<<MCID::CheapAsAMove), 0x0ULL, NULL, NULL, OperandInfo5 }, // Inst #12 = REG_SEQUENCE | |
| { 13, 2, 1, 0, 0, "COPY", 0|(1<<MCID::Pseudo)|(1<<MCID::CheapAsAMove), 0x0ULL, NULL, NULL, OperandInfo7 }, // Inst #13 = COPY | |
| { 14, 0, 0, 0, 0, "AAA", 0|(1<<MCID::UnmodeledSideEffects), 0x6e000001ULL, NULL, NULL, 0 }, // Inst #14 = AAA | |
| { 15, 1, 0, 0, 0, "AAD8i8", 0|(1<<MCID::UnmodeledSideEffects), 0x1aa004001ULL, NULL, NULL, OperandInfo2 }, // Inst #15 = AAD8i8 | |
| { 16, 1, 0, 0, 0, "AAM8i8", 0|(1<<MCID::UnmodeledSideEffects), 0x1a8004001ULL, NULL, NULL, OperandInfo2 }, // Inst #16 = AAM8i8 | |
| { 17, 0, 0, 0, 0, "AAS", 0|(1<<MCID::UnmodeledSideEffects), 0x7e000001ULL, NULL, NULL, 0 }, // Inst #17 = AAS | |
| { 18, 0, 0, 0, 0, "ABS_F", 0|(1<<MCID::UnmodeledSideEffects), 0x1c2000401ULL, NULL, NULL, 0 }, // Inst #18 = ABS_F | |
| { 19, 2, 1, 0, 0, "ABS_Fp32", 0, 0x60000ULL, NULL, NULL, OperandInfo8 }, // Inst #19 = ABS_Fp32 | |
| { 20, 2, 1, 0, 0, "ABS_Fp64", 0, 0x60000ULL, NULL, NULL, OperandInfo9 }, // Inst #20 = ABS_Fp64 | |
| { 21, 2, 1, 0, 0, "ABS_Fp80", 0, 0x60000ULL, NULL, NULL, OperandInfo10 }, // Inst #21 = ABS_Fp80 | |
| { 22, 6, 1, 0, 0, "ACQUIRE_MOV16rm", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x0ULL, NULL, NULL, OperandInfo11 }, // Inst #22 = ACQUIRE_MOV16rm | |
| { 23, 6, 1, 0, 0, "ACQUIRE_MOV32rm", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x0ULL, NULL, NULL, OperandInfo12 }, // Inst #23 = ACQUIRE_MOV32rm | |
| { 24, 6, 1, 0, 0, "ACQUIRE_MOV64rm", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x0ULL, NULL, NULL, OperandInfo13 }, // Inst #24 = ACQUIRE_MOV64rm | |
| { 25, 6, 1, 0, 0, "ACQUIRE_MOV8rm", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x0ULL, NULL, NULL, OperandInfo14 }, // Inst #25 = ACQUIRE_MOV8rm | |
| { 26, 1, 0, 0, 0, "ADC16i16", 0|(1<<MCID::UnmodeledSideEffects), 0x2a00c041ULL, ImplicitList1, ImplicitList1, OperandInfo2 }, // Inst #26 = ADC16i16 | |
| { 27, 6, 0, 0, 0, "ADC16mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10200c05aULL, ImplicitList1, ImplicitList1, OperandInfo15 }, // Inst #27 = ADC16mi | |
| { 28, 6, 0, 0, 0, "ADC16mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10600405aULL, ImplicitList1, ImplicitList1, OperandInfo15 }, // Inst #28 = ADC16mi8 | |
| { 29, 6, 0, 0, 0, "ADC16mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x22000044ULL, ImplicitList1, ImplicitList1, OperandInfo16 }, // Inst #29 = ADC16mr | |
| { 30, 3, 1, 0, 0, "ADC16ri", 0, 0x10200c052ULL, ImplicitList1, ImplicitList1, OperandInfo17 }, // Inst #30 = ADC16ri | |
| { 31, 3, 1, 0, 0, "ADC16ri8", 0, 0x106004052ULL, ImplicitList1, ImplicitList1, OperandInfo17 }, // Inst #31 = ADC16ri8 | |
| { 32, 7, 1, 0, 0, "ADC16rm", 0|(1<<MCID::MayLoad), 0x26000046ULL, ImplicitList1, ImplicitList1, OperandInfo18 }, // Inst #32 = ADC16rm | |
| { 33, 3, 1, 0, 0, "ADC16rr", 0|(1<<MCID::Commutable), 0x22000043ULL, ImplicitList1, ImplicitList1, OperandInfo19 }, // Inst #33 = ADC16rr | |
| { 34, 3, 1, 0, 0, "ADC16rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x26000045ULL, ImplicitList1, ImplicitList1, OperandInfo19 }, // Inst #34 = ADC16rr_REV | |
| { 35, 1, 0, 0, 0, "ADC32i32", 0|(1<<MCID::UnmodeledSideEffects), 0x2a014001ULL, ImplicitList1, ImplicitList1, OperandInfo2 }, // Inst #35 = ADC32i32 | |
| { 36, 6, 0, 0, 0, "ADC32mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10201401aULL, ImplicitList1, ImplicitList1, OperandInfo15 }, // Inst #36 = ADC32mi | |
| { 37, 6, 0, 0, 0, "ADC32mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10600401aULL, ImplicitList1, ImplicitList1, OperandInfo15 }, // Inst #37 = ADC32mi8 | |
| { 38, 6, 0, 0, 0, "ADC32mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x22000004ULL, ImplicitList1, ImplicitList1, OperandInfo20 }, // Inst #38 = ADC32mr | |
| { 39, 3, 1, 0, 0, "ADC32ri", 0, 0x102014012ULL, ImplicitList1, ImplicitList1, OperandInfo21 }, // Inst #39 = ADC32ri | |
| { 40, 3, 1, 0, 0, "ADC32ri8", 0, 0x106004012ULL, ImplicitList1, ImplicitList1, OperandInfo21 }, // Inst #40 = ADC32ri8 | |
| { 41, 7, 1, 0, 0, "ADC32rm", 0|(1<<MCID::MayLoad), 0x26000006ULL, ImplicitList1, ImplicitList1, OperandInfo22 }, // Inst #41 = ADC32rm | |
| { 42, 3, 1, 0, 0, "ADC32rr", 0|(1<<MCID::Commutable), 0x22000003ULL, ImplicitList1, ImplicitList1, OperandInfo23 }, // Inst #42 = ADC32rr | |
| { 43, 3, 1, 0, 0, "ADC32rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x26000005ULL, ImplicitList1, ImplicitList1, OperandInfo23 }, // Inst #43 = ADC32rr_REV | |
| { 44, 1, 0, 0, 0, "ADC64i32", 0|(1<<MCID::UnmodeledSideEffects), 0x2a016001ULL, ImplicitList1, ImplicitList1, OperandInfo2 }, // Inst #44 = ADC64i32 | |
| { 45, 6, 0, 0, 0, "ADC64mi32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10201601aULL, ImplicitList1, ImplicitList1, OperandInfo15 }, // Inst #45 = ADC64mi32 | |
| { 46, 6, 0, 0, 0, "ADC64mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10600601aULL, ImplicitList1, ImplicitList1, OperandInfo15 }, // Inst #46 = ADC64mi8 | |
| { 47, 6, 0, 0, 0, "ADC64mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x22002004ULL, ImplicitList1, ImplicitList1, OperandInfo24 }, // Inst #47 = ADC64mr | |
| { 48, 3, 1, 0, 0, "ADC64ri32", 0, 0x102016012ULL, ImplicitList1, ImplicitList1, OperandInfo25 }, // Inst #48 = ADC64ri32 | |
| { 49, 3, 1, 0, 0, "ADC64ri8", 0, 0x106006012ULL, ImplicitList1, ImplicitList1, OperandInfo25 }, // Inst #49 = ADC64ri8 | |
| { 50, 7, 1, 0, 0, "ADC64rm", 0|(1<<MCID::MayLoad), 0x26002006ULL, ImplicitList1, ImplicitList1, OperandInfo26 }, // Inst #50 = ADC64rm | |
| { 51, 3, 1, 0, 0, "ADC64rr", 0|(1<<MCID::Commutable), 0x22002003ULL, ImplicitList1, ImplicitList1, OperandInfo27 }, // Inst #51 = ADC64rr | |
| { 52, 3, 1, 0, 0, "ADC64rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x26002005ULL, ImplicitList1, ImplicitList1, OperandInfo27 }, // Inst #52 = ADC64rr_REV | |
| { 53, 1, 0, 0, 0, "ADC8i8", 0|(1<<MCID::UnmodeledSideEffects), 0x28004001ULL, ImplicitList1, ImplicitList1, OperandInfo2 }, // Inst #53 = ADC8i8 | |
| { 54, 6, 0, 0, 0, "ADC8mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10000401aULL, ImplicitList1, ImplicitList1, OperandInfo15 }, // Inst #54 = ADC8mi | |
| { 55, 6, 0, 0, 0, "ADC8mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x20000004ULL, ImplicitList1, ImplicitList1, OperandInfo28 }, // Inst #55 = ADC8mr | |
| { 56, 3, 1, 0, 0, "ADC8ri", 0, 0x100004012ULL, ImplicitList1, ImplicitList1, OperandInfo29 }, // Inst #56 = ADC8ri | |
| { 57, 7, 1, 0, 0, "ADC8rm", 0|(1<<MCID::MayLoad), 0x24000006ULL, ImplicitList1, ImplicitList1, OperandInfo30 }, // Inst #57 = ADC8rm | |
| { 58, 3, 1, 0, 0, "ADC8rr", 0|(1<<MCID::Commutable), 0x20000003ULL, ImplicitList1, ImplicitList1, OperandInfo31 }, // Inst #58 = ADC8rr | |
| { 59, 3, 1, 0, 0, "ADC8rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x24000005ULL, ImplicitList1, ImplicitList1, OperandInfo31 }, // Inst #59 = ADC8rr_REV | |
| { 60, 1, 0, 0, 0, "ADD16i16", 0|(1<<MCID::UnmodeledSideEffects), 0xa00c041ULL, ImplicitList2, ImplicitList1, OperandInfo2 }, // Inst #60 = ADD16i16 | |
| { 61, 6, 0, 0, 0, "ADD16mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10200c058ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #61 = ADD16mi | |
| { 62, 6, 0, 0, 0, "ADD16mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x106004058ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #62 = ADD16mi8 | |
| { 63, 6, 0, 0, 0, "ADD16mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x2000044ULL, NULL, ImplicitList1, OperandInfo16 }, // Inst #63 = ADD16mr | |
| { 64, 3, 1, 0, 0, "ADD16ri", 0|(1<<MCID::ConvertibleTo3Addr), 0x10200c050ULL, NULL, ImplicitList1, OperandInfo17 }, // Inst #64 = ADD16ri | |
| { 65, 3, 1, 0, 0, "ADD16ri8", 0|(1<<MCID::ConvertibleTo3Addr), 0x106004050ULL, NULL, ImplicitList1, OperandInfo17 }, // Inst #65 = ADD16ri8 | |
| { 66, 3, 1, 0, 0, "ADD16ri8_DB", 0|(1<<MCID::ConvertibleTo3Addr), 0x0ULL, NULL, ImplicitList1, OperandInfo17 }, // Inst #66 = ADD16ri8_DB | |
| { 67, 3, 1, 0, 0, "ADD16ri_DB", 0|(1<<MCID::ConvertibleTo3Addr), 0x0ULL, NULL, ImplicitList1, OperandInfo17 }, // Inst #67 = ADD16ri_DB | |
| { 68, 7, 1, 0, 0, "ADD16rm", 0|(1<<MCID::MayLoad), 0x6000046ULL, NULL, ImplicitList1, OperandInfo18 }, // Inst #68 = ADD16rm | |
| { 69, 3, 1, 0, 0, "ADD16rr", 0|(1<<MCID::ConvertibleTo3Addr)|(1<<MCID::Commutable), 0x2000043ULL, NULL, ImplicitList1, OperandInfo19 }, // Inst #69 = ADD16rr | |
| { 70, 3, 1, 0, 0, "ADD16rr_DB", 0|(1<<MCID::ConvertibleTo3Addr)|(1<<MCID::Commutable), 0x0ULL, NULL, ImplicitList1, OperandInfo19 }, // Inst #70 = ADD16rr_DB | |
| { 71, 3, 1, 0, 0, "ADD16rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x6000045ULL, NULL, ImplicitList1, OperandInfo19 }, // Inst #71 = ADD16rr_REV | |
| { 72, 1, 0, 0, 0, "ADD32i32", 0|(1<<MCID::UnmodeledSideEffects), 0xa014001ULL, ImplicitList3, ImplicitList1, OperandInfo2 }, // Inst #72 = ADD32i32 | |
| { 73, 6, 0, 0, 0, "ADD32mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x102014018ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #73 = ADD32mi | |
| { 74, 6, 0, 0, 0, "ADD32mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x106004018ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #74 = ADD32mi8 | |
| { 75, 6, 0, 0, 0, "ADD32mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x2000004ULL, NULL, ImplicitList1, OperandInfo20 }, // Inst #75 = ADD32mr | |
| { 76, 3, 1, 0, 0, "ADD32ri", 0|(1<<MCID::ConvertibleTo3Addr), 0x102014010ULL, NULL, ImplicitList1, OperandInfo21 }, // Inst #76 = ADD32ri | |
| { 77, 3, 1, 0, 0, "ADD32ri8", 0|(1<<MCID::ConvertibleTo3Addr), 0x106004010ULL, NULL, ImplicitList1, OperandInfo21 }, // Inst #77 = ADD32ri8 | |
| { 78, 3, 1, 0, 0, "ADD32ri8_DB", 0|(1<<MCID::ConvertibleTo3Addr), 0x0ULL, NULL, ImplicitList1, OperandInfo21 }, // Inst #78 = ADD32ri8_DB | |
| { 79, 3, 1, 0, 0, "ADD32ri_DB", 0|(1<<MCID::ConvertibleTo3Addr), 0x0ULL, NULL, ImplicitList1, OperandInfo21 }, // Inst #79 = ADD32ri_DB | |
| { 80, 7, 1, 0, 0, "ADD32rm", 0|(1<<MCID::MayLoad), 0x6000006ULL, NULL, ImplicitList1, OperandInfo22 }, // Inst #80 = ADD32rm | |
| { 81, 3, 1, 0, 0, "ADD32rr", 0|(1<<MCID::ConvertibleTo3Addr)|(1<<MCID::Commutable), 0x2000003ULL, NULL, ImplicitList1, OperandInfo23 }, // Inst #81 = ADD32rr | |
| { 82, 3, 1, 0, 0, "ADD32rr_DB", 0|(1<<MCID::ConvertibleTo3Addr)|(1<<MCID::Commutable), 0x0ULL, NULL, ImplicitList1, OperandInfo23 }, // Inst #82 = ADD32rr_DB | |
| { 83, 3, 1, 0, 0, "ADD32rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x6000005ULL, NULL, ImplicitList1, OperandInfo23 }, // Inst #83 = ADD32rr_REV | |
| { 84, 1, 0, 0, 0, "ADD64i32", 0|(1<<MCID::UnmodeledSideEffects), 0xa016001ULL, ImplicitList4, ImplicitList1, OperandInfo2 }, // Inst #84 = ADD64i32 | |
| { 85, 6, 0, 0, 0, "ADD64mi32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x102016018ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #85 = ADD64mi32 | |
| { 86, 6, 0, 0, 0, "ADD64mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x106006018ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #86 = ADD64mi8 | |
| { 87, 6, 0, 0, 0, "ADD64mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x2002004ULL, NULL, ImplicitList1, OperandInfo24 }, // Inst #87 = ADD64mr | |
| { 88, 3, 1, 0, 0, "ADD64ri32", 0|(1<<MCID::ConvertibleTo3Addr), 0x102016010ULL, NULL, ImplicitList1, OperandInfo25 }, // Inst #88 = ADD64ri32 | |
| { 89, 3, 1, 0, 0, "ADD64ri32_DB", 0|(1<<MCID::ConvertibleTo3Addr), 0x0ULL, NULL, ImplicitList1, OperandInfo25 }, // Inst #89 = ADD64ri32_DB | |
| { 90, 3, 1, 0, 0, "ADD64ri8", 0|(1<<MCID::ConvertibleTo3Addr), 0x106006010ULL, NULL, ImplicitList1, OperandInfo25 }, // Inst #90 = ADD64ri8 | |
| { 91, 3, 1, 0, 0, "ADD64ri8_DB", 0|(1<<MCID::ConvertibleTo3Addr), 0x0ULL, NULL, ImplicitList1, OperandInfo25 }, // Inst #91 = ADD64ri8_DB | |
| { 92, 7, 1, 0, 0, "ADD64rm", 0|(1<<MCID::MayLoad), 0x6002006ULL, NULL, ImplicitList1, OperandInfo26 }, // Inst #92 = ADD64rm | |
| { 93, 3, 1, 0, 0, "ADD64rr", 0|(1<<MCID::ConvertibleTo3Addr)|(1<<MCID::Commutable), 0x2002003ULL, NULL, ImplicitList1, OperandInfo27 }, // Inst #93 = ADD64rr | |
| { 94, 3, 1, 0, 0, "ADD64rr_DB", 0|(1<<MCID::ConvertibleTo3Addr)|(1<<MCID::Commutable), 0x0ULL, NULL, ImplicitList1, OperandInfo27 }, // Inst #94 = ADD64rr_DB | |
| { 95, 3, 1, 0, 0, "ADD64rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x6002005ULL, NULL, ImplicitList1, OperandInfo27 }, // Inst #95 = ADD64rr_REV | |
| { 96, 1, 0, 0, 0, "ADD8i8", 0|(1<<MCID::UnmodeledSideEffects), 0x8004001ULL, ImplicitList5, ImplicitList1, OperandInfo2 }, // Inst #96 = ADD8i8 | |
| { 97, 6, 0, 0, 0, "ADD8mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x100004018ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #97 = ADD8mi | |
| { 98, 6, 0, 0, 0, "ADD8mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x4ULL, NULL, ImplicitList1, OperandInfo28 }, // Inst #98 = ADD8mr | |
| { 99, 3, 1, 0, 0, "ADD8ri", 0|(1<<MCID::ConvertibleTo3Addr), 0x100004010ULL, NULL, ImplicitList1, OperandInfo29 }, // Inst #99 = ADD8ri | |
| { 100, 7, 1, 0, 0, "ADD8rm", 0|(1<<MCID::MayLoad), 0x4000006ULL, NULL, ImplicitList1, OperandInfo30 }, // Inst #100 = ADD8rm | |
| { 101, 3, 1, 0, 0, "ADD8rr", 0|(1<<MCID::ConvertibleTo3Addr)|(1<<MCID::Commutable), 0x3ULL, NULL, ImplicitList1, OperandInfo31 }, // Inst #101 = ADD8rr | |
| { 102, 3, 1, 0, 0, "ADD8rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x4000005ULL, NULL, ImplicitList1, OperandInfo31 }, // Inst #102 = ADD8rr_REV | |
| { 103, 7, 1, 0, 0, "ADDPDrm", 0|(1<<MCID::MayLoad), 0xb1000146ULL, NULL, NULL, OperandInfo32 }, // Inst #103 = ADDPDrm | |
| { 104, 3, 1, 0, 0, "ADDPDrr", 0|(1<<MCID::Commutable), 0xb1000145ULL, NULL, NULL, OperandInfo33 }, // Inst #104 = ADDPDrr | |
| { 105, 7, 1, 0, 0, "ADDPSrm", 0|(1<<MCID::MayLoad), 0xb0800106ULL, NULL, NULL, OperandInfo32 }, // Inst #105 = ADDPSrm | |
| { 106, 3, 1, 0, 0, "ADDPSrr", 0|(1<<MCID::Commutable), 0xb0800105ULL, NULL, NULL, OperandInfo33 }, // Inst #106 = ADDPSrr | |
| { 107, 7, 1, 0, 0, "ADDSDrm", 0|(1<<MCID::MayLoad), 0xb0000b06ULL, NULL, NULL, OperandInfo34 }, // Inst #107 = ADDSDrm | |
| { 108, 7, 1, 0, 0, "ADDSDrm_Int", 0|(1<<MCID::MayLoad), 0xb0000b06ULL, NULL, NULL, OperandInfo32 }, // Inst #108 = ADDSDrm_Int | |
| { 109, 3, 1, 0, 0, "ADDSDrr", 0|(1<<MCID::Commutable), 0xb0000b05ULL, NULL, NULL, OperandInfo35 }, // Inst #109 = ADDSDrr | |
| { 110, 3, 1, 0, 0, "ADDSDrr_Int", 0, 0xb0000b05ULL, NULL, NULL, OperandInfo33 }, // Inst #110 = ADDSDrr_Int | |
| { 111, 7, 1, 0, 0, "ADDSSrm", 0|(1<<MCID::MayLoad), 0xb0000c06ULL, NULL, NULL, OperandInfo36 }, // Inst #111 = ADDSSrm | |
| { 112, 7, 1, 0, 0, "ADDSSrm_Int", 0|(1<<MCID::MayLoad), 0xb0000c06ULL, NULL, NULL, OperandInfo32 }, // Inst #112 = ADDSSrm_Int | |
| { 113, 3, 1, 0, 0, "ADDSSrr", 0|(1<<MCID::Commutable), 0xb0000c05ULL, NULL, NULL, OperandInfo37 }, // Inst #113 = ADDSSrr | |
| { 114, 3, 1, 0, 0, "ADDSSrr_Int", 0, 0xb0000c05ULL, NULL, NULL, OperandInfo33 }, // Inst #114 = ADDSSrr_Int | |
| { 115, 7, 1, 0, 0, "ADDSUBPDrm", 0|(1<<MCID::MayLoad), 0x1a1000146ULL, NULL, NULL, OperandInfo32 }, // Inst #115 = ADDSUBPDrm | |
| { 116, 3, 1, 0, 0, "ADDSUBPDrr", 0, 0x1a1000145ULL, NULL, NULL, OperandInfo33 }, // Inst #116 = ADDSUBPDrr | |
| { 117, 7, 1, 0, 0, "ADDSUBPSrm", 0|(1<<MCID::MayLoad), 0x1a1000b06ULL, NULL, NULL, OperandInfo32 }, // Inst #117 = ADDSUBPSrm | |
| { 118, 3, 1, 0, 0, "ADDSUBPSrr", 0, 0x1a1000b05ULL, NULL, NULL, OperandInfo33 }, // Inst #118 = ADDSUBPSrr | |
| { 119, 5, 0, 0, 0, "ADD_F32m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b0000018ULL, NULL, NULL, OperandInfo38 }, // Inst #119 = ADD_F32m | |
| { 120, 5, 0, 0, 0, "ADD_F64m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b8000018ULL, NULL, NULL, OperandInfo38 }, // Inst #120 = ADD_F64m | |
| { 121, 5, 0, 0, 0, "ADD_FI16m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1bc000018ULL, NULL, NULL, OperandInfo38 }, // Inst #121 = ADD_FI16m | |
| { 122, 5, 0, 0, 0, "ADD_FI32m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b4000018ULL, NULL, NULL, OperandInfo38 }, // Inst #122 = ADD_FI32m | |
| { 123, 1, 0, 0, 0, "ADD_FPrST0", 0|(1<<MCID::UnmodeledSideEffects), 0x180000902ULL, NULL, NULL, OperandInfo39 }, // Inst #123 = ADD_FPrST0 | |
| { 124, 1, 0, 0, 0, "ADD_FST0r", 0|(1<<MCID::UnmodeledSideEffects), 0x180000302ULL, NULL, NULL, OperandInfo39 }, // Inst #124 = ADD_FST0r | |
| { 125, 3, 1, 0, 0, "ADD_Fp32", 0, 0x80000ULL, NULL, NULL, OperandInfo40 }, // Inst #125 = ADD_Fp32 | |
| { 126, 7, 1, 0, 0, "ADD_Fp32m", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo41 }, // Inst #126 = ADD_Fp32m | |
| { 127, 3, 1, 0, 0, "ADD_Fp64", 0, 0x80000ULL, NULL, NULL, OperandInfo42 }, // Inst #127 = ADD_Fp64 | |
| { 128, 7, 1, 0, 0, "ADD_Fp64m", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #128 = ADD_Fp64m | |
| { 129, 7, 1, 0, 0, "ADD_Fp64m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #129 = ADD_Fp64m32 | |
| { 130, 3, 1, 0, 0, "ADD_Fp80", 0, 0x80000ULL, NULL, NULL, OperandInfo44 }, // Inst #130 = ADD_Fp80 | |
| { 131, 7, 1, 0, 0, "ADD_Fp80m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #131 = ADD_Fp80m32 | |
| { 132, 7, 1, 0, 0, "ADD_Fp80m64", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #132 = ADD_Fp80m64 | |
| { 133, 7, 1, 0, 0, "ADD_FpI16m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo41 }, // Inst #133 = ADD_FpI16m32 | |
| { 134, 7, 1, 0, 0, "ADD_FpI16m64", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #134 = ADD_FpI16m64 | |
| { 135, 7, 1, 0, 0, "ADD_FpI16m80", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #135 = ADD_FpI16m80 | |
| { 136, 7, 1, 0, 0, "ADD_FpI32m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo41 }, // Inst #136 = ADD_FpI32m32 | |
| { 137, 7, 1, 0, 0, "ADD_FpI32m64", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #137 = ADD_FpI32m64 | |
| { 138, 7, 1, 0, 0, "ADD_FpI32m80", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #138 = ADD_FpI32m80 | |
| { 139, 1, 0, 0, 0, "ADD_FrST0", 0|(1<<MCID::UnmodeledSideEffects), 0x180000702ULL, NULL, NULL, OperandInfo39 }, // Inst #139 = ADD_FrST0 | |
| { 140, 1, 0, 0, 0, "ADJCALLSTACKDOWN32", 0, 0x0ULL, ImplicitList6, ImplicitList7, OperandInfo2 }, // Inst #140 = ADJCALLSTACKDOWN32 | |
| { 141, 1, 0, 0, 0, "ADJCALLSTACKDOWN64", 0, 0x0ULL, ImplicitList8, ImplicitList9, OperandInfo2 }, // Inst #141 = ADJCALLSTACKDOWN64 | |
| { 142, 2, 0, 0, 0, "ADJCALLSTACKUP32", 0, 0x0ULL, ImplicitList6, ImplicitList7, OperandInfo46 }, // Inst #142 = ADJCALLSTACKUP32 | |
| { 143, 2, 0, 0, 0, "ADJCALLSTACKUP64", 0, 0x0ULL, ImplicitList8, ImplicitList9, OperandInfo46 }, // Inst #143 = ADJCALLSTACKUP64 | |
| { 144, 7, 1, 0, 0, "AESDECLASTrm", 0|(1<<MCID::MayLoad), 0x1bf800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #144 = AESDECLASTrm | |
| { 145, 3, 1, 0, 0, "AESDECLASTrr", 0, 0x1bf800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #145 = AESDECLASTrr | |
| { 146, 7, 1, 0, 0, "AESDECrm", 0|(1<<MCID::MayLoad), 0x1bd800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #146 = AESDECrm | |
| { 147, 3, 1, 0, 0, "AESDECrr", 0, 0x1bd800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #147 = AESDECrr | |
| { 148, 7, 1, 0, 0, "AESENCLASTrm", 0|(1<<MCID::MayLoad), 0x1bb800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #148 = AESENCLASTrm | |
| { 149, 3, 1, 0, 0, "AESENCLASTrr", 0, 0x1bb800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #149 = AESENCLASTrr | |
| { 150, 7, 1, 0, 0, "AESENCrm", 0|(1<<MCID::MayLoad), 0x1b9800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #150 = AESENCrm | |
| { 151, 3, 1, 0, 0, "AESENCrr", 0, 0x1b9800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #151 = AESENCrr | |
| { 152, 6, 1, 0, 0, "AESIMCrm", 0|(1<<MCID::MayLoad), 0x1b7800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #152 = AESIMCrm | |
| { 153, 2, 1, 0, 0, "AESIMCrr", 0, 0x1b7800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #153 = AESIMCrr | |
| { 154, 7, 1, 0, 0, "AESKEYGENASSIST128rm", 0|(1<<MCID::MayLoad), 0x1bf804e46ULL, NULL, NULL, OperandInfo49 }, // Inst #154 = AESKEYGENASSIST128rm | |
| { 155, 3, 1, 0, 0, "AESKEYGENASSIST128rr", 0, 0x1bf804e45ULL, NULL, NULL, OperandInfo50 }, // Inst #155 = AESKEYGENASSIST128rr | |
| { 156, 1, 0, 0, 0, "AND16i16", 0|(1<<MCID::UnmodeledSideEffects), 0x4a00c041ULL, ImplicitList2, ImplicitList1, OperandInfo2 }, // Inst #156 = AND16i16 | |
| { 157, 6, 0, 0, 0, "AND16mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10200c05cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #157 = AND16mi | |
| { 158, 6, 0, 0, 0, "AND16mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10600405cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #158 = AND16mi8 | |
| { 159, 6, 0, 0, 0, "AND16mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x42000044ULL, NULL, ImplicitList1, OperandInfo16 }, // Inst #159 = AND16mr | |
| { 160, 3, 1, 0, 0, "AND16ri", 0, 0x10200c054ULL, NULL, ImplicitList1, OperandInfo17 }, // Inst #160 = AND16ri | |
| { 161, 3, 1, 0, 0, "AND16ri8", 0, 0x106004054ULL, NULL, ImplicitList1, OperandInfo17 }, // Inst #161 = AND16ri8 | |
| { 162, 7, 1, 0, 0, "AND16rm", 0|(1<<MCID::MayLoad), 0x46000046ULL, NULL, ImplicitList1, OperandInfo18 }, // Inst #162 = AND16rm | |
| { 163, 3, 1, 0, 0, "AND16rr", 0|(1<<MCID::Commutable), 0x42000043ULL, NULL, ImplicitList1, OperandInfo19 }, // Inst #163 = AND16rr | |
| { 164, 3, 1, 0, 0, "AND16rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x46000045ULL, NULL, ImplicitList1, OperandInfo19 }, // Inst #164 = AND16rr_REV | |
| { 165, 1, 0, 0, 0, "AND32i32", 0|(1<<MCID::UnmodeledSideEffects), 0x4a014001ULL, ImplicitList3, ImplicitList1, OperandInfo2 }, // Inst #165 = AND32i32 | |
| { 166, 6, 0, 0, 0, "AND32mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10201401cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #166 = AND32mi | |
| { 167, 6, 0, 0, 0, "AND32mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10600401cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #167 = AND32mi8 | |
| { 168, 6, 0, 0, 0, "AND32mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x42000004ULL, NULL, ImplicitList1, OperandInfo20 }, // Inst #168 = AND32mr | |
| { 169, 3, 1, 0, 0, "AND32ri", 0, 0x102014014ULL, NULL, ImplicitList1, OperandInfo21 }, // Inst #169 = AND32ri | |
| { 170, 3, 1, 0, 0, "AND32ri8", 0, 0x106004014ULL, NULL, ImplicitList1, OperandInfo21 }, // Inst #170 = AND32ri8 | |
| { 171, 7, 1, 0, 0, "AND32rm", 0|(1<<MCID::MayLoad), 0x46000006ULL, NULL, ImplicitList1, OperandInfo22 }, // Inst #171 = AND32rm | |
| { 172, 3, 1, 0, 0, "AND32rr", 0|(1<<MCID::Commutable), 0x42000003ULL, NULL, ImplicitList1, OperandInfo23 }, // Inst #172 = AND32rr | |
| { 173, 3, 1, 0, 0, "AND32rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x46000005ULL, NULL, ImplicitList1, OperandInfo23 }, // Inst #173 = AND32rr_REV | |
| { 174, 1, 0, 0, 0, "AND64i32", 0|(1<<MCID::UnmodeledSideEffects), 0x4a016001ULL, ImplicitList4, ImplicitList1, OperandInfo2 }, // Inst #174 = AND64i32 | |
| { 175, 6, 0, 0, 0, "AND64mi32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10201601cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #175 = AND64mi32 | |
| { 176, 6, 0, 0, 0, "AND64mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10600601cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #176 = AND64mi8 | |
| { 177, 6, 0, 0, 0, "AND64mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x42002004ULL, NULL, ImplicitList1, OperandInfo24 }, // Inst #177 = AND64mr | |
| { 178, 3, 1, 0, 0, "AND64ri32", 0, 0x102016014ULL, NULL, ImplicitList1, OperandInfo25 }, // Inst #178 = AND64ri32 | |
| { 179, 3, 1, 0, 0, "AND64ri8", 0, 0x106006014ULL, NULL, ImplicitList1, OperandInfo25 }, // Inst #179 = AND64ri8 | |
| { 180, 7, 1, 0, 0, "AND64rm", 0|(1<<MCID::MayLoad), 0x46002006ULL, NULL, ImplicitList1, OperandInfo26 }, // Inst #180 = AND64rm | |
| { 181, 3, 1, 0, 0, "AND64rr", 0|(1<<MCID::Commutable), 0x42002003ULL, NULL, ImplicitList1, OperandInfo27 }, // Inst #181 = AND64rr | |
| { 182, 3, 1, 0, 0, "AND64rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x46002005ULL, NULL, ImplicitList1, OperandInfo27 }, // Inst #182 = AND64rr_REV | |
| { 183, 1, 0, 0, 0, "AND8i8", 0|(1<<MCID::UnmodeledSideEffects), 0x48004001ULL, ImplicitList5, ImplicitList1, OperandInfo2 }, // Inst #183 = AND8i8 | |
| { 184, 6, 0, 0, 0, "AND8mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10000401cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #184 = AND8mi | |
| { 185, 6, 0, 0, 0, "AND8mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x40000004ULL, NULL, ImplicitList1, OperandInfo28 }, // Inst #185 = AND8mr | |
| { 186, 3, 1, 0, 0, "AND8ri", 0, 0x100004014ULL, NULL, ImplicitList1, OperandInfo29 }, // Inst #186 = AND8ri | |
| { 187, 7, 1, 0, 0, "AND8rm", 0|(1<<MCID::MayLoad), 0x44000006ULL, NULL, ImplicitList1, OperandInfo30 }, // Inst #187 = AND8rm | |
| { 188, 3, 1, 0, 0, "AND8rr", 0|(1<<MCID::Commutable), 0x40000003ULL, NULL, ImplicitList1, OperandInfo31 }, // Inst #188 = AND8rr | |
| { 189, 3, 1, 0, 0, "AND8rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x44000005ULL, NULL, ImplicitList1, OperandInfo31 }, // Inst #189 = AND8rr_REV | |
| { 190, 7, 1, 0, 0, "ANDN32rm", 0|(1<<MCID::MayLoad), 0xbe4000d06ULL, NULL, ImplicitList1, OperandInfo51 }, // Inst #190 = ANDN32rm | |
| { 191, 3, 1, 0, 0, "ANDN32rr", 0, 0xbe4000d05ULL, NULL, ImplicitList1, OperandInfo52 }, // Inst #191 = ANDN32rr | |
| { 192, 7, 1, 0, 0, "ANDN64rm", 0|(1<<MCID::MayLoad), 0xfe4000d06ULL, NULL, ImplicitList1, OperandInfo53 }, // Inst #192 = ANDN64rm | |
| { 193, 3, 1, 0, 0, "ANDN64rr", 0, 0xfe4000d05ULL, NULL, ImplicitList1, OperandInfo54 }, // Inst #193 = ANDN64rr | |
| { 194, 7, 1, 0, 0, "ANDNPDrm", 0|(1<<MCID::MayLoad), 0xab000146ULL, NULL, NULL, OperandInfo32 }, // Inst #194 = ANDNPDrm | |
| { 195, 3, 1, 0, 0, "ANDNPDrr", 0, 0xab000145ULL, NULL, NULL, OperandInfo33 }, // Inst #195 = ANDNPDrr | |
| { 196, 7, 1, 0, 0, "ANDNPSrm", 0|(1<<MCID::MayLoad), 0xaa800106ULL, NULL, NULL, OperandInfo32 }, // Inst #196 = ANDNPSrm | |
| { 197, 3, 1, 0, 0, "ANDNPSrr", 0, 0xaa800105ULL, NULL, NULL, OperandInfo33 }, // Inst #197 = ANDNPSrr | |
| { 198, 7, 1, 0, 0, "ANDPDrm", 0|(1<<MCID::MayLoad), 0xa9000146ULL, NULL, NULL, OperandInfo32 }, // Inst #198 = ANDPDrm | |
| { 199, 3, 1, 0, 0, "ANDPDrr", 0|(1<<MCID::Commutable), 0xa9000145ULL, NULL, NULL, OperandInfo33 }, // Inst #199 = ANDPDrr | |
| { 200, 7, 1, 0, 0, "ANDPSrm", 0|(1<<MCID::MayLoad), 0xa8800106ULL, NULL, NULL, OperandInfo32 }, // Inst #200 = ANDPSrm | |
| { 201, 3, 1, 0, 0, "ANDPSrr", 0|(1<<MCID::Commutable), 0xa8800105ULL, NULL, NULL, OperandInfo33 }, // Inst #201 = ANDPSrr | |
| { 202, 6, 1, 0, 0, "ARPL16mr", 0|(1<<MCID::UnmodeledSideEffects), 0xc6000006ULL, NULL, NULL, OperandInfo11 }, // Inst #202 = ARPL16mr | |
| { 203, 2, 1, 0, 0, "ARPL16rr", 0|(1<<MCID::UnmodeledSideEffects), 0xc6000003ULL, NULL, NULL, OperandInfo55 }, // Inst #203 = ARPL16rr | |
| { 204, 9, 2, 0, 0, "ATOMADD6432", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList11, OperandInfo56 }, // Inst #204 = ATOMADD6432 | |
| { 205, 7, 1, 0, 0, "ATOMAND16", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo57 }, // Inst #205 = ATOMAND16 | |
| { 206, 7, 1, 0, 0, "ATOMAND32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo58 }, // Inst #206 = ATOMAND32 | |
| { 207, 7, 1, 0, 0, "ATOMAND64", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo59 }, // Inst #207 = ATOMAND64 | |
| { 208, 9, 2, 0, 0, "ATOMAND6432", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList11, OperandInfo56 }, // Inst #208 = ATOMAND6432 | |
| { 209, 7, 1, 0, 0, "ATOMAND8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo60 }, // Inst #209 = ATOMAND8 | |
| { 210, 7, 1, 0, 0, "ATOMMAX16", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo57 }, // Inst #210 = ATOMMAX16 | |
| { 211, 7, 1, 0, 0, "ATOMMAX32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo58 }, // Inst #211 = ATOMMAX32 | |
| { 212, 7, 1, 0, 0, "ATOMMAX64", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo59 }, // Inst #212 = ATOMMAX64 | |
| { 213, 7, 1, 0, 0, "ATOMMIN16", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo57 }, // Inst #213 = ATOMMIN16 | |
| { 214, 7, 1, 0, 0, "ATOMMIN32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo58 }, // Inst #214 = ATOMMIN32 | |
| { 215, 7, 1, 0, 0, "ATOMMIN64", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo59 }, // Inst #215 = ATOMMIN64 | |
| { 216, 7, 1, 0, 0, "ATOMNAND16", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo57 }, // Inst #216 = ATOMNAND16 | |
| { 217, 7, 1, 0, 0, "ATOMNAND32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo58 }, // Inst #217 = ATOMNAND32 | |
| { 218, 7, 1, 0, 0, "ATOMNAND64", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo59 }, // Inst #218 = ATOMNAND64 | |
| { 219, 9, 2, 0, 0, "ATOMNAND6432", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList11, OperandInfo56 }, // Inst #219 = ATOMNAND6432 | |
| { 220, 7, 1, 0, 0, "ATOMNAND8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo60 }, // Inst #220 = ATOMNAND8 | |
| { 221, 7, 1, 0, 0, "ATOMOR16", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo57 }, // Inst #221 = ATOMOR16 | |
| { 222, 7, 1, 0, 0, "ATOMOR32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo58 }, // Inst #222 = ATOMOR32 | |
| { 223, 7, 1, 0, 0, "ATOMOR64", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo59 }, // Inst #223 = ATOMOR64 | |
| { 224, 9, 2, 0, 0, "ATOMOR6432", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList11, OperandInfo56 }, // Inst #224 = ATOMOR6432 | |
| { 225, 7, 1, 0, 0, "ATOMOR8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo60 }, // Inst #225 = ATOMOR8 | |
| { 226, 9, 2, 0, 0, "ATOMSUB6432", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList11, OperandInfo56 }, // Inst #226 = ATOMSUB6432 | |
| { 227, 9, 2, 0, 0, "ATOMSWAP6432", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList11, OperandInfo56 }, // Inst #227 = ATOMSWAP6432 | |
| { 228, 7, 1, 0, 0, "ATOMUMAX16", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo57 }, // Inst #228 = ATOMUMAX16 | |
| { 229, 7, 1, 0, 0, "ATOMUMAX32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo58 }, // Inst #229 = ATOMUMAX32 | |
| { 230, 7, 1, 0, 0, "ATOMUMAX64", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo59 }, // Inst #230 = ATOMUMAX64 | |
| { 231, 7, 1, 0, 0, "ATOMUMIN16", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo57 }, // Inst #231 = ATOMUMIN16 | |
| { 232, 7, 1, 0, 0, "ATOMUMIN32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo58 }, // Inst #232 = ATOMUMIN32 | |
| { 233, 7, 1, 0, 0, "ATOMUMIN64", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo59 }, // Inst #233 = ATOMUMIN64 | |
| { 234, 7, 1, 0, 0, "ATOMXOR16", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo57 }, // Inst #234 = ATOMXOR16 | |
| { 235, 7, 1, 0, 0, "ATOMXOR32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo58 }, // Inst #235 = ATOMXOR32 | |
| { 236, 7, 1, 0, 0, "ATOMXOR64", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo59 }, // Inst #236 = ATOMXOR64 | |
| { 237, 9, 2, 0, 0, "ATOMXOR6432", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList11, OperandInfo56 }, // Inst #237 = ATOMXOR6432 | |
| { 238, 7, 1, 0, 0, "ATOMXOR8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo60 }, // Inst #238 = ATOMXOR8 | |
| { 239, 1, 1, 0, 0, "AVX_SET0PDY", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::Rematerializable)|(1<<MCID::CheapAsAMove), 0xaaf000160ULL, NULL, NULL, OperandInfo61 }, // Inst #239 = AVX_SET0PDY | |
| { 240, 1, 1, 0, 0, "AVX_SET0PSY", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::Rematerializable)|(1<<MCID::CheapAsAMove), 0xaae800120ULL, NULL, NULL, OperandInfo61 }, // Inst #240 = AVX_SET0PSY | |
| { 241, 1, 1, 0, 0, "AVX_SETALLONES", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::Rematerializable)|(1<<MCID::CheapAsAMove), 0xaed800160ULL, NULL, NULL, OperandInfo62 }, // Inst #241 = AVX_SETALLONES | |
| { 242, 8, 1, 0, 0, "BLENDPDrmi", 0|(1<<MCID::MayLoad), 0x1b804e46ULL, NULL, NULL, OperandInfo63 }, // Inst #242 = BLENDPDrmi | |
| { 243, 4, 1, 0, 0, "BLENDPDrri", 0, 0x1b804e45ULL, NULL, NULL, OperandInfo64 }, // Inst #243 = BLENDPDrri | |
| { 244, 8, 1, 0, 0, "BLENDPSrmi", 0|(1<<MCID::MayLoad), 0x19804e46ULL, NULL, NULL, OperandInfo63 }, // Inst #244 = BLENDPSrmi | |
| { 245, 4, 1, 0, 0, "BLENDPSrri", 0, 0x19804e45ULL, NULL, NULL, OperandInfo64 }, // Inst #245 = BLENDPSrri | |
| { 246, 7, 1, 0, 0, "BLENDVPDrm0", 0|(1<<MCID::MayLoad), 0x2b800d46ULL, ImplicitList12, NULL, OperandInfo32 }, // Inst #246 = BLENDVPDrm0 | |
| { 247, 3, 1, 0, 0, "BLENDVPDrr0", 0, 0x2b800d45ULL, ImplicitList12, NULL, OperandInfo33 }, // Inst #247 = BLENDVPDrr0 | |
| { 248, 7, 1, 0, 0, "BLENDVPSrm0", 0|(1<<MCID::MayLoad), 0x29800d46ULL, ImplicitList12, NULL, OperandInfo32 }, // Inst #248 = BLENDVPSrm0 | |
| { 249, 3, 1, 0, 0, "BLENDVPSrr0", 0, 0x29800d45ULL, ImplicitList12, NULL, OperandInfo33 }, // Inst #249 = BLENDVPSrr0 | |
| { 250, 6, 1, 0, 0, "BOUNDS16rm", 0|(1<<MCID::UnmodeledSideEffects), 0xc4000046ULL, NULL, NULL, OperandInfo11 }, // Inst #250 = BOUNDS16rm | |
| { 251, 6, 1, 0, 0, "BOUNDS32rm", 0|(1<<MCID::UnmodeledSideEffects), 0xc4000006ULL, NULL, NULL, OperandInfo12 }, // Inst #251 = BOUNDS32rm | |
| { 252, 6, 1, 0, 0, "BSF16rm", 0|(1<<MCID::MayLoad), 0x178000146ULL, NULL, ImplicitList1, OperandInfo11 }, // Inst #252 = BSF16rm | |
| { 253, 2, 1, 0, 0, "BSF16rr", 0, 0x178000145ULL, NULL, ImplicitList1, OperandInfo55 }, // Inst #253 = BSF16rr | |
| { 254, 6, 1, 0, 0, "BSF32rm", 0|(1<<MCID::MayLoad), 0x178000106ULL, NULL, ImplicitList1, OperandInfo12 }, // Inst #254 = BSF32rm | |
| { 255, 2, 1, 0, 0, "BSF32rr", 0, 0x178000105ULL, NULL, ImplicitList1, OperandInfo65 }, // Inst #255 = BSF32rr | |
| { 256, 6, 1, 0, 0, "BSF64rm", 0|(1<<MCID::MayLoad), 0x178002106ULL, NULL, ImplicitList1, OperandInfo13 }, // Inst #256 = BSF64rm | |
| { 257, 2, 1, 0, 0, "BSF64rr", 0, 0x178002105ULL, NULL, ImplicitList1, OperandInfo66 }, // Inst #257 = BSF64rr | |
| { 258, 6, 1, 0, 0, "BSR16rm", 0|(1<<MCID::MayLoad), 0x17a000146ULL, NULL, ImplicitList1, OperandInfo11 }, // Inst #258 = BSR16rm | |
| { 259, 2, 1, 0, 0, "BSR16rr", 0, 0x17a000145ULL, NULL, ImplicitList1, OperandInfo55 }, // Inst #259 = BSR16rr | |
| { 260, 6, 1, 0, 0, "BSR32rm", 0|(1<<MCID::MayLoad), 0x17a000106ULL, NULL, ImplicitList1, OperandInfo12 }, // Inst #260 = BSR32rm | |
| { 261, 2, 1, 0, 0, "BSR32rr", 0, 0x17a000105ULL, NULL, ImplicitList1, OperandInfo65 }, // Inst #261 = BSR32rr | |
| { 262, 6, 1, 0, 0, "BSR64rm", 0|(1<<MCID::MayLoad), 0x17a002106ULL, NULL, ImplicitList1, OperandInfo13 }, // Inst #262 = BSR64rm | |
| { 263, 2, 1, 0, 0, "BSR64rr", 0, 0x17a002105ULL, NULL, ImplicitList1, OperandInfo66 }, // Inst #263 = BSR64rr | |
| { 264, 2, 1, 0, 0, "BSWAP32r", 0, 0x190000102ULL, NULL, NULL, OperandInfo67 }, // Inst #264 = BSWAP32r | |
| { 265, 2, 1, 0, 0, "BSWAP64r", 0, 0x190002102ULL, NULL, NULL, OperandInfo68 }, // Inst #265 = BSWAP64r | |
| { 266, 6, 0, 0, 0, "BT16mi8", 0|(1<<MCID::MayLoad), 0x17400415cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #266 = BT16mi8 | |
| { 267, 6, 0, 0, 0, "BT16mr", 0|(1<<MCID::UnmodeledSideEffects), 0x146000144ULL, NULL, ImplicitList1, OperandInfo16 }, // Inst #267 = BT16mr | |
| { 268, 2, 0, 0, 0, "BT16ri8", 0, 0x174004154ULL, NULL, ImplicitList1, OperandInfo69 }, // Inst #268 = BT16ri8 | |
| { 269, 2, 0, 0, 0, "BT16rr", 0, 0x146000143ULL, NULL, ImplicitList1, OperandInfo55 }, // Inst #269 = BT16rr | |
| { 270, 6, 0, 0, 0, "BT32mi8", 0|(1<<MCID::MayLoad), 0x17400411cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #270 = BT32mi8 | |
| { 271, 6, 0, 0, 0, "BT32mr", 0|(1<<MCID::UnmodeledSideEffects), 0x146000104ULL, NULL, ImplicitList1, OperandInfo20 }, // Inst #271 = BT32mr | |
| { 272, 2, 0, 0, 0, "BT32ri8", 0, 0x174004114ULL, NULL, ImplicitList1, OperandInfo70 }, // Inst #272 = BT32ri8 | |
| { 273, 2, 0, 0, 0, "BT32rr", 0, 0x146000103ULL, NULL, ImplicitList1, OperandInfo65 }, // Inst #273 = BT32rr | |
| { 274, 6, 0, 0, 0, "BT64mi8", 0|(1<<MCID::MayLoad), 0x17400611cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #274 = BT64mi8 | |
| { 275, 6, 0, 0, 0, "BT64mr", 0|(1<<MCID::UnmodeledSideEffects), 0x146002104ULL, NULL, ImplicitList1, OperandInfo24 }, // Inst #275 = BT64mr | |
| { 276, 2, 0, 0, 0, "BT64ri8", 0, 0x174006114ULL, NULL, ImplicitList1, OperandInfo71 }, // Inst #276 = BT64ri8 | |
| { 277, 2, 0, 0, 0, "BT64rr", 0, 0x146002103ULL, NULL, ImplicitList1, OperandInfo66 }, // Inst #277 = BT64rr | |
| { 278, 6, 0, 0, 0, "BTC16mi8", 0|(1<<MCID::UnmodeledSideEffects), 0x17400415fULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #278 = BTC16mi8 | |
| { 279, 6, 0, 0, 0, "BTC16mr", 0|(1<<MCID::UnmodeledSideEffects), 0x176000144ULL, NULL, ImplicitList1, OperandInfo16 }, // Inst #279 = BTC16mr | |
| { 280, 2, 0, 0, 0, "BTC16ri8", 0|(1<<MCID::UnmodeledSideEffects), 0x174004157ULL, NULL, ImplicitList1, OperandInfo69 }, // Inst #280 = BTC16ri8 | |
| { 281, 2, 0, 0, 0, "BTC16rr", 0|(1<<MCID::UnmodeledSideEffects), 0x176000143ULL, NULL, ImplicitList1, OperandInfo55 }, // Inst #281 = BTC16rr | |
| { 282, 6, 0, 0, 0, "BTC32mi8", 0|(1<<MCID::UnmodeledSideEffects), 0x17400411fULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #282 = BTC32mi8 | |
| { 283, 6, 0, 0, 0, "BTC32mr", 0|(1<<MCID::UnmodeledSideEffects), 0x176000104ULL, NULL, ImplicitList1, OperandInfo20 }, // Inst #283 = BTC32mr | |
| { 284, 2, 0, 0, 0, "BTC32ri8", 0|(1<<MCID::UnmodeledSideEffects), 0x174004117ULL, NULL, ImplicitList1, OperandInfo70 }, // Inst #284 = BTC32ri8 | |
| { 285, 2, 0, 0, 0, "BTC32rr", 0|(1<<MCID::UnmodeledSideEffects), 0x176000103ULL, NULL, ImplicitList1, OperandInfo65 }, // Inst #285 = BTC32rr | |
| { 286, 6, 0, 0, 0, "BTC64mi8", 0|(1<<MCID::UnmodeledSideEffects), 0x17400611fULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #286 = BTC64mi8 | |
| { 287, 6, 0, 0, 0, "BTC64mr", 0|(1<<MCID::UnmodeledSideEffects), 0x176002104ULL, NULL, ImplicitList1, OperandInfo24 }, // Inst #287 = BTC64mr | |
| { 288, 2, 0, 0, 0, "BTC64ri8", 0|(1<<MCID::UnmodeledSideEffects), 0x174006117ULL, NULL, ImplicitList1, OperandInfo71 }, // Inst #288 = BTC64ri8 | |
| { 289, 2, 0, 0, 0, "BTC64rr", 0|(1<<MCID::UnmodeledSideEffects), 0x176002103ULL, NULL, ImplicitList1, OperandInfo66 }, // Inst #289 = BTC64rr | |
| { 290, 6, 0, 0, 0, "BTR16mi8", 0|(1<<MCID::UnmodeledSideEffects), 0x17400415eULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #290 = BTR16mi8 | |
| { 291, 6, 0, 0, 0, "BTR16mr", 0|(1<<MCID::UnmodeledSideEffects), 0x166000144ULL, NULL, ImplicitList1, OperandInfo16 }, // Inst #291 = BTR16mr | |
| { 292, 2, 0, 0, 0, "BTR16ri8", 0|(1<<MCID::UnmodeledSideEffects), 0x174004156ULL, NULL, ImplicitList1, OperandInfo69 }, // Inst #292 = BTR16ri8 | |
| { 293, 2, 0, 0, 0, "BTR16rr", 0|(1<<MCID::UnmodeledSideEffects), 0x166000143ULL, NULL, ImplicitList1, OperandInfo55 }, // Inst #293 = BTR16rr | |
| { 294, 6, 0, 0, 0, "BTR32mi8", 0|(1<<MCID::UnmodeledSideEffects), 0x17400411eULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #294 = BTR32mi8 | |
| { 295, 6, 0, 0, 0, "BTR32mr", 0|(1<<MCID::UnmodeledSideEffects), 0x166000104ULL, NULL, ImplicitList1, OperandInfo20 }, // Inst #295 = BTR32mr | |
| { 296, 2, 0, 0, 0, "BTR32ri8", 0|(1<<MCID::UnmodeledSideEffects), 0x174004116ULL, NULL, ImplicitList1, OperandInfo70 }, // Inst #296 = BTR32ri8 | |
| { 297, 2, 0, 0, 0, "BTR32rr", 0|(1<<MCID::UnmodeledSideEffects), 0x166000103ULL, NULL, ImplicitList1, OperandInfo65 }, // Inst #297 = BTR32rr | |
| { 298, 6, 0, 0, 0, "BTR64mi8", 0|(1<<MCID::UnmodeledSideEffects), 0x17400611eULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #298 = BTR64mi8 | |
| { 299, 6, 0, 0, 0, "BTR64mr", 0|(1<<MCID::UnmodeledSideEffects), 0x166002104ULL, NULL, ImplicitList1, OperandInfo24 }, // Inst #299 = BTR64mr | |
| { 300, 2, 0, 0, 0, "BTR64ri8", 0|(1<<MCID::UnmodeledSideEffects), 0x174006116ULL, NULL, ImplicitList1, OperandInfo71 }, // Inst #300 = BTR64ri8 | |
| { 301, 2, 0, 0, 0, "BTR64rr", 0|(1<<MCID::UnmodeledSideEffects), 0x166002103ULL, NULL, ImplicitList1, OperandInfo66 }, // Inst #301 = BTR64rr | |
| { 302, 6, 0, 0, 0, "BTS16mi8", 0|(1<<MCID::UnmodeledSideEffects), 0x17400415dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #302 = BTS16mi8 | |
| { 303, 6, 0, 0, 0, "BTS16mr", 0|(1<<MCID::UnmodeledSideEffects), 0x156000144ULL, NULL, ImplicitList1, OperandInfo16 }, // Inst #303 = BTS16mr | |
| { 304, 2, 0, 0, 0, "BTS16ri8", 0|(1<<MCID::UnmodeledSideEffects), 0x174004155ULL, NULL, ImplicitList1, OperandInfo69 }, // Inst #304 = BTS16ri8 | |
| { 305, 2, 0, 0, 0, "BTS16rr", 0|(1<<MCID::UnmodeledSideEffects), 0x156000143ULL, NULL, ImplicitList1, OperandInfo55 }, // Inst #305 = BTS16rr | |
| { 306, 6, 0, 0, 0, "BTS32mi8", 0|(1<<MCID::UnmodeledSideEffects), 0x17400411dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #306 = BTS32mi8 | |
| { 307, 6, 0, 0, 0, "BTS32mr", 0|(1<<MCID::UnmodeledSideEffects), 0x156000104ULL, NULL, ImplicitList1, OperandInfo20 }, // Inst #307 = BTS32mr | |
| { 308, 2, 0, 0, 0, "BTS32ri8", 0|(1<<MCID::UnmodeledSideEffects), 0x174004115ULL, NULL, ImplicitList1, OperandInfo70 }, // Inst #308 = BTS32ri8 | |
| { 309, 2, 0, 0, 0, "BTS32rr", 0|(1<<MCID::UnmodeledSideEffects), 0x156000103ULL, NULL, ImplicitList1, OperandInfo65 }, // Inst #309 = BTS32rr | |
| { 310, 6, 0, 0, 0, "BTS64mi8", 0|(1<<MCID::UnmodeledSideEffects), 0x17400611dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #310 = BTS64mi8 | |
| { 311, 6, 0, 0, 0, "BTS64mr", 0|(1<<MCID::UnmodeledSideEffects), 0x156002104ULL, NULL, ImplicitList1, OperandInfo24 }, // Inst #311 = BTS64mr | |
| { 312, 2, 0, 0, 0, "BTS64ri8", 0|(1<<MCID::UnmodeledSideEffects), 0x174006115ULL, NULL, ImplicitList1, OperandInfo71 }, // Inst #312 = BTS64ri8 | |
| { 313, 2, 0, 0, 0, "BTS64rr", 0|(1<<MCID::UnmodeledSideEffects), 0x156002103ULL, NULL, ImplicitList1, OperandInfo66 }, // Inst #313 = BTS64rr | |
| { 314, 5, 0, 0, 0, "CALL32m", 0|(1<<MCID::Call)|(1<<MCID::MayLoad)|(1<<MCID::Variadic), 0x1fe00001aULL, ImplicitList6, ImplicitList13, OperandInfo38 }, // Inst #314 = CALL32m | |
| { 315, 1, 0, 0, 0, "CALL32r", 0|(1<<MCID::Call)|(1<<MCID::Variadic), 0x1fe000012ULL, ImplicitList6, ImplicitList13, OperandInfo72 }, // Inst #315 = CALL32r | |
| { 316, 5, 0, 0, 0, "CALL64m", 0|(1<<MCID::Call)|(1<<MCID::MayLoad)|(1<<MCID::Variadic), 0x1fe00001aULL, ImplicitList8, ImplicitList14, OperandInfo38 }, // Inst #316 = CALL64m | |
| { 317, 1, 0, 0, 0, "CALL64pcrel32", 0|(1<<MCID::Call)|(1<<MCID::Variadic)|(1<<MCID::UnmodeledSideEffects), 0x1d0018001ULL, ImplicitList8, ImplicitList14, OperandInfo73 }, // Inst #317 = CALL64pcrel32 | |
| { 318, 1, 0, 0, 0, "CALL64r", 0|(1<<MCID::Call)|(1<<MCID::Variadic), 0x1fe000012ULL, ImplicitList8, ImplicitList14, OperandInfo74 }, // Inst #318 = CALL64r | |
| { 319, 1, 0, 0, 0, "CALLpcrel16", 0|(1<<MCID::Call)|(1<<MCID::Variadic)|(1<<MCID::UnmodeledSideEffects), 0x1d0010041ULL, ImplicitList6, ImplicitList13, OperandInfo73 }, // Inst #319 = CALLpcrel16 | |
| { 320, 1, 0, 0, 0, "CALLpcrel32", 0|(1<<MCID::Call)|(1<<MCID::Variadic)|(1<<MCID::UnmodeledSideEffects), 0x1d0018001ULL, ImplicitList6, ImplicitList13, OperandInfo73 }, // Inst #320 = CALLpcrel32 | |
| { 321, 0, 0, 0, 0, "CBW", 0, 0x130000041ULL, ImplicitList5, ImplicitList2, 0 }, // Inst #321 = CBW | |
| { 322, 0, 0, 0, 0, "CDQ", 0, 0x132000001ULL, ImplicitList3, ImplicitList15, 0 }, // Inst #322 = CDQ | |
| { 323, 0, 0, 0, 0, "CDQE", 0, 0x130002001ULL, ImplicitList3, ImplicitList4, 0 }, // Inst #323 = CDQE | |
| { 324, 0, 0, 0, 0, "CHS_F", 0|(1<<MCID::UnmodeledSideEffects), 0x1c0000401ULL, NULL, NULL, 0 }, // Inst #324 = CHS_F | |
| { 325, 2, 1, 0, 0, "CHS_Fp32", 0, 0x60000ULL, NULL, NULL, OperandInfo8 }, // Inst #325 = CHS_Fp32 | |
| { 326, 2, 1, 0, 0, "CHS_Fp64", 0, 0x60000ULL, NULL, NULL, OperandInfo9 }, // Inst #326 = CHS_Fp64 | |
| { 327, 2, 1, 0, 0, "CHS_Fp80", 0, 0x60000ULL, NULL, NULL, OperandInfo10 }, // Inst #327 = CHS_Fp80 | |
| { 328, 0, 0, 0, 0, "CLC", 0|(1<<MCID::UnmodeledSideEffects), 0x1f0000001ULL, NULL, NULL, 0 }, // Inst #328 = CLC | |
| { 329, 0, 0, 0, 0, "CLD", 0|(1<<MCID::UnmodeledSideEffects), 0x1f8000001ULL, NULL, NULL, 0 }, // Inst #329 = CLD | |
| { 330, 5, 0, 0, 0, "CLFLUSH", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x15c00011fULL, NULL, NULL, OperandInfo38 }, // Inst #330 = CLFLUSH | |
| { 331, 0, 0, 0, 0, "CLI", 0|(1<<MCID::UnmodeledSideEffects), 0x1f4000001ULL, NULL, NULL, 0 }, // Inst #331 = CLI | |
| { 332, 0, 0, 0, 0, "CLTS", 0|(1<<MCID::UnmodeledSideEffects), 0xc000101ULL, NULL, NULL, 0 }, // Inst #332 = CLTS | |
| { 333, 0, 0, 0, 0, "CMC", 0|(1<<MCID::UnmodeledSideEffects), 0x1ea000001ULL, NULL, NULL, 0 }, // Inst #333 = CMC | |
| { 334, 7, 1, 0, 0, "CMOVA16rm", 0|(1<<MCID::MayLoad), 0x8e000146ULL, ImplicitList1, NULL, OperandInfo18 }, // Inst #334 = CMOVA16rm | |
| { 335, 3, 1, 0, 0, "CMOVA16rr", 0|(1<<MCID::Commutable), 0x8e000145ULL, ImplicitList1, NULL, OperandInfo19 }, // Inst #335 = CMOVA16rr | |
| { 336, 7, 1, 0, 0, "CMOVA32rm", 0|(1<<MCID::MayLoad), 0x8e000106ULL, ImplicitList1, NULL, OperandInfo22 }, // Inst #336 = CMOVA32rm | |
| { 337, 3, 1, 0, 0, "CMOVA32rr", 0|(1<<MCID::Commutable), 0x8e000105ULL, ImplicitList1, NULL, OperandInfo23 }, // Inst #337 = CMOVA32rr | |
| { 338, 7, 1, 0, 0, "CMOVA64rm", 0|(1<<MCID::MayLoad), 0x8e002106ULL, ImplicitList1, NULL, OperandInfo26 }, // Inst #338 = CMOVA64rm | |
| { 339, 3, 1, 0, 0, "CMOVA64rr", 0|(1<<MCID::Commutable), 0x8e002105ULL, ImplicitList1, NULL, OperandInfo27 }, // Inst #339 = CMOVA64rr | |
| { 340, 7, 1, 0, 0, "CMOVAE16rm", 0|(1<<MCID::MayLoad), 0x86000146ULL, ImplicitList1, NULL, OperandInfo18 }, // Inst #340 = CMOVAE16rm | |
| { 341, 3, 1, 0, 0, "CMOVAE16rr", 0|(1<<MCID::Commutable), 0x86000145ULL, ImplicitList1, NULL, OperandInfo19 }, // Inst #341 = CMOVAE16rr | |
| { 342, 7, 1, 0, 0, "CMOVAE32rm", 0|(1<<MCID::MayLoad), 0x86000106ULL, ImplicitList1, NULL, OperandInfo22 }, // Inst #342 = CMOVAE32rm | |
| { 343, 3, 1, 0, 0, "CMOVAE32rr", 0|(1<<MCID::Commutable), 0x86000105ULL, ImplicitList1, NULL, OperandInfo23 }, // Inst #343 = CMOVAE32rr | |
| { 344, 7, 1, 0, 0, "CMOVAE64rm", 0|(1<<MCID::MayLoad), 0x86002106ULL, ImplicitList1, NULL, OperandInfo26 }, // Inst #344 = CMOVAE64rm | |
| { 345, 3, 1, 0, 0, "CMOVAE64rr", 0|(1<<MCID::Commutable), 0x86002105ULL, ImplicitList1, NULL, OperandInfo27 }, // Inst #345 = CMOVAE64rr | |
| { 346, 7, 1, 0, 0, "CMOVB16rm", 0|(1<<MCID::MayLoad), 0x84000146ULL, ImplicitList1, NULL, OperandInfo18 }, // Inst #346 = CMOVB16rm | |
| { 347, 3, 1, 0, 0, "CMOVB16rr", 0|(1<<MCID::Commutable), 0x84000145ULL, ImplicitList1, NULL, OperandInfo19 }, // Inst #347 = CMOVB16rr | |
| { 348, 7, 1, 0, 0, "CMOVB32rm", 0|(1<<MCID::MayLoad), 0x84000106ULL, ImplicitList1, NULL, OperandInfo22 }, // Inst #348 = CMOVB32rm | |
| { 349, 3, 1, 0, 0, "CMOVB32rr", 0|(1<<MCID::Commutable), 0x84000105ULL, ImplicitList1, NULL, OperandInfo23 }, // Inst #349 = CMOVB32rr | |
| { 350, 7, 1, 0, 0, "CMOVB64rm", 0|(1<<MCID::MayLoad), 0x84002106ULL, ImplicitList1, NULL, OperandInfo26 }, // Inst #350 = CMOVB64rm | |
| { 351, 3, 1, 0, 0, "CMOVB64rr", 0|(1<<MCID::Commutable), 0x84002105ULL, ImplicitList1, NULL, OperandInfo27 }, // Inst #351 = CMOVB64rr | |
| { 352, 7, 1, 0, 0, "CMOVBE16rm", 0|(1<<MCID::MayLoad), 0x8c000146ULL, ImplicitList1, NULL, OperandInfo18 }, // Inst #352 = CMOVBE16rm | |
| { 353, 3, 1, 0, 0, "CMOVBE16rr", 0|(1<<MCID::Commutable), 0x8c000145ULL, ImplicitList1, NULL, OperandInfo19 }, // Inst #353 = CMOVBE16rr | |
| { 354, 7, 1, 0, 0, "CMOVBE32rm", 0|(1<<MCID::MayLoad), 0x8c000106ULL, ImplicitList1, NULL, OperandInfo22 }, // Inst #354 = CMOVBE32rm | |
| { 355, 3, 1, 0, 0, "CMOVBE32rr", 0|(1<<MCID::Commutable), 0x8c000105ULL, ImplicitList1, NULL, OperandInfo23 }, // Inst #355 = CMOVBE32rr | |
| { 356, 7, 1, 0, 0, "CMOVBE64rm", 0|(1<<MCID::MayLoad), 0x8c002106ULL, ImplicitList1, NULL, OperandInfo26 }, // Inst #356 = CMOVBE64rm | |
| { 357, 3, 1, 0, 0, "CMOVBE64rr", 0|(1<<MCID::Commutable), 0x8c002105ULL, ImplicitList1, NULL, OperandInfo27 }, // Inst #357 = CMOVBE64rr | |
| { 358, 1, 1, 0, 0, "CMOVBE_F", 0|(1<<MCID::UnmodeledSideEffects), 0x1a0000502ULL, NULL, NULL, OperandInfo39 }, // Inst #358 = CMOVBE_F | |
| { 359, 3, 1, 0, 0, "CMOVBE_Fp32", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo75 }, // Inst #359 = CMOVBE_Fp32 | |
| { 360, 3, 1, 0, 0, "CMOVBE_Fp64", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo76 }, // Inst #360 = CMOVBE_Fp64 | |
| { 361, 3, 1, 0, 0, "CMOVBE_Fp80", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo77 }, // Inst #361 = CMOVBE_Fp80 | |
| { 362, 1, 1, 0, 0, "CMOVB_F", 0|(1<<MCID::UnmodeledSideEffects), 0x180000502ULL, NULL, NULL, OperandInfo39 }, // Inst #362 = CMOVB_F | |
| { 363, 3, 1, 0, 0, "CMOVB_Fp32", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo75 }, // Inst #363 = CMOVB_Fp32 | |
| { 364, 3, 1, 0, 0, "CMOVB_Fp64", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo76 }, // Inst #364 = CMOVB_Fp64 | |
| { 365, 3, 1, 0, 0, "CMOVB_Fp80", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo77 }, // Inst #365 = CMOVB_Fp80 | |
| { 366, 7, 1, 0, 0, "CMOVE16rm", 0|(1<<MCID::MayLoad), 0x88000146ULL, ImplicitList1, NULL, OperandInfo18 }, // Inst #366 = CMOVE16rm | |
| { 367, 3, 1, 0, 0, "CMOVE16rr", 0|(1<<MCID::Commutable), 0x88000145ULL, ImplicitList1, NULL, OperandInfo19 }, // Inst #367 = CMOVE16rr | |
| { 368, 7, 1, 0, 0, "CMOVE32rm", 0|(1<<MCID::MayLoad), 0x88000106ULL, ImplicitList1, NULL, OperandInfo22 }, // Inst #368 = CMOVE32rm | |
| { 369, 3, 1, 0, 0, "CMOVE32rr", 0|(1<<MCID::Commutable), 0x88000105ULL, ImplicitList1, NULL, OperandInfo23 }, // Inst #369 = CMOVE32rr | |
| { 370, 7, 1, 0, 0, "CMOVE64rm", 0|(1<<MCID::MayLoad), 0x88002106ULL, ImplicitList1, NULL, OperandInfo26 }, // Inst #370 = CMOVE64rm | |
| { 371, 3, 1, 0, 0, "CMOVE64rr", 0|(1<<MCID::Commutable), 0x88002105ULL, ImplicitList1, NULL, OperandInfo27 }, // Inst #371 = CMOVE64rr | |
| { 372, 1, 1, 0, 0, "CMOVE_F", 0|(1<<MCID::UnmodeledSideEffects), 0x190000502ULL, NULL, NULL, OperandInfo39 }, // Inst #372 = CMOVE_F | |
| { 373, 3, 1, 0, 0, "CMOVE_Fp32", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo75 }, // Inst #373 = CMOVE_Fp32 | |
| { 374, 3, 1, 0, 0, "CMOVE_Fp64", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo76 }, // Inst #374 = CMOVE_Fp64 | |
| { 375, 3, 1, 0, 0, "CMOVE_Fp80", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo77 }, // Inst #375 = CMOVE_Fp80 | |
| { 376, 7, 1, 0, 0, "CMOVG16rm", 0|(1<<MCID::MayLoad), 0x9e000146ULL, ImplicitList1, NULL, OperandInfo18 }, // Inst #376 = CMOVG16rm | |
| { 377, 3, 1, 0, 0, "CMOVG16rr", 0|(1<<MCID::Commutable), 0x9e000145ULL, ImplicitList1, NULL, OperandInfo19 }, // Inst #377 = CMOVG16rr | |
| { 378, 7, 1, 0, 0, "CMOVG32rm", 0|(1<<MCID::MayLoad), 0x9e000106ULL, ImplicitList1, NULL, OperandInfo22 }, // Inst #378 = CMOVG32rm | |
| { 379, 3, 1, 0, 0, "CMOVG32rr", 0|(1<<MCID::Commutable), 0x9e000105ULL, ImplicitList1, NULL, OperandInfo23 }, // Inst #379 = CMOVG32rr | |
| { 380, 7, 1, 0, 0, "CMOVG64rm", 0|(1<<MCID::MayLoad), 0x9e002106ULL, ImplicitList1, NULL, OperandInfo26 }, // Inst #380 = CMOVG64rm | |
| { 381, 3, 1, 0, 0, "CMOVG64rr", 0|(1<<MCID::Commutable), 0x9e002105ULL, ImplicitList1, NULL, OperandInfo27 }, // Inst #381 = CMOVG64rr | |
| { 382, 7, 1, 0, 0, "CMOVGE16rm", 0|(1<<MCID::MayLoad), 0x9a000146ULL, ImplicitList1, NULL, OperandInfo18 }, // Inst #382 = CMOVGE16rm | |
| { 383, 3, 1, 0, 0, "CMOVGE16rr", 0|(1<<MCID::Commutable), 0x9a000145ULL, ImplicitList1, NULL, OperandInfo19 }, // Inst #383 = CMOVGE16rr | |
| { 384, 7, 1, 0, 0, "CMOVGE32rm", 0|(1<<MCID::MayLoad), 0x9a000106ULL, ImplicitList1, NULL, OperandInfo22 }, // Inst #384 = CMOVGE32rm | |
| { 385, 3, 1, 0, 0, "CMOVGE32rr", 0|(1<<MCID::Commutable), 0x9a000105ULL, ImplicitList1, NULL, OperandInfo23 }, // Inst #385 = CMOVGE32rr | |
| { 386, 7, 1, 0, 0, "CMOVGE64rm", 0|(1<<MCID::MayLoad), 0x9a002106ULL, ImplicitList1, NULL, OperandInfo26 }, // Inst #386 = CMOVGE64rm | |
| { 387, 3, 1, 0, 0, "CMOVGE64rr", 0|(1<<MCID::Commutable), 0x9a002105ULL, ImplicitList1, NULL, OperandInfo27 }, // Inst #387 = CMOVGE64rr | |
| { 388, 7, 1, 0, 0, "CMOVL16rm", 0|(1<<MCID::MayLoad), 0x98000146ULL, ImplicitList1, NULL, OperandInfo18 }, // Inst #388 = CMOVL16rm | |
| { 389, 3, 1, 0, 0, "CMOVL16rr", 0|(1<<MCID::Commutable), 0x98000145ULL, ImplicitList1, NULL, OperandInfo19 }, // Inst #389 = CMOVL16rr | |
| { 390, 7, 1, 0, 0, "CMOVL32rm", 0|(1<<MCID::MayLoad), 0x98000106ULL, ImplicitList1, NULL, OperandInfo22 }, // Inst #390 = CMOVL32rm | |
| { 391, 3, 1, 0, 0, "CMOVL32rr", 0|(1<<MCID::Commutable), 0x98000105ULL, ImplicitList1, NULL, OperandInfo23 }, // Inst #391 = CMOVL32rr | |
| { 392, 7, 1, 0, 0, "CMOVL64rm", 0|(1<<MCID::MayLoad), 0x98002106ULL, ImplicitList1, NULL, OperandInfo26 }, // Inst #392 = CMOVL64rm | |
| { 393, 3, 1, 0, 0, "CMOVL64rr", 0|(1<<MCID::Commutable), 0x98002105ULL, ImplicitList1, NULL, OperandInfo27 }, // Inst #393 = CMOVL64rr | |
| { 394, 7, 1, 0, 0, "CMOVLE16rm", 0|(1<<MCID::MayLoad), 0x9c000146ULL, ImplicitList1, NULL, OperandInfo18 }, // Inst #394 = CMOVLE16rm | |
| { 395, 3, 1, 0, 0, "CMOVLE16rr", 0|(1<<MCID::Commutable), 0x9c000145ULL, ImplicitList1, NULL, OperandInfo19 }, // Inst #395 = CMOVLE16rr | |
| { 396, 7, 1, 0, 0, "CMOVLE32rm", 0|(1<<MCID::MayLoad), 0x9c000106ULL, ImplicitList1, NULL, OperandInfo22 }, // Inst #396 = CMOVLE32rm | |
| { 397, 3, 1, 0, 0, "CMOVLE32rr", 0|(1<<MCID::Commutable), 0x9c000105ULL, ImplicitList1, NULL, OperandInfo23 }, // Inst #397 = CMOVLE32rr | |
| { 398, 7, 1, 0, 0, "CMOVLE64rm", 0|(1<<MCID::MayLoad), 0x9c002106ULL, ImplicitList1, NULL, OperandInfo26 }, // Inst #398 = CMOVLE64rm | |
| { 399, 3, 1, 0, 0, "CMOVLE64rr", 0|(1<<MCID::Commutable), 0x9c002105ULL, ImplicitList1, NULL, OperandInfo27 }, // Inst #399 = CMOVLE64rr | |
| { 400, 1, 1, 0, 0, "CMOVNBE_F", 0|(1<<MCID::UnmodeledSideEffects), 0x1a0000602ULL, NULL, NULL, OperandInfo39 }, // Inst #400 = CMOVNBE_F | |
| { 401, 3, 1, 0, 0, "CMOVNBE_Fp32", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo75 }, // Inst #401 = CMOVNBE_Fp32 | |
| { 402, 3, 1, 0, 0, "CMOVNBE_Fp64", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo76 }, // Inst #402 = CMOVNBE_Fp64 | |
| { 403, 3, 1, 0, 0, "CMOVNBE_Fp80", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo77 }, // Inst #403 = CMOVNBE_Fp80 | |
| { 404, 1, 1, 0, 0, "CMOVNB_F", 0|(1<<MCID::UnmodeledSideEffects), 0x180000602ULL, NULL, NULL, OperandInfo39 }, // Inst #404 = CMOVNB_F | |
| { 405, 3, 1, 0, 0, "CMOVNB_Fp32", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo75 }, // Inst #405 = CMOVNB_Fp32 | |
| { 406, 3, 1, 0, 0, "CMOVNB_Fp64", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo76 }, // Inst #406 = CMOVNB_Fp64 | |
| { 407, 3, 1, 0, 0, "CMOVNB_Fp80", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo77 }, // Inst #407 = CMOVNB_Fp80 | |
| { 408, 7, 1, 0, 0, "CMOVNE16rm", 0|(1<<MCID::MayLoad), 0x8a000146ULL, ImplicitList1, NULL, OperandInfo18 }, // Inst #408 = CMOVNE16rm | |
| { 409, 3, 1, 0, 0, "CMOVNE16rr", 0|(1<<MCID::Commutable), 0x8a000145ULL, ImplicitList1, NULL, OperandInfo19 }, // Inst #409 = CMOVNE16rr | |
| { 410, 7, 1, 0, 0, "CMOVNE32rm", 0|(1<<MCID::MayLoad), 0x8a000106ULL, ImplicitList1, NULL, OperandInfo22 }, // Inst #410 = CMOVNE32rm | |
| { 411, 3, 1, 0, 0, "CMOVNE32rr", 0|(1<<MCID::Commutable), 0x8a000105ULL, ImplicitList1, NULL, OperandInfo23 }, // Inst #411 = CMOVNE32rr | |
| { 412, 7, 1, 0, 0, "CMOVNE64rm", 0|(1<<MCID::MayLoad), 0x8a002106ULL, ImplicitList1, NULL, OperandInfo26 }, // Inst #412 = CMOVNE64rm | |
| { 413, 3, 1, 0, 0, "CMOVNE64rr", 0|(1<<MCID::Commutable), 0x8a002105ULL, ImplicitList1, NULL, OperandInfo27 }, // Inst #413 = CMOVNE64rr | |
| { 414, 1, 1, 0, 0, "CMOVNE_F", 0|(1<<MCID::UnmodeledSideEffects), 0x190000602ULL, NULL, NULL, OperandInfo39 }, // Inst #414 = CMOVNE_F | |
| { 415, 3, 1, 0, 0, "CMOVNE_Fp32", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo75 }, // Inst #415 = CMOVNE_Fp32 | |
| { 416, 3, 1, 0, 0, "CMOVNE_Fp64", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo76 }, // Inst #416 = CMOVNE_Fp64 | |
| { 417, 3, 1, 0, 0, "CMOVNE_Fp80", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo77 }, // Inst #417 = CMOVNE_Fp80 | |
| { 418, 7, 1, 0, 0, "CMOVNO16rm", 0|(1<<MCID::MayLoad), 0x82000146ULL, ImplicitList1, NULL, OperandInfo18 }, // Inst #418 = CMOVNO16rm | |
| { 419, 3, 1, 0, 0, "CMOVNO16rr", 0|(1<<MCID::Commutable), 0x82000145ULL, ImplicitList1, NULL, OperandInfo19 }, // Inst #419 = CMOVNO16rr | |
| { 420, 7, 1, 0, 0, "CMOVNO32rm", 0|(1<<MCID::MayLoad), 0x82000106ULL, ImplicitList1, NULL, OperandInfo22 }, // Inst #420 = CMOVNO32rm | |
| { 421, 3, 1, 0, 0, "CMOVNO32rr", 0|(1<<MCID::Commutable), 0x82000105ULL, ImplicitList1, NULL, OperandInfo23 }, // Inst #421 = CMOVNO32rr | |
| { 422, 7, 1, 0, 0, "CMOVNO64rm", 0|(1<<MCID::MayLoad), 0x82002106ULL, ImplicitList1, NULL, OperandInfo26 }, // Inst #422 = CMOVNO64rm | |
| { 423, 3, 1, 0, 0, "CMOVNO64rr", 0|(1<<MCID::Commutable), 0x82002105ULL, ImplicitList1, NULL, OperandInfo27 }, // Inst #423 = CMOVNO64rr | |
| { 424, 7, 1, 0, 0, "CMOVNP16rm", 0|(1<<MCID::MayLoad), 0x96000146ULL, ImplicitList1, NULL, OperandInfo18 }, // Inst #424 = CMOVNP16rm | |
| { 425, 3, 1, 0, 0, "CMOVNP16rr", 0|(1<<MCID::Commutable), 0x96000145ULL, ImplicitList1, NULL, OperandInfo19 }, // Inst #425 = CMOVNP16rr | |
| { 426, 7, 1, 0, 0, "CMOVNP32rm", 0|(1<<MCID::MayLoad), 0x96000106ULL, ImplicitList1, NULL, OperandInfo22 }, // Inst #426 = CMOVNP32rm | |
| { 427, 3, 1, 0, 0, "CMOVNP32rr", 0|(1<<MCID::Commutable), 0x96000105ULL, ImplicitList1, NULL, OperandInfo23 }, // Inst #427 = CMOVNP32rr | |
| { 428, 7, 1, 0, 0, "CMOVNP64rm", 0|(1<<MCID::MayLoad), 0x96002106ULL, ImplicitList1, NULL, OperandInfo26 }, // Inst #428 = CMOVNP64rm | |
| { 429, 3, 1, 0, 0, "CMOVNP64rr", 0|(1<<MCID::Commutable), 0x96002105ULL, ImplicitList1, NULL, OperandInfo27 }, // Inst #429 = CMOVNP64rr | |
| { 430, 1, 1, 0, 0, "CMOVNP_F", 0|(1<<MCID::UnmodeledSideEffects), 0x1b0000602ULL, NULL, NULL, OperandInfo39 }, // Inst #430 = CMOVNP_F | |
| { 431, 3, 1, 0, 0, "CMOVNP_Fp32", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo75 }, // Inst #431 = CMOVNP_Fp32 | |
| { 432, 3, 1, 0, 0, "CMOVNP_Fp64", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo76 }, // Inst #432 = CMOVNP_Fp64 | |
| { 433, 3, 1, 0, 0, "CMOVNP_Fp80", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo77 }, // Inst #433 = CMOVNP_Fp80 | |
| { 434, 7, 1, 0, 0, "CMOVNS16rm", 0|(1<<MCID::MayLoad), 0x92000146ULL, ImplicitList1, NULL, OperandInfo18 }, // Inst #434 = CMOVNS16rm | |
| { 435, 3, 1, 0, 0, "CMOVNS16rr", 0|(1<<MCID::Commutable), 0x92000145ULL, ImplicitList1, NULL, OperandInfo19 }, // Inst #435 = CMOVNS16rr | |
| { 436, 7, 1, 0, 0, "CMOVNS32rm", 0|(1<<MCID::MayLoad), 0x92000106ULL, ImplicitList1, NULL, OperandInfo22 }, // Inst #436 = CMOVNS32rm | |
| { 437, 3, 1, 0, 0, "CMOVNS32rr", 0|(1<<MCID::Commutable), 0x92000105ULL, ImplicitList1, NULL, OperandInfo23 }, // Inst #437 = CMOVNS32rr | |
| { 438, 7, 1, 0, 0, "CMOVNS64rm", 0|(1<<MCID::MayLoad), 0x92002106ULL, ImplicitList1, NULL, OperandInfo26 }, // Inst #438 = CMOVNS64rm | |
| { 439, 3, 1, 0, 0, "CMOVNS64rr", 0|(1<<MCID::Commutable), 0x92002105ULL, ImplicitList1, NULL, OperandInfo27 }, // Inst #439 = CMOVNS64rr | |
| { 440, 7, 1, 0, 0, "CMOVO16rm", 0|(1<<MCID::MayLoad), 0x80000146ULL, ImplicitList1, NULL, OperandInfo18 }, // Inst #440 = CMOVO16rm | |
| { 441, 3, 1, 0, 0, "CMOVO16rr", 0|(1<<MCID::Commutable), 0x80000145ULL, ImplicitList1, NULL, OperandInfo19 }, // Inst #441 = CMOVO16rr | |
| { 442, 7, 1, 0, 0, "CMOVO32rm", 0|(1<<MCID::MayLoad), 0x80000106ULL, ImplicitList1, NULL, OperandInfo22 }, // Inst #442 = CMOVO32rm | |
| { 443, 3, 1, 0, 0, "CMOVO32rr", 0|(1<<MCID::Commutable), 0x80000105ULL, ImplicitList1, NULL, OperandInfo23 }, // Inst #443 = CMOVO32rr | |
| { 444, 7, 1, 0, 0, "CMOVO64rm", 0|(1<<MCID::MayLoad), 0x80002106ULL, ImplicitList1, NULL, OperandInfo26 }, // Inst #444 = CMOVO64rm | |
| { 445, 3, 1, 0, 0, "CMOVO64rr", 0|(1<<MCID::Commutable), 0x80002105ULL, ImplicitList1, NULL, OperandInfo27 }, // Inst #445 = CMOVO64rr | |
| { 446, 7, 1, 0, 0, "CMOVP16rm", 0|(1<<MCID::MayLoad), 0x94000146ULL, ImplicitList1, NULL, OperandInfo18 }, // Inst #446 = CMOVP16rm | |
| { 447, 3, 1, 0, 0, "CMOVP16rr", 0|(1<<MCID::Commutable), 0x94000145ULL, ImplicitList1, NULL, OperandInfo19 }, // Inst #447 = CMOVP16rr | |
| { 448, 7, 1, 0, 0, "CMOVP32rm", 0|(1<<MCID::MayLoad), 0x94000106ULL, ImplicitList1, NULL, OperandInfo22 }, // Inst #448 = CMOVP32rm | |
| { 449, 3, 1, 0, 0, "CMOVP32rr", 0|(1<<MCID::Commutable), 0x94000105ULL, ImplicitList1, NULL, OperandInfo23 }, // Inst #449 = CMOVP32rr | |
| { 450, 7, 1, 0, 0, "CMOVP64rm", 0|(1<<MCID::MayLoad), 0x94002106ULL, ImplicitList1, NULL, OperandInfo26 }, // Inst #450 = CMOVP64rm | |
| { 451, 3, 1, 0, 0, "CMOVP64rr", 0|(1<<MCID::Commutable), 0x94002105ULL, ImplicitList1, NULL, OperandInfo27 }, // Inst #451 = CMOVP64rr | |
| { 452, 1, 1, 0, 0, "CMOVP_F", 0|(1<<MCID::UnmodeledSideEffects), 0x1b0000502ULL, NULL, NULL, OperandInfo39 }, // Inst #452 = CMOVP_F | |
| { 453, 3, 1, 0, 0, "CMOVP_Fp32", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo75 }, // Inst #453 = CMOVP_Fp32 | |
| { 454, 3, 1, 0, 0, "CMOVP_Fp64", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo76 }, // Inst #454 = CMOVP_Fp64 | |
| { 455, 3, 1, 0, 0, "CMOVP_Fp80", 0, 0xc0000ULL, ImplicitList1, NULL, OperandInfo77 }, // Inst #455 = CMOVP_Fp80 | |
| { 456, 7, 1, 0, 0, "CMOVS16rm", 0|(1<<MCID::MayLoad), 0x90000146ULL, ImplicitList1, NULL, OperandInfo18 }, // Inst #456 = CMOVS16rm | |
| { 457, 3, 1, 0, 0, "CMOVS16rr", 0|(1<<MCID::Commutable), 0x90000145ULL, ImplicitList1, NULL, OperandInfo19 }, // Inst #457 = CMOVS16rr | |
| { 458, 7, 1, 0, 0, "CMOVS32rm", 0|(1<<MCID::MayLoad), 0x90000106ULL, ImplicitList1, NULL, OperandInfo22 }, // Inst #458 = CMOVS32rm | |
| { 459, 3, 1, 0, 0, "CMOVS32rr", 0|(1<<MCID::Commutable), 0x90000105ULL, ImplicitList1, NULL, OperandInfo23 }, // Inst #459 = CMOVS32rr | |
| { 460, 7, 1, 0, 0, "CMOVS64rm", 0|(1<<MCID::MayLoad), 0x90002106ULL, ImplicitList1, NULL, OperandInfo26 }, // Inst #460 = CMOVS64rm | |
| { 461, 3, 1, 0, 0, "CMOVS64rr", 0|(1<<MCID::Commutable), 0x90002105ULL, ImplicitList1, NULL, OperandInfo27 }, // Inst #461 = CMOVS64rr | |
| { 462, 4, 1, 0, 0, "CMOV_FR32", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, NULL, OperandInfo78 }, // Inst #462 = CMOV_FR32 | |
| { 463, 4, 1, 0, 0, "CMOV_FR64", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, NULL, OperandInfo79 }, // Inst #463 = CMOV_FR64 | |
| { 464, 4, 1, 0, 0, "CMOV_GR16", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, NULL, OperandInfo80 }, // Inst #464 = CMOV_GR16 | |
| { 465, 4, 1, 0, 0, "CMOV_GR32", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, NULL, OperandInfo81 }, // Inst #465 = CMOV_GR32 | |
| { 466, 4, 1, 0, 0, "CMOV_GR8", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, NULL, OperandInfo82 }, // Inst #466 = CMOV_GR8 | |
| { 467, 4, 1, 0, 0, "CMOV_RFP32", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, NULL, OperandInfo83 }, // Inst #467 = CMOV_RFP32 | |
| { 468, 4, 1, 0, 0, "CMOV_RFP64", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, NULL, OperandInfo84 }, // Inst #468 = CMOV_RFP64 | |
| { 469, 4, 1, 0, 0, "CMOV_RFP80", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, NULL, OperandInfo85 }, // Inst #469 = CMOV_RFP80 | |
| { 470, 4, 1, 0, 0, "CMOV_V2F64", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, NULL, OperandInfo86 }, // Inst #470 = CMOV_V2F64 | |
| { 471, 4, 1, 0, 0, "CMOV_V2I64", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, NULL, OperandInfo86 }, // Inst #471 = CMOV_V2I64 | |
| { 472, 4, 1, 0, 0, "CMOV_V4F32", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, NULL, OperandInfo86 }, // Inst #472 = CMOV_V4F32 | |
| { 473, 4, 1, 0, 0, "CMOV_V4F64", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, NULL, OperandInfo87 }, // Inst #473 = CMOV_V4F64 | |
| { 474, 4, 1, 0, 0, "CMOV_V4I64", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, NULL, OperandInfo87 }, // Inst #474 = CMOV_V4I64 | |
| { 475, 4, 1, 0, 0, "CMOV_V8F32", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, NULL, OperandInfo87 }, // Inst #475 = CMOV_V8F32 | |
| { 476, 1, 0, 0, 0, "CMP16i16", 0|(1<<MCID::UnmodeledSideEffects), 0x7a00c041ULL, ImplicitList2, ImplicitList1, OperandInfo2 }, // Inst #476 = CMP16i16 | |
| { 477, 6, 0, 0, 0, "CMP16mi", 0|(1<<MCID::MayLoad), 0x10200c05fULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #477 = CMP16mi | |
| { 478, 6, 0, 0, 0, "CMP16mi8", 0|(1<<MCID::MayLoad), 0x10600405fULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #478 = CMP16mi8 | |
| { 479, 6, 0, 0, 0, "CMP16mr", 0|(1<<MCID::MayLoad), 0x72000044ULL, NULL, ImplicitList1, OperandInfo16 }, // Inst #479 = CMP16mr | |
| { 480, 2, 0, 0, 0, "CMP16ri", 0, 0x10200c057ULL, NULL, ImplicitList1, OperandInfo69 }, // Inst #480 = CMP16ri | |
| { 481, 2, 0, 0, 0, "CMP16ri8", 0, 0x106004057ULL, NULL, ImplicitList1, OperandInfo69 }, // Inst #481 = CMP16ri8 | |
| { 482, 6, 0, 0, 0, "CMP16rm", 0|(1<<MCID::MayLoad), 0x76000046ULL, NULL, ImplicitList1, OperandInfo11 }, // Inst #482 = CMP16rm | |
| { 483, 2, 0, 0, 0, "CMP16rr", 0, 0x72000043ULL, NULL, ImplicitList1, OperandInfo55 }, // Inst #483 = CMP16rr | |
| { 484, 2, 0, 0, 0, "CMP16rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x76000045ULL, NULL, ImplicitList1, OperandInfo55 }, // Inst #484 = CMP16rr_REV | |
| { 485, 1, 0, 0, 0, "CMP32i32", 0|(1<<MCID::UnmodeledSideEffects), 0x7a014001ULL, ImplicitList3, ImplicitList1, OperandInfo2 }, // Inst #485 = CMP32i32 | |
| { 486, 6, 0, 0, 0, "CMP32mi", 0|(1<<MCID::MayLoad), 0x10201401fULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #486 = CMP32mi | |
| { 487, 6, 0, 0, 0, "CMP32mi8", 0|(1<<MCID::MayLoad), 0x10600401fULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #487 = CMP32mi8 | |
| { 488, 6, 0, 0, 0, "CMP32mr", 0|(1<<MCID::MayLoad), 0x72000004ULL, NULL, ImplicitList1, OperandInfo20 }, // Inst #488 = CMP32mr | |
| { 489, 2, 0, 0, 0, "CMP32ri", 0, 0x102014017ULL, NULL, ImplicitList1, OperandInfo70 }, // Inst #489 = CMP32ri | |
| { 490, 2, 0, 0, 0, "CMP32ri8", 0, 0x106004017ULL, NULL, ImplicitList1, OperandInfo70 }, // Inst #490 = CMP32ri8 | |
| { 491, 6, 0, 0, 0, "CMP32rm", 0|(1<<MCID::MayLoad), 0x76000006ULL, NULL, ImplicitList1, OperandInfo12 }, // Inst #491 = CMP32rm | |
| { 492, 2, 0, 0, 0, "CMP32rr", 0, 0x72000003ULL, NULL, ImplicitList1, OperandInfo65 }, // Inst #492 = CMP32rr | |
| { 493, 2, 0, 0, 0, "CMP32rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x76000005ULL, NULL, ImplicitList1, OperandInfo65 }, // Inst #493 = CMP32rr_REV | |
| { 494, 1, 0, 0, 0, "CMP64i32", 0|(1<<MCID::UnmodeledSideEffects), 0x7a016001ULL, ImplicitList4, ImplicitList1, OperandInfo2 }, // Inst #494 = CMP64i32 | |
| { 495, 6, 0, 0, 0, "CMP64mi32", 0|(1<<MCID::MayLoad), 0x10201601fULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #495 = CMP64mi32 | |
| { 496, 6, 0, 0, 0, "CMP64mi8", 0|(1<<MCID::MayLoad), 0x10600601fULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #496 = CMP64mi8 | |
| { 497, 6, 0, 0, 0, "CMP64mr", 0|(1<<MCID::MayLoad), 0x72002004ULL, NULL, ImplicitList1, OperandInfo24 }, // Inst #497 = CMP64mr | |
| { 498, 2, 0, 0, 0, "CMP64ri32", 0, 0x102016017ULL, NULL, ImplicitList1, OperandInfo71 }, // Inst #498 = CMP64ri32 | |
| { 499, 2, 0, 0, 0, "CMP64ri8", 0, 0x106006017ULL, NULL, ImplicitList1, OperandInfo71 }, // Inst #499 = CMP64ri8 | |
| { 500, 6, 0, 0, 0, "CMP64rm", 0|(1<<MCID::MayLoad), 0x76002006ULL, NULL, ImplicitList1, OperandInfo13 }, // Inst #500 = CMP64rm | |
| { 501, 2, 0, 0, 0, "CMP64rr", 0, 0x72002003ULL, NULL, ImplicitList1, OperandInfo66 }, // Inst #501 = CMP64rr | |
| { 502, 2, 0, 0, 0, "CMP64rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x76002005ULL, NULL, ImplicitList1, OperandInfo66 }, // Inst #502 = CMP64rr_REV | |
| { 503, 1, 0, 0, 0, "CMP8i8", 0|(1<<MCID::UnmodeledSideEffects), 0x78004001ULL, ImplicitList5, ImplicitList1, OperandInfo2 }, // Inst #503 = CMP8i8 | |
| { 504, 6, 0, 0, 0, "CMP8mi", 0|(1<<MCID::MayLoad), 0x10000401fULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #504 = CMP8mi | |
| { 505, 6, 0, 0, 0, "CMP8mr", 0|(1<<MCID::MayLoad), 0x70000004ULL, NULL, ImplicitList1, OperandInfo28 }, // Inst #505 = CMP8mr | |
| { 506, 2, 0, 0, 0, "CMP8ri", 0, 0x100004017ULL, NULL, ImplicitList1, OperandInfo88 }, // Inst #506 = CMP8ri | |
| { 507, 6, 0, 0, 0, "CMP8rm", 0|(1<<MCID::MayLoad), 0x74000006ULL, NULL, ImplicitList1, OperandInfo14 }, // Inst #507 = CMP8rm | |
| { 508, 2, 0, 0, 0, "CMP8rr", 0, 0x70000003ULL, NULL, ImplicitList1, OperandInfo89 }, // Inst #508 = CMP8rr | |
| { 509, 2, 0, 0, 0, "CMP8rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x74000005ULL, NULL, ImplicitList1, OperandInfo89 }, // Inst #509 = CMP8rr_REV | |
| { 510, 8, 1, 0, 0, "CMPPDrmi", 0|(1<<MCID::MayLoad), 0x185004146ULL, NULL, NULL, OperandInfo63 }, // Inst #510 = CMPPDrmi | |
| { 511, 8, 1, 0, 0, "CMPPDrmi_alt", 0|(1<<MCID::UnmodeledSideEffects), 0x185004146ULL, NULL, NULL, OperandInfo63 }, // Inst #511 = CMPPDrmi_alt | |
| { 512, 4, 1, 0, 0, "CMPPDrri", 0, 0x185004145ULL, NULL, NULL, OperandInfo64 }, // Inst #512 = CMPPDrri | |
| { 513, 4, 1, 0, 0, "CMPPDrri_alt", 0|(1<<MCID::UnmodeledSideEffects), 0x185004145ULL, NULL, NULL, OperandInfo64 }, // Inst #513 = CMPPDrri_alt | |
| { 514, 8, 1, 0, 0, "CMPPSrmi", 0|(1<<MCID::MayLoad), 0x184804106ULL, NULL, NULL, OperandInfo63 }, // Inst #514 = CMPPSrmi | |
| { 515, 8, 1, 0, 0, "CMPPSrmi_alt", 0|(1<<MCID::UnmodeledSideEffects), 0x184804106ULL, NULL, NULL, OperandInfo63 }, // Inst #515 = CMPPSrmi_alt | |
| { 516, 4, 1, 0, 0, "CMPPSrri", 0, 0x184804105ULL, NULL, NULL, OperandInfo64 }, // Inst #516 = CMPPSrri | |
| { 517, 4, 1, 0, 0, "CMPPSrri_alt", 0|(1<<MCID::UnmodeledSideEffects), 0x184804105ULL, NULL, NULL, OperandInfo64 }, // Inst #517 = CMPPSrri_alt | |
| { 518, 0, 0, 0, 0, "CMPS16", 0|(1<<MCID::UnmodeledSideEffects), 0x14e000041ULL, NULL, NULL, 0 }, // Inst #518 = CMPS16 | |
| { 519, 0, 0, 0, 0, "CMPS32", 0|(1<<MCID::UnmodeledSideEffects), 0x14e000001ULL, NULL, NULL, 0 }, // Inst #519 = CMPS32 | |
| { 520, 0, 0, 0, 0, "CMPS64", 0|(1<<MCID::UnmodeledSideEffects), 0x14e002001ULL, NULL, NULL, 0 }, // Inst #520 = CMPS64 | |
| { 521, 0, 0, 0, 0, "CMPS8", 0|(1<<MCID::UnmodeledSideEffects), 0x14c000001ULL, NULL, NULL, 0 }, // Inst #521 = CMPS8 | |
| { 522, 8, 1, 0, 0, "CMPSDrm", 0|(1<<MCID::MayLoad), 0x184004b06ULL, NULL, NULL, OperandInfo90 }, // Inst #522 = CMPSDrm | |
| { 523, 8, 1, 0, 0, "CMPSDrm_alt", 0|(1<<MCID::MayLoad), 0x184004b06ULL, NULL, NULL, OperandInfo90 }, // Inst #523 = CMPSDrm_alt | |
| { 524, 4, 1, 0, 0, "CMPSDrr", 0, 0x184004b05ULL, NULL, NULL, OperandInfo91 }, // Inst #524 = CMPSDrr | |
| { 525, 4, 1, 0, 0, "CMPSDrr_alt", 0, 0x184004b05ULL, NULL, NULL, OperandInfo91 }, // Inst #525 = CMPSDrr_alt | |
| { 526, 8, 1, 0, 0, "CMPSSrm", 0|(1<<MCID::MayLoad), 0x184004c06ULL, NULL, NULL, OperandInfo92 }, // Inst #526 = CMPSSrm | |
| { 527, 8, 1, 0, 0, "CMPSSrm_alt", 0|(1<<MCID::MayLoad), 0x184004c06ULL, NULL, NULL, OperandInfo92 }, // Inst #527 = CMPSSrm_alt | |
| { 528, 4, 1, 0, 0, "CMPSSrr", 0, 0x184004c05ULL, NULL, NULL, OperandInfo93 }, // Inst #528 = CMPSSrr | |
| { 529, 4, 1, 0, 0, "CMPSSrr_alt", 0, 0x184004c05ULL, NULL, NULL, OperandInfo93 }, // Inst #529 = CMPSSrr_alt | |
| { 530, 5, 0, 0, 0, "CMPXCHG16B", 0|(1<<MCID::UnmodeledSideEffects), 0x18e002119ULL, ImplicitList16, ImplicitList17, OperandInfo38 }, // Inst #530 = CMPXCHG16B | |
| { 531, 6, 0, 0, 0, "CMPXCHG16rm", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x162000144ULL, NULL, NULL, OperandInfo16 }, // Inst #531 = CMPXCHG16rm | |
| { 532, 2, 1, 0, 0, "CMPXCHG16rr", 0|(1<<MCID::UnmodeledSideEffects), 0x162000143ULL, NULL, NULL, OperandInfo55 }, // Inst #532 = CMPXCHG16rr | |
| { 533, 6, 0, 0, 0, "CMPXCHG32rm", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x162000104ULL, NULL, NULL, OperandInfo20 }, // Inst #533 = CMPXCHG32rm | |
| { 534, 2, 1, 0, 0, "CMPXCHG32rr", 0|(1<<MCID::UnmodeledSideEffects), 0x162000103ULL, NULL, NULL, OperandInfo65 }, // Inst #534 = CMPXCHG32rr | |
| { 535, 6, 0, 0, 0, "CMPXCHG64rm", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x162002104ULL, NULL, NULL, OperandInfo24 }, // Inst #535 = CMPXCHG64rm | |
| { 536, 2, 1, 0, 0, "CMPXCHG64rr", 0|(1<<MCID::UnmodeledSideEffects), 0x162002103ULL, NULL, NULL, OperandInfo66 }, // Inst #536 = CMPXCHG64rr | |
| { 537, 5, 0, 0, 0, "CMPXCHG8B", 0|(1<<MCID::UnmodeledSideEffects), 0x18e000119ULL, ImplicitList10, ImplicitList18, OperandInfo38 }, // Inst #537 = CMPXCHG8B | |
| { 538, 6, 0, 0, 0, "CMPXCHG8rm", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x160000104ULL, NULL, NULL, OperandInfo28 }, // Inst #538 = CMPXCHG8rm | |
| { 539, 2, 1, 0, 0, "CMPXCHG8rr", 0|(1<<MCID::UnmodeledSideEffects), 0x160000103ULL, NULL, NULL, OperandInfo89 }, // Inst #539 = CMPXCHG8rr | |
| { 540, 6, 0, 0, 0, "COMISDrm", 0|(1<<MCID::UnmodeledSideEffects), 0x5f000146ULL, NULL, ImplicitList1, OperandInfo47 }, // Inst #540 = COMISDrm | |
| { 541, 2, 0, 0, 0, "COMISDrr", 0|(1<<MCID::UnmodeledSideEffects), 0x5f000145ULL, NULL, ImplicitList1, OperandInfo48 }, // Inst #541 = COMISDrr | |
| { 542, 6, 0, 0, 0, "COMISSrm", 0|(1<<MCID::UnmodeledSideEffects), 0x5e800106ULL, NULL, ImplicitList1, OperandInfo47 }, // Inst #542 = COMISSrm | |
| { 543, 2, 0, 0, 0, "COMISSrr", 0|(1<<MCID::UnmodeledSideEffects), 0x5e800105ULL, NULL, ImplicitList1, OperandInfo48 }, // Inst #543 = COMISSrr | |
| { 544, 1, 0, 0, 0, "COMP_FST0r", 0|(1<<MCID::UnmodeledSideEffects), 0x1b0000302ULL, NULL, NULL, OperandInfo39 }, // Inst #544 = COMP_FST0r | |
| { 545, 1, 0, 0, 0, "COM_FIPr", 0|(1<<MCID::UnmodeledSideEffects), 0x1e0000a02ULL, NULL, NULL, OperandInfo39 }, // Inst #545 = COM_FIPr | |
| { 546, 1, 0, 0, 0, "COM_FIr", 0|(1<<MCID::UnmodeledSideEffects), 0x1e0000602ULL, NULL, NULL, OperandInfo39 }, // Inst #546 = COM_FIr | |
| { 547, 1, 0, 0, 0, "COM_FST0r", 0|(1<<MCID::UnmodeledSideEffects), 0x1a0000302ULL, NULL, NULL, OperandInfo39 }, // Inst #547 = COM_FST0r | |
| { 548, 0, 0, 0, 0, "COS_F", 0|(1<<MCID::UnmodeledSideEffects), 0x1fe000401ULL, NULL, NULL, 0 }, // Inst #548 = COS_F | |
| { 549, 2, 1, 0, 0, "COS_Fp32", 0, 0x60000ULL, NULL, NULL, OperandInfo8 }, // Inst #549 = COS_Fp32 | |
| { 550, 2, 1, 0, 0, "COS_Fp64", 0, 0x60000ULL, NULL, NULL, OperandInfo9 }, // Inst #550 = COS_Fp64 | |
| { 551, 2, 1, 0, 0, "COS_Fp80", 0, 0x60000ULL, NULL, NULL, OperandInfo10 }, // Inst #551 = COS_Fp80 | |
| { 552, 0, 0, 0, 0, "CPUID", 0|(1<<MCID::UnmodeledSideEffects), 0x144000101ULL, NULL, NULL, 0 }, // Inst #552 = CPUID | |
| { 553, 0, 0, 0, 0, "CQO", 0, 0x132002001ULL, ImplicitList4, ImplicitList19, 0 }, // Inst #553 = CQO | |
| { 554, 7, 1, 0, 0, "CRC32r32m16", 0|(1<<MCID::MayLoad), 0x1e2001146ULL, NULL, NULL, OperandInfo22 }, // Inst #554 = CRC32r32m16 | |
| { 555, 7, 1, 0, 0, "CRC32r32m32", 0|(1<<MCID::MayLoad), 0x1e2001106ULL, NULL, NULL, OperandInfo22 }, // Inst #555 = CRC32r32m32 | |
| { 556, 7, 1, 0, 0, "CRC32r32m8", 0|(1<<MCID::MayLoad), 0x1e0001106ULL, NULL, NULL, OperandInfo22 }, // Inst #556 = CRC32r32m8 | |
| { 557, 3, 1, 0, 0, "CRC32r32r16", 0, 0x1e2001145ULL, NULL, NULL, OperandInfo94 }, // Inst #557 = CRC32r32r16 | |
| { 558, 3, 1, 0, 0, "CRC32r32r32", 0, 0x1e2001105ULL, NULL, NULL, OperandInfo23 }, // Inst #558 = CRC32r32r32 | |
| { 559, 3, 1, 0, 0, "CRC32r32r8", 0, 0x1e0001105ULL, NULL, NULL, OperandInfo95 }, // Inst #559 = CRC32r32r8 | |
| { 560, 7, 1, 0, 0, "CRC32r64m64", 0|(1<<MCID::MayLoad), 0x1e2003106ULL, NULL, NULL, OperandInfo26 }, // Inst #560 = CRC32r64m64 | |
| { 561, 7, 1, 0, 0, "CRC32r64m8", 0|(1<<MCID::MayLoad), 0x1e0003106ULL, NULL, NULL, OperandInfo26 }, // Inst #561 = CRC32r64m8 | |
| { 562, 3, 1, 0, 0, "CRC32r64r64", 0, 0x1e2003105ULL, NULL, NULL, OperandInfo27 }, // Inst #562 = CRC32r64r64 | |
| { 563, 3, 1, 0, 0, "CRC32r64r8", 0, 0x1e0003105ULL, NULL, NULL, OperandInfo96 }, // Inst #563 = CRC32r64r8 | |
| { 564, 0, 0, 0, 0, "CS_PREFIX", 0|(1<<MCID::UnmodeledSideEffects), 0x5c000001ULL, NULL, NULL, 0 }, // Inst #564 = CS_PREFIX | |
| { 565, 6, 1, 0, 0, "CVTDQ2PDrm", 0|(1<<MCID::UnmodeledSideEffects), 0x1cc800c06ULL, NULL, NULL, OperandInfo47 }, // Inst #565 = CVTDQ2PDrm | |
| { 566, 2, 1, 0, 0, "CVTDQ2PDrr", 0|(1<<MCID::UnmodeledSideEffects), 0x1cc800c05ULL, NULL, NULL, OperandInfo48 }, // Inst #566 = CVTDQ2PDrr | |
| { 567, 6, 1, 0, 0, "CVTDQ2PSrm", 0|(1<<MCID::UnmodeledSideEffects), 0xb6800106ULL, NULL, NULL, OperandInfo47 }, // Inst #567 = CVTDQ2PSrm | |
| { 568, 2, 1, 0, 0, "CVTDQ2PSrr", 0|(1<<MCID::UnmodeledSideEffects), 0xb6800105ULL, NULL, NULL, OperandInfo48 }, // Inst #568 = CVTDQ2PSrr | |
| { 569, 6, 1, 0, 0, "CVTPD2DQrm", 0|(1<<MCID::UnmodeledSideEffects), 0x1cd000b06ULL, NULL, NULL, OperandInfo47 }, // Inst #569 = CVTPD2DQrm | |
| { 570, 2, 1, 0, 0, "CVTPD2DQrr", 0|(1<<MCID::UnmodeledSideEffects), 0x1cd000b05ULL, NULL, NULL, OperandInfo48 }, // Inst #570 = CVTPD2DQrr | |
| { 571, 6, 1, 0, 0, "CVTPD2PSrm", 0|(1<<MCID::UnmodeledSideEffects), 0xb5000146ULL, NULL, NULL, OperandInfo47 }, // Inst #571 = CVTPD2PSrm | |
| { 572, 2, 1, 0, 0, "CVTPD2PSrr", 0|(1<<MCID::UnmodeledSideEffects), 0xb5000145ULL, NULL, NULL, OperandInfo48 }, // Inst #572 = CVTPD2PSrr | |
| { 573, 6, 1, 0, 0, "CVTPS2DQrm", 0|(1<<MCID::UnmodeledSideEffects), 0xb7000146ULL, NULL, NULL, OperandInfo47 }, // Inst #573 = CVTPS2DQrm | |
| { 574, 2, 1, 0, 0, "CVTPS2DQrr", 0|(1<<MCID::UnmodeledSideEffects), 0xb7000145ULL, NULL, NULL, OperandInfo48 }, // Inst #574 = CVTPS2DQrr | |
| { 575, 6, 1, 0, 0, "CVTPS2PDrm", 0|(1<<MCID::UnmodeledSideEffects), 0xb4000106ULL, NULL, NULL, OperandInfo47 }, // Inst #575 = CVTPS2PDrm | |
| { 576, 2, 1, 0, 0, "CVTPS2PDrr", 0|(1<<MCID::UnmodeledSideEffects), 0xb4000105ULL, NULL, NULL, OperandInfo48 }, // Inst #576 = CVTPS2PDrr | |
| { 577, 6, 1, 0, 0, "CVTSD2SI64rm", 0|(1<<MCID::MayLoad), 0x5a002b06ULL, NULL, NULL, OperandInfo13 }, // Inst #577 = CVTSD2SI64rm | |
| { 578, 2, 1, 0, 0, "CVTSD2SI64rr", 0, 0x5a002b05ULL, NULL, NULL, OperandInfo97 }, // Inst #578 = CVTSD2SI64rr | |
| { 579, 6, 1, 0, 0, "CVTSD2SIrm", 0|(1<<MCID::MayLoad), 0x5a000b06ULL, NULL, NULL, OperandInfo12 }, // Inst #579 = CVTSD2SIrm | |
| { 580, 2, 1, 0, 0, "CVTSD2SIrr", 0, 0x5a000b05ULL, NULL, NULL, OperandInfo98 }, // Inst #580 = CVTSD2SIrr | |
| { 581, 6, 1, 0, 0, "CVTSD2SSrm", 0|(1<<MCID::MayLoad), 0xb4000b06ULL, NULL, NULL, OperandInfo99 }, // Inst #581 = CVTSD2SSrm | |
| { 582, 2, 1, 0, 0, "CVTSD2SSrr", 0, 0xb4000b05ULL, NULL, NULL, OperandInfo100 }, // Inst #582 = CVTSD2SSrr | |
| { 583, 6, 1, 0, 0, "CVTSI2SD64rm", 0|(1<<MCID::MayLoad), 0x54002b06ULL, NULL, NULL, OperandInfo101 }, // Inst #583 = CVTSI2SD64rm | |
| { 584, 2, 1, 0, 0, "CVTSI2SD64rr", 0, 0x54002b05ULL, NULL, NULL, OperandInfo102 }, // Inst #584 = CVTSI2SD64rr | |
| { 585, 6, 1, 0, 0, "CVTSI2SDrm", 0|(1<<MCID::MayLoad), 0x54000b06ULL, NULL, NULL, OperandInfo101 }, // Inst #585 = CVTSI2SDrm | |
| { 586, 2, 1, 0, 0, "CVTSI2SDrr", 0, 0x54000b05ULL, NULL, NULL, OperandInfo103 }, // Inst #586 = CVTSI2SDrr | |
| { 587, 6, 1, 0, 0, "CVTSI2SS64rm", 0|(1<<MCID::MayLoad), 0x54002c06ULL, NULL, NULL, OperandInfo99 }, // Inst #587 = CVTSI2SS64rm | |
| { 588, 2, 1, 0, 0, "CVTSI2SS64rr", 0, 0x54002c05ULL, NULL, NULL, OperandInfo104 }, // Inst #588 = CVTSI2SS64rr | |
| { 589, 6, 1, 0, 0, "CVTSI2SSrm", 0|(1<<MCID::MayLoad), 0x54000c06ULL, NULL, NULL, OperandInfo99 }, // Inst #589 = CVTSI2SSrm | |
| { 590, 2, 1, 0, 0, "CVTSI2SSrr", 0, 0x54000c05ULL, NULL, NULL, OperandInfo105 }, // Inst #590 = CVTSI2SSrr | |
| { 591, 6, 1, 0, 0, "CVTSS2SDrm", 0|(1<<MCID::MayLoad), 0xb4000c06ULL, NULL, NULL, OperandInfo101 }, // Inst #591 = CVTSS2SDrm | |
| { 592, 2, 1, 0, 0, "CVTSS2SDrr", 0, 0xb4000c05ULL, NULL, NULL, OperandInfo106 }, // Inst #592 = CVTSS2SDrr | |
| { 593, 6, 1, 0, 0, "CVTSS2SI64rm", 0|(1<<MCID::UnmodeledSideEffects), 0x5a002c06ULL, NULL, NULL, OperandInfo13 }, // Inst #593 = CVTSS2SI64rm | |
| { 594, 2, 1, 0, 0, "CVTSS2SI64rr", 0|(1<<MCID::UnmodeledSideEffects), 0x5a002c05ULL, NULL, NULL, OperandInfo107 }, // Inst #594 = CVTSS2SI64rr | |
| { 595, 6, 1, 0, 0, "CVTSS2SIrm", 0|(1<<MCID::UnmodeledSideEffects), 0x5a000c06ULL, NULL, NULL, OperandInfo12 }, // Inst #595 = CVTSS2SIrm | |
| { 596, 2, 1, 0, 0, "CVTSS2SIrr", 0|(1<<MCID::UnmodeledSideEffects), 0x5a000c05ULL, NULL, NULL, OperandInfo108 }, // Inst #596 = CVTSS2SIrr | |
| { 597, 6, 1, 0, 0, "CVTTPD2DQrm", 0|(1<<MCID::MayLoad), 0x1cd000146ULL, NULL, NULL, OperandInfo47 }, // Inst #597 = CVTTPD2DQrm | |
| { 598, 2, 1, 0, 0, "CVTTPD2DQrr", 0, 0x1cd000145ULL, NULL, NULL, OperandInfo48 }, // Inst #598 = CVTTPD2DQrr | |
| { 599, 6, 1, 0, 0, "CVTTPS2DQrm", 0|(1<<MCID::MayLoad), 0xb6000c06ULL, NULL, NULL, OperandInfo47 }, // Inst #599 = CVTTPS2DQrm | |
| { 600, 2, 1, 0, 0, "CVTTPS2DQrr", 0, 0xb6000c05ULL, NULL, NULL, OperandInfo48 }, // Inst #600 = CVTTPS2DQrr | |
| { 601, 6, 1, 0, 0, "CVTTSD2SI64rm", 0|(1<<MCID::MayLoad), 0x58002b06ULL, NULL, NULL, OperandInfo13 }, // Inst #601 = CVTTSD2SI64rm | |
| { 602, 2, 1, 0, 0, "CVTTSD2SI64rr", 0, 0x58002b05ULL, NULL, NULL, OperandInfo109 }, // Inst #602 = CVTTSD2SI64rr | |
| { 603, 6, 1, 0, 0, "CVTTSD2SIrm", 0|(1<<MCID::MayLoad), 0x58000b06ULL, NULL, NULL, OperandInfo12 }, // Inst #603 = CVTTSD2SIrm | |
| { 604, 2, 1, 0, 0, "CVTTSD2SIrr", 0, 0x58000b05ULL, NULL, NULL, OperandInfo110 }, // Inst #604 = CVTTSD2SIrr | |
| { 605, 6, 1, 0, 0, "CVTTSS2SI64rm", 0|(1<<MCID::MayLoad), 0x58002c06ULL, NULL, NULL, OperandInfo13 }, // Inst #605 = CVTTSS2SI64rm | |
| { 606, 2, 1, 0, 0, "CVTTSS2SI64rr", 0, 0x58002c05ULL, NULL, NULL, OperandInfo107 }, // Inst #606 = CVTTSS2SI64rr | |
| { 607, 6, 1, 0, 0, "CVTTSS2SIrm", 0|(1<<MCID::MayLoad), 0x58000c06ULL, NULL, NULL, OperandInfo12 }, // Inst #607 = CVTTSS2SIrm | |
| { 608, 2, 1, 0, 0, "CVTTSS2SIrr", 0, 0x58000c05ULL, NULL, NULL, OperandInfo108 }, // Inst #608 = CVTTSS2SIrr | |
| { 609, 0, 0, 0, 0, "CWD", 0, 0x132000041ULL, ImplicitList2, ImplicitList20, 0 }, // Inst #609 = CWD | |
| { 610, 0, 0, 0, 0, "CWDE", 0, 0x130000001ULL, ImplicitList2, ImplicitList3, 0 }, // Inst #610 = CWDE | |
| { 611, 0, 0, 0, 0, "DAA", 0|(1<<MCID::UnmodeledSideEffects), 0x4e000001ULL, NULL, NULL, 0 }, // Inst #611 = DAA | |
| { 612, 0, 0, 0, 0, "DAS", 0|(1<<MCID::UnmodeledSideEffects), 0x5e000001ULL, NULL, NULL, 0 }, // Inst #612 = DAS | |
| { 613, 0, 0, 0, 0, "DATA16_PREFIX", 0|(1<<MCID::UnmodeledSideEffects), 0xcc000001ULL, NULL, NULL, 0 }, // Inst #613 = DATA16_PREFIX | |
| { 614, 5, 0, 0, 0, "DEC16m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1fe000059ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #614 = DEC16m | |
| { 615, 2, 1, 0, 0, "DEC16r", 0|(1<<MCID::ConvertibleTo3Addr), 0x90000042ULL, NULL, ImplicitList1, OperandInfo111 }, // Inst #615 = DEC16r | |
| { 616, 5, 0, 0, 0, "DEC32m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1fe000019ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #616 = DEC32m | |
| { 617, 2, 1, 0, 0, "DEC32r", 0|(1<<MCID::ConvertibleTo3Addr), 0x90000002ULL, NULL, ImplicitList1, OperandInfo67 }, // Inst #617 = DEC32r | |
| { 618, 5, 0, 0, 0, "DEC64_16m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1fe000059ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #618 = DEC64_16m | |
| { 619, 2, 1, 0, 0, "DEC64_16r", 0|(1<<MCID::ConvertibleTo3Addr), 0x1fe000051ULL, NULL, ImplicitList1, OperandInfo111 }, // Inst #619 = DEC64_16r | |
| { 620, 5, 0, 0, 0, "DEC64_32m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1fe000019ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #620 = DEC64_32m | |
| { 621, 2, 1, 0, 0, "DEC64_32r", 0|(1<<MCID::ConvertibleTo3Addr), 0x1fe000011ULL, NULL, ImplicitList1, OperandInfo67 }, // Inst #621 = DEC64_32r | |
| { 622, 5, 0, 0, 0, "DEC64m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1fe002019ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #622 = DEC64m | |
| { 623, 2, 1, 0, 0, "DEC64r", 0|(1<<MCID::ConvertibleTo3Addr), 0x1fe002011ULL, NULL, ImplicitList1, OperandInfo68 }, // Inst #623 = DEC64r | |
| { 624, 5, 0, 0, 0, "DEC8m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1fc000019ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #624 = DEC8m | |
| { 625, 2, 1, 0, 0, "DEC8r", 0, 0x1fc000011ULL, NULL, ImplicitList1, OperandInfo112 }, // Inst #625 = DEC8r | |
| { 626, 5, 0, 0, 0, "DIV16m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1ee00005eULL, ImplicitList20, ImplicitList21, OperandInfo38 }, // Inst #626 = DIV16m | |
| { 627, 1, 0, 0, 0, "DIV16r", 0|(1<<MCID::UnmodeledSideEffects), 0x1ee000056ULL, ImplicitList20, ImplicitList21, OperandInfo113 }, // Inst #627 = DIV16r | |
| { 628, 5, 0, 0, 0, "DIV32m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1ee00001eULL, ImplicitList15, ImplicitList18, OperandInfo38 }, // Inst #628 = DIV32m | |
| { 629, 1, 0, 0, 0, "DIV32r", 0|(1<<MCID::UnmodeledSideEffects), 0x1ee000016ULL, ImplicitList15, ImplicitList18, OperandInfo72 }, // Inst #629 = DIV32r | |
| { 630, 5, 0, 0, 0, "DIV64m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1ee00201eULL, ImplicitList19, ImplicitList17, OperandInfo38 }, // Inst #630 = DIV64m | |
| { 631, 1, 0, 0, 0, "DIV64r", 0|(1<<MCID::UnmodeledSideEffects), 0x1ee002016ULL, ImplicitList19, ImplicitList17, OperandInfo74 }, // Inst #631 = DIV64r | |
| { 632, 5, 0, 0, 0, "DIV8m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1ec00001eULL, ImplicitList2, ImplicitList22, OperandInfo38 }, // Inst #632 = DIV8m | |
| { 633, 1, 0, 0, 0, "DIV8r", 0|(1<<MCID::UnmodeledSideEffects), 0x1ec000016ULL, ImplicitList2, ImplicitList22, OperandInfo114 }, // Inst #633 = DIV8r | |
| { 634, 7, 1, 0, 0, "DIVPDrm", 0|(1<<MCID::MayLoad), 0xbd000146ULL, NULL, NULL, OperandInfo32 }, // Inst #634 = DIVPDrm | |
| { 635, 3, 1, 0, 0, "DIVPDrr", 0, 0xbd000145ULL, NULL, NULL, OperandInfo33 }, // Inst #635 = DIVPDrr | |
| { 636, 7, 1, 0, 0, "DIVPSrm", 0|(1<<MCID::MayLoad), 0xbc800106ULL, NULL, NULL, OperandInfo32 }, // Inst #636 = DIVPSrm | |
| { 637, 3, 1, 0, 0, "DIVPSrr", 0, 0xbc800105ULL, NULL, NULL, OperandInfo33 }, // Inst #637 = DIVPSrr | |
| { 638, 5, 0, 0, 0, "DIVR_F32m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b000001fULL, NULL, NULL, OperandInfo38 }, // Inst #638 = DIVR_F32m | |
| { 639, 5, 0, 0, 0, "DIVR_F64m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b800001fULL, NULL, NULL, OperandInfo38 }, // Inst #639 = DIVR_F64m | |
| { 640, 5, 0, 0, 0, "DIVR_FI16m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1bc00001fULL, NULL, NULL, OperandInfo38 }, // Inst #640 = DIVR_FI16m | |
| { 641, 5, 0, 0, 0, "DIVR_FI32m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b400001fULL, NULL, NULL, OperandInfo38 }, // Inst #641 = DIVR_FI32m | |
| { 642, 1, 0, 0, 0, "DIVR_FPrST0", 0|(1<<MCID::UnmodeledSideEffects), 0x1e0000902ULL, NULL, NULL, OperandInfo39 }, // Inst #642 = DIVR_FPrST0 | |
| { 643, 1, 0, 0, 0, "DIVR_FST0r", 0|(1<<MCID::UnmodeledSideEffects), 0x1f0000302ULL, NULL, NULL, OperandInfo39 }, // Inst #643 = DIVR_FST0r | |
| { 644, 7, 1, 0, 0, "DIVR_Fp32m", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo41 }, // Inst #644 = DIVR_Fp32m | |
| { 645, 7, 1, 0, 0, "DIVR_Fp64m", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #645 = DIVR_Fp64m | |
| { 646, 7, 1, 0, 0, "DIVR_Fp64m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #646 = DIVR_Fp64m32 | |
| { 647, 7, 1, 0, 0, "DIVR_Fp80m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #647 = DIVR_Fp80m32 | |
| { 648, 7, 1, 0, 0, "DIVR_Fp80m64", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #648 = DIVR_Fp80m64 | |
| { 649, 7, 1, 0, 0, "DIVR_FpI16m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo41 }, // Inst #649 = DIVR_FpI16m32 | |
| { 650, 7, 1, 0, 0, "DIVR_FpI16m64", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #650 = DIVR_FpI16m64 | |
| { 651, 7, 1, 0, 0, "DIVR_FpI16m80", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #651 = DIVR_FpI16m80 | |
| { 652, 7, 1, 0, 0, "DIVR_FpI32m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo41 }, // Inst #652 = DIVR_FpI32m32 | |
| { 653, 7, 1, 0, 0, "DIVR_FpI32m64", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #653 = DIVR_FpI32m64 | |
| { 654, 7, 1, 0, 0, "DIVR_FpI32m80", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #654 = DIVR_FpI32m80 | |
| { 655, 1, 0, 0, 0, "DIVR_FrST0", 0|(1<<MCID::UnmodeledSideEffects), 0x1e0000702ULL, NULL, NULL, OperandInfo39 }, // Inst #655 = DIVR_FrST0 | |
| { 656, 7, 1, 0, 0, "DIVSDrm", 0|(1<<MCID::MayLoad), 0xbc000b06ULL, NULL, NULL, OperandInfo34 }, // Inst #656 = DIVSDrm | |
| { 657, 7, 1, 0, 0, "DIVSDrm_Int", 0|(1<<MCID::MayLoad), 0xbc000b06ULL, NULL, NULL, OperandInfo32 }, // Inst #657 = DIVSDrm_Int | |
| { 658, 3, 1, 0, 0, "DIVSDrr", 0, 0xbc000b05ULL, NULL, NULL, OperandInfo35 }, // Inst #658 = DIVSDrr | |
| { 659, 3, 1, 0, 0, "DIVSDrr_Int", 0, 0xbc000b05ULL, NULL, NULL, OperandInfo33 }, // Inst #659 = DIVSDrr_Int | |
| { 660, 7, 1, 0, 0, "DIVSSrm", 0|(1<<MCID::MayLoad), 0xbc000c06ULL, NULL, NULL, OperandInfo36 }, // Inst #660 = DIVSSrm | |
| { 661, 7, 1, 0, 0, "DIVSSrm_Int", 0|(1<<MCID::MayLoad), 0xbc000c06ULL, NULL, NULL, OperandInfo32 }, // Inst #661 = DIVSSrm_Int | |
| { 662, 3, 1, 0, 0, "DIVSSrr", 0, 0xbc000c05ULL, NULL, NULL, OperandInfo37 }, // Inst #662 = DIVSSrr | |
| { 663, 3, 1, 0, 0, "DIVSSrr_Int", 0, 0xbc000c05ULL, NULL, NULL, OperandInfo33 }, // Inst #663 = DIVSSrr_Int | |
| { 664, 5, 0, 0, 0, "DIV_F32m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b000001eULL, NULL, NULL, OperandInfo38 }, // Inst #664 = DIV_F32m | |
| { 665, 5, 0, 0, 0, "DIV_F64m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b800001eULL, NULL, NULL, OperandInfo38 }, // Inst #665 = DIV_F64m | |
| { 666, 5, 0, 0, 0, "DIV_FI16m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1bc00001eULL, NULL, NULL, OperandInfo38 }, // Inst #666 = DIV_FI16m | |
| { 667, 5, 0, 0, 0, "DIV_FI32m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b400001eULL, NULL, NULL, OperandInfo38 }, // Inst #667 = DIV_FI32m | |
| { 668, 1, 0, 0, 0, "DIV_FPrST0", 0|(1<<MCID::UnmodeledSideEffects), 0x1f0000902ULL, NULL, NULL, OperandInfo39 }, // Inst #668 = DIV_FPrST0 | |
| { 669, 1, 0, 0, 0, "DIV_FST0r", 0|(1<<MCID::UnmodeledSideEffects), 0x1e0000302ULL, NULL, NULL, OperandInfo39 }, // Inst #669 = DIV_FST0r | |
| { 670, 3, 1, 0, 0, "DIV_Fp32", 0, 0x80000ULL, NULL, NULL, OperandInfo40 }, // Inst #670 = DIV_Fp32 | |
| { 671, 7, 1, 0, 0, "DIV_Fp32m", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo41 }, // Inst #671 = DIV_Fp32m | |
| { 672, 3, 1, 0, 0, "DIV_Fp64", 0, 0x80000ULL, NULL, NULL, OperandInfo42 }, // Inst #672 = DIV_Fp64 | |
| { 673, 7, 1, 0, 0, "DIV_Fp64m", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #673 = DIV_Fp64m | |
| { 674, 7, 1, 0, 0, "DIV_Fp64m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #674 = DIV_Fp64m32 | |
| { 675, 3, 1, 0, 0, "DIV_Fp80", 0, 0x80000ULL, NULL, NULL, OperandInfo44 }, // Inst #675 = DIV_Fp80 | |
| { 676, 7, 1, 0, 0, "DIV_Fp80m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #676 = DIV_Fp80m32 | |
| { 677, 7, 1, 0, 0, "DIV_Fp80m64", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #677 = DIV_Fp80m64 | |
| { 678, 7, 1, 0, 0, "DIV_FpI16m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo41 }, // Inst #678 = DIV_FpI16m32 | |
| { 679, 7, 1, 0, 0, "DIV_FpI16m64", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #679 = DIV_FpI16m64 | |
| { 680, 7, 1, 0, 0, "DIV_FpI16m80", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #680 = DIV_FpI16m80 | |
| { 681, 7, 1, 0, 0, "DIV_FpI32m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo41 }, // Inst #681 = DIV_FpI32m32 | |
| { 682, 7, 1, 0, 0, "DIV_FpI32m64", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #682 = DIV_FpI32m64 | |
| { 683, 7, 1, 0, 0, "DIV_FpI32m80", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #683 = DIV_FpI32m80 | |
| { 684, 1, 0, 0, 0, "DIV_FrST0", 0|(1<<MCID::UnmodeledSideEffects), 0x1f0000702ULL, NULL, NULL, OperandInfo39 }, // Inst #684 = DIV_FrST0 | |
| { 685, 8, 1, 0, 0, "DPPDrmi", 0|(1<<MCID::MayLoad), 0x83804e46ULL, NULL, NULL, OperandInfo63 }, // Inst #685 = DPPDrmi | |
| { 686, 4, 1, 0, 0, "DPPDrri", 0|(1<<MCID::Commutable), 0x83804e45ULL, NULL, NULL, OperandInfo64 }, // Inst #686 = DPPDrri | |
| { 687, 8, 1, 0, 0, "DPPSrmi", 0|(1<<MCID::MayLoad), 0x81804e46ULL, NULL, NULL, OperandInfo63 }, // Inst #687 = DPPSrmi | |
| { 688, 4, 1, 0, 0, "DPPSrri", 0|(1<<MCID::Commutable), 0x81804e45ULL, NULL, NULL, OperandInfo64 }, // Inst #688 = DPPSrri | |
| { 689, 0, 0, 0, 0, "DS_PREFIX", 0|(1<<MCID::UnmodeledSideEffects), 0x7c000001ULL, NULL, NULL, 0 }, // Inst #689 = DS_PREFIX | |
| { 690, 1, 0, 0, 0, "EH_RETURN", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Terminator), 0x186000001ULL, NULL, NULL, OperandInfo72 }, // Inst #690 = EH_RETURN | |
| { 691, 1, 0, 0, 0, "EH_RETURN64", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Terminator), 0x186000001ULL, NULL, NULL, OperandInfo74 }, // Inst #691 = EH_RETURN64 | |
| { 692, 2, 0, 0, 0, "ENTER", 0|(1<<MCID::UnmodeledSideEffects), 0x19000c02bULL, NULL, NULL, OperandInfo46 }, // Inst #692 = ENTER | |
| { 693, 0, 0, 0, 0, "ES_PREFIX", 0|(1<<MCID::UnmodeledSideEffects), 0x4c000001ULL, NULL, NULL, 0 }, // Inst #693 = ES_PREFIX | |
| { 694, 7, 0, 0, 0, "EXTRACTPSmr", 0|(1<<MCID::MayStore), 0x2f804e44ULL, NULL, NULL, OperandInfo115 }, // Inst #694 = EXTRACTPSmr | |
| { 695, 3, 1, 0, 0, "EXTRACTPSrr", 0, 0x2f804e43ULL, NULL, NULL, OperandInfo116 }, // Inst #695 = EXTRACTPSrr | |
| { 696, 0, 0, 0, 0, "F2XM1", 0|(1<<MCID::UnmodeledSideEffects), 0x1e0000401ULL, NULL, NULL, 0 }, // Inst #696 = F2XM1 | |
| { 697, 2, 0, 0, 0, "FARCALL16i", 0|(1<<MCID::Call)|(1<<MCID::UnmodeledSideEffects), 0x13400c06cULL, ImplicitList6, ImplicitList13, OperandInfo46 }, // Inst #697 = FARCALL16i | |
| { 698, 5, 0, 0, 0, "FARCALL16m", 0|(1<<MCID::Call)|(1<<MCID::UnmodeledSideEffects), 0x1fe00005bULL, ImplicitList6, ImplicitList13, OperandInfo38 }, // Inst #698 = FARCALL16m | |
| { 699, 2, 0, 0, 0, "FARCALL32i", 0|(1<<MCID::Call)|(1<<MCID::UnmodeledSideEffects), 0x13401402cULL, ImplicitList6, ImplicitList13, OperandInfo46 }, // Inst #699 = FARCALL32i | |
| { 700, 5, 0, 0, 0, "FARCALL32m", 0|(1<<MCID::Call)|(1<<MCID::UnmodeledSideEffects), 0x1fe00001bULL, ImplicitList6, ImplicitList13, OperandInfo38 }, // Inst #700 = FARCALL32m | |
| { 701, 5, 0, 0, 0, "FARCALL64", 0|(1<<MCID::Call)|(1<<MCID::UnmodeledSideEffects), 0x1fe00201bULL, ImplicitList8, ImplicitList14, OperandInfo38 }, // Inst #701 = FARCALL64 | |
| { 702, 2, 0, 0, 0, "FARJMP16i", 0|(1<<MCID::Branch)|(1<<MCID::IndirectBranch)|(1<<MCID::Barrier)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0x1d400c06cULL, NULL, NULL, OperandInfo46 }, // Inst #702 = FARJMP16i | |
| { 703, 5, 0, 0, 0, "FARJMP16m", 0|(1<<MCID::Branch)|(1<<MCID::IndirectBranch)|(1<<MCID::Barrier)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0x1fe00005dULL, NULL, NULL, OperandInfo38 }, // Inst #703 = FARJMP16m | |
| { 704, 2, 0, 0, 0, "FARJMP32i", 0|(1<<MCID::Branch)|(1<<MCID::IndirectBranch)|(1<<MCID::Barrier)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0x1d401402cULL, NULL, NULL, OperandInfo46 }, // Inst #704 = FARJMP32i | |
| { 705, 5, 0, 0, 0, "FARJMP32m", 0|(1<<MCID::Branch)|(1<<MCID::IndirectBranch)|(1<<MCID::Barrier)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0x1fe00001dULL, NULL, NULL, OperandInfo38 }, // Inst #705 = FARJMP32m | |
| { 706, 5, 0, 0, 0, "FARJMP64", 0|(1<<MCID::Branch)|(1<<MCID::IndirectBranch)|(1<<MCID::Barrier)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0x1fe00201dULL, NULL, NULL, OperandInfo38 }, // Inst #706 = FARJMP64 | |
| { 707, 5, 0, 0, 0, "FBLDm", 0|(1<<MCID::UnmodeledSideEffects), 0x1be00001cULL, NULL, NULL, OperandInfo38 }, // Inst #707 = FBLDm | |
| { 708, 5, 1, 0, 0, "FBSTPm", 0|(1<<MCID::UnmodeledSideEffects), 0x1be00001eULL, NULL, NULL, OperandInfo38 }, // Inst #708 = FBSTPm | |
| { 709, 5, 0, 0, 0, "FCOM32m", 0|(1<<MCID::UnmodeledSideEffects), 0x1b000001aULL, NULL, NULL, OperandInfo38 }, // Inst #709 = FCOM32m | |
| { 710, 5, 0, 0, 0, "FCOM64m", 0|(1<<MCID::UnmodeledSideEffects), 0x1b800001aULL, NULL, NULL, OperandInfo38 }, // Inst #710 = FCOM64m | |
| { 711, 5, 0, 0, 0, "FCOMP32m", 0|(1<<MCID::UnmodeledSideEffects), 0x1b000001bULL, NULL, NULL, OperandInfo38 }, // Inst #711 = FCOMP32m | |
| { 712, 5, 0, 0, 0, "FCOMP64m", 0|(1<<MCID::UnmodeledSideEffects), 0x1b800001bULL, NULL, NULL, OperandInfo38 }, // Inst #712 = FCOMP64m | |
| { 713, 0, 0, 0, 0, "FCOMPP", 0|(1<<MCID::UnmodeledSideEffects), 0x1b2000901ULL, NULL, NULL, 0 }, // Inst #713 = FCOMPP | |
| { 714, 0, 0, 0, 0, "FDECSTP", 0|(1<<MCID::UnmodeledSideEffects), 0x1ec000401ULL, NULL, NULL, 0 }, // Inst #714 = FDECSTP | |
| { 715, 0, 0, 0, 0, "FEMMS", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1c000101ULL, NULL, NULL, 0 }, // Inst #715 = FEMMS | |
| { 716, 1, 0, 0, 0, "FFREE", 0|(1<<MCID::UnmodeledSideEffects), 0x180000802ULL, NULL, NULL, OperandInfo39 }, // Inst #716 = FFREE | |
| { 717, 5, 0, 0, 0, "FICOM16m", 0|(1<<MCID::UnmodeledSideEffects), 0x1bc00001aULL, NULL, NULL, OperandInfo38 }, // Inst #717 = FICOM16m | |
| { 718, 5, 0, 0, 0, "FICOM32m", 0|(1<<MCID::UnmodeledSideEffects), 0x1b400001aULL, NULL, NULL, OperandInfo38 }, // Inst #718 = FICOM32m | |
| { 719, 5, 0, 0, 0, "FICOMP16m", 0|(1<<MCID::UnmodeledSideEffects), 0x1bc00001bULL, NULL, NULL, OperandInfo38 }, // Inst #719 = FICOMP16m | |
| { 720, 5, 0, 0, 0, "FICOMP32m", 0|(1<<MCID::UnmodeledSideEffects), 0x1b400001bULL, NULL, NULL, OperandInfo38 }, // Inst #720 = FICOMP32m | |
| { 721, 0, 0, 0, 0, "FINCSTP", 0|(1<<MCID::UnmodeledSideEffects), 0x1ee000401ULL, NULL, NULL, 0 }, // Inst #721 = FINCSTP | |
| { 722, 5, 0, 0, 0, "FLDCW16m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b200001dULL, NULL, NULL, OperandInfo38 }, // Inst #722 = FLDCW16m | |
| { 723, 5, 0, 0, 0, "FLDENVm", 0|(1<<MCID::UnmodeledSideEffects), 0x1b200001cULL, NULL, NULL, OperandInfo38 }, // Inst #723 = FLDENVm | |
| { 724, 0, 0, 0, 0, "FLDL2E", 0|(1<<MCID::UnmodeledSideEffects), 0x1d4000401ULL, NULL, NULL, 0 }, // Inst #724 = FLDL2E | |
| { 725, 0, 0, 0, 0, "FLDL2T", 0|(1<<MCID::UnmodeledSideEffects), 0x1d2000401ULL, NULL, NULL, 0 }, // Inst #725 = FLDL2T | |
| { 726, 0, 0, 0, 0, "FLDLG2", 0|(1<<MCID::UnmodeledSideEffects), 0x1d8000401ULL, NULL, NULL, 0 }, // Inst #726 = FLDLG2 | |
| { 727, 0, 0, 0, 0, "FLDLN2", 0|(1<<MCID::UnmodeledSideEffects), 0x1da000401ULL, NULL, NULL, 0 }, // Inst #727 = FLDLN2 | |
| { 728, 0, 0, 0, 0, "FLDPI", 0|(1<<MCID::UnmodeledSideEffects), 0x1d6000401ULL, NULL, NULL, 0 }, // Inst #728 = FLDPI | |
| { 729, 0, 0, 0, 0, "FNCLEX", 0|(1<<MCID::UnmodeledSideEffects), 0x1c4000601ULL, NULL, NULL, 0 }, // Inst #729 = FNCLEX | |
| { 730, 0, 0, 0, 0, "FNINIT", 0|(1<<MCID::UnmodeledSideEffects), 0x1c6000601ULL, NULL, NULL, 0 }, // Inst #730 = FNINIT | |
| { 731, 0, 0, 0, 0, "FNOP", 0|(1<<MCID::UnmodeledSideEffects), 0x1a0000401ULL, NULL, NULL, 0 }, // Inst #731 = FNOP | |
| { 732, 5, 0, 0, 0, "FNSTCW16m", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1b200001fULL, NULL, NULL, OperandInfo38 }, // Inst #732 = FNSTCW16m | |
| { 733, 0, 0, 0, 0, "FNSTSW8r", 0|(1<<MCID::UnmodeledSideEffects), 0x1c0000a01ULL, NULL, ImplicitList2, 0 }, // Inst #733 = FNSTSW8r | |
| { 734, 5, 1, 0, 0, "FNSTSWm", 0|(1<<MCID::UnmodeledSideEffects), 0x1ba00001fULL, NULL, NULL, OperandInfo38 }, // Inst #734 = FNSTSWm | |
| { 735, 6, 0, 0, 0, "FP32_TO_INT16_IN_MEM", 0|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo117 }, // Inst #735 = FP32_TO_INT16_IN_MEM | |
| { 736, 6, 0, 0, 0, "FP32_TO_INT32_IN_MEM", 0|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo117 }, // Inst #736 = FP32_TO_INT32_IN_MEM | |
| { 737, 6, 0, 0, 0, "FP32_TO_INT64_IN_MEM", 0|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo117 }, // Inst #737 = FP32_TO_INT64_IN_MEM | |
| { 738, 6, 0, 0, 0, "FP64_TO_INT16_IN_MEM", 0|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo118 }, // Inst #738 = FP64_TO_INT16_IN_MEM | |
| { 739, 6, 0, 0, 0, "FP64_TO_INT32_IN_MEM", 0|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo118 }, // Inst #739 = FP64_TO_INT32_IN_MEM | |
| { 740, 6, 0, 0, 0, "FP64_TO_INT64_IN_MEM", 0|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo118 }, // Inst #740 = FP64_TO_INT64_IN_MEM | |
| { 741, 6, 0, 0, 0, "FP80_TO_INT16_IN_MEM", 0|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo119 }, // Inst #741 = FP80_TO_INT16_IN_MEM | |
| { 742, 6, 0, 0, 0, "FP80_TO_INT32_IN_MEM", 0|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo119 }, // Inst #742 = FP80_TO_INT32_IN_MEM | |
| { 743, 6, 0, 0, 0, "FP80_TO_INT64_IN_MEM", 0|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo119 }, // Inst #743 = FP80_TO_INT64_IN_MEM | |
| { 744, 0, 0, 0, 0, "FPATAN", 0|(1<<MCID::UnmodeledSideEffects), 0x1e6000401ULL, NULL, NULL, 0 }, // Inst #744 = FPATAN | |
| { 745, 0, 0, 0, 0, "FPREM", 0|(1<<MCID::UnmodeledSideEffects), 0x1f0000401ULL, NULL, NULL, 0 }, // Inst #745 = FPREM | |
| { 746, 0, 0, 0, 0, "FPREM1", 0|(1<<MCID::UnmodeledSideEffects), 0x1ea000401ULL, NULL, NULL, 0 }, // Inst #746 = FPREM1 | |
| { 747, 0, 0, 0, 0, "FPTAN", 0|(1<<MCID::UnmodeledSideEffects), 0x1e4000401ULL, NULL, NULL, 0 }, // Inst #747 = FPTAN | |
| { 748, 0, 0, 0, 0, "FRNDINT", 0|(1<<MCID::UnmodeledSideEffects), 0x1f8000401ULL, NULL, NULL, 0 }, // Inst #748 = FRNDINT | |
| { 749, 5, 1, 0, 0, "FRSTORm", 0|(1<<MCID::UnmodeledSideEffects), 0x1ba00001cULL, NULL, NULL, OperandInfo38 }, // Inst #749 = FRSTORm | |
| { 750, 5, 1, 0, 0, "FSAVEm", 0|(1<<MCID::UnmodeledSideEffects), 0x1ba00001eULL, NULL, NULL, OperandInfo38 }, // Inst #750 = FSAVEm | |
| { 751, 0, 0, 0, 0, "FSCALE", 0|(1<<MCID::UnmodeledSideEffects), 0x1fa000401ULL, NULL, NULL, 0 }, // Inst #751 = FSCALE | |
| { 752, 0, 0, 0, 0, "FSINCOS", 0|(1<<MCID::UnmodeledSideEffects), 0x1f6000401ULL, NULL, NULL, 0 }, // Inst #752 = FSINCOS | |
| { 753, 5, 1, 0, 0, "FSTENVm", 0|(1<<MCID::UnmodeledSideEffects), 0x1b200001eULL, NULL, NULL, OperandInfo38 }, // Inst #753 = FSTENVm | |
| { 754, 0, 0, 0, 0, "FS_PREFIX", 0|(1<<MCID::UnmodeledSideEffects), 0xc8000001ULL, NULL, NULL, 0 }, // Inst #754 = FS_PREFIX | |
| { 755, 0, 0, 0, 0, "FXAM", 0|(1<<MCID::UnmodeledSideEffects), 0x1ca000401ULL, NULL, NULL, 0 }, // Inst #755 = FXAM | |
| { 756, 5, 0, 0, 0, "FXRSTOR", 0|(1<<MCID::UnmodeledSideEffects), 0x15c000119ULL, NULL, NULL, OperandInfo38 }, // Inst #756 = FXRSTOR | |
| { 757, 5, 0, 0, 0, "FXRSTOR64", 0|(1<<MCID::UnmodeledSideEffects), 0x15c002119ULL, NULL, NULL, OperandInfo38 }, // Inst #757 = FXRSTOR64 | |
| { 758, 5, 1, 0, 0, "FXSAVE", 0|(1<<MCID::UnmodeledSideEffects), 0x15c000118ULL, NULL, NULL, OperandInfo38 }, // Inst #758 = FXSAVE | |
| { 759, 5, 1, 0, 0, "FXSAVE64", 0|(1<<MCID::UnmodeledSideEffects), 0x15c002118ULL, NULL, NULL, OperandInfo38 }, // Inst #759 = FXSAVE64 | |
| { 760, 0, 0, 0, 0, "FXTRACT", 0|(1<<MCID::UnmodeledSideEffects), 0x1e8000401ULL, NULL, NULL, 0 }, // Inst #760 = FXTRACT | |
| { 761, 0, 0, 0, 0, "FYL2X", 0|(1<<MCID::UnmodeledSideEffects), 0x1e2000401ULL, NULL, NULL, 0 }, // Inst #761 = FYL2X | |
| { 762, 0, 0, 0, 0, "FYL2XP1", 0|(1<<MCID::UnmodeledSideEffects), 0x1f2000401ULL, NULL, NULL, 0 }, // Inst #762 = FYL2XP1 | |
| { 763, 1, 1, 0, 0, "FpPOP_RETVAL", 0|(1<<MCID::UnmodeledSideEffects), 0xe0000ULL, NULL, NULL, OperandInfo120 }, // Inst #763 = FpPOP_RETVAL | |
| { 764, 7, 1, 0, 0, "FsANDNPDrm", 0|(1<<MCID::MayLoad), 0xab000146ULL, NULL, NULL, OperandInfo34 }, // Inst #764 = FsANDNPDrm | |
| { 765, 3, 1, 0, 0, "FsANDNPDrr", 0, 0xab000145ULL, NULL, NULL, OperandInfo35 }, // Inst #765 = FsANDNPDrr | |
| { 766, 7, 1, 0, 0, "FsANDNPSrm", 0|(1<<MCID::MayLoad), 0xaa800106ULL, NULL, NULL, OperandInfo36 }, // Inst #766 = FsANDNPSrm | |
| { 767, 3, 1, 0, 0, "FsANDNPSrr", 0, 0xaa800105ULL, NULL, NULL, OperandInfo37 }, // Inst #767 = FsANDNPSrr | |
| { 768, 7, 1, 0, 0, "FsANDPDrm", 0|(1<<MCID::MayLoad), 0xa9000146ULL, NULL, NULL, OperandInfo34 }, // Inst #768 = FsANDPDrm | |
| { 769, 3, 1, 0, 0, "FsANDPDrr", 0|(1<<MCID::Commutable), 0xa9000145ULL, NULL, NULL, OperandInfo35 }, // Inst #769 = FsANDPDrr | |
| { 770, 7, 1, 0, 0, "FsANDPSrm", 0|(1<<MCID::MayLoad), 0xa8800106ULL, NULL, NULL, OperandInfo36 }, // Inst #770 = FsANDPSrm | |
| { 771, 3, 1, 0, 0, "FsANDPSrr", 0|(1<<MCID::Commutable), 0xa8800105ULL, NULL, NULL, OperandInfo37 }, // Inst #771 = FsANDPSrr | |
| { 772, 1, 1, 0, 0, "FsFLD0SD", 0|(1<<MCID::Pseudo)|(1<<MCID::FoldableAsLoad)|(1<<MCID::Rematerializable)|(1<<MCID::CheapAsAMove), 0x0ULL, NULL, NULL, OperandInfo121 }, // Inst #772 = FsFLD0SD | |
| { 773, 1, 1, 0, 0, "FsFLD0SS", 0|(1<<MCID::Pseudo)|(1<<MCID::FoldableAsLoad)|(1<<MCID::Rematerializable)|(1<<MCID::CheapAsAMove), 0x0ULL, NULL, NULL, OperandInfo122 }, // Inst #773 = FsFLD0SS | |
| { 774, 6, 1, 0, 0, "FsMOVAPDrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x51000146ULL, NULL, NULL, OperandInfo101 }, // Inst #774 = FsMOVAPDrm | |
| { 775, 2, 1, 0, 0, "FsMOVAPDrr", 0, 0x51000145ULL, NULL, NULL, OperandInfo123 }, // Inst #775 = FsMOVAPDrr | |
| { 776, 6, 1, 0, 0, "FsMOVAPSrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x50800106ULL, NULL, NULL, OperandInfo99 }, // Inst #776 = FsMOVAPSrm | |
| { 777, 2, 1, 0, 0, "FsMOVAPSrr", 0, 0x50800105ULL, NULL, NULL, OperandInfo124 }, // Inst #777 = FsMOVAPSrr | |
| { 778, 7, 1, 0, 0, "FsORPDrm", 0|(1<<MCID::MayLoad), 0xad000146ULL, NULL, NULL, OperandInfo34 }, // Inst #778 = FsORPDrm | |
| { 779, 3, 1, 0, 0, "FsORPDrr", 0|(1<<MCID::Commutable), 0xad000145ULL, NULL, NULL, OperandInfo35 }, // Inst #779 = FsORPDrr | |
| { 780, 7, 1, 0, 0, "FsORPSrm", 0|(1<<MCID::MayLoad), 0xac800106ULL, NULL, NULL, OperandInfo36 }, // Inst #780 = FsORPSrm | |
| { 781, 3, 1, 0, 0, "FsORPSrr", 0|(1<<MCID::Commutable), 0xac800105ULL, NULL, NULL, OperandInfo37 }, // Inst #781 = FsORPSrr | |
| { 782, 6, 1, 0, 0, "FsVMOVAPDrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x251000146ULL, NULL, NULL, OperandInfo101 }, // Inst #782 = FsVMOVAPDrm | |
| { 783, 2, 1, 0, 0, "FsVMOVAPDrr", 0, 0x251000145ULL, NULL, NULL, OperandInfo123 }, // Inst #783 = FsVMOVAPDrr | |
| { 784, 6, 1, 0, 0, "FsVMOVAPSrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x250800106ULL, NULL, NULL, OperandInfo99 }, // Inst #784 = FsVMOVAPSrm | |
| { 785, 2, 1, 0, 0, "FsVMOVAPSrr", 0, 0x250800105ULL, NULL, NULL, OperandInfo124 }, // Inst #785 = FsVMOVAPSrr | |
| { 786, 7, 1, 0, 0, "FsXORPDrm", 0|(1<<MCID::MayLoad), 0xaf000146ULL, NULL, NULL, OperandInfo34 }, // Inst #786 = FsXORPDrm | |
| { 787, 3, 1, 0, 0, "FsXORPDrr", 0|(1<<MCID::Commutable), 0xaf000145ULL, NULL, NULL, OperandInfo35 }, // Inst #787 = FsXORPDrr | |
| { 788, 7, 1, 0, 0, "FsXORPSrm", 0|(1<<MCID::MayLoad), 0xae800106ULL, NULL, NULL, OperandInfo36 }, // Inst #788 = FsXORPSrm | |
| { 789, 3, 1, 0, 0, "FsXORPSrr", 0|(1<<MCID::Commutable), 0xae800105ULL, NULL, NULL, OperandInfo37 }, // Inst #789 = FsXORPSrr | |
| { 790, 0, 0, 0, 0, "GS_PREFIX", 0|(1<<MCID::UnmodeledSideEffects), 0xca000001ULL, NULL, NULL, 0 }, // Inst #790 = GS_PREFIX | |
| { 791, 7, 1, 0, 0, "HADDPDrm", 0|(1<<MCID::MayLoad), 0xf9000146ULL, NULL, NULL, OperandInfo32 }, // Inst #791 = HADDPDrm | |
| { 792, 3, 1, 0, 0, "HADDPDrr", 0, 0xf9000145ULL, NULL, NULL, OperandInfo33 }, // Inst #792 = HADDPDrr | |
| { 793, 7, 1, 0, 0, "HADDPSrm", 0|(1<<MCID::MayLoad), 0xf9000b06ULL, NULL, NULL, OperandInfo32 }, // Inst #793 = HADDPSrm | |
| { 794, 3, 1, 0, 0, "HADDPSrr", 0, 0xf9000b05ULL, NULL, NULL, OperandInfo33 }, // Inst #794 = HADDPSrr | |
| { 795, 0, 0, 0, 0, "HLT", 0|(1<<MCID::UnmodeledSideEffects), 0x1e8000001ULL, NULL, NULL, 0 }, // Inst #795 = HLT | |
| { 796, 7, 1, 0, 0, "HSUBPDrm", 0|(1<<MCID::MayLoad), 0xfb000146ULL, NULL, NULL, OperandInfo32 }, // Inst #796 = HSUBPDrm | |
| { 797, 3, 1, 0, 0, "HSUBPDrr", 0, 0xfb000145ULL, NULL, NULL, OperandInfo33 }, // Inst #797 = HSUBPDrr | |
| { 798, 7, 1, 0, 0, "HSUBPSrm", 0|(1<<MCID::MayLoad), 0xfb000b06ULL, NULL, NULL, OperandInfo32 }, // Inst #798 = HSUBPSrm | |
| { 799, 3, 1, 0, 0, "HSUBPSrr", 0, 0xfb000b05ULL, NULL, NULL, OperandInfo33 }, // Inst #799 = HSUBPSrr | |
| { 800, 5, 0, 0, 0, "IDIV16m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1ee00005fULL, ImplicitList20, ImplicitList21, OperandInfo38 }, // Inst #800 = IDIV16m | |
| { 801, 1, 0, 0, 0, "IDIV16r", 0|(1<<MCID::UnmodeledSideEffects), 0x1ee000057ULL, ImplicitList20, ImplicitList21, OperandInfo113 }, // Inst #801 = IDIV16r | |
| { 802, 5, 0, 0, 0, "IDIV32m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1ee00001fULL, ImplicitList15, ImplicitList18, OperandInfo38 }, // Inst #802 = IDIV32m | |
| { 803, 1, 0, 0, 0, "IDIV32r", 0|(1<<MCID::UnmodeledSideEffects), 0x1ee000017ULL, ImplicitList15, ImplicitList18, OperandInfo72 }, // Inst #803 = IDIV32r | |
| { 804, 5, 0, 0, 0, "IDIV64m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1ee00201fULL, ImplicitList19, ImplicitList17, OperandInfo38 }, // Inst #804 = IDIV64m | |
| { 805, 1, 0, 0, 0, "IDIV64r", 0|(1<<MCID::UnmodeledSideEffects), 0x1ee002017ULL, ImplicitList19, ImplicitList17, OperandInfo74 }, // Inst #805 = IDIV64r | |
| { 806, 5, 0, 0, 0, "IDIV8m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1ec00001fULL, ImplicitList2, ImplicitList22, OperandInfo38 }, // Inst #806 = IDIV8m | |
| { 807, 1, 0, 0, 0, "IDIV8r", 0|(1<<MCID::UnmodeledSideEffects), 0x1ec000017ULL, ImplicitList2, ImplicitList22, OperandInfo114 }, // Inst #807 = IDIV8r | |
| { 808, 5, 0, 0, 0, "ILD_F16m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1be000018ULL, NULL, NULL, OperandInfo38 }, // Inst #808 = ILD_F16m | |
| { 809, 5, 0, 0, 0, "ILD_F32m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b6000018ULL, NULL, NULL, OperandInfo38 }, // Inst #809 = ILD_F32m | |
| { 810, 5, 0, 0, 0, "ILD_F64m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1be00001dULL, NULL, NULL, OperandInfo38 }, // Inst #810 = ILD_F64m | |
| { 811, 6, 1, 0, 0, "ILD_Fp16m32", 0|(1<<MCID::MayLoad), 0x20000ULL, NULL, NULL, OperandInfo125 }, // Inst #811 = ILD_Fp16m32 | |
| { 812, 6, 1, 0, 0, "ILD_Fp16m64", 0|(1<<MCID::MayLoad), 0x20000ULL, NULL, NULL, OperandInfo126 }, // Inst #812 = ILD_Fp16m64 | |
| { 813, 6, 1, 0, 0, "ILD_Fp16m80", 0|(1<<MCID::MayLoad), 0x20000ULL, NULL, NULL, OperandInfo127 }, // Inst #813 = ILD_Fp16m80 | |
| { 814, 6, 1, 0, 0, "ILD_Fp32m32", 0|(1<<MCID::MayLoad), 0x20000ULL, NULL, NULL, OperandInfo125 }, // Inst #814 = ILD_Fp32m32 | |
| { 815, 6, 1, 0, 0, "ILD_Fp32m64", 0|(1<<MCID::MayLoad), 0x20000ULL, NULL, NULL, OperandInfo126 }, // Inst #815 = ILD_Fp32m64 | |
| { 816, 6, 1, 0, 0, "ILD_Fp32m80", 0|(1<<MCID::MayLoad), 0x20000ULL, NULL, NULL, OperandInfo127 }, // Inst #816 = ILD_Fp32m80 | |
| { 817, 6, 1, 0, 0, "ILD_Fp64m32", 0|(1<<MCID::MayLoad), 0x20000ULL, NULL, NULL, OperandInfo125 }, // Inst #817 = ILD_Fp64m32 | |
| { 818, 6, 1, 0, 0, "ILD_Fp64m64", 0|(1<<MCID::MayLoad), 0x20000ULL, NULL, NULL, OperandInfo126 }, // Inst #818 = ILD_Fp64m64 | |
| { 819, 6, 1, 0, 0, "ILD_Fp64m80", 0|(1<<MCID::MayLoad), 0x20000ULL, NULL, NULL, OperandInfo127 }, // Inst #819 = ILD_Fp64m80 | |
| { 820, 5, 0, 0, 0, "IMUL16m", 0|(1<<MCID::MayLoad), 0x1ee00005dULL, ImplicitList2, ImplicitList21, OperandInfo38 }, // Inst #820 = IMUL16m | |
| { 821, 1, 0, 0, 0, "IMUL16r", 0, 0x1ee000055ULL, ImplicitList2, ImplicitList21, OperandInfo113 }, // Inst #821 = IMUL16r | |
| { 822, 7, 1, 0, 0, "IMUL16rm", 0|(1<<MCID::MayLoad), 0x15e000146ULL, NULL, ImplicitList1, OperandInfo18 }, // Inst #822 = IMUL16rm | |
| { 823, 7, 1, 0, 0, "IMUL16rmi", 0|(1<<MCID::MayLoad), 0xd200c046ULL, NULL, ImplicitList1, OperandInfo128 }, // Inst #823 = IMUL16rmi | |
| { 824, 7, 1, 0, 0, "IMUL16rmi8", 0|(1<<MCID::MayLoad), 0xd6004046ULL, NULL, ImplicitList1, OperandInfo128 }, // Inst #824 = IMUL16rmi8 | |
| { 825, 3, 1, 0, 0, "IMUL16rr", 0|(1<<MCID::Commutable), 0x15e000145ULL, NULL, ImplicitList1, OperandInfo19 }, // Inst #825 = IMUL16rr | |
| { 826, 3, 1, 0, 0, "IMUL16rri", 0, 0xd200c045ULL, NULL, ImplicitList1, OperandInfo129 }, // Inst #826 = IMUL16rri | |
| { 827, 3, 1, 0, 0, "IMUL16rri8", 0, 0xd6004045ULL, NULL, ImplicitList1, OperandInfo129 }, // Inst #827 = IMUL16rri8 | |
| { 828, 5, 0, 0, 0, "IMUL32m", 0|(1<<MCID::MayLoad), 0x1ee00001dULL, ImplicitList3, ImplicitList18, OperandInfo38 }, // Inst #828 = IMUL32m | |
| { 829, 1, 0, 0, 0, "IMUL32r", 0, 0x1ee000015ULL, ImplicitList3, ImplicitList18, OperandInfo72 }, // Inst #829 = IMUL32r | |
| { 830, 7, 1, 0, 0, "IMUL32rm", 0|(1<<MCID::MayLoad), 0x15e000106ULL, NULL, ImplicitList1, OperandInfo22 }, // Inst #830 = IMUL32rm | |
| { 831, 7, 1, 0, 0, "IMUL32rmi", 0|(1<<MCID::MayLoad), 0xd2014006ULL, NULL, ImplicitList1, OperandInfo130 }, // Inst #831 = IMUL32rmi | |
| { 832, 7, 1, 0, 0, "IMUL32rmi8", 0|(1<<MCID::MayLoad), 0xd6004006ULL, NULL, ImplicitList1, OperandInfo130 }, // Inst #832 = IMUL32rmi8 | |
| { 833, 3, 1, 0, 0, "IMUL32rr", 0|(1<<MCID::Commutable), 0x15e000105ULL, NULL, ImplicitList1, OperandInfo23 }, // Inst #833 = IMUL32rr | |
| { 834, 3, 1, 0, 0, "IMUL32rri", 0, 0xd2014005ULL, NULL, ImplicitList1, OperandInfo131 }, // Inst #834 = IMUL32rri | |
| { 835, 3, 1, 0, 0, "IMUL32rri8", 0, 0xd6004005ULL, NULL, ImplicitList1, OperandInfo131 }, // Inst #835 = IMUL32rri8 | |
| { 836, 5, 0, 0, 0, "IMUL64m", 0|(1<<MCID::MayLoad), 0x1ee00201dULL, ImplicitList4, ImplicitList17, OperandInfo38 }, // Inst #836 = IMUL64m | |
| { 837, 1, 0, 0, 0, "IMUL64r", 0, 0x1ee002015ULL, ImplicitList4, ImplicitList17, OperandInfo74 }, // Inst #837 = IMUL64r | |
| { 838, 7, 1, 0, 0, "IMUL64rm", 0|(1<<MCID::MayLoad), 0x15e002106ULL, NULL, ImplicitList1, OperandInfo26 }, // Inst #838 = IMUL64rm | |
| { 839, 7, 1, 0, 0, "IMUL64rmi32", 0|(1<<MCID::MayLoad), 0xd2016006ULL, NULL, ImplicitList1, OperandInfo132 }, // Inst #839 = IMUL64rmi32 | |
| { 840, 7, 1, 0, 0, "IMUL64rmi8", 0|(1<<MCID::MayLoad), 0xd6006006ULL, NULL, ImplicitList1, OperandInfo132 }, // Inst #840 = IMUL64rmi8 | |
| { 841, 3, 1, 0, 0, "IMUL64rr", 0|(1<<MCID::Commutable), 0x15e002105ULL, NULL, ImplicitList1, OperandInfo27 }, // Inst #841 = IMUL64rr | |
| { 842, 3, 1, 0, 0, "IMUL64rri32", 0, 0xd2016005ULL, NULL, ImplicitList1, OperandInfo133 }, // Inst #842 = IMUL64rri32 | |
| { 843, 3, 1, 0, 0, "IMUL64rri8", 0, 0xd6006005ULL, NULL, ImplicitList1, OperandInfo133 }, // Inst #843 = IMUL64rri8 | |
| { 844, 5, 0, 0, 0, "IMUL8m", 0|(1<<MCID::MayLoad), 0x1ec00001dULL, ImplicitList5, ImplicitList22, OperandInfo38 }, // Inst #844 = IMUL8m | |
| { 845, 1, 0, 0, 0, "IMUL8r", 0, 0x1ec000015ULL, ImplicitList5, ImplicitList22, OperandInfo114 }, // Inst #845 = IMUL8r | |
| { 846, 0, 0, 0, 0, "IN16", 0|(1<<MCID::UnmodeledSideEffects), 0xda000041ULL, NULL, NULL, 0 }, // Inst #846 = IN16 | |
| { 847, 1, 0, 0, 0, "IN16ri", 0|(1<<MCID::UnmodeledSideEffects), 0x1ca004041ULL, NULL, ImplicitList2, OperandInfo2 }, // Inst #847 = IN16ri | |
| { 848, 0, 0, 0, 0, "IN16rr", 0|(1<<MCID::UnmodeledSideEffects), 0x1da000041ULL, ImplicitList23, ImplicitList2, 0 }, // Inst #848 = IN16rr | |
| { 849, 0, 0, 0, 0, "IN32", 0|(1<<MCID::UnmodeledSideEffects), 0xda000001ULL, NULL, NULL, 0 }, // Inst #849 = IN32 | |
| { 850, 1, 0, 0, 0, "IN32ri", 0|(1<<MCID::UnmodeledSideEffects), 0x1ca004001ULL, NULL, ImplicitList3, OperandInfo2 }, // Inst #850 = IN32ri | |
| { 851, 0, 0, 0, 0, "IN32rr", 0|(1<<MCID::UnmodeledSideEffects), 0x1da000001ULL, ImplicitList23, ImplicitList3, 0 }, // Inst #851 = IN32rr | |
| { 852, 0, 0, 0, 0, "IN8", 0|(1<<MCID::UnmodeledSideEffects), 0xd8000001ULL, NULL, NULL, 0 }, // Inst #852 = IN8 | |
| { 853, 1, 0, 0, 0, "IN8ri", 0|(1<<MCID::UnmodeledSideEffects), 0x1c8004001ULL, NULL, ImplicitList5, OperandInfo2 }, // Inst #853 = IN8ri | |
| { 854, 0, 0, 0, 0, "IN8rr", 0|(1<<MCID::UnmodeledSideEffects), 0x1d8000001ULL, ImplicitList23, ImplicitList5, 0 }, // Inst #854 = IN8rr | |
| { 855, 5, 0, 0, 0, "INC16m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1fe000058ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #855 = INC16m | |
| { 856, 2, 1, 0, 0, "INC16r", 0|(1<<MCID::ConvertibleTo3Addr), 0x80000042ULL, NULL, ImplicitList1, OperandInfo111 }, // Inst #856 = INC16r | |
| { 857, 5, 0, 0, 0, "INC32m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1fe000018ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #857 = INC32m | |
| { 858, 2, 1, 0, 0, "INC32r", 0|(1<<MCID::ConvertibleTo3Addr), 0x80000002ULL, NULL, ImplicitList1, OperandInfo67 }, // Inst #858 = INC32r | |
| { 859, 5, 0, 0, 0, "INC64_16m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1fe000058ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #859 = INC64_16m | |
| { 860, 2, 1, 0, 0, "INC64_16r", 0|(1<<MCID::ConvertibleTo3Addr), 0x1fe000050ULL, NULL, ImplicitList1, OperandInfo111 }, // Inst #860 = INC64_16r | |
| { 861, 5, 0, 0, 0, "INC64_32m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1fe000018ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #861 = INC64_32m | |
| { 862, 2, 1, 0, 0, "INC64_32r", 0|(1<<MCID::ConvertibleTo3Addr), 0x1fe000010ULL, NULL, ImplicitList1, OperandInfo67 }, // Inst #862 = INC64_32r | |
| { 863, 5, 0, 0, 0, "INC64m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1fe002018ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #863 = INC64m | |
| { 864, 2, 1, 0, 0, "INC64r", 0|(1<<MCID::ConvertibleTo3Addr), 0x1fe002010ULL, NULL, ImplicitList1, OperandInfo68 }, // Inst #864 = INC64r | |
| { 865, 5, 0, 0, 0, "INC8m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1fc000018ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #865 = INC8m | |
| { 866, 2, 1, 0, 0, "INC8r", 0, 0x1fc000010ULL, NULL, ImplicitList1, OperandInfo112 }, // Inst #866 = INC8r | |
| { 867, 8, 1, 0, 0, "INSERTPSrm", 0|(1<<MCID::MayLoad), 0x43804e46ULL, NULL, NULL, OperandInfo63 }, // Inst #867 = INSERTPSrm | |
| { 868, 4, 1, 0, 0, "INSERTPSrr", 0, 0x43804e45ULL, NULL, NULL, OperandInfo64 }, // Inst #868 = INSERTPSrr | |
| { 869, 1, 0, 0, 0, "INT", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x19a004001ULL, NULL, NULL, OperandInfo2 }, // Inst #869 = INT | |
| { 870, 0, 0, 0, 0, "INT3", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x198000001ULL, NULL, NULL, 0 }, // Inst #870 = INT3 | |
| { 871, 0, 0, 0, 0, "INTO", 0|(1<<MCID::UnmodeledSideEffects), 0x19c000001ULL, ImplicitList1, NULL, 0 }, // Inst #871 = INTO | |
| { 872, 0, 0, 0, 0, "INVD", 0|(1<<MCID::UnmodeledSideEffects), 0x10000101ULL, NULL, NULL, 0 }, // Inst #872 = INVD | |
| { 873, 6, 0, 0, 0, "INVEPT32", 0|(1<<MCID::UnmodeledSideEffects), 0x100000d46ULL, NULL, NULL, OperandInfo12 }, // Inst #873 = INVEPT32 | |
| { 874, 6, 0, 0, 0, "INVEPT64", 0|(1<<MCID::UnmodeledSideEffects), 0x100000d46ULL, NULL, NULL, OperandInfo13 }, // Inst #874 = INVEPT64 | |
| { 875, 5, 0, 0, 0, "INVLPG", 0|(1<<MCID::UnmodeledSideEffects), 0x200011fULL, NULL, NULL, OperandInfo38 }, // Inst #875 = INVLPG | |
| { 876, 6, 0, 0, 0, "INVVPID32", 0|(1<<MCID::UnmodeledSideEffects), 0x102000d46ULL, NULL, NULL, OperandInfo12 }, // Inst #876 = INVVPID32 | |
| { 877, 6, 0, 0, 0, "INVVPID64", 0|(1<<MCID::UnmodeledSideEffects), 0x102000d46ULL, NULL, NULL, OperandInfo13 }, // Inst #877 = INVVPID64 | |
| { 878, 0, 0, 0, 0, "IRET16", 0|(1<<MCID::UnmodeledSideEffects), 0x19e000041ULL, NULL, NULL, 0 }, // Inst #878 = IRET16 | |
| { 879, 0, 0, 0, 0, "IRET32", 0|(1<<MCID::UnmodeledSideEffects), 0x19e000001ULL, NULL, NULL, 0 }, // Inst #879 = IRET32 | |
| { 880, 0, 0, 0, 0, "IRET64", 0|(1<<MCID::UnmodeledSideEffects), 0x19e002001ULL, NULL, NULL, 0 }, // Inst #880 = IRET64 | |
| { 881, 5, 0, 0, 0, "ISTT_FP16m", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1be000019ULL, NULL, NULL, OperandInfo38 }, // Inst #881 = ISTT_FP16m | |
| { 882, 5, 0, 0, 0, "ISTT_FP32m", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1b6000019ULL, NULL, NULL, OperandInfo38 }, // Inst #882 = ISTT_FP32m | |
| { 883, 5, 0, 0, 0, "ISTT_FP64m", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1ba000019ULL, NULL, NULL, OperandInfo38 }, // Inst #883 = ISTT_FP64m | |
| { 884, 6, 0, 0, 0, "ISTT_Fp16m32", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo117 }, // Inst #884 = ISTT_Fp16m32 | |
| { 885, 6, 0, 0, 0, "ISTT_Fp16m64", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo118 }, // Inst #885 = ISTT_Fp16m64 | |
| { 886, 6, 0, 0, 0, "ISTT_Fp16m80", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo119 }, // Inst #886 = ISTT_Fp16m80 | |
| { 887, 6, 0, 0, 0, "ISTT_Fp32m32", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo117 }, // Inst #887 = ISTT_Fp32m32 | |
| { 888, 6, 0, 0, 0, "ISTT_Fp32m64", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo118 }, // Inst #888 = ISTT_Fp32m64 | |
| { 889, 6, 0, 0, 0, "ISTT_Fp32m80", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo119 }, // Inst #889 = ISTT_Fp32m80 | |
| { 890, 6, 0, 0, 0, "ISTT_Fp64m32", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo117 }, // Inst #890 = ISTT_Fp64m32 | |
| { 891, 6, 0, 0, 0, "ISTT_Fp64m64", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo118 }, // Inst #891 = ISTT_Fp64m64 | |
| { 892, 6, 0, 0, 0, "ISTT_Fp64m80", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo119 }, // Inst #892 = ISTT_Fp64m80 | |
| { 893, 5, 0, 0, 0, "IST_F16m", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1be00001aULL, NULL, NULL, OperandInfo38 }, // Inst #893 = IST_F16m | |
| { 894, 5, 0, 0, 0, "IST_F32m", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1b600001aULL, NULL, NULL, OperandInfo38 }, // Inst #894 = IST_F32m | |
| { 895, 5, 0, 0, 0, "IST_FP16m", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1be00001bULL, NULL, NULL, OperandInfo38 }, // Inst #895 = IST_FP16m | |
| { 896, 5, 0, 0, 0, "IST_FP32m", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1b600001bULL, NULL, NULL, OperandInfo38 }, // Inst #896 = IST_FP32m | |
| { 897, 5, 0, 0, 0, "IST_FP64m", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1be00001fULL, NULL, NULL, OperandInfo38 }, // Inst #897 = IST_FP64m | |
| { 898, 6, 0, 0, 0, "IST_Fp16m32", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo117 }, // Inst #898 = IST_Fp16m32 | |
| { 899, 6, 0, 0, 0, "IST_Fp16m64", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo118 }, // Inst #899 = IST_Fp16m64 | |
| { 900, 6, 0, 0, 0, "IST_Fp16m80", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo119 }, // Inst #900 = IST_Fp16m80 | |
| { 901, 6, 0, 0, 0, "IST_Fp32m32", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo117 }, // Inst #901 = IST_Fp32m32 | |
| { 902, 6, 0, 0, 0, "IST_Fp32m64", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo118 }, // Inst #902 = IST_Fp32m64 | |
| { 903, 6, 0, 0, 0, "IST_Fp32m80", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo119 }, // Inst #903 = IST_Fp32m80 | |
| { 904, 6, 0, 0, 0, "IST_Fp64m32", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo117 }, // Inst #904 = IST_Fp64m32 | |
| { 905, 6, 0, 0, 0, "IST_Fp64m64", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo118 }, // Inst #905 = IST_Fp64m64 | |
| { 906, 6, 0, 0, 0, "IST_Fp64m80", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo119 }, // Inst #906 = IST_Fp64m80 | |
| { 907, 8, 1, 0, 0, "Int_CMPSDrm", 0|(1<<MCID::MayLoad), 0x184004b06ULL, NULL, NULL, OperandInfo63 }, // Inst #907 = Int_CMPSDrm | |
| { 908, 4, 1, 0, 0, "Int_CMPSDrr", 0, 0x184004b05ULL, NULL, NULL, OperandInfo64 }, // Inst #908 = Int_CMPSDrr | |
| { 909, 8, 1, 0, 0, "Int_CMPSSrm", 0|(1<<MCID::MayLoad), 0x184004c06ULL, NULL, NULL, OperandInfo63 }, // Inst #909 = Int_CMPSSrm | |
| { 910, 4, 1, 0, 0, "Int_CMPSSrr", 0, 0x184004c05ULL, NULL, NULL, OperandInfo64 }, // Inst #910 = Int_CMPSSrr | |
| { 911, 6, 0, 0, 0, "Int_COMISDrm", 0|(1<<MCID::MayLoad), 0x5f000146ULL, NULL, ImplicitList1, OperandInfo47 }, // Inst #911 = Int_COMISDrm | |
| { 912, 2, 0, 0, 0, "Int_COMISDrr", 0, 0x5f000145ULL, NULL, ImplicitList1, OperandInfo48 }, // Inst #912 = Int_COMISDrr | |
| { 913, 6, 0, 0, 0, "Int_COMISSrm", 0|(1<<MCID::MayLoad), 0x5e800106ULL, NULL, ImplicitList1, OperandInfo47 }, // Inst #913 = Int_COMISSrm | |
| { 914, 2, 0, 0, 0, "Int_COMISSrr", 0, 0x5e800105ULL, NULL, ImplicitList1, OperandInfo48 }, // Inst #914 = Int_COMISSrr | |
| { 915, 6, 1, 0, 0, "Int_CVTDQ2PDrm", 0|(1<<MCID::MayLoad), 0x1cc000c06ULL, NULL, NULL, OperandInfo47 }, // Inst #915 = Int_CVTDQ2PDrm | |
| { 916, 2, 1, 0, 0, "Int_CVTDQ2PDrr", 0, 0x1cc000c05ULL, NULL, NULL, OperandInfo48 }, // Inst #916 = Int_CVTDQ2PDrr | |
| { 917, 6, 1, 0, 0, "Int_CVTDQ2PSrm", 0|(1<<MCID::MayLoad), 0xb6000106ULL, NULL, NULL, OperandInfo47 }, // Inst #917 = Int_CVTDQ2PSrm | |
| { 918, 2, 1, 0, 0, "Int_CVTDQ2PSrr", 0, 0xb6000105ULL, NULL, NULL, OperandInfo48 }, // Inst #918 = Int_CVTDQ2PSrr | |
| { 919, 6, 1, 0, 0, "Int_CVTPD2DQrm", 0|(1<<MCID::MayLoad), 0x1cc000b06ULL, NULL, NULL, OperandInfo47 }, // Inst #919 = Int_CVTPD2DQrm | |
| { 920, 2, 1, 0, 0, "Int_CVTPD2DQrr", 0, 0x1cc000b05ULL, NULL, NULL, OperandInfo48 }, // Inst #920 = Int_CVTPD2DQrr | |
| { 921, 6, 1, 0, 0, "Int_CVTPD2PSrm", 0|(1<<MCID::MayLoad), 0xb5000146ULL, NULL, NULL, OperandInfo47 }, // Inst #921 = Int_CVTPD2PSrm | |
| { 922, 2, 1, 0, 0, "Int_CVTPD2PSrr", 0, 0xb5000145ULL, NULL, NULL, OperandInfo48 }, // Inst #922 = Int_CVTPD2PSrr | |
| { 923, 6, 1, 0, 0, "Int_CVTPS2DQrm", 0|(1<<MCID::MayLoad), 0xb7000146ULL, NULL, NULL, OperandInfo47 }, // Inst #923 = Int_CVTPS2DQrm | |
| { 924, 2, 1, 0, 0, "Int_CVTPS2DQrr", 0, 0xb7000145ULL, NULL, NULL, OperandInfo48 }, // Inst #924 = Int_CVTPS2DQrr | |
| { 925, 6, 1, 0, 0, "Int_CVTPS2PDrm", 0|(1<<MCID::MayLoad), 0xb4000106ULL, NULL, NULL, OperandInfo47 }, // Inst #925 = Int_CVTPS2PDrm | |
| { 926, 2, 1, 0, 0, "Int_CVTPS2PDrr", 0, 0xb4000105ULL, NULL, NULL, OperandInfo48 }, // Inst #926 = Int_CVTPS2PDrr | |
| { 927, 7, 1, 0, 0, "Int_CVTSD2SSrm", 0|(1<<MCID::MayLoad), 0xb4000c06ULL, NULL, NULL, OperandInfo32 }, // Inst #927 = Int_CVTSD2SSrm | |
| { 928, 3, 1, 0, 0, "Int_CVTSD2SSrr", 0, 0xb4000c05ULL, NULL, NULL, OperandInfo33 }, // Inst #928 = Int_CVTSD2SSrr | |
| { 929, 7, 1, 0, 0, "Int_CVTSI2SD64rm", 0|(1<<MCID::MayLoad), 0x54002b06ULL, NULL, NULL, OperandInfo32 }, // Inst #929 = Int_CVTSI2SD64rm | |
| { 930, 3, 1, 0, 0, "Int_CVTSI2SD64rr", 0, 0x54002b05ULL, NULL, NULL, OperandInfo134 }, // Inst #930 = Int_CVTSI2SD64rr | |
| { 931, 7, 1, 0, 0, "Int_CVTSI2SDrm", 0|(1<<MCID::MayLoad), 0x54000b06ULL, NULL, NULL, OperandInfo32 }, // Inst #931 = Int_CVTSI2SDrm | |
| { 932, 3, 1, 0, 0, "Int_CVTSI2SDrr", 0, 0x54000b05ULL, NULL, NULL, OperandInfo135 }, // Inst #932 = Int_CVTSI2SDrr | |
| { 933, 7, 1, 0, 0, "Int_CVTSI2SS64rm", 0|(1<<MCID::MayLoad), 0x54002c06ULL, NULL, NULL, OperandInfo32 }, // Inst #933 = Int_CVTSI2SS64rm | |
| { 934, 3, 1, 0, 0, "Int_CVTSI2SS64rr", 0, 0x54002c05ULL, NULL, NULL, OperandInfo134 }, // Inst #934 = Int_CVTSI2SS64rr | |
| { 935, 7, 1, 0, 0, "Int_CVTSI2SSrm", 0|(1<<MCID::MayLoad), 0x54000c06ULL, NULL, NULL, OperandInfo32 }, // Inst #935 = Int_CVTSI2SSrm | |
| { 936, 3, 1, 0, 0, "Int_CVTSI2SSrr", 0, 0x54000c05ULL, NULL, NULL, OperandInfo135 }, // Inst #936 = Int_CVTSI2SSrr | |
| { 937, 7, 1, 0, 0, "Int_CVTSS2SDrm", 0|(1<<MCID::MayLoad), 0xb4000c06ULL, NULL, NULL, OperandInfo32 }, // Inst #937 = Int_CVTSS2SDrm | |
| { 938, 3, 1, 0, 0, "Int_CVTSS2SDrr", 0, 0xb4000c05ULL, NULL, NULL, OperandInfo33 }, // Inst #938 = Int_CVTSS2SDrr | |
| { 939, 6, 1, 0, 0, "Int_CVTTSD2SI64rm", 0|(1<<MCID::MayLoad), 0x58002b06ULL, NULL, NULL, OperandInfo13 }, // Inst #939 = Int_CVTTSD2SI64rm | |
| { 940, 2, 1, 0, 0, "Int_CVTTSD2SI64rr", 0, 0x58002b05ULL, NULL, NULL, OperandInfo97 }, // Inst #940 = Int_CVTTSD2SI64rr | |
| { 941, 6, 1, 0, 0, "Int_CVTTSD2SIrm", 0|(1<<MCID::MayLoad), 0x58000b06ULL, NULL, NULL, OperandInfo12 }, // Inst #941 = Int_CVTTSD2SIrm | |
| { 942, 2, 1, 0, 0, "Int_CVTTSD2SIrr", 0, 0x58000b05ULL, NULL, NULL, OperandInfo98 }, // Inst #942 = Int_CVTTSD2SIrr | |
| { 943, 6, 1, 0, 0, "Int_CVTTSS2SI64rm", 0|(1<<MCID::MayLoad), 0x58002c06ULL, NULL, NULL, OperandInfo13 }, // Inst #943 = Int_CVTTSS2SI64rm | |
| { 944, 2, 1, 0, 0, "Int_CVTTSS2SI64rr", 0, 0x58002c05ULL, NULL, NULL, OperandInfo97 }, // Inst #944 = Int_CVTTSS2SI64rr | |
| { 945, 6, 1, 0, 0, "Int_CVTTSS2SIrm", 0|(1<<MCID::MayLoad), 0x58000c06ULL, NULL, NULL, OperandInfo12 }, // Inst #945 = Int_CVTTSS2SIrm | |
| { 946, 2, 1, 0, 0, "Int_CVTTSS2SIrr", 0, 0x58000c05ULL, NULL, NULL, OperandInfo98 }, // Inst #946 = Int_CVTTSS2SIrr | |
| { 947, 0, 0, 0, 0, "Int_MemBarrier", 0|(1<<MCID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, 0 }, // Inst #947 = Int_MemBarrier | |
| { 948, 1, 0, 0, 0, "Int_MemBarrierNoSSE64", 0|(1<<MCID::UnmodeledSideEffects), 0x12102011ULL, NULL, ImplicitList6, OperandInfo74 }, // Inst #948 = Int_MemBarrierNoSSE64 | |
| { 949, 6, 0, 0, 0, "Int_UCOMISDrm", 0|(1<<MCID::MayLoad), 0x5d000146ULL, NULL, ImplicitList1, OperandInfo47 }, // Inst #949 = Int_UCOMISDrm | |
| { 950, 2, 0, 0, 0, "Int_UCOMISDrr", 0, 0x5d000145ULL, NULL, ImplicitList1, OperandInfo48 }, // Inst #950 = Int_UCOMISDrr | |
| { 951, 6, 0, 0, 0, "Int_UCOMISSrm", 0|(1<<MCID::MayLoad), 0x5c800106ULL, NULL, ImplicitList1, OperandInfo47 }, // Inst #951 = Int_UCOMISSrm | |
| { 952, 2, 0, 0, 0, "Int_UCOMISSrr", 0, 0x5c800105ULL, NULL, ImplicitList1, OperandInfo48 }, // Inst #952 = Int_UCOMISSrr | |
| { 953, 8, 1, 0, 0, "Int_VCMPSDrm", 0|(1<<MCID::MayLoad), 0xb84004b06ULL, NULL, NULL, OperandInfo136 }, // Inst #953 = Int_VCMPSDrm | |
| { 954, 4, 1, 0, 0, "Int_VCMPSDrr", 0, 0xb84004b05ULL, NULL, NULL, OperandInfo86 }, // Inst #954 = Int_VCMPSDrr | |
| { 955, 8, 1, 0, 0, "Int_VCMPSSrm", 0|(1<<MCID::MayLoad), 0xb84004c06ULL, NULL, NULL, OperandInfo136 }, // Inst #955 = Int_VCMPSSrm | |
| { 956, 4, 1, 0, 0, "Int_VCMPSSrr", 0, 0xb84004c05ULL, NULL, NULL, OperandInfo86 }, // Inst #956 = Int_VCMPSSrr | |
| { 957, 6, 0, 0, 0, "Int_VCOMISDrm", 0|(1<<MCID::MayLoad), 0x25f000146ULL, NULL, ImplicitList1, OperandInfo47 }, // Inst #957 = Int_VCOMISDrm | |
| { 958, 2, 0, 0, 0, "Int_VCOMISDrr", 0, 0x25f000145ULL, NULL, ImplicitList1, OperandInfo48 }, // Inst #958 = Int_VCOMISDrr | |
| { 959, 6, 0, 0, 0, "Int_VCOMISSrm", 0|(1<<MCID::MayLoad), 0x25e800106ULL, NULL, ImplicitList1, OperandInfo47 }, // Inst #959 = Int_VCOMISSrm | |
| { 960, 2, 0, 0, 0, "Int_VCOMISSrr", 0, 0x25e800105ULL, NULL, ImplicitList1, OperandInfo48 }, // Inst #960 = Int_VCOMISSrr | |
| { 961, 6, 1, 0, 0, "Int_VCVTDQ2PDrm", 0|(1<<MCID::MayLoad), 0x3cc000c06ULL, NULL, NULL, OperandInfo47 }, // Inst #961 = Int_VCVTDQ2PDrm | |
| { 962, 2, 1, 0, 0, "Int_VCVTDQ2PDrr", 0, 0x3cc000c05ULL, NULL, NULL, OperandInfo48 }, // Inst #962 = Int_VCVTDQ2PDrr | |
| { 963, 6, 1, 0, 0, "Int_VCVTDQ2PSrm", 0|(1<<MCID::MayLoad), 0x2b6000106ULL, NULL, NULL, OperandInfo47 }, // Inst #963 = Int_VCVTDQ2PSrm | |
| { 964, 2, 1, 0, 0, "Int_VCVTDQ2PSrr", 0, 0x2b6000105ULL, NULL, NULL, OperandInfo48 }, // Inst #964 = Int_VCVTDQ2PSrr | |
| { 965, 6, 1, 0, 0, "Int_VCVTPD2DQrm", 0|(1<<MCID::MayLoad), 0x3cc000b06ULL, NULL, NULL, OperandInfo47 }, // Inst #965 = Int_VCVTPD2DQrm | |
| { 966, 2, 1, 0, 0, "Int_VCVTPD2DQrr", 0, 0x3cc000b05ULL, NULL, NULL, OperandInfo48 }, // Inst #966 = Int_VCVTPD2DQrr | |
| { 967, 6, 1, 0, 0, "Int_VCVTPD2PSrm", 0|(1<<MCID::MayLoad), 0xb5000146ULL, NULL, NULL, OperandInfo47 }, // Inst #967 = Int_VCVTPD2PSrm | |
| { 968, 2, 1, 0, 0, "Int_VCVTPD2PSrr", 0, 0xb5000145ULL, NULL, NULL, OperandInfo48 }, // Inst #968 = Int_VCVTPD2PSrr | |
| { 969, 6, 1, 0, 0, "Int_VCVTPS2DQrm", 0|(1<<MCID::MayLoad), 0x2b7000146ULL, NULL, NULL, OperandInfo47 }, // Inst #969 = Int_VCVTPS2DQrm | |
| { 970, 2, 1, 0, 0, "Int_VCVTPS2DQrr", 0, 0x2b7000145ULL, NULL, NULL, OperandInfo48 }, // Inst #970 = Int_VCVTPS2DQrr | |
| { 971, 6, 1, 0, 0, "Int_VCVTPS2PDrm", 0|(1<<MCID::MayLoad), 0x2b4000106ULL, NULL, NULL, OperandInfo47 }, // Inst #971 = Int_VCVTPS2PDrm | |
| { 972, 2, 1, 0, 0, "Int_VCVTPS2PDrr", 0, 0x2b4000105ULL, NULL, NULL, OperandInfo48 }, // Inst #972 = Int_VCVTPS2PDrr | |
| { 973, 6, 1, 0, 0, "Int_VCVTSD2SI64rm", 0|(1<<MCID::MayLoad), 0x65a000b06ULL, NULL, NULL, OperandInfo13 }, // Inst #973 = Int_VCVTSD2SI64rm | |
| { 974, 2, 1, 0, 0, "Int_VCVTSD2SI64rr", 0, 0x65a000b05ULL, NULL, NULL, OperandInfo97 }, // Inst #974 = Int_VCVTSD2SI64rr | |
| { 975, 6, 1, 0, 0, "Int_VCVTSD2SIrm", 0|(1<<MCID::MayLoad), 0x25a000b06ULL, NULL, NULL, OperandInfo12 }, // Inst #975 = Int_VCVTSD2SIrm | |
| { 976, 2, 1, 0, 0, "Int_VCVTSD2SIrr", 0, 0x25a000b05ULL, NULL, NULL, OperandInfo98 }, // Inst #976 = Int_VCVTSD2SIrr | |
| { 977, 7, 1, 0, 0, "Int_VCVTSD2SSrm", 0|(1<<MCID::MayLoad), 0xab4000c06ULL, NULL, NULL, OperandInfo137 }, // Inst #977 = Int_VCVTSD2SSrm | |
| { 978, 3, 1, 0, 0, "Int_VCVTSD2SSrr", 0, 0xab4000c05ULL, NULL, NULL, OperandInfo138 }, // Inst #978 = Int_VCVTSD2SSrr | |
| { 979, 7, 1, 0, 0, "Int_VCVTSI2SD64rm", 0|(1<<MCID::MayLoad), 0xe54000b06ULL, NULL, NULL, OperandInfo137 }, // Inst #979 = Int_VCVTSI2SD64rm | |
| { 980, 3, 1, 0, 0, "Int_VCVTSI2SD64rr", 0, 0xe54000b05ULL, NULL, NULL, OperandInfo139 }, // Inst #980 = Int_VCVTSI2SD64rr | |
| { 981, 7, 1, 0, 0, "Int_VCVTSI2SDrm", 0|(1<<MCID::MayLoad), 0xa54000b06ULL, NULL, NULL, OperandInfo137 }, // Inst #981 = Int_VCVTSI2SDrm | |
| { 982, 3, 1, 0, 0, "Int_VCVTSI2SDrr", 0, 0xa54000b05ULL, NULL, NULL, OperandInfo140 }, // Inst #982 = Int_VCVTSI2SDrr | |
| { 983, 7, 1, 0, 0, "Int_VCVTSI2SS64rm", 0|(1<<MCID::MayLoad), 0xe54000c06ULL, NULL, NULL, OperandInfo137 }, // Inst #983 = Int_VCVTSI2SS64rm | |
| { 984, 3, 1, 0, 0, "Int_VCVTSI2SS64rr", 0, 0xe54000c05ULL, NULL, NULL, OperandInfo139 }, // Inst #984 = Int_VCVTSI2SS64rr | |
| { 985, 7, 1, 0, 0, "Int_VCVTSI2SSrm", 0|(1<<MCID::MayLoad), 0xa54000c06ULL, NULL, NULL, OperandInfo137 }, // Inst #985 = Int_VCVTSI2SSrm | |
| { 986, 3, 1, 0, 0, "Int_VCVTSI2SSrr", 0, 0xa54000c05ULL, NULL, NULL, OperandInfo140 }, // Inst #986 = Int_VCVTSI2SSrr | |
| { 987, 7, 1, 0, 0, "Int_VCVTSS2SDrm", 0|(1<<MCID::MayLoad), 0xab4000c06ULL, NULL, NULL, OperandInfo137 }, // Inst #987 = Int_VCVTSS2SDrm | |
| { 988, 3, 1, 0, 0, "Int_VCVTSS2SDrr", 0, 0xab4000c05ULL, NULL, NULL, OperandInfo138 }, // Inst #988 = Int_VCVTSS2SDrr | |
| { 989, 6, 1, 0, 0, "Int_VCVTTPS2DQrm", 0|(1<<MCID::MayLoad), 0x2b6000c06ULL, NULL, NULL, OperandInfo47 }, // Inst #989 = Int_VCVTTPS2DQrm | |
| { 990, 2, 1, 0, 0, "Int_VCVTTPS2DQrr", 0, 0x2b6000c05ULL, NULL, NULL, OperandInfo48 }, // Inst #990 = Int_VCVTTPS2DQrr | |
| { 991, 6, 1, 0, 0, "Int_VCVTTSD2SI64rm", 0|(1<<MCID::MayLoad), 0x658000b06ULL, NULL, NULL, OperandInfo13 }, // Inst #991 = Int_VCVTTSD2SI64rm | |
| { 992, 2, 1, 0, 0, "Int_VCVTTSD2SI64rr", 0, 0x658000b05ULL, NULL, NULL, OperandInfo97 }, // Inst #992 = Int_VCVTTSD2SI64rr | |
| { 993, 6, 1, 0, 0, "Int_VCVTTSD2SIrm", 0|(1<<MCID::MayLoad), 0x258000b06ULL, NULL, NULL, OperandInfo12 }, // Inst #993 = Int_VCVTTSD2SIrm | |
| { 994, 2, 1, 0, 0, "Int_VCVTTSD2SIrr", 0, 0x258000b05ULL, NULL, NULL, OperandInfo98 }, // Inst #994 = Int_VCVTTSD2SIrr | |
| { 995, 6, 1, 0, 0, "Int_VCVTTSS2SI64rm", 0|(1<<MCID::MayLoad), 0x658000c06ULL, NULL, NULL, OperandInfo13 }, // Inst #995 = Int_VCVTTSS2SI64rm | |
| { 996, 2, 1, 0, 0, "Int_VCVTTSS2SI64rr", 0, 0x658000c05ULL, NULL, NULL, OperandInfo97 }, // Inst #996 = Int_VCVTTSS2SI64rr | |
| { 997, 6, 1, 0, 0, "Int_VCVTTSS2SIrm", 0|(1<<MCID::MayLoad), 0x258000c06ULL, NULL, NULL, OperandInfo12 }, // Inst #997 = Int_VCVTTSS2SIrm | |
| { 998, 2, 1, 0, 0, "Int_VCVTTSS2SIrr", 0, 0x258000c05ULL, NULL, NULL, OperandInfo98 }, // Inst #998 = Int_VCVTTSS2SIrr | |
| { 999, 6, 0, 0, 0, "Int_VUCOMISDrm", 0|(1<<MCID::MayLoad), 0x25d000146ULL, NULL, ImplicitList1, OperandInfo47 }, // Inst #999 = Int_VUCOMISDrm | |
| { 1000, 2, 0, 0, 0, "Int_VUCOMISDrr", 0, 0x25d000145ULL, NULL, ImplicitList1, OperandInfo48 }, // Inst #1000 = Int_VUCOMISDrr | |
| { 1001, 6, 0, 0, 0, "Int_VUCOMISSrm", 0|(1<<MCID::MayLoad), 0x25c800106ULL, NULL, ImplicitList1, OperandInfo47 }, // Inst #1001 = Int_VUCOMISSrm | |
| { 1002, 2, 0, 0, 0, "Int_VUCOMISSrr", 0, 0x25c800105ULL, NULL, ImplicitList1, OperandInfo48 }, // Inst #1002 = Int_VUCOMISSrr | |
| { 1003, 1, 0, 0, 0, "JAE_1", 0|(1<<MCID::Branch)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0xe6008001ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1003 = JAE_1 | |
| { 1004, 1, 0, 0, 0, "JAE_4", 0|(1<<MCID::Branch)|(1<<MCID::Terminator), 0x106018101ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1004 = JAE_4 | |
| { 1005, 1, 0, 0, 0, "JA_1", 0|(1<<MCID::Branch)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0xee008001ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1005 = JA_1 | |
| { 1006, 1, 0, 0, 0, "JA_4", 0|(1<<MCID::Branch)|(1<<MCID::Terminator), 0x10e018101ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1006 = JA_4 | |
| { 1007, 1, 0, 0, 0, "JBE_1", 0|(1<<MCID::Branch)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0xec008001ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1007 = JBE_1 | |
| { 1008, 1, 0, 0, 0, "JBE_4", 0|(1<<MCID::Branch)|(1<<MCID::Terminator), 0x10c018101ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1008 = JBE_4 | |
| { 1009, 1, 0, 0, 0, "JB_1", 0|(1<<MCID::Branch)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0xe4008001ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1009 = JB_1 | |
| { 1010, 1, 0, 0, 0, "JB_4", 0|(1<<MCID::Branch)|(1<<MCID::Terminator), 0x104018101ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1010 = JB_4 | |
| { 1011, 1, 0, 0, 0, "JCXZ", 0|(1<<MCID::Branch)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0x1c6008081ULL, ImplicitList24, NULL, OperandInfo73 }, // Inst #1011 = JCXZ | |
| { 1012, 1, 0, 0, 0, "JECXZ_32", 0|(1<<MCID::Branch)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0x1c6008001ULL, ImplicitList25, NULL, OperandInfo73 }, // Inst #1012 = JECXZ_32 | |
| { 1013, 1, 0, 0, 0, "JECXZ_64", 0|(1<<MCID::Branch)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0x1c6008081ULL, ImplicitList25, NULL, OperandInfo73 }, // Inst #1013 = JECXZ_64 | |
| { 1014, 1, 0, 0, 0, "JE_1", 0|(1<<MCID::Branch)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0xe8008001ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1014 = JE_1 | |
| { 1015, 1, 0, 0, 0, "JE_4", 0|(1<<MCID::Branch)|(1<<MCID::Terminator), 0x108018101ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1015 = JE_4 | |
| { 1016, 1, 0, 0, 0, "JGE_1", 0|(1<<MCID::Branch)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0xfa008001ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1016 = JGE_1 | |
| { 1017, 1, 0, 0, 0, "JGE_4", 0|(1<<MCID::Branch)|(1<<MCID::Terminator), 0x11a018101ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1017 = JGE_4 | |
| { 1018, 1, 0, 0, 0, "JG_1", 0|(1<<MCID::Branch)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0xfe008001ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1018 = JG_1 | |
| { 1019, 1, 0, 0, 0, "JG_4", 0|(1<<MCID::Branch)|(1<<MCID::Terminator), 0x11e018101ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1019 = JG_4 | |
| { 1020, 1, 0, 0, 0, "JLE_1", 0|(1<<MCID::Branch)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0xfc008001ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1020 = JLE_1 | |
| { 1021, 1, 0, 0, 0, "JLE_4", 0|(1<<MCID::Branch)|(1<<MCID::Terminator), 0x11c018101ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1021 = JLE_4 | |
| { 1022, 1, 0, 0, 0, "JL_1", 0|(1<<MCID::Branch)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0xf8008001ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1022 = JL_1 | |
| { 1023, 1, 0, 0, 0, "JL_4", 0|(1<<MCID::Branch)|(1<<MCID::Terminator), 0x118018101ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1023 = JL_4 | |
| { 1024, 5, 0, 0, 0, "JMP32m", 0|(1<<MCID::Branch)|(1<<MCID::IndirectBranch)|(1<<MCID::Barrier)|(1<<MCID::MayLoad)|(1<<MCID::Terminator), 0x1fe00001cULL, NULL, NULL, OperandInfo38 }, // Inst #1024 = JMP32m | |
| { 1025, 1, 0, 0, 0, "JMP32r", 0|(1<<MCID::Branch)|(1<<MCID::IndirectBranch)|(1<<MCID::Barrier)|(1<<MCID::Terminator), 0x1fe000014ULL, NULL, NULL, OperandInfo72 }, // Inst #1025 = JMP32r | |
| { 1026, 5, 0, 0, 0, "JMP64m", 0|(1<<MCID::Branch)|(1<<MCID::IndirectBranch)|(1<<MCID::Barrier)|(1<<MCID::MayLoad)|(1<<MCID::Terminator), 0x1fe00001cULL, NULL, NULL, OperandInfo38 }, // Inst #1026 = JMP64m | |
| { 1027, 1, 0, 0, 0, "JMP64pcrel32", 0|(1<<MCID::Branch)|(1<<MCID::Barrier)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0x1d2000001ULL, NULL, NULL, OperandInfo73 }, // Inst #1027 = JMP64pcrel32 | |
| { 1028, 1, 0, 0, 0, "JMP64r", 0|(1<<MCID::Branch)|(1<<MCID::IndirectBranch)|(1<<MCID::Barrier)|(1<<MCID::Terminator), 0x1fe000014ULL, NULL, NULL, OperandInfo74 }, // Inst #1028 = JMP64r | |
| { 1029, 1, 0, 0, 0, "JMP_1", 0|(1<<MCID::Branch)|(1<<MCID::Barrier)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0x1d6008001ULL, NULL, NULL, OperandInfo73 }, // Inst #1029 = JMP_1 | |
| { 1030, 1, 0, 0, 0, "JMP_4", 0|(1<<MCID::Branch)|(1<<MCID::Barrier)|(1<<MCID::Terminator), 0x1d2018001ULL, NULL, NULL, OperandInfo73 }, // Inst #1030 = JMP_4 | |
| { 1031, 1, 0, 0, 0, "JNE_1", 0|(1<<MCID::Branch)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0xea008001ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1031 = JNE_1 | |
| { 1032, 1, 0, 0, 0, "JNE_4", 0|(1<<MCID::Branch)|(1<<MCID::Terminator), 0x10a018101ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1032 = JNE_4 | |
| { 1033, 1, 0, 0, 0, "JNO_1", 0|(1<<MCID::Branch)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0xe2008001ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1033 = JNO_1 | |
| { 1034, 1, 0, 0, 0, "JNO_4", 0|(1<<MCID::Branch)|(1<<MCID::Terminator), 0x102018101ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1034 = JNO_4 | |
| { 1035, 1, 0, 0, 0, "JNP_1", 0|(1<<MCID::Branch)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0xf6008001ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1035 = JNP_1 | |
| { 1036, 1, 0, 0, 0, "JNP_4", 0|(1<<MCID::Branch)|(1<<MCID::Terminator), 0x116018101ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1036 = JNP_4 | |
| { 1037, 1, 0, 0, 0, "JNS_1", 0|(1<<MCID::Branch)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0xf2008001ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1037 = JNS_1 | |
| { 1038, 1, 0, 0, 0, "JNS_4", 0|(1<<MCID::Branch)|(1<<MCID::Terminator), 0x112018101ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1038 = JNS_4 | |
| { 1039, 1, 0, 0, 0, "JO_1", 0|(1<<MCID::Branch)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0xe0008001ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1039 = JO_1 | |
| { 1040, 1, 0, 0, 0, "JO_4", 0|(1<<MCID::Branch)|(1<<MCID::Terminator), 0x100018101ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1040 = JO_4 | |
| { 1041, 1, 0, 0, 0, "JP_1", 0|(1<<MCID::Branch)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0xf4008001ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1041 = JP_1 | |
| { 1042, 1, 0, 0, 0, "JP_4", 0|(1<<MCID::Branch)|(1<<MCID::Terminator), 0x114018101ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1042 = JP_4 | |
| { 1043, 1, 0, 0, 0, "JRCXZ", 0|(1<<MCID::Branch)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0x1c6008001ULL, ImplicitList26, NULL, OperandInfo73 }, // Inst #1043 = JRCXZ | |
| { 1044, 1, 0, 0, 0, "JS_1", 0|(1<<MCID::Branch)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0xf0008001ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1044 = JS_1 | |
| { 1045, 1, 0, 0, 0, "JS_4", 0|(1<<MCID::Branch)|(1<<MCID::Terminator), 0x110018101ULL, ImplicitList1, NULL, OperandInfo73 }, // Inst #1045 = JS_4 | |
| { 1046, 0, 0, 0, 0, "LAHF", 0, 0x13e000001ULL, ImplicitList1, ImplicitList27, 0 }, // Inst #1046 = LAHF | |
| { 1047, 6, 1, 0, 0, "LAR16rm", 0|(1<<MCID::UnmodeledSideEffects), 0x4000146ULL, NULL, NULL, OperandInfo11 }, // Inst #1047 = LAR16rm | |
| { 1048, 2, 1, 0, 0, "LAR16rr", 0|(1<<MCID::UnmodeledSideEffects), 0x4000145ULL, NULL, NULL, OperandInfo55 }, // Inst #1048 = LAR16rr | |
| { 1049, 6, 1, 0, 0, "LAR32rm", 0|(1<<MCID::UnmodeledSideEffects), 0x4000106ULL, NULL, NULL, OperandInfo12 }, // Inst #1049 = LAR32rm | |
| { 1050, 2, 1, 0, 0, "LAR32rr", 0|(1<<MCID::UnmodeledSideEffects), 0x4000105ULL, NULL, NULL, OperandInfo65 }, // Inst #1050 = LAR32rr | |
| { 1051, 6, 1, 0, 0, "LAR64rm", 0|(1<<MCID::UnmodeledSideEffects), 0x4002106ULL, NULL, NULL, OperandInfo13 }, // Inst #1051 = LAR64rm | |
| { 1052, 2, 1, 0, 0, "LAR64rr", 0|(1<<MCID::UnmodeledSideEffects), 0x4002105ULL, NULL, NULL, OperandInfo141 }, // Inst #1052 = LAR64rr | |
| { 1053, 6, 0, 0, 0, "LCMPXCHG16", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x162100144ULL, ImplicitList2, ImplicitList28, OperandInfo16 }, // Inst #1053 = LCMPXCHG16 | |
| { 1054, 5, 0, 0, 0, "LCMPXCHG16B", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x18e102119ULL, ImplicitList16, ImplicitList17, OperandInfo38 }, // Inst #1054 = LCMPXCHG16B | |
| { 1055, 6, 0, 0, 0, "LCMPXCHG32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x162100104ULL, ImplicitList3, ImplicitList29, OperandInfo20 }, // Inst #1055 = LCMPXCHG32 | |
| { 1056, 6, 0, 0, 0, "LCMPXCHG64", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x162102104ULL, ImplicitList4, ImplicitList30, OperandInfo24 }, // Inst #1056 = LCMPXCHG64 | |
| { 1057, 6, 0, 0, 0, "LCMPXCHG8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x160100104ULL, ImplicitList5, ImplicitList31, OperandInfo28 }, // Inst #1057 = LCMPXCHG8 | |
| { 1058, 5, 0, 0, 0, "LCMPXCHG8B", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x18e100119ULL, ImplicitList10, ImplicitList18, OperandInfo38 }, // Inst #1058 = LCMPXCHG8B | |
| { 1059, 6, 1, 0, 0, "LDDQUrm", 0|(1<<MCID::MayLoad), 0x1e1000b06ULL, NULL, NULL, OperandInfo47 }, // Inst #1059 = LDDQUrm | |
| { 1060, 5, 0, 0, 0, "LDMXCSR", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x15c80011aULL, NULL, NULL, OperandInfo38 }, // Inst #1060 = LDMXCSR | |
| { 1061, 6, 1, 0, 0, "LDS16rm", 0|(1<<MCID::UnmodeledSideEffects), 0x18a000046ULL, NULL, NULL, OperandInfo11 }, // Inst #1061 = LDS16rm | |
| { 1062, 6, 1, 0, 0, "LDS32rm", 0|(1<<MCID::UnmodeledSideEffects), 0x18a000006ULL, NULL, NULL, OperandInfo12 }, // Inst #1062 = LDS32rm | |
| { 1063, 0, 0, 0, 0, "LD_F0", 0|(1<<MCID::UnmodeledSideEffects), 0x1dc000401ULL, NULL, NULL, 0 }, // Inst #1063 = LD_F0 | |
| { 1064, 0, 0, 0, 0, "LD_F1", 0|(1<<MCID::UnmodeledSideEffects), 0x1d0000401ULL, NULL, NULL, 0 }, // Inst #1064 = LD_F1 | |
| { 1065, 5, 0, 0, 0, "LD_F32m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b2000018ULL, NULL, NULL, OperandInfo38 }, // Inst #1065 = LD_F32m | |
| { 1066, 5, 0, 0, 0, "LD_F64m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1ba000018ULL, NULL, NULL, OperandInfo38 }, // Inst #1066 = LD_F64m | |
| { 1067, 5, 0, 0, 0, "LD_F80m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b600001dULL, NULL, NULL, OperandInfo38 }, // Inst #1067 = LD_F80m | |
| { 1068, 1, 1, 0, 0, "LD_Fp032", 0|(1<<MCID::Rematerializable), 0x20000ULL, NULL, NULL, OperandInfo142 }, // Inst #1068 = LD_Fp032 | |
| { 1069, 1, 1, 0, 0, "LD_Fp064", 0|(1<<MCID::Rematerializable), 0x20000ULL, NULL, NULL, OperandInfo143 }, // Inst #1069 = LD_Fp064 | |
| { 1070, 1, 1, 0, 0, "LD_Fp080", 0|(1<<MCID::Rematerializable), 0x20000ULL, NULL, NULL, OperandInfo120 }, // Inst #1070 = LD_Fp080 | |
| { 1071, 1, 1, 0, 0, "LD_Fp132", 0|(1<<MCID::Rematerializable), 0x20000ULL, NULL, NULL, OperandInfo142 }, // Inst #1071 = LD_Fp132 | |
| { 1072, 1, 1, 0, 0, "LD_Fp164", 0|(1<<MCID::Rematerializable), 0x20000ULL, NULL, NULL, OperandInfo143 }, // Inst #1072 = LD_Fp164 | |
| { 1073, 1, 1, 0, 0, "LD_Fp180", 0|(1<<MCID::Rematerializable), 0x20000ULL, NULL, NULL, OperandInfo120 }, // Inst #1073 = LD_Fp180 | |
| { 1074, 6, 1, 0, 0, "LD_Fp32m", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad), 0x20000ULL, NULL, NULL, OperandInfo125 }, // Inst #1074 = LD_Fp32m | |
| { 1075, 6, 1, 0, 0, "LD_Fp32m64", 0|(1<<MCID::MayLoad), 0x20000ULL, NULL, NULL, OperandInfo126 }, // Inst #1075 = LD_Fp32m64 | |
| { 1076, 6, 1, 0, 0, "LD_Fp32m80", 0|(1<<MCID::MayLoad), 0x20000ULL, NULL, NULL, OperandInfo127 }, // Inst #1076 = LD_Fp32m80 | |
| { 1077, 6, 1, 0, 0, "LD_Fp64m", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x20000ULL, NULL, NULL, OperandInfo126 }, // Inst #1077 = LD_Fp64m | |
| { 1078, 6, 1, 0, 0, "LD_Fp64m80", 0|(1<<MCID::MayLoad), 0x20000ULL, NULL, NULL, OperandInfo127 }, // Inst #1078 = LD_Fp64m80 | |
| { 1079, 6, 1, 0, 0, "LD_Fp80m", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad), 0x20000ULL, NULL, NULL, OperandInfo127 }, // Inst #1079 = LD_Fp80m | |
| { 1080, 1, 0, 0, 0, "LD_Frr", 0|(1<<MCID::UnmodeledSideEffects), 0x180000402ULL, NULL, NULL, OperandInfo39 }, // Inst #1080 = LD_Frr | |
| { 1081, 6, 1, 0, 0, "LEA16r", 0, 0x11a000046ULL, NULL, NULL, OperandInfo11 }, // Inst #1081 = LEA16r | |
| { 1082, 6, 1, 0, 0, "LEA32r", 0|(1<<MCID::Rematerializable), 0x11a000006ULL, NULL, NULL, OperandInfo12 }, // Inst #1082 = LEA32r | |
| { 1083, 6, 1, 0, 0, "LEA64_32r", 0, 0x11a000006ULL, NULL, NULL, OperandInfo144 }, // Inst #1083 = LEA64_32r | |
| { 1084, 6, 1, 0, 0, "LEA64r", 0|(1<<MCID::Rematerializable), 0x11a002006ULL, NULL, NULL, OperandInfo13 }, // Inst #1084 = LEA64r | |
| { 1085, 0, 0, 0, 0, "LEAVE", 0|(1<<MCID::MayLoad), 0x192000001ULL, ImplicitList32, ImplicitList32, 0 }, // Inst #1085 = LEAVE | |
| { 1086, 0, 0, 0, 0, "LEAVE64", 0|(1<<MCID::MayLoad), 0x192000001ULL, ImplicitList33, ImplicitList33, 0 }, // Inst #1086 = LEAVE64 | |
| { 1087, 6, 1, 0, 0, "LES16rm", 0|(1<<MCID::UnmodeledSideEffects), 0x188000046ULL, NULL, NULL, OperandInfo11 }, // Inst #1087 = LES16rm | |
| { 1088, 6, 1, 0, 0, "LES32rm", 0|(1<<MCID::UnmodeledSideEffects), 0x188000006ULL, NULL, NULL, OperandInfo12 }, // Inst #1088 = LES32rm | |
| { 1089, 0, 0, 0, 0, "LFENCE", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x15c000127ULL, NULL, NULL, 0 }, // Inst #1089 = LFENCE | |
| { 1090, 6, 1, 0, 0, "LFS16rm", 0|(1<<MCID::UnmodeledSideEffects), 0x168000146ULL, NULL, NULL, OperandInfo11 }, // Inst #1090 = LFS16rm | |
| { 1091, 6, 1, 0, 0, "LFS32rm", 0|(1<<MCID::UnmodeledSideEffects), 0x168000106ULL, NULL, NULL, OperandInfo12 }, // Inst #1091 = LFS32rm | |
| { 1092, 6, 1, 0, 0, "LFS64rm", 0|(1<<MCID::UnmodeledSideEffects), 0x168002106ULL, NULL, NULL, OperandInfo13 }, // Inst #1092 = LFS64rm | |
| { 1093, 5, 0, 0, 0, "LGDT16m", 0|(1<<MCID::UnmodeledSideEffects), 0x200015aULL, NULL, NULL, OperandInfo38 }, // Inst #1093 = LGDT16m | |
| { 1094, 5, 0, 0, 0, "LGDTm", 0|(1<<MCID::UnmodeledSideEffects), 0x200011aULL, NULL, NULL, OperandInfo38 }, // Inst #1094 = LGDTm | |
| { 1095, 6, 1, 0, 0, "LGS16rm", 0|(1<<MCID::UnmodeledSideEffects), 0x16a000146ULL, NULL, NULL, OperandInfo11 }, // Inst #1095 = LGS16rm | |
| { 1096, 6, 1, 0, 0, "LGS32rm", 0|(1<<MCID::UnmodeledSideEffects), 0x16a000106ULL, NULL, NULL, OperandInfo12 }, // Inst #1096 = LGS32rm | |
| { 1097, 6, 1, 0, 0, "LGS64rm", 0|(1<<MCID::UnmodeledSideEffects), 0x16a002106ULL, NULL, NULL, OperandInfo13 }, // Inst #1097 = LGS64rm | |
| { 1098, 5, 0, 0, 0, "LIDT16m", 0|(1<<MCID::UnmodeledSideEffects), 0x200015bULL, NULL, NULL, OperandInfo38 }, // Inst #1098 = LIDT16m | |
| { 1099, 5, 0, 0, 0, "LIDTm", 0|(1<<MCID::UnmodeledSideEffects), 0x200011bULL, NULL, NULL, OperandInfo38 }, // Inst #1099 = LIDTm | |
| { 1100, 5, 0, 0, 0, "LLDT16m", 0|(1<<MCID::UnmodeledSideEffects), 0x11aULL, NULL, NULL, OperandInfo38 }, // Inst #1100 = LLDT16m | |
| { 1101, 1, 0, 0, 0, "LLDT16r", 0|(1<<MCID::UnmodeledSideEffects), 0x112ULL, NULL, NULL, OperandInfo113 }, // Inst #1101 = LLDT16r | |
| { 1102, 5, 0, 0, 0, "LMSW16m", 0|(1<<MCID::UnmodeledSideEffects), 0x200011eULL, NULL, NULL, OperandInfo38 }, // Inst #1102 = LMSW16m | |
| { 1103, 1, 0, 0, 0, "LMSW16r", 0|(1<<MCID::UnmodeledSideEffects), 0x2000116ULL, NULL, NULL, OperandInfo113 }, // Inst #1103 = LMSW16r | |
| { 1104, 6, 0, 0, 0, "LOCK_ADD16mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10210c018ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1104 = LOCK_ADD16mi | |
| { 1105, 6, 0, 0, 0, "LOCK_ADD16mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x106104018ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1105 = LOCK_ADD16mi8 | |
| { 1106, 6, 0, 0, 0, "LOCK_ADD16mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x2100044ULL, NULL, ImplicitList1, OperandInfo16 }, // Inst #1106 = LOCK_ADD16mr | |
| { 1107, 6, 0, 0, 0, "LOCK_ADD32mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x102114018ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1107 = LOCK_ADD32mi | |
| { 1108, 6, 0, 0, 0, "LOCK_ADD32mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x106104018ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1108 = LOCK_ADD32mi8 | |
| { 1109, 6, 0, 0, 0, "LOCK_ADD32mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x2100004ULL, NULL, ImplicitList1, OperandInfo20 }, // Inst #1109 = LOCK_ADD32mr | |
| { 1110, 6, 0, 0, 0, "LOCK_ADD64mi32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x102116018ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1110 = LOCK_ADD64mi32 | |
| { 1111, 6, 0, 0, 0, "LOCK_ADD64mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x106106018ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1111 = LOCK_ADD64mi8 | |
| { 1112, 6, 0, 0, 0, "LOCK_ADD64mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x2102004ULL, NULL, ImplicitList1, OperandInfo24 }, // Inst #1112 = LOCK_ADD64mr | |
| { 1113, 6, 0, 0, 0, "LOCK_ADD8mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x100104018ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1113 = LOCK_ADD8mi | |
| { 1114, 6, 0, 0, 0, "LOCK_ADD8mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x100004ULL, NULL, ImplicitList1, OperandInfo28 }, // Inst #1114 = LOCK_ADD8mr | |
| { 1115, 6, 0, 0, 0, "LOCK_AND16mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10210c01cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1115 = LOCK_AND16mi | |
| { 1116, 6, 0, 0, 0, "LOCK_AND16mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10610401cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1116 = LOCK_AND16mi8 | |
| { 1117, 6, 0, 0, 0, "LOCK_AND16mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x42100044ULL, NULL, ImplicitList1, OperandInfo16 }, // Inst #1117 = LOCK_AND16mr | |
| { 1118, 6, 0, 0, 0, "LOCK_AND32mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10211401cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1118 = LOCK_AND32mi | |
| { 1119, 6, 0, 0, 0, "LOCK_AND32mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10610401cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1119 = LOCK_AND32mi8 | |
| { 1120, 6, 0, 0, 0, "LOCK_AND32mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x42100004ULL, NULL, ImplicitList1, OperandInfo20 }, // Inst #1120 = LOCK_AND32mr | |
| { 1121, 6, 0, 0, 0, "LOCK_AND64mi32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10211601cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1121 = LOCK_AND64mi32 | |
| { 1122, 6, 0, 0, 0, "LOCK_AND64mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10610601cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1122 = LOCK_AND64mi8 | |
| { 1123, 6, 0, 0, 0, "LOCK_AND64mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x42102004ULL, NULL, ImplicitList1, OperandInfo24 }, // Inst #1123 = LOCK_AND64mr | |
| { 1124, 6, 0, 0, 0, "LOCK_AND8mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10010401cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1124 = LOCK_AND8mi | |
| { 1125, 6, 0, 0, 0, "LOCK_AND8mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x40100004ULL, NULL, ImplicitList1, OperandInfo28 }, // Inst #1125 = LOCK_AND8mr | |
| { 1126, 5, 0, 0, 0, "LOCK_DEC16m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1fe100059ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #1126 = LOCK_DEC16m | |
| { 1127, 5, 0, 0, 0, "LOCK_DEC32m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1fe100019ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #1127 = LOCK_DEC32m | |
| { 1128, 5, 0, 0, 0, "LOCK_DEC64m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1fe102019ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #1128 = LOCK_DEC64m | |
| { 1129, 5, 0, 0, 0, "LOCK_DEC8m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1fc100019ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #1129 = LOCK_DEC8m | |
| { 1130, 5, 0, 0, 0, "LOCK_INC16m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1fe100058ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #1130 = LOCK_INC16m | |
| { 1131, 5, 0, 0, 0, "LOCK_INC32m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1fe100018ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #1131 = LOCK_INC32m | |
| { 1132, 5, 0, 0, 0, "LOCK_INC64m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1fe102018ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #1132 = LOCK_INC64m | |
| { 1133, 5, 0, 0, 0, "LOCK_INC8m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1fc100018ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #1133 = LOCK_INC8m | |
| { 1134, 6, 0, 0, 0, "LOCK_OR16mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10210c019ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1134 = LOCK_OR16mi | |
| { 1135, 6, 0, 0, 0, "LOCK_OR16mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x106104019ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1135 = LOCK_OR16mi8 | |
| { 1136, 6, 0, 0, 0, "LOCK_OR16mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x12100044ULL, NULL, ImplicitList1, OperandInfo16 }, // Inst #1136 = LOCK_OR16mr | |
| { 1137, 6, 0, 0, 0, "LOCK_OR32mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x102114019ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1137 = LOCK_OR32mi | |
| { 1138, 6, 0, 0, 0, "LOCK_OR32mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x106104019ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1138 = LOCK_OR32mi8 | |
| { 1139, 6, 0, 0, 0, "LOCK_OR32mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x12100004ULL, NULL, ImplicitList1, OperandInfo20 }, // Inst #1139 = LOCK_OR32mr | |
| { 1140, 6, 0, 0, 0, "LOCK_OR64mi32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x102116019ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1140 = LOCK_OR64mi32 | |
| { 1141, 6, 0, 0, 0, "LOCK_OR64mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x106106019ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1141 = LOCK_OR64mi8 | |
| { 1142, 6, 0, 0, 0, "LOCK_OR64mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x12102004ULL, NULL, ImplicitList1, OperandInfo24 }, // Inst #1142 = LOCK_OR64mr | |
| { 1143, 6, 0, 0, 0, "LOCK_OR8mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x100104019ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1143 = LOCK_OR8mi | |
| { 1144, 6, 0, 0, 0, "LOCK_OR8mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10100004ULL, NULL, ImplicitList1, OperandInfo28 }, // Inst #1144 = LOCK_OR8mr | |
| { 1145, 0, 0, 0, 0, "LOCK_PREFIX", 0|(1<<MCID::UnmodeledSideEffects), 0x1e0000001ULL, NULL, NULL, 0 }, // Inst #1145 = LOCK_PREFIX | |
| { 1146, 6, 0, 0, 0, "LOCK_SUB16mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10210c01dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1146 = LOCK_SUB16mi | |
| { 1147, 6, 0, 0, 0, "LOCK_SUB16mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10610401dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1147 = LOCK_SUB16mi8 | |
| { 1148, 6, 0, 0, 0, "LOCK_SUB16mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x52100044ULL, NULL, ImplicitList1, OperandInfo16 }, // Inst #1148 = LOCK_SUB16mr | |
| { 1149, 6, 0, 0, 0, "LOCK_SUB32mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10211401dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1149 = LOCK_SUB32mi | |
| { 1150, 6, 0, 0, 0, "LOCK_SUB32mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10610401dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1150 = LOCK_SUB32mi8 | |
| { 1151, 6, 0, 0, 0, "LOCK_SUB32mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x52100004ULL, NULL, ImplicitList1, OperandInfo20 }, // Inst #1151 = LOCK_SUB32mr | |
| { 1152, 6, 0, 0, 0, "LOCK_SUB64mi32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10211601dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1152 = LOCK_SUB64mi32 | |
| { 1153, 6, 0, 0, 0, "LOCK_SUB64mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10610601dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1153 = LOCK_SUB64mi8 | |
| { 1154, 6, 0, 0, 0, "LOCK_SUB64mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x52102004ULL, NULL, ImplicitList1, OperandInfo24 }, // Inst #1154 = LOCK_SUB64mr | |
| { 1155, 6, 0, 0, 0, "LOCK_SUB8mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10010401dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1155 = LOCK_SUB8mi | |
| { 1156, 6, 0, 0, 0, "LOCK_SUB8mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x50100004ULL, NULL, ImplicitList1, OperandInfo28 }, // Inst #1156 = LOCK_SUB8mr | |
| { 1157, 6, 0, 0, 0, "LOCK_XOR16mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10210c01eULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1157 = LOCK_XOR16mi | |
| { 1158, 6, 0, 0, 0, "LOCK_XOR16mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10610401eULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1158 = LOCK_XOR16mi8 | |
| { 1159, 6, 0, 0, 0, "LOCK_XOR16mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x62100044ULL, NULL, ImplicitList1, OperandInfo16 }, // Inst #1159 = LOCK_XOR16mr | |
| { 1160, 6, 0, 0, 0, "LOCK_XOR32mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10211401eULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1160 = LOCK_XOR32mi | |
| { 1161, 6, 0, 0, 0, "LOCK_XOR32mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10610401eULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1161 = LOCK_XOR32mi8 | |
| { 1162, 6, 0, 0, 0, "LOCK_XOR32mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x62100004ULL, NULL, ImplicitList1, OperandInfo20 }, // Inst #1162 = LOCK_XOR32mr | |
| { 1163, 6, 0, 0, 0, "LOCK_XOR64mi32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10211601eULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1163 = LOCK_XOR64mi32 | |
| { 1164, 6, 0, 0, 0, "LOCK_XOR64mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10610601eULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1164 = LOCK_XOR64mi8 | |
| { 1165, 6, 0, 0, 0, "LOCK_XOR64mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x62102004ULL, NULL, ImplicitList1, OperandInfo24 }, // Inst #1165 = LOCK_XOR64mr | |
| { 1166, 6, 0, 0, 0, "LOCK_XOR8mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x10010401eULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1166 = LOCK_XOR8mi | |
| { 1167, 6, 0, 0, 0, "LOCK_XOR8mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x60100004ULL, NULL, ImplicitList1, OperandInfo28 }, // Inst #1167 = LOCK_XOR8mr | |
| { 1168, 0, 0, 0, 0, "LODSB", 0|(1<<MCID::UnmodeledSideEffects), 0x158000001ULL, NULL, NULL, 0 }, // Inst #1168 = LODSB | |
| { 1169, 0, 0, 0, 0, "LODSD", 0|(1<<MCID::UnmodeledSideEffects), 0x15a000001ULL, NULL, NULL, 0 }, // Inst #1169 = LODSD | |
| { 1170, 0, 0, 0, 0, "LODSQ", 0|(1<<MCID::UnmodeledSideEffects), 0x15a002001ULL, NULL, NULL, 0 }, // Inst #1170 = LODSQ | |
| { 1171, 0, 0, 0, 0, "LODSW", 0|(1<<MCID::UnmodeledSideEffects), 0x15a000041ULL, NULL, NULL, 0 }, // Inst #1171 = LODSW | |
| { 1172, 1, 0, 0, 0, "LOOP", 0|(1<<MCID::UnmodeledSideEffects), 0x1c4008001ULL, NULL, NULL, OperandInfo73 }, // Inst #1172 = LOOP | |
| { 1173, 1, 0, 0, 0, "LOOPE", 0|(1<<MCID::UnmodeledSideEffects), 0x1c2008001ULL, NULL, NULL, OperandInfo73 }, // Inst #1173 = LOOPE | |
| { 1174, 1, 0, 0, 0, "LOOPNE", 0|(1<<MCID::UnmodeledSideEffects), 0x1c0008001ULL, NULL, NULL, OperandInfo73 }, // Inst #1174 = LOOPNE | |
| { 1175, 1, 0, 0, 0, "LRETI", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0x1940ec001ULL, NULL, NULL, OperandInfo2 }, // Inst #1175 = LRETI | |
| { 1176, 1, 0, 0, 0, "LRETIW", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0x1940ec041ULL, NULL, NULL, OperandInfo2 }, // Inst #1176 = LRETIW | |
| { 1177, 0, 0, 0, 0, "LRETL", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0x1960e0001ULL, NULL, NULL, 0 }, // Inst #1177 = LRETL | |
| { 1178, 0, 0, 0, 0, "LRETQ", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0x1960e2001ULL, NULL, NULL, 0 }, // Inst #1178 = LRETQ | |
| { 1179, 6, 1, 0, 0, "LSL16rm", 0|(1<<MCID::UnmodeledSideEffects), 0x6000146ULL, NULL, NULL, OperandInfo11 }, // Inst #1179 = LSL16rm | |
| { 1180, 2, 1, 0, 0, "LSL16rr", 0|(1<<MCID::UnmodeledSideEffects), 0x6000145ULL, NULL, NULL, OperandInfo55 }, // Inst #1180 = LSL16rr | |
| { 1181, 6, 1, 0, 0, "LSL32rm", 0|(1<<MCID::UnmodeledSideEffects), 0x6000106ULL, NULL, NULL, OperandInfo12 }, // Inst #1181 = LSL32rm | |
| { 1182, 2, 1, 0, 0, "LSL32rr", 0|(1<<MCID::UnmodeledSideEffects), 0x6000105ULL, NULL, NULL, OperandInfo65 }, // Inst #1182 = LSL32rr | |
| { 1183, 6, 1, 0, 0, "LSL64rm", 0|(1<<MCID::UnmodeledSideEffects), 0x6002106ULL, NULL, NULL, OperandInfo13 }, // Inst #1183 = LSL64rm | |
| { 1184, 2, 1, 0, 0, "LSL64rr", 0|(1<<MCID::UnmodeledSideEffects), 0x6002105ULL, NULL, NULL, OperandInfo66 }, // Inst #1184 = LSL64rr | |
| { 1185, 6, 1, 0, 0, "LSS16rm", 0|(1<<MCID::UnmodeledSideEffects), 0x164000146ULL, NULL, NULL, OperandInfo11 }, // Inst #1185 = LSS16rm | |
| { 1186, 6, 1, 0, 0, "LSS32rm", 0|(1<<MCID::UnmodeledSideEffects), 0x164000106ULL, NULL, NULL, OperandInfo12 }, // Inst #1186 = LSS32rm | |
| { 1187, 6, 1, 0, 0, "LSS64rm", 0|(1<<MCID::UnmodeledSideEffects), 0x164002106ULL, NULL, NULL, OperandInfo13 }, // Inst #1187 = LSS64rm | |
| { 1188, 5, 0, 0, 0, "LTRm", 0|(1<<MCID::UnmodeledSideEffects), 0x11bULL, NULL, NULL, OperandInfo38 }, // Inst #1188 = LTRm | |
| { 1189, 1, 0, 0, 0, "LTRr", 0|(1<<MCID::UnmodeledSideEffects), 0x113ULL, NULL, NULL, OperandInfo113 }, // Inst #1189 = LTRr | |
| { 1190, 7, 1, 0, 0, "LXADD16", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x182100146ULL, NULL, ImplicitList1, OperandInfo18 }, // Inst #1190 = LXADD16 | |
| { 1191, 7, 1, 0, 0, "LXADD32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x182100106ULL, NULL, ImplicitList1, OperandInfo22 }, // Inst #1191 = LXADD32 | |
| { 1192, 7, 1, 0, 0, "LXADD64", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x182102106ULL, NULL, ImplicitList1, OperandInfo26 }, // Inst #1192 = LXADD64 | |
| { 1193, 7, 1, 0, 0, "LXADD8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x180100106ULL, NULL, ImplicitList1, OperandInfo30 }, // Inst #1193 = LXADD8 | |
| { 1194, 6, 1, 0, 0, "LZCNT16rm", 0|(1<<MCID::MayLoad), 0x17a000c46ULL, NULL, ImplicitList1, OperandInfo11 }, // Inst #1194 = LZCNT16rm | |
| { 1195, 2, 1, 0, 0, "LZCNT16rr", 0, 0x17a000c45ULL, NULL, ImplicitList1, OperandInfo55 }, // Inst #1195 = LZCNT16rr | |
| { 1196, 6, 1, 0, 0, "LZCNT32rm", 0|(1<<MCID::MayLoad), 0x17a000c06ULL, NULL, ImplicitList1, OperandInfo12 }, // Inst #1196 = LZCNT32rm | |
| { 1197, 2, 1, 0, 0, "LZCNT32rr", 0, 0x17a000c05ULL, NULL, ImplicitList1, OperandInfo65 }, // Inst #1197 = LZCNT32rr | |
| { 1198, 6, 1, 0, 0, "LZCNT64rm", 0|(1<<MCID::MayLoad), 0x17a002c06ULL, NULL, ImplicitList1, OperandInfo13 }, // Inst #1198 = LZCNT64rm | |
| { 1199, 2, 1, 0, 0, "LZCNT64rr", 0, 0x17a002c05ULL, NULL, ImplicitList1, OperandInfo66 }, // Inst #1199 = LZCNT64rr | |
| { 1200, 2, 0, 0, 0, "MASKMOVDQU", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1ef800145ULL, ImplicitList34, NULL, OperandInfo48 }, // Inst #1200 = MASKMOVDQU | |
| { 1201, 2, 0, 0, 0, "MASKMOVDQU64", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1ef800145ULL, ImplicitList35, NULL, OperandInfo48 }, // Inst #1201 = MASKMOVDQU64 | |
| { 1202, 7, 1, 0, 0, "MAXPDrm", 0|(1<<MCID::MayLoad), 0xbf000146ULL, NULL, NULL, OperandInfo32 }, // Inst #1202 = MAXPDrm | |
| { 1203, 7, 1, 0, 0, "MAXPDrm_Int", 0|(1<<MCID::MayLoad), 0xbf000146ULL, NULL, NULL, OperandInfo32 }, // Inst #1203 = MAXPDrm_Int | |
| { 1204, 3, 1, 0, 0, "MAXPDrr", 0, 0xbf000145ULL, NULL, NULL, OperandInfo33 }, // Inst #1204 = MAXPDrr | |
| { 1205, 3, 1, 0, 0, "MAXPDrr_Int", 0, 0xbf000145ULL, NULL, NULL, OperandInfo33 }, // Inst #1205 = MAXPDrr_Int | |
| { 1206, 7, 1, 0, 0, "MAXPSrm", 0|(1<<MCID::MayLoad), 0xbe800106ULL, NULL, NULL, OperandInfo32 }, // Inst #1206 = MAXPSrm | |
| { 1207, 7, 1, 0, 0, "MAXPSrm_Int", 0|(1<<MCID::MayLoad), 0xbe800106ULL, NULL, NULL, OperandInfo32 }, // Inst #1207 = MAXPSrm_Int | |
| { 1208, 3, 1, 0, 0, "MAXPSrr", 0, 0xbe800105ULL, NULL, NULL, OperandInfo33 }, // Inst #1208 = MAXPSrr | |
| { 1209, 3, 1, 0, 0, "MAXPSrr_Int", 0, 0xbe800105ULL, NULL, NULL, OperandInfo33 }, // Inst #1209 = MAXPSrr_Int | |
| { 1210, 7, 1, 0, 0, "MAXSDrm", 0|(1<<MCID::MayLoad), 0xbe000b06ULL, NULL, NULL, OperandInfo34 }, // Inst #1210 = MAXSDrm | |
| { 1211, 7, 1, 0, 0, "MAXSDrm_Int", 0|(1<<MCID::MayLoad), 0xbe000b06ULL, NULL, NULL, OperandInfo32 }, // Inst #1211 = MAXSDrm_Int | |
| { 1212, 3, 1, 0, 0, "MAXSDrr", 0, 0xbe000b05ULL, NULL, NULL, OperandInfo35 }, // Inst #1212 = MAXSDrr | |
| { 1213, 3, 1, 0, 0, "MAXSDrr_Int", 0, 0xbe000b05ULL, NULL, NULL, OperandInfo33 }, // Inst #1213 = MAXSDrr_Int | |
| { 1214, 7, 1, 0, 0, "MAXSSrm", 0|(1<<MCID::MayLoad), 0xbe000c06ULL, NULL, NULL, OperandInfo36 }, // Inst #1214 = MAXSSrm | |
| { 1215, 7, 1, 0, 0, "MAXSSrm_Int", 0|(1<<MCID::MayLoad), 0xbe000c06ULL, NULL, NULL, OperandInfo32 }, // Inst #1215 = MAXSSrm_Int | |
| { 1216, 3, 1, 0, 0, "MAXSSrr", 0, 0xbe000c05ULL, NULL, NULL, OperandInfo37 }, // Inst #1216 = MAXSSrr | |
| { 1217, 3, 1, 0, 0, "MAXSSrr_Int", 0, 0xbe000c05ULL, NULL, NULL, OperandInfo33 }, // Inst #1217 = MAXSSrr_Int | |
| { 1218, 0, 0, 0, 0, "MFENCE", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x15c000128ULL, NULL, NULL, 0 }, // Inst #1218 = MFENCE | |
| { 1219, 7, 1, 0, 0, "MINPDrm", 0|(1<<MCID::MayLoad), 0xbb000146ULL, NULL, NULL, OperandInfo32 }, // Inst #1219 = MINPDrm | |
| { 1220, 7, 1, 0, 0, "MINPDrm_Int", 0|(1<<MCID::MayLoad), 0xbb000146ULL, NULL, NULL, OperandInfo32 }, // Inst #1220 = MINPDrm_Int | |
| { 1221, 3, 1, 0, 0, "MINPDrr", 0, 0xbb000145ULL, NULL, NULL, OperandInfo33 }, // Inst #1221 = MINPDrr | |
| { 1222, 3, 1, 0, 0, "MINPDrr_Int", 0, 0xbb000145ULL, NULL, NULL, OperandInfo33 }, // Inst #1222 = MINPDrr_Int | |
| { 1223, 7, 1, 0, 0, "MINPSrm", 0|(1<<MCID::MayLoad), 0xba800106ULL, NULL, NULL, OperandInfo32 }, // Inst #1223 = MINPSrm | |
| { 1224, 7, 1, 0, 0, "MINPSrm_Int", 0|(1<<MCID::MayLoad), 0xba800106ULL, NULL, NULL, OperandInfo32 }, // Inst #1224 = MINPSrm_Int | |
| { 1225, 3, 1, 0, 0, "MINPSrr", 0, 0xba800105ULL, NULL, NULL, OperandInfo33 }, // Inst #1225 = MINPSrr | |
| { 1226, 3, 1, 0, 0, "MINPSrr_Int", 0, 0xba800105ULL, NULL, NULL, OperandInfo33 }, // Inst #1226 = MINPSrr_Int | |
| { 1227, 7, 1, 0, 0, "MINSDrm", 0|(1<<MCID::MayLoad), 0xba000b06ULL, NULL, NULL, OperandInfo34 }, // Inst #1227 = MINSDrm | |
| { 1228, 7, 1, 0, 0, "MINSDrm_Int", 0|(1<<MCID::MayLoad), 0xba000b06ULL, NULL, NULL, OperandInfo32 }, // Inst #1228 = MINSDrm_Int | |
| { 1229, 3, 1, 0, 0, "MINSDrr", 0, 0xba000b05ULL, NULL, NULL, OperandInfo35 }, // Inst #1229 = MINSDrr | |
| { 1230, 3, 1, 0, 0, "MINSDrr_Int", 0, 0xba000b05ULL, NULL, NULL, OperandInfo33 }, // Inst #1230 = MINSDrr_Int | |
| { 1231, 7, 1, 0, 0, "MINSSrm", 0|(1<<MCID::MayLoad), 0xba000c06ULL, NULL, NULL, OperandInfo36 }, // Inst #1231 = MINSSrm | |
| { 1232, 7, 1, 0, 0, "MINSSrm_Int", 0|(1<<MCID::MayLoad), 0xba000c06ULL, NULL, NULL, OperandInfo32 }, // Inst #1232 = MINSSrm_Int | |
| { 1233, 3, 1, 0, 0, "MINSSrr", 0, 0xba000c05ULL, NULL, NULL, OperandInfo37 }, // Inst #1233 = MINSSrr | |
| { 1234, 3, 1, 0, 0, "MINSSrr_Int", 0, 0xba000c05ULL, NULL, NULL, OperandInfo33 }, // Inst #1234 = MINSSrr_Int | |
| { 1235, 6, 1, 0, 0, "MMX_CVTPD2PIirm", 0|(1<<MCID::MayLoad), 0x5b000146ULL, NULL, NULL, OperandInfo145 }, // Inst #1235 = MMX_CVTPD2PIirm | |
| { 1236, 2, 1, 0, 0, "MMX_CVTPD2PIirr", 0, 0x5b000145ULL, NULL, NULL, OperandInfo146 }, // Inst #1236 = MMX_CVTPD2PIirr | |
| { 1237, 6, 1, 0, 0, "MMX_CVTPI2PDirm", 0|(1<<MCID::MayLoad), 0x55000146ULL, NULL, NULL, OperandInfo47 }, // Inst #1237 = MMX_CVTPI2PDirm | |
| { 1238, 2, 1, 0, 0, "MMX_CVTPI2PDirr", 0, 0x55000145ULL, NULL, NULL, OperandInfo147 }, // Inst #1238 = MMX_CVTPI2PDirr | |
| { 1239, 7, 1, 0, 0, "MMX_CVTPI2PSirm", 0|(1<<MCID::MayLoad), 0x54800106ULL, NULL, NULL, OperandInfo32 }, // Inst #1239 = MMX_CVTPI2PSirm | |
| { 1240, 3, 1, 0, 0, "MMX_CVTPI2PSirr", 0, 0x54800105ULL, NULL, NULL, OperandInfo148 }, // Inst #1240 = MMX_CVTPI2PSirr | |
| { 1241, 6, 1, 0, 0, "MMX_CVTPS2PIirm", 0|(1<<MCID::MayLoad), 0x5a800106ULL, NULL, NULL, OperandInfo145 }, // Inst #1241 = MMX_CVTPS2PIirm | |
| { 1242, 2, 1, 0, 0, "MMX_CVTPS2PIirr", 0, 0x5a800105ULL, NULL, NULL, OperandInfo146 }, // Inst #1242 = MMX_CVTPS2PIirr | |
| { 1243, 6, 1, 0, 0, "MMX_CVTTPD2PIirm", 0|(1<<MCID::MayLoad), 0x59000146ULL, NULL, NULL, OperandInfo145 }, // Inst #1243 = MMX_CVTTPD2PIirm | |
| { 1244, 2, 1, 0, 0, "MMX_CVTTPD2PIirr", 0, 0x59000145ULL, NULL, NULL, OperandInfo146 }, // Inst #1244 = MMX_CVTTPD2PIirr | |
| { 1245, 6, 1, 0, 0, "MMX_CVTTPS2PIirm", 0|(1<<MCID::MayLoad), 0x58800106ULL, NULL, NULL, OperandInfo145 }, // Inst #1245 = MMX_CVTTPS2PIirm | |
| { 1246, 2, 1, 0, 0, "MMX_CVTTPS2PIirr", 0, 0x58800105ULL, NULL, NULL, OperandInfo146 }, // Inst #1246 = MMX_CVTTPS2PIirr | |
| { 1247, 0, 0, 0, 0, "MMX_EMMS", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0xee000101ULL, NULL, NULL, 0 }, // Inst #1247 = MMX_EMMS | |
| { 1248, 2, 0, 0, 0, "MMX_MASKMOVQ", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1ee000105ULL, ImplicitList34, NULL, OperandInfo149 }, // Inst #1248 = MMX_MASKMOVQ | |
| { 1249, 2, 0, 0, 0, "MMX_MASKMOVQ64", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1ee000105ULL, ImplicitList35, NULL, OperandInfo149 }, // Inst #1249 = MMX_MASKMOVQ64 | |
| { 1250, 2, 1, 0, 0, "MMX_MOVD64from64rr", 0|(1<<MCID::Bitcast), 0xfc002103ULL, NULL, NULL, OperandInfo150 }, // Inst #1250 = MMX_MOVD64from64rr | |
| { 1251, 2, 1, 0, 0, "MMX_MOVD64grr", 0, 0xfc000103ULL, NULL, NULL, OperandInfo151 }, // Inst #1251 = MMX_MOVD64grr | |
| { 1252, 6, 0, 0, 0, "MMX_MOVD64mr", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0xfc000104ULL, NULL, NULL, OperandInfo152 }, // Inst #1252 = MMX_MOVD64mr | |
| { 1253, 6, 1, 0, 0, "MMX_MOVD64rm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad), 0xdc000106ULL, NULL, NULL, OperandInfo145 }, // Inst #1253 = MMX_MOVD64rm | |
| { 1254, 2, 1, 0, 0, "MMX_MOVD64rr", 0, 0xdc000105ULL, NULL, NULL, OperandInfo153 }, // Inst #1254 = MMX_MOVD64rr | |
| { 1255, 2, 1, 0, 0, "MMX_MOVD64rrv164", 0|(1<<MCID::Bitcast), 0xdc002105ULL, NULL, NULL, OperandInfo154 }, // Inst #1255 = MMX_MOVD64rrv164 | |
| { 1256, 2, 1, 0, 0, "MMX_MOVD64to64rr", 0, 0xdc002105ULL, NULL, NULL, OperandInfo154 }, // Inst #1256 = MMX_MOVD64to64rr | |
| { 1257, 2, 1, 0, 0, "MMX_MOVDQ2Qrr", 0, 0x1ac004b05ULL, NULL, NULL, OperandInfo146 }, // Inst #1257 = MMX_MOVDQ2Qrr | |
| { 1258, 2, 1, 0, 0, "MMX_MOVFR642Qrr", 0|(1<<MCID::UnmodeledSideEffects), 0x1ac004b05ULL, NULL, NULL, OperandInfo155 }, // Inst #1258 = MMX_MOVFR642Qrr | |
| { 1259, 6, 0, 0, 0, "MMX_MOVNTQmr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1ce000104ULL, NULL, NULL, OperandInfo152 }, // Inst #1259 = MMX_MOVNTQmr | |
| { 1260, 2, 1, 0, 0, "MMX_MOVQ2DQrr", 0, 0x1ac004c05ULL, NULL, NULL, OperandInfo147 }, // Inst #1260 = MMX_MOVQ2DQrr | |
| { 1261, 2, 1, 0, 0, "MMX_MOVQ2FR64rr", 0, 0x1ac004c05ULL, NULL, NULL, OperandInfo156 }, // Inst #1261 = MMX_MOVQ2FR64rr | |
| { 1262, 6, 0, 0, 0, "MMX_MOVQ64mr", 0|(1<<MCID::MayStore), 0xfe000104ULL, NULL, NULL, OperandInfo152 }, // Inst #1262 = MMX_MOVQ64mr | |
| { 1263, 6, 1, 0, 0, "MMX_MOVQ64rm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad), 0xde000106ULL, NULL, NULL, OperandInfo145 }, // Inst #1263 = MMX_MOVQ64rm | |
| { 1264, 2, 1, 0, 0, "MMX_MOVQ64rr", 0, 0xde000105ULL, NULL, NULL, OperandInfo149 }, // Inst #1264 = MMX_MOVQ64rr | |
| { 1265, 6, 1, 0, 0, "MMX_MOVZDI2PDIrm", 0|(1<<MCID::MayLoad), 0xdc000106ULL, NULL, NULL, OperandInfo145 }, // Inst #1265 = MMX_MOVZDI2PDIrm | |
| { 1266, 2, 1, 0, 0, "MMX_MOVZDI2PDIrr", 0, 0xdc000105ULL, NULL, NULL, OperandInfo153 }, // Inst #1266 = MMX_MOVZDI2PDIrr | |
| { 1267, 6, 1, 0, 0, "MMX_PABSBrm64", 0|(1<<MCID::MayLoad), 0x39804d06ULL, NULL, NULL, OperandInfo145 }, // Inst #1267 = MMX_PABSBrm64 | |
| { 1268, 2, 1, 0, 0, "MMX_PABSBrr64", 0, 0x39804d05ULL, NULL, NULL, OperandInfo149 }, // Inst #1268 = MMX_PABSBrr64 | |
| { 1269, 6, 1, 0, 0, "MMX_PABSDrm64", 0|(1<<MCID::MayLoad), 0x3d804d06ULL, NULL, NULL, OperandInfo145 }, // Inst #1269 = MMX_PABSDrm64 | |
| { 1270, 2, 1, 0, 0, "MMX_PABSDrr64", 0, 0x3d804d05ULL, NULL, NULL, OperandInfo149 }, // Inst #1270 = MMX_PABSDrr64 | |
| { 1271, 6, 1, 0, 0, "MMX_PABSWrm64", 0|(1<<MCID::MayLoad), 0x3b804d06ULL, NULL, NULL, OperandInfo145 }, // Inst #1271 = MMX_PABSWrm64 | |
| { 1272, 2, 1, 0, 0, "MMX_PABSWrr64", 0, 0x3b804d05ULL, NULL, NULL, OperandInfo149 }, // Inst #1272 = MMX_PABSWrr64 | |
| { 1273, 7, 1, 0, 0, "MMX_PACKSSDWirm", 0|(1<<MCID::MayLoad), 0xd6000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1273 = MMX_PACKSSDWirm | |
| { 1274, 3, 1, 0, 0, "MMX_PACKSSDWirr", 0, 0xd6000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1274 = MMX_PACKSSDWirr | |
| { 1275, 7, 1, 0, 0, "MMX_PACKSSWBirm", 0|(1<<MCID::MayLoad), 0xc6000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1275 = MMX_PACKSSWBirm | |
| { 1276, 3, 1, 0, 0, "MMX_PACKSSWBirr", 0, 0xc6000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1276 = MMX_PACKSSWBirr | |
| { 1277, 7, 1, 0, 0, "MMX_PACKUSWBirm", 0|(1<<MCID::MayLoad), 0xce000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1277 = MMX_PACKUSWBirm | |
| { 1278, 3, 1, 0, 0, "MMX_PACKUSWBirr", 0, 0xce000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1278 = MMX_PACKUSWBirr | |
| { 1279, 7, 1, 0, 0, "MMX_PADDBirm", 0|(1<<MCID::MayLoad), 0x1f8000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1279 = MMX_PADDBirm | |
| { 1280, 3, 1, 0, 0, "MMX_PADDBirr", 0|(1<<MCID::Commutable), 0x1f8000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1280 = MMX_PADDBirr | |
| { 1281, 7, 1, 0, 0, "MMX_PADDDirm", 0|(1<<MCID::MayLoad), 0x1fc000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1281 = MMX_PADDDirm | |
| { 1282, 3, 1, 0, 0, "MMX_PADDDirr", 0|(1<<MCID::Commutable), 0x1fc000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1282 = MMX_PADDDirr | |
| { 1283, 7, 1, 0, 0, "MMX_PADDQirm", 0|(1<<MCID::MayLoad), 0x1a8000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1283 = MMX_PADDQirm | |
| { 1284, 3, 1, 0, 0, "MMX_PADDQirr", 0|(1<<MCID::Commutable), 0x1a8000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1284 = MMX_PADDQirr | |
| { 1285, 7, 1, 0, 0, "MMX_PADDSBirm", 0|(1<<MCID::MayLoad), 0x1d8000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1285 = MMX_PADDSBirm | |
| { 1286, 3, 1, 0, 0, "MMX_PADDSBirr", 0|(1<<MCID::Commutable), 0x1d8000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1286 = MMX_PADDSBirr | |
| { 1287, 7, 1, 0, 0, "MMX_PADDSWirm", 0|(1<<MCID::MayLoad), 0x1da000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1287 = MMX_PADDSWirm | |
| { 1288, 3, 1, 0, 0, "MMX_PADDSWirr", 0|(1<<MCID::Commutable), 0x1da000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1288 = MMX_PADDSWirr | |
| { 1289, 7, 1, 0, 0, "MMX_PADDUSBirm", 0|(1<<MCID::MayLoad), 0x1b8000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1289 = MMX_PADDUSBirm | |
| { 1290, 3, 1, 0, 0, "MMX_PADDUSBirr", 0|(1<<MCID::Commutable), 0x1b8000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1290 = MMX_PADDUSBirr | |
| { 1291, 7, 1, 0, 0, "MMX_PADDUSWirm", 0|(1<<MCID::MayLoad), 0x1ba000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1291 = MMX_PADDUSWirm | |
| { 1292, 3, 1, 0, 0, "MMX_PADDUSWirr", 0|(1<<MCID::Commutable), 0x1ba000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1292 = MMX_PADDUSWirr | |
| { 1293, 7, 1, 0, 0, "MMX_PADDWirm", 0|(1<<MCID::MayLoad), 0x1fa000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1293 = MMX_PADDWirm | |
| { 1294, 3, 1, 0, 0, "MMX_PADDWirr", 0|(1<<MCID::Commutable), 0x1fa000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1294 = MMX_PADDWirr | |
| { 1295, 8, 1, 0, 0, "MMX_PALIGNR64irm", 0|(1<<MCID::MayLoad), 0x1f804e06ULL, NULL, NULL, OperandInfo159 }, // Inst #1295 = MMX_PALIGNR64irm | |
| { 1296, 4, 1, 0, 0, "MMX_PALIGNR64irr", 0, 0x1f804e05ULL, NULL, NULL, OperandInfo160 }, // Inst #1296 = MMX_PALIGNR64irr | |
| { 1297, 7, 1, 0, 0, "MMX_PANDNirm", 0|(1<<MCID::MayLoad), 0x1be000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1297 = MMX_PANDNirm | |
| { 1298, 3, 1, 0, 0, "MMX_PANDNirr", 0, 0x1be000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1298 = MMX_PANDNirr | |
| { 1299, 7, 1, 0, 0, "MMX_PANDirm", 0|(1<<MCID::MayLoad), 0x1b6000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1299 = MMX_PANDirm | |
| { 1300, 3, 1, 0, 0, "MMX_PANDirr", 0|(1<<MCID::Commutable), 0x1b6000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1300 = MMX_PANDirr | |
| { 1301, 7, 1, 0, 0, "MMX_PAVGBirm", 0|(1<<MCID::MayLoad), 0x1c0000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1301 = MMX_PAVGBirm | |
| { 1302, 3, 1, 0, 0, "MMX_PAVGBirr", 0|(1<<MCID::Commutable), 0x1c0000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1302 = MMX_PAVGBirr | |
| { 1303, 7, 1, 0, 0, "MMX_PAVGWirm", 0|(1<<MCID::MayLoad), 0x1c6000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1303 = MMX_PAVGWirm | |
| { 1304, 3, 1, 0, 0, "MMX_PAVGWirr", 0|(1<<MCID::Commutable), 0x1c6000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1304 = MMX_PAVGWirr | |
| { 1305, 7, 1, 0, 0, "MMX_PCMPEQBirm", 0|(1<<MCID::MayLoad), 0xe8000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1305 = MMX_PCMPEQBirm | |
| { 1306, 3, 1, 0, 0, "MMX_PCMPEQBirr", 0, 0xe8000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1306 = MMX_PCMPEQBirr | |
| { 1307, 7, 1, 0, 0, "MMX_PCMPEQDirm", 0|(1<<MCID::MayLoad), 0xec000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1307 = MMX_PCMPEQDirm | |
| { 1308, 3, 1, 0, 0, "MMX_PCMPEQDirr", 0, 0xec000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1308 = MMX_PCMPEQDirr | |
| { 1309, 7, 1, 0, 0, "MMX_PCMPEQWirm", 0|(1<<MCID::MayLoad), 0xea000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1309 = MMX_PCMPEQWirm | |
| { 1310, 3, 1, 0, 0, "MMX_PCMPEQWirr", 0, 0xea000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1310 = MMX_PCMPEQWirr | |
| { 1311, 7, 1, 0, 0, "MMX_PCMPGTBirm", 0|(1<<MCID::MayLoad), 0xc8000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1311 = MMX_PCMPGTBirm | |
| { 1312, 3, 1, 0, 0, "MMX_PCMPGTBirr", 0, 0xc8000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1312 = MMX_PCMPGTBirr | |
| { 1313, 7, 1, 0, 0, "MMX_PCMPGTDirm", 0|(1<<MCID::MayLoad), 0xcc000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1313 = MMX_PCMPGTDirm | |
| { 1314, 3, 1, 0, 0, "MMX_PCMPGTDirr", 0, 0xcc000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1314 = MMX_PCMPGTDirr | |
| { 1315, 7, 1, 0, 0, "MMX_PCMPGTWirm", 0|(1<<MCID::MayLoad), 0xca000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1315 = MMX_PCMPGTWirm | |
| { 1316, 3, 1, 0, 0, "MMX_PCMPGTWirr", 0, 0xca000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1316 = MMX_PCMPGTWirr | |
| { 1317, 3, 1, 0, 0, "MMX_PEXTRWirri", 0, 0x18a004105ULL, NULL, NULL, OperandInfo161 }, // Inst #1317 = MMX_PEXTRWirri | |
| { 1318, 7, 1, 0, 0, "MMX_PHADDSWrm64", 0|(1<<MCID::MayLoad), 0x7800d06ULL, NULL, NULL, OperandInfo157 }, // Inst #1318 = MMX_PHADDSWrm64 | |
| { 1319, 3, 1, 0, 0, "MMX_PHADDSWrr64", 0, 0x7800d05ULL, NULL, NULL, OperandInfo158 }, // Inst #1319 = MMX_PHADDSWrr64 | |
| { 1320, 7, 1, 0, 0, "MMX_PHADDWrm64", 0|(1<<MCID::MayLoad), 0x3800d06ULL, NULL, NULL, OperandInfo157 }, // Inst #1320 = MMX_PHADDWrm64 | |
| { 1321, 3, 1, 0, 0, "MMX_PHADDWrr64", 0, 0x3800d05ULL, NULL, NULL, OperandInfo158 }, // Inst #1321 = MMX_PHADDWrr64 | |
| { 1322, 7, 1, 0, 0, "MMX_PHADDrm64", 0|(1<<MCID::MayLoad), 0x5800d06ULL, NULL, NULL, OperandInfo157 }, // Inst #1322 = MMX_PHADDrm64 | |
| { 1323, 3, 1, 0, 0, "MMX_PHADDrr64", 0, 0x5800d05ULL, NULL, NULL, OperandInfo158 }, // Inst #1323 = MMX_PHADDrr64 | |
| { 1324, 7, 1, 0, 0, "MMX_PHSUBDrm64", 0|(1<<MCID::MayLoad), 0xd800d06ULL, NULL, NULL, OperandInfo157 }, // Inst #1324 = MMX_PHSUBDrm64 | |
| { 1325, 3, 1, 0, 0, "MMX_PHSUBDrr64", 0, 0xd800d05ULL, NULL, NULL, OperandInfo158 }, // Inst #1325 = MMX_PHSUBDrr64 | |
| { 1326, 7, 1, 0, 0, "MMX_PHSUBSWrm64", 0|(1<<MCID::MayLoad), 0xf800d06ULL, NULL, NULL, OperandInfo157 }, // Inst #1326 = MMX_PHSUBSWrm64 | |
| { 1327, 3, 1, 0, 0, "MMX_PHSUBSWrr64", 0, 0xf800d05ULL, NULL, NULL, OperandInfo158 }, // Inst #1327 = MMX_PHSUBSWrr64 | |
| { 1328, 7, 1, 0, 0, "MMX_PHSUBWrm64", 0|(1<<MCID::MayLoad), 0xb800d06ULL, NULL, NULL, OperandInfo157 }, // Inst #1328 = MMX_PHSUBWrm64 | |
| { 1329, 3, 1, 0, 0, "MMX_PHSUBWrr64", 0, 0xb800d05ULL, NULL, NULL, OperandInfo158 }, // Inst #1329 = MMX_PHSUBWrr64 | |
| { 1330, 8, 1, 0, 0, "MMX_PINSRWirmi", 0|(1<<MCID::MayLoad), 0x188004106ULL, NULL, NULL, OperandInfo159 }, // Inst #1330 = MMX_PINSRWirmi | |
| { 1331, 4, 1, 0, 0, "MMX_PINSRWirri", 0, 0x188004105ULL, NULL, NULL, OperandInfo162 }, // Inst #1331 = MMX_PINSRWirri | |
| { 1332, 7, 1, 0, 0, "MMX_PMADDUBSWrm64", 0|(1<<MCID::MayLoad), 0x9800d06ULL, NULL, NULL, OperandInfo157 }, // Inst #1332 = MMX_PMADDUBSWrm64 | |
| { 1333, 3, 1, 0, 0, "MMX_PMADDUBSWrr64", 0, 0x9800d05ULL, NULL, NULL, OperandInfo158 }, // Inst #1333 = MMX_PMADDUBSWrr64 | |
| { 1334, 7, 1, 0, 0, "MMX_PMADDWDirm", 0|(1<<MCID::MayLoad), 0x1ea000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1334 = MMX_PMADDWDirm | |
| { 1335, 3, 1, 0, 0, "MMX_PMADDWDirr", 0|(1<<MCID::Commutable), 0x1ea000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1335 = MMX_PMADDWDirr | |
| { 1336, 7, 1, 0, 0, "MMX_PMAXSWirm", 0|(1<<MCID::MayLoad), 0x1dc000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1336 = MMX_PMAXSWirm | |
| { 1337, 3, 1, 0, 0, "MMX_PMAXSWirr", 0|(1<<MCID::Commutable), 0x1dc000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1337 = MMX_PMAXSWirr | |
| { 1338, 7, 1, 0, 0, "MMX_PMAXUBirm", 0|(1<<MCID::MayLoad), 0x1bc000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1338 = MMX_PMAXUBirm | |
| { 1339, 3, 1, 0, 0, "MMX_PMAXUBirr", 0|(1<<MCID::Commutable), 0x1bc000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1339 = MMX_PMAXUBirr | |
| { 1340, 7, 1, 0, 0, "MMX_PMINSWirm", 0|(1<<MCID::MayLoad), 0x1d4000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1340 = MMX_PMINSWirm | |
| { 1341, 3, 1, 0, 0, "MMX_PMINSWirr", 0|(1<<MCID::Commutable), 0x1d4000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1341 = MMX_PMINSWirr | |
| { 1342, 7, 1, 0, 0, "MMX_PMINUBirm", 0|(1<<MCID::MayLoad), 0x1b4000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1342 = MMX_PMINUBirm | |
| { 1343, 3, 1, 0, 0, "MMX_PMINUBirr", 0|(1<<MCID::Commutable), 0x1b4000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1343 = MMX_PMINUBirr | |
| { 1344, 2, 1, 0, 0, "MMX_PMOVMSKBrr", 0, 0x1ae000105ULL, NULL, NULL, OperandInfo151 }, // Inst #1344 = MMX_PMOVMSKBrr | |
| { 1345, 7, 1, 0, 0, "MMX_PMULHRSWrm64", 0|(1<<MCID::MayLoad)|(1<<MCID::Commutable), 0x17800d06ULL, NULL, NULL, OperandInfo157 }, // Inst #1345 = MMX_PMULHRSWrm64 | |
| { 1346, 3, 1, 0, 0, "MMX_PMULHRSWrr64", 0|(1<<MCID::Commutable), 0x17800d05ULL, NULL, NULL, OperandInfo158 }, // Inst #1346 = MMX_PMULHRSWrr64 | |
| { 1347, 7, 1, 0, 0, "MMX_PMULHUWirm", 0|(1<<MCID::MayLoad), 0x1c8000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1347 = MMX_PMULHUWirm | |
| { 1348, 3, 1, 0, 0, "MMX_PMULHUWirr", 0|(1<<MCID::Commutable), 0x1c8000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1348 = MMX_PMULHUWirr | |
| { 1349, 7, 1, 0, 0, "MMX_PMULHWirm", 0|(1<<MCID::MayLoad), 0x1ca000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1349 = MMX_PMULHWirm | |
| { 1350, 3, 1, 0, 0, "MMX_PMULHWirr", 0|(1<<MCID::Commutable), 0x1ca000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1350 = MMX_PMULHWirr | |
| { 1351, 7, 1, 0, 0, "MMX_PMULLWirm", 0|(1<<MCID::MayLoad), 0x1aa000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1351 = MMX_PMULLWirm | |
| { 1352, 3, 1, 0, 0, "MMX_PMULLWirr", 0|(1<<MCID::Commutable), 0x1aa000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1352 = MMX_PMULLWirr | |
| { 1353, 7, 1, 0, 0, "MMX_PMULUDQirm", 0|(1<<MCID::MayLoad), 0x1e8000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1353 = MMX_PMULUDQirm | |
| { 1354, 3, 1, 0, 0, "MMX_PMULUDQirr", 0|(1<<MCID::Commutable), 0x1e8000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1354 = MMX_PMULUDQirr | |
| { 1355, 7, 1, 0, 0, "MMX_PORirm", 0|(1<<MCID::MayLoad), 0x1d6000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1355 = MMX_PORirm | |
| { 1356, 3, 1, 0, 0, "MMX_PORirr", 0|(1<<MCID::Commutable), 0x1d6000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1356 = MMX_PORirr | |
| { 1357, 7, 1, 0, 0, "MMX_PSADBWirm", 0|(1<<MCID::MayLoad), 0x1ec000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1357 = MMX_PSADBWirm | |
| { 1358, 3, 1, 0, 0, "MMX_PSADBWirr", 0|(1<<MCID::Commutable), 0x1ec000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1358 = MMX_PSADBWirr | |
| { 1359, 7, 1, 0, 0, "MMX_PSHUFBrm64", 0|(1<<MCID::MayLoad), 0x1800d06ULL, NULL, NULL, OperandInfo157 }, // Inst #1359 = MMX_PSHUFBrm64 | |
| { 1360, 3, 1, 0, 0, "MMX_PSHUFBrr64", 0, 0x1800d05ULL, NULL, NULL, OperandInfo158 }, // Inst #1360 = MMX_PSHUFBrr64 | |
| { 1361, 7, 1, 0, 0, "MMX_PSHUFWmi", 0|(1<<MCID::MayLoad), 0xe0004106ULL, NULL, NULL, OperandInfo163 }, // Inst #1361 = MMX_PSHUFWmi | |
| { 1362, 3, 1, 0, 0, "MMX_PSHUFWri", 0, 0xe0004105ULL, NULL, NULL, OperandInfo164 }, // Inst #1362 = MMX_PSHUFWri | |
| { 1363, 7, 1, 0, 0, "MMX_PSIGNBrm64", 0|(1<<MCID::MayLoad), 0x11800d06ULL, NULL, NULL, OperandInfo157 }, // Inst #1363 = MMX_PSIGNBrm64 | |
| { 1364, 3, 1, 0, 0, "MMX_PSIGNBrr64", 0, 0x11800d05ULL, NULL, NULL, OperandInfo158 }, // Inst #1364 = MMX_PSIGNBrr64 | |
| { 1365, 7, 1, 0, 0, "MMX_PSIGNDrm64", 0|(1<<MCID::MayLoad), 0x15800d06ULL, NULL, NULL, OperandInfo157 }, // Inst #1365 = MMX_PSIGNDrm64 | |
| { 1366, 3, 1, 0, 0, "MMX_PSIGNDrr64", 0, 0x15800d05ULL, NULL, NULL, OperandInfo158 }, // Inst #1366 = MMX_PSIGNDrr64 | |
| { 1367, 7, 1, 0, 0, "MMX_PSIGNWrm64", 0|(1<<MCID::MayLoad), 0x13800d06ULL, NULL, NULL, OperandInfo157 }, // Inst #1367 = MMX_PSIGNWrm64 | |
| { 1368, 3, 1, 0, 0, "MMX_PSIGNWrr64", 0, 0x13800d05ULL, NULL, NULL, OperandInfo158 }, // Inst #1368 = MMX_PSIGNWrr64 | |
| { 1369, 3, 1, 0, 0, "MMX_PSLLDri", 0, 0xe4004116ULL, NULL, NULL, OperandInfo165 }, // Inst #1369 = MMX_PSLLDri | |
| { 1370, 7, 1, 0, 0, "MMX_PSLLDrm", 0|(1<<MCID::MayLoad), 0x1e4000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1370 = MMX_PSLLDrm | |
| { 1371, 3, 1, 0, 0, "MMX_PSLLDrr", 0, 0x1e4000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1371 = MMX_PSLLDrr | |
| { 1372, 3, 1, 0, 0, "MMX_PSLLQri", 0, 0xe6004116ULL, NULL, NULL, OperandInfo165 }, // Inst #1372 = MMX_PSLLQri | |
| { 1373, 7, 1, 0, 0, "MMX_PSLLQrm", 0|(1<<MCID::MayLoad), 0x1e6000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1373 = MMX_PSLLQrm | |
| { 1374, 3, 1, 0, 0, "MMX_PSLLQrr", 0, 0x1e6000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1374 = MMX_PSLLQrr | |
| { 1375, 3, 1, 0, 0, "MMX_PSLLWri", 0, 0xe2004116ULL, NULL, NULL, OperandInfo165 }, // Inst #1375 = MMX_PSLLWri | |
| { 1376, 7, 1, 0, 0, "MMX_PSLLWrm", 0|(1<<MCID::MayLoad), 0x1e2000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1376 = MMX_PSLLWrm | |
| { 1377, 3, 1, 0, 0, "MMX_PSLLWrr", 0, 0x1e2000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1377 = MMX_PSLLWrr | |
| { 1378, 3, 1, 0, 0, "MMX_PSRADri", 0, 0xe4004114ULL, NULL, NULL, OperandInfo165 }, // Inst #1378 = MMX_PSRADri | |
| { 1379, 7, 1, 0, 0, "MMX_PSRADrm", 0|(1<<MCID::MayLoad), 0x1c4000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1379 = MMX_PSRADrm | |
| { 1380, 3, 1, 0, 0, "MMX_PSRADrr", 0, 0x1c4000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1380 = MMX_PSRADrr | |
| { 1381, 3, 1, 0, 0, "MMX_PSRAWri", 0, 0xe2004114ULL, NULL, NULL, OperandInfo165 }, // Inst #1381 = MMX_PSRAWri | |
| { 1382, 7, 1, 0, 0, "MMX_PSRAWrm", 0|(1<<MCID::MayLoad), 0x1c2000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1382 = MMX_PSRAWrm | |
| { 1383, 3, 1, 0, 0, "MMX_PSRAWrr", 0, 0x1c2000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1383 = MMX_PSRAWrr | |
| { 1384, 3, 1, 0, 0, "MMX_PSRLDri", 0, 0xe4004112ULL, NULL, NULL, OperandInfo165 }, // Inst #1384 = MMX_PSRLDri | |
| { 1385, 7, 1, 0, 0, "MMX_PSRLDrm", 0|(1<<MCID::MayLoad), 0x1a4000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1385 = MMX_PSRLDrm | |
| { 1386, 3, 1, 0, 0, "MMX_PSRLDrr", 0, 0x1a4000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1386 = MMX_PSRLDrr | |
| { 1387, 3, 1, 0, 0, "MMX_PSRLQri", 0, 0xe6004112ULL, NULL, NULL, OperandInfo165 }, // Inst #1387 = MMX_PSRLQri | |
| { 1388, 7, 1, 0, 0, "MMX_PSRLQrm", 0|(1<<MCID::MayLoad), 0x1a6000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1388 = MMX_PSRLQrm | |
| { 1389, 3, 1, 0, 0, "MMX_PSRLQrr", 0, 0x1a6000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1389 = MMX_PSRLQrr | |
| { 1390, 3, 1, 0, 0, "MMX_PSRLWri", 0, 0xe2004112ULL, NULL, NULL, OperandInfo165 }, // Inst #1390 = MMX_PSRLWri | |
| { 1391, 7, 1, 0, 0, "MMX_PSRLWrm", 0|(1<<MCID::MayLoad), 0x1a2000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1391 = MMX_PSRLWrm | |
| { 1392, 3, 1, 0, 0, "MMX_PSRLWrr", 0, 0x1a2000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1392 = MMX_PSRLWrr | |
| { 1393, 7, 1, 0, 0, "MMX_PSUBBirm", 0|(1<<MCID::MayLoad), 0x1f0000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1393 = MMX_PSUBBirm | |
| { 1394, 3, 1, 0, 0, "MMX_PSUBBirr", 0, 0x1f0000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1394 = MMX_PSUBBirr | |
| { 1395, 7, 1, 0, 0, "MMX_PSUBDirm", 0|(1<<MCID::MayLoad), 0x1f4000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1395 = MMX_PSUBDirm | |
| { 1396, 3, 1, 0, 0, "MMX_PSUBDirr", 0, 0x1f4000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1396 = MMX_PSUBDirr | |
| { 1397, 7, 1, 0, 0, "MMX_PSUBQirm", 0|(1<<MCID::MayLoad), 0x1f6000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1397 = MMX_PSUBQirm | |
| { 1398, 3, 1, 0, 0, "MMX_PSUBQirr", 0, 0x1f6000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1398 = MMX_PSUBQirr | |
| { 1399, 7, 1, 0, 0, "MMX_PSUBSBirm", 0|(1<<MCID::MayLoad), 0x1d0000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1399 = MMX_PSUBSBirm | |
| { 1400, 3, 1, 0, 0, "MMX_PSUBSBirr", 0, 0x1d0000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1400 = MMX_PSUBSBirr | |
| { 1401, 7, 1, 0, 0, "MMX_PSUBSWirm", 0|(1<<MCID::MayLoad), 0x1d2000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1401 = MMX_PSUBSWirm | |
| { 1402, 3, 1, 0, 0, "MMX_PSUBSWirr", 0, 0x1d2000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1402 = MMX_PSUBSWirr | |
| { 1403, 7, 1, 0, 0, "MMX_PSUBUSBirm", 0|(1<<MCID::MayLoad), 0x1b0000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1403 = MMX_PSUBUSBirm | |
| { 1404, 3, 1, 0, 0, "MMX_PSUBUSBirr", 0, 0x1b0000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1404 = MMX_PSUBUSBirr | |
| { 1405, 7, 1, 0, 0, "MMX_PSUBUSWirm", 0|(1<<MCID::MayLoad), 0x1b2000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1405 = MMX_PSUBUSWirm | |
| { 1406, 3, 1, 0, 0, "MMX_PSUBUSWirr", 0, 0x1b2000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1406 = MMX_PSUBUSWirr | |
| { 1407, 7, 1, 0, 0, "MMX_PSUBWirm", 0|(1<<MCID::MayLoad), 0x1f2000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1407 = MMX_PSUBWirm | |
| { 1408, 3, 1, 0, 0, "MMX_PSUBWirr", 0, 0x1f2000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1408 = MMX_PSUBWirr | |
| { 1409, 7, 1, 0, 0, "MMX_PUNPCKHBWirm", 0|(1<<MCID::MayLoad), 0xd0000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1409 = MMX_PUNPCKHBWirm | |
| { 1410, 3, 1, 0, 0, "MMX_PUNPCKHBWirr", 0, 0xd0000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1410 = MMX_PUNPCKHBWirr | |
| { 1411, 7, 1, 0, 0, "MMX_PUNPCKHDQirm", 0|(1<<MCID::MayLoad), 0xd4000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1411 = MMX_PUNPCKHDQirm | |
| { 1412, 3, 1, 0, 0, "MMX_PUNPCKHDQirr", 0, 0xd4000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1412 = MMX_PUNPCKHDQirr | |
| { 1413, 7, 1, 0, 0, "MMX_PUNPCKHWDirm", 0|(1<<MCID::MayLoad), 0xd2000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1413 = MMX_PUNPCKHWDirm | |
| { 1414, 3, 1, 0, 0, "MMX_PUNPCKHWDirr", 0, 0xd2000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1414 = MMX_PUNPCKHWDirr | |
| { 1415, 7, 1, 0, 0, "MMX_PUNPCKLBWirm", 0|(1<<MCID::MayLoad), 0xc0000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1415 = MMX_PUNPCKLBWirm | |
| { 1416, 3, 1, 0, 0, "MMX_PUNPCKLBWirr", 0, 0xc0000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1416 = MMX_PUNPCKLBWirr | |
| { 1417, 7, 1, 0, 0, "MMX_PUNPCKLDQirm", 0|(1<<MCID::MayLoad), 0xc4000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1417 = MMX_PUNPCKLDQirm | |
| { 1418, 3, 1, 0, 0, "MMX_PUNPCKLDQirr", 0, 0xc4000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1418 = MMX_PUNPCKLDQirr | |
| { 1419, 7, 1, 0, 0, "MMX_PUNPCKLWDirm", 0|(1<<MCID::MayLoad), 0xc2000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1419 = MMX_PUNPCKLWDirm | |
| { 1420, 3, 1, 0, 0, "MMX_PUNPCKLWDirr", 0, 0xc2000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1420 = MMX_PUNPCKLWDirr | |
| { 1421, 7, 1, 0, 0, "MMX_PXORirm", 0|(1<<MCID::MayLoad), 0x1de000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1421 = MMX_PXORirm | |
| { 1422, 3, 1, 0, 0, "MMX_PXORirr", 0|(1<<MCID::Commutable), 0x1de000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1422 = MMX_PXORirr | |
| { 1423, 7, 0, 0, 0, "MONITOR", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166 }, // Inst #1423 = MONITOR | |
| { 1424, 0, 0, 0, 0, "MONITORrrr", 0|(1<<MCID::UnmodeledSideEffects), 0x2000125ULL, ImplicitList36, NULL, 0 }, // Inst #1424 = MONITORrrr | |
| { 1425, 0, 0, 0, 0, "MONTMUL", 0|(1<<MCID::UnmodeledSideEffects), 0x180000f01ULL, ImplicitList37, ImplicitList38, 0 }, // Inst #1425 = MONTMUL | |
| { 1426, 1, 1, 0, 0, "MOV16ao16", 0|(1<<MCID::UnmodeledSideEffects), 0x146014041ULL, NULL, NULL, OperandInfo73 }, // Inst #1426 = MOV16ao16 | |
| { 1427, 6, 0, 0, 0, "MOV16mi", 0|(1<<MCID::MayStore), 0x18e00c058ULL, NULL, NULL, OperandInfo15 }, // Inst #1427 = MOV16mi | |
| { 1428, 6, 0, 0, 0, "MOV16mr", 0|(1<<MCID::MayStore), 0x112000044ULL, NULL, NULL, OperandInfo16 }, // Inst #1428 = MOV16mr | |
| { 1429, 6, 1, 0, 0, "MOV16ms", 0|(1<<MCID::UnmodeledSideEffects), 0x118000044ULL, NULL, NULL, OperandInfo167 }, // Inst #1429 = MOV16ms | |
| { 1430, 1, 0, 0, 0, "MOV16o16a", 0|(1<<MCID::UnmodeledSideEffects), 0x142014041ULL, NULL, NULL, OperandInfo73 }, // Inst #1430 = MOV16o16a | |
| { 1431, 1, 1, 0, 0, "MOV16r0", 0|(1<<MCID::Rematerializable)|(1<<MCID::CheapAsAMove), 0x62000060ULL, NULL, ImplicitList1, OperandInfo113 }, // Inst #1431 = MOV16r0 | |
| { 1432, 2, 1, 0, 0, "MOV16ri", 0|(1<<MCID::Rematerializable)|(1<<MCID::CheapAsAMove), 0x17000c042ULL, NULL, NULL, OperandInfo69 }, // Inst #1432 = MOV16ri | |
| { 1433, 6, 1, 0, 0, "MOV16rm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x116000046ULL, NULL, NULL, OperandInfo11 }, // Inst #1433 = MOV16rm | |
| { 1434, 2, 1, 0, 0, "MOV16rr", 0, 0x112000043ULL, NULL, NULL, OperandInfo55 }, // Inst #1434 = MOV16rr | |
| { 1435, 2, 1, 0, 0, "MOV16rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x116000045ULL, NULL, NULL, OperandInfo55 }, // Inst #1435 = MOV16rr_REV | |
| { 1436, 2, 1, 0, 0, "MOV16rs", 0|(1<<MCID::UnmodeledSideEffects), 0x118000043ULL, NULL, NULL, OperandInfo168 }, // Inst #1436 = MOV16rs | |
| { 1437, 6, 1, 0, 0, "MOV16sm", 0|(1<<MCID::UnmodeledSideEffects), 0x11c000046ULL, NULL, NULL, OperandInfo169 }, // Inst #1437 = MOV16sm | |
| { 1438, 2, 1, 0, 0, "MOV16sr", 0|(1<<MCID::UnmodeledSideEffects), 0x11c000045ULL, NULL, NULL, OperandInfo170 }, // Inst #1438 = MOV16sr | |
| { 1439, 1, 1, 0, 0, "MOV32ao32", 0|(1<<MCID::UnmodeledSideEffects), 0x146014001ULL, NULL, NULL, OperandInfo73 }, // Inst #1439 = MOV32ao32 | |
| { 1440, 2, 1, 0, 0, "MOV32cr", 0|(1<<MCID::UnmodeledSideEffects), 0x44000105ULL, NULL, NULL, OperandInfo171 }, // Inst #1440 = MOV32cr | |
| { 1441, 2, 1, 0, 0, "MOV32dr", 0|(1<<MCID::UnmodeledSideEffects), 0x46000105ULL, NULL, NULL, OperandInfo172 }, // Inst #1441 = MOV32dr | |
| { 1442, 6, 0, 0, 0, "MOV32mi", 0|(1<<MCID::MayStore), 0x18e014018ULL, NULL, NULL, OperandInfo15 }, // Inst #1442 = MOV32mi | |
| { 1443, 6, 0, 0, 0, "MOV32mr", 0|(1<<MCID::MayStore), 0x112000004ULL, NULL, NULL, OperandInfo20 }, // Inst #1443 = MOV32mr | |
| { 1444, 6, 1, 0, 0, "MOV32ms", 0|(1<<MCID::UnmodeledSideEffects), 0x118000004ULL, NULL, NULL, OperandInfo167 }, // Inst #1444 = MOV32ms | |
| { 1445, 1, 0, 0, 0, "MOV32o32a", 0|(1<<MCID::UnmodeledSideEffects), 0x142014001ULL, NULL, NULL, OperandInfo73 }, // Inst #1445 = MOV32o32a | |
| { 1446, 1, 1, 0, 0, "MOV32r0", 0|(1<<MCID::Rematerializable)|(1<<MCID::CheapAsAMove), 0x62000020ULL, NULL, ImplicitList1, OperandInfo72 }, // Inst #1446 = MOV32r0 | |
| { 1447, 2, 1, 0, 0, "MOV32rc", 0|(1<<MCID::UnmodeledSideEffects), 0x40000103ULL, NULL, NULL, OperandInfo173 }, // Inst #1447 = MOV32rc | |
| { 1448, 2, 1, 0, 0, "MOV32rd", 0|(1<<MCID::UnmodeledSideEffects), 0x42000103ULL, NULL, NULL, OperandInfo174 }, // Inst #1448 = MOV32rd | |
| { 1449, 2, 1, 0, 0, "MOV32ri", 0|(1<<MCID::Rematerializable)|(1<<MCID::CheapAsAMove), 0x170014002ULL, NULL, NULL, OperandInfo70 }, // Inst #1449 = MOV32ri | |
| { 1450, 6, 1, 0, 0, "MOV32rm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x116000006ULL, NULL, NULL, OperandInfo12 }, // Inst #1450 = MOV32rm | |
| { 1451, 2, 1, 0, 0, "MOV32rr", 0, 0x112000003ULL, NULL, NULL, OperandInfo65 }, // Inst #1451 = MOV32rr | |
| { 1452, 2, 1, 0, 0, "MOV32rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x116000005ULL, NULL, NULL, OperandInfo65 }, // Inst #1452 = MOV32rr_REV | |
| { 1453, 2, 1, 0, 0, "MOV32rs", 0|(1<<MCID::UnmodeledSideEffects), 0x118000003ULL, NULL, NULL, OperandInfo175 }, // Inst #1453 = MOV32rs | |
| { 1454, 6, 1, 0, 0, "MOV32sm", 0|(1<<MCID::UnmodeledSideEffects), 0x11c000006ULL, NULL, NULL, OperandInfo169 }, // Inst #1454 = MOV32sm | |
| { 1455, 2, 1, 0, 0, "MOV32sr", 0|(1<<MCID::UnmodeledSideEffects), 0x11c000005ULL, NULL, NULL, OperandInfo176 }, // Inst #1455 = MOV32sr | |
| { 1456, 2, 1, 0, 0, "MOV64cr", 0|(1<<MCID::UnmodeledSideEffects), 0x44000105ULL, NULL, NULL, OperandInfo177 }, // Inst #1456 = MOV64cr | |
| { 1457, 2, 1, 0, 0, "MOV64dr", 0|(1<<MCID::UnmodeledSideEffects), 0x46000105ULL, NULL, NULL, OperandInfo178 }, // Inst #1457 = MOV64dr | |
| { 1458, 6, 0, 0, 0, "MOV64mi32", 0|(1<<MCID::MayStore), 0x18e016018ULL, NULL, NULL, OperandInfo15 }, // Inst #1458 = MOV64mi32 | |
| { 1459, 6, 0, 0, 0, "MOV64mr", 0|(1<<MCID::MayStore), 0x112002004ULL, NULL, NULL, OperandInfo24 }, // Inst #1459 = MOV64mr | |
| { 1460, 6, 1, 0, 0, "MOV64ms", 0|(1<<MCID::UnmodeledSideEffects), 0x118002004ULL, NULL, NULL, OperandInfo167 }, // Inst #1460 = MOV64ms | |
| { 1461, 1, 1, 0, 0, "MOV64r0", 0|(1<<MCID::Rematerializable)|(1<<MCID::CheapAsAMove), 0x62000020ULL, NULL, ImplicitList1, OperandInfo74 }, // Inst #1461 = MOV64r0 | |
| { 1462, 2, 1, 0, 0, "MOV64rc", 0|(1<<MCID::UnmodeledSideEffects), 0x40000103ULL, NULL, NULL, OperandInfo179 }, // Inst #1462 = MOV64rc | |
| { 1463, 2, 1, 0, 0, "MOV64rd", 0|(1<<MCID::UnmodeledSideEffects), 0x42000103ULL, NULL, NULL, OperandInfo180 }, // Inst #1463 = MOV64rd | |
| { 1464, 2, 1, 0, 0, "MOV64ri", 0|(1<<MCID::Rematerializable)|(1<<MCID::CheapAsAMove), 0x17001e002ULL, NULL, NULL, OperandInfo71 }, // Inst #1464 = MOV64ri | |
| { 1465, 2, 1, 0, 0, "MOV64ri32", 0|(1<<MCID::Rematerializable)|(1<<MCID::CheapAsAMove), 0x18e016010ULL, NULL, NULL, OperandInfo71 }, // Inst #1465 = MOV64ri32 | |
| { 1466, 2, 1, 0, 0, "MOV64ri64i32", 0|(1<<MCID::Rematerializable)|(1<<MCID::CheapAsAMove), 0x170014002ULL, NULL, NULL, OperandInfo71 }, // Inst #1466 = MOV64ri64i32 | |
| { 1467, 6, 1, 0, 0, "MOV64rm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x116002006ULL, NULL, NULL, OperandInfo13 }, // Inst #1467 = MOV64rm | |
| { 1468, 2, 1, 0, 0, "MOV64rr", 0, 0x112002003ULL, NULL, NULL, OperandInfo66 }, // Inst #1468 = MOV64rr | |
| { 1469, 2, 1, 0, 0, "MOV64rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x116002005ULL, NULL, NULL, OperandInfo66 }, // Inst #1469 = MOV64rr_REV | |
| { 1470, 2, 1, 0, 0, "MOV64rs", 0|(1<<MCID::UnmodeledSideEffects), 0x118002003ULL, NULL, NULL, OperandInfo181 }, // Inst #1470 = MOV64rs | |
| { 1471, 6, 1, 0, 0, "MOV64sm", 0|(1<<MCID::UnmodeledSideEffects), 0x11c002006ULL, NULL, NULL, OperandInfo169 }, // Inst #1471 = MOV64sm | |
| { 1472, 2, 1, 0, 0, "MOV64sr", 0|(1<<MCID::UnmodeledSideEffects), 0x11c002005ULL, NULL, NULL, OperandInfo182 }, // Inst #1472 = MOV64sr | |
| { 1473, 2, 1, 0, 0, "MOV64toPQIrr", 0, 0xdd002145ULL, NULL, NULL, OperandInfo183 }, // Inst #1473 = MOV64toPQIrr | |
| { 1474, 6, 1, 0, 0, "MOV64toSDrm", 0|(1<<MCID::MayLoad), 0xfc800c06ULL, NULL, NULL, OperandInfo101 }, // Inst #1474 = MOV64toSDrm | |
| { 1475, 2, 1, 0, 0, "MOV64toSDrr", 0|(1<<MCID::Bitcast), 0xdd002145ULL, NULL, NULL, OperandInfo102 }, // Inst #1475 = MOV64toSDrr | |
| { 1476, 1, 1, 0, 0, "MOV8ao8", 0|(1<<MCID::UnmodeledSideEffects), 0x144014001ULL, NULL, NULL, OperandInfo73 }, // Inst #1476 = MOV8ao8 | |
| { 1477, 6, 0, 0, 0, "MOV8mi", 0|(1<<MCID::MayStore), 0x18c004018ULL, NULL, NULL, OperandInfo15 }, // Inst #1477 = MOV8mi | |
| { 1478, 6, 0, 0, 0, "MOV8mr", 0|(1<<MCID::MayStore), 0x110000004ULL, NULL, NULL, OperandInfo28 }, // Inst #1478 = MOV8mr | |
| { 1479, 6, 0, 0, 0, "MOV8mr_NOREX", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x110000004ULL, NULL, NULL, OperandInfo184 }, // Inst #1479 = MOV8mr_NOREX | |
| { 1480, 1, 0, 0, 0, "MOV8o8a", 0|(1<<MCID::UnmodeledSideEffects), 0x140014001ULL, NULL, NULL, OperandInfo73 }, // Inst #1480 = MOV8o8a | |
| { 1481, 1, 1, 0, 0, "MOV8r0", 0|(1<<MCID::Rematerializable)|(1<<MCID::CheapAsAMove), 0x60000020ULL, NULL, ImplicitList1, OperandInfo114 }, // Inst #1481 = MOV8r0 | |
| { 1482, 2, 1, 0, 0, "MOV8ri", 0|(1<<MCID::Rematerializable)|(1<<MCID::CheapAsAMove), 0x160004002ULL, NULL, NULL, OperandInfo88 }, // Inst #1482 = MOV8ri | |
| { 1483, 6, 1, 0, 0, "MOV8rm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x114000006ULL, NULL, NULL, OperandInfo14 }, // Inst #1483 = MOV8rm | |
| { 1484, 6, 1, 0, 0, "MOV8rm_NOREX", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x114000006ULL, NULL, NULL, OperandInfo185 }, // Inst #1484 = MOV8rm_NOREX | |
| { 1485, 2, 1, 0, 0, "MOV8rr", 0, 0x110000003ULL, NULL, NULL, OperandInfo89 }, // Inst #1485 = MOV8rr | |
| { 1486, 2, 1, 0, 0, "MOV8rr_NOREX", 0, 0x110000003ULL, NULL, NULL, OperandInfo186 }, // Inst #1486 = MOV8rr_NOREX | |
| { 1487, 2, 1, 0, 0, "MOV8rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x114000005ULL, NULL, NULL, OperandInfo89 }, // Inst #1487 = MOV8rr_REV | |
| { 1488, 6, 0, 0, 0, "MOVAPDmr", 0|(1<<MCID::MayStore), 0x53000144ULL, NULL, NULL, OperandInfo187 }, // Inst #1488 = MOVAPDmr | |
| { 1489, 6, 1, 0, 0, "MOVAPDrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x51000146ULL, NULL, NULL, OperandInfo47 }, // Inst #1489 = MOVAPDrm | |
| { 1490, 2, 1, 0, 0, "MOVAPDrr", 0, 0x51000145ULL, NULL, NULL, OperandInfo48 }, // Inst #1490 = MOVAPDrr | |
| { 1491, 2, 1, 0, 0, "MOVAPDrr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x53000143ULL, NULL, NULL, OperandInfo48 }, // Inst #1491 = MOVAPDrr_REV | |
| { 1492, 6, 0, 0, 0, "MOVAPSmr", 0|(1<<MCID::MayStore), 0x52800104ULL, NULL, NULL, OperandInfo187 }, // Inst #1492 = MOVAPSmr | |
| { 1493, 6, 1, 0, 0, "MOVAPSrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x50800106ULL, NULL, NULL, OperandInfo47 }, // Inst #1493 = MOVAPSrm | |
| { 1494, 2, 1, 0, 0, "MOVAPSrr", 0, 0x50800105ULL, NULL, NULL, OperandInfo48 }, // Inst #1494 = MOVAPSrr | |
| { 1495, 2, 1, 0, 0, "MOVAPSrr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x52800103ULL, NULL, NULL, OperandInfo48 }, // Inst #1495 = MOVAPSrr_REV | |
| { 1496, 6, 0, 0, 0, "MOVBE16mr", 0|(1<<MCID::MayStore), 0x1e2000d44ULL, NULL, NULL, OperandInfo16 }, // Inst #1496 = MOVBE16mr | |
| { 1497, 6, 1, 0, 0, "MOVBE16rm", 0|(1<<MCID::MayLoad), 0x1e0000d46ULL, NULL, NULL, OperandInfo11 }, // Inst #1497 = MOVBE16rm | |
| { 1498, 6, 0, 0, 0, "MOVBE32mr", 0|(1<<MCID::MayStore), 0x1e2000d04ULL, NULL, NULL, OperandInfo20 }, // Inst #1498 = MOVBE32mr | |
| { 1499, 6, 1, 0, 0, "MOVBE32rm", 0|(1<<MCID::MayLoad), 0x1e0000d06ULL, NULL, NULL, OperandInfo12 }, // Inst #1499 = MOVBE32rm | |
| { 1500, 6, 0, 0, 0, "MOVBE64mr", 0|(1<<MCID::MayStore), 0x1e2002d04ULL, NULL, NULL, OperandInfo24 }, // Inst #1500 = MOVBE64mr | |
| { 1501, 6, 1, 0, 0, "MOVBE64rm", 0|(1<<MCID::MayLoad), 0x1e0002d06ULL, NULL, NULL, OperandInfo13 }, // Inst #1501 = MOVBE64rm | |
| { 1502, 6, 1, 0, 0, "MOVDDUPrm", 0|(1<<MCID::MayLoad), 0x25000b06ULL, NULL, NULL, OperandInfo47 }, // Inst #1502 = MOVDDUPrm | |
| { 1503, 2, 1, 0, 0, "MOVDDUPrr", 0, 0x25000b05ULL, NULL, NULL, OperandInfo48 }, // Inst #1503 = MOVDDUPrr | |
| { 1504, 6, 1, 0, 0, "MOVDI2PDIrm", 0|(1<<MCID::MayLoad), 0xdd000146ULL, NULL, NULL, OperandInfo47 }, // Inst #1504 = MOVDI2PDIrm | |
| { 1505, 2, 1, 0, 0, "MOVDI2PDIrr", 0, 0xdd000145ULL, NULL, NULL, OperandInfo188 }, // Inst #1505 = MOVDI2PDIrr | |
| { 1506, 6, 1, 0, 0, "MOVDI2SSrm", 0|(1<<MCID::MayLoad), 0xdd000146ULL, NULL, NULL, OperandInfo99 }, // Inst #1506 = MOVDI2SSrm | |
| { 1507, 2, 1, 0, 0, "MOVDI2SSrr", 0|(1<<MCID::Bitcast), 0xdd000145ULL, NULL, NULL, OperandInfo105 }, // Inst #1507 = MOVDI2SSrr | |
| { 1508, 6, 0, 0, 0, "MOVDQAmr", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0xff800144ULL, NULL, NULL, OperandInfo187 }, // Inst #1508 = MOVDQAmr | |
| { 1509, 6, 1, 0, 0, "MOVDQArm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0xdf800146ULL, NULL, NULL, OperandInfo47 }, // Inst #1509 = MOVDQArm | |
| { 1510, 2, 1, 0, 0, "MOVDQArr", 0, 0xdf800145ULL, NULL, NULL, OperandInfo48 }, // Inst #1510 = MOVDQArr | |
| { 1511, 2, 1, 0, 0, "MOVDQArr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0xff800143ULL, NULL, NULL, OperandInfo48 }, // Inst #1511 = MOVDQArr_REV | |
| { 1512, 6, 0, 0, 0, "MOVDQUmr", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0xff800c04ULL, NULL, NULL, OperandInfo187 }, // Inst #1512 = MOVDQUmr | |
| { 1513, 6, 0, 0, 0, "MOVDQUmr_Int", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0xff800c04ULL, NULL, NULL, OperandInfo187 }, // Inst #1513 = MOVDQUmr_Int | |
| { 1514, 6, 1, 0, 0, "MOVDQUrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0xdf800c06ULL, NULL, NULL, OperandInfo47 }, // Inst #1514 = MOVDQUrm | |
| { 1515, 2, 1, 0, 0, "MOVDQUrr", 0|(1<<MCID::UnmodeledSideEffects), 0xdf800c05ULL, NULL, NULL, OperandInfo48 }, // Inst #1515 = MOVDQUrr | |
| { 1516, 2, 1, 0, 0, "MOVDQUrr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0xff800c03ULL, NULL, NULL, OperandInfo48 }, // Inst #1516 = MOVDQUrr_REV | |
| { 1517, 3, 1, 0, 0, "MOVHLPSrr", 0, 0x24800105ULL, NULL, NULL, OperandInfo33 }, // Inst #1517 = MOVHLPSrr | |
| { 1518, 6, 0, 0, 0, "MOVHPDmr", 0|(1<<MCID::MayStore), 0x2f000144ULL, NULL, NULL, OperandInfo187 }, // Inst #1518 = MOVHPDmr | |
| { 1519, 7, 1, 0, 0, "MOVHPDrm", 0|(1<<MCID::MayLoad), 0x2d000146ULL, NULL, NULL, OperandInfo32 }, // Inst #1519 = MOVHPDrm | |
| { 1520, 6, 0, 0, 0, "MOVHPSmr", 0|(1<<MCID::MayStore), 0x2e800104ULL, NULL, NULL, OperandInfo187 }, // Inst #1520 = MOVHPSmr | |
| { 1521, 7, 1, 0, 0, "MOVHPSrm", 0|(1<<MCID::MayLoad), 0x2c800106ULL, NULL, NULL, OperandInfo32 }, // Inst #1521 = MOVHPSrm | |
| { 1522, 3, 1, 0, 0, "MOVLHPSrr", 0, 0x2c800105ULL, NULL, NULL, OperandInfo33 }, // Inst #1522 = MOVLHPSrr | |
| { 1523, 6, 0, 0, 0, "MOVLPDmr", 0|(1<<MCID::MayStore), 0x27000144ULL, NULL, NULL, OperandInfo187 }, // Inst #1523 = MOVLPDmr | |
| { 1524, 7, 1, 0, 0, "MOVLPDrm", 0|(1<<MCID::MayLoad), 0x25000146ULL, NULL, NULL, OperandInfo32 }, // Inst #1524 = MOVLPDrm | |
| { 1525, 6, 0, 0, 0, "MOVLPSmr", 0|(1<<MCID::MayStore), 0x26800104ULL, NULL, NULL, OperandInfo187 }, // Inst #1525 = MOVLPSmr | |
| { 1526, 7, 1, 0, 0, "MOVLPSrm", 0|(1<<MCID::MayLoad), 0x24800106ULL, NULL, NULL, OperandInfo32 }, // Inst #1526 = MOVLPSrm | |
| { 1527, 6, 0, 0, 0, "MOVLQ128mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1ad000144ULL, NULL, NULL, OperandInfo187 }, // Inst #1527 = MOVLQ128mr | |
| { 1528, 2, 1, 0, 0, "MOVMSKPDrr32", 0, 0xa1000145ULL, NULL, NULL, OperandInfo98 }, // Inst #1528 = MOVMSKPDrr32 | |
| { 1529, 2, 1, 0, 0, "MOVMSKPDrr64", 0|(1<<MCID::UnmodeledSideEffects), 0xa1002145ULL, NULL, NULL, OperandInfo97 }, // Inst #1529 = MOVMSKPDrr64 | |
| { 1530, 2, 1, 0, 0, "MOVMSKPSrr32", 0, 0xa0800105ULL, NULL, NULL, OperandInfo98 }, // Inst #1530 = MOVMSKPSrr32 | |
| { 1531, 2, 1, 0, 0, "MOVMSKPSrr64", 0|(1<<MCID::UnmodeledSideEffects), 0xa0802105ULL, NULL, NULL, OperandInfo97 }, // Inst #1531 = MOVMSKPSrr64 | |
| { 1532, 6, 1, 0, 0, "MOVNTDQArm", 0|(1<<MCID::MayLoad), 0x55800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #1532 = MOVNTDQArm | |
| { 1533, 6, 0, 0, 0, "MOVNTDQ_64mr", 0|(1<<MCID::MayStore), 0x1cf000144ULL, NULL, NULL, OperandInfo187 }, // Inst #1533 = MOVNTDQ_64mr | |
| { 1534, 6, 0, 0, 0, "MOVNTDQmr", 0|(1<<MCID::MayStore), 0x1cf800144ULL, NULL, NULL, OperandInfo187 }, // Inst #1534 = MOVNTDQmr | |
| { 1535, 6, 0, 0, 0, "MOVNTI_64mr", 0|(1<<MCID::MayStore), 0x186002104ULL, NULL, NULL, OperandInfo24 }, // Inst #1535 = MOVNTI_64mr | |
| { 1536, 6, 0, 0, 0, "MOVNTImr", 0|(1<<MCID::MayStore), 0x186000104ULL, NULL, NULL, OperandInfo20 }, // Inst #1536 = MOVNTImr | |
| { 1537, 6, 0, 0, 0, "MOVNTPDmr", 0|(1<<MCID::MayStore), 0x57000144ULL, NULL, NULL, OperandInfo187 }, // Inst #1537 = MOVNTPDmr | |
| { 1538, 6, 0, 0, 0, "MOVNTPSmr", 0|(1<<MCID::MayStore), 0x56800104ULL, NULL, NULL, OperandInfo187 }, // Inst #1538 = MOVNTPSmr | |
| { 1539, 2, 1, 0, 0, "MOVPC32r", 0|(1<<MCID::NotDuplicable), 0x1d0014000ULL, ImplicitList6, NULL, OperandInfo70 }, // Inst #1539 = MOVPC32r | |
| { 1540, 6, 0, 0, 0, "MOVPDI2DImr", 0|(1<<MCID::MayStore), 0xfd000144ULL, NULL, NULL, OperandInfo187 }, // Inst #1540 = MOVPDI2DImr | |
| { 1541, 2, 1, 0, 0, "MOVPDI2DIrr", 0, 0xfd000143ULL, NULL, NULL, OperandInfo98 }, // Inst #1541 = MOVPDI2DIrr | |
| { 1542, 6, 0, 0, 0, "MOVPQI2QImr", 0|(1<<MCID::MayStore), 0x1ad000144ULL, NULL, NULL, OperandInfo187 }, // Inst #1542 = MOVPQI2QImr | |
| { 1543, 2, 1, 0, 0, "MOVPQIto64rr", 0, 0xfd002143ULL, NULL, NULL, OperandInfo97 }, // Inst #1543 = MOVPQIto64rr | |
| { 1544, 6, 1, 0, 0, "MOVQI2PQIrm", 0|(1<<MCID::MayLoad), 0xfc000c06ULL, NULL, NULL, OperandInfo47 }, // Inst #1544 = MOVQI2PQIrm | |
| { 1545, 2, 1, 0, 0, "MOVQxrxr", 0|(1<<MCID::UnmodeledSideEffects), 0xfc000c05ULL, NULL, NULL, OperandInfo48 }, // Inst #1545 = MOVQxrxr | |
| { 1546, 0, 0, 0, 0, "MOVSB", 0|(1<<MCID::UnmodeledSideEffects), 0x148000001ULL, ImplicitList39, ImplicitList40, 0 }, // Inst #1546 = MOVSB | |
| { 1547, 0, 0, 0, 0, "MOVSD", 0|(1<<MCID::UnmodeledSideEffects), 0x14a000001ULL, ImplicitList39, ImplicitList40, 0 }, // Inst #1547 = MOVSD | |
| { 1548, 6, 0, 0, 0, "MOVSDmr", 0|(1<<MCID::MayStore), 0x22000b04ULL, NULL, NULL, OperandInfo189 }, // Inst #1548 = MOVSDmr | |
| { 1549, 6, 1, 0, 0, "MOVSDrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x20000b06ULL, NULL, NULL, OperandInfo101 }, // Inst #1549 = MOVSDrm | |
| { 1550, 3, 1, 0, 0, "MOVSDrr", 0, 0x20000b05ULL, NULL, NULL, OperandInfo190 }, // Inst #1550 = MOVSDrr | |
| { 1551, 3, 1, 0, 0, "MOVSDrr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x22000b03ULL, NULL, NULL, OperandInfo190 }, // Inst #1551 = MOVSDrr_REV | |
| { 1552, 6, 0, 0, 0, "MOVSDto64mr", 0|(1<<MCID::MayStore), 0xfd002144ULL, NULL, NULL, OperandInfo189 }, // Inst #1552 = MOVSDto64mr | |
| { 1553, 2, 1, 0, 0, "MOVSDto64rr", 0|(1<<MCID::Bitcast), 0xfd002143ULL, NULL, NULL, OperandInfo109 }, // Inst #1553 = MOVSDto64rr | |
| { 1554, 6, 1, 0, 0, "MOVSHDUPrm", 0|(1<<MCID::MayLoad), 0x2c800c06ULL, NULL, NULL, OperandInfo47 }, // Inst #1554 = MOVSHDUPrm | |
| { 1555, 2, 1, 0, 0, "MOVSHDUPrr", 0, 0x2c800c05ULL, NULL, NULL, OperandInfo48 }, // Inst #1555 = MOVSHDUPrr | |
| { 1556, 6, 1, 0, 0, "MOVSLDUPrm", 0|(1<<MCID::MayLoad), 0x24800c06ULL, NULL, NULL, OperandInfo47 }, // Inst #1556 = MOVSLDUPrm | |
| { 1557, 2, 1, 0, 0, "MOVSLDUPrr", 0, 0x24800c05ULL, NULL, NULL, OperandInfo48 }, // Inst #1557 = MOVSLDUPrr | |
| { 1558, 0, 0, 0, 0, "MOVSQ", 0|(1<<MCID::UnmodeledSideEffects), 0x14a002001ULL, ImplicitList39, ImplicitList40, 0 }, // Inst #1558 = MOVSQ | |
| { 1559, 6, 0, 0, 0, "MOVSS2DImr", 0|(1<<MCID::MayStore), 0xfd000144ULL, NULL, NULL, OperandInfo191 }, // Inst #1559 = MOVSS2DImr | |
| { 1560, 2, 1, 0, 0, "MOVSS2DIrr", 0|(1<<MCID::Bitcast), 0xfd000143ULL, NULL, NULL, OperandInfo108 }, // Inst #1560 = MOVSS2DIrr | |
| { 1561, 6, 0, 0, 0, "MOVSSmr", 0|(1<<MCID::MayStore), 0x22000c04ULL, NULL, NULL, OperandInfo191 }, // Inst #1561 = MOVSSmr | |
| { 1562, 6, 1, 0, 0, "MOVSSrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x20000c06ULL, NULL, NULL, OperandInfo99 }, // Inst #1562 = MOVSSrm | |
| { 1563, 3, 1, 0, 0, "MOVSSrr", 0, 0x20000c05ULL, NULL, NULL, OperandInfo192 }, // Inst #1563 = MOVSSrr | |
| { 1564, 3, 1, 0, 0, "MOVSSrr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x22000c03ULL, NULL, NULL, OperandInfo192 }, // Inst #1564 = MOVSSrr_REV | |
| { 1565, 0, 0, 0, 0, "MOVSW", 0|(1<<MCID::UnmodeledSideEffects), 0x14a000041ULL, ImplicitList39, ImplicitList40, 0 }, // Inst #1565 = MOVSW | |
| { 1566, 6, 1, 0, 0, "MOVSX16rm8", 0|(1<<MCID::UnmodeledSideEffects), 0x17c000146ULL, NULL, NULL, OperandInfo11 }, // Inst #1566 = MOVSX16rm8 | |
| { 1567, 2, 1, 0, 0, "MOVSX16rr8", 0|(1<<MCID::UnmodeledSideEffects), 0x17c000145ULL, NULL, NULL, OperandInfo193 }, // Inst #1567 = MOVSX16rr8 | |
| { 1568, 6, 1, 0, 0, "MOVSX32rm16", 0|(1<<MCID::MayLoad), 0x17e000106ULL, NULL, NULL, OperandInfo12 }, // Inst #1568 = MOVSX32rm16 | |
| { 1569, 6, 1, 0, 0, "MOVSX32rm8", 0|(1<<MCID::MayLoad), 0x17c000106ULL, NULL, NULL, OperandInfo12 }, // Inst #1569 = MOVSX32rm8 | |
| { 1570, 2, 1, 0, 0, "MOVSX32rr16", 0, 0x17e000105ULL, NULL, NULL, OperandInfo194 }, // Inst #1570 = MOVSX32rr16 | |
| { 1571, 2, 1, 0, 0, "MOVSX32rr8", 0, 0x17c000105ULL, NULL, NULL, OperandInfo195 }, // Inst #1571 = MOVSX32rr8 | |
| { 1572, 6, 1, 0, 0, "MOVSX64rm16", 0|(1<<MCID::MayLoad), 0x17e002106ULL, NULL, NULL, OperandInfo13 }, // Inst #1572 = MOVSX64rm16 | |
| { 1573, 6, 1, 0, 0, "MOVSX64rm32", 0|(1<<MCID::MayLoad), 0xc6002006ULL, NULL, NULL, OperandInfo13 }, // Inst #1573 = MOVSX64rm32 | |
| { 1574, 6, 1, 0, 0, "MOVSX64rm8", 0|(1<<MCID::MayLoad), 0x17c002106ULL, NULL, NULL, OperandInfo13 }, // Inst #1574 = MOVSX64rm8 | |
| { 1575, 2, 1, 0, 0, "MOVSX64rr16", 0, 0x17e002105ULL, NULL, NULL, OperandInfo196 }, // Inst #1575 = MOVSX64rr16 | |
| { 1576, 2, 1, 0, 0, "MOVSX64rr32", 0, 0xc6002005ULL, NULL, NULL, OperandInfo141 }, // Inst #1576 = MOVSX64rr32 | |
| { 1577, 2, 1, 0, 0, "MOVSX64rr8", 0, 0x17c002105ULL, NULL, NULL, OperandInfo197 }, // Inst #1577 = MOVSX64rr8 | |
| { 1578, 6, 0, 0, 0, "MOVUPDmr", 0|(1<<MCID::MayStore), 0x23000144ULL, NULL, NULL, OperandInfo187 }, // Inst #1578 = MOVUPDmr | |
| { 1579, 6, 1, 0, 0, "MOVUPDrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad), 0x21000146ULL, NULL, NULL, OperandInfo47 }, // Inst #1579 = MOVUPDrm | |
| { 1580, 2, 1, 0, 0, "MOVUPDrr", 0, 0x21000145ULL, NULL, NULL, OperandInfo48 }, // Inst #1580 = MOVUPDrr | |
| { 1581, 2, 1, 0, 0, "MOVUPDrr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x23000143ULL, NULL, NULL, OperandInfo48 }, // Inst #1581 = MOVUPDrr_REV | |
| { 1582, 6, 0, 0, 0, "MOVUPSmr", 0|(1<<MCID::MayStore), 0x22800104ULL, NULL, NULL, OperandInfo187 }, // Inst #1582 = MOVUPSmr | |
| { 1583, 6, 1, 0, 0, "MOVUPSrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x20800106ULL, NULL, NULL, OperandInfo47 }, // Inst #1583 = MOVUPSrm | |
| { 1584, 2, 1, 0, 0, "MOVUPSrr", 0, 0x20800105ULL, NULL, NULL, OperandInfo48 }, // Inst #1584 = MOVUPSrr | |
| { 1585, 2, 1, 0, 0, "MOVUPSrr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x22800103ULL, NULL, NULL, OperandInfo48 }, // Inst #1585 = MOVUPSrr_REV | |
| { 1586, 6, 1, 0, 0, "MOVZDI2PDIrm", 0|(1<<MCID::MayLoad), 0xdd000146ULL, NULL, NULL, OperandInfo47 }, // Inst #1586 = MOVZDI2PDIrm | |
| { 1587, 2, 1, 0, 0, "MOVZDI2PDIrr", 0, 0xdd000145ULL, NULL, NULL, OperandInfo188 }, // Inst #1587 = MOVZDI2PDIrr | |
| { 1588, 6, 1, 0, 0, "MOVZPQILo2PQIrm", 0|(1<<MCID::MayLoad), 0xfc000c06ULL, NULL, NULL, OperandInfo47 }, // Inst #1588 = MOVZPQILo2PQIrm | |
| { 1589, 2, 1, 0, 0, "MOVZPQILo2PQIrr", 0, 0xfc000c05ULL, NULL, NULL, OperandInfo48 }, // Inst #1589 = MOVZPQILo2PQIrr | |
| { 1590, 6, 1, 0, 0, "MOVZQI2PQIrm", 0|(1<<MCID::MayLoad), 0xfc000c06ULL, NULL, NULL, OperandInfo47 }, // Inst #1590 = MOVZQI2PQIrm | |
| { 1591, 2, 1, 0, 0, "MOVZQI2PQIrr", 0, 0xdd002145ULL, NULL, NULL, OperandInfo183 }, // Inst #1591 = MOVZQI2PQIrr | |
| { 1592, 6, 1, 0, 0, "MOVZX16rm8", 0|(1<<MCID::UnmodeledSideEffects), 0x16c000146ULL, NULL, NULL, OperandInfo11 }, // Inst #1592 = MOVZX16rm8 | |
| { 1593, 2, 1, 0, 0, "MOVZX16rr8", 0|(1<<MCID::UnmodeledSideEffects), 0x16c000145ULL, NULL, NULL, OperandInfo193 }, // Inst #1593 = MOVZX16rr8 | |
| { 1594, 6, 1, 0, 0, "MOVZX32_NOREXrm8", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x16c000106ULL, NULL, NULL, OperandInfo198 }, // Inst #1594 = MOVZX32_NOREXrm8 | |
| { 1595, 2, 1, 0, 0, "MOVZX32_NOREXrr8", 0|(1<<MCID::UnmodeledSideEffects), 0x16c000105ULL, NULL, NULL, OperandInfo199 }, // Inst #1595 = MOVZX32_NOREXrr8 | |
| { 1596, 6, 1, 0, 0, "MOVZX32rm16", 0|(1<<MCID::MayLoad), 0x16e000106ULL, NULL, NULL, OperandInfo12 }, // Inst #1596 = MOVZX32rm16 | |
| { 1597, 6, 1, 0, 0, "MOVZX32rm8", 0|(1<<MCID::MayLoad), 0x16c000106ULL, NULL, NULL, OperandInfo12 }, // Inst #1597 = MOVZX32rm8 | |
| { 1598, 2, 1, 0, 0, "MOVZX32rr16", 0, 0x16e000105ULL, NULL, NULL, OperandInfo194 }, // Inst #1598 = MOVZX32rr16 | |
| { 1599, 2, 1, 0, 0, "MOVZX32rr8", 0, 0x16c000105ULL, NULL, NULL, OperandInfo195 }, // Inst #1599 = MOVZX32rr8 | |
| { 1600, 6, 1, 0, 0, "MOVZX64rm16", 0|(1<<MCID::MayLoad), 0x16e000106ULL, NULL, NULL, OperandInfo13 }, // Inst #1600 = MOVZX64rm16 | |
| { 1601, 6, 1, 0, 0, "MOVZX64rm16_Q", 0|(1<<MCID::UnmodeledSideEffects), 0x16e002106ULL, NULL, NULL, OperandInfo13 }, // Inst #1601 = MOVZX64rm16_Q | |
| { 1602, 6, 1, 0, 0, "MOVZX64rm32", 0|(1<<MCID::MayLoad), 0x116000006ULL, NULL, NULL, OperandInfo13 }, // Inst #1602 = MOVZX64rm32 | |
| { 1603, 6, 1, 0, 0, "MOVZX64rm8", 0|(1<<MCID::MayLoad), 0x16c000106ULL, NULL, NULL, OperandInfo13 }, // Inst #1603 = MOVZX64rm8 | |
| { 1604, 6, 1, 0, 0, "MOVZX64rm8_Q", 0|(1<<MCID::UnmodeledSideEffects), 0x16c002106ULL, NULL, NULL, OperandInfo13 }, // Inst #1604 = MOVZX64rm8_Q | |
| { 1605, 2, 1, 0, 0, "MOVZX64rr16", 0, 0x16e000105ULL, NULL, NULL, OperandInfo196 }, // Inst #1605 = MOVZX64rr16 | |
| { 1606, 2, 1, 0, 0, "MOVZX64rr16_Q", 0|(1<<MCID::UnmodeledSideEffects), 0x16e002105ULL, NULL, NULL, OperandInfo196 }, // Inst #1606 = MOVZX64rr16_Q | |
| { 1607, 2, 1, 0, 0, "MOVZX64rr32", 0, 0x112000003ULL, NULL, NULL, OperandInfo141 }, // Inst #1607 = MOVZX64rr32 | |
| { 1608, 2, 1, 0, 0, "MOVZX64rr8", 0, 0x16c000105ULL, NULL, NULL, OperandInfo197 }, // Inst #1608 = MOVZX64rr8 | |
| { 1609, 2, 1, 0, 0, "MOVZX64rr8_Q", 0|(1<<MCID::UnmodeledSideEffects), 0x16c002105ULL, NULL, NULL, OperandInfo197 }, // Inst #1609 = MOVZX64rr8_Q | |
| { 1610, 8, 1, 0, 0, "MPSADBWrmi", 0|(1<<MCID::MayLoad), 0x85804e46ULL, NULL, NULL, OperandInfo63 }, // Inst #1610 = MPSADBWrmi | |
| { 1611, 4, 1, 0, 0, "MPSADBWrri", 0, 0x85804e45ULL, NULL, NULL, OperandInfo64 }, // Inst #1611 = MPSADBWrri | |
| { 1612, 5, 0, 0, 0, "MUL16m", 0|(1<<MCID::MayLoad), 0x1ee00005cULL, ImplicitList2, ImplicitList21, OperandInfo38 }, // Inst #1612 = MUL16m | |
| { 1613, 1, 0, 0, 0, "MUL16r", 0, 0x1ee000054ULL, ImplicitList2, ImplicitList21, OperandInfo113 }, // Inst #1613 = MUL16r | |
| { 1614, 5, 0, 0, 0, "MUL32m", 0|(1<<MCID::MayLoad), 0x1ee00001cULL, ImplicitList3, ImplicitList18, OperandInfo38 }, // Inst #1614 = MUL32m | |
| { 1615, 1, 0, 0, 0, "MUL32r", 0, 0x1ee000014ULL, ImplicitList3, ImplicitList18, OperandInfo72 }, // Inst #1615 = MUL32r | |
| { 1616, 5, 0, 0, 0, "MUL64m", 0|(1<<MCID::MayLoad), 0x1ee00201cULL, ImplicitList4, ImplicitList17, OperandInfo38 }, // Inst #1616 = MUL64m | |
| { 1617, 1, 0, 0, 0, "MUL64r", 0, 0x1ee002014ULL, ImplicitList4, ImplicitList17, OperandInfo74 }, // Inst #1617 = MUL64r | |
| { 1618, 5, 0, 0, 0, "MUL8m", 0|(1<<MCID::MayLoad), 0x1ec00001cULL, ImplicitList5, ImplicitList22, OperandInfo38 }, // Inst #1618 = MUL8m | |
| { 1619, 1, 0, 0, 0, "MUL8r", 0, 0x1ec000014ULL, ImplicitList5, ImplicitList22, OperandInfo114 }, // Inst #1619 = MUL8r | |
| { 1620, 7, 1, 0, 0, "MULPDrm", 0|(1<<MCID::MayLoad), 0xb3000146ULL, NULL, NULL, OperandInfo32 }, // Inst #1620 = MULPDrm | |
| { 1621, 3, 1, 0, 0, "MULPDrr", 0|(1<<MCID::Commutable), 0xb3000145ULL, NULL, NULL, OperandInfo33 }, // Inst #1621 = MULPDrr | |
| { 1622, 7, 1, 0, 0, "MULPSrm", 0|(1<<MCID::MayLoad), 0xb2800106ULL, NULL, NULL, OperandInfo32 }, // Inst #1622 = MULPSrm | |
| { 1623, 3, 1, 0, 0, "MULPSrr", 0|(1<<MCID::Commutable), 0xb2800105ULL, NULL, NULL, OperandInfo33 }, // Inst #1623 = MULPSrr | |
| { 1624, 7, 1, 0, 0, "MULSDrm", 0|(1<<MCID::MayLoad), 0xb2000b06ULL, NULL, NULL, OperandInfo34 }, // Inst #1624 = MULSDrm | |
| { 1625, 7, 1, 0, 0, "MULSDrm_Int", 0|(1<<MCID::MayLoad), 0xb2000b06ULL, NULL, NULL, OperandInfo32 }, // Inst #1625 = MULSDrm_Int | |
| { 1626, 3, 1, 0, 0, "MULSDrr", 0|(1<<MCID::Commutable), 0xb2000b05ULL, NULL, NULL, OperandInfo35 }, // Inst #1626 = MULSDrr | |
| { 1627, 3, 1, 0, 0, "MULSDrr_Int", 0, 0xb2000b05ULL, NULL, NULL, OperandInfo33 }, // Inst #1627 = MULSDrr_Int | |
| { 1628, 7, 1, 0, 0, "MULSSrm", 0|(1<<MCID::MayLoad), 0xb2000c06ULL, NULL, NULL, OperandInfo36 }, // Inst #1628 = MULSSrm | |
| { 1629, 7, 1, 0, 0, "MULSSrm_Int", 0|(1<<MCID::MayLoad), 0xb2000c06ULL, NULL, NULL, OperandInfo32 }, // Inst #1629 = MULSSrm_Int | |
| { 1630, 3, 1, 0, 0, "MULSSrr", 0|(1<<MCID::Commutable), 0xb2000c05ULL, NULL, NULL, OperandInfo37 }, // Inst #1630 = MULSSrr | |
| { 1631, 3, 1, 0, 0, "MULSSrr_Int", 0, 0xb2000c05ULL, NULL, NULL, OperandInfo33 }, // Inst #1631 = MULSSrr_Int | |
| { 1632, 5, 0, 0, 0, "MUL_F32m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b0000019ULL, NULL, NULL, OperandInfo38 }, // Inst #1632 = MUL_F32m | |
| { 1633, 5, 0, 0, 0, "MUL_F64m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b8000019ULL, NULL, NULL, OperandInfo38 }, // Inst #1633 = MUL_F64m | |
| { 1634, 5, 0, 0, 0, "MUL_FI16m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1bc000019ULL, NULL, NULL, OperandInfo38 }, // Inst #1634 = MUL_FI16m | |
| { 1635, 5, 0, 0, 0, "MUL_FI32m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b4000019ULL, NULL, NULL, OperandInfo38 }, // Inst #1635 = MUL_FI32m | |
| { 1636, 1, 0, 0, 0, "MUL_FPrST0", 0|(1<<MCID::UnmodeledSideEffects), 0x190000902ULL, NULL, NULL, OperandInfo39 }, // Inst #1636 = MUL_FPrST0 | |
| { 1637, 1, 0, 0, 0, "MUL_FST0r", 0|(1<<MCID::UnmodeledSideEffects), 0x190000302ULL, NULL, NULL, OperandInfo39 }, // Inst #1637 = MUL_FST0r | |
| { 1638, 3, 1, 0, 0, "MUL_Fp32", 0, 0x80000ULL, NULL, NULL, OperandInfo40 }, // Inst #1638 = MUL_Fp32 | |
| { 1639, 7, 1, 0, 0, "MUL_Fp32m", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo41 }, // Inst #1639 = MUL_Fp32m | |
| { 1640, 3, 1, 0, 0, "MUL_Fp64", 0, 0x80000ULL, NULL, NULL, OperandInfo42 }, // Inst #1640 = MUL_Fp64 | |
| { 1641, 7, 1, 0, 0, "MUL_Fp64m", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #1641 = MUL_Fp64m | |
| { 1642, 7, 1, 0, 0, "MUL_Fp64m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #1642 = MUL_Fp64m32 | |
| { 1643, 3, 1, 0, 0, "MUL_Fp80", 0, 0x80000ULL, NULL, NULL, OperandInfo44 }, // Inst #1643 = MUL_Fp80 | |
| { 1644, 7, 1, 0, 0, "MUL_Fp80m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #1644 = MUL_Fp80m32 | |
| { 1645, 7, 1, 0, 0, "MUL_Fp80m64", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #1645 = MUL_Fp80m64 | |
| { 1646, 7, 1, 0, 0, "MUL_FpI16m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo41 }, // Inst #1646 = MUL_FpI16m32 | |
| { 1647, 7, 1, 0, 0, "MUL_FpI16m64", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #1647 = MUL_FpI16m64 | |
| { 1648, 7, 1, 0, 0, "MUL_FpI16m80", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #1648 = MUL_FpI16m80 | |
| { 1649, 7, 1, 0, 0, "MUL_FpI32m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo41 }, // Inst #1649 = MUL_FpI32m32 | |
| { 1650, 7, 1, 0, 0, "MUL_FpI32m64", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #1650 = MUL_FpI32m64 | |
| { 1651, 7, 1, 0, 0, "MUL_FpI32m80", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #1651 = MUL_FpI32m80 | |
| { 1652, 1, 0, 0, 0, "MUL_FrST0", 0|(1<<MCID::UnmodeledSideEffects), 0x190000702ULL, NULL, NULL, OperandInfo39 }, // Inst #1652 = MUL_FrST0 | |
| { 1653, 2, 0, 0, 0, "MWAIT", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo65 }, // Inst #1653 = MWAIT | |
| { 1654, 0, 0, 0, 0, "MWAITrr", 0|(1<<MCID::UnmodeledSideEffects), 0x2000126ULL, ImplicitList41, NULL, 0 }, // Inst #1654 = MWAITrr | |
| { 1655, 5, 0, 0, 0, "NEG16m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1ee00005bULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #1655 = NEG16m | |
| { 1656, 2, 1, 0, 0, "NEG16r", 0, 0x1ee000053ULL, NULL, ImplicitList1, OperandInfo111 }, // Inst #1656 = NEG16r | |
| { 1657, 5, 0, 0, 0, "NEG32m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1ee00001bULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #1657 = NEG32m | |
| { 1658, 2, 1, 0, 0, "NEG32r", 0, 0x1ee000013ULL, NULL, ImplicitList1, OperandInfo67 }, // Inst #1658 = NEG32r | |
| { 1659, 5, 0, 0, 0, "NEG64m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1ee00201bULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #1659 = NEG64m | |
| { 1660, 2, 1, 0, 0, "NEG64r", 0, 0x1ee002013ULL, NULL, ImplicitList1, OperandInfo68 }, // Inst #1660 = NEG64r | |
| { 1661, 5, 0, 0, 0, "NEG8m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1ec00001bULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #1661 = NEG8m | |
| { 1662, 2, 1, 0, 0, "NEG8r", 0, 0x1ec000013ULL, NULL, ImplicitList1, OperandInfo112 }, // Inst #1662 = NEG8r | |
| { 1663, 0, 0, 0, 0, "NOOP", 0, 0x120000001ULL, NULL, NULL, 0 }, // Inst #1663 = NOOP | |
| { 1664, 5, 0, 0, 0, "NOOPL", 0, 0x3e000118ULL, NULL, NULL, OperandInfo38 }, // Inst #1664 = NOOPL | |
| { 1665, 5, 0, 0, 0, "NOOPW", 0, 0x3e000158ULL, NULL, NULL, OperandInfo38 }, // Inst #1665 = NOOPW | |
| { 1666, 5, 0, 0, 0, "NOT16m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1ee00005aULL, NULL, NULL, OperandInfo38 }, // Inst #1666 = NOT16m | |
| { 1667, 2, 1, 0, 0, "NOT16r", 0, 0x1ee000052ULL, NULL, NULL, OperandInfo111 }, // Inst #1667 = NOT16r | |
| { 1668, 5, 0, 0, 0, "NOT32m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1ee00001aULL, NULL, NULL, OperandInfo38 }, // Inst #1668 = NOT32m | |
| { 1669, 2, 1, 0, 0, "NOT32r", 0, 0x1ee000012ULL, NULL, NULL, OperandInfo67 }, // Inst #1669 = NOT32r | |
| { 1670, 5, 0, 0, 0, "NOT64m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1ee00201aULL, NULL, NULL, OperandInfo38 }, // Inst #1670 = NOT64m | |
| { 1671, 2, 1, 0, 0, "NOT64r", 0, 0x1ee002012ULL, NULL, NULL, OperandInfo68 }, // Inst #1671 = NOT64r | |
| { 1672, 5, 0, 0, 0, "NOT8m", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1ec00001aULL, NULL, NULL, OperandInfo38 }, // Inst #1672 = NOT8m | |
| { 1673, 2, 1, 0, 0, "NOT8r", 0, 0x1ec000012ULL, NULL, NULL, OperandInfo112 }, // Inst #1673 = NOT8r | |
| { 1674, 1, 0, 0, 0, "OR16i16", 0|(1<<MCID::UnmodeledSideEffects), 0x1a00c041ULL, ImplicitList2, ImplicitList1, OperandInfo2 }, // Inst #1674 = OR16i16 | |
| { 1675, 6, 0, 0, 0, "OR16mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10200c059ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1675 = OR16mi | |
| { 1676, 6, 0, 0, 0, "OR16mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x106004059ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1676 = OR16mi8 | |
| { 1677, 6, 0, 0, 0, "OR16mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x12000044ULL, NULL, ImplicitList1, OperandInfo16 }, // Inst #1677 = OR16mr | |
| { 1678, 3, 1, 0, 0, "OR16ri", 0, 0x10200c051ULL, NULL, ImplicitList1, OperandInfo17 }, // Inst #1678 = OR16ri | |
| { 1679, 3, 1, 0, 0, "OR16ri8", 0, 0x106004051ULL, NULL, ImplicitList1, OperandInfo17 }, // Inst #1679 = OR16ri8 | |
| { 1680, 7, 1, 0, 0, "OR16rm", 0|(1<<MCID::MayLoad), 0x16000046ULL, NULL, ImplicitList1, OperandInfo18 }, // Inst #1680 = OR16rm | |
| { 1681, 3, 1, 0, 0, "OR16rr", 0|(1<<MCID::Commutable), 0x12000043ULL, NULL, ImplicitList1, OperandInfo19 }, // Inst #1681 = OR16rr | |
| { 1682, 3, 1, 0, 0, "OR16rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x16000045ULL, NULL, ImplicitList1, OperandInfo19 }, // Inst #1682 = OR16rr_REV | |
| { 1683, 1, 0, 0, 0, "OR32i32", 0|(1<<MCID::UnmodeledSideEffects), 0x1a014001ULL, ImplicitList3, ImplicitList1, OperandInfo2 }, // Inst #1683 = OR32i32 | |
| { 1684, 6, 0, 0, 0, "OR32mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x102014019ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1684 = OR32mi | |
| { 1685, 6, 0, 0, 0, "OR32mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x106004019ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1685 = OR32mi8 | |
| { 1686, 6, 0, 0, 0, "OR32mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x12000004ULL, NULL, ImplicitList1, OperandInfo20 }, // Inst #1686 = OR32mr | |
| { 1687, 6, 0, 0, 0, "OR32mrLocked", 0|(1<<MCID::UnmodeledSideEffects), 0x12100004ULL, NULL, NULL, OperandInfo20 }, // Inst #1687 = OR32mrLocked | |
| { 1688, 3, 1, 0, 0, "OR32ri", 0, 0x102014011ULL, NULL, ImplicitList1, OperandInfo21 }, // Inst #1688 = OR32ri | |
| { 1689, 3, 1, 0, 0, "OR32ri8", 0, 0x106004011ULL, NULL, ImplicitList1, OperandInfo21 }, // Inst #1689 = OR32ri8 | |
| { 1690, 7, 1, 0, 0, "OR32rm", 0|(1<<MCID::MayLoad), 0x16000006ULL, NULL, ImplicitList1, OperandInfo22 }, // Inst #1690 = OR32rm | |
| { 1691, 3, 1, 0, 0, "OR32rr", 0|(1<<MCID::Commutable), 0x12000003ULL, NULL, ImplicitList1, OperandInfo23 }, // Inst #1691 = OR32rr | |
| { 1692, 3, 1, 0, 0, "OR32rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x16000005ULL, NULL, ImplicitList1, OperandInfo23 }, // Inst #1692 = OR32rr_REV | |
| { 1693, 1, 0, 0, 0, "OR64i32", 0|(1<<MCID::UnmodeledSideEffects), 0x1a016001ULL, ImplicitList4, ImplicitList1, OperandInfo2 }, // Inst #1693 = OR64i32 | |
| { 1694, 6, 0, 0, 0, "OR64mi32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x102016019ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1694 = OR64mi32 | |
| { 1695, 6, 0, 0, 0, "OR64mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x106006019ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1695 = OR64mi8 | |
| { 1696, 6, 0, 0, 0, "OR64mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x12002004ULL, NULL, ImplicitList1, OperandInfo24 }, // Inst #1696 = OR64mr | |
| { 1697, 3, 1, 0, 0, "OR64ri32", 0, 0x102016011ULL, NULL, ImplicitList1, OperandInfo25 }, // Inst #1697 = OR64ri32 | |
| { 1698, 3, 1, 0, 0, "OR64ri8", 0, 0x106006011ULL, NULL, ImplicitList1, OperandInfo25 }, // Inst #1698 = OR64ri8 | |
| { 1699, 7, 1, 0, 0, "OR64rm", 0|(1<<MCID::MayLoad), 0x16002006ULL, NULL, ImplicitList1, OperandInfo26 }, // Inst #1699 = OR64rm | |
| { 1700, 3, 1, 0, 0, "OR64rr", 0|(1<<MCID::Commutable), 0x12002003ULL, NULL, ImplicitList1, OperandInfo27 }, // Inst #1700 = OR64rr | |
| { 1701, 3, 1, 0, 0, "OR64rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x16002005ULL, NULL, ImplicitList1, OperandInfo27 }, // Inst #1701 = OR64rr_REV | |
| { 1702, 1, 0, 0, 0, "OR8i8", 0|(1<<MCID::UnmodeledSideEffects), 0x18004001ULL, ImplicitList5, ImplicitList1, OperandInfo2 }, // Inst #1702 = OR8i8 | |
| { 1703, 6, 0, 0, 0, "OR8mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x100004019ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #1703 = OR8mi | |
| { 1704, 6, 0, 0, 0, "OR8mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10000004ULL, NULL, ImplicitList1, OperandInfo28 }, // Inst #1704 = OR8mr | |
| { 1705, 3, 1, 0, 0, "OR8ri", 0, 0x100004011ULL, NULL, ImplicitList1, OperandInfo29 }, // Inst #1705 = OR8ri | |
| { 1706, 7, 1, 0, 0, "OR8rm", 0|(1<<MCID::MayLoad), 0x14000006ULL, NULL, ImplicitList1, OperandInfo30 }, // Inst #1706 = OR8rm | |
| { 1707, 3, 1, 0, 0, "OR8rr", 0|(1<<MCID::Commutable), 0x10000003ULL, NULL, ImplicitList1, OperandInfo31 }, // Inst #1707 = OR8rr | |
| { 1708, 3, 1, 0, 0, "OR8rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x14000005ULL, NULL, ImplicitList1, OperandInfo31 }, // Inst #1708 = OR8rr_REV | |
| { 1709, 7, 1, 0, 0, "ORPDrm", 0|(1<<MCID::MayLoad), 0xad000146ULL, NULL, NULL, OperandInfo32 }, // Inst #1709 = ORPDrm | |
| { 1710, 3, 1, 0, 0, "ORPDrr", 0|(1<<MCID::Commutable), 0xad000145ULL, NULL, NULL, OperandInfo33 }, // Inst #1710 = ORPDrr | |
| { 1711, 7, 1, 0, 0, "ORPSrm", 0|(1<<MCID::MayLoad), 0xac800106ULL, NULL, NULL, OperandInfo32 }, // Inst #1711 = ORPSrm | |
| { 1712, 3, 1, 0, 0, "ORPSrr", 0|(1<<MCID::Commutable), 0xac800105ULL, NULL, NULL, OperandInfo33 }, // Inst #1712 = ORPSrr | |
| { 1713, 1, 0, 0, 0, "OUT16ir", 0|(1<<MCID::UnmodeledSideEffects), 0x1ce004041ULL, ImplicitList2, NULL, OperandInfo2 }, // Inst #1713 = OUT16ir | |
| { 1714, 0, 0, 0, 0, "OUT16rr", 0|(1<<MCID::UnmodeledSideEffects), 0x1de000041ULL, ImplicitList42, NULL, 0 }, // Inst #1714 = OUT16rr | |
| { 1715, 1, 0, 0, 0, "OUT32ir", 0|(1<<MCID::UnmodeledSideEffects), 0x1ce004001ULL, ImplicitList3, NULL, OperandInfo2 }, // Inst #1715 = OUT32ir | |
| { 1716, 0, 0, 0, 0, "OUT32rr", 0|(1<<MCID::UnmodeledSideEffects), 0x1de000001ULL, ImplicitList43, NULL, 0 }, // Inst #1716 = OUT32rr | |
| { 1717, 1, 0, 0, 0, "OUT8ir", 0|(1<<MCID::UnmodeledSideEffects), 0x1cc004001ULL, ImplicitList5, NULL, OperandInfo2 }, // Inst #1717 = OUT8ir | |
| { 1718, 0, 0, 0, 0, "OUT8rr", 0|(1<<MCID::UnmodeledSideEffects), 0x1dc000001ULL, ImplicitList44, NULL, 0 }, // Inst #1718 = OUT8rr | |
| { 1719, 0, 0, 0, 0, "OUTSB", 0|(1<<MCID::UnmodeledSideEffects), 0xdc000001ULL, NULL, NULL, 0 }, // Inst #1719 = OUTSB | |
| { 1720, 0, 0, 0, 0, "OUTSD", 0|(1<<MCID::UnmodeledSideEffects), 0xde000001ULL, NULL, NULL, 0 }, // Inst #1720 = OUTSD | |
| { 1721, 0, 0, 0, 0, "OUTSW", 0|(1<<MCID::UnmodeledSideEffects), 0xde000041ULL, NULL, NULL, 0 }, // Inst #1721 = OUTSW | |
| { 1722, 6, 1, 0, 0, "PABSBrm128", 0|(1<<MCID::MayLoad), 0x39804d46ULL, NULL, NULL, OperandInfo47 }, // Inst #1722 = PABSBrm128 | |
| { 1723, 2, 1, 0, 0, "PABSBrr128", 0, 0x39804d45ULL, NULL, NULL, OperandInfo48 }, // Inst #1723 = PABSBrr128 | |
| { 1724, 6, 1, 0, 0, "PABSDrm128", 0|(1<<MCID::MayLoad), 0x3d804d46ULL, NULL, NULL, OperandInfo47 }, // Inst #1724 = PABSDrm128 | |
| { 1725, 2, 1, 0, 0, "PABSDrr128", 0, 0x3d804d45ULL, NULL, NULL, OperandInfo48 }, // Inst #1725 = PABSDrr128 | |
| { 1726, 6, 1, 0, 0, "PABSWrm128", 0|(1<<MCID::MayLoad), 0x3b804d46ULL, NULL, NULL, OperandInfo47 }, // Inst #1726 = PABSWrm128 | |
| { 1727, 2, 1, 0, 0, "PABSWrr128", 0, 0x3b804d45ULL, NULL, NULL, OperandInfo48 }, // Inst #1727 = PABSWrr128 | |
| { 1728, 7, 1, 0, 0, "PACKSSDWrm", 0|(1<<MCID::MayLoad), 0xd7800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1728 = PACKSSDWrm | |
| { 1729, 3, 1, 0, 0, "PACKSSDWrr", 0, 0xd7800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1729 = PACKSSDWrr | |
| { 1730, 7, 1, 0, 0, "PACKSSWBrm", 0|(1<<MCID::MayLoad), 0xc7800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1730 = PACKSSWBrm | |
| { 1731, 3, 1, 0, 0, "PACKSSWBrr", 0, 0xc7800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1731 = PACKSSWBrr | |
| { 1732, 7, 1, 0, 0, "PACKUSDWrm", 0|(1<<MCID::MayLoad), 0x57800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1732 = PACKUSDWrm | |
| { 1733, 3, 1, 0, 0, "PACKUSDWrr", 0, 0x57800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1733 = PACKUSDWrr | |
| { 1734, 7, 1, 0, 0, "PACKUSWBrm", 0|(1<<MCID::MayLoad), 0xcf800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1734 = PACKUSWBrm | |
| { 1735, 3, 1, 0, 0, "PACKUSWBrr", 0, 0xcf800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1735 = PACKUSWBrr | |
| { 1736, 7, 1, 0, 0, "PADDBrm", 0|(1<<MCID::MayLoad), 0x1f9800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1736 = PADDBrm | |
| { 1737, 3, 1, 0, 0, "PADDBrr", 0|(1<<MCID::Commutable), 0x1f9800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1737 = PADDBrr | |
| { 1738, 7, 1, 0, 0, "PADDDrm", 0|(1<<MCID::MayLoad), 0x1fd800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1738 = PADDDrm | |
| { 1739, 3, 1, 0, 0, "PADDDrr", 0|(1<<MCID::Commutable), 0x1fd800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1739 = PADDDrr | |
| { 1740, 7, 1, 0, 0, "PADDQrm", 0|(1<<MCID::MayLoad), 0x1a9800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1740 = PADDQrm | |
| { 1741, 3, 1, 0, 0, "PADDQrr", 0|(1<<MCID::Commutable), 0x1a9800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1741 = PADDQrr | |
| { 1742, 7, 1, 0, 0, "PADDSBrm", 0|(1<<MCID::MayLoad), 0x1d9800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1742 = PADDSBrm | |
| { 1743, 3, 1, 0, 0, "PADDSBrr", 0|(1<<MCID::Commutable), 0x1d9800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1743 = PADDSBrr | |
| { 1744, 7, 1, 0, 0, "PADDSWrm", 0|(1<<MCID::MayLoad), 0x1db800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1744 = PADDSWrm | |
| { 1745, 3, 1, 0, 0, "PADDSWrr", 0|(1<<MCID::Commutable), 0x1db800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1745 = PADDSWrr | |
| { 1746, 7, 1, 0, 0, "PADDUSBrm", 0|(1<<MCID::MayLoad), 0x1b9800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1746 = PADDUSBrm | |
| { 1747, 3, 1, 0, 0, "PADDUSBrr", 0|(1<<MCID::Commutable), 0x1b9800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1747 = PADDUSBrr | |
| { 1748, 7, 1, 0, 0, "PADDUSWrm", 0|(1<<MCID::MayLoad), 0x1bb800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1748 = PADDUSWrm | |
| { 1749, 3, 1, 0, 0, "PADDUSWrr", 0|(1<<MCID::Commutable), 0x1bb800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1749 = PADDUSWrr | |
| { 1750, 7, 1, 0, 0, "PADDWrm", 0|(1<<MCID::MayLoad), 0x1fb800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1750 = PADDWrm | |
| { 1751, 3, 1, 0, 0, "PADDWrr", 0|(1<<MCID::Commutable), 0x1fb800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1751 = PADDWrr | |
| { 1752, 8, 1, 0, 0, "PALIGNR128rm", 0|(1<<MCID::UnmodeledSideEffects), 0x1f804e46ULL, NULL, NULL, OperandInfo63 }, // Inst #1752 = PALIGNR128rm | |
| { 1753, 4, 1, 0, 0, "PALIGNR128rr", 0|(1<<MCID::UnmodeledSideEffects), 0x1f804e45ULL, NULL, NULL, OperandInfo64 }, // Inst #1753 = PALIGNR128rr | |
| { 1754, 7, 1, 0, 0, "PANDNrm", 0|(1<<MCID::UnmodeledSideEffects), 0x1bf800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1754 = PANDNrm | |
| { 1755, 3, 1, 0, 0, "PANDNrr", 0|(1<<MCID::UnmodeledSideEffects), 0x1bf800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1755 = PANDNrr | |
| { 1756, 7, 1, 0, 0, "PANDrm", 0|(1<<MCID::MayLoad), 0x1b7800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1756 = PANDrm | |
| { 1757, 3, 1, 0, 0, "PANDrr", 0|(1<<MCID::Commutable), 0x1b7800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1757 = PANDrr | |
| { 1758, 0, 0, 0, 0, "PAUSE", 0|(1<<MCID::UnmodeledSideEffects), 0x120000201ULL, NULL, NULL, 0 }, // Inst #1758 = PAUSE | |
| { 1759, 7, 1, 0, 0, "PAVGBrm", 0|(1<<MCID::MayLoad), 0x1c1800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1759 = PAVGBrm | |
| { 1760, 3, 1, 0, 0, "PAVGBrr", 0|(1<<MCID::Commutable), 0x1c1800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1760 = PAVGBrr | |
| { 1761, 7, 1, 0, 0, "PAVGUSBrm", 0|(1<<MCID::MayLoad), 0x817e000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1761 = PAVGUSBrm | |
| { 1762, 3, 1, 0, 0, "PAVGUSBrr", 0, 0x817e000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1762 = PAVGUSBrr | |
| { 1763, 7, 1, 0, 0, "PAVGWrm", 0|(1<<MCID::MayLoad), 0x1c7800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1763 = PAVGWrm | |
| { 1764, 3, 1, 0, 0, "PAVGWrr", 0|(1<<MCID::Commutable), 0x1c7800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1764 = PAVGWrr | |
| { 1765, 7, 1, 0, 0, "PBLENDVBrm0", 0|(1<<MCID::MayLoad), 0x21800d46ULL, ImplicitList12, NULL, OperandInfo32 }, // Inst #1765 = PBLENDVBrm0 | |
| { 1766, 3, 1, 0, 0, "PBLENDVBrr0", 0, 0x21800d45ULL, ImplicitList12, NULL, OperandInfo33 }, // Inst #1766 = PBLENDVBrr0 | |
| { 1767, 8, 1, 0, 0, "PBLENDWrmi", 0|(1<<MCID::MayLoad), 0x1d804e46ULL, NULL, NULL, OperandInfo63 }, // Inst #1767 = PBLENDWrmi | |
| { 1768, 4, 1, 0, 0, "PBLENDWrri", 0, 0x1d804e45ULL, NULL, NULL, OperandInfo64 }, // Inst #1768 = PBLENDWrri | |
| { 1769, 8, 1, 0, 0, "PCLMULQDQrm", 0|(1<<MCID::UnmodeledSideEffects), 0x89804e46ULL, NULL, NULL, OperandInfo63 }, // Inst #1769 = PCLMULQDQrm | |
| { 1770, 4, 1, 0, 0, "PCLMULQDQrr", 0|(1<<MCID::UnmodeledSideEffects), 0x89804e45ULL, NULL, NULL, OperandInfo64 }, // Inst #1770 = PCLMULQDQrr | |
| { 1771, 7, 1, 0, 0, "PCMPEQBrm", 0|(1<<MCID::MayLoad), 0xe9800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1771 = PCMPEQBrm | |
| { 1772, 3, 1, 0, 0, "PCMPEQBrr", 0|(1<<MCID::Commutable), 0xe9800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1772 = PCMPEQBrr | |
| { 1773, 7, 1, 0, 0, "PCMPEQDrm", 0|(1<<MCID::MayLoad), 0xed800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1773 = PCMPEQDrm | |
| { 1774, 3, 1, 0, 0, "PCMPEQDrr", 0|(1<<MCID::Commutable), 0xed800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1774 = PCMPEQDrr | |
| { 1775, 7, 1, 0, 0, "PCMPEQQrm", 0|(1<<MCID::MayLoad), 0x53800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1775 = PCMPEQQrm | |
| { 1776, 3, 1, 0, 0, "PCMPEQQrr", 0|(1<<MCID::Commutable), 0x53800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1776 = PCMPEQQrr | |
| { 1777, 7, 1, 0, 0, "PCMPEQWrm", 0|(1<<MCID::MayLoad), 0xeb800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1777 = PCMPEQWrm | |
| { 1778, 3, 1, 0, 0, "PCMPEQWrr", 0|(1<<MCID::Commutable), 0xeb800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1778 = PCMPEQWrr | |
| { 1779, 7, 0, 0, 0, "PCMPESTRIArm", 0|(1<<MCID::MayLoad), 0xc3804e46ULL, ImplicitList15, ImplicitList45, OperandInfo49 }, // Inst #1779 = PCMPESTRIArm | |
| { 1780, 3, 0, 0, 0, "PCMPESTRIArr", 0, 0xc3804e45ULL, ImplicitList15, ImplicitList45, OperandInfo50 }, // Inst #1780 = PCMPESTRIArr | |
| { 1781, 7, 0, 0, 0, "PCMPESTRICrm", 0|(1<<MCID::MayLoad), 0xc3804e46ULL, ImplicitList15, ImplicitList45, OperandInfo49 }, // Inst #1781 = PCMPESTRICrm | |
| { 1782, 3, 0, 0, 0, "PCMPESTRICrr", 0, 0xc3804e45ULL, ImplicitList15, ImplicitList45, OperandInfo50 }, // Inst #1782 = PCMPESTRICrr | |
| { 1783, 7, 0, 0, 0, "PCMPESTRIOrm", 0|(1<<MCID::MayLoad), 0xc3804e46ULL, ImplicitList15, ImplicitList45, OperandInfo49 }, // Inst #1783 = PCMPESTRIOrm | |
| { 1784, 3, 0, 0, 0, "PCMPESTRIOrr", 0, 0xc3804e45ULL, ImplicitList15, ImplicitList45, OperandInfo50 }, // Inst #1784 = PCMPESTRIOrr | |
| { 1785, 7, 0, 0, 0, "PCMPESTRISrm", 0|(1<<MCID::MayLoad), 0xc3804e46ULL, ImplicitList15, ImplicitList45, OperandInfo49 }, // Inst #1785 = PCMPESTRISrm | |
| { 1786, 3, 0, 0, 0, "PCMPESTRISrr", 0, 0xc3804e45ULL, ImplicitList15, ImplicitList45, OperandInfo50 }, // Inst #1786 = PCMPESTRISrr | |
| { 1787, 7, 0, 0, 0, "PCMPESTRIZrm", 0|(1<<MCID::MayLoad), 0xc3804e46ULL, ImplicitList15, ImplicitList45, OperandInfo49 }, // Inst #1787 = PCMPESTRIZrm | |
| { 1788, 3, 0, 0, 0, "PCMPESTRIZrr", 0, 0xc3804e45ULL, ImplicitList15, ImplicitList45, OperandInfo50 }, // Inst #1788 = PCMPESTRIZrr | |
| { 1789, 7, 0, 0, 0, "PCMPESTRIrm", 0|(1<<MCID::MayLoad), 0xc3804e46ULL, ImplicitList15, ImplicitList45, OperandInfo49 }, // Inst #1789 = PCMPESTRIrm | |
| { 1790, 3, 0, 0, 0, "PCMPESTRIrr", 0, 0xc3804e45ULL, ImplicitList15, ImplicitList45, OperandInfo50 }, // Inst #1790 = PCMPESTRIrr | |
| { 1791, 8, 1, 0, 0, "PCMPESTRM128MEM", 0|(1<<MCID::MayLoad)|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList15, ImplicitList1, OperandInfo136 }, // Inst #1791 = PCMPESTRM128MEM | |
| { 1792, 4, 1, 0, 0, "PCMPESTRM128REG", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList15, ImplicitList1, OperandInfo86 }, // Inst #1792 = PCMPESTRM128REG | |
| { 1793, 7, 0, 0, 0, "PCMPESTRM128rm", 0|(1<<MCID::UnmodeledSideEffects), 0xc1804e46ULL, ImplicitList15, ImplicitList46, OperandInfo49 }, // Inst #1793 = PCMPESTRM128rm | |
| { 1794, 3, 0, 0, 0, "PCMPESTRM128rr", 0|(1<<MCID::UnmodeledSideEffects), 0xc1804e45ULL, ImplicitList15, ImplicitList46, OperandInfo50 }, // Inst #1794 = PCMPESTRM128rr | |
| { 1795, 7, 1, 0, 0, "PCMPGTBrm", 0|(1<<MCID::MayLoad), 0xc9800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1795 = PCMPGTBrm | |
| { 1796, 3, 1, 0, 0, "PCMPGTBrr", 0, 0xc9800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1796 = PCMPGTBrr | |
| { 1797, 7, 1, 0, 0, "PCMPGTDrm", 0|(1<<MCID::MayLoad), 0xcd800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1797 = PCMPGTDrm | |
| { 1798, 3, 1, 0, 0, "PCMPGTDrr", 0, 0xcd800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1798 = PCMPGTDrr | |
| { 1799, 7, 1, 0, 0, "PCMPGTQrm", 0|(1<<MCID::MayLoad), 0x6f800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1799 = PCMPGTQrm | |
| { 1800, 3, 1, 0, 0, "PCMPGTQrr", 0, 0x6f800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1800 = PCMPGTQrr | |
| { 1801, 7, 1, 0, 0, "PCMPGTWrm", 0|(1<<MCID::MayLoad), 0xcb800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1801 = PCMPGTWrm | |
| { 1802, 3, 1, 0, 0, "PCMPGTWrr", 0, 0xcb800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1802 = PCMPGTWrr | |
| { 1803, 7, 0, 0, 0, "PCMPISTRIArm", 0|(1<<MCID::MayLoad), 0xc7804e46ULL, NULL, ImplicitList45, OperandInfo49 }, // Inst #1803 = PCMPISTRIArm | |
| { 1804, 3, 0, 0, 0, "PCMPISTRIArr", 0, 0xc7804e45ULL, NULL, ImplicitList45, OperandInfo50 }, // Inst #1804 = PCMPISTRIArr | |
| { 1805, 7, 0, 0, 0, "PCMPISTRICrm", 0|(1<<MCID::MayLoad), 0xc7804e46ULL, NULL, ImplicitList45, OperandInfo49 }, // Inst #1805 = PCMPISTRICrm | |
| { 1806, 3, 0, 0, 0, "PCMPISTRICrr", 0, 0xc7804e45ULL, NULL, ImplicitList45, OperandInfo50 }, // Inst #1806 = PCMPISTRICrr | |
| { 1807, 7, 0, 0, 0, "PCMPISTRIOrm", 0|(1<<MCID::MayLoad), 0xc7804e46ULL, NULL, ImplicitList45, OperandInfo49 }, // Inst #1807 = PCMPISTRIOrm | |
| { 1808, 3, 0, 0, 0, "PCMPISTRIOrr", 0, 0xc7804e45ULL, NULL, ImplicitList45, OperandInfo50 }, // Inst #1808 = PCMPISTRIOrr | |
| { 1809, 7, 0, 0, 0, "PCMPISTRISrm", 0|(1<<MCID::MayLoad), 0xc7804e46ULL, NULL, ImplicitList45, OperandInfo49 }, // Inst #1809 = PCMPISTRISrm | |
| { 1810, 3, 0, 0, 0, "PCMPISTRISrr", 0, 0xc7804e45ULL, NULL, ImplicitList45, OperandInfo50 }, // Inst #1810 = PCMPISTRISrr | |
| { 1811, 7, 0, 0, 0, "PCMPISTRIZrm", 0|(1<<MCID::MayLoad), 0xc7804e46ULL, NULL, ImplicitList45, OperandInfo49 }, // Inst #1811 = PCMPISTRIZrm | |
| { 1812, 3, 0, 0, 0, "PCMPISTRIZrr", 0, 0xc7804e45ULL, NULL, ImplicitList45, OperandInfo50 }, // Inst #1812 = PCMPISTRIZrr | |
| { 1813, 7, 0, 0, 0, "PCMPISTRIrm", 0|(1<<MCID::MayLoad), 0xc7804e46ULL, NULL, ImplicitList45, OperandInfo49 }, // Inst #1813 = PCMPISTRIrm | |
| { 1814, 3, 0, 0, 0, "PCMPISTRIrr", 0, 0xc7804e45ULL, NULL, ImplicitList45, OperandInfo50 }, // Inst #1814 = PCMPISTRIrr | |
| { 1815, 8, 1, 0, 0, "PCMPISTRM128MEM", 0|(1<<MCID::MayLoad)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo136 }, // Inst #1815 = PCMPISTRM128MEM | |
| { 1816, 4, 1, 0, 0, "PCMPISTRM128REG", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo86 }, // Inst #1816 = PCMPISTRM128REG | |
| { 1817, 7, 0, 0, 0, "PCMPISTRM128rm", 0|(1<<MCID::UnmodeledSideEffects), 0xc5804e46ULL, NULL, ImplicitList46, OperandInfo49 }, // Inst #1817 = PCMPISTRM128rm | |
| { 1818, 3, 0, 0, 0, "PCMPISTRM128rr", 0|(1<<MCID::UnmodeledSideEffects), 0xc5804e45ULL, NULL, ImplicitList46, OperandInfo50 }, // Inst #1818 = PCMPISTRM128rr | |
| { 1819, 7, 0, 0, 0, "PEXTRBmr", 0|(1<<MCID::UnmodeledSideEffects), 0x29804e44ULL, NULL, NULL, OperandInfo115 }, // Inst #1819 = PEXTRBmr | |
| { 1820, 3, 1, 0, 0, "PEXTRBrr", 0, 0x29804e43ULL, NULL, NULL, OperandInfo116 }, // Inst #1820 = PEXTRBrr | |
| { 1821, 7, 0, 0, 0, "PEXTRDmr", 0|(1<<MCID::MayStore), 0x2d804e44ULL, NULL, NULL, OperandInfo115 }, // Inst #1821 = PEXTRDmr | |
| { 1822, 3, 1, 0, 0, "PEXTRDrr", 0, 0x2d804e43ULL, NULL, NULL, OperandInfo116 }, // Inst #1822 = PEXTRDrr | |
| { 1823, 7, 0, 0, 0, "PEXTRQmr", 0|(1<<MCID::MayStore), 0x2d806e44ULL, NULL, NULL, OperandInfo115 }, // Inst #1823 = PEXTRQmr | |
| { 1824, 3, 1, 0, 0, "PEXTRQrr", 0, 0x2d806e43ULL, NULL, NULL, OperandInfo200 }, // Inst #1824 = PEXTRQrr | |
| { 1825, 7, 0, 0, 0, "PEXTRWmr", 0|(1<<MCID::UnmodeledSideEffects), 0x2b804e44ULL, NULL, NULL, OperandInfo115 }, // Inst #1825 = PEXTRWmr | |
| { 1826, 3, 1, 0, 0, "PEXTRWri", 0, 0x18b804145ULL, NULL, NULL, OperandInfo116 }, // Inst #1826 = PEXTRWri | |
| { 1827, 6, 1, 0, 0, "PF2IDrm", 0|(1<<MCID::MayLoad), 0x803a000106ULL, NULL, NULL, OperandInfo145 }, // Inst #1827 = PF2IDrm | |
| { 1828, 2, 1, 0, 0, "PF2IDrr", 0, 0x803a000105ULL, NULL, NULL, OperandInfo149 }, // Inst #1828 = PF2IDrr | |
| { 1829, 6, 1, 0, 0, "PF2IWrm", 0|(1<<MCID::MayLoad), 0x8038000106ULL, NULL, NULL, OperandInfo145 }, // Inst #1829 = PF2IWrm | |
| { 1830, 2, 1, 0, 0, "PF2IWrr", 0, 0x8038000105ULL, NULL, NULL, OperandInfo149 }, // Inst #1830 = PF2IWrr | |
| { 1831, 7, 1, 0, 0, "PFACCrm", 0|(1<<MCID::MayLoad), 0x815c000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1831 = PFACCrm | |
| { 1832, 3, 1, 0, 0, "PFACCrr", 0, 0x815c000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1832 = PFACCrr | |
| { 1833, 7, 1, 0, 0, "PFADDrm", 0|(1<<MCID::MayLoad), 0x813c000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1833 = PFADDrm | |
| { 1834, 3, 1, 0, 0, "PFADDrr", 0, 0x813c000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1834 = PFADDrr | |
| { 1835, 7, 1, 0, 0, "PFCMPEQrm", 0|(1<<MCID::MayLoad), 0x8160000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1835 = PFCMPEQrm | |
| { 1836, 3, 1, 0, 0, "PFCMPEQrr", 0, 0x8160000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1836 = PFCMPEQrr | |
| { 1837, 7, 1, 0, 0, "PFCMPGErm", 0|(1<<MCID::MayLoad), 0x8120000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1837 = PFCMPGErm | |
| { 1838, 3, 1, 0, 0, "PFCMPGErr", 0, 0x8120000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1838 = PFCMPGErr | |
| { 1839, 7, 1, 0, 0, "PFCMPGTrm", 0|(1<<MCID::MayLoad), 0x8140000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1839 = PFCMPGTrm | |
| { 1840, 3, 1, 0, 0, "PFCMPGTrr", 0, 0x8140000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1840 = PFCMPGTrr | |
| { 1841, 7, 1, 0, 0, "PFMAXrm", 0|(1<<MCID::MayLoad), 0x8148000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1841 = PFMAXrm | |
| { 1842, 3, 1, 0, 0, "PFMAXrr", 0, 0x8148000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1842 = PFMAXrr | |
| { 1843, 7, 1, 0, 0, "PFMINrm", 0|(1<<MCID::MayLoad), 0x8128000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1843 = PFMINrm | |
| { 1844, 3, 1, 0, 0, "PFMINrr", 0, 0x8128000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1844 = PFMINrr | |
| { 1845, 7, 1, 0, 0, "PFMULrm", 0|(1<<MCID::MayLoad), 0x8168000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1845 = PFMULrm | |
| { 1846, 3, 1, 0, 0, "PFMULrr", 0, 0x8168000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1846 = PFMULrr | |
| { 1847, 7, 1, 0, 0, "PFNACCrm", 0|(1<<MCID::MayLoad), 0x8114000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1847 = PFNACCrm | |
| { 1848, 3, 1, 0, 0, "PFNACCrr", 0, 0x8114000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1848 = PFNACCrr | |
| { 1849, 7, 1, 0, 0, "PFPNACCrm", 0|(1<<MCID::MayLoad), 0x811c000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1849 = PFPNACCrm | |
| { 1850, 3, 1, 0, 0, "PFPNACCrr", 0, 0x811c000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1850 = PFPNACCrr | |
| { 1851, 7, 1, 0, 0, "PFRCPIT1rm", 0|(1<<MCID::MayLoad), 0x814c000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1851 = PFRCPIT1rm | |
| { 1852, 3, 1, 0, 0, "PFRCPIT1rr", 0, 0x814c000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1852 = PFRCPIT1rr | |
| { 1853, 7, 1, 0, 0, "PFRCPIT2rm", 0|(1<<MCID::MayLoad), 0x816c000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1853 = PFRCPIT2rm | |
| { 1854, 3, 1, 0, 0, "PFRCPIT2rr", 0, 0x816c000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1854 = PFRCPIT2rr | |
| { 1855, 6, 1, 0, 0, "PFRCPrm", 0|(1<<MCID::MayLoad), 0x812c000106ULL, NULL, NULL, OperandInfo145 }, // Inst #1855 = PFRCPrm | |
| { 1856, 2, 1, 0, 0, "PFRCPrr", 0, 0x812c000105ULL, NULL, NULL, OperandInfo149 }, // Inst #1856 = PFRCPrr | |
| { 1857, 7, 1, 0, 0, "PFRSQIT1rm", 0|(1<<MCID::MayLoad), 0x814e000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1857 = PFRSQIT1rm | |
| { 1858, 3, 1, 0, 0, "PFRSQIT1rr", 0, 0x814e000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1858 = PFRSQIT1rr | |
| { 1859, 6, 1, 0, 0, "PFRSQRTrm", 0|(1<<MCID::MayLoad), 0x812e000106ULL, NULL, NULL, OperandInfo145 }, // Inst #1859 = PFRSQRTrm | |
| { 1860, 2, 1, 0, 0, "PFRSQRTrr", 0, 0x812e000105ULL, NULL, NULL, OperandInfo149 }, // Inst #1860 = PFRSQRTrr | |
| { 1861, 7, 1, 0, 0, "PFSUBRrm", 0|(1<<MCID::MayLoad), 0x8154000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1861 = PFSUBRrm | |
| { 1862, 3, 1, 0, 0, "PFSUBRrr", 0, 0x8154000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1862 = PFSUBRrr | |
| { 1863, 7, 1, 0, 0, "PFSUBrm", 0|(1<<MCID::MayLoad), 0x8134000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1863 = PFSUBrm | |
| { 1864, 3, 1, 0, 0, "PFSUBrr", 0, 0x8134000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1864 = PFSUBrr | |
| { 1865, 7, 1, 0, 0, "PHADDDrm128", 0|(1<<MCID::MayLoad), 0x5800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1865 = PHADDDrm128 | |
| { 1866, 3, 1, 0, 0, "PHADDDrr128", 0, 0x5800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1866 = PHADDDrr128 | |
| { 1867, 7, 1, 0, 0, "PHADDSWrm128", 0|(1<<MCID::MayLoad), 0x7800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1867 = PHADDSWrm128 | |
| { 1868, 3, 1, 0, 0, "PHADDSWrr128", 0, 0x7800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1868 = PHADDSWrr128 | |
| { 1869, 7, 1, 0, 0, "PHADDWrm128", 0|(1<<MCID::MayLoad), 0x3800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1869 = PHADDWrm128 | |
| { 1870, 3, 1, 0, 0, "PHADDWrr128", 0, 0x3800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1870 = PHADDWrr128 | |
| { 1871, 6, 1, 0, 0, "PHMINPOSUWrm128", 0|(1<<MCID::MayLoad), 0x83800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #1871 = PHMINPOSUWrm128 | |
| { 1872, 2, 1, 0, 0, "PHMINPOSUWrr128", 0, 0x83800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #1872 = PHMINPOSUWrr128 | |
| { 1873, 7, 1, 0, 0, "PHSUBDrm128", 0|(1<<MCID::MayLoad), 0xd800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1873 = PHSUBDrm128 | |
| { 1874, 3, 1, 0, 0, "PHSUBDrr128", 0, 0xd800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1874 = PHSUBDrr128 | |
| { 1875, 7, 1, 0, 0, "PHSUBSWrm128", 0|(1<<MCID::MayLoad), 0xf800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1875 = PHSUBSWrm128 | |
| { 1876, 3, 1, 0, 0, "PHSUBSWrr128", 0, 0xf800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1876 = PHSUBSWrr128 | |
| { 1877, 7, 1, 0, 0, "PHSUBWrm128", 0|(1<<MCID::MayLoad), 0xb800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1877 = PHSUBWrm128 | |
| { 1878, 3, 1, 0, 0, "PHSUBWrr128", 0, 0xb800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1878 = PHSUBWrr128 | |
| { 1879, 6, 1, 0, 0, "PI2FDrm", 0|(1<<MCID::MayLoad), 0x801a000106ULL, NULL, NULL, OperandInfo145 }, // Inst #1879 = PI2FDrm | |
| { 1880, 2, 1, 0, 0, "PI2FDrr", 0, 0x801a000105ULL, NULL, NULL, OperandInfo149 }, // Inst #1880 = PI2FDrr | |
| { 1881, 6, 1, 0, 0, "PI2FWrm", 0|(1<<MCID::MayLoad), 0x8018000106ULL, NULL, NULL, OperandInfo145 }, // Inst #1881 = PI2FWrm | |
| { 1882, 2, 1, 0, 0, "PI2FWrr", 0, 0x8018000105ULL, NULL, NULL, OperandInfo149 }, // Inst #1882 = PI2FWrr | |
| { 1883, 8, 1, 0, 0, "PINSRBrm", 0|(1<<MCID::MayLoad), 0x41804e46ULL, NULL, NULL, OperandInfo63 }, // Inst #1883 = PINSRBrm | |
| { 1884, 4, 1, 0, 0, "PINSRBrr", 0, 0x41804e45ULL, NULL, NULL, OperandInfo201 }, // Inst #1884 = PINSRBrr | |
| { 1885, 8, 1, 0, 0, "PINSRDrm", 0|(1<<MCID::MayLoad), 0x45804e46ULL, NULL, NULL, OperandInfo63 }, // Inst #1885 = PINSRDrm | |
| { 1886, 4, 1, 0, 0, "PINSRDrr", 0, 0x45804e45ULL, NULL, NULL, OperandInfo201 }, // Inst #1886 = PINSRDrr | |
| { 1887, 8, 1, 0, 0, "PINSRQrm", 0|(1<<MCID::MayLoad), 0x45806e46ULL, NULL, NULL, OperandInfo63 }, // Inst #1887 = PINSRQrm | |
| { 1888, 4, 1, 0, 0, "PINSRQrr", 0, 0x45806e45ULL, NULL, NULL, OperandInfo202 }, // Inst #1888 = PINSRQrr | |
| { 1889, 8, 1, 0, 0, "PINSRWrmi", 0|(1<<MCID::MayLoad), 0x189804146ULL, NULL, NULL, OperandInfo63 }, // Inst #1889 = PINSRWrmi | |
| { 1890, 4, 1, 0, 0, "PINSRWrri", 0, 0x189804145ULL, NULL, NULL, OperandInfo201 }, // Inst #1890 = PINSRWrri | |
| { 1891, 7, 1, 0, 0, "PMADDUBSWrm128", 0|(1<<MCID::MayLoad), 0x9800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1891 = PMADDUBSWrm128 | |
| { 1892, 3, 1, 0, 0, "PMADDUBSWrr128", 0, 0x9800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1892 = PMADDUBSWrr128 | |
| { 1893, 7, 1, 0, 0, "PMADDWDrm", 0|(1<<MCID::MayLoad), 0x1eb800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1893 = PMADDWDrm | |
| { 1894, 3, 1, 0, 0, "PMADDWDrr", 0|(1<<MCID::Commutable), 0x1eb800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1894 = PMADDWDrr | |
| { 1895, 7, 1, 0, 0, "PMAXSBrm", 0|(1<<MCID::MayLoad), 0x79800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1895 = PMAXSBrm | |
| { 1896, 3, 1, 0, 0, "PMAXSBrr", 0|(1<<MCID::Commutable), 0x79800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1896 = PMAXSBrr | |
| { 1897, 7, 1, 0, 0, "PMAXSDrm", 0|(1<<MCID::MayLoad), 0x7b800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1897 = PMAXSDrm | |
| { 1898, 3, 1, 0, 0, "PMAXSDrr", 0|(1<<MCID::Commutable), 0x7b800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1898 = PMAXSDrr | |
| { 1899, 7, 1, 0, 0, "PMAXSWrm", 0|(1<<MCID::MayLoad), 0x1dd800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1899 = PMAXSWrm | |
| { 1900, 3, 1, 0, 0, "PMAXSWrr", 0|(1<<MCID::Commutable), 0x1dd800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1900 = PMAXSWrr | |
| { 1901, 7, 1, 0, 0, "PMAXUBrm", 0|(1<<MCID::MayLoad), 0x1bd800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1901 = PMAXUBrm | |
| { 1902, 3, 1, 0, 0, "PMAXUBrr", 0|(1<<MCID::Commutable), 0x1bd800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1902 = PMAXUBrr | |
| { 1903, 7, 1, 0, 0, "PMAXUDrm", 0|(1<<MCID::MayLoad), 0x7f800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1903 = PMAXUDrm | |
| { 1904, 3, 1, 0, 0, "PMAXUDrr", 0|(1<<MCID::Commutable), 0x7f800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1904 = PMAXUDrr | |
| { 1905, 7, 1, 0, 0, "PMAXUWrm", 0|(1<<MCID::MayLoad), 0x7d800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1905 = PMAXUWrm | |
| { 1906, 3, 1, 0, 0, "PMAXUWrr", 0|(1<<MCID::Commutable), 0x7d800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1906 = PMAXUWrr | |
| { 1907, 7, 1, 0, 0, "PMINSBrm", 0|(1<<MCID::MayLoad), 0x71800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1907 = PMINSBrm | |
| { 1908, 3, 1, 0, 0, "PMINSBrr", 0|(1<<MCID::Commutable), 0x71800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1908 = PMINSBrr | |
| { 1909, 7, 1, 0, 0, "PMINSDrm", 0|(1<<MCID::MayLoad), 0x73800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1909 = PMINSDrm | |
| { 1910, 3, 1, 0, 0, "PMINSDrr", 0|(1<<MCID::Commutable), 0x73800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1910 = PMINSDrr | |
| { 1911, 7, 1, 0, 0, "PMINSWrm", 0|(1<<MCID::MayLoad), 0x1d5800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1911 = PMINSWrm | |
| { 1912, 3, 1, 0, 0, "PMINSWrr", 0|(1<<MCID::Commutable), 0x1d5800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1912 = PMINSWrr | |
| { 1913, 7, 1, 0, 0, "PMINUBrm", 0|(1<<MCID::MayLoad), 0x1b5800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1913 = PMINUBrm | |
| { 1914, 3, 1, 0, 0, "PMINUBrr", 0|(1<<MCID::Commutable), 0x1b5800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1914 = PMINUBrr | |
| { 1915, 7, 1, 0, 0, "PMINUDrm", 0|(1<<MCID::MayLoad), 0x77800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1915 = PMINUDrm | |
| { 1916, 3, 1, 0, 0, "PMINUDrr", 0|(1<<MCID::Commutable), 0x77800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1916 = PMINUDrr | |
| { 1917, 7, 1, 0, 0, "PMINUWrm", 0|(1<<MCID::MayLoad), 0x75800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1917 = PMINUWrm | |
| { 1918, 3, 1, 0, 0, "PMINUWrr", 0|(1<<MCID::Commutable), 0x75800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1918 = PMINUWrr | |
| { 1919, 2, 1, 0, 0, "PMOVMSKBrr", 0, 0x1af800145ULL, NULL, NULL, OperandInfo98 }, // Inst #1919 = PMOVMSKBrr | |
| { 1920, 6, 1, 0, 0, "PMOVSXBDrm", 0|(1<<MCID::MayLoad), 0x43800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #1920 = PMOVSXBDrm | |
| { 1921, 2, 1, 0, 0, "PMOVSXBDrr", 0, 0x43800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #1921 = PMOVSXBDrr | |
| { 1922, 6, 1, 0, 0, "PMOVSXBQrm", 0|(1<<MCID::MayLoad), 0x45800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #1922 = PMOVSXBQrm | |
| { 1923, 2, 1, 0, 0, "PMOVSXBQrr", 0, 0x45800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #1923 = PMOVSXBQrr | |
| { 1924, 6, 1, 0, 0, "PMOVSXBWrm", 0|(1<<MCID::MayLoad), 0x41800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #1924 = PMOVSXBWrm | |
| { 1925, 2, 1, 0, 0, "PMOVSXBWrr", 0, 0x41800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #1925 = PMOVSXBWrr | |
| { 1926, 6, 1, 0, 0, "PMOVSXDQrm", 0|(1<<MCID::MayLoad), 0x4b800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #1926 = PMOVSXDQrm | |
| { 1927, 2, 1, 0, 0, "PMOVSXDQrr", 0, 0x4b800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #1927 = PMOVSXDQrr | |
| { 1928, 6, 1, 0, 0, "PMOVSXWDrm", 0|(1<<MCID::MayLoad), 0x47800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #1928 = PMOVSXWDrm | |
| { 1929, 2, 1, 0, 0, "PMOVSXWDrr", 0, 0x47800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #1929 = PMOVSXWDrr | |
| { 1930, 6, 1, 0, 0, "PMOVSXWQrm", 0|(1<<MCID::MayLoad), 0x49800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #1930 = PMOVSXWQrm | |
| { 1931, 2, 1, 0, 0, "PMOVSXWQrr", 0, 0x49800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #1931 = PMOVSXWQrr | |
| { 1932, 6, 1, 0, 0, "PMOVZXBDrm", 0|(1<<MCID::MayLoad), 0x63800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #1932 = PMOVZXBDrm | |
| { 1933, 2, 1, 0, 0, "PMOVZXBDrr", 0, 0x63800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #1933 = PMOVZXBDrr | |
| { 1934, 6, 1, 0, 0, "PMOVZXBQrm", 0|(1<<MCID::MayLoad), 0x65800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #1934 = PMOVZXBQrm | |
| { 1935, 2, 1, 0, 0, "PMOVZXBQrr", 0, 0x65800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #1935 = PMOVZXBQrr | |
| { 1936, 6, 1, 0, 0, "PMOVZXBWrm", 0|(1<<MCID::MayLoad), 0x61800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #1936 = PMOVZXBWrm | |
| { 1937, 2, 1, 0, 0, "PMOVZXBWrr", 0, 0x61800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #1937 = PMOVZXBWrr | |
| { 1938, 6, 1, 0, 0, "PMOVZXDQrm", 0|(1<<MCID::MayLoad), 0x6b800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #1938 = PMOVZXDQrm | |
| { 1939, 2, 1, 0, 0, "PMOVZXDQrr", 0, 0x6b800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #1939 = PMOVZXDQrr | |
| { 1940, 6, 1, 0, 0, "PMOVZXWDrm", 0|(1<<MCID::MayLoad), 0x67800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #1940 = PMOVZXWDrm | |
| { 1941, 2, 1, 0, 0, "PMOVZXWDrr", 0, 0x67800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #1941 = PMOVZXWDrr | |
| { 1942, 6, 1, 0, 0, "PMOVZXWQrm", 0|(1<<MCID::MayLoad), 0x69800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #1942 = PMOVZXWQrm | |
| { 1943, 2, 1, 0, 0, "PMOVZXWQrr", 0, 0x69800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #1943 = PMOVZXWQrr | |
| { 1944, 7, 1, 0, 0, "PMULDQrm", 0|(1<<MCID::MayLoad), 0x51800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1944 = PMULDQrm | |
| { 1945, 3, 1, 0, 0, "PMULDQrr", 0|(1<<MCID::Commutable), 0x51800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1945 = PMULDQrr | |
| { 1946, 7, 1, 0, 0, "PMULHRSWrm128", 0|(1<<MCID::MayLoad), 0x17800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1946 = PMULHRSWrm128 | |
| { 1947, 3, 1, 0, 0, "PMULHRSWrr128", 0|(1<<MCID::Commutable), 0x17800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1947 = PMULHRSWrr128 | |
| { 1948, 7, 1, 0, 0, "PMULHRWrm", 0|(1<<MCID::MayLoad), 0x816e000106ULL, NULL, NULL, OperandInfo157 }, // Inst #1948 = PMULHRWrm | |
| { 1949, 3, 1, 0, 0, "PMULHRWrr", 0, 0x816e000105ULL, NULL, NULL, OperandInfo158 }, // Inst #1949 = PMULHRWrr | |
| { 1950, 7, 1, 0, 0, "PMULHUWrm", 0|(1<<MCID::MayLoad), 0x1c9800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1950 = PMULHUWrm | |
| { 1951, 3, 1, 0, 0, "PMULHUWrr", 0|(1<<MCID::Commutable), 0x1c9800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1951 = PMULHUWrr | |
| { 1952, 7, 1, 0, 0, "PMULHWrm", 0|(1<<MCID::MayLoad), 0x1cb800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1952 = PMULHWrm | |
| { 1953, 3, 1, 0, 0, "PMULHWrr", 0|(1<<MCID::Commutable), 0x1cb800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1953 = PMULHWrr | |
| { 1954, 7, 1, 0, 0, "PMULLDrm", 0|(1<<MCID::MayLoad), 0x81800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #1954 = PMULLDrm | |
| { 1955, 3, 1, 0, 0, "PMULLDrr", 0|(1<<MCID::Commutable), 0x81800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #1955 = PMULLDrr | |
| { 1956, 7, 1, 0, 0, "PMULLWrm", 0|(1<<MCID::MayLoad), 0x1ab800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1956 = PMULLWrm | |
| { 1957, 3, 1, 0, 0, "PMULLWrr", 0|(1<<MCID::Commutable), 0x1ab800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1957 = PMULLWrr | |
| { 1958, 7, 1, 0, 0, "PMULUDQrm", 0|(1<<MCID::MayLoad), 0x1e9800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1958 = PMULUDQrm | |
| { 1959, 3, 1, 0, 0, "PMULUDQrr", 0|(1<<MCID::Commutable), 0x1e9800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1959 = PMULUDQrr | |
| { 1960, 1, 1, 0, 0, "POP16r", 0|(1<<MCID::MayLoad), 0xb0000042ULL, ImplicitList6, ImplicitList6, OperandInfo113 }, // Inst #1960 = POP16r | |
| { 1961, 5, 1, 0, 0, "POP16rmm", 0|(1<<MCID::MayLoad), 0x11e000058ULL, ImplicitList6, ImplicitList6, OperandInfo38 }, // Inst #1961 = POP16rmm | |
| { 1962, 1, 1, 0, 0, "POP16rmr", 0|(1<<MCID::MayLoad), 0x11e000050ULL, ImplicitList6, ImplicitList6, OperandInfo113 }, // Inst #1962 = POP16rmr | |
| { 1963, 1, 1, 0, 0, "POP32r", 0|(1<<MCID::MayLoad), 0xb0000002ULL, ImplicitList6, ImplicitList6, OperandInfo72 }, // Inst #1963 = POP32r | |
| { 1964, 5, 1, 0, 0, "POP32rmm", 0|(1<<MCID::MayLoad), 0x11e000018ULL, ImplicitList6, ImplicitList6, OperandInfo38 }, // Inst #1964 = POP32rmm | |
| { 1965, 1, 1, 0, 0, "POP32rmr", 0|(1<<MCID::MayLoad), 0x11e000010ULL, ImplicitList6, ImplicitList6, OperandInfo72 }, // Inst #1965 = POP32rmr | |
| { 1966, 1, 1, 0, 0, "POP64r", 0|(1<<MCID::MayLoad), 0xb0000002ULL, ImplicitList8, ImplicitList8, OperandInfo74 }, // Inst #1966 = POP64r | |
| { 1967, 5, 1, 0, 0, "POP64rmm", 0|(1<<MCID::MayLoad), 0x11e000018ULL, ImplicitList8, ImplicitList8, OperandInfo38 }, // Inst #1967 = POP64rmm | |
| { 1968, 1, 1, 0, 0, "POP64rmr", 0|(1<<MCID::MayLoad), 0x11e000010ULL, ImplicitList8, ImplicitList8, OperandInfo74 }, // Inst #1968 = POP64rmr | |
| { 1969, 0, 0, 0, 0, "POPA32", 0|(1<<MCID::MayLoad), 0xc2000001ULL, ImplicitList6, ImplicitList47, 0 }, // Inst #1969 = POPA32 | |
| { 1970, 6, 1, 0, 0, "POPCNT16rm", 0|(1<<MCID::MayLoad), 0x170000c46ULL, NULL, ImplicitList1, OperandInfo11 }, // Inst #1970 = POPCNT16rm | |
| { 1971, 2, 1, 0, 0, "POPCNT16rr", 0, 0x170000c45ULL, NULL, ImplicitList1, OperandInfo55 }, // Inst #1971 = POPCNT16rr | |
| { 1972, 6, 1, 0, 0, "POPCNT32rm", 0|(1<<MCID::MayLoad), 0x170000c06ULL, NULL, ImplicitList1, OperandInfo12 }, // Inst #1972 = POPCNT32rm | |
| { 1973, 2, 1, 0, 0, "POPCNT32rr", 0, 0x170000c05ULL, NULL, ImplicitList1, OperandInfo65 }, // Inst #1973 = POPCNT32rr | |
| { 1974, 6, 1, 0, 0, "POPCNT64rm", 0|(1<<MCID::MayLoad), 0x170002c06ULL, NULL, ImplicitList1, OperandInfo13 }, // Inst #1974 = POPCNT64rm | |
| { 1975, 2, 1, 0, 0, "POPCNT64rr", 0, 0x170002c05ULL, NULL, ImplicitList1, OperandInfo66 }, // Inst #1975 = POPCNT64rr | |
| { 1976, 0, 0, 0, 0, "POPDS16", 0|(1<<MCID::UnmodeledSideEffects), 0x3e000041ULL, NULL, NULL, 0 }, // Inst #1976 = POPDS16 | |
| { 1977, 0, 0, 0, 0, "POPDS32", 0|(1<<MCID::UnmodeledSideEffects), 0x3e000001ULL, NULL, NULL, 0 }, // Inst #1977 = POPDS32 | |
| { 1978, 0, 0, 0, 0, "POPES16", 0|(1<<MCID::UnmodeledSideEffects), 0xe000041ULL, NULL, NULL, 0 }, // Inst #1978 = POPES16 | |
| { 1979, 0, 0, 0, 0, "POPES32", 0|(1<<MCID::UnmodeledSideEffects), 0xe000001ULL, NULL, NULL, 0 }, // Inst #1979 = POPES32 | |
| { 1980, 0, 0, 0, 0, "POPF16", 0|(1<<MCID::MayLoad), 0x13a000041ULL, ImplicitList6, ImplicitList6, 0 }, // Inst #1980 = POPF16 | |
| { 1981, 0, 0, 0, 0, "POPF32", 0|(1<<MCID::MayLoad), 0x13a000001ULL, ImplicitList6, ImplicitList6, 0 }, // Inst #1981 = POPF32 | |
| { 1982, 0, 0, 0, 0, "POPF64", 0|(1<<MCID::MayLoad), 0x13a000001ULL, ImplicitList8, ImplicitList9, 0 }, // Inst #1982 = POPF64 | |
| { 1983, 0, 0, 0, 0, "POPFS16", 0|(1<<MCID::UnmodeledSideEffects), 0x142000141ULL, NULL, NULL, 0 }, // Inst #1983 = POPFS16 | |
| { 1984, 0, 0, 0, 0, "POPFS32", 0|(1<<MCID::UnmodeledSideEffects), 0x142000101ULL, NULL, NULL, 0 }, // Inst #1984 = POPFS32 | |
| { 1985, 0, 0, 0, 0, "POPFS64", 0|(1<<MCID::UnmodeledSideEffects), 0x142000101ULL, NULL, NULL, 0 }, // Inst #1985 = POPFS64 | |
| { 1986, 0, 0, 0, 0, "POPGS16", 0|(1<<MCID::UnmodeledSideEffects), 0x152000141ULL, NULL, NULL, 0 }, // Inst #1986 = POPGS16 | |
| { 1987, 0, 0, 0, 0, "POPGS32", 0|(1<<MCID::UnmodeledSideEffects), 0x152000101ULL, NULL, NULL, 0 }, // Inst #1987 = POPGS32 | |
| { 1988, 0, 0, 0, 0, "POPGS64", 0|(1<<MCID::UnmodeledSideEffects), 0x152000101ULL, NULL, NULL, 0 }, // Inst #1988 = POPGS64 | |
| { 1989, 0, 0, 0, 0, "POPSS16", 0|(1<<MCID::UnmodeledSideEffects), 0x2e000041ULL, NULL, NULL, 0 }, // Inst #1989 = POPSS16 | |
| { 1990, 0, 0, 0, 0, "POPSS32", 0|(1<<MCID::UnmodeledSideEffects), 0x2e000001ULL, NULL, NULL, 0 }, // Inst #1990 = POPSS32 | |
| { 1991, 7, 1, 0, 0, "PORrm", 0|(1<<MCID::MayLoad), 0x1d7800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1991 = PORrm | |
| { 1992, 3, 1, 0, 0, "PORrr", 0|(1<<MCID::Commutable), 0x1d7800145ULL, NULL, NULL, OperandInfo33 }, // Inst #1992 = PORrr | |
| { 1993, 5, 0, 0, 0, "PREFETCH", 0|(1<<MCID::UnmodeledSideEffects), 0x1a000118ULL, NULL, NULL, OperandInfo38 }, // Inst #1993 = PREFETCH | |
| { 1994, 5, 0, 0, 0, "PREFETCHNTA", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x30800118ULL, NULL, NULL, OperandInfo38 }, // Inst #1994 = PREFETCHNTA | |
| { 1995, 5, 0, 0, 0, "PREFETCHT0", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x30800119ULL, NULL, NULL, OperandInfo38 }, // Inst #1995 = PREFETCHT0 | |
| { 1996, 5, 0, 0, 0, "PREFETCHT1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x3080011aULL, NULL, NULL, OperandInfo38 }, // Inst #1996 = PREFETCHT1 | |
| { 1997, 5, 0, 0, 0, "PREFETCHT2", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x3080011bULL, NULL, NULL, OperandInfo38 }, // Inst #1997 = PREFETCHT2 | |
| { 1998, 5, 0, 0, 0, "PREFETCHW", 0|(1<<MCID::UnmodeledSideEffects), 0x1a000119ULL, NULL, NULL, OperandInfo38 }, // Inst #1998 = PREFETCHW | |
| { 1999, 7, 1, 0, 0, "PSADBWrm", 0|(1<<MCID::MayLoad), 0x1ed800146ULL, NULL, NULL, OperandInfo32 }, // Inst #1999 = PSADBWrm | |
| { 2000, 3, 1, 0, 0, "PSADBWrr", 0|(1<<MCID::Commutable), 0x1ed800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2000 = PSADBWrr | |
| { 2001, 7, 1, 0, 0, "PSHUFBrm128", 0|(1<<MCID::MayLoad), 0x1800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #2001 = PSHUFBrm128 | |
| { 2002, 3, 1, 0, 0, "PSHUFBrr128", 0, 0x1800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #2002 = PSHUFBrr128 | |
| { 2003, 7, 1, 0, 0, "PSHUFDmi", 0|(1<<MCID::MayLoad), 0xe1804146ULL, NULL, NULL, OperandInfo49 }, // Inst #2003 = PSHUFDmi | |
| { 2004, 3, 1, 0, 0, "PSHUFDri", 0, 0xe1804145ULL, NULL, NULL, OperandInfo50 }, // Inst #2004 = PSHUFDri | |
| { 2005, 7, 1, 0, 0, "PSHUFHWmi", 0|(1<<MCID::MayLoad), 0xe1804c06ULL, NULL, NULL, OperandInfo49 }, // Inst #2005 = PSHUFHWmi | |
| { 2006, 3, 1, 0, 0, "PSHUFHWri", 0, 0xe1804c05ULL, NULL, NULL, OperandInfo50 }, // Inst #2006 = PSHUFHWri | |
| { 2007, 7, 1, 0, 0, "PSHUFLWmi", 0|(1<<MCID::MayLoad), 0xe1804b06ULL, NULL, NULL, OperandInfo49 }, // Inst #2007 = PSHUFLWmi | |
| { 2008, 3, 1, 0, 0, "PSHUFLWri", 0, 0xe1804b05ULL, NULL, NULL, OperandInfo50 }, // Inst #2008 = PSHUFLWri | |
| { 2009, 7, 1, 0, 0, "PSIGNBrm128", 0|(1<<MCID::MayLoad), 0x11800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #2009 = PSIGNBrm128 | |
| { 2010, 3, 1, 0, 0, "PSIGNBrr128", 0, 0x11800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #2010 = PSIGNBrr128 | |
| { 2011, 7, 1, 0, 0, "PSIGNDrm128", 0|(1<<MCID::MayLoad), 0x15800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #2011 = PSIGNDrm128 | |
| { 2012, 3, 1, 0, 0, "PSIGNDrr128", 0, 0x15800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #2012 = PSIGNDrr128 | |
| { 2013, 7, 1, 0, 0, "PSIGNWrm128", 0|(1<<MCID::MayLoad), 0x13800d46ULL, NULL, NULL, OperandInfo32 }, // Inst #2013 = PSIGNWrm128 | |
| { 2014, 3, 1, 0, 0, "PSIGNWrr128", 0, 0x13800d45ULL, NULL, NULL, OperandInfo33 }, // Inst #2014 = PSIGNWrr128 | |
| { 2015, 3, 1, 0, 0, "PSLLDQri", 0, 0xe7804157ULL, NULL, NULL, OperandInfo203 }, // Inst #2015 = PSLLDQri | |
| { 2016, 3, 1, 0, 0, "PSLLDri", 0, 0xe5804156ULL, NULL, NULL, OperandInfo203 }, // Inst #2016 = PSLLDri | |
| { 2017, 7, 1, 0, 0, "PSLLDrm", 0|(1<<MCID::MayLoad), 0x1e5800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2017 = PSLLDrm | |
| { 2018, 3, 1, 0, 0, "PSLLDrr", 0, 0x1e5800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2018 = PSLLDrr | |
| { 2019, 3, 1, 0, 0, "PSLLQri", 0, 0xe7804156ULL, NULL, NULL, OperandInfo203 }, // Inst #2019 = PSLLQri | |
| { 2020, 7, 1, 0, 0, "PSLLQrm", 0|(1<<MCID::MayLoad), 0x1e7800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2020 = PSLLQrm | |
| { 2021, 3, 1, 0, 0, "PSLLQrr", 0, 0x1e7800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2021 = PSLLQrr | |
| { 2022, 3, 1, 0, 0, "PSLLWri", 0, 0xe3804156ULL, NULL, NULL, OperandInfo203 }, // Inst #2022 = PSLLWri | |
| { 2023, 7, 1, 0, 0, "PSLLWrm", 0|(1<<MCID::MayLoad), 0x1e3800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2023 = PSLLWrm | |
| { 2024, 3, 1, 0, 0, "PSLLWrr", 0, 0x1e3800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2024 = PSLLWrr | |
| { 2025, 3, 1, 0, 0, "PSRADri", 0, 0xe5804154ULL, NULL, NULL, OperandInfo203 }, // Inst #2025 = PSRADri | |
| { 2026, 7, 1, 0, 0, "PSRADrm", 0|(1<<MCID::MayLoad), 0x1c5800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2026 = PSRADrm | |
| { 2027, 3, 1, 0, 0, "PSRADrr", 0, 0x1c5800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2027 = PSRADrr | |
| { 2028, 3, 1, 0, 0, "PSRAWri", 0, 0xe3804154ULL, NULL, NULL, OperandInfo203 }, // Inst #2028 = PSRAWri | |
| { 2029, 7, 1, 0, 0, "PSRAWrm", 0|(1<<MCID::MayLoad), 0x1c3800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2029 = PSRAWrm | |
| { 2030, 3, 1, 0, 0, "PSRAWrr", 0, 0x1c3800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2030 = PSRAWrr | |
| { 2031, 3, 1, 0, 0, "PSRLDQri", 0, 0xe7804153ULL, NULL, NULL, OperandInfo203 }, // Inst #2031 = PSRLDQri | |
| { 2032, 3, 1, 0, 0, "PSRLDri", 0, 0xe5804152ULL, NULL, NULL, OperandInfo203 }, // Inst #2032 = PSRLDri | |
| { 2033, 7, 1, 0, 0, "PSRLDrm", 0|(1<<MCID::MayLoad), 0x1a5800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2033 = PSRLDrm | |
| { 2034, 3, 1, 0, 0, "PSRLDrr", 0, 0x1a5800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2034 = PSRLDrr | |
| { 2035, 3, 1, 0, 0, "PSRLQri", 0, 0xe7804152ULL, NULL, NULL, OperandInfo203 }, // Inst #2035 = PSRLQri | |
| { 2036, 7, 1, 0, 0, "PSRLQrm", 0|(1<<MCID::MayLoad), 0x1a7800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2036 = PSRLQrm | |
| { 2037, 3, 1, 0, 0, "PSRLQrr", 0, 0x1a7800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2037 = PSRLQrr | |
| { 2038, 3, 1, 0, 0, "PSRLWri", 0, 0xe3804152ULL, NULL, NULL, OperandInfo203 }, // Inst #2038 = PSRLWri | |
| { 2039, 7, 1, 0, 0, "PSRLWrm", 0|(1<<MCID::MayLoad), 0x1a3800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2039 = PSRLWrm | |
| { 2040, 3, 1, 0, 0, "PSRLWrr", 0, 0x1a3800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2040 = PSRLWrr | |
| { 2041, 7, 1, 0, 0, "PSUBBrm", 0|(1<<MCID::MayLoad), 0x1f1800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2041 = PSUBBrm | |
| { 2042, 3, 1, 0, 0, "PSUBBrr", 0, 0x1f1800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2042 = PSUBBrr | |
| { 2043, 7, 1, 0, 0, "PSUBDrm", 0|(1<<MCID::MayLoad), 0x1f5800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2043 = PSUBDrm | |
| { 2044, 3, 1, 0, 0, "PSUBDrr", 0, 0x1f5800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2044 = PSUBDrr | |
| { 2045, 7, 1, 0, 0, "PSUBQrm", 0|(1<<MCID::MayLoad), 0x1f7800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2045 = PSUBQrm | |
| { 2046, 3, 1, 0, 0, "PSUBQrr", 0, 0x1f7800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2046 = PSUBQrr | |
| { 2047, 7, 1, 0, 0, "PSUBSBrm", 0|(1<<MCID::MayLoad), 0x1d1800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2047 = PSUBSBrm | |
| { 2048, 3, 1, 0, 0, "PSUBSBrr", 0, 0x1d1800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2048 = PSUBSBrr | |
| { 2049, 7, 1, 0, 0, "PSUBSWrm", 0|(1<<MCID::MayLoad), 0x1d3800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2049 = PSUBSWrm | |
| { 2050, 3, 1, 0, 0, "PSUBSWrr", 0, 0x1d3800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2050 = PSUBSWrr | |
| { 2051, 7, 1, 0, 0, "PSUBUSBrm", 0|(1<<MCID::MayLoad), 0x1b1800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2051 = PSUBUSBrm | |
| { 2052, 3, 1, 0, 0, "PSUBUSBrr", 0, 0x1b1800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2052 = PSUBUSBrr | |
| { 2053, 7, 1, 0, 0, "PSUBUSWrm", 0|(1<<MCID::MayLoad), 0x1b3800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2053 = PSUBUSWrm | |
| { 2054, 3, 1, 0, 0, "PSUBUSWrr", 0, 0x1b3800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2054 = PSUBUSWrr | |
| { 2055, 7, 1, 0, 0, "PSUBWrm", 0|(1<<MCID::MayLoad), 0x1f3800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2055 = PSUBWrm | |
| { 2056, 3, 1, 0, 0, "PSUBWrr", 0, 0x1f3800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2056 = PSUBWrr | |
| { 2057, 6, 1, 0, 0, "PSWAPDrm", 0|(1<<MCID::MayLoad), 0x8176000106ULL, NULL, NULL, OperandInfo145 }, // Inst #2057 = PSWAPDrm | |
| { 2058, 2, 1, 0, 0, "PSWAPDrr", 0, 0x8176000105ULL, NULL, NULL, OperandInfo149 }, // Inst #2058 = PSWAPDrr | |
| { 2059, 6, 0, 0, 0, "PTESTrm", 0|(1<<MCID::MayLoad), 0x2f800d46ULL, NULL, ImplicitList1, OperandInfo47 }, // Inst #2059 = PTESTrm | |
| { 2060, 2, 0, 0, 0, "PTESTrr", 0, 0x2f800d45ULL, NULL, ImplicitList1, OperandInfo48 }, // Inst #2060 = PTESTrr | |
| { 2061, 7, 1, 0, 0, "PUNPCKHBWrm", 0|(1<<MCID::MayLoad), 0xd1800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2061 = PUNPCKHBWrm | |
| { 2062, 3, 1, 0, 0, "PUNPCKHBWrr", 0, 0xd1800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2062 = PUNPCKHBWrr | |
| { 2063, 7, 1, 0, 0, "PUNPCKHDQrm", 0|(1<<MCID::MayLoad), 0xd5800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2063 = PUNPCKHDQrm | |
| { 2064, 3, 1, 0, 0, "PUNPCKHDQrr", 0, 0xd5800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2064 = PUNPCKHDQrr | |
| { 2065, 7, 1, 0, 0, "PUNPCKHQDQrm", 0|(1<<MCID::MayLoad), 0xdb800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2065 = PUNPCKHQDQrm | |
| { 2066, 3, 1, 0, 0, "PUNPCKHQDQrr", 0, 0xdb800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2066 = PUNPCKHQDQrr | |
| { 2067, 7, 1, 0, 0, "PUNPCKHWDrm", 0|(1<<MCID::MayLoad), 0xd3800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2067 = PUNPCKHWDrm | |
| { 2068, 3, 1, 0, 0, "PUNPCKHWDrr", 0, 0xd3800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2068 = PUNPCKHWDrr | |
| { 2069, 7, 1, 0, 0, "PUNPCKLBWrm", 0|(1<<MCID::MayLoad), 0xc1800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2069 = PUNPCKLBWrm | |
| { 2070, 3, 1, 0, 0, "PUNPCKLBWrr", 0, 0xc1800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2070 = PUNPCKLBWrr | |
| { 2071, 7, 1, 0, 0, "PUNPCKLDQrm", 0|(1<<MCID::MayLoad), 0xc5800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2071 = PUNPCKLDQrm | |
| { 2072, 3, 1, 0, 0, "PUNPCKLDQrr", 0, 0xc5800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2072 = PUNPCKLDQrr | |
| { 2073, 7, 1, 0, 0, "PUNPCKLQDQrm", 0|(1<<MCID::MayLoad), 0xd9800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2073 = PUNPCKLQDQrm | |
| { 2074, 3, 1, 0, 0, "PUNPCKLQDQrr", 0, 0xd9800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2074 = PUNPCKLQDQrr | |
| { 2075, 7, 1, 0, 0, "PUNPCKLWDrm", 0|(1<<MCID::MayLoad), 0xc3800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2075 = PUNPCKLWDrm | |
| { 2076, 3, 1, 0, 0, "PUNPCKLWDrr", 0, 0xc3800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2076 = PUNPCKLWDrr | |
| { 2077, 1, 0, 0, 0, "PUSH16r", 0|(1<<MCID::MayStore), 0xa0000042ULL, ImplicitList6, ImplicitList6, OperandInfo113 }, // Inst #2077 = PUSH16r | |
| { 2078, 5, 0, 0, 0, "PUSH16rmm", 0|(1<<MCID::MayStore), 0x1fe00005eULL, ImplicitList6, ImplicitList6, OperandInfo38 }, // Inst #2078 = PUSH16rmm | |
| { 2079, 1, 0, 0, 0, "PUSH16rmr", 0|(1<<MCID::MayStore), 0x1fe000056ULL, ImplicitList6, ImplicitList6, OperandInfo113 }, // Inst #2079 = PUSH16rmr | |
| { 2080, 1, 0, 0, 0, "PUSH32r", 0|(1<<MCID::MayStore), 0xa0000002ULL, ImplicitList6, ImplicitList6, OperandInfo72 }, // Inst #2080 = PUSH32r | |
| { 2081, 5, 0, 0, 0, "PUSH32rmm", 0|(1<<MCID::MayStore), 0x1fe00001eULL, ImplicitList6, ImplicitList6, OperandInfo38 }, // Inst #2081 = PUSH32rmm | |
| { 2082, 1, 0, 0, 0, "PUSH32rmr", 0|(1<<MCID::MayStore), 0x1fe000016ULL, ImplicitList6, ImplicitList6, OperandInfo72 }, // Inst #2082 = PUSH32rmr | |
| { 2083, 1, 0, 0, 0, "PUSH64i16", 0|(1<<MCID::MayStore), 0xd000c001ULL, ImplicitList8, ImplicitList8, OperandInfo2 }, // Inst #2083 = PUSH64i16 | |
| { 2084, 1, 0, 0, 0, "PUSH64i32", 0|(1<<MCID::MayStore), 0xd0014001ULL, ImplicitList8, ImplicitList8, OperandInfo2 }, // Inst #2084 = PUSH64i32 | |
| { 2085, 1, 0, 0, 0, "PUSH64i8", 0|(1<<MCID::MayStore), 0xd4004001ULL, ImplicitList8, ImplicitList8, OperandInfo2 }, // Inst #2085 = PUSH64i8 | |
| { 2086, 1, 0, 0, 0, "PUSH64r", 0|(1<<MCID::MayStore), 0xa0000002ULL, ImplicitList8, ImplicitList8, OperandInfo74 }, // Inst #2086 = PUSH64r | |
| { 2087, 5, 0, 0, 0, "PUSH64rmm", 0|(1<<MCID::MayStore), 0x1fe00001eULL, ImplicitList8, ImplicitList8, OperandInfo38 }, // Inst #2087 = PUSH64rmm | |
| { 2088, 1, 0, 0, 0, "PUSH64rmr", 0|(1<<MCID::MayStore), 0x1fe000016ULL, ImplicitList8, ImplicitList8, OperandInfo74 }, // Inst #2088 = PUSH64rmr | |
| { 2089, 0, 0, 0, 0, "PUSHA32", 0|(1<<MCID::MayStore), 0xc0000001ULL, ImplicitList47, ImplicitList6, 0 }, // Inst #2089 = PUSHA32 | |
| { 2090, 0, 0, 0, 0, "PUSHCS16", 0|(1<<MCID::UnmodeledSideEffects), 0x1c000041ULL, NULL, NULL, 0 }, // Inst #2090 = PUSHCS16 | |
| { 2091, 0, 0, 0, 0, "PUSHCS32", 0|(1<<MCID::UnmodeledSideEffects), 0x1c000001ULL, NULL, NULL, 0 }, // Inst #2091 = PUSHCS32 | |
| { 2092, 0, 0, 0, 0, "PUSHDS16", 0|(1<<MCID::UnmodeledSideEffects), 0x3c000041ULL, NULL, NULL, 0 }, // Inst #2092 = PUSHDS16 | |
| { 2093, 0, 0, 0, 0, "PUSHDS32", 0|(1<<MCID::UnmodeledSideEffects), 0x3c000001ULL, NULL, NULL, 0 }, // Inst #2093 = PUSHDS32 | |
| { 2094, 0, 0, 0, 0, "PUSHES16", 0|(1<<MCID::UnmodeledSideEffects), 0xc000041ULL, NULL, NULL, 0 }, // Inst #2094 = PUSHES16 | |
| { 2095, 0, 0, 0, 0, "PUSHES32", 0|(1<<MCID::UnmodeledSideEffects), 0xc000001ULL, NULL, NULL, 0 }, // Inst #2095 = PUSHES32 | |
| { 2096, 0, 0, 0, 0, "PUSHF16", 0|(1<<MCID::MayStore), 0x138000041ULL, ImplicitList6, ImplicitList6, 0 }, // Inst #2096 = PUSHF16 | |
| { 2097, 0, 0, 0, 0, "PUSHF32", 0|(1<<MCID::MayStore), 0x138000001ULL, ImplicitList6, ImplicitList6, 0 }, // Inst #2097 = PUSHF32 | |
| { 2098, 0, 0, 0, 0, "PUSHF64", 0|(1<<MCID::MayStore), 0x138000001ULL, ImplicitList9, ImplicitList8, 0 }, // Inst #2098 = PUSHF64 | |
| { 2099, 0, 0, 0, 0, "PUSHFS16", 0|(1<<MCID::UnmodeledSideEffects), 0x140000141ULL, NULL, NULL, 0 }, // Inst #2099 = PUSHFS16 | |
| { 2100, 0, 0, 0, 0, "PUSHFS32", 0|(1<<MCID::UnmodeledSideEffects), 0x140000101ULL, NULL, NULL, 0 }, // Inst #2100 = PUSHFS32 | |
| { 2101, 0, 0, 0, 0, "PUSHFS64", 0|(1<<MCID::UnmodeledSideEffects), 0x140000101ULL, NULL, NULL, 0 }, // Inst #2101 = PUSHFS64 | |
| { 2102, 0, 0, 0, 0, "PUSHGS16", 0|(1<<MCID::UnmodeledSideEffects), 0x150000141ULL, NULL, NULL, 0 }, // Inst #2102 = PUSHGS16 | |
| { 2103, 0, 0, 0, 0, "PUSHGS32", 0|(1<<MCID::UnmodeledSideEffects), 0x150000101ULL, NULL, NULL, 0 }, // Inst #2103 = PUSHGS32 | |
| { 2104, 0, 0, 0, 0, "PUSHGS64", 0|(1<<MCID::UnmodeledSideEffects), 0x150000101ULL, NULL, NULL, 0 }, // Inst #2104 = PUSHGS64 | |
| { 2105, 0, 0, 0, 0, "PUSHSS16", 0|(1<<MCID::UnmodeledSideEffects), 0x2c000041ULL, NULL, NULL, 0 }, // Inst #2105 = PUSHSS16 | |
| { 2106, 0, 0, 0, 0, "PUSHSS32", 0|(1<<MCID::UnmodeledSideEffects), 0x2c000001ULL, NULL, NULL, 0 }, // Inst #2106 = PUSHSS32 | |
| { 2107, 1, 0, 0, 0, "PUSHi16", 0|(1<<MCID::MayStore), 0xd000c041ULL, ImplicitList6, ImplicitList6, OperandInfo2 }, // Inst #2107 = PUSHi16 | |
| { 2108, 1, 0, 0, 0, "PUSHi32", 0|(1<<MCID::MayStore), 0xd0014001ULL, ImplicitList6, ImplicitList6, OperandInfo2 }, // Inst #2108 = PUSHi32 | |
| { 2109, 1, 0, 0, 0, "PUSHi8", 0|(1<<MCID::MayStore), 0xd4004001ULL, ImplicitList6, ImplicitList6, OperandInfo2 }, // Inst #2109 = PUSHi8 | |
| { 2110, 7, 1, 0, 0, "PXORrm", 0|(1<<MCID::MayLoad), 0x1df800146ULL, NULL, NULL, OperandInfo32 }, // Inst #2110 = PXORrm | |
| { 2111, 3, 1, 0, 0, "PXORrr", 0|(1<<MCID::Commutable), 0x1df800145ULL, NULL, NULL, OperandInfo33 }, // Inst #2111 = PXORrr | |
| { 2112, 5, 0, 0, 0, "RCL16m1", 0|(1<<MCID::UnmodeledSideEffects), 0x1a200005aULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2112 = RCL16m1 | |
| { 2113, 5, 0, 0, 0, "RCL16mCL", 0|(1<<MCID::UnmodeledSideEffects), 0x1a600005aULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2113 = RCL16mCL | |
| { 2114, 6, 0, 0, 0, "RCL16mi", 0|(1<<MCID::UnmodeledSideEffects), 0x18200405aULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2114 = RCL16mi | |
| { 2115, 2, 1, 0, 0, "RCL16r1", 0|(1<<MCID::UnmodeledSideEffects), 0x1a2000052ULL, NULL, ImplicitList1, OperandInfo111 }, // Inst #2115 = RCL16r1 | |
| { 2116, 2, 1, 0, 0, "RCL16rCL", 0|(1<<MCID::UnmodeledSideEffects), 0x1a6000052ULL, ImplicitList48, ImplicitList1, OperandInfo111 }, // Inst #2116 = RCL16rCL | |
| { 2117, 3, 1, 0, 0, "RCL16ri", 0|(1<<MCID::UnmodeledSideEffects), 0x182004052ULL, NULL, ImplicitList1, OperandInfo17 }, // Inst #2117 = RCL16ri | |
| { 2118, 5, 0, 0, 0, "RCL32m1", 0|(1<<MCID::UnmodeledSideEffects), 0x1a200001aULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2118 = RCL32m1 | |
| { 2119, 5, 0, 0, 0, "RCL32mCL", 0|(1<<MCID::UnmodeledSideEffects), 0x1a600001aULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2119 = RCL32mCL | |
| { 2120, 6, 0, 0, 0, "RCL32mi", 0|(1<<MCID::UnmodeledSideEffects), 0x18200401aULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2120 = RCL32mi | |
| { 2121, 2, 1, 0, 0, "RCL32r1", 0|(1<<MCID::UnmodeledSideEffects), 0x1a2000012ULL, NULL, ImplicitList1, OperandInfo67 }, // Inst #2121 = RCL32r1 | |
| { 2122, 2, 1, 0, 0, "RCL32rCL", 0|(1<<MCID::UnmodeledSideEffects), 0x1a6000012ULL, ImplicitList48, ImplicitList1, OperandInfo67 }, // Inst #2122 = RCL32rCL | |
| { 2123, 3, 1, 0, 0, "RCL32ri", 0|(1<<MCID::UnmodeledSideEffects), 0x182004012ULL, NULL, ImplicitList1, OperandInfo21 }, // Inst #2123 = RCL32ri | |
| { 2124, 5, 0, 0, 0, "RCL64m1", 0|(1<<MCID::UnmodeledSideEffects), 0x1a200201aULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2124 = RCL64m1 | |
| { 2125, 5, 0, 0, 0, "RCL64mCL", 0|(1<<MCID::UnmodeledSideEffects), 0x1a600201aULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2125 = RCL64mCL | |
| { 2126, 6, 0, 0, 0, "RCL64mi", 0|(1<<MCID::UnmodeledSideEffects), 0x18200601aULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2126 = RCL64mi | |
| { 2127, 2, 1, 0, 0, "RCL64r1", 0|(1<<MCID::UnmodeledSideEffects), 0x1a2002012ULL, NULL, ImplicitList1, OperandInfo68 }, // Inst #2127 = RCL64r1 | |
| { 2128, 2, 1, 0, 0, "RCL64rCL", 0|(1<<MCID::UnmodeledSideEffects), 0x1a6002012ULL, ImplicitList48, ImplicitList1, OperandInfo68 }, // Inst #2128 = RCL64rCL | |
| { 2129, 3, 1, 0, 0, "RCL64ri", 0|(1<<MCID::UnmodeledSideEffects), 0x182006012ULL, NULL, ImplicitList1, OperandInfo25 }, // Inst #2129 = RCL64ri | |
| { 2130, 5, 0, 0, 0, "RCL8m1", 0|(1<<MCID::UnmodeledSideEffects), 0x1a000001aULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2130 = RCL8m1 | |
| { 2131, 5, 0, 0, 0, "RCL8mCL", 0|(1<<MCID::UnmodeledSideEffects), 0x1a400001aULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2131 = RCL8mCL | |
| { 2132, 6, 0, 0, 0, "RCL8mi", 0|(1<<MCID::UnmodeledSideEffects), 0x18000401aULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2132 = RCL8mi | |
| { 2133, 2, 1, 0, 0, "RCL8r1", 0|(1<<MCID::UnmodeledSideEffects), 0x1a0000012ULL, NULL, ImplicitList1, OperandInfo112 }, // Inst #2133 = RCL8r1 | |
| { 2134, 2, 1, 0, 0, "RCL8rCL", 0|(1<<MCID::UnmodeledSideEffects), 0x1a4000012ULL, ImplicitList48, ImplicitList1, OperandInfo112 }, // Inst #2134 = RCL8rCL | |
| { 2135, 3, 1, 0, 0, "RCL8ri", 0|(1<<MCID::UnmodeledSideEffects), 0x180004012ULL, NULL, ImplicitList1, OperandInfo29 }, // Inst #2135 = RCL8ri | |
| { 2136, 6, 1, 0, 0, "RCPPSm", 0|(1<<MCID::MayLoad), 0xa6800106ULL, NULL, NULL, OperandInfo47 }, // Inst #2136 = RCPPSm | |
| { 2137, 6, 1, 0, 0, "RCPPSm_Int", 0|(1<<MCID::MayLoad), 0xa6800106ULL, NULL, NULL, OperandInfo47 }, // Inst #2137 = RCPPSm_Int | |
| { 2138, 2, 1, 0, 0, "RCPPSr", 0, 0xa6800105ULL, NULL, NULL, OperandInfo48 }, // Inst #2138 = RCPPSr | |
| { 2139, 2, 1, 0, 0, "RCPPSr_Int", 0, 0xa6800105ULL, NULL, NULL, OperandInfo48 }, // Inst #2139 = RCPPSr_Int | |
| { 2140, 6, 1, 0, 0, "RCPSSm", 0|(1<<MCID::MayLoad), 0xa6000c06ULL, NULL, NULL, OperandInfo99 }, // Inst #2140 = RCPSSm | |
| { 2141, 6, 1, 0, 0, "RCPSSm_Int", 0|(1<<MCID::MayLoad), 0xa6000c06ULL, NULL, NULL, OperandInfo47 }, // Inst #2141 = RCPSSm_Int | |
| { 2142, 2, 1, 0, 0, "RCPSSr", 0, 0xa6000c05ULL, NULL, NULL, OperandInfo124 }, // Inst #2142 = RCPSSr | |
| { 2143, 2, 1, 0, 0, "RCPSSr_Int", 0, 0xa6000c05ULL, NULL, NULL, OperandInfo48 }, // Inst #2143 = RCPSSr_Int | |
| { 2144, 5, 0, 0, 0, "RCR16m1", 0|(1<<MCID::UnmodeledSideEffects), 0x1a200005bULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2144 = RCR16m1 | |
| { 2145, 5, 0, 0, 0, "RCR16mCL", 0|(1<<MCID::UnmodeledSideEffects), 0x1a600005bULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2145 = RCR16mCL | |
| { 2146, 6, 0, 0, 0, "RCR16mi", 0|(1<<MCID::UnmodeledSideEffects), 0x18200405bULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2146 = RCR16mi | |
| { 2147, 2, 1, 0, 0, "RCR16r1", 0|(1<<MCID::UnmodeledSideEffects), 0x1a2000053ULL, NULL, ImplicitList1, OperandInfo111 }, // Inst #2147 = RCR16r1 | |
| { 2148, 2, 1, 0, 0, "RCR16rCL", 0|(1<<MCID::UnmodeledSideEffects), 0x1a6000053ULL, ImplicitList48, ImplicitList1, OperandInfo111 }, // Inst #2148 = RCR16rCL | |
| { 2149, 3, 1, 0, 0, "RCR16ri", 0|(1<<MCID::UnmodeledSideEffects), 0x182004053ULL, NULL, ImplicitList1, OperandInfo17 }, // Inst #2149 = RCR16ri | |
| { 2150, 5, 0, 0, 0, "RCR32m1", 0|(1<<MCID::UnmodeledSideEffects), 0x1a200001bULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2150 = RCR32m1 | |
| { 2151, 5, 0, 0, 0, "RCR32mCL", 0|(1<<MCID::UnmodeledSideEffects), 0x1a600001bULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2151 = RCR32mCL | |
| { 2152, 6, 0, 0, 0, "RCR32mi", 0|(1<<MCID::UnmodeledSideEffects), 0x18200401bULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2152 = RCR32mi | |
| { 2153, 2, 1, 0, 0, "RCR32r1", 0|(1<<MCID::UnmodeledSideEffects), 0x1a2000013ULL, NULL, ImplicitList1, OperandInfo67 }, // Inst #2153 = RCR32r1 | |
| { 2154, 2, 1, 0, 0, "RCR32rCL", 0|(1<<MCID::UnmodeledSideEffects), 0x1a6000013ULL, ImplicitList48, ImplicitList1, OperandInfo67 }, // Inst #2154 = RCR32rCL | |
| { 2155, 3, 1, 0, 0, "RCR32ri", 0|(1<<MCID::UnmodeledSideEffects), 0x182004013ULL, NULL, ImplicitList1, OperandInfo21 }, // Inst #2155 = RCR32ri | |
| { 2156, 5, 0, 0, 0, "RCR64m1", 0|(1<<MCID::UnmodeledSideEffects), 0x1a200201bULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2156 = RCR64m1 | |
| { 2157, 5, 0, 0, 0, "RCR64mCL", 0|(1<<MCID::UnmodeledSideEffects), 0x1a600201bULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2157 = RCR64mCL | |
| { 2158, 6, 0, 0, 0, "RCR64mi", 0|(1<<MCID::UnmodeledSideEffects), 0x18200601bULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2158 = RCR64mi | |
| { 2159, 2, 1, 0, 0, "RCR64r1", 0|(1<<MCID::UnmodeledSideEffects), 0x1a2002013ULL, NULL, ImplicitList1, OperandInfo68 }, // Inst #2159 = RCR64r1 | |
| { 2160, 2, 1, 0, 0, "RCR64rCL", 0|(1<<MCID::UnmodeledSideEffects), 0x1a6002013ULL, ImplicitList48, ImplicitList1, OperandInfo68 }, // Inst #2160 = RCR64rCL | |
| { 2161, 3, 1, 0, 0, "RCR64ri", 0|(1<<MCID::UnmodeledSideEffects), 0x182006013ULL, NULL, ImplicitList1, OperandInfo25 }, // Inst #2161 = RCR64ri | |
| { 2162, 5, 0, 0, 0, "RCR8m1", 0|(1<<MCID::UnmodeledSideEffects), 0x1a000001bULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2162 = RCR8m1 | |
| { 2163, 5, 0, 0, 0, "RCR8mCL", 0|(1<<MCID::UnmodeledSideEffects), 0x1a400001bULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2163 = RCR8mCL | |
| { 2164, 6, 0, 0, 0, "RCR8mi", 0|(1<<MCID::UnmodeledSideEffects), 0x18000401bULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2164 = RCR8mi | |
| { 2165, 2, 1, 0, 0, "RCR8r1", 0|(1<<MCID::UnmodeledSideEffects), 0x1a0000013ULL, NULL, ImplicitList1, OperandInfo112 }, // Inst #2165 = RCR8r1 | |
| { 2166, 2, 1, 0, 0, "RCR8rCL", 0|(1<<MCID::UnmodeledSideEffects), 0x1a4000013ULL, ImplicitList48, ImplicitList1, OperandInfo112 }, // Inst #2166 = RCR8rCL | |
| { 2167, 3, 1, 0, 0, "RCR8ri", 0|(1<<MCID::UnmodeledSideEffects), 0x180004013ULL, NULL, ImplicitList1, OperandInfo29 }, // Inst #2167 = RCR8ri | |
| { 2168, 1, 1, 0, 0, "RDFSBASE", 0|(1<<MCID::UnmodeledSideEffects), 0x15c000c10ULL, NULL, NULL, OperandInfo72 }, // Inst #2168 = RDFSBASE | |
| { 2169, 1, 1, 0, 0, "RDFSBASE64", 0|(1<<MCID::UnmodeledSideEffects), 0x15c002c10ULL, NULL, NULL, OperandInfo74 }, // Inst #2169 = RDFSBASE64 | |
| { 2170, 1, 1, 0, 0, "RDGSBASE", 0|(1<<MCID::UnmodeledSideEffects), 0x15c000c11ULL, NULL, NULL, OperandInfo72 }, // Inst #2170 = RDGSBASE | |
| { 2171, 1, 1, 0, 0, "RDGSBASE64", 0|(1<<MCID::UnmodeledSideEffects), 0x15c002c11ULL, NULL, NULL, OperandInfo74 }, // Inst #2171 = RDGSBASE64 | |
| { 2172, 0, 0, 0, 0, "RDMSR", 0|(1<<MCID::UnmodeledSideEffects), 0x64000101ULL, NULL, NULL, 0 }, // Inst #2172 = RDMSR | |
| { 2173, 0, 0, 0, 0, "RDPMC", 0|(1<<MCID::UnmodeledSideEffects), 0x66000101ULL, NULL, NULL, 0 }, // Inst #2173 = RDPMC | |
| { 2174, 1, 1, 0, 0, "RDRAND16r", 0|(1<<MCID::UnmodeledSideEffects), 0x18e000156ULL, NULL, ImplicitList1, OperandInfo113 }, // Inst #2174 = RDRAND16r | |
| { 2175, 1, 1, 0, 0, "RDRAND32r", 0|(1<<MCID::UnmodeledSideEffects), 0x18e000116ULL, NULL, ImplicitList1, OperandInfo72 }, // Inst #2175 = RDRAND32r | |
| { 2176, 1, 1, 0, 0, "RDRAND64r", 0|(1<<MCID::UnmodeledSideEffects), 0x18e002116ULL, NULL, ImplicitList1, OperandInfo74 }, // Inst #2176 = RDRAND64r | |
| { 2177, 0, 0, 0, 0, "RDTSC", 0|(1<<MCID::UnmodeledSideEffects), 0x62000101ULL, NULL, ImplicitList19, 0 }, // Inst #2177 = RDTSC | |
| { 2178, 0, 0, 0, 0, "RDTSCP", 0|(1<<MCID::UnmodeledSideEffects), 0x200012aULL, NULL, ImplicitList49, 0 }, // Inst #2178 = RDTSCP | |
| { 2179, 6, 0, 0, 0, "RELEASE_MOV16mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x0ULL, NULL, NULL, OperandInfo16 }, // Inst #2179 = RELEASE_MOV16mr | |
| { 2180, 6, 0, 0, 0, "RELEASE_MOV32mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x0ULL, NULL, NULL, OperandInfo20 }, // Inst #2180 = RELEASE_MOV32mr | |
| { 2181, 6, 0, 0, 0, "RELEASE_MOV64mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x0ULL, NULL, NULL, OperandInfo24 }, // Inst #2181 = RELEASE_MOV64mr | |
| { 2182, 6, 0, 0, 0, "RELEASE_MOV8mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x0ULL, NULL, NULL, OperandInfo28 }, // Inst #2182 = RELEASE_MOV8mr | |
| { 2183, 0, 0, 0, 0, "REPNE_PREFIX", 0|(1<<MCID::UnmodeledSideEffects), 0x1e4000001ULL, ImplicitList45, ImplicitList25, 0 }, // Inst #2183 = REPNE_PREFIX | |
| { 2184, 0, 0, 0, 0, "REP_MOVSB", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x148000201ULL, ImplicitList50, ImplicitList50, 0 }, // Inst #2184 = REP_MOVSB | |
| { 2185, 0, 0, 0, 0, "REP_MOVSD", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x14a000201ULL, ImplicitList50, ImplicitList50, 0 }, // Inst #2185 = REP_MOVSD | |
| { 2186, 0, 0, 0, 0, "REP_MOVSQ", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x14a002201ULL, ImplicitList51, ImplicitList51, 0 }, // Inst #2186 = REP_MOVSQ | |
| { 2187, 0, 0, 0, 0, "REP_MOVSW", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x14a000241ULL, ImplicitList50, ImplicitList50, 0 }, // Inst #2187 = REP_MOVSW | |
| { 2188, 0, 0, 0, 0, "REP_PREFIX", 0|(1<<MCID::UnmodeledSideEffects), 0x1e6000001ULL, ImplicitList45, ImplicitList25, 0 }, // Inst #2188 = REP_PREFIX | |
| { 2189, 0, 0, 0, 0, "REP_STOSB", 0|(1<<MCID::MayStore), 0x154000201ULL, ImplicitList52, ImplicitList53, 0 }, // Inst #2189 = REP_STOSB | |
| { 2190, 0, 0, 0, 0, "REP_STOSD", 0|(1<<MCID::MayStore), 0x156000201ULL, ImplicitList54, ImplicitList53, 0 }, // Inst #2190 = REP_STOSD | |
| { 2191, 0, 0, 0, 0, "REP_STOSQ", 0|(1<<MCID::MayStore), 0x156002201ULL, ImplicitList55, ImplicitList56, 0 }, // Inst #2191 = REP_STOSQ | |
| { 2192, 0, 0, 0, 0, "REP_STOSW", 0|(1<<MCID::MayStore), 0x156000241ULL, ImplicitList57, ImplicitList53, 0 }, // Inst #2192 = REP_STOSW | |
| { 2193, 0, 0, 0, 0, "RET", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Terminator)|(1<<MCID::Variadic), 0x1860e0001ULL, NULL, NULL, 0 }, // Inst #2193 = RET | |
| { 2194, 1, 0, 0, 0, "RETI", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Terminator)|(1<<MCID::Variadic), 0x1840ec001ULL, NULL, NULL, OperandInfo2 }, // Inst #2194 = RETI | |
| { 2195, 1, 0, 0, 0, "RETIW", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Terminator)|(1<<MCID::Variadic)|(1<<MCID::UnmodeledSideEffects), 0x1840ec041ULL, NULL, NULL, OperandInfo2 }, // Inst #2195 = RETIW | |
| { 2196, 0, 0, 0, 0, "REX64_PREFIX", 0|(1<<MCID::UnmodeledSideEffects), 0x90000001ULL, NULL, NULL, 0 }, // Inst #2196 = REX64_PREFIX | |
| { 2197, 5, 0, 0, 0, "ROL16m1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a2000058ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2197 = ROL16m1 | |
| { 2198, 5, 0, 0, 0, "ROL16mCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a6000058ULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2198 = ROL16mCL | |
| { 2199, 6, 0, 0, 0, "ROL16mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x182004058ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2199 = ROL16mi | |
| { 2200, 2, 1, 0, 0, "ROL16r1", 0, 0x1a2000050ULL, NULL, ImplicitList1, OperandInfo111 }, // Inst #2200 = ROL16r1 | |
| { 2201, 2, 1, 0, 0, "ROL16rCL", 0, 0x1a6000050ULL, ImplicitList48, ImplicitList1, OperandInfo111 }, // Inst #2201 = ROL16rCL | |
| { 2202, 3, 1, 0, 0, "ROL16ri", 0, 0x182004050ULL, NULL, ImplicitList1, OperandInfo17 }, // Inst #2202 = ROL16ri | |
| { 2203, 5, 0, 0, 0, "ROL32m1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a2000018ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2203 = ROL32m1 | |
| { 2204, 5, 0, 0, 0, "ROL32mCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a6000018ULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2204 = ROL32mCL | |
| { 2205, 6, 0, 0, 0, "ROL32mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x182004018ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2205 = ROL32mi | |
| { 2206, 2, 1, 0, 0, "ROL32r1", 0, 0x1a2000010ULL, NULL, ImplicitList1, OperandInfo67 }, // Inst #2206 = ROL32r1 | |
| { 2207, 2, 1, 0, 0, "ROL32rCL", 0, 0x1a6000010ULL, ImplicitList48, ImplicitList1, OperandInfo67 }, // Inst #2207 = ROL32rCL | |
| { 2208, 3, 1, 0, 0, "ROL32ri", 0, 0x182004010ULL, NULL, ImplicitList1, OperandInfo21 }, // Inst #2208 = ROL32ri | |
| { 2209, 5, 0, 0, 0, "ROL64m1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a2002018ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2209 = ROL64m1 | |
| { 2210, 5, 0, 0, 0, "ROL64mCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a6002018ULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2210 = ROL64mCL | |
| { 2211, 6, 0, 0, 0, "ROL64mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x182006018ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2211 = ROL64mi | |
| { 2212, 2, 1, 0, 0, "ROL64r1", 0, 0x1a2002010ULL, NULL, ImplicitList1, OperandInfo68 }, // Inst #2212 = ROL64r1 | |
| { 2213, 2, 1, 0, 0, "ROL64rCL", 0, 0x1a6002010ULL, ImplicitList48, ImplicitList1, OperandInfo68 }, // Inst #2213 = ROL64rCL | |
| { 2214, 3, 1, 0, 0, "ROL64ri", 0, 0x182006010ULL, NULL, ImplicitList1, OperandInfo25 }, // Inst #2214 = ROL64ri | |
| { 2215, 5, 0, 0, 0, "ROL8m1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a0000018ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2215 = ROL8m1 | |
| { 2216, 5, 0, 0, 0, "ROL8mCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a4000018ULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2216 = ROL8mCL | |
| { 2217, 6, 0, 0, 0, "ROL8mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x180004018ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2217 = ROL8mi | |
| { 2218, 2, 1, 0, 0, "ROL8r1", 0, 0x1a0000010ULL, NULL, ImplicitList1, OperandInfo112 }, // Inst #2218 = ROL8r1 | |
| { 2219, 2, 1, 0, 0, "ROL8rCL", 0, 0x1a4000010ULL, ImplicitList48, ImplicitList1, OperandInfo112 }, // Inst #2219 = ROL8rCL | |
| { 2220, 3, 1, 0, 0, "ROL8ri", 0, 0x180004010ULL, NULL, ImplicitList1, OperandInfo29 }, // Inst #2220 = ROL8ri | |
| { 2221, 5, 0, 0, 0, "ROR16m1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a2000059ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2221 = ROR16m1 | |
| { 2222, 5, 0, 0, 0, "ROR16mCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a6000059ULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2222 = ROR16mCL | |
| { 2223, 6, 0, 0, 0, "ROR16mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x182004059ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2223 = ROR16mi | |
| { 2224, 2, 1, 0, 0, "ROR16r1", 0, 0x1a2000051ULL, NULL, ImplicitList1, OperandInfo111 }, // Inst #2224 = ROR16r1 | |
| { 2225, 2, 1, 0, 0, "ROR16rCL", 0, 0x1a6000051ULL, ImplicitList48, ImplicitList1, OperandInfo111 }, // Inst #2225 = ROR16rCL | |
| { 2226, 3, 1, 0, 0, "ROR16ri", 0, 0x182004051ULL, NULL, ImplicitList1, OperandInfo17 }, // Inst #2226 = ROR16ri | |
| { 2227, 5, 0, 0, 0, "ROR32m1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a2000019ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2227 = ROR32m1 | |
| { 2228, 5, 0, 0, 0, "ROR32mCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a6000019ULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2228 = ROR32mCL | |
| { 2229, 6, 0, 0, 0, "ROR32mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x182004019ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2229 = ROR32mi | |
| { 2230, 2, 1, 0, 0, "ROR32r1", 0, 0x1a2000011ULL, NULL, ImplicitList1, OperandInfo67 }, // Inst #2230 = ROR32r1 | |
| { 2231, 2, 1, 0, 0, "ROR32rCL", 0, 0x1a6000011ULL, ImplicitList48, ImplicitList1, OperandInfo67 }, // Inst #2231 = ROR32rCL | |
| { 2232, 3, 1, 0, 0, "ROR32ri", 0, 0x182004011ULL, NULL, ImplicitList1, OperandInfo21 }, // Inst #2232 = ROR32ri | |
| { 2233, 5, 0, 0, 0, "ROR64m1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a2002019ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2233 = ROR64m1 | |
| { 2234, 5, 0, 0, 0, "ROR64mCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a6002019ULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2234 = ROR64mCL | |
| { 2235, 6, 0, 0, 0, "ROR64mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x182006019ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2235 = ROR64mi | |
| { 2236, 2, 1, 0, 0, "ROR64r1", 0, 0x1a2002011ULL, NULL, ImplicitList1, OperandInfo68 }, // Inst #2236 = ROR64r1 | |
| { 2237, 2, 1, 0, 0, "ROR64rCL", 0, 0x1a6002011ULL, ImplicitList48, ImplicitList1, OperandInfo68 }, // Inst #2237 = ROR64rCL | |
| { 2238, 3, 1, 0, 0, "ROR64ri", 0, 0x182006011ULL, NULL, ImplicitList1, OperandInfo25 }, // Inst #2238 = ROR64ri | |
| { 2239, 5, 0, 0, 0, "ROR8m1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a0000019ULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2239 = ROR8m1 | |
| { 2240, 5, 0, 0, 0, "ROR8mCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a4000019ULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2240 = ROR8mCL | |
| { 2241, 6, 0, 0, 0, "ROR8mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x180004019ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2241 = ROR8mi | |
| { 2242, 2, 1, 0, 0, "ROR8r1", 0, 0x1a0000011ULL, NULL, ImplicitList1, OperandInfo112 }, // Inst #2242 = ROR8r1 | |
| { 2243, 2, 1, 0, 0, "ROR8rCL", 0, 0x1a4000011ULL, ImplicitList48, ImplicitList1, OperandInfo112 }, // Inst #2243 = ROR8rCL | |
| { 2244, 3, 1, 0, 0, "ROR8ri", 0, 0x180004011ULL, NULL, ImplicitList1, OperandInfo29 }, // Inst #2244 = ROR8ri | |
| { 2245, 7, 1, 0, 0, "ROUNDPDm", 0|(1<<MCID::MayLoad), 0x13804e46ULL, NULL, NULL, OperandInfo49 }, // Inst #2245 = ROUNDPDm | |
| { 2246, 3, 1, 0, 0, "ROUNDPDr", 0, 0x13804e45ULL, NULL, NULL, OperandInfo50 }, // Inst #2246 = ROUNDPDr | |
| { 2247, 7, 1, 0, 0, "ROUNDPSm", 0|(1<<MCID::MayLoad), 0x10004e46ULL, NULL, NULL, OperandInfo49 }, // Inst #2247 = ROUNDPSm | |
| { 2248, 3, 1, 0, 0, "ROUNDPSr", 0, 0x11804e45ULL, NULL, NULL, OperandInfo50 }, // Inst #2248 = ROUNDPSr | |
| { 2249, 8, 1, 0, 0, "ROUNDSDm", 0|(1<<MCID::MayLoad), 0x17804e46ULL, NULL, NULL, OperandInfo63 }, // Inst #2249 = ROUNDSDm | |
| { 2250, 4, 1, 0, 0, "ROUNDSDr", 0, 0x17804e45ULL, NULL, NULL, OperandInfo64 }, // Inst #2250 = ROUNDSDr | |
| { 2251, 8, 1, 0, 0, "ROUNDSSm", 0|(1<<MCID::MayLoad), 0x15804e46ULL, NULL, NULL, OperandInfo63 }, // Inst #2251 = ROUNDSSm | |
| { 2252, 4, 1, 0, 0, "ROUNDSSr", 0, 0x15804e45ULL, NULL, NULL, OperandInfo64 }, // Inst #2252 = ROUNDSSr | |
| { 2253, 0, 0, 0, 0, "RSM", 0|(1<<MCID::UnmodeledSideEffects), 0x154000101ULL, NULL, NULL, 0 }, // Inst #2253 = RSM | |
| { 2254, 6, 1, 0, 0, "RSQRTPSm", 0|(1<<MCID::MayLoad), 0xa4800106ULL, NULL, NULL, OperandInfo47 }, // Inst #2254 = RSQRTPSm | |
| { 2255, 6, 1, 0, 0, "RSQRTPSm_Int", 0|(1<<MCID::MayLoad), 0xa4800106ULL, NULL, NULL, OperandInfo47 }, // Inst #2255 = RSQRTPSm_Int | |
| { 2256, 2, 1, 0, 0, "RSQRTPSr", 0, 0xa4800105ULL, NULL, NULL, OperandInfo48 }, // Inst #2256 = RSQRTPSr | |
| { 2257, 2, 1, 0, 0, "RSQRTPSr_Int", 0, 0xa4800105ULL, NULL, NULL, OperandInfo48 }, // Inst #2257 = RSQRTPSr_Int | |
| { 2258, 6, 1, 0, 0, "RSQRTSSm", 0|(1<<MCID::MayLoad), 0xa4000c06ULL, NULL, NULL, OperandInfo99 }, // Inst #2258 = RSQRTSSm | |
| { 2259, 6, 1, 0, 0, "RSQRTSSm_Int", 0|(1<<MCID::MayLoad), 0xa4000c06ULL, NULL, NULL, OperandInfo47 }, // Inst #2259 = RSQRTSSm_Int | |
| { 2260, 2, 1, 0, 0, "RSQRTSSr", 0, 0xa4000c05ULL, NULL, NULL, OperandInfo124 }, // Inst #2260 = RSQRTSSr | |
| { 2261, 2, 1, 0, 0, "RSQRTSSr_Int", 0, 0xa4000c05ULL, NULL, NULL, OperandInfo48 }, // Inst #2261 = RSQRTSSr_Int | |
| { 2262, 0, 0, 0, 0, "SAHF", 0, 0x13c000001ULL, ImplicitList27, ImplicitList1, 0 }, // Inst #2262 = SAHF | |
| { 2263, 5, 0, 0, 0, "SAR16m1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a200005fULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2263 = SAR16m1 | |
| { 2264, 5, 0, 0, 0, "SAR16mCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a600005fULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2264 = SAR16mCL | |
| { 2265, 6, 0, 0, 0, "SAR16mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x18200405fULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2265 = SAR16mi | |
| { 2266, 2, 1, 0, 0, "SAR16r1", 0, 0x1a2000057ULL, NULL, ImplicitList1, OperandInfo111 }, // Inst #2266 = SAR16r1 | |
| { 2267, 2, 1, 0, 0, "SAR16rCL", 0, 0x1a6000057ULL, ImplicitList48, ImplicitList1, OperandInfo111 }, // Inst #2267 = SAR16rCL | |
| { 2268, 3, 1, 0, 0, "SAR16ri", 0, 0x182004057ULL, NULL, ImplicitList1, OperandInfo17 }, // Inst #2268 = SAR16ri | |
| { 2269, 5, 0, 0, 0, "SAR32m1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a200001fULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2269 = SAR32m1 | |
| { 2270, 5, 0, 0, 0, "SAR32mCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a600001fULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2270 = SAR32mCL | |
| { 2271, 6, 0, 0, 0, "SAR32mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x18200401fULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2271 = SAR32mi | |
| { 2272, 2, 1, 0, 0, "SAR32r1", 0, 0x1a2000017ULL, NULL, ImplicitList1, OperandInfo67 }, // Inst #2272 = SAR32r1 | |
| { 2273, 2, 1, 0, 0, "SAR32rCL", 0, 0x1a6000017ULL, ImplicitList48, ImplicitList1, OperandInfo67 }, // Inst #2273 = SAR32rCL | |
| { 2274, 3, 1, 0, 0, "SAR32ri", 0, 0x182004017ULL, NULL, ImplicitList1, OperandInfo21 }, // Inst #2274 = SAR32ri | |
| { 2275, 5, 0, 0, 0, "SAR64m1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a200201fULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2275 = SAR64m1 | |
| { 2276, 5, 0, 0, 0, "SAR64mCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a600201fULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2276 = SAR64mCL | |
| { 2277, 6, 0, 0, 0, "SAR64mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x18200601fULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2277 = SAR64mi | |
| { 2278, 2, 1, 0, 0, "SAR64r1", 0, 0x1a2002017ULL, NULL, ImplicitList1, OperandInfo68 }, // Inst #2278 = SAR64r1 | |
| { 2279, 2, 1, 0, 0, "SAR64rCL", 0, 0x1a6002017ULL, ImplicitList48, ImplicitList1, OperandInfo68 }, // Inst #2279 = SAR64rCL | |
| { 2280, 3, 1, 0, 0, "SAR64ri", 0, 0x182006017ULL, NULL, ImplicitList1, OperandInfo25 }, // Inst #2280 = SAR64ri | |
| { 2281, 5, 0, 0, 0, "SAR8m1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a000001fULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2281 = SAR8m1 | |
| { 2282, 5, 0, 0, 0, "SAR8mCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a400001fULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2282 = SAR8mCL | |
| { 2283, 6, 0, 0, 0, "SAR8mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x18000401fULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2283 = SAR8mi | |
| { 2284, 2, 1, 0, 0, "SAR8r1", 0, 0x1a0000017ULL, NULL, ImplicitList1, OperandInfo112 }, // Inst #2284 = SAR8r1 | |
| { 2285, 2, 1, 0, 0, "SAR8rCL", 0, 0x1a4000017ULL, ImplicitList48, ImplicitList1, OperandInfo112 }, // Inst #2285 = SAR8rCL | |
| { 2286, 3, 1, 0, 0, "SAR8ri", 0, 0x180004017ULL, NULL, ImplicitList1, OperandInfo29 }, // Inst #2286 = SAR8ri | |
| { 2287, 1, 0, 0, 0, "SBB16i16", 0|(1<<MCID::UnmodeledSideEffects), 0x3a00c041ULL, ImplicitList1, ImplicitList1, OperandInfo2 }, // Inst #2287 = SBB16i16 | |
| { 2288, 6, 0, 0, 0, "SBB16mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10200c05bULL, ImplicitList1, ImplicitList1, OperandInfo15 }, // Inst #2288 = SBB16mi | |
| { 2289, 6, 0, 0, 0, "SBB16mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10600405bULL, ImplicitList1, ImplicitList1, OperandInfo15 }, // Inst #2289 = SBB16mi8 | |
| { 2290, 6, 0, 0, 0, "SBB16mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x32000044ULL, ImplicitList1, ImplicitList1, OperandInfo16 }, // Inst #2290 = SBB16mr | |
| { 2291, 3, 1, 0, 0, "SBB16ri", 0, 0x10200c053ULL, ImplicitList1, ImplicitList1, OperandInfo17 }, // Inst #2291 = SBB16ri | |
| { 2292, 3, 1, 0, 0, "SBB16ri8", 0, 0x106004053ULL, ImplicitList1, ImplicitList1, OperandInfo17 }, // Inst #2292 = SBB16ri8 | |
| { 2293, 7, 1, 0, 0, "SBB16rm", 0|(1<<MCID::MayLoad), 0x36000046ULL, ImplicitList1, ImplicitList1, OperandInfo18 }, // Inst #2293 = SBB16rm | |
| { 2294, 3, 1, 0, 0, "SBB16rr", 0, 0x32000043ULL, ImplicitList1, ImplicitList1, OperandInfo19 }, // Inst #2294 = SBB16rr | |
| { 2295, 3, 1, 0, 0, "SBB16rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x36000045ULL, ImplicitList1, ImplicitList1, OperandInfo19 }, // Inst #2295 = SBB16rr_REV | |
| { 2296, 1, 0, 0, 0, "SBB32i32", 0|(1<<MCID::UnmodeledSideEffects), 0x3a014001ULL, ImplicitList1, ImplicitList1, OperandInfo2 }, // Inst #2296 = SBB32i32 | |
| { 2297, 6, 0, 0, 0, "SBB32mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10201401bULL, ImplicitList1, ImplicitList1, OperandInfo15 }, // Inst #2297 = SBB32mi | |
| { 2298, 6, 0, 0, 0, "SBB32mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10600401bULL, ImplicitList1, ImplicitList1, OperandInfo15 }, // Inst #2298 = SBB32mi8 | |
| { 2299, 6, 0, 0, 0, "SBB32mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x32000004ULL, ImplicitList1, ImplicitList1, OperandInfo20 }, // Inst #2299 = SBB32mr | |
| { 2300, 3, 1, 0, 0, "SBB32ri", 0, 0x102014013ULL, ImplicitList1, ImplicitList1, OperandInfo21 }, // Inst #2300 = SBB32ri | |
| { 2301, 3, 1, 0, 0, "SBB32ri8", 0, 0x106004013ULL, ImplicitList1, ImplicitList1, OperandInfo21 }, // Inst #2301 = SBB32ri8 | |
| { 2302, 7, 1, 0, 0, "SBB32rm", 0|(1<<MCID::MayLoad), 0x36000006ULL, ImplicitList1, ImplicitList1, OperandInfo22 }, // Inst #2302 = SBB32rm | |
| { 2303, 3, 1, 0, 0, "SBB32rr", 0, 0x32000003ULL, ImplicitList1, ImplicitList1, OperandInfo23 }, // Inst #2303 = SBB32rr | |
| { 2304, 3, 1, 0, 0, "SBB32rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x36000005ULL, ImplicitList1, ImplicitList1, OperandInfo23 }, // Inst #2304 = SBB32rr_REV | |
| { 2305, 1, 0, 0, 0, "SBB64i32", 0|(1<<MCID::UnmodeledSideEffects), 0x3a016001ULL, ImplicitList1, ImplicitList1, OperandInfo2 }, // Inst #2305 = SBB64i32 | |
| { 2306, 6, 0, 0, 0, "SBB64mi32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10201601bULL, ImplicitList1, ImplicitList1, OperandInfo15 }, // Inst #2306 = SBB64mi32 | |
| { 2307, 6, 0, 0, 0, "SBB64mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10600601bULL, ImplicitList1, ImplicitList1, OperandInfo15 }, // Inst #2307 = SBB64mi8 | |
| { 2308, 6, 0, 0, 0, "SBB64mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x32002004ULL, ImplicitList1, ImplicitList1, OperandInfo24 }, // Inst #2308 = SBB64mr | |
| { 2309, 3, 1, 0, 0, "SBB64ri32", 0, 0x102016013ULL, ImplicitList1, ImplicitList1, OperandInfo25 }, // Inst #2309 = SBB64ri32 | |
| { 2310, 3, 1, 0, 0, "SBB64ri8", 0, 0x106006013ULL, ImplicitList1, ImplicitList1, OperandInfo25 }, // Inst #2310 = SBB64ri8 | |
| { 2311, 7, 1, 0, 0, "SBB64rm", 0|(1<<MCID::MayLoad), 0x36002006ULL, ImplicitList1, ImplicitList1, OperandInfo26 }, // Inst #2311 = SBB64rm | |
| { 2312, 3, 1, 0, 0, "SBB64rr", 0, 0x32002003ULL, ImplicitList1, ImplicitList1, OperandInfo27 }, // Inst #2312 = SBB64rr | |
| { 2313, 3, 1, 0, 0, "SBB64rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x36002005ULL, ImplicitList1, ImplicitList1, OperandInfo27 }, // Inst #2313 = SBB64rr_REV | |
| { 2314, 1, 0, 0, 0, "SBB8i8", 0|(1<<MCID::UnmodeledSideEffects), 0x38004001ULL, ImplicitList1, ImplicitList1, OperandInfo2 }, // Inst #2314 = SBB8i8 | |
| { 2315, 6, 0, 0, 0, "SBB8mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10000401bULL, ImplicitList1, ImplicitList1, OperandInfo15 }, // Inst #2315 = SBB8mi | |
| { 2316, 6, 0, 0, 0, "SBB8mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x30000004ULL, ImplicitList1, ImplicitList1, OperandInfo28 }, // Inst #2316 = SBB8mr | |
| { 2317, 3, 1, 0, 0, "SBB8ri", 0, 0x100004013ULL, ImplicitList1, ImplicitList1, OperandInfo29 }, // Inst #2317 = SBB8ri | |
| { 2318, 7, 1, 0, 0, "SBB8rm", 0|(1<<MCID::MayLoad), 0x34000006ULL, ImplicitList1, ImplicitList1, OperandInfo30 }, // Inst #2318 = SBB8rm | |
| { 2319, 3, 1, 0, 0, "SBB8rr", 0, 0x30000003ULL, ImplicitList1, ImplicitList1, OperandInfo31 }, // Inst #2319 = SBB8rr | |
| { 2320, 3, 1, 0, 0, "SBB8rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x34000005ULL, ImplicitList1, ImplicitList1, OperandInfo31 }, // Inst #2320 = SBB8rr_REV | |
| { 2321, 0, 0, 0, 0, "SCAS16", 0|(1<<MCID::UnmodeledSideEffects), 0x15e000041ULL, NULL, NULL, 0 }, // Inst #2321 = SCAS16 | |
| { 2322, 0, 0, 0, 0, "SCAS32", 0|(1<<MCID::UnmodeledSideEffects), 0x15e000001ULL, NULL, NULL, 0 }, // Inst #2322 = SCAS32 | |
| { 2323, 0, 0, 0, 0, "SCAS64", 0|(1<<MCID::UnmodeledSideEffects), 0x15e002001ULL, NULL, NULL, 0 }, // Inst #2323 = SCAS64 | |
| { 2324, 0, 0, 0, 0, "SCAS8", 0|(1<<MCID::UnmodeledSideEffects), 0x15c000001ULL, NULL, NULL, 0 }, // Inst #2324 = SCAS8 | |
| { 2325, 2, 1, 0, 0, "SEG_ALLOCA_32", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList58, ImplicitList59, OperandInfo65 }, // Inst #2325 = SEG_ALLOCA_32 | |
| { 2326, 2, 1, 0, 0, "SEG_ALLOCA_64", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList60, ImplicitList61, OperandInfo66 }, // Inst #2326 = SEG_ALLOCA_64 | |
| { 2327, 5, 0, 0, 0, "SETAEm", 0|(1<<MCID::MayStore), 0x126000118ULL, ImplicitList1, NULL, OperandInfo38 }, // Inst #2327 = SETAEm | |
| { 2328, 1, 1, 0, 0, "SETAEr", 0, 0x126000110ULL, ImplicitList1, NULL, OperandInfo114 }, // Inst #2328 = SETAEr | |
| { 2329, 5, 0, 0, 0, "SETAm", 0|(1<<MCID::MayStore), 0x12e000118ULL, ImplicitList1, NULL, OperandInfo38 }, // Inst #2329 = SETAm | |
| { 2330, 1, 1, 0, 0, "SETAr", 0, 0x12e000110ULL, ImplicitList1, NULL, OperandInfo114 }, // Inst #2330 = SETAr | |
| { 2331, 5, 0, 0, 0, "SETBEm", 0|(1<<MCID::MayStore), 0x12c000118ULL, ImplicitList1, NULL, OperandInfo38 }, // Inst #2331 = SETBEm | |
| { 2332, 1, 1, 0, 0, "SETBEr", 0, 0x12c000110ULL, ImplicitList1, NULL, OperandInfo114 }, // Inst #2332 = SETBEr | |
| { 2333, 1, 1, 0, 0, "SETB_C16r", 0, 0x32000060ULL, ImplicitList1, ImplicitList1, OperandInfo113 }, // Inst #2333 = SETB_C16r | |
| { 2334, 1, 1, 0, 0, "SETB_C32r", 0, 0x32000020ULL, ImplicitList1, ImplicitList1, OperandInfo72 }, // Inst #2334 = SETB_C32r | |
| { 2335, 1, 1, 0, 0, "SETB_C64r", 0, 0x32002020ULL, ImplicitList1, ImplicitList1, OperandInfo74 }, // Inst #2335 = SETB_C64r | |
| { 2336, 1, 1, 0, 0, "SETB_C8r", 0, 0x30000020ULL, ImplicitList1, ImplicitList1, OperandInfo114 }, // Inst #2336 = SETB_C8r | |
| { 2337, 5, 0, 0, 0, "SETBm", 0|(1<<MCID::MayStore), 0x124000118ULL, ImplicitList1, NULL, OperandInfo38 }, // Inst #2337 = SETBm | |
| { 2338, 1, 1, 0, 0, "SETBr", 0, 0x124000110ULL, ImplicitList1, NULL, OperandInfo114 }, // Inst #2338 = SETBr | |
| { 2339, 5, 0, 0, 0, "SETEm", 0|(1<<MCID::MayStore), 0x128000118ULL, ImplicitList1, NULL, OperandInfo38 }, // Inst #2339 = SETEm | |
| { 2340, 1, 1, 0, 0, "SETEr", 0, 0x128000110ULL, ImplicitList1, NULL, OperandInfo114 }, // Inst #2340 = SETEr | |
| { 2341, 5, 0, 0, 0, "SETGEm", 0|(1<<MCID::MayStore), 0x13a000118ULL, ImplicitList1, NULL, OperandInfo38 }, // Inst #2341 = SETGEm | |
| { 2342, 1, 1, 0, 0, "SETGEr", 0, 0x13a000110ULL, ImplicitList1, NULL, OperandInfo114 }, // Inst #2342 = SETGEr | |
| { 2343, 5, 0, 0, 0, "SETGm", 0|(1<<MCID::MayStore), 0x13e000118ULL, ImplicitList1, NULL, OperandInfo38 }, // Inst #2343 = SETGm | |
| { 2344, 1, 1, 0, 0, "SETGr", 0, 0x13e000110ULL, ImplicitList1, NULL, OperandInfo114 }, // Inst #2344 = SETGr | |
| { 2345, 5, 0, 0, 0, "SETLEm", 0|(1<<MCID::MayStore), 0x13c000118ULL, ImplicitList1, NULL, OperandInfo38 }, // Inst #2345 = SETLEm | |
| { 2346, 1, 1, 0, 0, "SETLEr", 0, 0x13c000110ULL, ImplicitList1, NULL, OperandInfo114 }, // Inst #2346 = SETLEr | |
| { 2347, 5, 0, 0, 0, "SETLm", 0|(1<<MCID::MayStore), 0x138000118ULL, ImplicitList1, NULL, OperandInfo38 }, // Inst #2347 = SETLm | |
| { 2348, 1, 1, 0, 0, "SETLr", 0, 0x138000110ULL, ImplicitList1, NULL, OperandInfo114 }, // Inst #2348 = SETLr | |
| { 2349, 5, 0, 0, 0, "SETNEm", 0|(1<<MCID::MayStore), 0x12a000118ULL, ImplicitList1, NULL, OperandInfo38 }, // Inst #2349 = SETNEm | |
| { 2350, 1, 1, 0, 0, "SETNEr", 0, 0x12a000110ULL, ImplicitList1, NULL, OperandInfo114 }, // Inst #2350 = SETNEr | |
| { 2351, 5, 0, 0, 0, "SETNOm", 0|(1<<MCID::MayStore), 0x122000118ULL, ImplicitList1, NULL, OperandInfo38 }, // Inst #2351 = SETNOm | |
| { 2352, 1, 1, 0, 0, "SETNOr", 0, 0x122000110ULL, ImplicitList1, NULL, OperandInfo114 }, // Inst #2352 = SETNOr | |
| { 2353, 5, 0, 0, 0, "SETNPm", 0|(1<<MCID::MayStore), 0x136000118ULL, ImplicitList1, NULL, OperandInfo38 }, // Inst #2353 = SETNPm | |
| { 2354, 1, 1, 0, 0, "SETNPr", 0, 0x136000110ULL, ImplicitList1, NULL, OperandInfo114 }, // Inst #2354 = SETNPr | |
| { 2355, 5, 0, 0, 0, "SETNSm", 0|(1<<MCID::MayStore), 0x132000118ULL, ImplicitList1, NULL, OperandInfo38 }, // Inst #2355 = SETNSm | |
| { 2356, 1, 1, 0, 0, "SETNSr", 0, 0x132000110ULL, ImplicitList1, NULL, OperandInfo114 }, // Inst #2356 = SETNSr | |
| { 2357, 5, 0, 0, 0, "SETOm", 0|(1<<MCID::MayStore), 0x120000118ULL, ImplicitList1, NULL, OperandInfo38 }, // Inst #2357 = SETOm | |
| { 2358, 1, 1, 0, 0, "SETOr", 0, 0x120000110ULL, ImplicitList1, NULL, OperandInfo114 }, // Inst #2358 = SETOr | |
| { 2359, 5, 0, 0, 0, "SETPm", 0|(1<<MCID::MayStore), 0x134000118ULL, ImplicitList1, NULL, OperandInfo38 }, // Inst #2359 = SETPm | |
| { 2360, 1, 1, 0, 0, "SETPr", 0, 0x134000110ULL, ImplicitList1, NULL, OperandInfo114 }, // Inst #2360 = SETPr | |
| { 2361, 5, 0, 0, 0, "SETSm", 0|(1<<MCID::MayStore), 0x130000118ULL, ImplicitList1, NULL, OperandInfo38 }, // Inst #2361 = SETSm | |
| { 2362, 1, 1, 0, 0, "SETSr", 0, 0x130000110ULL, ImplicitList1, NULL, OperandInfo114 }, // Inst #2362 = SETSr | |
| { 2363, 0, 0, 0, 0, "SFENCE", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x15c000129ULL, NULL, NULL, 0 }, // Inst #2363 = SFENCE | |
| { 2364, 5, 1, 0, 0, "SGDT16m", 0|(1<<MCID::UnmodeledSideEffects), 0x2000158ULL, NULL, NULL, OperandInfo38 }, // Inst #2364 = SGDT16m | |
| { 2365, 5, 1, 0, 0, "SGDTm", 0|(1<<MCID::UnmodeledSideEffects), 0x2000118ULL, NULL, NULL, OperandInfo38 }, // Inst #2365 = SGDTm | |
| { 2366, 5, 0, 0, 0, "SHL16m1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a200005cULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2366 = SHL16m1 | |
| { 2367, 5, 0, 0, 0, "SHL16mCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a600005cULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2367 = SHL16mCL | |
| { 2368, 6, 0, 0, 0, "SHL16mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x18200405cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2368 = SHL16mi | |
| { 2369, 2, 1, 0, 0, "SHL16r1", 0|(1<<MCID::ConvertibleTo3Addr)|(1<<MCID::UnmodeledSideEffects), 0x1a2000054ULL, NULL, ImplicitList1, OperandInfo111 }, // Inst #2369 = SHL16r1 | |
| { 2370, 2, 1, 0, 0, "SHL16rCL", 0, 0x1a6000054ULL, ImplicitList48, ImplicitList1, OperandInfo111 }, // Inst #2370 = SHL16rCL | |
| { 2371, 3, 1, 0, 0, "SHL16ri", 0|(1<<MCID::ConvertibleTo3Addr), 0x182004054ULL, NULL, ImplicitList1, OperandInfo17 }, // Inst #2371 = SHL16ri | |
| { 2372, 5, 0, 0, 0, "SHL32m1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a200001cULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2372 = SHL32m1 | |
| { 2373, 5, 0, 0, 0, "SHL32mCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a600001cULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2373 = SHL32mCL | |
| { 2374, 6, 0, 0, 0, "SHL32mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x18200401cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2374 = SHL32mi | |
| { 2375, 2, 1, 0, 0, "SHL32r1", 0|(1<<MCID::ConvertibleTo3Addr)|(1<<MCID::UnmodeledSideEffects), 0x1a2000014ULL, NULL, ImplicitList1, OperandInfo67 }, // Inst #2375 = SHL32r1 | |
| { 2376, 2, 1, 0, 0, "SHL32rCL", 0, 0x1a6000014ULL, ImplicitList48, ImplicitList1, OperandInfo67 }, // Inst #2376 = SHL32rCL | |
| { 2377, 3, 1, 0, 0, "SHL32ri", 0|(1<<MCID::ConvertibleTo3Addr), 0x182004014ULL, NULL, ImplicitList1, OperandInfo21 }, // Inst #2377 = SHL32ri | |
| { 2378, 5, 0, 0, 0, "SHL64m1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a200201cULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2378 = SHL64m1 | |
| { 2379, 5, 0, 0, 0, "SHL64mCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a600201cULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2379 = SHL64mCL | |
| { 2380, 6, 0, 0, 0, "SHL64mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x18200601cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2380 = SHL64mi | |
| { 2381, 2, 1, 0, 0, "SHL64r1", 0|(1<<MCID::ConvertibleTo3Addr)|(1<<MCID::UnmodeledSideEffects), 0x1a2002014ULL, NULL, ImplicitList1, OperandInfo68 }, // Inst #2381 = SHL64r1 | |
| { 2382, 2, 1, 0, 0, "SHL64rCL", 0, 0x1a6002014ULL, ImplicitList48, ImplicitList1, OperandInfo68 }, // Inst #2382 = SHL64rCL | |
| { 2383, 3, 1, 0, 0, "SHL64ri", 0|(1<<MCID::ConvertibleTo3Addr), 0x182006014ULL, NULL, ImplicitList1, OperandInfo25 }, // Inst #2383 = SHL64ri | |
| { 2384, 5, 0, 0, 0, "SHL8m1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a000001cULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2384 = SHL8m1 | |
| { 2385, 5, 0, 0, 0, "SHL8mCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a400001cULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2385 = SHL8mCL | |
| { 2386, 6, 0, 0, 0, "SHL8mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x18000401cULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2386 = SHL8mi | |
| { 2387, 2, 1, 0, 0, "SHL8r1", 0|(1<<MCID::ConvertibleTo3Addr)|(1<<MCID::UnmodeledSideEffects), 0x1a0000014ULL, NULL, ImplicitList1, OperandInfo112 }, // Inst #2387 = SHL8r1 | |
| { 2388, 2, 1, 0, 0, "SHL8rCL", 0, 0x1a4000014ULL, ImplicitList48, ImplicitList1, OperandInfo112 }, // Inst #2388 = SHL8rCL | |
| { 2389, 3, 1, 0, 0, "SHL8ri", 0, 0x180004014ULL, NULL, ImplicitList1, OperandInfo29 }, // Inst #2389 = SHL8ri | |
| { 2390, 6, 0, 0, 0, "SHLD16mrCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x14a000144ULL, ImplicitList48, ImplicitList1, OperandInfo16 }, // Inst #2390 = SHLD16mrCL | |
| { 2391, 7, 0, 0, 0, "SHLD16mri8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x148004144ULL, NULL, ImplicitList1, OperandInfo204 }, // Inst #2391 = SHLD16mri8 | |
| { 2392, 3, 1, 0, 0, "SHLD16rrCL", 0, 0x14a000143ULL, ImplicitList48, ImplicitList1, OperandInfo19 }, // Inst #2392 = SHLD16rrCL | |
| { 2393, 4, 1, 0, 0, "SHLD16rri8", 0|(1<<MCID::Commutable), 0x148004143ULL, NULL, ImplicitList1, OperandInfo205 }, // Inst #2393 = SHLD16rri8 | |
| { 2394, 6, 0, 0, 0, "SHLD32mrCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x14a000104ULL, ImplicitList48, ImplicitList1, OperandInfo20 }, // Inst #2394 = SHLD32mrCL | |
| { 2395, 7, 0, 0, 0, "SHLD32mri8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x148004104ULL, NULL, ImplicitList1, OperandInfo206 }, // Inst #2395 = SHLD32mri8 | |
| { 2396, 3, 1, 0, 0, "SHLD32rrCL", 0, 0x14a000103ULL, ImplicitList48, ImplicitList1, OperandInfo23 }, // Inst #2396 = SHLD32rrCL | |
| { 2397, 4, 1, 0, 0, "SHLD32rri8", 0|(1<<MCID::Commutable), 0x148004103ULL, NULL, ImplicitList1, OperandInfo207 }, // Inst #2397 = SHLD32rri8 | |
| { 2398, 6, 0, 0, 0, "SHLD64mrCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x14a002104ULL, ImplicitList48, ImplicitList1, OperandInfo24 }, // Inst #2398 = SHLD64mrCL | |
| { 2399, 7, 0, 0, 0, "SHLD64mri8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x148006104ULL, NULL, ImplicitList1, OperandInfo208 }, // Inst #2399 = SHLD64mri8 | |
| { 2400, 3, 1, 0, 0, "SHLD64rrCL", 0, 0x14a002103ULL, ImplicitList48, ImplicitList1, OperandInfo27 }, // Inst #2400 = SHLD64rrCL | |
| { 2401, 4, 1, 0, 0, "SHLD64rri8", 0|(1<<MCID::Commutable), 0x148006103ULL, NULL, ImplicitList1, OperandInfo209 }, // Inst #2401 = SHLD64rri8 | |
| { 2402, 5, 0, 0, 0, "SHR16m1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a200005dULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2402 = SHR16m1 | |
| { 2403, 5, 0, 0, 0, "SHR16mCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a600005dULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2403 = SHR16mCL | |
| { 2404, 6, 0, 0, 0, "SHR16mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x18200405dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2404 = SHR16mi | |
| { 2405, 2, 1, 0, 0, "SHR16r1", 0, 0x1a2000055ULL, NULL, ImplicitList1, OperandInfo111 }, // Inst #2405 = SHR16r1 | |
| { 2406, 2, 1, 0, 0, "SHR16rCL", 0, 0x1a6000055ULL, ImplicitList48, ImplicitList1, OperandInfo111 }, // Inst #2406 = SHR16rCL | |
| { 2407, 3, 1, 0, 0, "SHR16ri", 0, 0x182004055ULL, NULL, ImplicitList1, OperandInfo17 }, // Inst #2407 = SHR16ri | |
| { 2408, 5, 0, 0, 0, "SHR32m1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a200001dULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2408 = SHR32m1 | |
| { 2409, 5, 0, 0, 0, "SHR32mCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a600001dULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2409 = SHR32mCL | |
| { 2410, 6, 0, 0, 0, "SHR32mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x18200401dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2410 = SHR32mi | |
| { 2411, 2, 1, 0, 0, "SHR32r1", 0, 0x1a2000015ULL, NULL, ImplicitList1, OperandInfo67 }, // Inst #2411 = SHR32r1 | |
| { 2412, 2, 1, 0, 0, "SHR32rCL", 0, 0x1a6000015ULL, ImplicitList48, ImplicitList1, OperandInfo67 }, // Inst #2412 = SHR32rCL | |
| { 2413, 3, 1, 0, 0, "SHR32ri", 0, 0x182004015ULL, NULL, ImplicitList1, OperandInfo21 }, // Inst #2413 = SHR32ri | |
| { 2414, 5, 0, 0, 0, "SHR64m1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a200201dULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2414 = SHR64m1 | |
| { 2415, 5, 0, 0, 0, "SHR64mCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a600201dULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2415 = SHR64mCL | |
| { 2416, 6, 0, 0, 0, "SHR64mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x18200601dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2416 = SHR64mi | |
| { 2417, 2, 1, 0, 0, "SHR64r1", 0, 0x1a2002015ULL, NULL, ImplicitList1, OperandInfo68 }, // Inst #2417 = SHR64r1 | |
| { 2418, 2, 1, 0, 0, "SHR64rCL", 0, 0x1a6002015ULL, ImplicitList48, ImplicitList1, OperandInfo68 }, // Inst #2418 = SHR64rCL | |
| { 2419, 3, 1, 0, 0, "SHR64ri", 0, 0x182006015ULL, NULL, ImplicitList1, OperandInfo25 }, // Inst #2419 = SHR64ri | |
| { 2420, 5, 0, 0, 0, "SHR8m1", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a000001dULL, NULL, ImplicitList1, OperandInfo38 }, // Inst #2420 = SHR8m1 | |
| { 2421, 5, 0, 0, 0, "SHR8mCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x1a400001dULL, ImplicitList48, ImplicitList1, OperandInfo38 }, // Inst #2421 = SHR8mCL | |
| { 2422, 6, 0, 0, 0, "SHR8mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x18000401dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2422 = SHR8mi | |
| { 2423, 2, 1, 0, 0, "SHR8r1", 0, 0x1a0000015ULL, NULL, ImplicitList1, OperandInfo112 }, // Inst #2423 = SHR8r1 | |
| { 2424, 2, 1, 0, 0, "SHR8rCL", 0, 0x1a4000015ULL, ImplicitList48, ImplicitList1, OperandInfo112 }, // Inst #2424 = SHR8rCL | |
| { 2425, 3, 1, 0, 0, "SHR8ri", 0, 0x180004015ULL, NULL, ImplicitList1, OperandInfo29 }, // Inst #2425 = SHR8ri | |
| { 2426, 6, 0, 0, 0, "SHRD16mrCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x15a000144ULL, ImplicitList48, ImplicitList1, OperandInfo16 }, // Inst #2426 = SHRD16mrCL | |
| { 2427, 7, 0, 0, 0, "SHRD16mri8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x158004144ULL, NULL, ImplicitList1, OperandInfo204 }, // Inst #2427 = SHRD16mri8 | |
| { 2428, 3, 1, 0, 0, "SHRD16rrCL", 0, 0x15a000143ULL, ImplicitList48, ImplicitList1, OperandInfo19 }, // Inst #2428 = SHRD16rrCL | |
| { 2429, 4, 1, 0, 0, "SHRD16rri8", 0|(1<<MCID::Commutable), 0x158004143ULL, NULL, ImplicitList1, OperandInfo205 }, // Inst #2429 = SHRD16rri8 | |
| { 2430, 6, 0, 0, 0, "SHRD32mrCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x15a000104ULL, ImplicitList48, ImplicitList1, OperandInfo20 }, // Inst #2430 = SHRD32mrCL | |
| { 2431, 7, 0, 0, 0, "SHRD32mri8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x158004104ULL, NULL, ImplicitList1, OperandInfo206 }, // Inst #2431 = SHRD32mri8 | |
| { 2432, 3, 1, 0, 0, "SHRD32rrCL", 0, 0x15a000103ULL, ImplicitList48, ImplicitList1, OperandInfo23 }, // Inst #2432 = SHRD32rrCL | |
| { 2433, 4, 1, 0, 0, "SHRD32rri8", 0|(1<<MCID::Commutable), 0x158004103ULL, NULL, ImplicitList1, OperandInfo207 }, // Inst #2433 = SHRD32rri8 | |
| { 2434, 6, 0, 0, 0, "SHRD64mrCL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x15a002104ULL, ImplicitList48, ImplicitList1, OperandInfo24 }, // Inst #2434 = SHRD64mrCL | |
| { 2435, 7, 0, 0, 0, "SHRD64mri8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x158006104ULL, NULL, ImplicitList1, OperandInfo208 }, // Inst #2435 = SHRD64mri8 | |
| { 2436, 3, 1, 0, 0, "SHRD64rrCL", 0, 0x15a002103ULL, ImplicitList48, ImplicitList1, OperandInfo27 }, // Inst #2436 = SHRD64rrCL | |
| { 2437, 4, 1, 0, 0, "SHRD64rri8", 0|(1<<MCID::Commutable), 0x158006103ULL, NULL, ImplicitList1, OperandInfo209 }, // Inst #2437 = SHRD64rri8 | |
| { 2438, 8, 1, 0, 0, "SHUFPDrmi", 0|(1<<MCID::MayLoad), 0x18d004146ULL, NULL, NULL, OperandInfo63 }, // Inst #2438 = SHUFPDrmi | |
| { 2439, 4, 1, 0, 0, "SHUFPDrri", 0, 0x18d004145ULL, NULL, NULL, OperandInfo64 }, // Inst #2439 = SHUFPDrri | |
| { 2440, 8, 1, 0, 0, "SHUFPSrmi", 0|(1<<MCID::MayLoad), 0x18c804106ULL, NULL, NULL, OperandInfo63 }, // Inst #2440 = SHUFPSrmi | |
| { 2441, 4, 1, 0, 0, "SHUFPSrri", 0|(1<<MCID::ConvertibleTo3Addr), 0x18c804105ULL, NULL, NULL, OperandInfo64 }, // Inst #2441 = SHUFPSrri | |
| { 2442, 5, 1, 0, 0, "SIDT16m", 0|(1<<MCID::UnmodeledSideEffects), 0x2000159ULL, NULL, NULL, OperandInfo38 }, // Inst #2442 = SIDT16m | |
| { 2443, 5, 1, 0, 0, "SIDTm", 0|(1<<MCID::UnmodeledSideEffects), 0x2000119ULL, NULL, NULL, OperandInfo38 }, // Inst #2443 = SIDTm | |
| { 2444, 0, 0, 0, 0, "SIN_F", 0|(1<<MCID::UnmodeledSideEffects), 0x1fc000401ULL, NULL, NULL, 0 }, // Inst #2444 = SIN_F | |
| { 2445, 2, 1, 0, 0, "SIN_Fp32", 0, 0x60000ULL, NULL, NULL, OperandInfo8 }, // Inst #2445 = SIN_Fp32 | |
| { 2446, 2, 1, 0, 0, "SIN_Fp64", 0, 0x60000ULL, NULL, NULL, OperandInfo9 }, // Inst #2446 = SIN_Fp64 | |
| { 2447, 2, 1, 0, 0, "SIN_Fp80", 0, 0x60000ULL, NULL, NULL, OperandInfo10 }, // Inst #2447 = SIN_Fp80 | |
| { 2448, 5, 1, 0, 0, "SLDT16m", 0|(1<<MCID::UnmodeledSideEffects), 0x118ULL, NULL, NULL, OperandInfo38 }, // Inst #2448 = SLDT16m | |
| { 2449, 1, 1, 0, 0, "SLDT16r", 0|(1<<MCID::UnmodeledSideEffects), 0x150ULL, NULL, NULL, OperandInfo113 }, // Inst #2449 = SLDT16r | |
| { 2450, 1, 1, 0, 0, "SLDT32r", 0|(1<<MCID::UnmodeledSideEffects), 0x110ULL, NULL, NULL, OperandInfo72 }, // Inst #2450 = SLDT32r | |
| { 2451, 5, 1, 0, 0, "SLDT64m", 0|(1<<MCID::UnmodeledSideEffects), 0x2118ULL, NULL, NULL, OperandInfo38 }, // Inst #2451 = SLDT64m | |
| { 2452, 1, 1, 0, 0, "SLDT64r", 0|(1<<MCID::UnmodeledSideEffects), 0x2110ULL, NULL, NULL, OperandInfo74 }, // Inst #2452 = SLDT64r | |
| { 2453, 5, 1, 0, 0, "SMSW16m", 0|(1<<MCID::UnmodeledSideEffects), 0x200011cULL, NULL, NULL, OperandInfo38 }, // Inst #2453 = SMSW16m | |
| { 2454, 1, 1, 0, 0, "SMSW16r", 0|(1<<MCID::UnmodeledSideEffects), 0x2000154ULL, NULL, NULL, OperandInfo113 }, // Inst #2454 = SMSW16r | |
| { 2455, 1, 1, 0, 0, "SMSW32r", 0|(1<<MCID::UnmodeledSideEffects), 0x2000114ULL, NULL, NULL, OperandInfo72 }, // Inst #2455 = SMSW32r | |
| { 2456, 1, 1, 0, 0, "SMSW64r", 0|(1<<MCID::UnmodeledSideEffects), 0x2002114ULL, NULL, NULL, OperandInfo74 }, // Inst #2456 = SMSW64r | |
| { 2457, 6, 1, 0, 0, "SQRTPDm", 0|(1<<MCID::MayLoad), 0xa3000146ULL, NULL, NULL, OperandInfo47 }, // Inst #2457 = SQRTPDm | |
| { 2458, 6, 1, 0, 0, "SQRTPDm_Int", 0|(1<<MCID::MayLoad), 0xa3000146ULL, NULL, NULL, OperandInfo47 }, // Inst #2458 = SQRTPDm_Int | |
| { 2459, 2, 1, 0, 0, "SQRTPDr", 0, 0xa3000145ULL, NULL, NULL, OperandInfo48 }, // Inst #2459 = SQRTPDr | |
| { 2460, 2, 1, 0, 0, "SQRTPDr_Int", 0, 0xa3000145ULL, NULL, NULL, OperandInfo48 }, // Inst #2460 = SQRTPDr_Int | |
| { 2461, 6, 1, 0, 0, "SQRTPSm", 0|(1<<MCID::MayLoad), 0xa2800106ULL, NULL, NULL, OperandInfo47 }, // Inst #2461 = SQRTPSm | |
| { 2462, 6, 1, 0, 0, "SQRTPSm_Int", 0|(1<<MCID::MayLoad), 0xa2800106ULL, NULL, NULL, OperandInfo47 }, // Inst #2462 = SQRTPSm_Int | |
| { 2463, 2, 1, 0, 0, "SQRTPSr", 0, 0xa2800105ULL, NULL, NULL, OperandInfo48 }, // Inst #2463 = SQRTPSr | |
| { 2464, 2, 1, 0, 0, "SQRTPSr_Int", 0, 0xa2800105ULL, NULL, NULL, OperandInfo48 }, // Inst #2464 = SQRTPSr_Int | |
| { 2465, 6, 1, 0, 0, "SQRTSDm", 0|(1<<MCID::MayLoad), 0xa2000b06ULL, NULL, NULL, OperandInfo101 }, // Inst #2465 = SQRTSDm | |
| { 2466, 6, 1, 0, 0, "SQRTSDm_Int", 0|(1<<MCID::MayLoad), 0xa2000b06ULL, NULL, NULL, OperandInfo47 }, // Inst #2466 = SQRTSDm_Int | |
| { 2467, 2, 1, 0, 0, "SQRTSDr", 0, 0xa2000b05ULL, NULL, NULL, OperandInfo123 }, // Inst #2467 = SQRTSDr | |
| { 2468, 2, 1, 0, 0, "SQRTSDr_Int", 0, 0xa2000b05ULL, NULL, NULL, OperandInfo48 }, // Inst #2468 = SQRTSDr_Int | |
| { 2469, 6, 1, 0, 0, "SQRTSSm", 0|(1<<MCID::MayLoad), 0xa2000c06ULL, NULL, NULL, OperandInfo99 }, // Inst #2469 = SQRTSSm | |
| { 2470, 6, 1, 0, 0, "SQRTSSm_Int", 0|(1<<MCID::MayLoad), 0xa2000c06ULL, NULL, NULL, OperandInfo47 }, // Inst #2470 = SQRTSSm_Int | |
| { 2471, 2, 1, 0, 0, "SQRTSSr", 0, 0xa2000c05ULL, NULL, NULL, OperandInfo124 }, // Inst #2471 = SQRTSSr | |
| { 2472, 2, 1, 0, 0, "SQRTSSr_Int", 0, 0xa2000c05ULL, NULL, NULL, OperandInfo48 }, // Inst #2472 = SQRTSSr_Int | |
| { 2473, 0, 0, 0, 0, "SQRT_F", 0|(1<<MCID::UnmodeledSideEffects), 0x1f4000401ULL, NULL, NULL, 0 }, // Inst #2473 = SQRT_F | |
| { 2474, 2, 1, 0, 0, "SQRT_Fp32", 0, 0x60000ULL, NULL, NULL, OperandInfo8 }, // Inst #2474 = SQRT_Fp32 | |
| { 2475, 2, 1, 0, 0, "SQRT_Fp64", 0, 0x60000ULL, NULL, NULL, OperandInfo9 }, // Inst #2475 = SQRT_Fp64 | |
| { 2476, 2, 1, 0, 0, "SQRT_Fp80", 0, 0x60000ULL, NULL, NULL, OperandInfo10 }, // Inst #2476 = SQRT_Fp80 | |
| { 2477, 0, 0, 0, 0, "SS_PREFIX", 0|(1<<MCID::UnmodeledSideEffects), 0x6c000001ULL, NULL, NULL, 0 }, // Inst #2477 = SS_PREFIX | |
| { 2478, 0, 0, 0, 0, "STC", 0|(1<<MCID::UnmodeledSideEffects), 0x1f2000001ULL, NULL, NULL, 0 }, // Inst #2478 = STC | |
| { 2479, 0, 0, 0, 0, "STD", 0|(1<<MCID::UnmodeledSideEffects), 0x1fa000001ULL, NULL, NULL, 0 }, // Inst #2479 = STD | |
| { 2480, 0, 0, 0, 0, "STI", 0|(1<<MCID::UnmodeledSideEffects), 0x1f6000001ULL, NULL, NULL, 0 }, // Inst #2480 = STI | |
| { 2481, 5, 0, 0, 0, "STMXCSR", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x15c80011bULL, NULL, NULL, OperandInfo38 }, // Inst #2481 = STMXCSR | |
| { 2482, 0, 0, 0, 0, "STOSB", 0|(1<<MCID::UnmodeledSideEffects), 0x154000001ULL, ImplicitList62, ImplicitList34, 0 }, // Inst #2482 = STOSB | |
| { 2483, 0, 0, 0, 0, "STOSD", 0|(1<<MCID::UnmodeledSideEffects), 0x156000001ULL, ImplicitList63, ImplicitList34, 0 }, // Inst #2483 = STOSD | |
| { 2484, 0, 0, 0, 0, "STOSQ", 0|(1<<MCID::UnmodeledSideEffects), 0x156002001ULL, ImplicitList64, ImplicitList56, 0 }, // Inst #2484 = STOSQ | |
| { 2485, 0, 0, 0, 0, "STOSW", 0|(1<<MCID::UnmodeledSideEffects), 0x156000041ULL, ImplicitList65, ImplicitList34, 0 }, // Inst #2485 = STOSW | |
| { 2486, 1, 1, 0, 0, "STR16r", 0|(1<<MCID::UnmodeledSideEffects), 0x151ULL, NULL, NULL, OperandInfo113 }, // Inst #2486 = STR16r | |
| { 2487, 1, 1, 0, 0, "STR32r", 0|(1<<MCID::UnmodeledSideEffects), 0x111ULL, NULL, NULL, OperandInfo72 }, // Inst #2487 = STR32r | |
| { 2488, 1, 1, 0, 0, "STR64r", 0|(1<<MCID::UnmodeledSideEffects), 0x2111ULL, NULL, NULL, OperandInfo74 }, // Inst #2488 = STR64r | |
| { 2489, 5, 1, 0, 0, "STRm", 0|(1<<MCID::UnmodeledSideEffects), 0x119ULL, NULL, NULL, OperandInfo38 }, // Inst #2489 = STRm | |
| { 2490, 5, 0, 0, 0, "ST_F32m", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1b200001aULL, NULL, NULL, OperandInfo38 }, // Inst #2490 = ST_F32m | |
| { 2491, 5, 0, 0, 0, "ST_F64m", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1ba00001aULL, NULL, NULL, OperandInfo38 }, // Inst #2491 = ST_F64m | |
| { 2492, 5, 0, 0, 0, "ST_FP32m", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1b200001bULL, NULL, NULL, OperandInfo38 }, // Inst #2492 = ST_FP32m | |
| { 2493, 5, 0, 0, 0, "ST_FP64m", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1ba00001bULL, NULL, NULL, OperandInfo38 }, // Inst #2493 = ST_FP64m | |
| { 2494, 5, 0, 0, 0, "ST_FP80m", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x1b600001fULL, NULL, NULL, OperandInfo38 }, // Inst #2494 = ST_FP80m | |
| { 2495, 1, 0, 0, 0, "ST_FPrr", 0|(1<<MCID::UnmodeledSideEffects), 0x1b0000802ULL, NULL, NULL, OperandInfo39 }, // Inst #2495 = ST_FPrr | |
| { 2496, 6, 0, 0, 0, "ST_Fp32m", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo117 }, // Inst #2496 = ST_Fp32m | |
| { 2497, 6, 0, 0, 0, "ST_Fp64m", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo118 }, // Inst #2497 = ST_Fp64m | |
| { 2498, 6, 0, 0, 0, "ST_Fp64m32", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo118 }, // Inst #2498 = ST_Fp64m32 | |
| { 2499, 6, 0, 0, 0, "ST_Fp80m32", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo119 }, // Inst #2499 = ST_Fp80m32 | |
| { 2500, 6, 0, 0, 0, "ST_Fp80m64", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo119 }, // Inst #2500 = ST_Fp80m64 | |
| { 2501, 6, 0, 0, 0, "ST_FpP32m", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo117 }, // Inst #2501 = ST_FpP32m | |
| { 2502, 6, 0, 0, 0, "ST_FpP64m", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo118 }, // Inst #2502 = ST_FpP64m | |
| { 2503, 6, 0, 0, 0, "ST_FpP64m32", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo118 }, // Inst #2503 = ST_FpP64m32 | |
| { 2504, 6, 0, 0, 0, "ST_FpP80m", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo119 }, // Inst #2504 = ST_FpP80m | |
| { 2505, 6, 0, 0, 0, "ST_FpP80m32", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo119 }, // Inst #2505 = ST_FpP80m32 | |
| { 2506, 6, 0, 0, 0, "ST_FpP80m64", 0|(1<<MCID::MayStore), 0x40000ULL, NULL, NULL, OperandInfo119 }, // Inst #2506 = ST_FpP80m64 | |
| { 2507, 1, 0, 0, 0, "ST_Frr", 0|(1<<MCID::UnmodeledSideEffects), 0x1a0000802ULL, NULL, NULL, OperandInfo39 }, // Inst #2507 = ST_Frr | |
| { 2508, 1, 0, 0, 0, "SUB16i16", 0|(1<<MCID::UnmodeledSideEffects), 0x5a00c041ULL, ImplicitList2, ImplicitList1, OperandInfo2 }, // Inst #2508 = SUB16i16 | |
| { 2509, 6, 0, 0, 0, "SUB16mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10200c05dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2509 = SUB16mi | |
| { 2510, 6, 0, 0, 0, "SUB16mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10600405dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2510 = SUB16mi8 | |
| { 2511, 6, 0, 0, 0, "SUB16mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x52000044ULL, NULL, ImplicitList1, OperandInfo16 }, // Inst #2511 = SUB16mr | |
| { 2512, 3, 1, 0, 0, "SUB16ri", 0, 0x10200c055ULL, NULL, ImplicitList1, OperandInfo17 }, // Inst #2512 = SUB16ri | |
| { 2513, 3, 1, 0, 0, "SUB16ri8", 0, 0x106004055ULL, NULL, ImplicitList1, OperandInfo17 }, // Inst #2513 = SUB16ri8 | |
| { 2514, 7, 1, 0, 0, "SUB16rm", 0|(1<<MCID::MayLoad), 0x56000046ULL, NULL, ImplicitList1, OperandInfo18 }, // Inst #2514 = SUB16rm | |
| { 2515, 3, 1, 0, 0, "SUB16rr", 0, 0x52000043ULL, NULL, ImplicitList1, OperandInfo19 }, // Inst #2515 = SUB16rr | |
| { 2516, 3, 1, 0, 0, "SUB16rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x56000045ULL, NULL, ImplicitList1, OperandInfo19 }, // Inst #2516 = SUB16rr_REV | |
| { 2517, 1, 0, 0, 0, "SUB32i32", 0|(1<<MCID::UnmodeledSideEffects), 0x5a014001ULL, ImplicitList3, ImplicitList1, OperandInfo2 }, // Inst #2517 = SUB32i32 | |
| { 2518, 6, 0, 0, 0, "SUB32mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10201401dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2518 = SUB32mi | |
| { 2519, 6, 0, 0, 0, "SUB32mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10600401dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2519 = SUB32mi8 | |
| { 2520, 6, 0, 0, 0, "SUB32mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x52000004ULL, NULL, ImplicitList1, OperandInfo20 }, // Inst #2520 = SUB32mr | |
| { 2521, 3, 1, 0, 0, "SUB32ri", 0, 0x102014015ULL, NULL, ImplicitList1, OperandInfo21 }, // Inst #2521 = SUB32ri | |
| { 2522, 3, 1, 0, 0, "SUB32ri8", 0, 0x106004015ULL, NULL, ImplicitList1, OperandInfo21 }, // Inst #2522 = SUB32ri8 | |
| { 2523, 7, 1, 0, 0, "SUB32rm", 0|(1<<MCID::MayLoad), 0x56000006ULL, NULL, ImplicitList1, OperandInfo22 }, // Inst #2523 = SUB32rm | |
| { 2524, 3, 1, 0, 0, "SUB32rr", 0, 0x52000003ULL, NULL, ImplicitList1, OperandInfo23 }, // Inst #2524 = SUB32rr | |
| { 2525, 3, 1, 0, 0, "SUB32rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x56000005ULL, NULL, ImplicitList1, OperandInfo23 }, // Inst #2525 = SUB32rr_REV | |
| { 2526, 1, 0, 0, 0, "SUB64i32", 0|(1<<MCID::UnmodeledSideEffects), 0x5a016001ULL, ImplicitList4, ImplicitList1, OperandInfo2 }, // Inst #2526 = SUB64i32 | |
| { 2527, 6, 0, 0, 0, "SUB64mi32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10201601dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2527 = SUB64mi32 | |
| { 2528, 6, 0, 0, 0, "SUB64mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10600601dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2528 = SUB64mi8 | |
| { 2529, 6, 0, 0, 0, "SUB64mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x52002004ULL, NULL, ImplicitList1, OperandInfo24 }, // Inst #2529 = SUB64mr | |
| { 2530, 3, 1, 0, 0, "SUB64ri32", 0, 0x102016015ULL, NULL, ImplicitList1, OperandInfo25 }, // Inst #2530 = SUB64ri32 | |
| { 2531, 3, 1, 0, 0, "SUB64ri8", 0, 0x106006015ULL, NULL, ImplicitList1, OperandInfo25 }, // Inst #2531 = SUB64ri8 | |
| { 2532, 7, 1, 0, 0, "SUB64rm", 0|(1<<MCID::MayLoad), 0x56002006ULL, NULL, ImplicitList1, OperandInfo26 }, // Inst #2532 = SUB64rm | |
| { 2533, 3, 1, 0, 0, "SUB64rr", 0, 0x52002003ULL, NULL, ImplicitList1, OperandInfo27 }, // Inst #2533 = SUB64rr | |
| { 2534, 3, 1, 0, 0, "SUB64rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x56002005ULL, NULL, ImplicitList1, OperandInfo27 }, // Inst #2534 = SUB64rr_REV | |
| { 2535, 1, 0, 0, 0, "SUB8i8", 0|(1<<MCID::UnmodeledSideEffects), 0x58004001ULL, ImplicitList5, ImplicitList1, OperandInfo2 }, // Inst #2535 = SUB8i8 | |
| { 2536, 6, 0, 0, 0, "SUB8mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10000401dULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2536 = SUB8mi | |
| { 2537, 6, 0, 0, 0, "SUB8mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x50000004ULL, NULL, ImplicitList1, OperandInfo28 }, // Inst #2537 = SUB8mr | |
| { 2538, 3, 1, 0, 0, "SUB8ri", 0, 0x100004015ULL, NULL, ImplicitList1, OperandInfo29 }, // Inst #2538 = SUB8ri | |
| { 2539, 7, 1, 0, 0, "SUB8rm", 0|(1<<MCID::MayLoad), 0x54000006ULL, NULL, ImplicitList1, OperandInfo30 }, // Inst #2539 = SUB8rm | |
| { 2540, 3, 1, 0, 0, "SUB8rr", 0, 0x50000003ULL, NULL, ImplicitList1, OperandInfo31 }, // Inst #2540 = SUB8rr | |
| { 2541, 3, 1, 0, 0, "SUB8rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x54000005ULL, NULL, ImplicitList1, OperandInfo31 }, // Inst #2541 = SUB8rr_REV | |
| { 2542, 7, 1, 0, 0, "SUBPDrm", 0|(1<<MCID::MayLoad), 0xb9000146ULL, NULL, NULL, OperandInfo32 }, // Inst #2542 = SUBPDrm | |
| { 2543, 3, 1, 0, 0, "SUBPDrr", 0, 0xb9000145ULL, NULL, NULL, OperandInfo33 }, // Inst #2543 = SUBPDrr | |
| { 2544, 7, 1, 0, 0, "SUBPSrm", 0|(1<<MCID::MayLoad), 0xb8800106ULL, NULL, NULL, OperandInfo32 }, // Inst #2544 = SUBPSrm | |
| { 2545, 3, 1, 0, 0, "SUBPSrr", 0, 0xb8800105ULL, NULL, NULL, OperandInfo33 }, // Inst #2545 = SUBPSrr | |
| { 2546, 5, 0, 0, 0, "SUBR_F32m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b000001dULL, NULL, NULL, OperandInfo38 }, // Inst #2546 = SUBR_F32m | |
| { 2547, 5, 0, 0, 0, "SUBR_F64m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b800001dULL, NULL, NULL, OperandInfo38 }, // Inst #2547 = SUBR_F64m | |
| { 2548, 5, 0, 0, 0, "SUBR_FI16m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1bc00001dULL, NULL, NULL, OperandInfo38 }, // Inst #2548 = SUBR_FI16m | |
| { 2549, 5, 0, 0, 0, "SUBR_FI32m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b400001dULL, NULL, NULL, OperandInfo38 }, // Inst #2549 = SUBR_FI32m | |
| { 2550, 1, 0, 0, 0, "SUBR_FPrST0", 0|(1<<MCID::UnmodeledSideEffects), 0x1c0000902ULL, NULL, NULL, OperandInfo39 }, // Inst #2550 = SUBR_FPrST0 | |
| { 2551, 1, 0, 0, 0, "SUBR_FST0r", 0|(1<<MCID::UnmodeledSideEffects), 0x1d0000302ULL, NULL, NULL, OperandInfo39 }, // Inst #2551 = SUBR_FST0r | |
| { 2552, 7, 1, 0, 0, "SUBR_Fp32m", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo41 }, // Inst #2552 = SUBR_Fp32m | |
| { 2553, 7, 1, 0, 0, "SUBR_Fp64m", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #2553 = SUBR_Fp64m | |
| { 2554, 7, 1, 0, 0, "SUBR_Fp64m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #2554 = SUBR_Fp64m32 | |
| { 2555, 7, 1, 0, 0, "SUBR_Fp80m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #2555 = SUBR_Fp80m32 | |
| { 2556, 7, 1, 0, 0, "SUBR_Fp80m64", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #2556 = SUBR_Fp80m64 | |
| { 2557, 7, 1, 0, 0, "SUBR_FpI16m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo41 }, // Inst #2557 = SUBR_FpI16m32 | |
| { 2558, 7, 1, 0, 0, "SUBR_FpI16m64", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #2558 = SUBR_FpI16m64 | |
| { 2559, 7, 1, 0, 0, "SUBR_FpI16m80", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #2559 = SUBR_FpI16m80 | |
| { 2560, 7, 1, 0, 0, "SUBR_FpI32m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo41 }, // Inst #2560 = SUBR_FpI32m32 | |
| { 2561, 7, 1, 0, 0, "SUBR_FpI32m64", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #2561 = SUBR_FpI32m64 | |
| { 2562, 7, 1, 0, 0, "SUBR_FpI32m80", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #2562 = SUBR_FpI32m80 | |
| { 2563, 1, 0, 0, 0, "SUBR_FrST0", 0|(1<<MCID::UnmodeledSideEffects), 0x1c0000702ULL, NULL, NULL, OperandInfo39 }, // Inst #2563 = SUBR_FrST0 | |
| { 2564, 7, 1, 0, 0, "SUBSDrm", 0|(1<<MCID::MayLoad), 0xb8000b06ULL, NULL, NULL, OperandInfo34 }, // Inst #2564 = SUBSDrm | |
| { 2565, 7, 1, 0, 0, "SUBSDrm_Int", 0|(1<<MCID::MayLoad), 0xb8000b06ULL, NULL, NULL, OperandInfo32 }, // Inst #2565 = SUBSDrm_Int | |
| { 2566, 3, 1, 0, 0, "SUBSDrr", 0, 0xb8000b05ULL, NULL, NULL, OperandInfo35 }, // Inst #2566 = SUBSDrr | |
| { 2567, 3, 1, 0, 0, "SUBSDrr_Int", 0, 0xb8000b05ULL, NULL, NULL, OperandInfo33 }, // Inst #2567 = SUBSDrr_Int | |
| { 2568, 7, 1, 0, 0, "SUBSSrm", 0|(1<<MCID::MayLoad), 0xb8000c06ULL, NULL, NULL, OperandInfo36 }, // Inst #2568 = SUBSSrm | |
| { 2569, 7, 1, 0, 0, "SUBSSrm_Int", 0|(1<<MCID::MayLoad), 0xb8000c06ULL, NULL, NULL, OperandInfo32 }, // Inst #2569 = SUBSSrm_Int | |
| { 2570, 3, 1, 0, 0, "SUBSSrr", 0, 0xb8000c05ULL, NULL, NULL, OperandInfo37 }, // Inst #2570 = SUBSSrr | |
| { 2571, 3, 1, 0, 0, "SUBSSrr_Int", 0, 0xb8000c05ULL, NULL, NULL, OperandInfo33 }, // Inst #2571 = SUBSSrr_Int | |
| { 2572, 5, 0, 0, 0, "SUB_F32m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b000001cULL, NULL, NULL, OperandInfo38 }, // Inst #2572 = SUB_F32m | |
| { 2573, 5, 0, 0, 0, "SUB_F64m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b800001cULL, NULL, NULL, OperandInfo38 }, // Inst #2573 = SUB_F64m | |
| { 2574, 5, 0, 0, 0, "SUB_FI16m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1bc00001cULL, NULL, NULL, OperandInfo38 }, // Inst #2574 = SUB_FI16m | |
| { 2575, 5, 0, 0, 0, "SUB_FI32m", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x1b400001cULL, NULL, NULL, OperandInfo38 }, // Inst #2575 = SUB_FI32m | |
| { 2576, 1, 0, 0, 0, "SUB_FPrST0", 0|(1<<MCID::UnmodeledSideEffects), 0x1d0000902ULL, NULL, NULL, OperandInfo39 }, // Inst #2576 = SUB_FPrST0 | |
| { 2577, 1, 0, 0, 0, "SUB_FST0r", 0|(1<<MCID::UnmodeledSideEffects), 0x1c0000302ULL, NULL, NULL, OperandInfo39 }, // Inst #2577 = SUB_FST0r | |
| { 2578, 3, 1, 0, 0, "SUB_Fp32", 0, 0x80000ULL, NULL, NULL, OperandInfo40 }, // Inst #2578 = SUB_Fp32 | |
| { 2579, 7, 1, 0, 0, "SUB_Fp32m", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo41 }, // Inst #2579 = SUB_Fp32m | |
| { 2580, 3, 1, 0, 0, "SUB_Fp64", 0, 0x80000ULL, NULL, NULL, OperandInfo42 }, // Inst #2580 = SUB_Fp64 | |
| { 2581, 7, 1, 0, 0, "SUB_Fp64m", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #2581 = SUB_Fp64m | |
| { 2582, 7, 1, 0, 0, "SUB_Fp64m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #2582 = SUB_Fp64m32 | |
| { 2583, 3, 1, 0, 0, "SUB_Fp80", 0, 0x80000ULL, NULL, NULL, OperandInfo44 }, // Inst #2583 = SUB_Fp80 | |
| { 2584, 7, 1, 0, 0, "SUB_Fp80m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #2584 = SUB_Fp80m32 | |
| { 2585, 7, 1, 0, 0, "SUB_Fp80m64", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #2585 = SUB_Fp80m64 | |
| { 2586, 7, 1, 0, 0, "SUB_FpI16m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo41 }, // Inst #2586 = SUB_FpI16m32 | |
| { 2587, 7, 1, 0, 0, "SUB_FpI16m64", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #2587 = SUB_FpI16m64 | |
| { 2588, 7, 1, 0, 0, "SUB_FpI16m80", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #2588 = SUB_FpI16m80 | |
| { 2589, 7, 1, 0, 0, "SUB_FpI32m32", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo41 }, // Inst #2589 = SUB_FpI32m32 | |
| { 2590, 7, 1, 0, 0, "SUB_FpI32m64", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo43 }, // Inst #2590 = SUB_FpI32m64 | |
| { 2591, 7, 1, 0, 0, "SUB_FpI32m80", 0|(1<<MCID::MayLoad), 0x60000ULL, NULL, NULL, OperandInfo45 }, // Inst #2591 = SUB_FpI32m80 | |
| { 2592, 1, 0, 0, 0, "SUB_FrST0", 0|(1<<MCID::UnmodeledSideEffects), 0x1d0000702ULL, NULL, NULL, OperandInfo39 }, // Inst #2592 = SUB_FrST0 | |
| { 2593, 0, 0, 0, 0, "SWAPGS", 0|(1<<MCID::UnmodeledSideEffects), 0x2000129ULL, NULL, NULL, 0 }, // Inst #2593 = SWAPGS | |
| { 2594, 0, 0, 0, 0, "SYSCALL", 0|(1<<MCID::UnmodeledSideEffects), 0xa000101ULL, NULL, NULL, 0 }, // Inst #2594 = SYSCALL | |
| { 2595, 0, 0, 0, 0, "SYSENTER", 0|(1<<MCID::UnmodeledSideEffects), 0x68000101ULL, NULL, NULL, 0 }, // Inst #2595 = SYSENTER | |
| { 2596, 0, 0, 0, 0, "SYSEXIT", 0|(1<<MCID::UnmodeledSideEffects), 0x6a000101ULL, NULL, NULL, 0 }, // Inst #2596 = SYSEXIT | |
| { 2597, 0, 0, 0, 0, "SYSEXIT64", 0|(1<<MCID::UnmodeledSideEffects), 0x6a002101ULL, NULL, NULL, 0 }, // Inst #2597 = SYSEXIT64 | |
| { 2598, 0, 0, 0, 0, "SYSRETL", 0|(1<<MCID::UnmodeledSideEffects), 0xe000101ULL, NULL, NULL, 0 }, // Inst #2598 = SYSRETL | |
| { 2599, 0, 0, 0, 0, "SYSRETQ", 0|(1<<MCID::UnmodeledSideEffects), 0xe002101ULL, NULL, NULL, 0 }, // Inst #2599 = SYSRETQ | |
| { 2600, 1, 0, 0, 0, "TAILJMPd", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Call)|(1<<MCID::Terminator)|(1<<MCID::Variadic)|(1<<MCID::UnmodeledSideEffects), 0x1d2018001ULL, ImplicitList6, ImplicitList13, OperandInfo73 }, // Inst #2600 = TAILJMPd | |
| { 2601, 1, 0, 0, 0, "TAILJMPd64", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Call)|(1<<MCID::Terminator)|(1<<MCID::UsesCustomInserter)|(1<<MCID::Variadic)|(1<<MCID::UnmodeledSideEffects), 0x1d2018001ULL, ImplicitList8, ImplicitList66, OperandInfo73 }, // Inst #2601 = TAILJMPd64 | |
| { 2602, 5, 0, 0, 0, "TAILJMPm", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Call)|(1<<MCID::MayLoad)|(1<<MCID::Terminator)|(1<<MCID::Variadic)|(1<<MCID::UnmodeledSideEffects), 0x1fe00001cULL, ImplicitList6, ImplicitList13, OperandInfo210 }, // Inst #2602 = TAILJMPm | |
| { 2603, 5, 0, 0, 0, "TAILJMPm64", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Call)|(1<<MCID::MayLoad)|(1<<MCID::Terminator)|(1<<MCID::UsesCustomInserter)|(1<<MCID::Variadic)|(1<<MCID::UnmodeledSideEffects), 0x1fe00001cULL, ImplicitList8, ImplicitList66, OperandInfo211 }, // Inst #2603 = TAILJMPm64 | |
| { 2604, 1, 0, 0, 0, "TAILJMPr", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Call)|(1<<MCID::Terminator)|(1<<MCID::Variadic)|(1<<MCID::UnmodeledSideEffects), 0x1fe000014ULL, ImplicitList6, ImplicitList13, OperandInfo212 }, // Inst #2604 = TAILJMPr | |
| { 2605, 1, 0, 0, 0, "TAILJMPr64", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Call)|(1<<MCID::Terminator)|(1<<MCID::UsesCustomInserter)|(1<<MCID::Variadic)|(1<<MCID::UnmodeledSideEffects), 0x1fe000014ULL, ImplicitList8, ImplicitList66, OperandInfo213 }, // Inst #2605 = TAILJMPr64 | |
| { 2606, 2, 0, 0, 0, "TCRETURNdi", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Call)|(1<<MCID::Terminator)|(1<<MCID::Variadic)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList6, ImplicitList13, OperandInfo214 }, // Inst #2606 = TCRETURNdi | |
| { 2607, 2, 0, 0, 0, "TCRETURNdi64", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Call)|(1<<MCID::Terminator)|(1<<MCID::UsesCustomInserter)|(1<<MCID::Variadic)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList8, ImplicitList66, OperandInfo214 }, // Inst #2607 = TCRETURNdi64 | |
| { 2608, 6, 0, 0, 0, "TCRETURNmi", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Call)|(1<<MCID::MayLoad)|(1<<MCID::Terminator)|(1<<MCID::Variadic)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList6, ImplicitList13, OperandInfo215 }, // Inst #2608 = TCRETURNmi | |
| { 2609, 6, 0, 0, 0, "TCRETURNmi64", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Call)|(1<<MCID::MayLoad)|(1<<MCID::Terminator)|(1<<MCID::UsesCustomInserter)|(1<<MCID::Variadic)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList8, ImplicitList66, OperandInfo216 }, // Inst #2609 = TCRETURNmi64 | |
| { 2610, 2, 0, 0, 0, "TCRETURNri", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Call)|(1<<MCID::Terminator)|(1<<MCID::Variadic)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList6, ImplicitList13, OperandInfo217 }, // Inst #2610 = TCRETURNri | |
| { 2611, 2, 0, 0, 0, "TCRETURNri64", 0|(1<<MCID::Return)|(1<<MCID::Barrier)|(1<<MCID::Call)|(1<<MCID::Terminator)|(1<<MCID::UsesCustomInserter)|(1<<MCID::Variadic)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList8, ImplicitList66, OperandInfo218 }, // Inst #2611 = TCRETURNri64 | |
| { 2612, 1, 0, 0, 0, "TEST16i16", 0|(1<<MCID::UnmodeledSideEffects), 0x15200c041ULL, ImplicitList2, ImplicitList1, OperandInfo2 }, // Inst #2612 = TEST16i16 | |
| { 2613, 6, 0, 0, 0, "TEST16mi", 0|(1<<MCID::MayLoad), 0x1ee00c058ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2613 = TEST16mi | |
| { 2614, 2, 0, 0, 0, "TEST16ri", 0, 0x1ee00c050ULL, NULL, ImplicitList1, OperandInfo69 }, // Inst #2614 = TEST16ri | |
| { 2615, 6, 0, 0, 0, "TEST16rm", 0|(1<<MCID::MayLoad), 0x10a000046ULL, NULL, ImplicitList1, OperandInfo11 }, // Inst #2615 = TEST16rm | |
| { 2616, 2, 0, 0, 0, "TEST16rr", 0|(1<<MCID::Commutable), 0x10a000045ULL, NULL, ImplicitList1, OperandInfo55 }, // Inst #2616 = TEST16rr | |
| { 2617, 1, 0, 0, 0, "TEST32i32", 0|(1<<MCID::UnmodeledSideEffects), 0x152014001ULL, ImplicitList3, ImplicitList1, OperandInfo2 }, // Inst #2617 = TEST32i32 | |
| { 2618, 6, 0, 0, 0, "TEST32mi", 0|(1<<MCID::MayLoad), 0x1ee014018ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2618 = TEST32mi | |
| { 2619, 2, 0, 0, 0, "TEST32ri", 0, 0x1ee014010ULL, NULL, ImplicitList1, OperandInfo70 }, // Inst #2619 = TEST32ri | |
| { 2620, 6, 0, 0, 0, "TEST32rm", 0|(1<<MCID::MayLoad), 0x10a000006ULL, NULL, ImplicitList1, OperandInfo12 }, // Inst #2620 = TEST32rm | |
| { 2621, 2, 0, 0, 0, "TEST32rr", 0|(1<<MCID::Commutable), 0x10a000005ULL, NULL, ImplicitList1, OperandInfo65 }, // Inst #2621 = TEST32rr | |
| { 2622, 1, 0, 0, 0, "TEST64i32", 0|(1<<MCID::UnmodeledSideEffects), 0x152016001ULL, ImplicitList4, ImplicitList1, OperandInfo2 }, // Inst #2622 = TEST64i32 | |
| { 2623, 6, 0, 0, 0, "TEST64mi32", 0|(1<<MCID::MayLoad), 0x1ee016018ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2623 = TEST64mi32 | |
| { 2624, 2, 0, 0, 0, "TEST64ri32", 0, 0x1ee016010ULL, NULL, ImplicitList1, OperandInfo71 }, // Inst #2624 = TEST64ri32 | |
| { 2625, 6, 0, 0, 0, "TEST64rm", 0|(1<<MCID::MayLoad), 0x10a002006ULL, NULL, ImplicitList1, OperandInfo13 }, // Inst #2625 = TEST64rm | |
| { 2626, 2, 0, 0, 0, "TEST64rr", 0|(1<<MCID::Commutable), 0x10a002005ULL, NULL, ImplicitList1, OperandInfo66 }, // Inst #2626 = TEST64rr | |
| { 2627, 1, 0, 0, 0, "TEST8i8", 0|(1<<MCID::UnmodeledSideEffects), 0x150004001ULL, ImplicitList5, ImplicitList1, OperandInfo2 }, // Inst #2627 = TEST8i8 | |
| { 2628, 6, 0, 0, 0, "TEST8mi", 0|(1<<MCID::MayLoad), 0x1ec004018ULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #2628 = TEST8mi | |
| { 2629, 2, 0, 0, 0, "TEST8ri", 0, 0x1ec004010ULL, NULL, ImplicitList1, OperandInfo88 }, // Inst #2629 = TEST8ri | |
| { 2630, 2, 0, 0, 0, "TEST8ri_NOREX", 0|(1<<MCID::Pseudo)|(1<<MCID::UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo219 }, // Inst #2630 = TEST8ri_NOREX | |
| { 2631, 6, 0, 0, 0, "TEST8rm", 0|(1<<MCID::MayLoad), 0x108000006ULL, NULL, ImplicitList1, OperandInfo14 }, // Inst #2631 = TEST8rm | |
| { 2632, 2, 0, 0, 0, "TEST8rr", 0|(1<<MCID::Commutable), 0x108000005ULL, NULL, ImplicitList1, OperandInfo89 }, // Inst #2632 = TEST8rr | |
| { 2633, 5, 0, 0, 0, "TLSCall_32", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList6, ImplicitList67, OperandInfo38 }, // Inst #2633 = TLSCall_32 | |
| { 2634, 5, 0, 0, 0, "TLSCall_64", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList68, ImplicitList30, OperandInfo38 }, // Inst #2634 = TLSCall_64 | |
| { 2635, 5, 0, 0, 0, "TLS_addr32", 0, 0x0ULL, ImplicitList6, ImplicitList13, OperandInfo38 }, // Inst #2635 = TLS_addr32 | |
| { 2636, 5, 0, 0, 0, "TLS_addr64", 0, 0x0ULL, ImplicitList8, ImplicitList14, OperandInfo38 }, // Inst #2636 = TLS_addr64 | |
| { 2637, 0, 0, 0, 0, "TRAP", 0|(1<<MCID::Barrier)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0x16000101ULL, NULL, NULL, 0 }, // Inst #2637 = TRAP | |
| { 2638, 0, 0, 0, 0, "TST_F", 0|(1<<MCID::UnmodeledSideEffects), 0x1c8000401ULL, NULL, NULL, 0 }, // Inst #2638 = TST_F | |
| { 2639, 1, 0, 0, 0, "TST_Fp32", 0, 0x40000ULL, NULL, NULL, OperandInfo142 }, // Inst #2639 = TST_Fp32 | |
| { 2640, 1, 0, 0, 0, "TST_Fp64", 0, 0x40000ULL, NULL, NULL, OperandInfo143 }, // Inst #2640 = TST_Fp64 | |
| { 2641, 1, 0, 0, 0, "TST_Fp80", 0, 0x40000ULL, NULL, NULL, OperandInfo120 }, // Inst #2641 = TST_Fp80 | |
| { 2642, 6, 1, 0, 0, "TZCNT16rm", 0|(1<<MCID::MayLoad), 0x178000c46ULL, NULL, ImplicitList1, OperandInfo11 }, // Inst #2642 = TZCNT16rm | |
| { 2643, 2, 1, 0, 0, "TZCNT16rr", 0, 0x178000c45ULL, NULL, ImplicitList1, OperandInfo55 }, // Inst #2643 = TZCNT16rr | |
| { 2644, 6, 1, 0, 0, "TZCNT32rm", 0|(1<<MCID::MayLoad), 0x178000c06ULL, NULL, ImplicitList1, OperandInfo12 }, // Inst #2644 = TZCNT32rm | |
| { 2645, 2, 1, 0, 0, "TZCNT32rr", 0, 0x178000c05ULL, NULL, ImplicitList1, OperandInfo65 }, // Inst #2645 = TZCNT32rr | |
| { 2646, 6, 1, 0, 0, "TZCNT64rm", 0|(1<<MCID::MayLoad), 0x178002c06ULL, NULL, ImplicitList1, OperandInfo13 }, // Inst #2646 = TZCNT64rm | |
| { 2647, 2, 1, 0, 0, "TZCNT64rr", 0, 0x178002c05ULL, NULL, ImplicitList1, OperandInfo66 }, // Inst #2647 = TZCNT64rr | |
| { 2648, 6, 0, 0, 0, "UCOMISDrm", 0|(1<<MCID::MayLoad), 0x5d000146ULL, NULL, ImplicitList1, OperandInfo101 }, // Inst #2648 = UCOMISDrm | |
| { 2649, 2, 0, 0, 0, "UCOMISDrr", 0, 0x5d000145ULL, NULL, ImplicitList1, OperandInfo123 }, // Inst #2649 = UCOMISDrr | |
| { 2650, 6, 0, 0, 0, "UCOMISSrm", 0|(1<<MCID::MayLoad), 0x5c800106ULL, NULL, ImplicitList1, OperandInfo99 }, // Inst #2650 = UCOMISSrm | |
| { 2651, 2, 0, 0, 0, "UCOMISSrr", 0, 0x5c800105ULL, NULL, ImplicitList1, OperandInfo124 }, // Inst #2651 = UCOMISSrr | |
| { 2652, 1, 0, 0, 0, "UCOM_FIPr", 0|(1<<MCID::UnmodeledSideEffects), 0x1d0000a02ULL, ImplicitList69, ImplicitList1, OperandInfo39 }, // Inst #2652 = UCOM_FIPr | |
| { 2653, 1, 0, 0, 0, "UCOM_FIr", 0|(1<<MCID::UnmodeledSideEffects), 0x1d0000602ULL, ImplicitList69, ImplicitList1, OperandInfo39 }, // Inst #2653 = UCOM_FIr | |
| { 2654, 0, 0, 0, 0, "UCOM_FPPr", 0|(1<<MCID::UnmodeledSideEffects), 0x1d2000501ULL, ImplicitList69, ImplicitList1, 0 }, // Inst #2654 = UCOM_FPPr | |
| { 2655, 1, 0, 0, 0, "UCOM_FPr", 0|(1<<MCID::UnmodeledSideEffects), 0x1d0000802ULL, ImplicitList69, ImplicitList1, OperandInfo39 }, // Inst #2655 = UCOM_FPr | |
| { 2656, 2, 0, 0, 0, "UCOM_FpIr32", 0, 0xa0000ULL, NULL, ImplicitList1, OperandInfo8 }, // Inst #2656 = UCOM_FpIr32 | |
| { 2657, 2, 0, 0, 0, "UCOM_FpIr64", 0, 0xa0000ULL, NULL, ImplicitList1, OperandInfo9 }, // Inst #2657 = UCOM_FpIr64 | |
| { 2658, 2, 0, 0, 0, "UCOM_FpIr80", 0, 0xa0000ULL, NULL, ImplicitList1, OperandInfo10 }, // Inst #2658 = UCOM_FpIr80 | |
| { 2659, 2, 0, 0, 0, "UCOM_Fpr32", 0|(1<<MCID::UnmodeledSideEffects), 0xa0000ULL, NULL, ImplicitList1, OperandInfo8 }, // Inst #2659 = UCOM_Fpr32 | |
| { 2660, 2, 0, 0, 0, "UCOM_Fpr64", 0|(1<<MCID::UnmodeledSideEffects), 0xa0000ULL, NULL, ImplicitList1, OperandInfo9 }, // Inst #2660 = UCOM_Fpr64 | |
| { 2661, 2, 0, 0, 0, "UCOM_Fpr80", 0|(1<<MCID::UnmodeledSideEffects), 0xa0000ULL, NULL, ImplicitList1, OperandInfo10 }, // Inst #2661 = UCOM_Fpr80 | |
| { 2662, 1, 0, 0, 0, "UCOM_Fr", 0|(1<<MCID::UnmodeledSideEffects), 0x1c0000802ULL, ImplicitList69, ImplicitList1, OperandInfo39 }, // Inst #2662 = UCOM_Fr | |
| { 2663, 0, 0, 0, 0, "UD2B", 0|(1<<MCID::Barrier)|(1<<MCID::Terminator)|(1<<MCID::UnmodeledSideEffects), 0x172000101ULL, NULL, NULL, 0 }, // Inst #2663 = UD2B | |
| { 2664, 7, 1, 0, 0, "UNPCKHPDrm", 0|(1<<MCID::MayLoad), 0x2b000146ULL, NULL, NULL, OperandInfo32 }, // Inst #2664 = UNPCKHPDrm | |
| { 2665, 3, 1, 0, 0, "UNPCKHPDrr", 0, 0x2b000145ULL, NULL, NULL, OperandInfo33 }, // Inst #2665 = UNPCKHPDrr | |
| { 2666, 7, 1, 0, 0, "UNPCKHPSrm", 0|(1<<MCID::MayLoad), 0x2a800106ULL, NULL, NULL, OperandInfo32 }, // Inst #2666 = UNPCKHPSrm | |
| { 2667, 3, 1, 0, 0, "UNPCKHPSrr", 0, 0x2a800105ULL, NULL, NULL, OperandInfo33 }, // Inst #2667 = UNPCKHPSrr | |
| { 2668, 7, 1, 0, 0, "UNPCKLPDrm", 0|(1<<MCID::MayLoad), 0x29000146ULL, NULL, NULL, OperandInfo32 }, // Inst #2668 = UNPCKLPDrm | |
| { 2669, 3, 1, 0, 0, "UNPCKLPDrr", 0, 0x29000145ULL, NULL, NULL, OperandInfo33 }, // Inst #2669 = UNPCKLPDrr | |
| { 2670, 7, 1, 0, 0, "UNPCKLPSrm", 0|(1<<MCID::MayLoad), 0x28800106ULL, NULL, NULL, OperandInfo32 }, // Inst #2670 = UNPCKLPSrm | |
| { 2671, 3, 1, 0, 0, "UNPCKLPSrr", 0, 0x28800105ULL, NULL, NULL, OperandInfo33 }, // Inst #2671 = UNPCKLPSrr | |
| { 2672, 9, 1, 0, 0, "VAARG_64", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo220 }, // Inst #2672 = VAARG_64 | |
| { 2673, 7, 1, 0, 0, "VADDPDYrm", 0|(1<<MCID::MayLoad), 0xab1000146ULL, NULL, NULL, OperandInfo221 }, // Inst #2673 = VADDPDYrm | |
| { 2674, 3, 1, 0, 0, "VADDPDYrr", 0|(1<<MCID::Commutable), 0xab1000145ULL, NULL, NULL, OperandInfo222 }, // Inst #2674 = VADDPDYrr | |
| { 2675, 7, 1, 0, 0, "VADDPDrm", 0|(1<<MCID::MayLoad), 0xab1000146ULL, NULL, NULL, OperandInfo137 }, // Inst #2675 = VADDPDrm | |
| { 2676, 3, 1, 0, 0, "VADDPDrr", 0|(1<<MCID::Commutable), 0xab1000145ULL, NULL, NULL, OperandInfo138 }, // Inst #2676 = VADDPDrr | |
| { 2677, 7, 1, 0, 0, "VADDPSYrm", 0|(1<<MCID::MayLoad), 0xab0800106ULL, NULL, NULL, OperandInfo221 }, // Inst #2677 = VADDPSYrm | |
| { 2678, 3, 1, 0, 0, "VADDPSYrr", 0|(1<<MCID::Commutable), 0xab0800105ULL, NULL, NULL, OperandInfo222 }, // Inst #2678 = VADDPSYrr | |
| { 2679, 7, 1, 0, 0, "VADDPSrm", 0|(1<<MCID::MayLoad), 0xab0800106ULL, NULL, NULL, OperandInfo137 }, // Inst #2679 = VADDPSrm | |
| { 2680, 3, 1, 0, 0, "VADDPSrr", 0|(1<<MCID::Commutable), 0xab0800105ULL, NULL, NULL, OperandInfo138 }, // Inst #2680 = VADDPSrr | |
| { 2681, 7, 1, 0, 0, "VADDSDrm", 0|(1<<MCID::MayLoad), 0x4ab0000b06ULL, NULL, NULL, OperandInfo223 }, // Inst #2681 = VADDSDrm | |
| { 2682, 7, 1, 0, 0, "VADDSDrm_Int", 0|(1<<MCID::MayLoad), 0x4ab0000b06ULL, NULL, NULL, OperandInfo137 }, // Inst #2682 = VADDSDrm_Int | |
| { 2683, 3, 1, 0, 0, "VADDSDrr", 0|(1<<MCID::Commutable), 0x4ab0000b05ULL, NULL, NULL, OperandInfo224 }, // Inst #2683 = VADDSDrr | |
| { 2684, 3, 1, 0, 0, "VADDSDrr_Int", 0, 0x4ab0000b05ULL, NULL, NULL, OperandInfo138 }, // Inst #2684 = VADDSDrr_Int | |
| { 2685, 7, 1, 0, 0, "VADDSSrm", 0|(1<<MCID::MayLoad), 0x4ab0000c06ULL, NULL, NULL, OperandInfo225 }, // Inst #2685 = VADDSSrm | |
| { 2686, 7, 1, 0, 0, "VADDSSrm_Int", 0|(1<<MCID::MayLoad), 0x4ab0000c06ULL, NULL, NULL, OperandInfo137 }, // Inst #2686 = VADDSSrm_Int | |
| { 2687, 3, 1, 0, 0, "VADDSSrr", 0|(1<<MCID::Commutable), 0x4ab0000c05ULL, NULL, NULL, OperandInfo226 }, // Inst #2687 = VADDSSrr | |
| { 2688, 3, 1, 0, 0, "VADDSSrr_Int", 0, 0x4ab0000c05ULL, NULL, NULL, OperandInfo138 }, // Inst #2688 = VADDSSrr_Int | |
| { 2689, 7, 1, 0, 0, "VADDSUBPDYrm", 0|(1<<MCID::MayLoad), 0xba1000146ULL, NULL, NULL, OperandInfo221 }, // Inst #2689 = VADDSUBPDYrm | |
| { 2690, 3, 1, 0, 0, "VADDSUBPDYrr", 0, 0xba1000145ULL, NULL, NULL, OperandInfo222 }, // Inst #2690 = VADDSUBPDYrr | |
| { 2691, 7, 1, 0, 0, "VADDSUBPDrm", 0|(1<<MCID::MayLoad), 0xba1000146ULL, NULL, NULL, OperandInfo137 }, // Inst #2691 = VADDSUBPDrm | |
| { 2692, 3, 1, 0, 0, "VADDSUBPDrr", 0, 0xba1000145ULL, NULL, NULL, OperandInfo138 }, // Inst #2692 = VADDSUBPDrr | |
| { 2693, 7, 1, 0, 0, "VADDSUBPSYrm", 0|(1<<MCID::MayLoad), 0xba1000b06ULL, NULL, NULL, OperandInfo221 }, // Inst #2693 = VADDSUBPSYrm | |
| { 2694, 3, 1, 0, 0, "VADDSUBPSYrr", 0, 0xba1000b05ULL, NULL, NULL, OperandInfo222 }, // Inst #2694 = VADDSUBPSYrr | |
| { 2695, 7, 1, 0, 0, "VADDSUBPSrm", 0|(1<<MCID::MayLoad), 0xba1000b06ULL, NULL, NULL, OperandInfo137 }, // Inst #2695 = VADDSUBPSrm | |
| { 2696, 3, 1, 0, 0, "VADDSUBPSrr", 0, 0xba1000b05ULL, NULL, NULL, OperandInfo138 }, // Inst #2696 = VADDSUBPSrr | |
| { 2697, 7, 1, 0, 0, "VAESDECLASTrm", 0|(1<<MCID::MayLoad), 0xbbf800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2697 = VAESDECLASTrm | |
| { 2698, 3, 1, 0, 0, "VAESDECLASTrr", 0, 0xbbf800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2698 = VAESDECLASTrr | |
| { 2699, 7, 1, 0, 0, "VAESDECrm", 0|(1<<MCID::MayLoad), 0xbbd800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2699 = VAESDECrm | |
| { 2700, 3, 1, 0, 0, "VAESDECrr", 0, 0xbbd800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2700 = VAESDECrr | |
| { 2701, 7, 1, 0, 0, "VAESENCLASTrm", 0|(1<<MCID::MayLoad), 0xbbb800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2701 = VAESENCLASTrm | |
| { 2702, 3, 1, 0, 0, "VAESENCLASTrr", 0, 0xbbb800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2702 = VAESENCLASTrr | |
| { 2703, 7, 1, 0, 0, "VAESENCrm", 0|(1<<MCID::MayLoad), 0xbb9800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2703 = VAESENCrm | |
| { 2704, 3, 1, 0, 0, "VAESENCrr", 0, 0xbb9800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2704 = VAESENCrr | |
| { 2705, 6, 1, 0, 0, "VAESIMCrm", 0|(1<<MCID::MayLoad), 0x3b7800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #2705 = VAESIMCrm | |
| { 2706, 2, 1, 0, 0, "VAESIMCrr", 0, 0x3b7800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #2706 = VAESIMCrr | |
| { 2707, 7, 1, 0, 0, "VAESKEYGENASSIST128rm", 0|(1<<MCID::MayLoad), 0x3bf804e46ULL, NULL, NULL, OperandInfo49 }, // Inst #2707 = VAESKEYGENASSIST128rm | |
| { 2708, 3, 1, 0, 0, "VAESKEYGENASSIST128rr", 0, 0x3bf804e45ULL, NULL, NULL, OperandInfo50 }, // Inst #2708 = VAESKEYGENASSIST128rr | |
| { 2709, 7, 1, 0, 0, "VANDNPDYrm", 0|(1<<MCID::MayLoad), 0xaab000146ULL, NULL, NULL, OperandInfo221 }, // Inst #2709 = VANDNPDYrm | |
| { 2710, 3, 1, 0, 0, "VANDNPDYrr", 0|(1<<MCID::Commutable), 0xaab000145ULL, NULL, NULL, OperandInfo222 }, // Inst #2710 = VANDNPDYrr | |
| { 2711, 7, 1, 0, 0, "VANDNPDrm", 0|(1<<MCID::MayLoad), 0xaab000146ULL, NULL, NULL, OperandInfo137 }, // Inst #2711 = VANDNPDrm | |
| { 2712, 3, 1, 0, 0, "VANDNPDrr", 0, 0xaab000145ULL, NULL, NULL, OperandInfo138 }, // Inst #2712 = VANDNPDrr | |
| { 2713, 7, 1, 0, 0, "VANDNPSYrm", 0|(1<<MCID::MayLoad), 0xaaa800106ULL, NULL, NULL, OperandInfo221 }, // Inst #2713 = VANDNPSYrm | |
| { 2714, 3, 1, 0, 0, "VANDNPSYrr", 0|(1<<MCID::Commutable), 0xaaa800105ULL, NULL, NULL, OperandInfo222 }, // Inst #2714 = VANDNPSYrr | |
| { 2715, 7, 1, 0, 0, "VANDNPSrm", 0|(1<<MCID::MayLoad), 0xaaa800106ULL, NULL, NULL, OperandInfo137 }, // Inst #2715 = VANDNPSrm | |
| { 2716, 3, 1, 0, 0, "VANDNPSrr", 0|(1<<MCID::UnmodeledSideEffects), 0xaaa800105ULL, NULL, NULL, OperandInfo138 }, // Inst #2716 = VANDNPSrr | |
| { 2717, 7, 1, 0, 0, "VANDPDYrm", 0|(1<<MCID::MayLoad), 0xaa9000146ULL, NULL, NULL, OperandInfo221 }, // Inst #2717 = VANDPDYrm | |
| { 2718, 3, 1, 0, 0, "VANDPDYrr", 0|(1<<MCID::Commutable), 0xaa9000145ULL, NULL, NULL, OperandInfo222 }, // Inst #2718 = VANDPDYrr | |
| { 2719, 7, 1, 0, 0, "VANDPDrm", 0|(1<<MCID::MayLoad), 0xaa9000146ULL, NULL, NULL, OperandInfo137 }, // Inst #2719 = VANDPDrm | |
| { 2720, 3, 1, 0, 0, "VANDPDrr", 0|(1<<MCID::Commutable), 0xaa9000145ULL, NULL, NULL, OperandInfo138 }, // Inst #2720 = VANDPDrr | |
| { 2721, 7, 1, 0, 0, "VANDPSYrm", 0|(1<<MCID::MayLoad), 0xaa8800106ULL, NULL, NULL, OperandInfo221 }, // Inst #2721 = VANDPSYrm | |
| { 2722, 3, 1, 0, 0, "VANDPSYrr", 0|(1<<MCID::Commutable), 0xaa8800105ULL, NULL, NULL, OperandInfo222 }, // Inst #2722 = VANDPSYrr | |
| { 2723, 7, 1, 0, 0, "VANDPSrm", 0|(1<<MCID::MayLoad), 0xaa8800106ULL, NULL, NULL, OperandInfo137 }, // Inst #2723 = VANDPSrm | |
| { 2724, 3, 1, 0, 0, "VANDPSrr", 0|(1<<MCID::Commutable)|(1<<MCID::UnmodeledSideEffects), 0xaa8800105ULL, NULL, NULL, OperandInfo138 }, // Inst #2724 = VANDPSrr | |
| { 2725, 3, 0, 0, 0, "VASTART_SAVE_XMM_REGS", 0|(1<<MCID::UsesCustomInserter)|(1<<MCID::Variadic), 0x0ULL, NULL, NULL, OperandInfo227 }, // Inst #2725 = VASTART_SAVE_XMM_REGS | |
| { 2726, 8, 1, 0, 0, "VBLENDPDYrmi", 0|(1<<MCID::MayLoad), 0xa1b804e46ULL, NULL, NULL, OperandInfo228 }, // Inst #2726 = VBLENDPDYrmi | |
| { 2727, 4, 1, 0, 0, "VBLENDPDYrri", 0, 0xa1b804e45ULL, NULL, NULL, OperandInfo87 }, // Inst #2727 = VBLENDPDYrri | |
| { 2728, 8, 1, 0, 0, "VBLENDPDrmi", 0|(1<<MCID::MayLoad), 0xa1b804e46ULL, NULL, NULL, OperandInfo136 }, // Inst #2728 = VBLENDPDrmi | |
| { 2729, 4, 1, 0, 0, "VBLENDPDrri", 0, 0xa1b804e45ULL, NULL, NULL, OperandInfo86 }, // Inst #2729 = VBLENDPDrri | |
| { 2730, 8, 1, 0, 0, "VBLENDPSYrmi", 0|(1<<MCID::MayLoad), 0xa19804e46ULL, NULL, NULL, OperandInfo228 }, // Inst #2730 = VBLENDPSYrmi | |
| { 2731, 4, 1, 0, 0, "VBLENDPSYrri", 0, 0xa19804e45ULL, NULL, NULL, OperandInfo87 }, // Inst #2731 = VBLENDPSYrri | |
| { 2732, 8, 1, 0, 0, "VBLENDPSrmi", 0|(1<<MCID::MayLoad), 0xa19804e46ULL, NULL, NULL, OperandInfo136 }, // Inst #2732 = VBLENDPSrmi | |
| { 2733, 4, 1, 0, 0, "VBLENDPSrri", 0, 0xa19804e45ULL, NULL, NULL, OperandInfo86 }, // Inst #2733 = VBLENDPSrri | |
| { 2734, 8, 1, 0, 0, "VBLENDVPDYrm", 0|(1<<MCID::MayLoad), 0x1a97800e46ULL, NULL, NULL, OperandInfo229 }, // Inst #2734 = VBLENDVPDYrm | |
| { 2735, 4, 1, 0, 0, "VBLENDVPDYrr", 0, 0x1a97800e45ULL, NULL, NULL, OperandInfo230 }, // Inst #2735 = VBLENDVPDYrr | |
| { 2736, 8, 1, 0, 0, "VBLENDVPDrm", 0|(1<<MCID::MayLoad), 0x1a97800e46ULL, NULL, NULL, OperandInfo231 }, // Inst #2736 = VBLENDVPDrm | |
| { 2737, 4, 1, 0, 0, "VBLENDVPDrr", 0, 0x1a97800e45ULL, NULL, NULL, OperandInfo232 }, // Inst #2737 = VBLENDVPDrr | |
| { 2738, 8, 1, 0, 0, "VBLENDVPSYrm", 0|(1<<MCID::MayLoad), 0x1a95800e46ULL, NULL, NULL, OperandInfo229 }, // Inst #2738 = VBLENDVPSYrm | |
| { 2739, 4, 1, 0, 0, "VBLENDVPSYrr", 0, 0x1a95800e45ULL, NULL, NULL, OperandInfo230 }, // Inst #2739 = VBLENDVPSYrr | |
| { 2740, 8, 1, 0, 0, "VBLENDVPSrm", 0|(1<<MCID::MayLoad), 0x1a95800e46ULL, NULL, NULL, OperandInfo231 }, // Inst #2740 = VBLENDVPSrm | |
| { 2741, 4, 1, 0, 0, "VBLENDVPSrr", 0, 0x1a95800e45ULL, NULL, NULL, OperandInfo232 }, // Inst #2741 = VBLENDVPSrr | |
| { 2742, 6, 1, 0, 0, "VBROADCASTF128", 0|(1<<MCID::MayLoad), 0x235800d46ULL, NULL, NULL, OperandInfo233 }, // Inst #2742 = VBROADCASTF128 | |
| { 2743, 6, 1, 0, 0, "VBROADCASTSD", 0|(1<<MCID::MayLoad), 0x233800d46ULL, NULL, NULL, OperandInfo233 }, // Inst #2743 = VBROADCASTSD | |
| { 2744, 6, 1, 0, 0, "VBROADCASTSS", 0|(1<<MCID::MayLoad), 0x231800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #2744 = VBROADCASTSS | |
| { 2745, 6, 1, 0, 0, "VBROADCASTSSY", 0|(1<<MCID::MayLoad), 0x231800d46ULL, NULL, NULL, OperandInfo233 }, // Inst #2745 = VBROADCASTSSY | |
| { 2746, 8, 1, 0, 0, "VCMPPDYrmi", 0|(1<<MCID::MayLoad), 0xb85004146ULL, NULL, NULL, OperandInfo228 }, // Inst #2746 = VCMPPDYrmi | |
| { 2747, 8, 1, 0, 0, "VCMPPDYrmi_alt", 0|(1<<MCID::UnmodeledSideEffects), 0xb85004146ULL, NULL, NULL, OperandInfo228 }, // Inst #2747 = VCMPPDYrmi_alt | |
| { 2748, 4, 1, 0, 0, "VCMPPDYrri", 0, 0xb85004145ULL, NULL, NULL, OperandInfo87 }, // Inst #2748 = VCMPPDYrri | |
| { 2749, 4, 1, 0, 0, "VCMPPDYrri_alt", 0|(1<<MCID::UnmodeledSideEffects), 0xb85004145ULL, NULL, NULL, OperandInfo87 }, // Inst #2749 = VCMPPDYrri_alt | |
| { 2750, 8, 1, 0, 0, "VCMPPDrmi", 0|(1<<MCID::MayLoad), 0xb85004146ULL, NULL, NULL, OperandInfo136 }, // Inst #2750 = VCMPPDrmi | |
| { 2751, 8, 1, 0, 0, "VCMPPDrmi_alt", 0|(1<<MCID::UnmodeledSideEffects), 0xb85004146ULL, NULL, NULL, OperandInfo136 }, // Inst #2751 = VCMPPDrmi_alt | |
| { 2752, 4, 1, 0, 0, "VCMPPDrri", 0, 0xb85004145ULL, NULL, NULL, OperandInfo86 }, // Inst #2752 = VCMPPDrri | |
| { 2753, 4, 1, 0, 0, "VCMPPDrri_alt", 0|(1<<MCID::UnmodeledSideEffects), 0xb85004145ULL, NULL, NULL, OperandInfo86 }, // Inst #2753 = VCMPPDrri_alt | |
| { 2754, 8, 1, 0, 0, "VCMPPSYrmi", 0|(1<<MCID::MayLoad), 0xb84804106ULL, NULL, NULL, OperandInfo228 }, // Inst #2754 = VCMPPSYrmi | |
| { 2755, 8, 1, 0, 0, "VCMPPSYrmi_alt", 0|(1<<MCID::UnmodeledSideEffects), 0xb84804106ULL, NULL, NULL, OperandInfo228 }, // Inst #2755 = VCMPPSYrmi_alt | |
| { 2756, 4, 1, 0, 0, "VCMPPSYrri", 0, 0xb84804105ULL, NULL, NULL, OperandInfo87 }, // Inst #2756 = VCMPPSYrri | |
| { 2757, 4, 1, 0, 0, "VCMPPSYrri_alt", 0|(1<<MCID::UnmodeledSideEffects), 0xb84804105ULL, NULL, NULL, OperandInfo87 }, // Inst #2757 = VCMPPSYrri_alt | |
| { 2758, 8, 1, 0, 0, "VCMPPSrmi", 0|(1<<MCID::MayLoad), 0xb84804106ULL, NULL, NULL, OperandInfo136 }, // Inst #2758 = VCMPPSrmi | |
| { 2759, 8, 1, 0, 0, "VCMPPSrmi_alt", 0|(1<<MCID::UnmodeledSideEffects), 0xb84804106ULL, NULL, NULL, OperandInfo136 }, // Inst #2759 = VCMPPSrmi_alt | |
| { 2760, 4, 1, 0, 0, "VCMPPSrri", 0, 0xb84804105ULL, NULL, NULL, OperandInfo86 }, // Inst #2760 = VCMPPSrri | |
| { 2761, 4, 1, 0, 0, "VCMPPSrri_alt", 0|(1<<MCID::UnmodeledSideEffects), 0xb84804105ULL, NULL, NULL, OperandInfo86 }, // Inst #2761 = VCMPPSrri_alt | |
| { 2762, 8, 1, 0, 0, "VCMPSDrm", 0|(1<<MCID::MayLoad), 0x4b84004b06ULL, NULL, NULL, OperandInfo234 }, // Inst #2762 = VCMPSDrm | |
| { 2763, 8, 1, 0, 0, "VCMPSDrm_alt", 0|(1<<MCID::MayLoad), 0x4b84004b06ULL, NULL, NULL, OperandInfo234 }, // Inst #2763 = VCMPSDrm_alt | |
| { 2764, 4, 1, 0, 0, "VCMPSDrr", 0, 0x4b84004b05ULL, NULL, NULL, OperandInfo79 }, // Inst #2764 = VCMPSDrr | |
| { 2765, 4, 1, 0, 0, "VCMPSDrr_alt", 0, 0x4b84004b05ULL, NULL, NULL, OperandInfo79 }, // Inst #2765 = VCMPSDrr_alt | |
| { 2766, 8, 1, 0, 0, "VCMPSSrm", 0|(1<<MCID::MayLoad), 0x4b84004c06ULL, NULL, NULL, OperandInfo235 }, // Inst #2766 = VCMPSSrm | |
| { 2767, 8, 1, 0, 0, "VCMPSSrm_alt", 0|(1<<MCID::MayLoad), 0x4b84004c06ULL, NULL, NULL, OperandInfo235 }, // Inst #2767 = VCMPSSrm_alt | |
| { 2768, 4, 1, 0, 0, "VCMPSSrr", 0, 0x4b84004c05ULL, NULL, NULL, OperandInfo78 }, // Inst #2768 = VCMPSSrr | |
| { 2769, 4, 1, 0, 0, "VCMPSSrr_alt", 0, 0x4b84004c05ULL, NULL, NULL, OperandInfo78 }, // Inst #2769 = VCMPSSrr_alt | |
| { 2770, 6, 0, 0, 0, "VCOMISDrm", 0|(1<<MCID::UnmodeledSideEffects), 0x425f000146ULL, NULL, ImplicitList1, OperandInfo47 }, // Inst #2770 = VCOMISDrm | |
| { 2771, 2, 0, 0, 0, "VCOMISDrr", 0|(1<<MCID::UnmodeledSideEffects), 0x425f000145ULL, NULL, ImplicitList1, OperandInfo48 }, // Inst #2771 = VCOMISDrr | |
| { 2772, 6, 0, 0, 0, "VCOMISSrm", 0|(1<<MCID::UnmodeledSideEffects), 0x425e800106ULL, NULL, ImplicitList1, OperandInfo47 }, // Inst #2772 = VCOMISSrm | |
| { 2773, 2, 0, 0, 0, "VCOMISSrr", 0|(1<<MCID::UnmodeledSideEffects), 0x425e800105ULL, NULL, ImplicitList1, OperandInfo48 }, // Inst #2773 = VCOMISSrr | |
| { 2774, 6, 1, 0, 0, "VCVTDQ2PDYrm", 0|(1<<MCID::UnmodeledSideEffects), 0x3cc800c06ULL, NULL, NULL, OperandInfo233 }, // Inst #2774 = VCVTDQ2PDYrm | |
| { 2775, 2, 1, 0, 0, "VCVTDQ2PDYrr", 0|(1<<MCID::UnmodeledSideEffects), 0x3cc800c05ULL, NULL, NULL, OperandInfo236 }, // Inst #2775 = VCVTDQ2PDYrr | |
| { 2776, 6, 1, 0, 0, "VCVTDQ2PDrm", 0|(1<<MCID::UnmodeledSideEffects), 0x3cc800c06ULL, NULL, NULL, OperandInfo47 }, // Inst #2776 = VCVTDQ2PDrm | |
| { 2777, 2, 1, 0, 0, "VCVTDQ2PDrr", 0|(1<<MCID::UnmodeledSideEffects), 0x3cc800c05ULL, NULL, NULL, OperandInfo48 }, // Inst #2777 = VCVTDQ2PDrr | |
| { 2778, 6, 1, 0, 0, "VCVTDQ2PSYrm", 0|(1<<MCID::UnmodeledSideEffects), 0x2b6800106ULL, NULL, NULL, OperandInfo233 }, // Inst #2778 = VCVTDQ2PSYrm | |
| { 2779, 2, 1, 0, 0, "VCVTDQ2PSYrr", 0|(1<<MCID::UnmodeledSideEffects), 0x2b6800105ULL, NULL, NULL, OperandInfo237 }, // Inst #2779 = VCVTDQ2PSYrr | |
| { 2780, 6, 1, 0, 0, "VCVTDQ2PSrm", 0|(1<<MCID::UnmodeledSideEffects), 0x2b6800106ULL, NULL, NULL, OperandInfo47 }, // Inst #2780 = VCVTDQ2PSrm | |
| { 2781, 2, 1, 0, 0, "VCVTDQ2PSrr", 0|(1<<MCID::UnmodeledSideEffects), 0x2b6800105ULL, NULL, NULL, OperandInfo48 }, // Inst #2781 = VCVTDQ2PSrr | |
| { 2782, 2, 1, 0, 0, "VCVTPD2DQXrYr", 0|(1<<MCID::UnmodeledSideEffects), 0x3cd000b05ULL, NULL, NULL, OperandInfo238 }, // Inst #2782 = VCVTPD2DQXrYr | |
| { 2783, 6, 1, 0, 0, "VCVTPD2DQXrm", 0|(1<<MCID::UnmodeledSideEffects), 0x3cd000b06ULL, NULL, NULL, OperandInfo47 }, // Inst #2783 = VCVTPD2DQXrm | |
| { 2784, 2, 1, 0, 0, "VCVTPD2DQXrr", 0|(1<<MCID::UnmodeledSideEffects), 0x3cd000b05ULL, NULL, NULL, OperandInfo48 }, // Inst #2784 = VCVTPD2DQXrr | |
| { 2785, 6, 1, 0, 0, "VCVTPD2DQYrm", 0|(1<<MCID::UnmodeledSideEffects), 0x23cd000b06ULL, NULL, NULL, OperandInfo47 }, // Inst #2785 = VCVTPD2DQYrm | |
| { 2786, 2, 1, 0, 0, "VCVTPD2DQYrr", 0|(1<<MCID::UnmodeledSideEffects), 0x3cd000b05ULL, NULL, NULL, OperandInfo238 }, // Inst #2786 = VCVTPD2DQYrr | |
| { 2787, 2, 1, 0, 0, "VCVTPD2DQrr", 0|(1<<MCID::UnmodeledSideEffects), 0x3cd000b05ULL, NULL, NULL, OperandInfo48 }, // Inst #2787 = VCVTPD2DQrr | |
| { 2788, 2, 1, 0, 0, "VCVTPD2PSXrYr", 0|(1<<MCID::UnmodeledSideEffects), 0x2b5000145ULL, NULL, NULL, OperandInfo238 }, // Inst #2788 = VCVTPD2PSXrYr | |
| { 2789, 6, 1, 0, 0, "VCVTPD2PSXrm", 0|(1<<MCID::UnmodeledSideEffects), 0x2b5000146ULL, NULL, NULL, OperandInfo47 }, // Inst #2789 = VCVTPD2PSXrm | |
| { 2790, 2, 1, 0, 0, "VCVTPD2PSXrr", 0|(1<<MCID::UnmodeledSideEffects), 0x2b5000145ULL, NULL, NULL, OperandInfo48 }, // Inst #2790 = VCVTPD2PSXrr | |
| { 2791, 6, 1, 0, 0, "VCVTPD2PSYrm", 0|(1<<MCID::UnmodeledSideEffects), 0x22b5000146ULL, NULL, NULL, OperandInfo47 }, // Inst #2791 = VCVTPD2PSYrm | |
| { 2792, 2, 1, 0, 0, "VCVTPD2PSYrr", 0|(1<<MCID::UnmodeledSideEffects), 0x2b5000145ULL, NULL, NULL, OperandInfo238 }, // Inst #2792 = VCVTPD2PSYrr | |
| { 2793, 2, 1, 0, 0, "VCVTPD2PSrr", 0|(1<<MCID::UnmodeledSideEffects), 0x2b5000145ULL, NULL, NULL, OperandInfo48 }, // Inst #2793 = VCVTPD2PSrr | |
| { 2794, 6, 1, 0, 0, "VCVTPH2PSYrm", 0|(1<<MCID::UnmodeledSideEffects), 0x226000d46ULL, NULL, NULL, OperandInfo233 }, // Inst #2794 = VCVTPH2PSYrm | |
| { 2795, 2, 1, 0, 0, "VCVTPH2PSYrr", 0|(1<<MCID::UnmodeledSideEffects), 0x226000d45ULL, NULL, NULL, OperandInfo236 }, // Inst #2795 = VCVTPH2PSYrr | |
| { 2796, 6, 1, 0, 0, "VCVTPH2PSrm", 0|(1<<MCID::UnmodeledSideEffects), 0x226000d46ULL, NULL, NULL, OperandInfo47 }, // Inst #2796 = VCVTPH2PSrm | |
| { 2797, 2, 1, 0, 0, "VCVTPH2PSrr", 0|(1<<MCID::UnmodeledSideEffects), 0x226000d45ULL, NULL, NULL, OperandInfo48 }, // Inst #2797 = VCVTPH2PSrr | |
| { 2798, 6, 1, 0, 0, "VCVTPS2DQYrm", 0|(1<<MCID::UnmodeledSideEffects), 0x2b7000146ULL, NULL, NULL, OperandInfo233 }, // Inst #2798 = VCVTPS2DQYrm | |
| { 2799, 2, 1, 0, 0, "VCVTPS2DQYrr", 0|(1<<MCID::UnmodeledSideEffects), 0x2b7000145ULL, NULL, NULL, OperandInfo237 }, // Inst #2799 = VCVTPS2DQYrr | |
| { 2800, 6, 1, 0, 0, "VCVTPS2DQrm", 0|(1<<MCID::UnmodeledSideEffects), 0x2b7000146ULL, NULL, NULL, OperandInfo47 }, // Inst #2800 = VCVTPS2DQrm | |
| { 2801, 2, 1, 0, 0, "VCVTPS2DQrr", 0|(1<<MCID::UnmodeledSideEffects), 0x2b7000145ULL, NULL, NULL, OperandInfo48 }, // Inst #2801 = VCVTPS2DQrr | |
| { 2802, 6, 1, 0, 0, "VCVTPS2PDYrm", 0|(1<<MCID::UnmodeledSideEffects), 0x2b4000106ULL, NULL, NULL, OperandInfo233 }, // Inst #2802 = VCVTPS2PDYrm | |
| { 2803, 2, 1, 0, 0, "VCVTPS2PDYrr", 0|(1<<MCID::UnmodeledSideEffects), 0x2b4000105ULL, NULL, NULL, OperandInfo236 }, // Inst #2803 = VCVTPS2PDYrr | |
| { 2804, 6, 1, 0, 0, "VCVTPS2PDrm", 0|(1<<MCID::UnmodeledSideEffects), 0x2b4000106ULL, NULL, NULL, OperandInfo47 }, // Inst #2804 = VCVTPS2PDrm | |
| { 2805, 2, 1, 0, 0, "VCVTPS2PDrr", 0|(1<<MCID::UnmodeledSideEffects), 0x2b4000105ULL, NULL, NULL, OperandInfo48 }, // Inst #2805 = VCVTPS2PDrr | |
| { 2806, 7, 1, 0, 0, "VCVTPS2PHYmr", 0|(1<<MCID::UnmodeledSideEffects), 0x23a004e44ULL, NULL, NULL, OperandInfo239 }, // Inst #2806 = VCVTPS2PHYmr | |
| { 2807, 3, 1, 0, 0, "VCVTPS2PHYrr", 0|(1<<MCID::UnmodeledSideEffects), 0x23a004e43ULL, NULL, NULL, OperandInfo240 }, // Inst #2807 = VCVTPS2PHYrr | |
| { 2808, 7, 1, 0, 0, "VCVTPS2PHmr", 0|(1<<MCID::UnmodeledSideEffects), 0x23a004e44ULL, NULL, NULL, OperandInfo115 }, // Inst #2808 = VCVTPS2PHmr | |
| { 2809, 3, 1, 0, 0, "VCVTPS2PHrr", 0|(1<<MCID::UnmodeledSideEffects), 0x23a004e43ULL, NULL, NULL, OperandInfo50 }, // Inst #2809 = VCVTPS2PHrr | |
| { 2810, 6, 1, 0, 0, "VCVTSD2SI64rm", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x465a000b06ULL, NULL, NULL, OperandInfo13 }, // Inst #2810 = VCVTSD2SI64rm | |
| { 2811, 2, 1, 0, 0, "VCVTSD2SI64rr", 0|(1<<MCID::UnmodeledSideEffects), 0x465a000b05ULL, NULL, NULL, OperandInfo109 }, // Inst #2811 = VCVTSD2SI64rr | |
| { 2812, 6, 1, 0, 0, "VCVTSD2SIrm", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x425a000b06ULL, NULL, NULL, OperandInfo12 }, // Inst #2812 = VCVTSD2SIrm | |
| { 2813, 2, 1, 0, 0, "VCVTSD2SIrr", 0|(1<<MCID::UnmodeledSideEffects), 0x425a000b05ULL, NULL, NULL, OperandInfo110 }, // Inst #2813 = VCVTSD2SIrr | |
| { 2814, 7, 1, 0, 0, "VCVTSD2SSrm", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x4ab4000b06ULL, NULL, NULL, OperandInfo241 }, // Inst #2814 = VCVTSD2SSrm | |
| { 2815, 3, 1, 0, 0, "VCVTSD2SSrr", 0|(1<<MCID::UnmodeledSideEffects), 0x4ab4000b05ULL, NULL, NULL, OperandInfo242 }, // Inst #2815 = VCVTSD2SSrr | |
| { 2816, 7, 1, 0, 0, "VCVTSI2SD64rm", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x4e54000b06ULL, NULL, NULL, OperandInfo223 }, // Inst #2816 = VCVTSI2SD64rm | |
| { 2817, 3, 1, 0, 0, "VCVTSI2SD64rr", 0|(1<<MCID::UnmodeledSideEffects), 0x4e54000b05ULL, NULL, NULL, OperandInfo243 }, // Inst #2817 = VCVTSI2SD64rr | |
| { 2818, 7, 1, 0, 0, "VCVTSI2SDLrm", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x4a54000b06ULL, NULL, NULL, OperandInfo223 }, // Inst #2818 = VCVTSI2SDLrm | |
| { 2819, 3, 1, 0, 0, "VCVTSI2SDLrr", 0|(1<<MCID::UnmodeledSideEffects), 0x4a54000b05ULL, NULL, NULL, OperandInfo244 }, // Inst #2819 = VCVTSI2SDLrr | |
| { 2820, 7, 1, 0, 0, "VCVTSI2SDrm", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x4a54000b06ULL, NULL, NULL, OperandInfo223 }, // Inst #2820 = VCVTSI2SDrm | |
| { 2821, 3, 1, 0, 0, "VCVTSI2SDrr", 0|(1<<MCID::UnmodeledSideEffects), 0x4a54000b05ULL, NULL, NULL, OperandInfo244 }, // Inst #2821 = VCVTSI2SDrr | |
| { 2822, 7, 1, 0, 0, "VCVTSI2SS64rm", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x4e54000c06ULL, NULL, NULL, OperandInfo225 }, // Inst #2822 = VCVTSI2SS64rm | |
| { 2823, 3, 1, 0, 0, "VCVTSI2SS64rr", 0|(1<<MCID::UnmodeledSideEffects), 0x4e54000c05ULL, NULL, NULL, OperandInfo245 }, // Inst #2823 = VCVTSI2SS64rr | |
| { 2824, 7, 1, 0, 0, "VCVTSI2SSrm", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x4a54000c06ULL, NULL, NULL, OperandInfo225 }, // Inst #2824 = VCVTSI2SSrm | |
| { 2825, 3, 1, 0, 0, "VCVTSI2SSrr", 0|(1<<MCID::UnmodeledSideEffects), 0x4a54000c05ULL, NULL, NULL, OperandInfo246 }, // Inst #2825 = VCVTSI2SSrr | |
| { 2826, 7, 1, 0, 0, "VCVTSS2SDrm", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x4ab4000c06ULL, NULL, NULL, OperandInfo247 }, // Inst #2826 = VCVTSS2SDrm | |
| { 2827, 3, 1, 0, 0, "VCVTSS2SDrr", 0|(1<<MCID::UnmodeledSideEffects), 0x4ab4000c05ULL, NULL, NULL, OperandInfo248 }, // Inst #2827 = VCVTSS2SDrr | |
| { 2828, 6, 1, 0, 0, "VCVTSS2SI64rm", 0|(1<<MCID::UnmodeledSideEffects), 0x465a000c06ULL, NULL, NULL, OperandInfo13 }, // Inst #2828 = VCVTSS2SI64rm | |
| { 2829, 2, 1, 0, 0, "VCVTSS2SI64rr", 0|(1<<MCID::UnmodeledSideEffects), 0x465a000c05ULL, NULL, NULL, OperandInfo107 }, // Inst #2829 = VCVTSS2SI64rr | |
| { 2830, 6, 1, 0, 0, "VCVTSS2SIrm", 0|(1<<MCID::UnmodeledSideEffects), 0x425a000c06ULL, NULL, NULL, OperandInfo12 }, // Inst #2830 = VCVTSS2SIrm | |
| { 2831, 2, 1, 0, 0, "VCVTSS2SIrr", 0|(1<<MCID::UnmodeledSideEffects), 0x425a000c05ULL, NULL, NULL, OperandInfo108 }, // Inst #2831 = VCVTSS2SIrr | |
| { 2832, 2, 1, 0, 0, "VCVTTPD2DQXrYr", 0|(1<<MCID::UnmodeledSideEffects), 0x3cd000145ULL, NULL, NULL, OperandInfo238 }, // Inst #2832 = VCVTTPD2DQXrYr | |
| { 2833, 6, 1, 0, 0, "VCVTTPD2DQXrm", 0|(1<<MCID::UnmodeledSideEffects), 0x3cd000146ULL, NULL, NULL, OperandInfo47 }, // Inst #2833 = VCVTTPD2DQXrm | |
| { 2834, 2, 1, 0, 0, "VCVTTPD2DQXrr", 0|(1<<MCID::UnmodeledSideEffects), 0x3cd000145ULL, NULL, NULL, OperandInfo48 }, // Inst #2834 = VCVTTPD2DQXrr | |
| { 2835, 6, 1, 0, 0, "VCVTTPD2DQYrm", 0|(1<<MCID::UnmodeledSideEffects), 0x23cd000146ULL, NULL, NULL, OperandInfo47 }, // Inst #2835 = VCVTTPD2DQYrm | |
| { 2836, 2, 1, 0, 0, "VCVTTPD2DQYrr", 0|(1<<MCID::UnmodeledSideEffects), 0x3cd000145ULL, NULL, NULL, OperandInfo238 }, // Inst #2836 = VCVTTPD2DQYrr | |
| { 2837, 6, 1, 0, 0, "VCVTTPD2DQrm", 0|(1<<MCID::MayLoad), 0x3cd000146ULL, NULL, NULL, OperandInfo47 }, // Inst #2837 = VCVTTPD2DQrm | |
| { 2838, 2, 1, 0, 0, "VCVTTPD2DQrr", 0, 0x3cd000145ULL, NULL, NULL, OperandInfo48 }, // Inst #2838 = VCVTTPD2DQrr | |
| { 2839, 6, 1, 0, 0, "VCVTTPS2DQYrm", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x2b6000c06ULL, NULL, NULL, OperandInfo233 }, // Inst #2839 = VCVTTPS2DQYrm | |
| { 2840, 2, 1, 0, 0, "VCVTTPS2DQYrr", 0|(1<<MCID::UnmodeledSideEffects), 0x2b6000c05ULL, NULL, NULL, OperandInfo237 }, // Inst #2840 = VCVTTPS2DQYrr | |
| { 2841, 6, 1, 0, 0, "VCVTTPS2DQrm", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x2b6000c06ULL, NULL, NULL, OperandInfo47 }, // Inst #2841 = VCVTTPS2DQrm | |
| { 2842, 2, 1, 0, 0, "VCVTTPS2DQrr", 0|(1<<MCID::UnmodeledSideEffects), 0x2b6000c05ULL, NULL, NULL, OperandInfo48 }, // Inst #2842 = VCVTTPS2DQrr | |
| { 2843, 6, 1, 0, 0, "VCVTTSD2SI64rm", 0|(1<<MCID::MayLoad), 0x4658000b06ULL, NULL, NULL, OperandInfo13 }, // Inst #2843 = VCVTTSD2SI64rm | |
| { 2844, 2, 1, 0, 0, "VCVTTSD2SI64rr", 0, 0x4658000b05ULL, NULL, NULL, OperandInfo109 }, // Inst #2844 = VCVTTSD2SI64rr | |
| { 2845, 6, 1, 0, 0, "VCVTTSD2SIrm", 0|(1<<MCID::MayLoad), 0x4258000b06ULL, NULL, NULL, OperandInfo12 }, // Inst #2845 = VCVTTSD2SIrm | |
| { 2846, 2, 1, 0, 0, "VCVTTSD2SIrr", 0, 0x4258000b05ULL, NULL, NULL, OperandInfo110 }, // Inst #2846 = VCVTTSD2SIrr | |
| { 2847, 6, 1, 0, 0, "VCVTTSS2SI64rm", 0|(1<<MCID::MayLoad), 0x4658000c06ULL, NULL, NULL, OperandInfo13 }, // Inst #2847 = VCVTTSS2SI64rm | |
| { 2848, 2, 1, 0, 0, "VCVTTSS2SI64rr", 0, 0x4658000c05ULL, NULL, NULL, OperandInfo107 }, // Inst #2848 = VCVTTSS2SI64rr | |
| { 2849, 6, 1, 0, 0, "VCVTTSS2SIrm", 0|(1<<MCID::MayLoad), 0x4258000c06ULL, NULL, NULL, OperandInfo12 }, // Inst #2849 = VCVTTSS2SIrm | |
| { 2850, 2, 1, 0, 0, "VCVTTSS2SIrr", 0, 0x4258000c05ULL, NULL, NULL, OperandInfo108 }, // Inst #2850 = VCVTTSS2SIrr | |
| { 2851, 7, 1, 0, 0, "VDIVPDYrm", 0|(1<<MCID::MayLoad), 0xabd000146ULL, NULL, NULL, OperandInfo221 }, // Inst #2851 = VDIVPDYrm | |
| { 2852, 3, 1, 0, 0, "VDIVPDYrr", 0, 0xabd000145ULL, NULL, NULL, OperandInfo222 }, // Inst #2852 = VDIVPDYrr | |
| { 2853, 7, 1, 0, 0, "VDIVPDrm", 0|(1<<MCID::MayLoad), 0xabd000146ULL, NULL, NULL, OperandInfo137 }, // Inst #2853 = VDIVPDrm | |
| { 2854, 3, 1, 0, 0, "VDIVPDrr", 0, 0xabd000145ULL, NULL, NULL, OperandInfo138 }, // Inst #2854 = VDIVPDrr | |
| { 2855, 7, 1, 0, 0, "VDIVPSYrm", 0|(1<<MCID::MayLoad), 0xabc800106ULL, NULL, NULL, OperandInfo221 }, // Inst #2855 = VDIVPSYrm | |
| { 2856, 3, 1, 0, 0, "VDIVPSYrr", 0, 0xabc800105ULL, NULL, NULL, OperandInfo222 }, // Inst #2856 = VDIVPSYrr | |
| { 2857, 7, 1, 0, 0, "VDIVPSrm", 0|(1<<MCID::MayLoad), 0xabc800106ULL, NULL, NULL, OperandInfo137 }, // Inst #2857 = VDIVPSrm | |
| { 2858, 3, 1, 0, 0, "VDIVPSrr", 0, 0xabc800105ULL, NULL, NULL, OperandInfo138 }, // Inst #2858 = VDIVPSrr | |
| { 2859, 7, 1, 0, 0, "VDIVSDrm", 0|(1<<MCID::MayLoad), 0x4abc000b06ULL, NULL, NULL, OperandInfo223 }, // Inst #2859 = VDIVSDrm | |
| { 2860, 7, 1, 0, 0, "VDIVSDrm_Int", 0|(1<<MCID::MayLoad), 0x4abc000b06ULL, NULL, NULL, OperandInfo137 }, // Inst #2860 = VDIVSDrm_Int | |
| { 2861, 3, 1, 0, 0, "VDIVSDrr", 0, 0x4abc000b05ULL, NULL, NULL, OperandInfo224 }, // Inst #2861 = VDIVSDrr | |
| { 2862, 3, 1, 0, 0, "VDIVSDrr_Int", 0, 0x4abc000b05ULL, NULL, NULL, OperandInfo138 }, // Inst #2862 = VDIVSDrr_Int | |
| { 2863, 7, 1, 0, 0, "VDIVSSrm", 0|(1<<MCID::MayLoad), 0x4abc000c06ULL, NULL, NULL, OperandInfo225 }, // Inst #2863 = VDIVSSrm | |
| { 2864, 7, 1, 0, 0, "VDIVSSrm_Int", 0|(1<<MCID::MayLoad), 0x4abc000c06ULL, NULL, NULL, OperandInfo137 }, // Inst #2864 = VDIVSSrm_Int | |
| { 2865, 3, 1, 0, 0, "VDIVSSrr", 0, 0x4abc000c05ULL, NULL, NULL, OperandInfo226 }, // Inst #2865 = VDIVSSrr | |
| { 2866, 3, 1, 0, 0, "VDIVSSrr_Int", 0, 0x4abc000c05ULL, NULL, NULL, OperandInfo138 }, // Inst #2866 = VDIVSSrr_Int | |
| { 2867, 8, 1, 0, 0, "VDPPDrmi", 0|(1<<MCID::MayLoad), 0xa83804e46ULL, NULL, NULL, OperandInfo136 }, // Inst #2867 = VDPPDrmi | |
| { 2868, 4, 1, 0, 0, "VDPPDrri", 0|(1<<MCID::Commutable), 0xa83804e45ULL, NULL, NULL, OperandInfo86 }, // Inst #2868 = VDPPDrri | |
| { 2869, 8, 1, 0, 0, "VDPPSYrmi", 0|(1<<MCID::MayLoad), 0xa81804e46ULL, NULL, NULL, OperandInfo228 }, // Inst #2869 = VDPPSYrmi | |
| { 2870, 4, 1, 0, 0, "VDPPSYrri", 0|(1<<MCID::Commutable), 0xa81804e45ULL, NULL, NULL, OperandInfo87 }, // Inst #2870 = VDPPSYrri | |
| { 2871, 8, 1, 0, 0, "VDPPSrmi", 0|(1<<MCID::MayLoad), 0xa81804e46ULL, NULL, NULL, OperandInfo136 }, // Inst #2871 = VDPPSrmi | |
| { 2872, 4, 1, 0, 0, "VDPPSrri", 0|(1<<MCID::Commutable), 0xa81804e45ULL, NULL, NULL, OperandInfo86 }, // Inst #2872 = VDPPSrri | |
| { 2873, 5, 0, 0, 0, "VERRm", 0|(1<<MCID::UnmodeledSideEffects), 0x11cULL, NULL, NULL, OperandInfo38 }, // Inst #2873 = VERRm | |
| { 2874, 1, 0, 0, 0, "VERRr", 0|(1<<MCID::UnmodeledSideEffects), 0x114ULL, NULL, NULL, OperandInfo113 }, // Inst #2874 = VERRr | |
| { 2875, 5, 0, 0, 0, "VERWm", 0|(1<<MCID::UnmodeledSideEffects), 0x11dULL, NULL, NULL, OperandInfo38 }, // Inst #2875 = VERWm | |
| { 2876, 1, 0, 0, 0, "VERWr", 0|(1<<MCID::UnmodeledSideEffects), 0x115ULL, NULL, NULL, OperandInfo113 }, // Inst #2876 = VERWr | |
| { 2877, 7, 0, 0, 0, "VEXTRACTF128mr", 0|(1<<MCID::UnmodeledSideEffects), 0x233804e44ULL, NULL, NULL, OperandInfo239 }, // Inst #2877 = VEXTRACTF128mr | |
| { 2878, 3, 1, 0, 0, "VEXTRACTF128rr", 0|(1<<MCID::UnmodeledSideEffects), 0x233804e43ULL, NULL, NULL, OperandInfo240 }, // Inst #2878 = VEXTRACTF128rr | |
| { 2879, 7, 0, 0, 0, "VEXTRACTPSmr", 0|(1<<MCID::MayStore), 0x22f804e44ULL, NULL, NULL, OperandInfo115 }, // Inst #2879 = VEXTRACTPSmr | |
| { 2880, 3, 1, 0, 0, "VEXTRACTPSrr", 0, 0x22f804e43ULL, NULL, NULL, OperandInfo116 }, // Inst #2880 = VEXTRACTPSrr | |
| { 2881, 3, 1, 0, 0, "VEXTRACTPSrr64", 0|(1<<MCID::UnmodeledSideEffects), 0x22f804e43ULL, NULL, NULL, OperandInfo200 }, // Inst #2881 = VEXTRACTPSrr64 | |
| { 2882, 7, 1, 0, 0, "VFMADDPDr132m", 0|(1<<MCID::UnmodeledSideEffects), 0xf31800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2882 = VFMADDPDr132m | |
| { 2883, 7, 1, 0, 0, "VFMADDPDr132mY", 0|(1<<MCID::UnmodeledSideEffects), 0xf31800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2883 = VFMADDPDr132mY | |
| { 2884, 3, 1, 0, 0, "VFMADDPDr132r", 0|(1<<MCID::UnmodeledSideEffects), 0xf31800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2884 = VFMADDPDr132r | |
| { 2885, 3, 1, 0, 0, "VFMADDPDr132rY", 0|(1<<MCID::UnmodeledSideEffects), 0xf31800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2885 = VFMADDPDr132rY | |
| { 2886, 7, 1, 0, 0, "VFMADDPDr213m", 0|(1<<MCID::UnmodeledSideEffects), 0xf51800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2886 = VFMADDPDr213m | |
| { 2887, 7, 1, 0, 0, "VFMADDPDr213mY", 0|(1<<MCID::UnmodeledSideEffects), 0xf51800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2887 = VFMADDPDr213mY | |
| { 2888, 3, 1, 0, 0, "VFMADDPDr213r", 0|(1<<MCID::UnmodeledSideEffects), 0xf51800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2888 = VFMADDPDr213r | |
| { 2889, 3, 1, 0, 0, "VFMADDPDr213rY", 0|(1<<MCID::UnmodeledSideEffects), 0xf51800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2889 = VFMADDPDr213rY | |
| { 2890, 7, 1, 0, 0, "VFMADDPDr231m", 0|(1<<MCID::UnmodeledSideEffects), 0xf71800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2890 = VFMADDPDr231m | |
| { 2891, 7, 1, 0, 0, "VFMADDPDr231mY", 0|(1<<MCID::UnmodeledSideEffects), 0xf71800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2891 = VFMADDPDr231mY | |
| { 2892, 3, 1, 0, 0, "VFMADDPDr231r", 0|(1<<MCID::UnmodeledSideEffects), 0xf71800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2892 = VFMADDPDr231r | |
| { 2893, 3, 1, 0, 0, "VFMADDPDr231rY", 0|(1<<MCID::UnmodeledSideEffects), 0xf71800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2893 = VFMADDPDr231rY | |
| { 2894, 7, 1, 0, 0, "VFMADDPSr132m", 0|(1<<MCID::UnmodeledSideEffects), 0xb31800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2894 = VFMADDPSr132m | |
| { 2895, 7, 1, 0, 0, "VFMADDPSr132mY", 0|(1<<MCID::UnmodeledSideEffects), 0xb31800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2895 = VFMADDPSr132mY | |
| { 2896, 3, 1, 0, 0, "VFMADDPSr132r", 0|(1<<MCID::UnmodeledSideEffects), 0xb31800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2896 = VFMADDPSr132r | |
| { 2897, 3, 1, 0, 0, "VFMADDPSr132rY", 0|(1<<MCID::UnmodeledSideEffects), 0xb31800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2897 = VFMADDPSr132rY | |
| { 2898, 7, 1, 0, 0, "VFMADDPSr213m", 0|(1<<MCID::UnmodeledSideEffects), 0xb51800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2898 = VFMADDPSr213m | |
| { 2899, 7, 1, 0, 0, "VFMADDPSr213mY", 0|(1<<MCID::UnmodeledSideEffects), 0xb51800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2899 = VFMADDPSr213mY | |
| { 2900, 3, 1, 0, 0, "VFMADDPSr213r", 0|(1<<MCID::UnmodeledSideEffects), 0xb51800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2900 = VFMADDPSr213r | |
| { 2901, 3, 1, 0, 0, "VFMADDPSr213rY", 0|(1<<MCID::UnmodeledSideEffects), 0xb51800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2901 = VFMADDPSr213rY | |
| { 2902, 7, 1, 0, 0, "VFMADDPSr231m", 0|(1<<MCID::UnmodeledSideEffects), 0xb71800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2902 = VFMADDPSr231m | |
| { 2903, 7, 1, 0, 0, "VFMADDPSr231mY", 0|(1<<MCID::UnmodeledSideEffects), 0xb71800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2903 = VFMADDPSr231mY | |
| { 2904, 3, 1, 0, 0, "VFMADDPSr231r", 0|(1<<MCID::UnmodeledSideEffects), 0xb71800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2904 = VFMADDPSr231r | |
| { 2905, 3, 1, 0, 0, "VFMADDPSr231rY", 0|(1<<MCID::UnmodeledSideEffects), 0xb71800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2905 = VFMADDPSr231rY | |
| { 2906, 7, 1, 0, 0, "VFMADDSUBPDr132m", 0|(1<<MCID::UnmodeledSideEffects), 0xf2d800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2906 = VFMADDSUBPDr132m | |
| { 2907, 7, 1, 0, 0, "VFMADDSUBPDr132mY", 0|(1<<MCID::UnmodeledSideEffects), 0xf2d800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2907 = VFMADDSUBPDr132mY | |
| { 2908, 3, 1, 0, 0, "VFMADDSUBPDr132r", 0|(1<<MCID::UnmodeledSideEffects), 0xf2d800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2908 = VFMADDSUBPDr132r | |
| { 2909, 3, 1, 0, 0, "VFMADDSUBPDr132rY", 0|(1<<MCID::UnmodeledSideEffects), 0xf2d800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2909 = VFMADDSUBPDr132rY | |
| { 2910, 7, 1, 0, 0, "VFMADDSUBPDr213m", 0|(1<<MCID::UnmodeledSideEffects), 0xf4d800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2910 = VFMADDSUBPDr213m | |
| { 2911, 7, 1, 0, 0, "VFMADDSUBPDr213mY", 0|(1<<MCID::UnmodeledSideEffects), 0xf4d800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2911 = VFMADDSUBPDr213mY | |
| { 2912, 3, 1, 0, 0, "VFMADDSUBPDr213r", 0|(1<<MCID::UnmodeledSideEffects), 0xf4d800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2912 = VFMADDSUBPDr213r | |
| { 2913, 3, 1, 0, 0, "VFMADDSUBPDr213rY", 0|(1<<MCID::UnmodeledSideEffects), 0xf4d800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2913 = VFMADDSUBPDr213rY | |
| { 2914, 7, 1, 0, 0, "VFMADDSUBPDr231m", 0|(1<<MCID::UnmodeledSideEffects), 0xf6d800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2914 = VFMADDSUBPDr231m | |
| { 2915, 7, 1, 0, 0, "VFMADDSUBPDr231mY", 0|(1<<MCID::UnmodeledSideEffects), 0xf6d800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2915 = VFMADDSUBPDr231mY | |
| { 2916, 3, 1, 0, 0, "VFMADDSUBPDr231r", 0|(1<<MCID::UnmodeledSideEffects), 0xf6d800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2916 = VFMADDSUBPDr231r | |
| { 2917, 3, 1, 0, 0, "VFMADDSUBPDr231rY", 0|(1<<MCID::UnmodeledSideEffects), 0xf6d800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2917 = VFMADDSUBPDr231rY | |
| { 2918, 7, 1, 0, 0, "VFMADDSUBPSr132m", 0|(1<<MCID::UnmodeledSideEffects), 0xb2d800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2918 = VFMADDSUBPSr132m | |
| { 2919, 7, 1, 0, 0, "VFMADDSUBPSr132mY", 0|(1<<MCID::UnmodeledSideEffects), 0xb2d800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2919 = VFMADDSUBPSr132mY | |
| { 2920, 3, 1, 0, 0, "VFMADDSUBPSr132r", 0|(1<<MCID::UnmodeledSideEffects), 0xb2d800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2920 = VFMADDSUBPSr132r | |
| { 2921, 3, 1, 0, 0, "VFMADDSUBPSr132rY", 0|(1<<MCID::UnmodeledSideEffects), 0xb2d800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2921 = VFMADDSUBPSr132rY | |
| { 2922, 7, 1, 0, 0, "VFMADDSUBPSr213m", 0|(1<<MCID::UnmodeledSideEffects), 0xb4d800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2922 = VFMADDSUBPSr213m | |
| { 2923, 7, 1, 0, 0, "VFMADDSUBPSr213mY", 0|(1<<MCID::UnmodeledSideEffects), 0xb4d800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2923 = VFMADDSUBPSr213mY | |
| { 2924, 3, 1, 0, 0, "VFMADDSUBPSr213r", 0|(1<<MCID::UnmodeledSideEffects), 0xb4d800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2924 = VFMADDSUBPSr213r | |
| { 2925, 3, 1, 0, 0, "VFMADDSUBPSr213rY", 0|(1<<MCID::UnmodeledSideEffects), 0xb4d800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2925 = VFMADDSUBPSr213rY | |
| { 2926, 7, 1, 0, 0, "VFMADDSUBPSr231m", 0|(1<<MCID::UnmodeledSideEffects), 0xb6d800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2926 = VFMADDSUBPSr231m | |
| { 2927, 7, 1, 0, 0, "VFMADDSUBPSr231mY", 0|(1<<MCID::UnmodeledSideEffects), 0xb6d800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2927 = VFMADDSUBPSr231mY | |
| { 2928, 3, 1, 0, 0, "VFMADDSUBPSr231r", 0|(1<<MCID::UnmodeledSideEffects), 0xb6d800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2928 = VFMADDSUBPSr231r | |
| { 2929, 3, 1, 0, 0, "VFMADDSUBPSr231rY", 0|(1<<MCID::UnmodeledSideEffects), 0xb6d800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2929 = VFMADDSUBPSr231rY | |
| { 2930, 7, 1, 0, 0, "VFMSUBADDPDr132m", 0|(1<<MCID::UnmodeledSideEffects), 0xf2f800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2930 = VFMSUBADDPDr132m | |
| { 2931, 7, 1, 0, 0, "VFMSUBADDPDr132mY", 0|(1<<MCID::UnmodeledSideEffects), 0xf2f800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2931 = VFMSUBADDPDr132mY | |
| { 2932, 3, 1, 0, 0, "VFMSUBADDPDr132r", 0|(1<<MCID::UnmodeledSideEffects), 0xf2f800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2932 = VFMSUBADDPDr132r | |
| { 2933, 3, 1, 0, 0, "VFMSUBADDPDr132rY", 0|(1<<MCID::UnmodeledSideEffects), 0xf2f800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2933 = VFMSUBADDPDr132rY | |
| { 2934, 7, 1, 0, 0, "VFMSUBADDPDr213m", 0|(1<<MCID::UnmodeledSideEffects), 0xf4f800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2934 = VFMSUBADDPDr213m | |
| { 2935, 7, 1, 0, 0, "VFMSUBADDPDr213mY", 0|(1<<MCID::UnmodeledSideEffects), 0xf4f800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2935 = VFMSUBADDPDr213mY | |
| { 2936, 3, 1, 0, 0, "VFMSUBADDPDr213r", 0|(1<<MCID::UnmodeledSideEffects), 0xf4f800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2936 = VFMSUBADDPDr213r | |
| { 2937, 3, 1, 0, 0, "VFMSUBADDPDr213rY", 0|(1<<MCID::UnmodeledSideEffects), 0xf4f800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2937 = VFMSUBADDPDr213rY | |
| { 2938, 7, 1, 0, 0, "VFMSUBADDPDr231m", 0|(1<<MCID::UnmodeledSideEffects), 0xf6f800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2938 = VFMSUBADDPDr231m | |
| { 2939, 7, 1, 0, 0, "VFMSUBADDPDr231mY", 0|(1<<MCID::UnmodeledSideEffects), 0xf6f800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2939 = VFMSUBADDPDr231mY | |
| { 2940, 3, 1, 0, 0, "VFMSUBADDPDr231r", 0|(1<<MCID::UnmodeledSideEffects), 0xf6f800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2940 = VFMSUBADDPDr231r | |
| { 2941, 3, 1, 0, 0, "VFMSUBADDPDr231rY", 0|(1<<MCID::UnmodeledSideEffects), 0xf6f800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2941 = VFMSUBADDPDr231rY | |
| { 2942, 7, 1, 0, 0, "VFMSUBADDPSr132m", 0|(1<<MCID::UnmodeledSideEffects), 0xb2f800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2942 = VFMSUBADDPSr132m | |
| { 2943, 7, 1, 0, 0, "VFMSUBADDPSr132mY", 0|(1<<MCID::UnmodeledSideEffects), 0xb2f800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2943 = VFMSUBADDPSr132mY | |
| { 2944, 3, 1, 0, 0, "VFMSUBADDPSr132r", 0|(1<<MCID::UnmodeledSideEffects), 0xb2f800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2944 = VFMSUBADDPSr132r | |
| { 2945, 3, 1, 0, 0, "VFMSUBADDPSr132rY", 0|(1<<MCID::UnmodeledSideEffects), 0xb2f800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2945 = VFMSUBADDPSr132rY | |
| { 2946, 7, 1, 0, 0, "VFMSUBADDPSr213m", 0|(1<<MCID::UnmodeledSideEffects), 0xb4f800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2946 = VFMSUBADDPSr213m | |
| { 2947, 7, 1, 0, 0, "VFMSUBADDPSr213mY", 0|(1<<MCID::UnmodeledSideEffects), 0xb4f800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2947 = VFMSUBADDPSr213mY | |
| { 2948, 3, 1, 0, 0, "VFMSUBADDPSr213r", 0|(1<<MCID::UnmodeledSideEffects), 0xb4f800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2948 = VFMSUBADDPSr213r | |
| { 2949, 3, 1, 0, 0, "VFMSUBADDPSr213rY", 0|(1<<MCID::UnmodeledSideEffects), 0xb4f800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2949 = VFMSUBADDPSr213rY | |
| { 2950, 7, 1, 0, 0, "VFMSUBADDPSr231m", 0|(1<<MCID::UnmodeledSideEffects), 0xb6f800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2950 = VFMSUBADDPSr231m | |
| { 2951, 7, 1, 0, 0, "VFMSUBADDPSr231mY", 0|(1<<MCID::UnmodeledSideEffects), 0xb6f800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2951 = VFMSUBADDPSr231mY | |
| { 2952, 3, 1, 0, 0, "VFMSUBADDPSr231r", 0|(1<<MCID::UnmodeledSideEffects), 0xb6f800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2952 = VFMSUBADDPSr231r | |
| { 2953, 3, 1, 0, 0, "VFMSUBADDPSr231rY", 0|(1<<MCID::UnmodeledSideEffects), 0xb6f800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2953 = VFMSUBADDPSr231rY | |
| { 2954, 7, 1, 0, 0, "VFMSUBPDr132m", 0|(1<<MCID::UnmodeledSideEffects), 0xf35800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2954 = VFMSUBPDr132m | |
| { 2955, 7, 1, 0, 0, "VFMSUBPDr132mY", 0|(1<<MCID::UnmodeledSideEffects), 0xf35800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2955 = VFMSUBPDr132mY | |
| { 2956, 3, 1, 0, 0, "VFMSUBPDr132r", 0|(1<<MCID::UnmodeledSideEffects), 0xf35800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2956 = VFMSUBPDr132r | |
| { 2957, 3, 1, 0, 0, "VFMSUBPDr132rY", 0|(1<<MCID::UnmodeledSideEffects), 0xf35800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2957 = VFMSUBPDr132rY | |
| { 2958, 7, 1, 0, 0, "VFMSUBPDr213m", 0|(1<<MCID::UnmodeledSideEffects), 0xf55800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2958 = VFMSUBPDr213m | |
| { 2959, 7, 1, 0, 0, "VFMSUBPDr213mY", 0|(1<<MCID::UnmodeledSideEffects), 0xf55800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2959 = VFMSUBPDr213mY | |
| { 2960, 3, 1, 0, 0, "VFMSUBPDr213r", 0|(1<<MCID::UnmodeledSideEffects), 0xf55800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2960 = VFMSUBPDr213r | |
| { 2961, 3, 1, 0, 0, "VFMSUBPDr213rY", 0|(1<<MCID::UnmodeledSideEffects), 0xf55800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2961 = VFMSUBPDr213rY | |
| { 2962, 7, 1, 0, 0, "VFMSUBPDr231m", 0|(1<<MCID::UnmodeledSideEffects), 0xf75800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2962 = VFMSUBPDr231m | |
| { 2963, 7, 1, 0, 0, "VFMSUBPDr231mY", 0|(1<<MCID::UnmodeledSideEffects), 0xf75800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2963 = VFMSUBPDr231mY | |
| { 2964, 3, 1, 0, 0, "VFMSUBPDr231r", 0|(1<<MCID::UnmodeledSideEffects), 0xf75800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2964 = VFMSUBPDr231r | |
| { 2965, 3, 1, 0, 0, "VFMSUBPDr231rY", 0|(1<<MCID::UnmodeledSideEffects), 0xf75800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2965 = VFMSUBPDr231rY | |
| { 2966, 7, 1, 0, 0, "VFMSUBPSr132m", 0|(1<<MCID::UnmodeledSideEffects), 0xb35800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2966 = VFMSUBPSr132m | |
| { 2967, 7, 1, 0, 0, "VFMSUBPSr132mY", 0|(1<<MCID::UnmodeledSideEffects), 0xb35800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2967 = VFMSUBPSr132mY | |
| { 2968, 3, 1, 0, 0, "VFMSUBPSr132r", 0|(1<<MCID::UnmodeledSideEffects), 0xb35800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2968 = VFMSUBPSr132r | |
| { 2969, 3, 1, 0, 0, "VFMSUBPSr132rY", 0|(1<<MCID::UnmodeledSideEffects), 0xb35800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2969 = VFMSUBPSr132rY | |
| { 2970, 7, 1, 0, 0, "VFMSUBPSr213m", 0|(1<<MCID::UnmodeledSideEffects), 0xb55800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2970 = VFMSUBPSr213m | |
| { 2971, 7, 1, 0, 0, "VFMSUBPSr213mY", 0|(1<<MCID::UnmodeledSideEffects), 0xb55800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2971 = VFMSUBPSr213mY | |
| { 2972, 3, 1, 0, 0, "VFMSUBPSr213r", 0|(1<<MCID::UnmodeledSideEffects), 0xb55800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2972 = VFMSUBPSr213r | |
| { 2973, 3, 1, 0, 0, "VFMSUBPSr213rY", 0|(1<<MCID::UnmodeledSideEffects), 0xb55800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2973 = VFMSUBPSr213rY | |
| { 2974, 7, 1, 0, 0, "VFMSUBPSr231m", 0|(1<<MCID::UnmodeledSideEffects), 0xb75800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2974 = VFMSUBPSr231m | |
| { 2975, 7, 1, 0, 0, "VFMSUBPSr231mY", 0|(1<<MCID::UnmodeledSideEffects), 0xb75800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2975 = VFMSUBPSr231mY | |
| { 2976, 3, 1, 0, 0, "VFMSUBPSr231r", 0|(1<<MCID::UnmodeledSideEffects), 0xb75800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2976 = VFMSUBPSr231r | |
| { 2977, 3, 1, 0, 0, "VFMSUBPSr231rY", 0|(1<<MCID::UnmodeledSideEffects), 0xb75800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2977 = VFMSUBPSr231rY | |
| { 2978, 7, 1, 0, 0, "VFNMADDPDr132m", 0|(1<<MCID::UnmodeledSideEffects), 0xf39800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2978 = VFNMADDPDr132m | |
| { 2979, 7, 1, 0, 0, "VFNMADDPDr132mY", 0|(1<<MCID::UnmodeledSideEffects), 0xf39800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2979 = VFNMADDPDr132mY | |
| { 2980, 3, 1, 0, 0, "VFNMADDPDr132r", 0|(1<<MCID::UnmodeledSideEffects), 0xf39800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2980 = VFNMADDPDr132r | |
| { 2981, 3, 1, 0, 0, "VFNMADDPDr132rY", 0|(1<<MCID::UnmodeledSideEffects), 0xf39800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2981 = VFNMADDPDr132rY | |
| { 2982, 7, 1, 0, 0, "VFNMADDPDr213m", 0|(1<<MCID::UnmodeledSideEffects), 0xf59800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2982 = VFNMADDPDr213m | |
| { 2983, 7, 1, 0, 0, "VFNMADDPDr213mY", 0|(1<<MCID::UnmodeledSideEffects), 0xf59800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2983 = VFNMADDPDr213mY | |
| { 2984, 3, 1, 0, 0, "VFNMADDPDr213r", 0|(1<<MCID::UnmodeledSideEffects), 0xf59800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2984 = VFNMADDPDr213r | |
| { 2985, 3, 1, 0, 0, "VFNMADDPDr213rY", 0|(1<<MCID::UnmodeledSideEffects), 0xf59800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2985 = VFNMADDPDr213rY | |
| { 2986, 7, 1, 0, 0, "VFNMADDPDr231m", 0|(1<<MCID::UnmodeledSideEffects), 0xf79800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2986 = VFNMADDPDr231m | |
| { 2987, 7, 1, 0, 0, "VFNMADDPDr231mY", 0|(1<<MCID::UnmodeledSideEffects), 0xf79800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2987 = VFNMADDPDr231mY | |
| { 2988, 3, 1, 0, 0, "VFNMADDPDr231r", 0|(1<<MCID::UnmodeledSideEffects), 0xf79800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2988 = VFNMADDPDr231r | |
| { 2989, 3, 1, 0, 0, "VFNMADDPDr231rY", 0|(1<<MCID::UnmodeledSideEffects), 0xf79800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2989 = VFNMADDPDr231rY | |
| { 2990, 7, 1, 0, 0, "VFNMADDPSr132m", 0|(1<<MCID::UnmodeledSideEffects), 0xb39800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2990 = VFNMADDPSr132m | |
| { 2991, 7, 1, 0, 0, "VFNMADDPSr132mY", 0|(1<<MCID::UnmodeledSideEffects), 0xb39800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2991 = VFNMADDPSr132mY | |
| { 2992, 3, 1, 0, 0, "VFNMADDPSr132r", 0|(1<<MCID::UnmodeledSideEffects), 0xb39800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2992 = VFNMADDPSr132r | |
| { 2993, 3, 1, 0, 0, "VFNMADDPSr132rY", 0|(1<<MCID::UnmodeledSideEffects), 0xb39800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2993 = VFNMADDPSr132rY | |
| { 2994, 7, 1, 0, 0, "VFNMADDPSr213m", 0|(1<<MCID::UnmodeledSideEffects), 0xb59800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2994 = VFNMADDPSr213m | |
| { 2995, 7, 1, 0, 0, "VFNMADDPSr213mY", 0|(1<<MCID::UnmodeledSideEffects), 0xb59800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2995 = VFNMADDPSr213mY | |
| { 2996, 3, 1, 0, 0, "VFNMADDPSr213r", 0|(1<<MCID::UnmodeledSideEffects), 0xb59800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #2996 = VFNMADDPSr213r | |
| { 2997, 3, 1, 0, 0, "VFNMADDPSr213rY", 0|(1<<MCID::UnmodeledSideEffects), 0xb59800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #2997 = VFNMADDPSr213rY | |
| { 2998, 7, 1, 0, 0, "VFNMADDPSr231m", 0|(1<<MCID::UnmodeledSideEffects), 0xb79800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #2998 = VFNMADDPSr231m | |
| { 2999, 7, 1, 0, 0, "VFNMADDPSr231mY", 0|(1<<MCID::UnmodeledSideEffects), 0xb79800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #2999 = VFNMADDPSr231mY | |
| { 3000, 3, 1, 0, 0, "VFNMADDPSr231r", 0|(1<<MCID::UnmodeledSideEffects), 0xb79800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3000 = VFNMADDPSr231r | |
| { 3001, 3, 1, 0, 0, "VFNMADDPSr231rY", 0|(1<<MCID::UnmodeledSideEffects), 0xb79800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #3001 = VFNMADDPSr231rY | |
| { 3002, 7, 1, 0, 0, "VFNMSUBPDr132m", 0|(1<<MCID::UnmodeledSideEffects), 0xf3d800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3002 = VFNMSUBPDr132m | |
| { 3003, 7, 1, 0, 0, "VFNMSUBPDr132mY", 0|(1<<MCID::UnmodeledSideEffects), 0xf3d800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #3003 = VFNMSUBPDr132mY | |
| { 3004, 3, 1, 0, 0, "VFNMSUBPDr132r", 0|(1<<MCID::UnmodeledSideEffects), 0xf3d800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3004 = VFNMSUBPDr132r | |
| { 3005, 3, 1, 0, 0, "VFNMSUBPDr132rY", 0|(1<<MCID::UnmodeledSideEffects), 0xf3d800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #3005 = VFNMSUBPDr132rY | |
| { 3006, 7, 1, 0, 0, "VFNMSUBPDr213m", 0|(1<<MCID::UnmodeledSideEffects), 0xf5d800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3006 = VFNMSUBPDr213m | |
| { 3007, 7, 1, 0, 0, "VFNMSUBPDr213mY", 0|(1<<MCID::UnmodeledSideEffects), 0xf5d800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #3007 = VFNMSUBPDr213mY | |
| { 3008, 3, 1, 0, 0, "VFNMSUBPDr213r", 0|(1<<MCID::UnmodeledSideEffects), 0xf5d800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3008 = VFNMSUBPDr213r | |
| { 3009, 3, 1, 0, 0, "VFNMSUBPDr213rY", 0|(1<<MCID::UnmodeledSideEffects), 0xf5d800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #3009 = VFNMSUBPDr213rY | |
| { 3010, 7, 1, 0, 0, "VFNMSUBPDr231m", 0|(1<<MCID::UnmodeledSideEffects), 0xf7d800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3010 = VFNMSUBPDr231m | |
| { 3011, 7, 1, 0, 0, "VFNMSUBPDr231mY", 0|(1<<MCID::UnmodeledSideEffects), 0xf7d800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #3011 = VFNMSUBPDr231mY | |
| { 3012, 3, 1, 0, 0, "VFNMSUBPDr231r", 0|(1<<MCID::UnmodeledSideEffects), 0xf7d800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3012 = VFNMSUBPDr231r | |
| { 3013, 3, 1, 0, 0, "VFNMSUBPDr231rY", 0|(1<<MCID::UnmodeledSideEffects), 0xf7d800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #3013 = VFNMSUBPDr231rY | |
| { 3014, 7, 1, 0, 0, "VFNMSUBPSr132m", 0|(1<<MCID::UnmodeledSideEffects), 0xb3d800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3014 = VFNMSUBPSr132m | |
| { 3015, 7, 1, 0, 0, "VFNMSUBPSr132mY", 0|(1<<MCID::UnmodeledSideEffects), 0xb3d800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #3015 = VFNMSUBPSr132mY | |
| { 3016, 3, 1, 0, 0, "VFNMSUBPSr132r", 0|(1<<MCID::UnmodeledSideEffects), 0xb3d800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3016 = VFNMSUBPSr132r | |
| { 3017, 3, 1, 0, 0, "VFNMSUBPSr132rY", 0|(1<<MCID::UnmodeledSideEffects), 0xb3d800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #3017 = VFNMSUBPSr132rY | |
| { 3018, 7, 1, 0, 0, "VFNMSUBPSr213m", 0|(1<<MCID::UnmodeledSideEffects), 0xb5d800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3018 = VFNMSUBPSr213m | |
| { 3019, 7, 1, 0, 0, "VFNMSUBPSr213mY", 0|(1<<MCID::UnmodeledSideEffects), 0xb5d800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #3019 = VFNMSUBPSr213mY | |
| { 3020, 3, 1, 0, 0, "VFNMSUBPSr213r", 0|(1<<MCID::UnmodeledSideEffects), 0xb5d800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3020 = VFNMSUBPSr213r | |
| { 3021, 3, 1, 0, 0, "VFNMSUBPSr213rY", 0|(1<<MCID::UnmodeledSideEffects), 0xb5d800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #3021 = VFNMSUBPSr213rY | |
| { 3022, 7, 1, 0, 0, "VFNMSUBPSr231m", 0|(1<<MCID::UnmodeledSideEffects), 0xb7d800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3022 = VFNMSUBPSr231m | |
| { 3023, 7, 1, 0, 0, "VFNMSUBPSr231mY", 0|(1<<MCID::UnmodeledSideEffects), 0xb7d800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #3023 = VFNMSUBPSr231mY | |
| { 3024, 3, 1, 0, 0, "VFNMSUBPSr231r", 0|(1<<MCID::UnmodeledSideEffects), 0xb7d800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3024 = VFNMSUBPSr231r | |
| { 3025, 3, 1, 0, 0, "VFNMSUBPSr231rY", 0|(1<<MCID::UnmodeledSideEffects), 0xb7d800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #3025 = VFNMSUBPSr231rY | |
| { 3026, 7, 1, 0, 0, "VFsANDNPDrm", 0|(1<<MCID::MayLoad), 0xaab000146ULL, NULL, NULL, OperandInfo223 }, // Inst #3026 = VFsANDNPDrm | |
| { 3027, 3, 1, 0, 0, "VFsANDNPDrr", 0, 0xaab000145ULL, NULL, NULL, OperandInfo224 }, // Inst #3027 = VFsANDNPDrr | |
| { 3028, 7, 1, 0, 0, "VFsANDNPSrm", 0|(1<<MCID::MayLoad), 0xaaa800106ULL, NULL, NULL, OperandInfo225 }, // Inst #3028 = VFsANDNPSrm | |
| { 3029, 3, 1, 0, 0, "VFsANDNPSrr", 0, 0xaaa800105ULL, NULL, NULL, OperandInfo226 }, // Inst #3029 = VFsANDNPSrr | |
| { 3030, 7, 1, 0, 0, "VFsANDPDrm", 0|(1<<MCID::MayLoad), 0xaa9000146ULL, NULL, NULL, OperandInfo223 }, // Inst #3030 = VFsANDPDrm | |
| { 3031, 3, 1, 0, 0, "VFsANDPDrr", 0|(1<<MCID::Commutable), 0xaa9000145ULL, NULL, NULL, OperandInfo224 }, // Inst #3031 = VFsANDPDrr | |
| { 3032, 7, 1, 0, 0, "VFsANDPSrm", 0|(1<<MCID::MayLoad), 0xaa8800106ULL, NULL, NULL, OperandInfo225 }, // Inst #3032 = VFsANDPSrm | |
| { 3033, 3, 1, 0, 0, "VFsANDPSrr", 0|(1<<MCID::Commutable), 0xaa8800105ULL, NULL, NULL, OperandInfo226 }, // Inst #3033 = VFsANDPSrr | |
| { 3034, 7, 1, 0, 0, "VFsORPDrm", 0|(1<<MCID::MayLoad), 0xaad000146ULL, NULL, NULL, OperandInfo223 }, // Inst #3034 = VFsORPDrm | |
| { 3035, 3, 1, 0, 0, "VFsORPDrr", 0|(1<<MCID::Commutable), 0xaad000145ULL, NULL, NULL, OperandInfo224 }, // Inst #3035 = VFsORPDrr | |
| { 3036, 7, 1, 0, 0, "VFsORPSrm", 0|(1<<MCID::MayLoad), 0xaac800106ULL, NULL, NULL, OperandInfo225 }, // Inst #3036 = VFsORPSrm | |
| { 3037, 3, 1, 0, 0, "VFsORPSrr", 0|(1<<MCID::Commutable), 0xaac800105ULL, NULL, NULL, OperandInfo226 }, // Inst #3037 = VFsORPSrr | |
| { 3038, 7, 1, 0, 0, "VFsXORPDrm", 0|(1<<MCID::MayLoad), 0xaaf000146ULL, NULL, NULL, OperandInfo223 }, // Inst #3038 = VFsXORPDrm | |
| { 3039, 3, 1, 0, 0, "VFsXORPDrr", 0|(1<<MCID::Commutable), 0xaaf000145ULL, NULL, NULL, OperandInfo224 }, // Inst #3039 = VFsXORPDrr | |
| { 3040, 7, 1, 0, 0, "VFsXORPSrm", 0|(1<<MCID::MayLoad), 0xaae800106ULL, NULL, NULL, OperandInfo225 }, // Inst #3040 = VFsXORPSrm | |
| { 3041, 3, 1, 0, 0, "VFsXORPSrr", 0|(1<<MCID::Commutable), 0xaae800105ULL, NULL, NULL, OperandInfo226 }, // Inst #3041 = VFsXORPSrr | |
| { 3042, 7, 1, 0, 0, "VHADDPDYrm", 0|(1<<MCID::MayLoad), 0xaf9000146ULL, NULL, NULL, OperandInfo221 }, // Inst #3042 = VHADDPDYrm | |
| { 3043, 3, 1, 0, 0, "VHADDPDYrr", 0, 0xaf9000145ULL, NULL, NULL, OperandInfo222 }, // Inst #3043 = VHADDPDYrr | |
| { 3044, 7, 1, 0, 0, "VHADDPDrm", 0|(1<<MCID::MayLoad), 0xaf9000146ULL, NULL, NULL, OperandInfo137 }, // Inst #3044 = VHADDPDrm | |
| { 3045, 3, 1, 0, 0, "VHADDPDrr", 0, 0xaf9000145ULL, NULL, NULL, OperandInfo138 }, // Inst #3045 = VHADDPDrr | |
| { 3046, 7, 1, 0, 0, "VHADDPSYrm", 0|(1<<MCID::MayLoad), 0xaf9000b06ULL, NULL, NULL, OperandInfo221 }, // Inst #3046 = VHADDPSYrm | |
| { 3047, 3, 1, 0, 0, "VHADDPSYrr", 0, 0xaf9000b05ULL, NULL, NULL, OperandInfo222 }, // Inst #3047 = VHADDPSYrr | |
| { 3048, 7, 1, 0, 0, "VHADDPSrm", 0|(1<<MCID::MayLoad), 0xaf9000b06ULL, NULL, NULL, OperandInfo137 }, // Inst #3048 = VHADDPSrm | |
| { 3049, 3, 1, 0, 0, "VHADDPSrr", 0, 0xaf9000b05ULL, NULL, NULL, OperandInfo138 }, // Inst #3049 = VHADDPSrr | |
| { 3050, 7, 1, 0, 0, "VHSUBPDYrm", 0|(1<<MCID::MayLoad), 0xafb000146ULL, NULL, NULL, OperandInfo221 }, // Inst #3050 = VHSUBPDYrm | |
| { 3051, 3, 1, 0, 0, "VHSUBPDYrr", 0, 0xafb000145ULL, NULL, NULL, OperandInfo222 }, // Inst #3051 = VHSUBPDYrr | |
| { 3052, 7, 1, 0, 0, "VHSUBPDrm", 0|(1<<MCID::MayLoad), 0xafb000146ULL, NULL, NULL, OperandInfo137 }, // Inst #3052 = VHSUBPDrm | |
| { 3053, 3, 1, 0, 0, "VHSUBPDrr", 0, 0xafb000145ULL, NULL, NULL, OperandInfo138 }, // Inst #3053 = VHSUBPDrr | |
| { 3054, 7, 1, 0, 0, "VHSUBPSYrm", 0|(1<<MCID::MayLoad), 0xafb000b06ULL, NULL, NULL, OperandInfo221 }, // Inst #3054 = VHSUBPSYrm | |
| { 3055, 3, 1, 0, 0, "VHSUBPSYrr", 0, 0xafb000b05ULL, NULL, NULL, OperandInfo222 }, // Inst #3055 = VHSUBPSYrr | |
| { 3056, 7, 1, 0, 0, "VHSUBPSrm", 0|(1<<MCID::MayLoad), 0xafb000b06ULL, NULL, NULL, OperandInfo137 }, // Inst #3056 = VHSUBPSrm | |
| { 3057, 3, 1, 0, 0, "VHSUBPSrr", 0, 0xafb000b05ULL, NULL, NULL, OperandInfo138 }, // Inst #3057 = VHSUBPSrr | |
| { 3058, 8, 1, 0, 0, "VINSERTF128rm", 0|(1<<MCID::UnmodeledSideEffects), 0xa31804e46ULL, NULL, NULL, OperandInfo228 }, // Inst #3058 = VINSERTF128rm | |
| { 3059, 4, 1, 0, 0, "VINSERTF128rr", 0|(1<<MCID::UnmodeledSideEffects), 0xa31804e45ULL, NULL, NULL, OperandInfo249 }, // Inst #3059 = VINSERTF128rr | |
| { 3060, 8, 1, 0, 0, "VINSERTPSrm", 0|(1<<MCID::MayLoad), 0xa43804e46ULL, NULL, NULL, OperandInfo136 }, // Inst #3060 = VINSERTPSrm | |
| { 3061, 4, 1, 0, 0, "VINSERTPSrr", 0, 0xa43804e45ULL, NULL, NULL, OperandInfo86 }, // Inst #3061 = VINSERTPSrr | |
| { 3062, 6, 1, 0, 0, "VLDDQUYrm", 0|(1<<MCID::MayLoad), 0x3e1000b06ULL, NULL, NULL, OperandInfo233 }, // Inst #3062 = VLDDQUYrm | |
| { 3063, 6, 1, 0, 0, "VLDDQUrm", 0|(1<<MCID::MayLoad), 0x3e1000b06ULL, NULL, NULL, OperandInfo47 }, // Inst #3063 = VLDDQUrm | |
| { 3064, 5, 0, 0, 0, "VLDMXCSR", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x35c80011aULL, NULL, NULL, OperandInfo38 }, // Inst #3064 = VLDMXCSR | |
| { 3065, 2, 0, 0, 0, "VMASKMOVDQU", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x3ef800145ULL, ImplicitList34, NULL, OperandInfo48 }, // Inst #3065 = VMASKMOVDQU | |
| { 3066, 2, 0, 0, 0, "VMASKMOVDQU64", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x3ef800145ULL, ImplicitList35, NULL, OperandInfo48 }, // Inst #3066 = VMASKMOVDQU64 | |
| { 3067, 7, 0, 0, 0, "VMASKMOVPDYmr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0xa5f800d44ULL, NULL, NULL, OperandInfo250 }, // Inst #3067 = VMASKMOVPDYmr | |
| { 3068, 7, 1, 0, 0, "VMASKMOVPDYrm", 0|(1<<MCID::MayLoad), 0xa5b800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #3068 = VMASKMOVPDYrm | |
| { 3069, 7, 0, 0, 0, "VMASKMOVPDmr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0xa5f800d44ULL, NULL, NULL, OperandInfo251 }, // Inst #3069 = VMASKMOVPDmr | |
| { 3070, 7, 1, 0, 0, "VMASKMOVPDrm", 0|(1<<MCID::MayLoad), 0xa5b800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3070 = VMASKMOVPDrm | |
| { 3071, 7, 0, 0, 0, "VMASKMOVPSYmr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0xa5d800d44ULL, NULL, NULL, OperandInfo250 }, // Inst #3071 = VMASKMOVPSYmr | |
| { 3072, 7, 1, 0, 0, "VMASKMOVPSYrm", 0|(1<<MCID::MayLoad), 0xa59800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #3072 = VMASKMOVPSYrm | |
| { 3073, 7, 0, 0, 0, "VMASKMOVPSmr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0xa5d800d44ULL, NULL, NULL, OperandInfo251 }, // Inst #3073 = VMASKMOVPSmr | |
| { 3074, 7, 1, 0, 0, "VMASKMOVPSrm", 0|(1<<MCID::MayLoad), 0xa59800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3074 = VMASKMOVPSrm | |
| { 3075, 7, 1, 0, 0, "VMAXPDYrm", 0|(1<<MCID::MayLoad), 0xabf000146ULL, NULL, NULL, OperandInfo221 }, // Inst #3075 = VMAXPDYrm | |
| { 3076, 7, 1, 0, 0, "VMAXPDYrm_Int", 0|(1<<MCID::MayLoad), 0xabf000146ULL, NULL, NULL, OperandInfo221 }, // Inst #3076 = VMAXPDYrm_Int | |
| { 3077, 3, 1, 0, 0, "VMAXPDYrr", 0, 0xabf000145ULL, NULL, NULL, OperandInfo222 }, // Inst #3077 = VMAXPDYrr | |
| { 3078, 3, 1, 0, 0, "VMAXPDYrr_Int", 0, 0xabf000145ULL, NULL, NULL, OperandInfo222 }, // Inst #3078 = VMAXPDYrr_Int | |
| { 3079, 7, 1, 0, 0, "VMAXPDrm", 0|(1<<MCID::MayLoad), 0xabf000146ULL, NULL, NULL, OperandInfo137 }, // Inst #3079 = VMAXPDrm | |
| { 3080, 7, 1, 0, 0, "VMAXPDrm_Int", 0|(1<<MCID::MayLoad), 0xabf000146ULL, NULL, NULL, OperandInfo137 }, // Inst #3080 = VMAXPDrm_Int | |
| { 3081, 3, 1, 0, 0, "VMAXPDrr", 0, 0xabf000145ULL, NULL, NULL, OperandInfo138 }, // Inst #3081 = VMAXPDrr | |
| { 3082, 3, 1, 0, 0, "VMAXPDrr_Int", 0, 0xabf000145ULL, NULL, NULL, OperandInfo138 }, // Inst #3082 = VMAXPDrr_Int | |
| { 3083, 7, 1, 0, 0, "VMAXPSYrm", 0|(1<<MCID::MayLoad), 0xabe800106ULL, NULL, NULL, OperandInfo221 }, // Inst #3083 = VMAXPSYrm | |
| { 3084, 7, 1, 0, 0, "VMAXPSYrm_Int", 0|(1<<MCID::MayLoad), 0xabe800106ULL, NULL, NULL, OperandInfo221 }, // Inst #3084 = VMAXPSYrm_Int | |
| { 3085, 3, 1, 0, 0, "VMAXPSYrr", 0, 0xabe800105ULL, NULL, NULL, OperandInfo222 }, // Inst #3085 = VMAXPSYrr | |
| { 3086, 3, 1, 0, 0, "VMAXPSYrr_Int", 0, 0xabe800105ULL, NULL, NULL, OperandInfo222 }, // Inst #3086 = VMAXPSYrr_Int | |
| { 3087, 7, 1, 0, 0, "VMAXPSrm", 0|(1<<MCID::MayLoad), 0xabe800106ULL, NULL, NULL, OperandInfo137 }, // Inst #3087 = VMAXPSrm | |
| { 3088, 7, 1, 0, 0, "VMAXPSrm_Int", 0|(1<<MCID::MayLoad), 0xabe800106ULL, NULL, NULL, OperandInfo137 }, // Inst #3088 = VMAXPSrm_Int | |
| { 3089, 3, 1, 0, 0, "VMAXPSrr", 0, 0xabe800105ULL, NULL, NULL, OperandInfo138 }, // Inst #3089 = VMAXPSrr | |
| { 3090, 3, 1, 0, 0, "VMAXPSrr_Int", 0, 0xabe800105ULL, NULL, NULL, OperandInfo138 }, // Inst #3090 = VMAXPSrr_Int | |
| { 3091, 7, 1, 0, 0, "VMAXSDrm", 0|(1<<MCID::MayLoad), 0x4abe000b06ULL, NULL, NULL, OperandInfo223 }, // Inst #3091 = VMAXSDrm | |
| { 3092, 7, 1, 0, 0, "VMAXSDrm_Int", 0|(1<<MCID::MayLoad), 0x4abe000b06ULL, NULL, NULL, OperandInfo137 }, // Inst #3092 = VMAXSDrm_Int | |
| { 3093, 3, 1, 0, 0, "VMAXSDrr", 0, 0x4abe000b05ULL, NULL, NULL, OperandInfo224 }, // Inst #3093 = VMAXSDrr | |
| { 3094, 3, 1, 0, 0, "VMAXSDrr_Int", 0, 0x4abe000b05ULL, NULL, NULL, OperandInfo138 }, // Inst #3094 = VMAXSDrr_Int | |
| { 3095, 7, 1, 0, 0, "VMAXSSrm", 0|(1<<MCID::MayLoad), 0x4abe000c06ULL, NULL, NULL, OperandInfo225 }, // Inst #3095 = VMAXSSrm | |
| { 3096, 7, 1, 0, 0, "VMAXSSrm_Int", 0|(1<<MCID::MayLoad), 0x4abe000c06ULL, NULL, NULL, OperandInfo137 }, // Inst #3096 = VMAXSSrm_Int | |
| { 3097, 3, 1, 0, 0, "VMAXSSrr", 0, 0x4abe000c05ULL, NULL, NULL, OperandInfo226 }, // Inst #3097 = VMAXSSrr | |
| { 3098, 3, 1, 0, 0, "VMAXSSrr_Int", 0, 0x4abe000c05ULL, NULL, NULL, OperandInfo138 }, // Inst #3098 = VMAXSSrr_Int | |
| { 3099, 0, 0, 0, 0, "VMCALL", 0|(1<<MCID::UnmodeledSideEffects), 0x2000121ULL, NULL, NULL, 0 }, // Inst #3099 = VMCALL | |
| { 3100, 5, 0, 0, 0, "VMCLEARm", 0|(1<<MCID::UnmodeledSideEffects), 0x18e00015eULL, NULL, NULL, OperandInfo38 }, // Inst #3100 = VMCLEARm | |
| { 3101, 7, 1, 0, 0, "VMINPDYrm", 0|(1<<MCID::MayLoad), 0xabb000146ULL, NULL, NULL, OperandInfo221 }, // Inst #3101 = VMINPDYrm | |
| { 3102, 7, 1, 0, 0, "VMINPDYrm_Int", 0|(1<<MCID::MayLoad), 0xabb000146ULL, NULL, NULL, OperandInfo221 }, // Inst #3102 = VMINPDYrm_Int | |
| { 3103, 3, 1, 0, 0, "VMINPDYrr", 0, 0xabb000145ULL, NULL, NULL, OperandInfo222 }, // Inst #3103 = VMINPDYrr | |
| { 3104, 3, 1, 0, 0, "VMINPDYrr_Int", 0, 0xabb000145ULL, NULL, NULL, OperandInfo222 }, // Inst #3104 = VMINPDYrr_Int | |
| { 3105, 7, 1, 0, 0, "VMINPDrm", 0|(1<<MCID::MayLoad), 0xabb000146ULL, NULL, NULL, OperandInfo137 }, // Inst #3105 = VMINPDrm | |
| { 3106, 7, 1, 0, 0, "VMINPDrm_Int", 0|(1<<MCID::MayLoad), 0xabb000146ULL, NULL, NULL, OperandInfo137 }, // Inst #3106 = VMINPDrm_Int | |
| { 3107, 3, 1, 0, 0, "VMINPDrr", 0, 0xabb000145ULL, NULL, NULL, OperandInfo138 }, // Inst #3107 = VMINPDrr | |
| { 3108, 3, 1, 0, 0, "VMINPDrr_Int", 0, 0xabb000145ULL, NULL, NULL, OperandInfo138 }, // Inst #3108 = VMINPDrr_Int | |
| { 3109, 7, 1, 0, 0, "VMINPSYrm", 0|(1<<MCID::MayLoad), 0xaba800106ULL, NULL, NULL, OperandInfo221 }, // Inst #3109 = VMINPSYrm | |
| { 3110, 7, 1, 0, 0, "VMINPSYrm_Int", 0|(1<<MCID::MayLoad), 0xaba800106ULL, NULL, NULL, OperandInfo221 }, // Inst #3110 = VMINPSYrm_Int | |
| { 3111, 3, 1, 0, 0, "VMINPSYrr", 0, 0xaba800105ULL, NULL, NULL, OperandInfo222 }, // Inst #3111 = VMINPSYrr | |
| { 3112, 3, 1, 0, 0, "VMINPSYrr_Int", 0, 0xaba800105ULL, NULL, NULL, OperandInfo222 }, // Inst #3112 = VMINPSYrr_Int | |
| { 3113, 7, 1, 0, 0, "VMINPSrm", 0|(1<<MCID::MayLoad), 0xaba800106ULL, NULL, NULL, OperandInfo137 }, // Inst #3113 = VMINPSrm | |
| { 3114, 7, 1, 0, 0, "VMINPSrm_Int", 0|(1<<MCID::MayLoad), 0xaba800106ULL, NULL, NULL, OperandInfo137 }, // Inst #3114 = VMINPSrm_Int | |
| { 3115, 3, 1, 0, 0, "VMINPSrr", 0, 0xaba800105ULL, NULL, NULL, OperandInfo138 }, // Inst #3115 = VMINPSrr | |
| { 3116, 3, 1, 0, 0, "VMINPSrr_Int", 0, 0xaba800105ULL, NULL, NULL, OperandInfo138 }, // Inst #3116 = VMINPSrr_Int | |
| { 3117, 7, 1, 0, 0, "VMINSDrm", 0|(1<<MCID::MayLoad), 0x4aba000b06ULL, NULL, NULL, OperandInfo223 }, // Inst #3117 = VMINSDrm | |
| { 3118, 7, 1, 0, 0, "VMINSDrm_Int", 0|(1<<MCID::MayLoad), 0x4aba000b06ULL, NULL, NULL, OperandInfo137 }, // Inst #3118 = VMINSDrm_Int | |
| { 3119, 3, 1, 0, 0, "VMINSDrr", 0, 0x4aba000b05ULL, NULL, NULL, OperandInfo224 }, // Inst #3119 = VMINSDrr | |
| { 3120, 3, 1, 0, 0, "VMINSDrr_Int", 0, 0x4aba000b05ULL, NULL, NULL, OperandInfo138 }, // Inst #3120 = VMINSDrr_Int | |
| { 3121, 7, 1, 0, 0, "VMINSSrm", 0|(1<<MCID::MayLoad), 0x4aba000c06ULL, NULL, NULL, OperandInfo225 }, // Inst #3121 = VMINSSrm | |
| { 3122, 7, 1, 0, 0, "VMINSSrm_Int", 0|(1<<MCID::MayLoad), 0x4aba000c06ULL, NULL, NULL, OperandInfo137 }, // Inst #3122 = VMINSSrm_Int | |
| { 3123, 3, 1, 0, 0, "VMINSSrr", 0, 0x4aba000c05ULL, NULL, NULL, OperandInfo226 }, // Inst #3123 = VMINSSrr | |
| { 3124, 3, 1, 0, 0, "VMINSSrr_Int", 0, 0x4aba000c05ULL, NULL, NULL, OperandInfo138 }, // Inst #3124 = VMINSSrr_Int | |
| { 3125, 0, 0, 0, 0, "VMLAUNCH", 0|(1<<MCID::UnmodeledSideEffects), 0x2000122ULL, NULL, NULL, 0 }, // Inst #3125 = VMLAUNCH | |
| { 3126, 2, 1, 0, 0, "VMOV64toPQIrr", 0, 0x6dd000145ULL, NULL, NULL, OperandInfo183 }, // Inst #3126 = VMOV64toPQIrr | |
| { 3127, 6, 1, 0, 0, "VMOV64toSDrm", 0|(1<<MCID::MayLoad), 0x2fc800c06ULL, NULL, NULL, OperandInfo101 }, // Inst #3127 = VMOV64toSDrm | |
| { 3128, 2, 1, 0, 0, "VMOV64toSDrr", 0|(1<<MCID::Bitcast), 0x6dd000145ULL, NULL, NULL, OperandInfo102 }, // Inst #3128 = VMOV64toSDrr | |
| { 3129, 6, 0, 0, 0, "VMOVAPDYmr", 0|(1<<MCID::MayStore), 0x253000144ULL, NULL, NULL, OperandInfo252 }, // Inst #3129 = VMOVAPDYmr | |
| { 3130, 6, 1, 0, 0, "VMOVAPDYrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x251000146ULL, NULL, NULL, OperandInfo233 }, // Inst #3130 = VMOVAPDYrm | |
| { 3131, 2, 1, 0, 0, "VMOVAPDYrr", 0, 0x251000145ULL, NULL, NULL, OperandInfo237 }, // Inst #3131 = VMOVAPDYrr | |
| { 3132, 2, 1, 0, 0, "VMOVAPDYrr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x253000143ULL, NULL, NULL, OperandInfo237 }, // Inst #3132 = VMOVAPDYrr_REV | |
| { 3133, 6, 0, 0, 0, "VMOVAPDmr", 0|(1<<MCID::MayStore), 0x253000144ULL, NULL, NULL, OperandInfo187 }, // Inst #3133 = VMOVAPDmr | |
| { 3134, 6, 1, 0, 0, "VMOVAPDrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x251000146ULL, NULL, NULL, OperandInfo47 }, // Inst #3134 = VMOVAPDrm | |
| { 3135, 2, 1, 0, 0, "VMOVAPDrr", 0, 0x251000145ULL, NULL, NULL, OperandInfo48 }, // Inst #3135 = VMOVAPDrr | |
| { 3136, 2, 1, 0, 0, "VMOVAPDrr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x253000143ULL, NULL, NULL, OperandInfo48 }, // Inst #3136 = VMOVAPDrr_REV | |
| { 3137, 6, 0, 0, 0, "VMOVAPSYmr", 0|(1<<MCID::MayStore), 0x252800104ULL, NULL, NULL, OperandInfo252 }, // Inst #3137 = VMOVAPSYmr | |
| { 3138, 6, 1, 0, 0, "VMOVAPSYrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x250800106ULL, NULL, NULL, OperandInfo233 }, // Inst #3138 = VMOVAPSYrm | |
| { 3139, 2, 1, 0, 0, "VMOVAPSYrr", 0, 0x250800105ULL, NULL, NULL, OperandInfo237 }, // Inst #3139 = VMOVAPSYrr | |
| { 3140, 2, 1, 0, 0, "VMOVAPSYrr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x252800103ULL, NULL, NULL, OperandInfo237 }, // Inst #3140 = VMOVAPSYrr_REV | |
| { 3141, 6, 0, 0, 0, "VMOVAPSmr", 0|(1<<MCID::MayStore), 0x252800104ULL, NULL, NULL, OperandInfo187 }, // Inst #3141 = VMOVAPSmr | |
| { 3142, 6, 1, 0, 0, "VMOVAPSrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x250800106ULL, NULL, NULL, OperandInfo47 }, // Inst #3142 = VMOVAPSrm | |
| { 3143, 2, 1, 0, 0, "VMOVAPSrr", 0, 0x250800105ULL, NULL, NULL, OperandInfo48 }, // Inst #3143 = VMOVAPSrr | |
| { 3144, 2, 1, 0, 0, "VMOVAPSrr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x252800103ULL, NULL, NULL, OperandInfo48 }, // Inst #3144 = VMOVAPSrr_REV | |
| { 3145, 6, 1, 0, 0, "VMOVDDUPYrm", 0|(1<<MCID::UnmodeledSideEffects), 0x225000b06ULL, NULL, NULL, OperandInfo233 }, // Inst #3145 = VMOVDDUPYrm | |
| { 3146, 2, 1, 0, 0, "VMOVDDUPYrr", 0|(1<<MCID::UnmodeledSideEffects), 0x225000b05ULL, NULL, NULL, OperandInfo237 }, // Inst #3146 = VMOVDDUPYrr | |
| { 3147, 6, 1, 0, 0, "VMOVDDUPrm", 0|(1<<MCID::MayLoad), 0x225000b06ULL, NULL, NULL, OperandInfo47 }, // Inst #3147 = VMOVDDUPrm | |
| { 3148, 2, 1, 0, 0, "VMOVDDUPrr", 0, 0x225000b05ULL, NULL, NULL, OperandInfo48 }, // Inst #3148 = VMOVDDUPrr | |
| { 3149, 6, 1, 0, 0, "VMOVDI2PDIrm", 0|(1<<MCID::MayLoad), 0x2dd000146ULL, NULL, NULL, OperandInfo47 }, // Inst #3149 = VMOVDI2PDIrm | |
| { 3150, 2, 1, 0, 0, "VMOVDI2PDIrr", 0, 0x2dd000145ULL, NULL, NULL, OperandInfo188 }, // Inst #3150 = VMOVDI2PDIrr | |
| { 3151, 6, 1, 0, 0, "VMOVDI2SSrm", 0|(1<<MCID::MayLoad), 0x2dd000146ULL, NULL, NULL, OperandInfo99 }, // Inst #3151 = VMOVDI2SSrm | |
| { 3152, 2, 1, 0, 0, "VMOVDI2SSrr", 0|(1<<MCID::Bitcast), 0x2dd000145ULL, NULL, NULL, OperandInfo105 }, // Inst #3152 = VMOVDI2SSrr | |
| { 3153, 6, 0, 0, 0, "VMOVDQAYmr", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x2ff800144ULL, NULL, NULL, OperandInfo252 }, // Inst #3153 = VMOVDQAYmr | |
| { 3154, 6, 1, 0, 0, "VMOVDQAYrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x2df800146ULL, NULL, NULL, OperandInfo233 }, // Inst #3154 = VMOVDQAYrm | |
| { 3155, 2, 1, 0, 0, "VMOVDQAYrr", 0, 0x2df800145ULL, NULL, NULL, OperandInfo237 }, // Inst #3155 = VMOVDQAYrr | |
| { 3156, 2, 1, 0, 0, "VMOVDQAYrr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x2ff800143ULL, NULL, NULL, OperandInfo237 }, // Inst #3156 = VMOVDQAYrr_REV | |
| { 3157, 6, 0, 0, 0, "VMOVDQAmr", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x2ff800144ULL, NULL, NULL, OperandInfo187 }, // Inst #3157 = VMOVDQAmr | |
| { 3158, 6, 1, 0, 0, "VMOVDQArm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x2df800146ULL, NULL, NULL, OperandInfo47 }, // Inst #3158 = VMOVDQArm | |
| { 3159, 2, 1, 0, 0, "VMOVDQArr", 0, 0x2df800145ULL, NULL, NULL, OperandInfo48 }, // Inst #3159 = VMOVDQArr | |
| { 3160, 2, 1, 0, 0, "VMOVDQArr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x2ff800143ULL, NULL, NULL, OperandInfo48 }, // Inst #3160 = VMOVDQArr_REV | |
| { 3161, 6, 0, 0, 0, "VMOVDQUYmr", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x2ff800c04ULL, NULL, NULL, OperandInfo252 }, // Inst #3161 = VMOVDQUYmr | |
| { 3162, 6, 1, 0, 0, "VMOVDQUYrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x2df800c06ULL, NULL, NULL, OperandInfo233 }, // Inst #3162 = VMOVDQUYrm | |
| { 3163, 2, 1, 0, 0, "VMOVDQUYrr", 0|(1<<MCID::UnmodeledSideEffects), 0x2df800c05ULL, NULL, NULL, OperandInfo237 }, // Inst #3163 = VMOVDQUYrr | |
| { 3164, 2, 1, 0, 0, "VMOVDQUYrr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x2ff800c03ULL, NULL, NULL, OperandInfo237 }, // Inst #3164 = VMOVDQUYrr_REV | |
| { 3165, 6, 0, 0, 0, "VMOVDQUmr", 0|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x2ff800c04ULL, NULL, NULL, OperandInfo187 }, // Inst #3165 = VMOVDQUmr | |
| { 3166, 6, 0, 0, 0, "VMOVDQUmr_Int", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x2ff800c04ULL, NULL, NULL, OperandInfo187 }, // Inst #3166 = VMOVDQUmr_Int | |
| { 3167, 6, 1, 0, 0, "VMOVDQUrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x2df800c06ULL, NULL, NULL, OperandInfo47 }, // Inst #3167 = VMOVDQUrm | |
| { 3168, 2, 1, 0, 0, "VMOVDQUrr", 0|(1<<MCID::UnmodeledSideEffects), 0x2df800c05ULL, NULL, NULL, OperandInfo48 }, // Inst #3168 = VMOVDQUrr | |
| { 3169, 2, 1, 0, 0, "VMOVDQUrr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x2ff800c03ULL, NULL, NULL, OperandInfo48 }, // Inst #3169 = VMOVDQUrr_REV | |
| { 3170, 3, 1, 0, 0, "VMOVHLPSrr", 0, 0xa24800105ULL, NULL, NULL, OperandInfo138 }, // Inst #3170 = VMOVHLPSrr | |
| { 3171, 6, 0, 0, 0, "VMOVHPDmr", 0|(1<<MCID::MayStore), 0x22f000144ULL, NULL, NULL, OperandInfo187 }, // Inst #3171 = VMOVHPDmr | |
| { 3172, 7, 1, 0, 0, "VMOVHPDrm", 0|(1<<MCID::MayLoad), 0xa2d000146ULL, NULL, NULL, OperandInfo137 }, // Inst #3172 = VMOVHPDrm | |
| { 3173, 6, 0, 0, 0, "VMOVHPSmr", 0|(1<<MCID::MayStore), 0x22e800104ULL, NULL, NULL, OperandInfo187 }, // Inst #3173 = VMOVHPSmr | |
| { 3174, 7, 1, 0, 0, "VMOVHPSrm", 0|(1<<MCID::MayLoad), 0xa2c800106ULL, NULL, NULL, OperandInfo137 }, // Inst #3174 = VMOVHPSrm | |
| { 3175, 3, 1, 0, 0, "VMOVLHPSrr", 0, 0xa2c800105ULL, NULL, NULL, OperandInfo138 }, // Inst #3175 = VMOVLHPSrr | |
| { 3176, 6, 0, 0, 0, "VMOVLPDmr", 0|(1<<MCID::MayStore), 0x227000144ULL, NULL, NULL, OperandInfo187 }, // Inst #3176 = VMOVLPDmr | |
| { 3177, 7, 1, 0, 0, "VMOVLPDrm", 0|(1<<MCID::MayLoad), 0xa25000146ULL, NULL, NULL, OperandInfo137 }, // Inst #3177 = VMOVLPDrm | |
| { 3178, 6, 0, 0, 0, "VMOVLPSmr", 0|(1<<MCID::MayStore), 0x226800104ULL, NULL, NULL, OperandInfo187 }, // Inst #3178 = VMOVLPSmr | |
| { 3179, 7, 1, 0, 0, "VMOVLPSrm", 0|(1<<MCID::MayLoad), 0xa24800106ULL, NULL, NULL, OperandInfo137 }, // Inst #3179 = VMOVLPSrm | |
| { 3180, 6, 0, 0, 0, "VMOVLQ128mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x3ad000144ULL, NULL, NULL, OperandInfo187 }, // Inst #3180 = VMOVLQ128mr | |
| { 3181, 2, 1, 0, 0, "VMOVMSKPDYr64r", 0|(1<<MCID::UnmodeledSideEffects), 0x2a1000145ULL, NULL, NULL, OperandInfo253 }, // Inst #3181 = VMOVMSKPDYr64r | |
| { 3182, 2, 1, 0, 0, "VMOVMSKPDYrr32", 0, 0x2a1000145ULL, NULL, NULL, OperandInfo254 }, // Inst #3182 = VMOVMSKPDYrr32 | |
| { 3183, 2, 1, 0, 0, "VMOVMSKPDYrr64", 0|(1<<MCID::UnmodeledSideEffects), 0x2a1002145ULL, NULL, NULL, OperandInfo253 }, // Inst #3183 = VMOVMSKPDYrr64 | |
| { 3184, 2, 1, 0, 0, "VMOVMSKPDr64r", 0|(1<<MCID::UnmodeledSideEffects), 0x2a1000145ULL, NULL, NULL, OperandInfo97 }, // Inst #3184 = VMOVMSKPDr64r | |
| { 3185, 2, 1, 0, 0, "VMOVMSKPDrr32", 0, 0x2a1000145ULL, NULL, NULL, OperandInfo98 }, // Inst #3185 = VMOVMSKPDrr32 | |
| { 3186, 2, 1, 0, 0, "VMOVMSKPDrr64", 0|(1<<MCID::UnmodeledSideEffects), 0x2a1002145ULL, NULL, NULL, OperandInfo97 }, // Inst #3186 = VMOVMSKPDrr64 | |
| { 3187, 2, 1, 0, 0, "VMOVMSKPSYr64r", 0|(1<<MCID::UnmodeledSideEffects), 0x2a0800105ULL, NULL, NULL, OperandInfo253 }, // Inst #3187 = VMOVMSKPSYr64r | |
| { 3188, 2, 1, 0, 0, "VMOVMSKPSYrr32", 0, 0x2a0800105ULL, NULL, NULL, OperandInfo254 }, // Inst #3188 = VMOVMSKPSYrr32 | |
| { 3189, 2, 1, 0, 0, "VMOVMSKPSYrr64", 0|(1<<MCID::UnmodeledSideEffects), 0x2a0802105ULL, NULL, NULL, OperandInfo253 }, // Inst #3189 = VMOVMSKPSYrr64 | |
| { 3190, 2, 1, 0, 0, "VMOVMSKPSr64r", 0|(1<<MCID::UnmodeledSideEffects), 0x2a0800105ULL, NULL, NULL, OperandInfo97 }, // Inst #3190 = VMOVMSKPSr64r | |
| { 3191, 2, 1, 0, 0, "VMOVMSKPSrr32", 0, 0x2a0800105ULL, NULL, NULL, OperandInfo98 }, // Inst #3191 = VMOVMSKPSrr32 | |
| { 3192, 2, 1, 0, 0, "VMOVMSKPSrr64", 0|(1<<MCID::UnmodeledSideEffects), 0x2a0802105ULL, NULL, NULL, OperandInfo97 }, // Inst #3192 = VMOVMSKPSrr64 | |
| { 3193, 6, 1, 0, 0, "VMOVNTDQArm", 0|(1<<MCID::MayLoad), 0x255800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #3193 = VMOVNTDQArm | |
| { 3194, 6, 0, 0, 0, "VMOVNTDQY_64mr", 0|(1<<MCID::MayStore), 0x3cf000144ULL, NULL, NULL, OperandInfo252 }, // Inst #3194 = VMOVNTDQY_64mr | |
| { 3195, 6, 0, 0, 0, "VMOVNTDQYmr", 0|(1<<MCID::MayStore), 0x3cf800144ULL, NULL, NULL, OperandInfo252 }, // Inst #3195 = VMOVNTDQYmr | |
| { 3196, 6, 0, 0, 0, "VMOVNTDQ_64mr", 0|(1<<MCID::MayStore), 0x3cf000144ULL, NULL, NULL, OperandInfo187 }, // Inst #3196 = VMOVNTDQ_64mr | |
| { 3197, 6, 0, 0, 0, "VMOVNTDQmr", 0|(1<<MCID::MayStore), 0x3cf800144ULL, NULL, NULL, OperandInfo187 }, // Inst #3197 = VMOVNTDQmr | |
| { 3198, 6, 0, 0, 0, "VMOVNTPDYmr", 0|(1<<MCID::MayStore), 0x257000144ULL, NULL, NULL, OperandInfo252 }, // Inst #3198 = VMOVNTPDYmr | |
| { 3199, 6, 0, 0, 0, "VMOVNTPDmr", 0|(1<<MCID::MayStore), 0x257000144ULL, NULL, NULL, OperandInfo187 }, // Inst #3199 = VMOVNTPDmr | |
| { 3200, 6, 0, 0, 0, "VMOVNTPSYmr", 0|(1<<MCID::MayStore), 0x256800104ULL, NULL, NULL, OperandInfo252 }, // Inst #3200 = VMOVNTPSYmr | |
| { 3201, 6, 0, 0, 0, "VMOVNTPSmr", 0|(1<<MCID::MayStore), 0x256800104ULL, NULL, NULL, OperandInfo187 }, // Inst #3201 = VMOVNTPSmr | |
| { 3202, 6, 0, 0, 0, "VMOVPDI2DImr", 0|(1<<MCID::MayStore), 0x2fd000144ULL, NULL, NULL, OperandInfo187 }, // Inst #3202 = VMOVPDI2DImr | |
| { 3203, 2, 1, 0, 0, "VMOVPDI2DIrr", 0, 0x2fd000143ULL, NULL, NULL, OperandInfo98 }, // Inst #3203 = VMOVPDI2DIrr | |
| { 3204, 6, 0, 0, 0, "VMOVPQI2QImr", 0|(1<<MCID::MayStore), 0x3ad000144ULL, NULL, NULL, OperandInfo187 }, // Inst #3204 = VMOVPQI2QImr | |
| { 3205, 2, 1, 0, 0, "VMOVPQIto64rr", 0, 0x6fc000143ULL, NULL, NULL, OperandInfo97 }, // Inst #3205 = VMOVPQIto64rr | |
| { 3206, 6, 1, 0, 0, "VMOVQI2PQIrm", 0|(1<<MCID::MayLoad), 0x2fc000c06ULL, NULL, NULL, OperandInfo47 }, // Inst #3206 = VMOVQI2PQIrm | |
| { 3207, 2, 1, 0, 0, "VMOVQd64rr", 0|(1<<MCID::UnmodeledSideEffects), 0x6fd000143ULL, NULL, NULL, OperandInfo97 }, // Inst #3207 = VMOVQd64rr | |
| { 3208, 2, 1, 0, 0, "VMOVQd64rr_alt", 0|(1<<MCID::UnmodeledSideEffects), 0x6fd000143ULL, NULL, NULL, OperandInfo97 }, // Inst #3208 = VMOVQd64rr_alt | |
| { 3209, 2, 1, 0, 0, "VMOVQs64rr", 0|(1<<MCID::UnmodeledSideEffects), 0x6dd000145ULL, NULL, NULL, OperandInfo183 }, // Inst #3209 = VMOVQs64rr | |
| { 3210, 2, 1, 0, 0, "VMOVQxrxr", 0|(1<<MCID::UnmodeledSideEffects), 0x2fc000c05ULL, NULL, NULL, OperandInfo48 }, // Inst #3210 = VMOVQxrxr | |
| { 3211, 6, 0, 0, 0, "VMOVSDmr", 0|(1<<MCID::MayStore), 0x4222000b04ULL, NULL, NULL, OperandInfo189 }, // Inst #3211 = VMOVSDmr | |
| { 3212, 6, 1, 0, 0, "VMOVSDrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x4220000b06ULL, NULL, NULL, OperandInfo101 }, // Inst #3212 = VMOVSDrm | |
| { 3213, 3, 1, 0, 0, "VMOVSDrr", 0, 0x4a20000b05ULL, NULL, NULL, OperandInfo255 }, // Inst #3213 = VMOVSDrr | |
| { 3214, 3, 1, 0, 0, "VMOVSDrr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x4a22000b03ULL, NULL, NULL, OperandInfo255 }, // Inst #3214 = VMOVSDrr_REV | |
| { 3215, 6, 0, 0, 0, "VMOVSDto64mr", 0|(1<<MCID::MayStore), 0x4fd000144ULL, NULL, NULL, OperandInfo189 }, // Inst #3215 = VMOVSDto64mr | |
| { 3216, 2, 1, 0, 0, "VMOVSDto64rr", 0|(1<<MCID::Bitcast), 0x4fd000143ULL, NULL, NULL, OperandInfo109 }, // Inst #3216 = VMOVSDto64rr | |
| { 3217, 6, 1, 0, 0, "VMOVSHDUPYrm", 0|(1<<MCID::MayLoad), 0x22c800c06ULL, NULL, NULL, OperandInfo233 }, // Inst #3217 = VMOVSHDUPYrm | |
| { 3218, 2, 1, 0, 0, "VMOVSHDUPYrr", 0, 0x22c800c05ULL, NULL, NULL, OperandInfo237 }, // Inst #3218 = VMOVSHDUPYrr | |
| { 3219, 6, 1, 0, 0, "VMOVSHDUPrm", 0|(1<<MCID::MayLoad), 0x22c800c06ULL, NULL, NULL, OperandInfo47 }, // Inst #3219 = VMOVSHDUPrm | |
| { 3220, 2, 1, 0, 0, "VMOVSHDUPrr", 0, 0x22c800c05ULL, NULL, NULL, OperandInfo48 }, // Inst #3220 = VMOVSHDUPrr | |
| { 3221, 6, 1, 0, 0, "VMOVSLDUPYrm", 0|(1<<MCID::MayLoad), 0x224800c06ULL, NULL, NULL, OperandInfo233 }, // Inst #3221 = VMOVSLDUPYrm | |
| { 3222, 2, 1, 0, 0, "VMOVSLDUPYrr", 0, 0x224800c05ULL, NULL, NULL, OperandInfo237 }, // Inst #3222 = VMOVSLDUPYrr | |
| { 3223, 6, 1, 0, 0, "VMOVSLDUPrm", 0|(1<<MCID::MayLoad), 0x224800c06ULL, NULL, NULL, OperandInfo47 }, // Inst #3223 = VMOVSLDUPrm | |
| { 3224, 2, 1, 0, 0, "VMOVSLDUPrr", 0, 0x224800c05ULL, NULL, NULL, OperandInfo48 }, // Inst #3224 = VMOVSLDUPrr | |
| { 3225, 6, 0, 0, 0, "VMOVSS2DImr", 0|(1<<MCID::MayStore), 0x2fd000144ULL, NULL, NULL, OperandInfo191 }, // Inst #3225 = VMOVSS2DImr | |
| { 3226, 2, 1, 0, 0, "VMOVSS2DIrr", 0|(1<<MCID::Bitcast), 0x2fd000143ULL, NULL, NULL, OperandInfo108 }, // Inst #3226 = VMOVSS2DIrr | |
| { 3227, 6, 0, 0, 0, "VMOVSSmr", 0|(1<<MCID::MayStore), 0x4222000c04ULL, NULL, NULL, OperandInfo191 }, // Inst #3227 = VMOVSSmr | |
| { 3228, 6, 1, 0, 0, "VMOVSSrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x4220000c06ULL, NULL, NULL, OperandInfo99 }, // Inst #3228 = VMOVSSrm | |
| { 3229, 3, 1, 0, 0, "VMOVSSrr", 0, 0x4a20000c05ULL, NULL, NULL, OperandInfo256 }, // Inst #3229 = VMOVSSrr | |
| { 3230, 3, 1, 0, 0, "VMOVSSrr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x4a22000c03ULL, NULL, NULL, OperandInfo256 }, // Inst #3230 = VMOVSSrr_REV | |
| { 3231, 6, 0, 0, 0, "VMOVUPDYmr", 0|(1<<MCID::MayStore), 0x223000144ULL, NULL, NULL, OperandInfo252 }, // Inst #3231 = VMOVUPDYmr | |
| { 3232, 6, 1, 0, 0, "VMOVUPDYrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad), 0x221000146ULL, NULL, NULL, OperandInfo233 }, // Inst #3232 = VMOVUPDYrm | |
| { 3233, 2, 1, 0, 0, "VMOVUPDYrr", 0, 0x221000145ULL, NULL, NULL, OperandInfo237 }, // Inst #3233 = VMOVUPDYrr | |
| { 3234, 2, 1, 0, 0, "VMOVUPDYrr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x223000143ULL, NULL, NULL, OperandInfo237 }, // Inst #3234 = VMOVUPDYrr_REV | |
| { 3235, 6, 0, 0, 0, "VMOVUPDmr", 0|(1<<MCID::MayStore), 0x223000144ULL, NULL, NULL, OperandInfo187 }, // Inst #3235 = VMOVUPDmr | |
| { 3236, 6, 1, 0, 0, "VMOVUPDrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad), 0x221000146ULL, NULL, NULL, OperandInfo47 }, // Inst #3236 = VMOVUPDrm | |
| { 3237, 2, 1, 0, 0, "VMOVUPDrr", 0, 0x221000145ULL, NULL, NULL, OperandInfo48 }, // Inst #3237 = VMOVUPDrr | |
| { 3238, 2, 1, 0, 0, "VMOVUPDrr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x223000143ULL, NULL, NULL, OperandInfo48 }, // Inst #3238 = VMOVUPDrr_REV | |
| { 3239, 6, 0, 0, 0, "VMOVUPSYmr", 0|(1<<MCID::MayStore), 0x222800104ULL, NULL, NULL, OperandInfo252 }, // Inst #3239 = VMOVUPSYmr | |
| { 3240, 6, 1, 0, 0, "VMOVUPSYrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x220800106ULL, NULL, NULL, OperandInfo233 }, // Inst #3240 = VMOVUPSYrm | |
| { 3241, 2, 1, 0, 0, "VMOVUPSYrr", 0, 0x220800105ULL, NULL, NULL, OperandInfo237 }, // Inst #3241 = VMOVUPSYrr | |
| { 3242, 2, 1, 0, 0, "VMOVUPSYrr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x222800103ULL, NULL, NULL, OperandInfo237 }, // Inst #3242 = VMOVUPSYrr_REV | |
| { 3243, 6, 0, 0, 0, "VMOVUPSmr", 0|(1<<MCID::MayStore), 0x222800104ULL, NULL, NULL, OperandInfo187 }, // Inst #3243 = VMOVUPSmr | |
| { 3244, 6, 1, 0, 0, "VMOVUPSrm", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::MayLoad)|(1<<MCID::Rematerializable), 0x220800106ULL, NULL, NULL, OperandInfo47 }, // Inst #3244 = VMOVUPSrm | |
| { 3245, 2, 1, 0, 0, "VMOVUPSrr", 0, 0x220800105ULL, NULL, NULL, OperandInfo48 }, // Inst #3245 = VMOVUPSrr | |
| { 3246, 2, 1, 0, 0, "VMOVUPSrr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x222800103ULL, NULL, NULL, OperandInfo48 }, // Inst #3246 = VMOVUPSrr_REV | |
| { 3247, 6, 1, 0, 0, "VMOVZDI2PDIrm", 0|(1<<MCID::MayLoad), 0x2dd000146ULL, NULL, NULL, OperandInfo47 }, // Inst #3247 = VMOVZDI2PDIrm | |
| { 3248, 2, 1, 0, 0, "VMOVZDI2PDIrr", 0, 0x2dd000145ULL, NULL, NULL, OperandInfo188 }, // Inst #3248 = VMOVZDI2PDIrr | |
| { 3249, 6, 1, 0, 0, "VMOVZPQILo2PQIrm", 0|(1<<MCID::MayLoad), 0x2fc000c06ULL, NULL, NULL, OperandInfo47 }, // Inst #3249 = VMOVZPQILo2PQIrm | |
| { 3250, 2, 1, 0, 0, "VMOVZPQILo2PQIrr", 0, 0x2fc000c05ULL, NULL, NULL, OperandInfo48 }, // Inst #3250 = VMOVZPQILo2PQIrr | |
| { 3251, 6, 1, 0, 0, "VMOVZQI2PQIrm", 0|(1<<MCID::MayLoad), 0x2fc000c06ULL, NULL, NULL, OperandInfo47 }, // Inst #3251 = VMOVZQI2PQIrm | |
| { 3252, 2, 1, 0, 0, "VMOVZQI2PQIrr", 0, 0x6dd000145ULL, NULL, NULL, OperandInfo183 }, // Inst #3252 = VMOVZQI2PQIrr | |
| { 3253, 8, 1, 0, 0, "VMPSADBWrmi", 0|(1<<MCID::MayLoad), 0xa85804e46ULL, NULL, NULL, OperandInfo136 }, // Inst #3253 = VMPSADBWrmi | |
| { 3254, 4, 1, 0, 0, "VMPSADBWrri", 0, 0xa85804e45ULL, NULL, NULL, OperandInfo86 }, // Inst #3254 = VMPSADBWrri | |
| { 3255, 5, 0, 0, 0, "VMPTRLDm", 0|(1<<MCID::UnmodeledSideEffects), 0x18e00011eULL, NULL, NULL, OperandInfo38 }, // Inst #3255 = VMPTRLDm | |
| { 3256, 5, 1, 0, 0, "VMPTRSTm", 0|(1<<MCID::UnmodeledSideEffects), 0x18e00011fULL, NULL, NULL, OperandInfo38 }, // Inst #3256 = VMPTRSTm | |
| { 3257, 6, 1, 0, 0, "VMREAD32rm", 0|(1<<MCID::UnmodeledSideEffects), 0xf0000104ULL, NULL, NULL, OperandInfo20 }, // Inst #3257 = VMREAD32rm | |
| { 3258, 2, 1, 0, 0, "VMREAD32rr", 0|(1<<MCID::UnmodeledSideEffects), 0xf0000103ULL, NULL, NULL, OperandInfo65 }, // Inst #3258 = VMREAD32rr | |
| { 3259, 6, 1, 0, 0, "VMREAD64rm", 0|(1<<MCID::UnmodeledSideEffects), 0xf0000104ULL, NULL, NULL, OperandInfo24 }, // Inst #3259 = VMREAD64rm | |
| { 3260, 2, 1, 0, 0, "VMREAD64rr", 0|(1<<MCID::UnmodeledSideEffects), 0xf0000103ULL, NULL, NULL, OperandInfo66 }, // Inst #3260 = VMREAD64rr | |
| { 3261, 0, 0, 0, 0, "VMRESUME", 0|(1<<MCID::UnmodeledSideEffects), 0x2000123ULL, NULL, NULL, 0 }, // Inst #3261 = VMRESUME | |
| { 3262, 7, 1, 0, 0, "VMULPDYrm", 0|(1<<MCID::MayLoad), 0xab3000146ULL, NULL, NULL, OperandInfo221 }, // Inst #3262 = VMULPDYrm | |
| { 3263, 3, 1, 0, 0, "VMULPDYrr", 0|(1<<MCID::Commutable), 0xab3000145ULL, NULL, NULL, OperandInfo222 }, // Inst #3263 = VMULPDYrr | |
| { 3264, 7, 1, 0, 0, "VMULPDrm", 0|(1<<MCID::MayLoad), 0xab3000146ULL, NULL, NULL, OperandInfo137 }, // Inst #3264 = VMULPDrm | |
| { 3265, 3, 1, 0, 0, "VMULPDrr", 0|(1<<MCID::Commutable), 0xab3000145ULL, NULL, NULL, OperandInfo138 }, // Inst #3265 = VMULPDrr | |
| { 3266, 7, 1, 0, 0, "VMULPSYrm", 0|(1<<MCID::MayLoad), 0xab2800106ULL, NULL, NULL, OperandInfo221 }, // Inst #3266 = VMULPSYrm | |
| { 3267, 3, 1, 0, 0, "VMULPSYrr", 0|(1<<MCID::Commutable), 0xab2800105ULL, NULL, NULL, OperandInfo222 }, // Inst #3267 = VMULPSYrr | |
| { 3268, 7, 1, 0, 0, "VMULPSrm", 0|(1<<MCID::MayLoad), 0xab2800106ULL, NULL, NULL, OperandInfo137 }, // Inst #3268 = VMULPSrm | |
| { 3269, 3, 1, 0, 0, "VMULPSrr", 0|(1<<MCID::Commutable), 0xab2800105ULL, NULL, NULL, OperandInfo138 }, // Inst #3269 = VMULPSrr | |
| { 3270, 7, 1, 0, 0, "VMULSDrm", 0|(1<<MCID::MayLoad), 0x4ab2000b06ULL, NULL, NULL, OperandInfo223 }, // Inst #3270 = VMULSDrm | |
| { 3271, 7, 1, 0, 0, "VMULSDrm_Int", 0|(1<<MCID::MayLoad), 0x4ab2000b06ULL, NULL, NULL, OperandInfo137 }, // Inst #3271 = VMULSDrm_Int | |
| { 3272, 3, 1, 0, 0, "VMULSDrr", 0|(1<<MCID::Commutable), 0x4ab2000b05ULL, NULL, NULL, OperandInfo224 }, // Inst #3272 = VMULSDrr | |
| { 3273, 3, 1, 0, 0, "VMULSDrr_Int", 0, 0x4ab2000b05ULL, NULL, NULL, OperandInfo138 }, // Inst #3273 = VMULSDrr_Int | |
| { 3274, 7, 1, 0, 0, "VMULSSrm", 0|(1<<MCID::MayLoad), 0x4ab2000c06ULL, NULL, NULL, OperandInfo225 }, // Inst #3274 = VMULSSrm | |
| { 3275, 7, 1, 0, 0, "VMULSSrm_Int", 0|(1<<MCID::MayLoad), 0x4ab2000c06ULL, NULL, NULL, OperandInfo137 }, // Inst #3275 = VMULSSrm_Int | |
| { 3276, 3, 1, 0, 0, "VMULSSrr", 0|(1<<MCID::Commutable), 0x4ab2000c05ULL, NULL, NULL, OperandInfo226 }, // Inst #3276 = VMULSSrr | |
| { 3277, 3, 1, 0, 0, "VMULSSrr_Int", 0, 0x4ab2000c05ULL, NULL, NULL, OperandInfo138 }, // Inst #3277 = VMULSSrr_Int | |
| { 3278, 6, 1, 0, 0, "VMWRITE32rm", 0|(1<<MCID::UnmodeledSideEffects), 0xf2000106ULL, NULL, NULL, OperandInfo12 }, // Inst #3278 = VMWRITE32rm | |
| { 3279, 2, 1, 0, 0, "VMWRITE32rr", 0|(1<<MCID::UnmodeledSideEffects), 0xf2000105ULL, NULL, NULL, OperandInfo65 }, // Inst #3279 = VMWRITE32rr | |
| { 3280, 6, 1, 0, 0, "VMWRITE64rm", 0|(1<<MCID::UnmodeledSideEffects), 0xf2000106ULL, NULL, NULL, OperandInfo13 }, // Inst #3280 = VMWRITE64rm | |
| { 3281, 2, 1, 0, 0, "VMWRITE64rr", 0|(1<<MCID::UnmodeledSideEffects), 0xf2000105ULL, NULL, NULL, OperandInfo66 }, // Inst #3281 = VMWRITE64rr | |
| { 3282, 0, 0, 0, 0, "VMXOFF", 0|(1<<MCID::UnmodeledSideEffects), 0x2000124ULL, NULL, NULL, 0 }, // Inst #3282 = VMXOFF | |
| { 3283, 5, 0, 0, 0, "VMXON", 0|(1<<MCID::UnmodeledSideEffects), 0x18e000c1eULL, NULL, NULL, OperandInfo38 }, // Inst #3283 = VMXON | |
| { 3284, 7, 1, 0, 0, "VORPDYrm", 0|(1<<MCID::MayLoad), 0xaad000146ULL, NULL, NULL, OperandInfo221 }, // Inst #3284 = VORPDYrm | |
| { 3285, 3, 1, 0, 0, "VORPDYrr", 0|(1<<MCID::Commutable), 0xaad000145ULL, NULL, NULL, OperandInfo222 }, // Inst #3285 = VORPDYrr | |
| { 3286, 7, 1, 0, 0, "VORPDrm", 0|(1<<MCID::MayLoad), 0xaad000146ULL, NULL, NULL, OperandInfo137 }, // Inst #3286 = VORPDrm | |
| { 3287, 3, 1, 0, 0, "VORPDrr", 0|(1<<MCID::Commutable), 0xaad000145ULL, NULL, NULL, OperandInfo138 }, // Inst #3287 = VORPDrr | |
| { 3288, 7, 1, 0, 0, "VORPSYrm", 0|(1<<MCID::MayLoad), 0xaac800106ULL, NULL, NULL, OperandInfo221 }, // Inst #3288 = VORPSYrm | |
| { 3289, 3, 1, 0, 0, "VORPSYrr", 0|(1<<MCID::Commutable), 0xaac800105ULL, NULL, NULL, OperandInfo222 }, // Inst #3289 = VORPSYrr | |
| { 3290, 7, 1, 0, 0, "VORPSrm", 0|(1<<MCID::MayLoad), 0xaac800106ULL, NULL, NULL, OperandInfo137 }, // Inst #3290 = VORPSrm | |
| { 3291, 3, 1, 0, 0, "VORPSrr", 0|(1<<MCID::Commutable)|(1<<MCID::UnmodeledSideEffects), 0xaac800105ULL, NULL, NULL, OperandInfo138 }, // Inst #3291 = VORPSrr | |
| { 3292, 6, 1, 0, 0, "VPABSBrm128", 0|(1<<MCID::MayLoad), 0x239804d46ULL, NULL, NULL, OperandInfo47 }, // Inst #3292 = VPABSBrm128 | |
| { 3293, 2, 1, 0, 0, "VPABSBrr128", 0, 0x239804d45ULL, NULL, NULL, OperandInfo48 }, // Inst #3293 = VPABSBrr128 | |
| { 3294, 6, 1, 0, 0, "VPABSDrm128", 0|(1<<MCID::MayLoad), 0x23d804d46ULL, NULL, NULL, OperandInfo47 }, // Inst #3294 = VPABSDrm128 | |
| { 3295, 2, 1, 0, 0, "VPABSDrr128", 0, 0x23d804d45ULL, NULL, NULL, OperandInfo48 }, // Inst #3295 = VPABSDrr128 | |
| { 3296, 6, 1, 0, 0, "VPABSWrm128", 0|(1<<MCID::MayLoad), 0x23b804d46ULL, NULL, NULL, OperandInfo47 }, // Inst #3296 = VPABSWrm128 | |
| { 3297, 2, 1, 0, 0, "VPABSWrr128", 0, 0x23b804d45ULL, NULL, NULL, OperandInfo48 }, // Inst #3297 = VPABSWrr128 | |
| { 3298, 7, 1, 0, 0, "VPACKSSDWrm", 0|(1<<MCID::MayLoad), 0xad7800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3298 = VPACKSSDWrm | |
| { 3299, 3, 1, 0, 0, "VPACKSSDWrr", 0, 0xad7800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3299 = VPACKSSDWrr | |
| { 3300, 7, 1, 0, 0, "VPACKSSWBrm", 0|(1<<MCID::MayLoad), 0xac7800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3300 = VPACKSSWBrm | |
| { 3301, 3, 1, 0, 0, "VPACKSSWBrr", 0, 0xac7800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3301 = VPACKSSWBrr | |
| { 3302, 7, 1, 0, 0, "VPACKUSDWrm", 0|(1<<MCID::MayLoad), 0xa57800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3302 = VPACKUSDWrm | |
| { 3303, 3, 1, 0, 0, "VPACKUSDWrr", 0, 0xa57800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3303 = VPACKUSDWrr | |
| { 3304, 7, 1, 0, 0, "VPACKUSWBrm", 0|(1<<MCID::MayLoad), 0xacf800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3304 = VPACKUSWBrm | |
| { 3305, 3, 1, 0, 0, "VPACKUSWBrr", 0, 0xacf800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3305 = VPACKUSWBrr | |
| { 3306, 7, 1, 0, 0, "VPADDBrm", 0|(1<<MCID::MayLoad), 0xbf9800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3306 = VPADDBrm | |
| { 3307, 3, 1, 0, 0, "VPADDBrr", 0|(1<<MCID::Commutable), 0xbf9800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3307 = VPADDBrr | |
| { 3308, 7, 1, 0, 0, "VPADDDrm", 0|(1<<MCID::MayLoad), 0xbfd800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3308 = VPADDDrm | |
| { 3309, 3, 1, 0, 0, "VPADDDrr", 0|(1<<MCID::Commutable), 0xbfd800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3309 = VPADDDrr | |
| { 3310, 7, 1, 0, 0, "VPADDQrm", 0|(1<<MCID::MayLoad), 0xba9800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3310 = VPADDQrm | |
| { 3311, 3, 1, 0, 0, "VPADDQrr", 0|(1<<MCID::Commutable), 0xba9800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3311 = VPADDQrr | |
| { 3312, 7, 1, 0, 0, "VPADDSBrm", 0|(1<<MCID::MayLoad), 0xbd9800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3312 = VPADDSBrm | |
| { 3313, 3, 1, 0, 0, "VPADDSBrr", 0|(1<<MCID::Commutable), 0xbd9800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3313 = VPADDSBrr | |
| { 3314, 7, 1, 0, 0, "VPADDSWrm", 0|(1<<MCID::MayLoad), 0xbdb800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3314 = VPADDSWrm | |
| { 3315, 3, 1, 0, 0, "VPADDSWrr", 0|(1<<MCID::Commutable), 0xbdb800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3315 = VPADDSWrr | |
| { 3316, 7, 1, 0, 0, "VPADDUSBrm", 0|(1<<MCID::MayLoad), 0xbb9800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3316 = VPADDUSBrm | |
| { 3317, 3, 1, 0, 0, "VPADDUSBrr", 0|(1<<MCID::Commutable), 0xbb9800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3317 = VPADDUSBrr | |
| { 3318, 7, 1, 0, 0, "VPADDUSWrm", 0|(1<<MCID::MayLoad), 0xbbb800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3318 = VPADDUSWrm | |
| { 3319, 3, 1, 0, 0, "VPADDUSWrr", 0|(1<<MCID::Commutable), 0xbbb800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3319 = VPADDUSWrr | |
| { 3320, 7, 1, 0, 0, "VPADDWrm", 0|(1<<MCID::MayLoad), 0xbfb800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3320 = VPADDWrm | |
| { 3321, 3, 1, 0, 0, "VPADDWrr", 0|(1<<MCID::Commutable), 0xbfb800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3321 = VPADDWrr | |
| { 3322, 8, 1, 0, 0, "VPALIGNR128rm", 0|(1<<MCID::UnmodeledSideEffects), 0xa1f804e46ULL, NULL, NULL, OperandInfo136 }, // Inst #3322 = VPALIGNR128rm | |
| { 3323, 4, 1, 0, 0, "VPALIGNR128rr", 0|(1<<MCID::UnmodeledSideEffects), 0xa1f804e45ULL, NULL, NULL, OperandInfo86 }, // Inst #3323 = VPALIGNR128rr | |
| { 3324, 7, 1, 0, 0, "VPANDNrm", 0|(1<<MCID::MayLoad), 0xbbf800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3324 = VPANDNrm | |
| { 3325, 3, 1, 0, 0, "VPANDNrr", 0, 0xbbf800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3325 = VPANDNrr | |
| { 3326, 7, 1, 0, 0, "VPANDrm", 0|(1<<MCID::MayLoad), 0xbb7800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3326 = VPANDrm | |
| { 3327, 3, 1, 0, 0, "VPANDrr", 0|(1<<MCID::Commutable), 0xbb7800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3327 = VPANDrr | |
| { 3328, 7, 1, 0, 0, "VPAVGBrm", 0|(1<<MCID::MayLoad), 0xbc1800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3328 = VPAVGBrm | |
| { 3329, 3, 1, 0, 0, "VPAVGBrr", 0|(1<<MCID::Commutable), 0xbc1800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3329 = VPAVGBrr | |
| { 3330, 7, 1, 0, 0, "VPAVGWrm", 0|(1<<MCID::MayLoad), 0xbc7800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3330 = VPAVGWrm | |
| { 3331, 3, 1, 0, 0, "VPAVGWrr", 0|(1<<MCID::Commutable), 0xbc7800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3331 = VPAVGWrr | |
| { 3332, 8, 1, 0, 0, "VPBLENDVBrm", 0|(1<<MCID::MayLoad), 0x1a99800e46ULL, NULL, NULL, OperandInfo231 }, // Inst #3332 = VPBLENDVBrm | |
| { 3333, 4, 1, 0, 0, "VPBLENDVBrr", 0, 0x1a99800e45ULL, NULL, NULL, OperandInfo232 }, // Inst #3333 = VPBLENDVBrr | |
| { 3334, 8, 1, 0, 0, "VPBLENDWrmi", 0|(1<<MCID::MayLoad), 0xa1d804e46ULL, NULL, NULL, OperandInfo136 }, // Inst #3334 = VPBLENDWrmi | |
| { 3335, 4, 1, 0, 0, "VPBLENDWrri", 0, 0xa1d804e45ULL, NULL, NULL, OperandInfo86 }, // Inst #3335 = VPBLENDWrri | |
| { 3336, 8, 1, 0, 0, "VPCLMULQDQrm", 0|(1<<MCID::UnmodeledSideEffects), 0xa89804e46ULL, NULL, NULL, OperandInfo136 }, // Inst #3336 = VPCLMULQDQrm | |
| { 3337, 4, 1, 0, 0, "VPCLMULQDQrr", 0|(1<<MCID::UnmodeledSideEffects), 0xa89804e45ULL, NULL, NULL, OperandInfo86 }, // Inst #3337 = VPCLMULQDQrr | |
| { 3338, 7, 1, 0, 0, "VPCMPEQBrm", 0|(1<<MCID::MayLoad), 0xae9800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3338 = VPCMPEQBrm | |
| { 3339, 3, 1, 0, 0, "VPCMPEQBrr", 0|(1<<MCID::Commutable), 0xae9800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3339 = VPCMPEQBrr | |
| { 3340, 7, 1, 0, 0, "VPCMPEQDrm", 0|(1<<MCID::MayLoad), 0xaed800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3340 = VPCMPEQDrm | |
| { 3341, 3, 1, 0, 0, "VPCMPEQDrr", 0|(1<<MCID::Commutable), 0xaed800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3341 = VPCMPEQDrr | |
| { 3342, 7, 1, 0, 0, "VPCMPEQQrm", 0|(1<<MCID::MayLoad), 0xa53800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3342 = VPCMPEQQrm | |
| { 3343, 3, 1, 0, 0, "VPCMPEQQrr", 0|(1<<MCID::Commutable), 0xa53800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3343 = VPCMPEQQrr | |
| { 3344, 7, 1, 0, 0, "VPCMPEQWrm", 0|(1<<MCID::MayLoad), 0xaeb800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3344 = VPCMPEQWrm | |
| { 3345, 3, 1, 0, 0, "VPCMPEQWrr", 0|(1<<MCID::Commutable), 0xaeb800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3345 = VPCMPEQWrr | |
| { 3346, 7, 0, 0, 0, "VPCMPESTRIArm", 0|(1<<MCID::MayLoad), 0x2c3804e46ULL, ImplicitList15, ImplicitList45, OperandInfo49 }, // Inst #3346 = VPCMPESTRIArm | |
| { 3347, 3, 0, 0, 0, "VPCMPESTRIArr", 0, 0x2c3804e45ULL, ImplicitList15, ImplicitList45, OperandInfo50 }, // Inst #3347 = VPCMPESTRIArr | |
| { 3348, 7, 0, 0, 0, "VPCMPESTRICrm", 0|(1<<MCID::MayLoad), 0x2c3804e46ULL, ImplicitList15, ImplicitList45, OperandInfo49 }, // Inst #3348 = VPCMPESTRICrm | |
| { 3349, 3, 0, 0, 0, "VPCMPESTRICrr", 0, 0x2c3804e45ULL, ImplicitList15, ImplicitList45, OperandInfo50 }, // Inst #3349 = VPCMPESTRICrr | |
| { 3350, 7, 0, 0, 0, "VPCMPESTRIOrm", 0|(1<<MCID::MayLoad), 0x2c3804e46ULL, ImplicitList15, ImplicitList45, OperandInfo49 }, // Inst #3350 = VPCMPESTRIOrm | |
| { 3351, 3, 0, 0, 0, "VPCMPESTRIOrr", 0, 0x2c3804e45ULL, ImplicitList15, ImplicitList45, OperandInfo50 }, // Inst #3351 = VPCMPESTRIOrr | |
| { 3352, 7, 0, 0, 0, "VPCMPESTRISrm", 0|(1<<MCID::MayLoad), 0x2c3804e46ULL, ImplicitList15, ImplicitList45, OperandInfo49 }, // Inst #3352 = VPCMPESTRISrm | |
| { 3353, 3, 0, 0, 0, "VPCMPESTRISrr", 0, 0x2c3804e45ULL, ImplicitList15, ImplicitList45, OperandInfo50 }, // Inst #3353 = VPCMPESTRISrr | |
| { 3354, 7, 0, 0, 0, "VPCMPESTRIZrm", 0|(1<<MCID::MayLoad), 0x2c3804e46ULL, ImplicitList15, ImplicitList45, OperandInfo49 }, // Inst #3354 = VPCMPESTRIZrm | |
| { 3355, 3, 0, 0, 0, "VPCMPESTRIZrr", 0, 0x2c3804e45ULL, ImplicitList15, ImplicitList45, OperandInfo50 }, // Inst #3355 = VPCMPESTRIZrr | |
| { 3356, 7, 0, 0, 0, "VPCMPESTRIrm", 0|(1<<MCID::MayLoad), 0x2c3804e46ULL, ImplicitList15, ImplicitList45, OperandInfo49 }, // Inst #3356 = VPCMPESTRIrm | |
| { 3357, 3, 0, 0, 0, "VPCMPESTRIrr", 0, 0x2c3804e45ULL, ImplicitList15, ImplicitList45, OperandInfo50 }, // Inst #3357 = VPCMPESTRIrr | |
| { 3358, 8, 1, 0, 0, "VPCMPESTRM128MEM", 0|(1<<MCID::MayLoad)|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList15, ImplicitList1, OperandInfo136 }, // Inst #3358 = VPCMPESTRM128MEM | |
| { 3359, 4, 1, 0, 0, "VPCMPESTRM128REG", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList15, ImplicitList1, OperandInfo86 }, // Inst #3359 = VPCMPESTRM128REG | |
| { 3360, 7, 0, 0, 0, "VPCMPESTRM128rm", 0|(1<<MCID::UnmodeledSideEffects), 0x2c1804e46ULL, ImplicitList15, ImplicitList46, OperandInfo49 }, // Inst #3360 = VPCMPESTRM128rm | |
| { 3361, 3, 0, 0, 0, "VPCMPESTRM128rr", 0|(1<<MCID::UnmodeledSideEffects), 0x2c1804e45ULL, ImplicitList15, ImplicitList46, OperandInfo50 }, // Inst #3361 = VPCMPESTRM128rr | |
| { 3362, 7, 1, 0, 0, "VPCMPGTBrm", 0|(1<<MCID::MayLoad), 0xac9800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3362 = VPCMPGTBrm | |
| { 3363, 3, 1, 0, 0, "VPCMPGTBrr", 0, 0xac9800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3363 = VPCMPGTBrr | |
| { 3364, 7, 1, 0, 0, "VPCMPGTDrm", 0|(1<<MCID::MayLoad), 0xacd800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3364 = VPCMPGTDrm | |
| { 3365, 3, 1, 0, 0, "VPCMPGTDrr", 0, 0xacd800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3365 = VPCMPGTDrr | |
| { 3366, 7, 1, 0, 0, "VPCMPGTQrm", 0|(1<<MCID::MayLoad), 0xa6f800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3366 = VPCMPGTQrm | |
| { 3367, 3, 1, 0, 0, "VPCMPGTQrr", 0, 0xa6f800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3367 = VPCMPGTQrr | |
| { 3368, 7, 1, 0, 0, "VPCMPGTWrm", 0|(1<<MCID::MayLoad), 0xacb800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3368 = VPCMPGTWrm | |
| { 3369, 3, 1, 0, 0, "VPCMPGTWrr", 0, 0xacb800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3369 = VPCMPGTWrr | |
| { 3370, 7, 0, 0, 0, "VPCMPISTRIArm", 0|(1<<MCID::MayLoad), 0x2c7804e46ULL, NULL, ImplicitList45, OperandInfo49 }, // Inst #3370 = VPCMPISTRIArm | |
| { 3371, 3, 0, 0, 0, "VPCMPISTRIArr", 0, 0x2c7804e45ULL, NULL, ImplicitList45, OperandInfo50 }, // Inst #3371 = VPCMPISTRIArr | |
| { 3372, 7, 0, 0, 0, "VPCMPISTRICrm", 0|(1<<MCID::MayLoad), 0x2c7804e46ULL, NULL, ImplicitList45, OperandInfo49 }, // Inst #3372 = VPCMPISTRICrm | |
| { 3373, 3, 0, 0, 0, "VPCMPISTRICrr", 0, 0x2c7804e45ULL, NULL, ImplicitList45, OperandInfo50 }, // Inst #3373 = VPCMPISTRICrr | |
| { 3374, 7, 0, 0, 0, "VPCMPISTRIOrm", 0|(1<<MCID::MayLoad), 0x2c7804e46ULL, NULL, ImplicitList45, OperandInfo49 }, // Inst #3374 = VPCMPISTRIOrm | |
| { 3375, 3, 0, 0, 0, "VPCMPISTRIOrr", 0, 0x2c7804e45ULL, NULL, ImplicitList45, OperandInfo50 }, // Inst #3375 = VPCMPISTRIOrr | |
| { 3376, 7, 0, 0, 0, "VPCMPISTRISrm", 0|(1<<MCID::MayLoad), 0x2c7804e46ULL, NULL, ImplicitList45, OperandInfo49 }, // Inst #3376 = VPCMPISTRISrm | |
| { 3377, 3, 0, 0, 0, "VPCMPISTRISrr", 0, 0x2c7804e45ULL, NULL, ImplicitList45, OperandInfo50 }, // Inst #3377 = VPCMPISTRISrr | |
| { 3378, 7, 0, 0, 0, "VPCMPISTRIZrm", 0|(1<<MCID::MayLoad), 0x2c7804e46ULL, NULL, ImplicitList45, OperandInfo49 }, // Inst #3378 = VPCMPISTRIZrm | |
| { 3379, 3, 0, 0, 0, "VPCMPISTRIZrr", 0, 0x2c7804e45ULL, NULL, ImplicitList45, OperandInfo50 }, // Inst #3379 = VPCMPISTRIZrr | |
| { 3380, 7, 0, 0, 0, "VPCMPISTRIrm", 0|(1<<MCID::MayLoad), 0x2c7804e46ULL, NULL, ImplicitList45, OperandInfo49 }, // Inst #3380 = VPCMPISTRIrm | |
| { 3381, 3, 0, 0, 0, "VPCMPISTRIrr", 0, 0x2c7804e45ULL, NULL, ImplicitList45, OperandInfo50 }, // Inst #3381 = VPCMPISTRIrr | |
| { 3382, 8, 1, 0, 0, "VPCMPISTRM128MEM", 0|(1<<MCID::MayLoad)|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo136 }, // Inst #3382 = VPCMPISTRM128MEM | |
| { 3383, 4, 1, 0, 0, "VPCMPISTRM128REG", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo86 }, // Inst #3383 = VPCMPISTRM128REG | |
| { 3384, 7, 0, 0, 0, "VPCMPISTRM128rm", 0|(1<<MCID::UnmodeledSideEffects), 0x2c5804e46ULL, NULL, ImplicitList46, OperandInfo49 }, // Inst #3384 = VPCMPISTRM128rm | |
| { 3385, 3, 0, 0, 0, "VPCMPISTRM128rr", 0|(1<<MCID::UnmodeledSideEffects), 0x2c5804e45ULL, NULL, ImplicitList46, OperandInfo50 }, // Inst #3385 = VPCMPISTRM128rr | |
| { 3386, 8, 1, 0, 0, "VPERM2F128rm", 0|(1<<MCID::UnmodeledSideEffects), 0xa0d804e46ULL, NULL, NULL, OperandInfo228 }, // Inst #3386 = VPERM2F128rm | |
| { 3387, 4, 1, 0, 0, "VPERM2F128rr", 0|(1<<MCID::UnmodeledSideEffects), 0xa0d804e45ULL, NULL, NULL, OperandInfo87 }, // Inst #3387 = VPERM2F128rr | |
| { 3388, 7, 1, 0, 0, "VPERMILPDYmi", 0|(1<<MCID::MayLoad), 0x20b804e46ULL, NULL, NULL, OperandInfo257 }, // Inst #3388 = VPERMILPDYmi | |
| { 3389, 3, 1, 0, 0, "VPERMILPDYri", 0, 0x20b804e45ULL, NULL, NULL, OperandInfo258 }, // Inst #3389 = VPERMILPDYri | |
| { 3390, 7, 1, 0, 0, "VPERMILPDYrm", 0|(1<<MCID::MayLoad), 0xa1b800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #3390 = VPERMILPDYrm | |
| { 3391, 3, 1, 0, 0, "VPERMILPDYrr", 0, 0xa1b800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #3391 = VPERMILPDYrr | |
| { 3392, 7, 1, 0, 0, "VPERMILPDmi", 0|(1<<MCID::MayLoad), 0x20b804e46ULL, NULL, NULL, OperandInfo49 }, // Inst #3392 = VPERMILPDmi | |
| { 3393, 3, 1, 0, 0, "VPERMILPDri", 0, 0x20b804e45ULL, NULL, NULL, OperandInfo50 }, // Inst #3393 = VPERMILPDri | |
| { 3394, 7, 1, 0, 0, "VPERMILPDrm", 0|(1<<MCID::MayLoad), 0xa1b800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3394 = VPERMILPDrm | |
| { 3395, 3, 1, 0, 0, "VPERMILPDrr", 0, 0xa1b800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3395 = VPERMILPDrr | |
| { 3396, 7, 1, 0, 0, "VPERMILPSYmi", 0|(1<<MCID::MayLoad), 0x209804e46ULL, NULL, NULL, OperandInfo257 }, // Inst #3396 = VPERMILPSYmi | |
| { 3397, 3, 1, 0, 0, "VPERMILPSYri", 0, 0x209804e45ULL, NULL, NULL, OperandInfo258 }, // Inst #3397 = VPERMILPSYri | |
| { 3398, 7, 1, 0, 0, "VPERMILPSYrm", 0|(1<<MCID::MayLoad), 0xa19800d46ULL, NULL, NULL, OperandInfo221 }, // Inst #3398 = VPERMILPSYrm | |
| { 3399, 3, 1, 0, 0, "VPERMILPSYrr", 0, 0xa19800d45ULL, NULL, NULL, OperandInfo222 }, // Inst #3399 = VPERMILPSYrr | |
| { 3400, 7, 1, 0, 0, "VPERMILPSmi", 0|(1<<MCID::MayLoad), 0x209804e46ULL, NULL, NULL, OperandInfo49 }, // Inst #3400 = VPERMILPSmi | |
| { 3401, 3, 1, 0, 0, "VPERMILPSri", 0, 0x209804e45ULL, NULL, NULL, OperandInfo50 }, // Inst #3401 = VPERMILPSri | |
| { 3402, 7, 1, 0, 0, "VPERMILPSrm", 0|(1<<MCID::MayLoad), 0xa19800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3402 = VPERMILPSrm | |
| { 3403, 3, 1, 0, 0, "VPERMILPSrr", 0, 0xa19800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3403 = VPERMILPSrr | |
| { 3404, 7, 0, 0, 0, "VPEXTRBmr", 0|(1<<MCID::UnmodeledSideEffects), 0x229804e44ULL, NULL, NULL, OperandInfo115 }, // Inst #3404 = VPEXTRBmr | |
| { 3405, 3, 1, 0, 0, "VPEXTRBrr", 0, 0x229804e43ULL, NULL, NULL, OperandInfo116 }, // Inst #3405 = VPEXTRBrr | |
| { 3406, 3, 1, 0, 0, "VPEXTRBrr64", 0|(1<<MCID::UnmodeledSideEffects), 0x229804e43ULL, NULL, NULL, OperandInfo200 }, // Inst #3406 = VPEXTRBrr64 | |
| { 3407, 7, 0, 0, 0, "VPEXTRDmr", 0|(1<<MCID::MayStore), 0x22d804e44ULL, NULL, NULL, OperandInfo115 }, // Inst #3407 = VPEXTRDmr | |
| { 3408, 3, 1, 0, 0, "VPEXTRDrr", 0, 0x22d804e43ULL, NULL, NULL, OperandInfo116 }, // Inst #3408 = VPEXTRDrr | |
| { 3409, 7, 0, 0, 0, "VPEXTRQmr", 0|(1<<MCID::MayStore), 0x62d806e44ULL, NULL, NULL, OperandInfo115 }, // Inst #3409 = VPEXTRQmr | |
| { 3410, 3, 1, 0, 0, "VPEXTRQrr", 0, 0x62d806e43ULL, NULL, NULL, OperandInfo200 }, // Inst #3410 = VPEXTRQrr | |
| { 3411, 7, 0, 0, 0, "VPEXTRWmr", 0|(1<<MCID::UnmodeledSideEffects), 0x22b804e44ULL, NULL, NULL, OperandInfo115 }, // Inst #3411 = VPEXTRWmr | |
| { 3412, 3, 1, 0, 0, "VPEXTRWri", 0, 0x38b804145ULL, NULL, NULL, OperandInfo116 }, // Inst #3412 = VPEXTRWri | |
| { 3413, 7, 1, 0, 0, "VPHADDDrm128", 0|(1<<MCID::MayLoad), 0xa05800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3413 = VPHADDDrm128 | |
| { 3414, 3, 1, 0, 0, "VPHADDDrr128", 0, 0xa05800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3414 = VPHADDDrr128 | |
| { 3415, 7, 1, 0, 0, "VPHADDSWrm128", 0|(1<<MCID::MayLoad), 0xa07800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3415 = VPHADDSWrm128 | |
| { 3416, 3, 1, 0, 0, "VPHADDSWrr128", 0, 0xa07800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3416 = VPHADDSWrr128 | |
| { 3417, 7, 1, 0, 0, "VPHADDWrm128", 0|(1<<MCID::MayLoad), 0xa03800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3417 = VPHADDWrm128 | |
| { 3418, 3, 1, 0, 0, "VPHADDWrr128", 0, 0xa03800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3418 = VPHADDWrr128 | |
| { 3419, 6, 1, 0, 0, "VPHMINPOSUWrm128", 0|(1<<MCID::MayLoad), 0x283800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #3419 = VPHMINPOSUWrm128 | |
| { 3420, 2, 1, 0, 0, "VPHMINPOSUWrr128", 0, 0x283800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #3420 = VPHMINPOSUWrr128 | |
| { 3421, 7, 1, 0, 0, "VPHSUBDrm128", 0|(1<<MCID::MayLoad), 0xa0d800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3421 = VPHSUBDrm128 | |
| { 3422, 3, 1, 0, 0, "VPHSUBDrr128", 0, 0xa0d800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3422 = VPHSUBDrr128 | |
| { 3423, 7, 1, 0, 0, "VPHSUBSWrm128", 0|(1<<MCID::MayLoad), 0xa0f800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3423 = VPHSUBSWrm128 | |
| { 3424, 3, 1, 0, 0, "VPHSUBSWrr128", 0, 0xa0f800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3424 = VPHSUBSWrr128 | |
| { 3425, 7, 1, 0, 0, "VPHSUBWrm128", 0|(1<<MCID::MayLoad), 0xa0b800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3425 = VPHSUBWrm128 | |
| { 3426, 3, 1, 0, 0, "VPHSUBWrr128", 0, 0xa0b800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3426 = VPHSUBWrr128 | |
| { 3427, 8, 1, 0, 0, "VPINSRBrm", 0|(1<<MCID::MayLoad), 0xa41804e46ULL, NULL, NULL, OperandInfo136 }, // Inst #3427 = VPINSRBrm | |
| { 3428, 4, 1, 0, 0, "VPINSRBrr", 0, 0xa41804e45ULL, NULL, NULL, OperandInfo259 }, // Inst #3428 = VPINSRBrr | |
| { 3429, 8, 1, 0, 0, "VPINSRDrm", 0|(1<<MCID::MayLoad), 0xa45804e46ULL, NULL, NULL, OperandInfo136 }, // Inst #3429 = VPINSRDrm | |
| { 3430, 4, 1, 0, 0, "VPINSRDrr", 0, 0xa45804e45ULL, NULL, NULL, OperandInfo259 }, // Inst #3430 = VPINSRDrr | |
| { 3431, 8, 1, 0, 0, "VPINSRQrm", 0|(1<<MCID::MayLoad), 0xe45804e46ULL, NULL, NULL, OperandInfo136 }, // Inst #3431 = VPINSRQrm | |
| { 3432, 4, 1, 0, 0, "VPINSRQrr", 0, 0xe45804e45ULL, NULL, NULL, OperandInfo260 }, // Inst #3432 = VPINSRQrr | |
| { 3433, 8, 1, 0, 0, "VPINSRWrmi", 0|(1<<MCID::MayLoad), 0xb89804146ULL, NULL, NULL, OperandInfo136 }, // Inst #3433 = VPINSRWrmi | |
| { 3434, 4, 1, 0, 0, "VPINSRWrr64i", 0|(1<<MCID::UnmodeledSideEffects), 0xb89804145ULL, NULL, NULL, OperandInfo260 }, // Inst #3434 = VPINSRWrr64i | |
| { 3435, 4, 1, 0, 0, "VPINSRWrri", 0, 0xb89804145ULL, NULL, NULL, OperandInfo259 }, // Inst #3435 = VPINSRWrri | |
| { 3436, 7, 1, 0, 0, "VPMADDUBSWrm128", 0|(1<<MCID::MayLoad), 0xa09800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3436 = VPMADDUBSWrm128 | |
| { 3437, 3, 1, 0, 0, "VPMADDUBSWrr128", 0, 0xa09800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3437 = VPMADDUBSWrr128 | |
| { 3438, 7, 1, 0, 0, "VPMADDWDrm", 0|(1<<MCID::MayLoad), 0xbeb800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3438 = VPMADDWDrm | |
| { 3439, 3, 1, 0, 0, "VPMADDWDrr", 0|(1<<MCID::Commutable), 0xbeb800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3439 = VPMADDWDrr | |
| { 3440, 7, 1, 0, 0, "VPMAXSBrm", 0|(1<<MCID::MayLoad), 0xa79800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3440 = VPMAXSBrm | |
| { 3441, 3, 1, 0, 0, "VPMAXSBrr", 0|(1<<MCID::Commutable), 0xa79800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3441 = VPMAXSBrr | |
| { 3442, 7, 1, 0, 0, "VPMAXSDrm", 0|(1<<MCID::MayLoad), 0xa7b800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3442 = VPMAXSDrm | |
| { 3443, 3, 1, 0, 0, "VPMAXSDrr", 0|(1<<MCID::Commutable), 0xa7b800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3443 = VPMAXSDrr | |
| { 3444, 7, 1, 0, 0, "VPMAXSWrm", 0|(1<<MCID::MayLoad), 0xbdd800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3444 = VPMAXSWrm | |
| { 3445, 3, 1, 0, 0, "VPMAXSWrr", 0|(1<<MCID::Commutable), 0xbdd800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3445 = VPMAXSWrr | |
| { 3446, 7, 1, 0, 0, "VPMAXUBrm", 0|(1<<MCID::MayLoad), 0xbbd800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3446 = VPMAXUBrm | |
| { 3447, 3, 1, 0, 0, "VPMAXUBrr", 0|(1<<MCID::Commutable), 0xbbd800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3447 = VPMAXUBrr | |
| { 3448, 7, 1, 0, 0, "VPMAXUDrm", 0|(1<<MCID::MayLoad), 0xa7f800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3448 = VPMAXUDrm | |
| { 3449, 3, 1, 0, 0, "VPMAXUDrr", 0|(1<<MCID::Commutable), 0xa7f800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3449 = VPMAXUDrr | |
| { 3450, 7, 1, 0, 0, "VPMAXUWrm", 0|(1<<MCID::MayLoad), 0xa7d800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3450 = VPMAXUWrm | |
| { 3451, 3, 1, 0, 0, "VPMAXUWrr", 0|(1<<MCID::Commutable), 0xa7d800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3451 = VPMAXUWrr | |
| { 3452, 7, 1, 0, 0, "VPMINSBrm", 0|(1<<MCID::MayLoad), 0xa71800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3452 = VPMINSBrm | |
| { 3453, 3, 1, 0, 0, "VPMINSBrr", 0|(1<<MCID::Commutable), 0xa71800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3453 = VPMINSBrr | |
| { 3454, 7, 1, 0, 0, "VPMINSDrm", 0|(1<<MCID::MayLoad), 0xa73800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3454 = VPMINSDrm | |
| { 3455, 3, 1, 0, 0, "VPMINSDrr", 0|(1<<MCID::Commutable), 0xa73800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3455 = VPMINSDrr | |
| { 3456, 7, 1, 0, 0, "VPMINSWrm", 0|(1<<MCID::MayLoad), 0xbd5800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3456 = VPMINSWrm | |
| { 3457, 3, 1, 0, 0, "VPMINSWrr", 0|(1<<MCID::Commutable), 0xbd5800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3457 = VPMINSWrr | |
| { 3458, 7, 1, 0, 0, "VPMINUBrm", 0|(1<<MCID::MayLoad), 0xbb5800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3458 = VPMINUBrm | |
| { 3459, 3, 1, 0, 0, "VPMINUBrr", 0|(1<<MCID::Commutable), 0xbb5800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3459 = VPMINUBrr | |
| { 3460, 7, 1, 0, 0, "VPMINUDrm", 0|(1<<MCID::MayLoad), 0xa77800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3460 = VPMINUDrm | |
| { 3461, 3, 1, 0, 0, "VPMINUDrr", 0|(1<<MCID::Commutable), 0xa77800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3461 = VPMINUDrr | |
| { 3462, 7, 1, 0, 0, "VPMINUWrm", 0|(1<<MCID::MayLoad), 0xa75800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3462 = VPMINUWrm | |
| { 3463, 3, 1, 0, 0, "VPMINUWrr", 0|(1<<MCID::Commutable), 0xa75800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3463 = VPMINUWrr | |
| { 3464, 2, 1, 0, 0, "VPMOVMSKBr64r", 0|(1<<MCID::UnmodeledSideEffects), 0x3af800145ULL, NULL, NULL, OperandInfo97 }, // Inst #3464 = VPMOVMSKBr64r | |
| { 3465, 2, 1, 0, 0, "VPMOVMSKBrr", 0, 0x3af800145ULL, NULL, NULL, OperandInfo98 }, // Inst #3465 = VPMOVMSKBrr | |
| { 3466, 6, 1, 0, 0, "VPMOVSXBDrm", 0|(1<<MCID::MayLoad), 0x243800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #3466 = VPMOVSXBDrm | |
| { 3467, 2, 1, 0, 0, "VPMOVSXBDrr", 0, 0x243800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #3467 = VPMOVSXBDrr | |
| { 3468, 6, 1, 0, 0, "VPMOVSXBQrm", 0|(1<<MCID::MayLoad), 0x245800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #3468 = VPMOVSXBQrm | |
| { 3469, 2, 1, 0, 0, "VPMOVSXBQrr", 0, 0x245800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #3469 = VPMOVSXBQrr | |
| { 3470, 6, 1, 0, 0, "VPMOVSXBWrm", 0|(1<<MCID::MayLoad), 0x241800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #3470 = VPMOVSXBWrm | |
| { 3471, 2, 1, 0, 0, "VPMOVSXBWrr", 0, 0x241800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #3471 = VPMOVSXBWrr | |
| { 3472, 6, 1, 0, 0, "VPMOVSXDQrm", 0|(1<<MCID::MayLoad), 0x24b800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #3472 = VPMOVSXDQrm | |
| { 3473, 2, 1, 0, 0, "VPMOVSXDQrr", 0, 0x24b800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #3473 = VPMOVSXDQrr | |
| { 3474, 6, 1, 0, 0, "VPMOVSXWDrm", 0|(1<<MCID::MayLoad), 0x247800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #3474 = VPMOVSXWDrm | |
| { 3475, 2, 1, 0, 0, "VPMOVSXWDrr", 0, 0x247800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #3475 = VPMOVSXWDrr | |
| { 3476, 6, 1, 0, 0, "VPMOVSXWQrm", 0|(1<<MCID::MayLoad), 0x249800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #3476 = VPMOVSXWQrm | |
| { 3477, 2, 1, 0, 0, "VPMOVSXWQrr", 0, 0x249800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #3477 = VPMOVSXWQrr | |
| { 3478, 6, 1, 0, 0, "VPMOVZXBDrm", 0|(1<<MCID::MayLoad), 0x263800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #3478 = VPMOVZXBDrm | |
| { 3479, 2, 1, 0, 0, "VPMOVZXBDrr", 0, 0x263800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #3479 = VPMOVZXBDrr | |
| { 3480, 6, 1, 0, 0, "VPMOVZXBQrm", 0|(1<<MCID::MayLoad), 0x265800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #3480 = VPMOVZXBQrm | |
| { 3481, 2, 1, 0, 0, "VPMOVZXBQrr", 0, 0x265800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #3481 = VPMOVZXBQrr | |
| { 3482, 6, 1, 0, 0, "VPMOVZXBWrm", 0|(1<<MCID::MayLoad), 0x261800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #3482 = VPMOVZXBWrm | |
| { 3483, 2, 1, 0, 0, "VPMOVZXBWrr", 0, 0x261800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #3483 = VPMOVZXBWrr | |
| { 3484, 6, 1, 0, 0, "VPMOVZXDQrm", 0|(1<<MCID::MayLoad), 0x26b800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #3484 = VPMOVZXDQrm | |
| { 3485, 2, 1, 0, 0, "VPMOVZXDQrr", 0, 0x26b800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #3485 = VPMOVZXDQrr | |
| { 3486, 6, 1, 0, 0, "VPMOVZXWDrm", 0|(1<<MCID::MayLoad), 0x267800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #3486 = VPMOVZXWDrm | |
| { 3487, 2, 1, 0, 0, "VPMOVZXWDrr", 0, 0x267800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #3487 = VPMOVZXWDrr | |
| { 3488, 6, 1, 0, 0, "VPMOVZXWQrm", 0|(1<<MCID::MayLoad), 0x269800d46ULL, NULL, NULL, OperandInfo47 }, // Inst #3488 = VPMOVZXWQrm | |
| { 3489, 2, 1, 0, 0, "VPMOVZXWQrr", 0, 0x269800d45ULL, NULL, NULL, OperandInfo48 }, // Inst #3489 = VPMOVZXWQrr | |
| { 3490, 7, 1, 0, 0, "VPMULDQrm", 0|(1<<MCID::MayLoad), 0xa51800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3490 = VPMULDQrm | |
| { 3491, 3, 1, 0, 0, "VPMULDQrr", 0|(1<<MCID::Commutable), 0xa51800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3491 = VPMULDQrr | |
| { 3492, 7, 1, 0, 0, "VPMULHRSWrm128", 0|(1<<MCID::MayLoad), 0xa17800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3492 = VPMULHRSWrm128 | |
| { 3493, 3, 1, 0, 0, "VPMULHRSWrr128", 0|(1<<MCID::Commutable), 0xa17800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3493 = VPMULHRSWrr128 | |
| { 3494, 7, 1, 0, 0, "VPMULHUWrm", 0|(1<<MCID::MayLoad), 0xbc9800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3494 = VPMULHUWrm | |
| { 3495, 3, 1, 0, 0, "VPMULHUWrr", 0|(1<<MCID::Commutable), 0xbc9800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3495 = VPMULHUWrr | |
| { 3496, 7, 1, 0, 0, "VPMULHWrm", 0|(1<<MCID::MayLoad), 0xbcb800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3496 = VPMULHWrm | |
| { 3497, 3, 1, 0, 0, "VPMULHWrr", 0|(1<<MCID::Commutable), 0xbcb800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3497 = VPMULHWrr | |
| { 3498, 7, 1, 0, 0, "VPMULLDrm", 0|(1<<MCID::MayLoad), 0xa81800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3498 = VPMULLDrm | |
| { 3499, 3, 1, 0, 0, "VPMULLDrr", 0|(1<<MCID::Commutable), 0xa81800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3499 = VPMULLDrr | |
| { 3500, 7, 1, 0, 0, "VPMULLWrm", 0|(1<<MCID::MayLoad), 0xbab800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3500 = VPMULLWrm | |
| { 3501, 3, 1, 0, 0, "VPMULLWrr", 0|(1<<MCID::Commutable), 0xbab800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3501 = VPMULLWrr | |
| { 3502, 7, 1, 0, 0, "VPMULUDQrm", 0|(1<<MCID::MayLoad), 0xbe9800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3502 = VPMULUDQrm | |
| { 3503, 3, 1, 0, 0, "VPMULUDQrr", 0|(1<<MCID::Commutable), 0xbe9800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3503 = VPMULUDQrr | |
| { 3504, 7, 1, 0, 0, "VPORrm", 0|(1<<MCID::MayLoad), 0xbd7800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3504 = VPORrm | |
| { 3505, 3, 1, 0, 0, "VPORrr", 0|(1<<MCID::Commutable), 0xbd7800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3505 = VPORrr | |
| { 3506, 7, 1, 0, 0, "VPSADBWrm", 0|(1<<MCID::MayLoad), 0xbed800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3506 = VPSADBWrm | |
| { 3507, 3, 1, 0, 0, "VPSADBWrr", 0|(1<<MCID::Commutable), 0xbed800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3507 = VPSADBWrr | |
| { 3508, 7, 1, 0, 0, "VPSHUFBrm128", 0|(1<<MCID::MayLoad), 0xa01800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3508 = VPSHUFBrm128 | |
| { 3509, 3, 1, 0, 0, "VPSHUFBrr128", 0, 0xa01800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3509 = VPSHUFBrr128 | |
| { 3510, 7, 1, 0, 0, "VPSHUFDmi", 0|(1<<MCID::MayLoad), 0x2e1804146ULL, NULL, NULL, OperandInfo49 }, // Inst #3510 = VPSHUFDmi | |
| { 3511, 3, 1, 0, 0, "VPSHUFDri", 0, 0x2e1804145ULL, NULL, NULL, OperandInfo50 }, // Inst #3511 = VPSHUFDri | |
| { 3512, 7, 1, 0, 0, "VPSHUFHWmi", 0|(1<<MCID::MayLoad), 0x2e1804c06ULL, NULL, NULL, OperandInfo49 }, // Inst #3512 = VPSHUFHWmi | |
| { 3513, 3, 1, 0, 0, "VPSHUFHWri", 0, 0x2e1804c05ULL, NULL, NULL, OperandInfo50 }, // Inst #3513 = VPSHUFHWri | |
| { 3514, 7, 1, 0, 0, "VPSHUFLWmi", 0|(1<<MCID::MayLoad), 0x2e1804b06ULL, NULL, NULL, OperandInfo49 }, // Inst #3514 = VPSHUFLWmi | |
| { 3515, 3, 1, 0, 0, "VPSHUFLWri", 0, 0x2e1804b05ULL, NULL, NULL, OperandInfo50 }, // Inst #3515 = VPSHUFLWri | |
| { 3516, 7, 1, 0, 0, "VPSIGNBrm128", 0|(1<<MCID::MayLoad), 0xa11800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3516 = VPSIGNBrm128 | |
| { 3517, 3, 1, 0, 0, "VPSIGNBrr128", 0, 0xa11800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3517 = VPSIGNBrr128 | |
| { 3518, 7, 1, 0, 0, "VPSIGNDrm128", 0|(1<<MCID::MayLoad), 0xa15800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3518 = VPSIGNDrm128 | |
| { 3519, 3, 1, 0, 0, "VPSIGNDrr128", 0, 0xa15800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3519 = VPSIGNDrr128 | |
| { 3520, 7, 1, 0, 0, "VPSIGNWrm128", 0|(1<<MCID::MayLoad), 0xa13800d46ULL, NULL, NULL, OperandInfo137 }, // Inst #3520 = VPSIGNWrm128 | |
| { 3521, 3, 1, 0, 0, "VPSIGNWrr128", 0, 0xa13800d45ULL, NULL, NULL, OperandInfo138 }, // Inst #3521 = VPSIGNWrr128 | |
| { 3522, 3, 1, 0, 0, "VPSLLDQri", 0, 0xae7804157ULL, NULL, NULL, OperandInfo50 }, // Inst #3522 = VPSLLDQri | |
| { 3523, 3, 1, 0, 0, "VPSLLDri", 0, 0xae5804156ULL, NULL, NULL, OperandInfo50 }, // Inst #3523 = VPSLLDri | |
| { 3524, 7, 1, 0, 0, "VPSLLDrm", 0|(1<<MCID::MayLoad), 0xbe5800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3524 = VPSLLDrm | |
| { 3525, 3, 1, 0, 0, "VPSLLDrr", 0, 0xbe5800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3525 = VPSLLDrr | |
| { 3526, 3, 1, 0, 0, "VPSLLQri", 0, 0xae7804156ULL, NULL, NULL, OperandInfo50 }, // Inst #3526 = VPSLLQri | |
| { 3527, 7, 1, 0, 0, "VPSLLQrm", 0|(1<<MCID::MayLoad), 0xbe7800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3527 = VPSLLQrm | |
| { 3528, 3, 1, 0, 0, "VPSLLQrr", 0, 0xbe7800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3528 = VPSLLQrr | |
| { 3529, 3, 1, 0, 0, "VPSLLWri", 0, 0xae3804156ULL, NULL, NULL, OperandInfo50 }, // Inst #3529 = VPSLLWri | |
| { 3530, 7, 1, 0, 0, "VPSLLWrm", 0|(1<<MCID::MayLoad), 0xbe3800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3530 = VPSLLWrm | |
| { 3531, 3, 1, 0, 0, "VPSLLWrr", 0, 0xbe3800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3531 = VPSLLWrr | |
| { 3532, 3, 1, 0, 0, "VPSRADri", 0, 0xae5804154ULL, NULL, NULL, OperandInfo50 }, // Inst #3532 = VPSRADri | |
| { 3533, 7, 1, 0, 0, "VPSRADrm", 0|(1<<MCID::MayLoad), 0xbc5800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3533 = VPSRADrm | |
| { 3534, 3, 1, 0, 0, "VPSRADrr", 0, 0xbc5800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3534 = VPSRADrr | |
| { 3535, 3, 1, 0, 0, "VPSRAWri", 0, 0xae3804154ULL, NULL, NULL, OperandInfo50 }, // Inst #3535 = VPSRAWri | |
| { 3536, 7, 1, 0, 0, "VPSRAWrm", 0|(1<<MCID::MayLoad), 0xbc3800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3536 = VPSRAWrm | |
| { 3537, 3, 1, 0, 0, "VPSRAWrr", 0, 0xbc3800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3537 = VPSRAWrr | |
| { 3538, 3, 1, 0, 0, "VPSRLDQri", 0, 0xae7804153ULL, NULL, NULL, OperandInfo50 }, // Inst #3538 = VPSRLDQri | |
| { 3539, 3, 1, 0, 0, "VPSRLDri", 0, 0xae5804152ULL, NULL, NULL, OperandInfo50 }, // Inst #3539 = VPSRLDri | |
| { 3540, 7, 1, 0, 0, "VPSRLDrm", 0|(1<<MCID::MayLoad), 0xba5800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3540 = VPSRLDrm | |
| { 3541, 3, 1, 0, 0, "VPSRLDrr", 0, 0xba5800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3541 = VPSRLDrr | |
| { 3542, 3, 1, 0, 0, "VPSRLQri", 0, 0xae7804152ULL, NULL, NULL, OperandInfo50 }, // Inst #3542 = VPSRLQri | |
| { 3543, 7, 1, 0, 0, "VPSRLQrm", 0|(1<<MCID::MayLoad), 0xba7800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3543 = VPSRLQrm | |
| { 3544, 3, 1, 0, 0, "VPSRLQrr", 0, 0xba7800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3544 = VPSRLQrr | |
| { 3545, 3, 1, 0, 0, "VPSRLWri", 0, 0xae3804152ULL, NULL, NULL, OperandInfo50 }, // Inst #3545 = VPSRLWri | |
| { 3546, 7, 1, 0, 0, "VPSRLWrm", 0|(1<<MCID::MayLoad), 0xba3800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3546 = VPSRLWrm | |
| { 3547, 3, 1, 0, 0, "VPSRLWrr", 0, 0xba3800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3547 = VPSRLWrr | |
| { 3548, 7, 1, 0, 0, "VPSUBBrm", 0|(1<<MCID::MayLoad), 0xbf1800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3548 = VPSUBBrm | |
| { 3549, 3, 1, 0, 0, "VPSUBBrr", 0, 0xbf1800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3549 = VPSUBBrr | |
| { 3550, 7, 1, 0, 0, "VPSUBDrm", 0|(1<<MCID::MayLoad), 0xbf5800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3550 = VPSUBDrm | |
| { 3551, 3, 1, 0, 0, "VPSUBDrr", 0, 0xbf5800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3551 = VPSUBDrr | |
| { 3552, 7, 1, 0, 0, "VPSUBQrm", 0|(1<<MCID::MayLoad), 0xbf7800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3552 = VPSUBQrm | |
| { 3553, 3, 1, 0, 0, "VPSUBQrr", 0, 0xbf7800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3553 = VPSUBQrr | |
| { 3554, 7, 1, 0, 0, "VPSUBSBrm", 0|(1<<MCID::MayLoad), 0xbd1800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3554 = VPSUBSBrm | |
| { 3555, 3, 1, 0, 0, "VPSUBSBrr", 0, 0xbd1800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3555 = VPSUBSBrr | |
| { 3556, 7, 1, 0, 0, "VPSUBSWrm", 0|(1<<MCID::MayLoad), 0xbd3800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3556 = VPSUBSWrm | |
| { 3557, 3, 1, 0, 0, "VPSUBSWrr", 0, 0xbd3800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3557 = VPSUBSWrr | |
| { 3558, 7, 1, 0, 0, "VPSUBUSBrm", 0|(1<<MCID::MayLoad), 0xbb1800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3558 = VPSUBUSBrm | |
| { 3559, 3, 1, 0, 0, "VPSUBUSBrr", 0, 0xbb1800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3559 = VPSUBUSBrr | |
| { 3560, 7, 1, 0, 0, "VPSUBUSWrm", 0|(1<<MCID::MayLoad), 0xbb3800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3560 = VPSUBUSWrm | |
| { 3561, 3, 1, 0, 0, "VPSUBUSWrr", 0, 0xbb3800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3561 = VPSUBUSWrr | |
| { 3562, 7, 1, 0, 0, "VPSUBWrm", 0|(1<<MCID::MayLoad), 0xbf3800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3562 = VPSUBWrm | |
| { 3563, 3, 1, 0, 0, "VPSUBWrr", 0, 0xbf3800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3563 = VPSUBWrr | |
| { 3564, 6, 0, 0, 0, "VPTESTYrm", 0|(1<<MCID::MayLoad), 0x22f800d46ULL, NULL, ImplicitList1, OperandInfo233 }, // Inst #3564 = VPTESTYrm | |
| { 3565, 2, 0, 0, 0, "VPTESTYrr", 0, 0x22f800d45ULL, NULL, ImplicitList1, OperandInfo237 }, // Inst #3565 = VPTESTYrr | |
| { 3566, 6, 0, 0, 0, "VPTESTrm", 0|(1<<MCID::MayLoad), 0x22f800d46ULL, NULL, ImplicitList1, OperandInfo47 }, // Inst #3566 = VPTESTrm | |
| { 3567, 2, 0, 0, 0, "VPTESTrr", 0, 0x22f800d45ULL, NULL, ImplicitList1, OperandInfo48 }, // Inst #3567 = VPTESTrr | |
| { 3568, 7, 1, 0, 0, "VPUNPCKHBWrm", 0|(1<<MCID::MayLoad), 0xad1800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3568 = VPUNPCKHBWrm | |
| { 3569, 3, 1, 0, 0, "VPUNPCKHBWrr", 0, 0xad1800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3569 = VPUNPCKHBWrr | |
| { 3570, 7, 1, 0, 0, "VPUNPCKHDQrm", 0|(1<<MCID::MayLoad), 0xad5800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3570 = VPUNPCKHDQrm | |
| { 3571, 3, 1, 0, 0, "VPUNPCKHDQrr", 0, 0xad5800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3571 = VPUNPCKHDQrr | |
| { 3572, 7, 1, 0, 0, "VPUNPCKHQDQrm", 0|(1<<MCID::MayLoad), 0xadb800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3572 = VPUNPCKHQDQrm | |
| { 3573, 3, 1, 0, 0, "VPUNPCKHQDQrr", 0, 0xadb800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3573 = VPUNPCKHQDQrr | |
| { 3574, 7, 1, 0, 0, "VPUNPCKHWDrm", 0|(1<<MCID::MayLoad), 0xad3800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3574 = VPUNPCKHWDrm | |
| { 3575, 3, 1, 0, 0, "VPUNPCKHWDrr", 0, 0xad3800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3575 = VPUNPCKHWDrr | |
| { 3576, 7, 1, 0, 0, "VPUNPCKLBWrm", 0|(1<<MCID::MayLoad), 0xac1800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3576 = VPUNPCKLBWrm | |
| { 3577, 3, 1, 0, 0, "VPUNPCKLBWrr", 0, 0xac1800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3577 = VPUNPCKLBWrr | |
| { 3578, 7, 1, 0, 0, "VPUNPCKLDQrm", 0|(1<<MCID::MayLoad), 0xac5800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3578 = VPUNPCKLDQrm | |
| { 3579, 3, 1, 0, 0, "VPUNPCKLDQrr", 0, 0xac5800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3579 = VPUNPCKLDQrr | |
| { 3580, 7, 1, 0, 0, "VPUNPCKLQDQrm", 0|(1<<MCID::MayLoad), 0xad9800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3580 = VPUNPCKLQDQrm | |
| { 3581, 3, 1, 0, 0, "VPUNPCKLQDQrr", 0, 0xad9800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3581 = VPUNPCKLQDQrr | |
| { 3582, 7, 1, 0, 0, "VPUNPCKLWDrm", 0|(1<<MCID::MayLoad), 0xac3800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3582 = VPUNPCKLWDrm | |
| { 3583, 3, 1, 0, 0, "VPUNPCKLWDrr", 0, 0xac3800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3583 = VPUNPCKLWDrr | |
| { 3584, 7, 1, 0, 0, "VPXORrm", 0|(1<<MCID::MayLoad), 0xbdf800146ULL, NULL, NULL, OperandInfo137 }, // Inst #3584 = VPXORrm | |
| { 3585, 3, 1, 0, 0, "VPXORrr", 0|(1<<MCID::Commutable), 0xbdf800145ULL, NULL, NULL, OperandInfo138 }, // Inst #3585 = VPXORrr | |
| { 3586, 6, 1, 0, 0, "VRCPPSYm", 0|(1<<MCID::MayLoad), 0x2a6800106ULL, NULL, NULL, OperandInfo233 }, // Inst #3586 = VRCPPSYm | |
| { 3587, 6, 1, 0, 0, "VRCPPSYm_Int", 0|(1<<MCID::MayLoad), 0x2a6800106ULL, NULL, NULL, OperandInfo233 }, // Inst #3587 = VRCPPSYm_Int | |
| { 3588, 2, 1, 0, 0, "VRCPPSYr", 0, 0x2a6800105ULL, NULL, NULL, OperandInfo237 }, // Inst #3588 = VRCPPSYr | |
| { 3589, 2, 1, 0, 0, "VRCPPSYr_Int", 0, 0x2a6800105ULL, NULL, NULL, OperandInfo237 }, // Inst #3589 = VRCPPSYr_Int | |
| { 3590, 6, 1, 0, 0, "VRCPPSm", 0|(1<<MCID::MayLoad), 0x2a6800106ULL, NULL, NULL, OperandInfo47 }, // Inst #3590 = VRCPPSm | |
| { 3591, 6, 1, 0, 0, "VRCPPSm_Int", 0|(1<<MCID::MayLoad), 0x2a6800106ULL, NULL, NULL, OperandInfo47 }, // Inst #3591 = VRCPPSm_Int | |
| { 3592, 2, 1, 0, 0, "VRCPPSr", 0, 0x2a6800105ULL, NULL, NULL, OperandInfo48 }, // Inst #3592 = VRCPPSr | |
| { 3593, 2, 1, 0, 0, "VRCPPSr_Int", 0, 0x2a6800105ULL, NULL, NULL, OperandInfo48 }, // Inst #3593 = VRCPPSr_Int | |
| { 3594, 7, 1, 0, 0, "VRCPSSm", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x4aa6000c06ULL, NULL, NULL, OperandInfo225 }, // Inst #3594 = VRCPSSm | |
| { 3595, 7, 1, 0, 0, "VRCPSSm_Int", 0|(1<<MCID::UnmodeledSideEffects), 0x4aa6000c06ULL, NULL, NULL, OperandInfo261 }, // Inst #3595 = VRCPSSm_Int | |
| { 3596, 3, 1, 0, 0, "VRCPSSr", 0|(1<<MCID::UnmodeledSideEffects), 0x4aa6000c05ULL, NULL, NULL, OperandInfo226 }, // Inst #3596 = VRCPSSr | |
| { 3597, 7, 1, 0, 0, "VROUNDPDm", 0|(1<<MCID::MayLoad), 0x213804e46ULL, NULL, NULL, OperandInfo49 }, // Inst #3597 = VROUNDPDm | |
| { 3598, 7, 1, 0, 0, "VROUNDPDm_AVX", 0|(1<<MCID::UnmodeledSideEffects), 0x213804e46ULL, NULL, NULL, OperandInfo49 }, // Inst #3598 = VROUNDPDm_AVX | |
| { 3599, 3, 1, 0, 0, "VROUNDPDr", 0, 0x213804e45ULL, NULL, NULL, OperandInfo50 }, // Inst #3599 = VROUNDPDr | |
| { 3600, 3, 1, 0, 0, "VROUNDPDr_AVX", 0|(1<<MCID::UnmodeledSideEffects), 0x213804e45ULL, NULL, NULL, OperandInfo50 }, // Inst #3600 = VROUNDPDr_AVX | |
| { 3601, 7, 1, 0, 0, "VROUNDPSm", 0|(1<<MCID::MayLoad), 0x210004e46ULL, NULL, NULL, OperandInfo49 }, // Inst #3601 = VROUNDPSm | |
| { 3602, 7, 1, 0, 0, "VROUNDPSm_AVX", 0|(1<<MCID::UnmodeledSideEffects), 0x210004e46ULL, NULL, NULL, OperandInfo49 }, // Inst #3602 = VROUNDPSm_AVX | |
| { 3603, 3, 1, 0, 0, "VROUNDPSr", 0, 0x211804e45ULL, NULL, NULL, OperandInfo50 }, // Inst #3603 = VROUNDPSr | |
| { 3604, 3, 1, 0, 0, "VROUNDPSr_AVX", 0|(1<<MCID::UnmodeledSideEffects), 0x211804e45ULL, NULL, NULL, OperandInfo50 }, // Inst #3604 = VROUNDPSr_AVX | |
| { 3605, 8, 1, 0, 0, "VROUNDSDm", 0|(1<<MCID::MayLoad), 0x4a17804e46ULL, NULL, NULL, OperandInfo136 }, // Inst #3605 = VROUNDSDm | |
| { 3606, 8, 1, 0, 0, "VROUNDSDm_AVX", 0|(1<<MCID::UnmodeledSideEffects), 0x4a17804e46ULL, NULL, NULL, OperandInfo136 }, // Inst #3606 = VROUNDSDm_AVX | |
| { 3607, 4, 1, 0, 0, "VROUNDSDr", 0, 0x4a17804e45ULL, NULL, NULL, OperandInfo86 }, // Inst #3607 = VROUNDSDr | |
| { 3608, 4, 1, 0, 0, "VROUNDSDr_AVX", 0|(1<<MCID::UnmodeledSideEffects), 0x4a17804e45ULL, NULL, NULL, OperandInfo86 }, // Inst #3608 = VROUNDSDr_AVX | |
| { 3609, 8, 1, 0, 0, "VROUNDSSm", 0|(1<<MCID::MayLoad), 0x4a15804e46ULL, NULL, NULL, OperandInfo136 }, // Inst #3609 = VROUNDSSm | |
| { 3610, 8, 1, 0, 0, "VROUNDSSm_AVX", 0|(1<<MCID::UnmodeledSideEffects), 0x4a15804e46ULL, NULL, NULL, OperandInfo136 }, // Inst #3610 = VROUNDSSm_AVX | |
| { 3611, 4, 1, 0, 0, "VROUNDSSr", 0, 0x4a15804e45ULL, NULL, NULL, OperandInfo86 }, // Inst #3611 = VROUNDSSr | |
| { 3612, 4, 1, 0, 0, "VROUNDSSr_AVX", 0|(1<<MCID::UnmodeledSideEffects), 0x4a15804e45ULL, NULL, NULL, OperandInfo86 }, // Inst #3612 = VROUNDSSr_AVX | |
| { 3613, 7, 1, 0, 0, "VROUNDYPDm", 0|(1<<MCID::MayLoad), 0x213804e46ULL, NULL, NULL, OperandInfo257 }, // Inst #3613 = VROUNDYPDm | |
| { 3614, 7, 1, 0, 0, "VROUNDYPDm_AVX", 0|(1<<MCID::UnmodeledSideEffects), 0x213804e46ULL, NULL, NULL, OperandInfo257 }, // Inst #3614 = VROUNDYPDm_AVX | |
| { 3615, 3, 1, 0, 0, "VROUNDYPDr", 0, 0x213804e45ULL, NULL, NULL, OperandInfo258 }, // Inst #3615 = VROUNDYPDr | |
| { 3616, 3, 1, 0, 0, "VROUNDYPDr_AVX", 0|(1<<MCID::UnmodeledSideEffects), 0x213804e45ULL, NULL, NULL, OperandInfo258 }, // Inst #3616 = VROUNDYPDr_AVX | |
| { 3617, 7, 1, 0, 0, "VROUNDYPSm", 0|(1<<MCID::MayLoad), 0x210004e46ULL, NULL, NULL, OperandInfo257 }, // Inst #3617 = VROUNDYPSm | |
| { 3618, 7, 1, 0, 0, "VROUNDYPSm_AVX", 0|(1<<MCID::UnmodeledSideEffects), 0x210004e46ULL, NULL, NULL, OperandInfo257 }, // Inst #3618 = VROUNDYPSm_AVX | |
| { 3619, 3, 1, 0, 0, "VROUNDYPSr", 0, 0x211804e45ULL, NULL, NULL, OperandInfo258 }, // Inst #3619 = VROUNDYPSr | |
| { 3620, 3, 1, 0, 0, "VROUNDYPSr_AVX", 0|(1<<MCID::UnmodeledSideEffects), 0x211804e45ULL, NULL, NULL, OperandInfo258 }, // Inst #3620 = VROUNDYPSr_AVX | |
| { 3621, 6, 1, 0, 0, "VRSQRTPSYm", 0|(1<<MCID::MayLoad), 0x2a4800106ULL, NULL, NULL, OperandInfo233 }, // Inst #3621 = VRSQRTPSYm | |
| { 3622, 6, 1, 0, 0, "VRSQRTPSYm_Int", 0|(1<<MCID::MayLoad), 0x2a4800106ULL, NULL, NULL, OperandInfo233 }, // Inst #3622 = VRSQRTPSYm_Int | |
| { 3623, 2, 1, 0, 0, "VRSQRTPSYr", 0, 0x2a4800105ULL, NULL, NULL, OperandInfo237 }, // Inst #3623 = VRSQRTPSYr | |
| { 3624, 2, 1, 0, 0, "VRSQRTPSYr_Int", 0, 0x2a4800105ULL, NULL, NULL, OperandInfo237 }, // Inst #3624 = VRSQRTPSYr_Int | |
| { 3625, 6, 1, 0, 0, "VRSQRTPSm", 0|(1<<MCID::MayLoad), 0x2a4800106ULL, NULL, NULL, OperandInfo47 }, // Inst #3625 = VRSQRTPSm | |
| { 3626, 6, 1, 0, 0, "VRSQRTPSm_Int", 0|(1<<MCID::MayLoad), 0x2a4800106ULL, NULL, NULL, OperandInfo47 }, // Inst #3626 = VRSQRTPSm_Int | |
| { 3627, 2, 1, 0, 0, "VRSQRTPSr", 0, 0x2a4800105ULL, NULL, NULL, OperandInfo48 }, // Inst #3627 = VRSQRTPSr | |
| { 3628, 2, 1, 0, 0, "VRSQRTPSr_Int", 0, 0x2a4800105ULL, NULL, NULL, OperandInfo48 }, // Inst #3628 = VRSQRTPSr_Int | |
| { 3629, 7, 1, 0, 0, "VRSQRTSSm", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x4aa4000c06ULL, NULL, NULL, OperandInfo225 }, // Inst #3629 = VRSQRTSSm | |
| { 3630, 7, 1, 0, 0, "VRSQRTSSm_Int", 0|(1<<MCID::UnmodeledSideEffects), 0x4aa4000c06ULL, NULL, NULL, OperandInfo261 }, // Inst #3630 = VRSQRTSSm_Int | |
| { 3631, 3, 1, 0, 0, "VRSQRTSSr", 0|(1<<MCID::UnmodeledSideEffects), 0x4aa4000c05ULL, NULL, NULL, OperandInfo226 }, // Inst #3631 = VRSQRTSSr | |
| { 3632, 8, 1, 0, 0, "VSHUFPDYrmi", 0|(1<<MCID::MayLoad), 0xb8d004146ULL, NULL, NULL, OperandInfo228 }, // Inst #3632 = VSHUFPDYrmi | |
| { 3633, 4, 1, 0, 0, "VSHUFPDYrri", 0, 0xb8d004145ULL, NULL, NULL, OperandInfo87 }, // Inst #3633 = VSHUFPDYrri | |
| { 3634, 8, 1, 0, 0, "VSHUFPDrmi", 0|(1<<MCID::MayLoad), 0xb8d004146ULL, NULL, NULL, OperandInfo136 }, // Inst #3634 = VSHUFPDrmi | |
| { 3635, 4, 1, 0, 0, "VSHUFPDrri", 0, 0xb8d004145ULL, NULL, NULL, OperandInfo86 }, // Inst #3635 = VSHUFPDrri | |
| { 3636, 8, 1, 0, 0, "VSHUFPSYrmi", 0|(1<<MCID::MayLoad), 0xb8c804106ULL, NULL, NULL, OperandInfo228 }, // Inst #3636 = VSHUFPSYrmi | |
| { 3637, 4, 1, 0, 0, "VSHUFPSYrri", 0, 0xb8c804105ULL, NULL, NULL, OperandInfo87 }, // Inst #3637 = VSHUFPSYrri | |
| { 3638, 8, 1, 0, 0, "VSHUFPSrmi", 0|(1<<MCID::MayLoad), 0xb8c804106ULL, NULL, NULL, OperandInfo136 }, // Inst #3638 = VSHUFPSrmi | |
| { 3639, 4, 1, 0, 0, "VSHUFPSrri", 0, 0xb8c804105ULL, NULL, NULL, OperandInfo86 }, // Inst #3639 = VSHUFPSrri | |
| { 3640, 6, 1, 0, 0, "VSQRTPDYm", 0|(1<<MCID::MayLoad), 0x2a3000146ULL, NULL, NULL, OperandInfo233 }, // Inst #3640 = VSQRTPDYm | |
| { 3641, 6, 1, 0, 0, "VSQRTPDYm_Int", 0|(1<<MCID::MayLoad), 0x2a3000146ULL, NULL, NULL, OperandInfo233 }, // Inst #3641 = VSQRTPDYm_Int | |
| { 3642, 2, 1, 0, 0, "VSQRTPDYr", 0, 0x2a3000145ULL, NULL, NULL, OperandInfo237 }, // Inst #3642 = VSQRTPDYr | |
| { 3643, 2, 1, 0, 0, "VSQRTPDYr_Int", 0, 0x2a3000145ULL, NULL, NULL, OperandInfo237 }, // Inst #3643 = VSQRTPDYr_Int | |
| { 3644, 6, 1, 0, 0, "VSQRTPDm", 0|(1<<MCID::MayLoad), 0x2a3000146ULL, NULL, NULL, OperandInfo47 }, // Inst #3644 = VSQRTPDm | |
| { 3645, 6, 1, 0, 0, "VSQRTPDm_Int", 0|(1<<MCID::MayLoad), 0x2a3000146ULL, NULL, NULL, OperandInfo47 }, // Inst #3645 = VSQRTPDm_Int | |
| { 3646, 2, 1, 0, 0, "VSQRTPDr", 0, 0x2a3000145ULL, NULL, NULL, OperandInfo48 }, // Inst #3646 = VSQRTPDr | |
| { 3647, 2, 1, 0, 0, "VSQRTPDr_Int", 0, 0x2a3000145ULL, NULL, NULL, OperandInfo48 }, // Inst #3647 = VSQRTPDr_Int | |
| { 3648, 6, 1, 0, 0, "VSQRTPSYm", 0|(1<<MCID::MayLoad), 0x2a2800106ULL, NULL, NULL, OperandInfo233 }, // Inst #3648 = VSQRTPSYm | |
| { 3649, 6, 1, 0, 0, "VSQRTPSYm_Int", 0|(1<<MCID::MayLoad), 0x2a2800106ULL, NULL, NULL, OperandInfo233 }, // Inst #3649 = VSQRTPSYm_Int | |
| { 3650, 2, 1, 0, 0, "VSQRTPSYr", 0, 0x2a2800105ULL, NULL, NULL, OperandInfo237 }, // Inst #3650 = VSQRTPSYr | |
| { 3651, 2, 1, 0, 0, "VSQRTPSYr_Int", 0, 0x2a2800105ULL, NULL, NULL, OperandInfo237 }, // Inst #3651 = VSQRTPSYr_Int | |
| { 3652, 6, 1, 0, 0, "VSQRTPSm", 0|(1<<MCID::MayLoad), 0x2a2800106ULL, NULL, NULL, OperandInfo47 }, // Inst #3652 = VSQRTPSm | |
| { 3653, 6, 1, 0, 0, "VSQRTPSm_Int", 0|(1<<MCID::MayLoad), 0x2a2800106ULL, NULL, NULL, OperandInfo47 }, // Inst #3653 = VSQRTPSm_Int | |
| { 3654, 2, 1, 0, 0, "VSQRTPSr", 0, 0x2a2800105ULL, NULL, NULL, OperandInfo48 }, // Inst #3654 = VSQRTPSr | |
| { 3655, 2, 1, 0, 0, "VSQRTPSr_Int", 0, 0x2a2800105ULL, NULL, NULL, OperandInfo48 }, // Inst #3655 = VSQRTPSr_Int | |
| { 3656, 7, 1, 0, 0, "VSQRTSDm", 0|(1<<MCID::UnmodeledSideEffects), 0x4aa2000b06ULL, NULL, NULL, OperandInfo223 }, // Inst #3656 = VSQRTSDm | |
| { 3657, 7, 1, 0, 0, "VSQRTSDm_Int", 0|(1<<MCID::UnmodeledSideEffects), 0x4aa2000b06ULL, NULL, NULL, OperandInfo137 }, // Inst #3657 = VSQRTSDm_Int | |
| { 3658, 3, 1, 0, 0, "VSQRTSDr", 0|(1<<MCID::UnmodeledSideEffects), 0x4aa2000b05ULL, NULL, NULL, OperandInfo224 }, // Inst #3658 = VSQRTSDr | |
| { 3659, 7, 1, 0, 0, "VSQRTSSm", 0|(1<<MCID::MayLoad)|(1<<MCID::UnmodeledSideEffects), 0x4aa2000c06ULL, NULL, NULL, OperandInfo225 }, // Inst #3659 = VSQRTSSm | |
| { 3660, 7, 1, 0, 0, "VSQRTSSm_Int", 0|(1<<MCID::UnmodeledSideEffects), 0x4aa2000c06ULL, NULL, NULL, OperandInfo261 }, // Inst #3660 = VSQRTSSm_Int | |
| { 3661, 3, 1, 0, 0, "VSQRTSSr", 0|(1<<MCID::UnmodeledSideEffects), 0x4aa2000c05ULL, NULL, NULL, OperandInfo226 }, // Inst #3661 = VSQRTSSr | |
| { 3662, 5, 0, 0, 0, "VSTMXCSR", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x35c80011bULL, NULL, NULL, OperandInfo38 }, // Inst #3662 = VSTMXCSR | |
| { 3663, 7, 1, 0, 0, "VSUBPDYrm", 0|(1<<MCID::MayLoad), 0xab9000146ULL, NULL, NULL, OperandInfo221 }, // Inst #3663 = VSUBPDYrm | |
| { 3664, 3, 1, 0, 0, "VSUBPDYrr", 0, 0xab9000145ULL, NULL, NULL, OperandInfo222 }, // Inst #3664 = VSUBPDYrr | |
| { 3665, 7, 1, 0, 0, "VSUBPDrm", 0|(1<<MCID::MayLoad), 0xab9000146ULL, NULL, NULL, OperandInfo137 }, // Inst #3665 = VSUBPDrm | |
| { 3666, 3, 1, 0, 0, "VSUBPDrr", 0, 0xab9000145ULL, NULL, NULL, OperandInfo138 }, // Inst #3666 = VSUBPDrr | |
| { 3667, 7, 1, 0, 0, "VSUBPSYrm", 0|(1<<MCID::MayLoad), 0xab8800106ULL, NULL, NULL, OperandInfo221 }, // Inst #3667 = VSUBPSYrm | |
| { 3668, 3, 1, 0, 0, "VSUBPSYrr", 0, 0xab8800105ULL, NULL, NULL, OperandInfo222 }, // Inst #3668 = VSUBPSYrr | |
| { 3669, 7, 1, 0, 0, "VSUBPSrm", 0|(1<<MCID::MayLoad), 0xab8800106ULL, NULL, NULL, OperandInfo137 }, // Inst #3669 = VSUBPSrm | |
| { 3670, 3, 1, 0, 0, "VSUBPSrr", 0, 0xab8800105ULL, NULL, NULL, OperandInfo138 }, // Inst #3670 = VSUBPSrr | |
| { 3671, 7, 1, 0, 0, "VSUBSDrm", 0|(1<<MCID::MayLoad), 0x4ab8000b06ULL, NULL, NULL, OperandInfo223 }, // Inst #3671 = VSUBSDrm | |
| { 3672, 7, 1, 0, 0, "VSUBSDrm_Int", 0|(1<<MCID::MayLoad), 0x4ab8000b06ULL, NULL, NULL, OperandInfo137 }, // Inst #3672 = VSUBSDrm_Int | |
| { 3673, 3, 1, 0, 0, "VSUBSDrr", 0, 0x4ab8000b05ULL, NULL, NULL, OperandInfo224 }, // Inst #3673 = VSUBSDrr | |
| { 3674, 3, 1, 0, 0, "VSUBSDrr_Int", 0, 0x4ab8000b05ULL, NULL, NULL, OperandInfo138 }, // Inst #3674 = VSUBSDrr_Int | |
| { 3675, 7, 1, 0, 0, "VSUBSSrm", 0|(1<<MCID::MayLoad), 0x4ab8000c06ULL, NULL, NULL, OperandInfo225 }, // Inst #3675 = VSUBSSrm | |
| { 3676, 7, 1, 0, 0, "VSUBSSrm_Int", 0|(1<<MCID::MayLoad), 0x4ab8000c06ULL, NULL, NULL, OperandInfo137 }, // Inst #3676 = VSUBSSrm_Int | |
| { 3677, 3, 1, 0, 0, "VSUBSSrr", 0, 0x4ab8000c05ULL, NULL, NULL, OperandInfo226 }, // Inst #3677 = VSUBSSrr | |
| { 3678, 3, 1, 0, 0, "VSUBSSrr_Int", 0, 0x4ab8000c05ULL, NULL, NULL, OperandInfo138 }, // Inst #3678 = VSUBSSrr_Int | |
| { 3679, 6, 0, 0, 0, "VTESTPDYrm", 0|(1<<MCID::MayLoad), 0x21f800d46ULL, NULL, ImplicitList1, OperandInfo233 }, // Inst #3679 = VTESTPDYrm | |
| { 3680, 2, 0, 0, 0, "VTESTPDYrr", 0, 0x21f800d45ULL, NULL, ImplicitList1, OperandInfo237 }, // Inst #3680 = VTESTPDYrr | |
| { 3681, 6, 0, 0, 0, "VTESTPDrm", 0|(1<<MCID::MayLoad), 0x21f800d46ULL, NULL, ImplicitList1, OperandInfo47 }, // Inst #3681 = VTESTPDrm | |
| { 3682, 2, 0, 0, 0, "VTESTPDrr", 0, 0x21f800d45ULL, NULL, ImplicitList1, OperandInfo48 }, // Inst #3682 = VTESTPDrr | |
| { 3683, 6, 0, 0, 0, "VTESTPSYrm", 0|(1<<MCID::MayLoad), 0x21d800d46ULL, NULL, ImplicitList1, OperandInfo233 }, // Inst #3683 = VTESTPSYrm | |
| { 3684, 2, 0, 0, 0, "VTESTPSYrr", 0, 0x21d800d45ULL, NULL, ImplicitList1, OperandInfo237 }, // Inst #3684 = VTESTPSYrr | |
| { 3685, 6, 0, 0, 0, "VTESTPSrm", 0|(1<<MCID::MayLoad), 0x21d800d46ULL, NULL, ImplicitList1, OperandInfo47 }, // Inst #3685 = VTESTPSrm | |
| { 3686, 2, 0, 0, 0, "VTESTPSrr", 0, 0x21d800d45ULL, NULL, ImplicitList1, OperandInfo48 }, // Inst #3686 = VTESTPSrr | |
| { 3687, 6, 0, 0, 0, "VUCOMISDrm", 0|(1<<MCID::MayLoad), 0x425d000146ULL, NULL, ImplicitList1, OperandInfo101 }, // Inst #3687 = VUCOMISDrm | |
| { 3688, 2, 0, 0, 0, "VUCOMISDrr", 0, 0x425d000145ULL, NULL, ImplicitList1, OperandInfo123 }, // Inst #3688 = VUCOMISDrr | |
| { 3689, 6, 0, 0, 0, "VUCOMISSrm", 0|(1<<MCID::MayLoad), 0x425c800106ULL, NULL, ImplicitList1, OperandInfo99 }, // Inst #3689 = VUCOMISSrm | |
| { 3690, 2, 0, 0, 0, "VUCOMISSrr", 0, 0x425c800105ULL, NULL, ImplicitList1, OperandInfo124 }, // Inst #3690 = VUCOMISSrr | |
| { 3691, 7, 1, 0, 0, "VUNPCKHPDYrm", 0|(1<<MCID::MayLoad), 0xa2b000146ULL, NULL, NULL, OperandInfo221 }, // Inst #3691 = VUNPCKHPDYrm | |
| { 3692, 3, 1, 0, 0, "VUNPCKHPDYrr", 0, 0xa2b000145ULL, NULL, NULL, OperandInfo222 }, // Inst #3692 = VUNPCKHPDYrr | |
| { 3693, 7, 1, 0, 0, "VUNPCKHPDrm", 0|(1<<MCID::MayLoad), 0xa2b000146ULL, NULL, NULL, OperandInfo137 }, // Inst #3693 = VUNPCKHPDrm | |
| { 3694, 3, 1, 0, 0, "VUNPCKHPDrr", 0, 0xa2b000145ULL, NULL, NULL, OperandInfo138 }, // Inst #3694 = VUNPCKHPDrr | |
| { 3695, 7, 1, 0, 0, "VUNPCKHPSYrm", 0|(1<<MCID::MayLoad), 0xa2a800106ULL, NULL, NULL, OperandInfo221 }, // Inst #3695 = VUNPCKHPSYrm | |
| { 3696, 3, 1, 0, 0, "VUNPCKHPSYrr", 0, 0xa2a800105ULL, NULL, NULL, OperandInfo222 }, // Inst #3696 = VUNPCKHPSYrr | |
| { 3697, 7, 1, 0, 0, "VUNPCKHPSrm", 0|(1<<MCID::MayLoad), 0xa2a800106ULL, NULL, NULL, OperandInfo137 }, // Inst #3697 = VUNPCKHPSrm | |
| { 3698, 3, 1, 0, 0, "VUNPCKHPSrr", 0, 0xa2a800105ULL, NULL, NULL, OperandInfo138 }, // Inst #3698 = VUNPCKHPSrr | |
| { 3699, 7, 1, 0, 0, "VUNPCKLPDYrm", 0|(1<<MCID::MayLoad), 0xa29000146ULL, NULL, NULL, OperandInfo221 }, // Inst #3699 = VUNPCKLPDYrm | |
| { 3700, 3, 1, 0, 0, "VUNPCKLPDYrr", 0, 0xa29000145ULL, NULL, NULL, OperandInfo222 }, // Inst #3700 = VUNPCKLPDYrr | |
| { 3701, 7, 1, 0, 0, "VUNPCKLPDrm", 0|(1<<MCID::MayLoad), 0xa29000146ULL, NULL, NULL, OperandInfo137 }, // Inst #3701 = VUNPCKLPDrm | |
| { 3702, 3, 1, 0, 0, "VUNPCKLPDrr", 0, 0xa29000145ULL, NULL, NULL, OperandInfo138 }, // Inst #3702 = VUNPCKLPDrr | |
| { 3703, 7, 1, 0, 0, "VUNPCKLPSYrm", 0|(1<<MCID::MayLoad), 0xa28800106ULL, NULL, NULL, OperandInfo221 }, // Inst #3703 = VUNPCKLPSYrm | |
| { 3704, 3, 1, 0, 0, "VUNPCKLPSYrr", 0, 0xa28800105ULL, NULL, NULL, OperandInfo222 }, // Inst #3704 = VUNPCKLPSYrr | |
| { 3705, 7, 1, 0, 0, "VUNPCKLPSrm", 0|(1<<MCID::MayLoad), 0xa28800106ULL, NULL, NULL, OperandInfo137 }, // Inst #3705 = VUNPCKLPSrm | |
| { 3706, 3, 1, 0, 0, "VUNPCKLPSrr", 0, 0xa28800105ULL, NULL, NULL, OperandInfo138 }, // Inst #3706 = VUNPCKLPSrr | |
| { 3707, 7, 1, 0, 0, "VXORPDYrm", 0|(1<<MCID::MayLoad), 0xaaf000146ULL, NULL, NULL, OperandInfo221 }, // Inst #3707 = VXORPDYrm | |
| { 3708, 3, 1, 0, 0, "VXORPDYrr", 0|(1<<MCID::Commutable), 0xaaf000145ULL, NULL, NULL, OperandInfo222 }, // Inst #3708 = VXORPDYrr | |
| { 3709, 7, 1, 0, 0, "VXORPDrm", 0|(1<<MCID::MayLoad), 0xaaf000146ULL, NULL, NULL, OperandInfo137 }, // Inst #3709 = VXORPDrm | |
| { 3710, 3, 1, 0, 0, "VXORPDrr", 0|(1<<MCID::Commutable), 0xaaf000145ULL, NULL, NULL, OperandInfo138 }, // Inst #3710 = VXORPDrr | |
| { 3711, 7, 1, 0, 0, "VXORPSYrm", 0|(1<<MCID::MayLoad), 0xaae800106ULL, NULL, NULL, OperandInfo221 }, // Inst #3711 = VXORPSYrm | |
| { 3712, 3, 1, 0, 0, "VXORPSYrr", 0|(1<<MCID::Commutable), 0xaae800105ULL, NULL, NULL, OperandInfo222 }, // Inst #3712 = VXORPSYrr | |
| { 3713, 7, 1, 0, 0, "VXORPSrm", 0|(1<<MCID::MayLoad), 0xaae800106ULL, NULL, NULL, OperandInfo137 }, // Inst #3713 = VXORPSrm | |
| { 3714, 3, 1, 0, 0, "VXORPSrr", 0|(1<<MCID::Commutable)|(1<<MCID::UnmodeledSideEffects), 0xaae800105ULL, NULL, NULL, OperandInfo138 }, // Inst #3714 = VXORPSrr | |
| { 3715, 0, 0, 0, 0, "VZEROALL", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x22ee000101ULL, NULL, ImplicitList70, 0 }, // Inst #3715 = VZEROALL | |
| { 3716, 0, 0, 0, 0, "VZEROUPPER", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x2ee000101ULL, NULL, ImplicitList70, 0 }, // Inst #3716 = VZEROUPPER | |
| { 3717, 1, 1, 0, 0, "V_SET0", 0|(1<<MCID::Pseudo)|(1<<MCID::FoldableAsLoad)|(1<<MCID::Rematerializable)|(1<<MCID::CheapAsAMove), 0x0ULL, NULL, NULL, OperandInfo62 }, // Inst #3717 = V_SET0 | |
| { 3718, 1, 1, 0, 0, "V_SETALLONES", 0|(1<<MCID::FoldableAsLoad)|(1<<MCID::Rematerializable)|(1<<MCID::CheapAsAMove), 0xed800160ULL, NULL, NULL, OperandInfo62 }, // Inst #3718 = V_SETALLONES | |
| { 3719, 1, 0, 0, 0, "W64ALLOCA", 0|(1<<MCID::Call)|(1<<MCID::Variadic)|(1<<MCID::UnmodeledSideEffects), 0x1d0018001ULL, ImplicitList8, ImplicitList71, OperandInfo73 }, // Inst #3719 = W64ALLOCA | |
| { 3720, 0, 0, 0, 0, "WAIT", 0|(1<<MCID::UnmodeledSideEffects), 0x136000001ULL, NULL, NULL, 0 }, // Inst #3720 = WAIT | |
| { 3721, 0, 0, 0, 0, "WBINVD", 0|(1<<MCID::UnmodeledSideEffects), 0x12000101ULL, NULL, NULL, 0 }, // Inst #3721 = WBINVD | |
| { 3722, 5, 0, 0, 0, "WINCALL64m", 0|(1<<MCID::Call)|(1<<MCID::MayLoad)|(1<<MCID::Variadic), 0x1fe00001aULL, ImplicitList8, ImplicitList66, OperandInfo38 }, // Inst #3722 = WINCALL64m | |
| { 3723, 1, 0, 0, 0, "WINCALL64pcrel32", 0|(1<<MCID::Call)|(1<<MCID::Variadic)|(1<<MCID::UnmodeledSideEffects), 0x1d0018001ULL, ImplicitList8, ImplicitList66, OperandInfo73 }, // Inst #3723 = WINCALL64pcrel32 | |
| { 3724, 1, 0, 0, 0, "WINCALL64r", 0|(1<<MCID::Call)|(1<<MCID::Variadic), 0x1fe000012ULL, ImplicitList8, ImplicitList66, OperandInfo74 }, // Inst #3724 = WINCALL64r | |
| { 3725, 0, 0, 0, 0, "WIN_ALLOCA", 0|(1<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList6, ImplicitList59, 0 }, // Inst #3725 = WIN_ALLOCA | |
| { 3726, 1, 0, 0, 0, "WRFSBASE", 0|(1<<MCID::UnmodeledSideEffects), 0x15c000c12ULL, NULL, NULL, OperandInfo72 }, // Inst #3726 = WRFSBASE | |
| { 3727, 1, 0, 0, 0, "WRFSBASE64", 0|(1<<MCID::UnmodeledSideEffects), 0x15c002c12ULL, NULL, NULL, OperandInfo74 }, // Inst #3727 = WRFSBASE64 | |
| { 3728, 1, 0, 0, 0, "WRGSBASE", 0|(1<<MCID::UnmodeledSideEffects), 0x15c000c13ULL, NULL, NULL, OperandInfo72 }, // Inst #3728 = WRGSBASE | |
| { 3729, 1, 0, 0, 0, "WRGSBASE64", 0|(1<<MCID::UnmodeledSideEffects), 0x15c002c13ULL, NULL, NULL, OperandInfo74 }, // Inst #3729 = WRGSBASE64 | |
| { 3730, 0, 0, 0, 0, "WRMSR", 0|(1<<MCID::UnmodeledSideEffects), 0x60000101ULL, NULL, NULL, 0 }, // Inst #3730 = WRMSR | |
| { 3731, 6, 0, 0, 0, "XADD16rm", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x182000144ULL, NULL, NULL, OperandInfo16 }, // Inst #3731 = XADD16rm | |
| { 3732, 2, 1, 0, 0, "XADD16rr", 0|(1<<MCID::UnmodeledSideEffects), 0x182000143ULL, NULL, NULL, OperandInfo55 }, // Inst #3732 = XADD16rr | |
| { 3733, 6, 0, 0, 0, "XADD32rm", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x182000104ULL, NULL, NULL, OperandInfo20 }, // Inst #3733 = XADD32rm | |
| { 3734, 2, 1, 0, 0, "XADD32rr", 0|(1<<MCID::UnmodeledSideEffects), 0x182000103ULL, NULL, NULL, OperandInfo65 }, // Inst #3734 = XADD32rr | |
| { 3735, 6, 0, 0, 0, "XADD64rm", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x182002104ULL, NULL, NULL, OperandInfo24 }, // Inst #3735 = XADD64rm | |
| { 3736, 2, 1, 0, 0, "XADD64rr", 0|(1<<MCID::UnmodeledSideEffects), 0x182002103ULL, NULL, NULL, OperandInfo66 }, // Inst #3736 = XADD64rr | |
| { 3737, 6, 0, 0, 0, "XADD8rm", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore)|(1<<MCID::UnmodeledSideEffects), 0x180000104ULL, NULL, NULL, OperandInfo28 }, // Inst #3737 = XADD8rm | |
| { 3738, 2, 1, 0, 0, "XADD8rr", 0|(1<<MCID::UnmodeledSideEffects), 0x180000103ULL, NULL, NULL, OperandInfo89 }, // Inst #3738 = XADD8rr | |
| { 3739, 1, 0, 0, 0, "XCHG16ar", 0|(1<<MCID::UnmodeledSideEffects), 0x120000042ULL, NULL, NULL, OperandInfo113 }, // Inst #3739 = XCHG16ar | |
| { 3740, 7, 1, 0, 0, "XCHG16rm", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10e000046ULL, NULL, NULL, OperandInfo18 }, // Inst #3740 = XCHG16rm | |
| { 3741, 3, 1, 0, 0, "XCHG16rr", 0|(1<<MCID::UnmodeledSideEffects), 0x10e000045ULL, NULL, NULL, OperandInfo19 }, // Inst #3741 = XCHG16rr | |
| { 3742, 1, 0, 0, 0, "XCHG32ar", 0|(1<<MCID::UnmodeledSideEffects), 0x120000002ULL, NULL, NULL, OperandInfo72 }, // Inst #3742 = XCHG32ar | |
| { 3743, 1, 0, 0, 0, "XCHG32ar64", 0|(1<<MCID::UnmodeledSideEffects), 0x120000002ULL, NULL, NULL, OperandInfo262 }, // Inst #3743 = XCHG32ar64 | |
| { 3744, 7, 1, 0, 0, "XCHG32rm", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10e000006ULL, NULL, NULL, OperandInfo22 }, // Inst #3744 = XCHG32rm | |
| { 3745, 3, 1, 0, 0, "XCHG32rr", 0|(1<<MCID::UnmodeledSideEffects), 0x10e000005ULL, NULL, NULL, OperandInfo23 }, // Inst #3745 = XCHG32rr | |
| { 3746, 1, 0, 0, 0, "XCHG64ar", 0|(1<<MCID::UnmodeledSideEffects), 0x120002002ULL, NULL, NULL, OperandInfo74 }, // Inst #3746 = XCHG64ar | |
| { 3747, 7, 1, 0, 0, "XCHG64rm", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10e002006ULL, NULL, NULL, OperandInfo26 }, // Inst #3747 = XCHG64rm | |
| { 3748, 3, 1, 0, 0, "XCHG64rr", 0|(1<<MCID::UnmodeledSideEffects), 0x10e002005ULL, NULL, NULL, OperandInfo27 }, // Inst #3748 = XCHG64rr | |
| { 3749, 7, 1, 0, 0, "XCHG8rm", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10c000006ULL, NULL, NULL, OperandInfo30 }, // Inst #3749 = XCHG8rm | |
| { 3750, 3, 1, 0, 0, "XCHG8rr", 0|(1<<MCID::UnmodeledSideEffects), 0x10c000005ULL, NULL, NULL, OperandInfo31 }, // Inst #3750 = XCHG8rr | |
| { 3751, 1, 0, 0, 0, "XCH_F", 0|(1<<MCID::UnmodeledSideEffects), 0x190000402ULL, NULL, NULL, OperandInfo39 }, // Inst #3751 = XCH_F | |
| { 3752, 0, 0, 0, 0, "XCRYPTCBC", 0|(1<<MCID::UnmodeledSideEffects), 0x1a0001001ULL, ImplicitList72, ImplicitList73, 0 }, // Inst #3752 = XCRYPTCBC | |
| { 3753, 0, 0, 0, 0, "XCRYPTCFB", 0|(1<<MCID::UnmodeledSideEffects), 0x1c0001001ULL, ImplicitList72, ImplicitList73, 0 }, // Inst #3753 = XCRYPTCFB | |
| { 3754, 0, 0, 0, 0, "XCRYPTCTR", 0|(1<<MCID::UnmodeledSideEffects), 0x1b0001001ULL, ImplicitList72, ImplicitList73, 0 }, // Inst #3754 = XCRYPTCTR | |
| { 3755, 0, 0, 0, 0, "XCRYPTECB", 0|(1<<MCID::UnmodeledSideEffects), 0x190001001ULL, ImplicitList72, ImplicitList73, 0 }, // Inst #3755 = XCRYPTECB | |
| { 3756, 0, 0, 0, 0, "XCRYPTOFB", 0|(1<<MCID::UnmodeledSideEffects), 0x1d0001001ULL, ImplicitList72, ImplicitList73, 0 }, // Inst #3756 = XCRYPTOFB | |
| { 3757, 0, 0, 0, 0, "XGETBV", 0|(1<<MCID::UnmodeledSideEffects), 0x200012dULL, ImplicitList26, ImplicitList74, 0 }, // Inst #3757 = XGETBV | |
| { 3758, 0, 0, 0, 0, "XLAT", 0|(1<<MCID::UnmodeledSideEffects), 0x1ae000001ULL, NULL, NULL, 0 }, // Inst #3758 = XLAT | |
| { 3759, 1, 0, 0, 0, "XOR16i16", 0|(1<<MCID::UnmodeledSideEffects), 0x6a00c041ULL, ImplicitList2, ImplicitList1, OperandInfo2 }, // Inst #3759 = XOR16i16 | |
| { 3760, 6, 0, 0, 0, "XOR16mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10200c05eULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #3760 = XOR16mi | |
| { 3761, 6, 0, 0, 0, "XOR16mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10600405eULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #3761 = XOR16mi8 | |
| { 3762, 6, 0, 0, 0, "XOR16mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x62000044ULL, NULL, ImplicitList1, OperandInfo16 }, // Inst #3762 = XOR16mr | |
| { 3763, 3, 1, 0, 0, "XOR16ri", 0, 0x10200c056ULL, NULL, ImplicitList1, OperandInfo17 }, // Inst #3763 = XOR16ri | |
| { 3764, 3, 1, 0, 0, "XOR16ri8", 0, 0x106004056ULL, NULL, ImplicitList1, OperandInfo17 }, // Inst #3764 = XOR16ri8 | |
| { 3765, 7, 1, 0, 0, "XOR16rm", 0|(1<<MCID::MayLoad), 0x66000046ULL, NULL, ImplicitList1, OperandInfo18 }, // Inst #3765 = XOR16rm | |
| { 3766, 3, 1, 0, 0, "XOR16rr", 0|(1<<MCID::Commutable), 0x62000043ULL, NULL, ImplicitList1, OperandInfo19 }, // Inst #3766 = XOR16rr | |
| { 3767, 3, 1, 0, 0, "XOR16rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x66000045ULL, NULL, ImplicitList1, OperandInfo19 }, // Inst #3767 = XOR16rr_REV | |
| { 3768, 1, 0, 0, 0, "XOR32i32", 0|(1<<MCID::UnmodeledSideEffects), 0x6a014001ULL, ImplicitList3, ImplicitList1, OperandInfo2 }, // Inst #3768 = XOR32i32 | |
| { 3769, 6, 0, 0, 0, "XOR32mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10201401eULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #3769 = XOR32mi | |
| { 3770, 6, 0, 0, 0, "XOR32mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10600401eULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #3770 = XOR32mi8 | |
| { 3771, 6, 0, 0, 0, "XOR32mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x62000004ULL, NULL, ImplicitList1, OperandInfo20 }, // Inst #3771 = XOR32mr | |
| { 3772, 3, 1, 0, 0, "XOR32ri", 0, 0x102014016ULL, NULL, ImplicitList1, OperandInfo21 }, // Inst #3772 = XOR32ri | |
| { 3773, 3, 1, 0, 0, "XOR32ri8", 0, 0x106004016ULL, NULL, ImplicitList1, OperandInfo21 }, // Inst #3773 = XOR32ri8 | |
| { 3774, 7, 1, 0, 0, "XOR32rm", 0|(1<<MCID::MayLoad), 0x66000006ULL, NULL, ImplicitList1, OperandInfo22 }, // Inst #3774 = XOR32rm | |
| { 3775, 3, 1, 0, 0, "XOR32rr", 0|(1<<MCID::Commutable), 0x62000003ULL, NULL, ImplicitList1, OperandInfo23 }, // Inst #3775 = XOR32rr | |
| { 3776, 3, 1, 0, 0, "XOR32rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x66000005ULL, NULL, ImplicitList1, OperandInfo23 }, // Inst #3776 = XOR32rr_REV | |
| { 3777, 1, 0, 0, 0, "XOR64i32", 0|(1<<MCID::UnmodeledSideEffects), 0x6a016001ULL, ImplicitList4, ImplicitList1, OperandInfo2 }, // Inst #3777 = XOR64i32 | |
| { 3778, 6, 0, 0, 0, "XOR64mi32", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10201601eULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #3778 = XOR64mi32 | |
| { 3779, 6, 0, 0, 0, "XOR64mi8", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10600601eULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #3779 = XOR64mi8 | |
| { 3780, 6, 0, 0, 0, "XOR64mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x62002004ULL, NULL, ImplicitList1, OperandInfo24 }, // Inst #3780 = XOR64mr | |
| { 3781, 3, 1, 0, 0, "XOR64ri32", 0, 0x102016016ULL, NULL, ImplicitList1, OperandInfo25 }, // Inst #3781 = XOR64ri32 | |
| { 3782, 3, 1, 0, 0, "XOR64ri8", 0, 0x106006016ULL, NULL, ImplicitList1, OperandInfo25 }, // Inst #3782 = XOR64ri8 | |
| { 3783, 7, 1, 0, 0, "XOR64rm", 0|(1<<MCID::MayLoad), 0x66002006ULL, NULL, ImplicitList1, OperandInfo26 }, // Inst #3783 = XOR64rm | |
| { 3784, 3, 1, 0, 0, "XOR64rr", 0|(1<<MCID::Commutable), 0x62002003ULL, NULL, ImplicitList1, OperandInfo27 }, // Inst #3784 = XOR64rr | |
| { 3785, 3, 1, 0, 0, "XOR64rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x66002005ULL, NULL, ImplicitList1, OperandInfo27 }, // Inst #3785 = XOR64rr_REV | |
| { 3786, 1, 0, 0, 0, "XOR8i8", 0|(1<<MCID::UnmodeledSideEffects), 0x68004001ULL, ImplicitList5, ImplicitList1, OperandInfo2 }, // Inst #3786 = XOR8i8 | |
| { 3787, 6, 0, 0, 0, "XOR8mi", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x10000401eULL, NULL, ImplicitList1, OperandInfo15 }, // Inst #3787 = XOR8mi | |
| { 3788, 6, 0, 0, 0, "XOR8mr", 0|(1<<MCID::MayLoad)|(1<<MCID::MayStore), 0x60000004ULL, NULL, ImplicitList1, OperandInfo28 }, // Inst #3788 = XOR8mr | |
| { 3789, 3, 1, 0, 0, "XOR8ri", 0, 0x100004016ULL, NULL, ImplicitList1, OperandInfo29 }, // Inst #3789 = XOR8ri | |
| { 3790, 7, 1, 0, 0, "XOR8rm", 0|(1<<MCID::MayLoad), 0x64000006ULL, NULL, ImplicitList1, OperandInfo30 }, // Inst #3790 = XOR8rm | |
| { 3791, 3, 1, 0, 0, "XOR8rr", 0|(1<<MCID::Commutable), 0x60000003ULL, NULL, ImplicitList1, OperandInfo31 }, // Inst #3791 = XOR8rr | |
| { 3792, 3, 1, 0, 0, "XOR8rr_REV", 0|(1<<MCID::UnmodeledSideEffects), 0x64000005ULL, NULL, ImplicitList1, OperandInfo31 }, // Inst #3792 = XOR8rr_REV | |
| { 3793, 7, 1, 0, 0, "XORPDrm", 0|(1<<MCID::MayLoad), 0xaf000146ULL, NULL, NULL, OperandInfo32 }, // Inst #3793 = XORPDrm | |
| { 3794, 3, 1, 0, 0, "XORPDrr", 0|(1<<MCID::Commutable), 0xaf000145ULL, NULL, NULL, OperandInfo33 }, // Inst #3794 = XORPDrr | |
| { 3795, 7, 1, 0, 0, "XORPSrm", 0|(1<<MCID::MayLoad), 0xae800106ULL, NULL, NULL, OperandInfo32 }, // Inst #3795 = XORPSrm | |
| { 3796, 3, 1, 0, 0, "XORPSrr", 0|(1<<MCID::Commutable), 0xae800105ULL, NULL, NULL, OperandInfo33 }, // Inst #3796 = XORPSrr | |
| { 3797, 5, 0, 0, 0, "XRSTOR", 0|(1<<MCID::UnmodeledSideEffects), 0x15c00011dULL, ImplicitList74, NULL, OperandInfo38 }, // Inst #3797 = XRSTOR | |
| { 3798, 5, 0, 0, 0, "XRSTOR64", 0|(1<<MCID::UnmodeledSideEffects), 0x15c00211dULL, ImplicitList74, NULL, OperandInfo38 }, // Inst #3798 = XRSTOR64 | |
| { 3799, 5, 1, 0, 0, "XSAVE", 0|(1<<MCID::UnmodeledSideEffects), 0x15c00011cULL, ImplicitList74, NULL, OperandInfo38 }, // Inst #3799 = XSAVE | |
| { 3800, 5, 1, 0, 0, "XSAVE64", 0|(1<<MCID::UnmodeledSideEffects), 0x15c00211cULL, ImplicitList74, NULL, OperandInfo38 }, // Inst #3800 = XSAVE64 | |
| { 3801, 5, 1, 0, 0, "XSAVEOPT", 0|(1<<MCID::UnmodeledSideEffects), 0x15c00011eULL, ImplicitList74, NULL, OperandInfo38 }, // Inst #3801 = XSAVEOPT | |
| { 3802, 5, 1, 0, 0, "XSAVEOPT64", 0|(1<<MCID::UnmodeledSideEffects), 0x15c00211eULL, ImplicitList74, NULL, OperandInfo38 }, // Inst #3802 = XSAVEOPT64 | |
| { 3803, 0, 0, 0, 0, "XSETBV", 0|(1<<MCID::UnmodeledSideEffects), 0x200012eULL, ImplicitList75, NULL, 0 }, // Inst #3803 = XSETBV | |
| { 3804, 0, 0, 0, 0, "XSHA1", 0|(1<<MCID::UnmodeledSideEffects), 0x190000f01ULL, ImplicitList76, ImplicitList76, 0 }, // Inst #3804 = XSHA1 | |
| { 3805, 0, 0, 0, 0, "XSHA256", 0|(1<<MCID::UnmodeledSideEffects), 0x1a0000f01ULL, ImplicitList76, ImplicitList76, 0 }, // Inst #3805 = XSHA256 | |
| { 3806, 0, 0, 0, 0, "XSTORE", 0|(1<<MCID::UnmodeledSideEffects), 0x180001001ULL, ImplicitList77, ImplicitList78, 0 }, // Inst #3806 = XSTORE | |
| }; | |
| static inline void InitX86MCInstrInfo(MCInstrInfo *II) { | |
| II->InitMCInstrInfo(X86Insts, 3807); | |
| } | |
| } // End llvm namespace | |
| #endif // GET_INSTRINFO_MC_DESC | |
| #ifdef GET_INSTRINFO_HEADER | |
| #undef GET_INSTRINFO_HEADER | |
| namespace llvm { | |
| struct X86GenInstrInfo : public TargetInstrInfoImpl { | |
| explicit X86GenInstrInfo(int SO = -1, int DO = -1); | |
| }; | |
| } // End llvm namespace | |
| #endif // GET_INSTRINFO_HEADER | |
| #ifdef GET_INSTRINFO_CTOR | |
| #undef GET_INSTRINFO_CTOR | |
| namespace llvm { | |
| extern MCInstrDesc X86Insts[]; | |
| X86GenInstrInfo::X86GenInstrInfo(int SO, int DO) | |
| : TargetInstrInfoImpl(SO, DO) { | |
| InitMCInstrInfo(X86Insts, 3807); | |
| } | |
| } // End llvm namespace | |
| #endif // GET_INSTRINFO_CTOR | |