| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ | |
| |* *| | |
| |* Target Instruction Enum Values and Descriptors *| | |
| |* *| | |
| |* Automatically generated file, do not edit! *| | |
| |* *| | |
| \*===----------------------------------------------------------------------===*/ | |
| #ifdef GET_INSTRINFO_ENUM | |
| #undef GET_INSTRINFO_ENUM | |
| namespace llvm { | |
| namespace PPC { | |
| enum { | |
| PHI = 0, | |
| INLINEASM = 1, | |
| INLINEASM_BR = 2, | |
| CFI_INSTRUCTION = 3, | |
| EH_LABEL = 4, | |
| GC_LABEL = 5, | |
| ANNOTATION_LABEL = 6, | |
| KILL = 7, | |
| EXTRACT_SUBREG = 8, | |
| INSERT_SUBREG = 9, | |
| IMPLICIT_DEF = 10, | |
| SUBREG_TO_REG = 11, | |
| COPY_TO_REGCLASS = 12, | |
| DBG_VALUE = 13, | |
| DBG_VALUE_LIST = 14, | |
| DBG_INSTR_REF = 15, | |
| DBG_PHI = 16, | |
| DBG_LABEL = 17, | |
| REG_SEQUENCE = 18, | |
| COPY = 19, | |
| BUNDLE = 20, | |
| LIFETIME_START = 21, | |
| LIFETIME_END = 22, | |
| PSEUDO_PROBE = 23, | |
| ARITH_FENCE = 24, | |
| STACKMAP = 25, | |
| FENTRY_CALL = 26, | |
| PATCHPOINT = 27, | |
| LOAD_STACK_GUARD = 28, | |
| PREALLOCATED_SETUP = 29, | |
| PREALLOCATED_ARG = 30, | |
| STATEPOINT = 31, | |
| LOCAL_ESCAPE = 32, | |
| FAULTING_OP = 33, | |
| PATCHABLE_OP = 34, | |
| PATCHABLE_FUNCTION_ENTER = 35, | |
| PATCHABLE_RET = 36, | |
| PATCHABLE_FUNCTION_EXIT = 37, | |
| PATCHABLE_TAIL_CALL = 38, | |
| PATCHABLE_EVENT_CALL = 39, | |
| PATCHABLE_TYPED_EVENT_CALL = 40, | |
| ICALL_BRANCH_FUNNEL = 41, | |
| MEMBARRIER = 42, | |
| G_ASSERT_SEXT = 43, | |
| G_ASSERT_ZEXT = 44, | |
| G_ASSERT_ALIGN = 45, | |
| G_ADD = 46, | |
| G_SUB = 47, | |
| G_MUL = 48, | |
| G_SDIV = 49, | |
| G_UDIV = 50, | |
| G_SREM = 51, | |
| G_UREM = 52, | |
| G_SDIVREM = 53, | |
| G_UDIVREM = 54, | |
| G_AND = 55, | |
| G_OR = 56, | |
| G_XOR = 57, | |
| G_IMPLICIT_DEF = 58, | |
| G_PHI = 59, | |
| G_FRAME_INDEX = 60, | |
| G_GLOBAL_VALUE = 61, | |
| G_EXTRACT = 62, | |
| G_UNMERGE_VALUES = 63, | |
| G_INSERT = 64, | |
| G_MERGE_VALUES = 65, | |
| G_BUILD_VECTOR = 66, | |
| G_BUILD_VECTOR_TRUNC = 67, | |
| G_CONCAT_VECTORS = 68, | |
| G_PTRTOINT = 69, | |
| G_INTTOPTR = 70, | |
| G_BITCAST = 71, | |
| G_FREEZE = 72, | |
| G_INTRINSIC_FPTRUNC_ROUND = 73, | |
| G_INTRINSIC_TRUNC = 74, | |
| G_INTRINSIC_ROUND = 75, | |
| G_INTRINSIC_LRINT = 76, | |
| G_INTRINSIC_ROUNDEVEN = 77, | |
| G_READCYCLECOUNTER = 78, | |
| G_LOAD = 79, | |
| G_SEXTLOAD = 80, | |
| G_ZEXTLOAD = 81, | |
| G_INDEXED_LOAD = 82, | |
| G_INDEXED_SEXTLOAD = 83, | |
| G_INDEXED_ZEXTLOAD = 84, | |
| G_STORE = 85, | |
| G_INDEXED_STORE = 86, | |
| G_ATOMIC_CMPXCHG_WITH_SUCCESS = 87, | |
| G_ATOMIC_CMPXCHG = 88, | |
| G_ATOMICRMW_XCHG = 89, | |
| G_ATOMICRMW_ADD = 90, | |
| G_ATOMICRMW_SUB = 91, | |
| G_ATOMICRMW_AND = 92, | |
| G_ATOMICRMW_NAND = 93, | |
| G_ATOMICRMW_OR = 94, | |
| G_ATOMICRMW_XOR = 95, | |
| G_ATOMICRMW_MAX = 96, | |
| G_ATOMICRMW_MIN = 97, | |
| G_ATOMICRMW_UMAX = 98, | |
| G_ATOMICRMW_UMIN = 99, | |
| G_ATOMICRMW_FADD = 100, | |
| G_ATOMICRMW_FSUB = 101, | |
| G_ATOMICRMW_FMAX = 102, | |
| G_ATOMICRMW_FMIN = 103, | |
| G_ATOMICRMW_UINC_WRAP = 104, | |
| G_ATOMICRMW_UDEC_WRAP = 105, | |
| G_FENCE = 106, | |
| G_BRCOND = 107, | |
| G_BRINDIRECT = 108, | |
| G_INVOKE_REGION_START = 109, | |
| G_INTRINSIC = 110, | |
| G_INTRINSIC_W_SIDE_EFFECTS = 111, | |
| G_ANYEXT = 112, | |
| G_TRUNC = 113, | |
| G_CONSTANT = 114, | |
| G_FCONSTANT = 115, | |
| G_VASTART = 116, | |
| G_VAARG = 117, | |
| G_SEXT = 118, | |
| G_SEXT_INREG = 119, | |
| G_ZEXT = 120, | |
| G_SHL = 121, | |
| G_LSHR = 122, | |
| G_ASHR = 123, | |
| G_FSHL = 124, | |
| G_FSHR = 125, | |
| G_ROTR = 126, | |
| G_ROTL = 127, | |
| G_ICMP = 128, | |
| G_FCMP = 129, | |
| G_SELECT = 130, | |
| G_UADDO = 131, | |
| G_UADDE = 132, | |
| G_USUBO = 133, | |
| G_USUBE = 134, | |
| G_SADDO = 135, | |
| G_SADDE = 136, | |
| G_SSUBO = 137, | |
| G_SSUBE = 138, | |
| G_UMULO = 139, | |
| G_SMULO = 140, | |
| G_UMULH = 141, | |
| G_SMULH = 142, | |
| G_UADDSAT = 143, | |
| G_SADDSAT = 144, | |
| G_USUBSAT = 145, | |
| G_SSUBSAT = 146, | |
| G_USHLSAT = 147, | |
| G_SSHLSAT = 148, | |
| G_SMULFIX = 149, | |
| G_UMULFIX = 150, | |
| G_SMULFIXSAT = 151, | |
| G_UMULFIXSAT = 152, | |
| G_SDIVFIX = 153, | |
| G_UDIVFIX = 154, | |
| G_SDIVFIXSAT = 155, | |
| G_UDIVFIXSAT = 156, | |
| G_FADD = 157, | |
| G_FSUB = 158, | |
| G_FMUL = 159, | |
| G_FMA = 160, | |
| G_FMAD = 161, | |
| G_FDIV = 162, | |
| G_FREM = 163, | |
| G_FPOW = 164, | |
| G_FPOWI = 165, | |
| G_FEXP = 166, | |
| G_FEXP2 = 167, | |
| G_FLOG = 168, | |
| G_FLOG2 = 169, | |
| G_FLOG10 = 170, | |
| G_FNEG = 171, | |
| G_FPEXT = 172, | |
| G_FPTRUNC = 173, | |
| G_FPTOSI = 174, | |
| G_FPTOUI = 175, | |
| G_SITOFP = 176, | |
| G_UITOFP = 177, | |
| G_FABS = 178, | |
| G_FCOPYSIGN = 179, | |
| G_IS_FPCLASS = 180, | |
| G_FCANONICALIZE = 181, | |
| G_FMINNUM = 182, | |
| G_FMAXNUM = 183, | |
| G_FMINNUM_IEEE = 184, | |
| G_FMAXNUM_IEEE = 185, | |
| G_FMINIMUM = 186, | |
| G_FMAXIMUM = 187, | |
| G_PTR_ADD = 188, | |
| G_PTRMASK = 189, | |
| G_SMIN = 190, | |
| G_SMAX = 191, | |
| G_UMIN = 192, | |
| G_UMAX = 193, | |
| G_ABS = 194, | |
| G_LROUND = 195, | |
| G_LLROUND = 196, | |
| G_BR = 197, | |
| G_BRJT = 198, | |
| G_INSERT_VECTOR_ELT = 199, | |
| G_EXTRACT_VECTOR_ELT = 200, | |
| G_SHUFFLE_VECTOR = 201, | |
| G_CTTZ = 202, | |
| G_CTTZ_ZERO_UNDEF = 203, | |
| G_CTLZ = 204, | |
| G_CTLZ_ZERO_UNDEF = 205, | |
| G_CTPOP = 206, | |
| G_BSWAP = 207, | |
| G_BITREVERSE = 208, | |
| G_FCEIL = 209, | |
| G_FCOS = 210, | |
| G_FSIN = 211, | |
| G_FSQRT = 212, | |
| G_FFLOOR = 213, | |
| G_FRINT = 214, | |
| G_FNEARBYINT = 215, | |
| G_ADDRSPACE_CAST = 216, | |
| G_BLOCK_ADDR = 217, | |
| G_JUMP_TABLE = 218, | |
| G_DYN_STACKALLOC = 219, | |
| G_STRICT_FADD = 220, | |
| G_STRICT_FSUB = 221, | |
| G_STRICT_FMUL = 222, | |
| G_STRICT_FDIV = 223, | |
| G_STRICT_FREM = 224, | |
| G_STRICT_FMA = 225, | |
| G_STRICT_FSQRT = 226, | |
| G_READ_REGISTER = 227, | |
| G_WRITE_REGISTER = 228, | |
| G_MEMCPY = 229, | |
| G_MEMCPY_INLINE = 230, | |
| G_MEMMOVE = 231, | |
| G_MEMSET = 232, | |
| G_BZERO = 233, | |
| G_VECREDUCE_SEQ_FADD = 234, | |
| G_VECREDUCE_SEQ_FMUL = 235, | |
| G_VECREDUCE_FADD = 236, | |
| G_VECREDUCE_FMUL = 237, | |
| G_VECREDUCE_FMAX = 238, | |
| G_VECREDUCE_FMIN = 239, | |
| G_VECREDUCE_ADD = 240, | |
| G_VECREDUCE_MUL = 241, | |
| G_VECREDUCE_AND = 242, | |
| G_VECREDUCE_OR = 243, | |
| G_VECREDUCE_XOR = 244, | |
| G_VECREDUCE_SMAX = 245, | |
| G_VECREDUCE_SMIN = 246, | |
| G_VECREDUCE_UMAX = 247, | |
| G_VECREDUCE_UMIN = 248, | |
| G_SBFX = 249, | |
| G_UBFX = 250, | |
| ATOMIC_CMP_SWAP_I128 = 251, | |
| ATOMIC_LOAD_ADD_I128 = 252, | |
| ATOMIC_LOAD_AND_I128 = 253, | |
| ATOMIC_LOAD_NAND_I128 = 254, | |
| ATOMIC_LOAD_OR_I128 = 255, | |
| ATOMIC_LOAD_SUB_I128 = 256, | |
| ATOMIC_LOAD_XOR_I128 = 257, | |
| ATOMIC_SWAP_I128 = 258, | |
| BUILD_QUADWORD = 259, | |
| BUILD_UACC = 260, | |
| CFENCE8 = 261, | |
| CLRLSLDI = 262, | |
| CLRLSLDI_rec = 263, | |
| CLRLSLWI = 264, | |
| CLRLSLWI_rec = 265, | |
| CLRRDI = 266, | |
| CLRRDI_rec = 267, | |
| CLRRWI = 268, | |
| CLRRWI_rec = 269, | |
| DCBFL = 270, | |
| DCBFLP = 271, | |
| DCBFPS = 272, | |
| DCBFx = 273, | |
| DCBSTPS = 274, | |
| DCBTCT = 275, | |
| DCBTDS = 276, | |
| DCBTSTCT = 277, | |
| DCBTSTDS = 278, | |
| DCBTSTT = 279, | |
| DCBTSTx = 280, | |
| DCBTT = 281, | |
| DCBTx = 282, | |
| DFLOADf32 = 283, | |
| DFLOADf64 = 284, | |
| DFSTOREf32 = 285, | |
| DFSTOREf64 = 286, | |
| EXTLDI = 287, | |
| EXTLDI_rec = 288, | |
| EXTLWI = 289, | |
| EXTLWI_rec = 290, | |
| EXTRDI = 291, | |
| EXTRDI_rec = 292, | |
| EXTRWI = 293, | |
| EXTRWI_rec = 294, | |
| INSLWI = 295, | |
| INSLWI_rec = 296, | |
| INSRDI = 297, | |
| INSRDI_rec = 298, | |
| INSRWI = 299, | |
| INSRWI_rec = 300, | |
| KILL_PAIR = 301, | |
| LAx = 302, | |
| LIWAX = 303, | |
| LIWZX = 304, | |
| RLWIMIbm = 305, | |
| RLWIMIbm_rec = 306, | |
| RLWINMbm = 307, | |
| RLWINMbm_rec = 308, | |
| RLWNMbm = 309, | |
| RLWNMbm_rec = 310, | |
| ROTRDI = 311, | |
| ROTRDI_rec = 312, | |
| ROTRWI = 313, | |
| ROTRWI_rec = 314, | |
| SLDI = 315, | |
| SLDI_rec = 316, | |
| SLWI = 317, | |
| SLWI_rec = 318, | |
| SPILLTOVSR_LD = 319, | |
| SPILLTOVSR_LDX = 320, | |
| SPILLTOVSR_ST = 321, | |
| SPILLTOVSR_STX = 322, | |
| SRDI = 323, | |
| SRDI_rec = 324, | |
| SRWI = 325, | |
| SRWI_rec = 326, | |
| STIWX = 327, | |
| SUBI = 328, | |
| SUBIC = 329, | |
| SUBIC_rec = 330, | |
| SUBIS = 331, | |
| SUBPCIS = 332, | |
| XFLOADf32 = 333, | |
| XFLOADf64 = 334, | |
| XFSTOREf32 = 335, | |
| XFSTOREf64 = 336, | |
| ADD4 = 337, | |
| ADD4O = 338, | |
| ADD4O_rec = 339, | |
| ADD4TLS = 340, | |
| ADD4_rec = 341, | |
| ADD8 = 342, | |
| ADD8O = 343, | |
| ADD8O_rec = 344, | |
| ADD8TLS = 345, | |
| ADD8TLS_ = 346, | |
| ADD8_rec = 347, | |
| ADDC = 348, | |
| ADDC8 = 349, | |
| ADDC8O = 350, | |
| ADDC8O_rec = 351, | |
| ADDC8_rec = 352, | |
| ADDCO = 353, | |
| ADDCO_rec = 354, | |
| ADDC_rec = 355, | |
| ADDE = 356, | |
| ADDE8 = 357, | |
| ADDE8O = 358, | |
| ADDE8O_rec = 359, | |
| ADDE8_rec = 360, | |
| ADDEO = 361, | |
| ADDEO_rec = 362, | |
| ADDEX = 363, | |
| ADDEX8 = 364, | |
| ADDE_rec = 365, | |
| ADDI = 366, | |
| ADDI8 = 367, | |
| ADDIC = 368, | |
| ADDIC8 = 369, | |
| ADDIC_rec = 370, | |
| ADDIS = 371, | |
| ADDIS8 = 372, | |
| ADDISdtprelHA = 373, | |
| ADDISdtprelHA32 = 374, | |
| ADDISgotTprelHA = 375, | |
| ADDIStlsgdHA = 376, | |
| ADDIStlsldHA = 377, | |
| ADDIStocHA = 378, | |
| ADDIStocHA8 = 379, | |
| ADDIdtprelL = 380, | |
| ADDIdtprelL32 = 381, | |
| ADDItlsgdL = 382, | |
| ADDItlsgdL32 = 383, | |
| ADDItlsgdLADDR = 384, | |
| ADDItlsgdLADDR32 = 385, | |
| ADDItlsldL = 386, | |
| ADDItlsldL32 = 387, | |
| ADDItlsldLADDR = 388, | |
| ADDItlsldLADDR32 = 389, | |
| ADDItoc = 390, | |
| ADDItoc8 = 391, | |
| ADDItocL = 392, | |
| ADDME = 393, | |
| ADDME8 = 394, | |
| ADDME8O = 395, | |
| ADDME8O_rec = 396, | |
| ADDME8_rec = 397, | |
| ADDMEO = 398, | |
| ADDMEO_rec = 399, | |
| ADDME_rec = 400, | |
| ADDPCIS = 401, | |
| ADDZE = 402, | |
| ADDZE8 = 403, | |
| ADDZE8O = 404, | |
| ADDZE8O_rec = 405, | |
| ADDZE8_rec = 406, | |
| ADDZEO = 407, | |
| ADDZEO_rec = 408, | |
| ADDZE_rec = 409, | |
| ADJCALLSTACKDOWN = 410, | |
| ADJCALLSTACKUP = 411, | |
| AND = 412, | |
| AND8 = 413, | |
| AND8_rec = 414, | |
| ANDC = 415, | |
| ANDC8 = 416, | |
| ANDC8_rec = 417, | |
| ANDC_rec = 418, | |
| ANDI8_rec = 419, | |
| ANDIS8_rec = 420, | |
| ANDIS_rec = 421, | |
| ANDI_rec = 422, | |
| ANDI_rec_1_EQ_BIT = 423, | |
| ANDI_rec_1_EQ_BIT8 = 424, | |
| ANDI_rec_1_GT_BIT = 425, | |
| ANDI_rec_1_GT_BIT8 = 426, | |
| AND_rec = 427, | |
| ATOMIC_CMP_SWAP_I16 = 428, | |
| ATOMIC_CMP_SWAP_I32 = 429, | |
| ATOMIC_CMP_SWAP_I64 = 430, | |
| ATOMIC_CMP_SWAP_I8 = 431, | |
| ATOMIC_LOAD_ADD_I16 = 432, | |
| ATOMIC_LOAD_ADD_I32 = 433, | |
| ATOMIC_LOAD_ADD_I64 = 434, | |
| ATOMIC_LOAD_ADD_I8 = 435, | |
| ATOMIC_LOAD_AND_I16 = 436, | |
| ATOMIC_LOAD_AND_I32 = 437, | |
| ATOMIC_LOAD_AND_I64 = 438, | |
| ATOMIC_LOAD_AND_I8 = 439, | |
| ATOMIC_LOAD_MAX_I16 = 440, | |
| ATOMIC_LOAD_MAX_I32 = 441, | |
| ATOMIC_LOAD_MAX_I64 = 442, | |
| ATOMIC_LOAD_MAX_I8 = 443, | |
| ATOMIC_LOAD_MIN_I16 = 444, | |
| ATOMIC_LOAD_MIN_I32 = 445, | |
| ATOMIC_LOAD_MIN_I64 = 446, | |
| ATOMIC_LOAD_MIN_I8 = 447, | |
| ATOMIC_LOAD_NAND_I16 = 448, | |
| ATOMIC_LOAD_NAND_I32 = 449, | |
| ATOMIC_LOAD_NAND_I64 = 450, | |
| ATOMIC_LOAD_NAND_I8 = 451, | |
| ATOMIC_LOAD_OR_I16 = 452, | |
| ATOMIC_LOAD_OR_I32 = 453, | |
| ATOMIC_LOAD_OR_I64 = 454, | |
| ATOMIC_LOAD_OR_I8 = 455, | |
| ATOMIC_LOAD_SUB_I16 = 456, | |
| ATOMIC_LOAD_SUB_I32 = 457, | |
| ATOMIC_LOAD_SUB_I64 = 458, | |
| ATOMIC_LOAD_SUB_I8 = 459, | |
| ATOMIC_LOAD_UMAX_I16 = 460, | |
| ATOMIC_LOAD_UMAX_I32 = 461, | |
| ATOMIC_LOAD_UMAX_I64 = 462, | |
| ATOMIC_LOAD_UMAX_I8 = 463, | |
| ATOMIC_LOAD_UMIN_I16 = 464, | |
| ATOMIC_LOAD_UMIN_I32 = 465, | |
| ATOMIC_LOAD_UMIN_I64 = 466, | |
| ATOMIC_LOAD_UMIN_I8 = 467, | |
| ATOMIC_LOAD_XOR_I16 = 468, | |
| ATOMIC_LOAD_XOR_I32 = 469, | |
| ATOMIC_LOAD_XOR_I64 = 470, | |
| ATOMIC_LOAD_XOR_I8 = 471, | |
| ATOMIC_SWAP_I16 = 472, | |
| ATOMIC_SWAP_I32 = 473, | |
| ATOMIC_SWAP_I64 = 474, | |
| ATOMIC_SWAP_I8 = 475, | |
| ATTN = 476, | |
| B = 477, | |
| BA = 478, | |
| BC = 479, | |
| BCC = 480, | |
| BCCA = 481, | |
| BCCCTR = 482, | |
| BCCCTR8 = 483, | |
| BCCCTRL = 484, | |
| BCCCTRL8 = 485, | |
| BCCL = 486, | |
| BCCLA = 487, | |
| BCCLR = 488, | |
| BCCLRL = 489, | |
| BCCTR = 490, | |
| BCCTR8 = 491, | |
| BCCTR8n = 492, | |
| BCCTRL = 493, | |
| BCCTRL8 = 494, | |
| BCCTRL8n = 495, | |
| BCCTRLn = 496, | |
| BCCTRn = 497, | |
| BCDADD_rec = 498, | |
| BCDCFN_rec = 499, | |
| BCDCFSQ_rec = 500, | |
| BCDCFZ_rec = 501, | |
| BCDCPSGN_rec = 502, | |
| BCDCTN_rec = 503, | |
| BCDCTSQ_rec = 504, | |
| BCDCTZ_rec = 505, | |
| BCDSETSGN_rec = 506, | |
| BCDSR_rec = 507, | |
| BCDSUB_rec = 508, | |
| BCDS_rec = 509, | |
| BCDTRUNC_rec = 510, | |
| BCDUS_rec = 511, | |
| BCDUTRUNC_rec = 512, | |
| BCL = 513, | |
| BCLR = 514, | |
| BCLRL = 515, | |
| BCLRLn = 516, | |
| BCLRn = 517, | |
| BCLalways = 518, | |
| BCLn = 519, | |
| BCTR = 520, | |
| BCTR8 = 521, | |
| BCTRL = 522, | |
| BCTRL8 = 523, | |
| BCTRL8_LDinto_toc = 524, | |
| BCTRL8_LDinto_toc_RM = 525, | |
| BCTRL8_RM = 526, | |
| BCTRL_LWZinto_toc = 527, | |
| BCTRL_LWZinto_toc_RM = 528, | |
| BCTRL_RM = 529, | |
| BCn = 530, | |
| BDNZ = 531, | |
| BDNZ8 = 532, | |
| BDNZA = 533, | |
| BDNZAm = 534, | |
| BDNZAp = 535, | |
| BDNZL = 536, | |
| BDNZLA = 537, | |
| BDNZLAm = 538, | |
| BDNZLAp = 539, | |
| BDNZLR = 540, | |
| BDNZLR8 = 541, | |
| BDNZLRL = 542, | |
| BDNZLRLm = 543, | |
| BDNZLRLp = 544, | |
| BDNZLRm = 545, | |
| BDNZLRp = 546, | |
| BDNZLm = 547, | |
| BDNZLp = 548, | |
| BDNZm = 549, | |
| BDNZp = 550, | |
| BDZ = 551, | |
| BDZ8 = 552, | |
| BDZA = 553, | |
| BDZAm = 554, | |
| BDZAp = 555, | |
| BDZL = 556, | |
| BDZLA = 557, | |
| BDZLAm = 558, | |
| BDZLAp = 559, | |
| BDZLR = 560, | |
| BDZLR8 = 561, | |
| BDZLRL = 562, | |
| BDZLRLm = 563, | |
| BDZLRLp = 564, | |
| BDZLRm = 565, | |
| BDZLRp = 566, | |
| BDZLm = 567, | |
| BDZLp = 568, | |
| BDZm = 569, | |
| BDZp = 570, | |
| BL = 571, | |
| BL8 = 572, | |
| BL8_NOP = 573, | |
| BL8_NOP_RM = 574, | |
| BL8_NOP_TLS = 575, | |
| BL8_NOTOC = 576, | |
| BL8_NOTOC_RM = 577, | |
| BL8_NOTOC_TLS = 578, | |
| BL8_RM = 579, | |
| BL8_TLS = 580, | |
| BL8_TLS_ = 581, | |
| BLA = 582, | |
| BLA8 = 583, | |
| BLA8_NOP = 584, | |
| BLA8_NOP_RM = 585, | |
| BLA8_RM = 586, | |
| BLA_RM = 587, | |
| BLR = 588, | |
| BLR8 = 589, | |
| BLRL = 590, | |
| BL_NOP = 591, | |
| BL_NOP_RM = 592, | |
| BL_RM = 593, | |
| BL_TLS = 594, | |
| BPERMD = 595, | |
| BRD = 596, | |
| BRH = 597, | |
| BRH8 = 598, | |
| BRINC = 599, | |
| BRW = 600, | |
| BRW8 = 601, | |
| CFUGED = 602, | |
| CLRBHRB = 603, | |
| CMPB = 604, | |
| CMPB8 = 605, | |
| CMPD = 606, | |
| CMPDI = 607, | |
| CMPEQB = 608, | |
| CMPLD = 609, | |
| CMPLDI = 610, | |
| CMPLW = 611, | |
| CMPLWI = 612, | |
| CMPRB = 613, | |
| CMPRB8 = 614, | |
| CMPW = 615, | |
| CMPWI = 616, | |
| CNTLZD = 617, | |
| CNTLZDM = 618, | |
| CNTLZD_rec = 619, | |
| CNTLZW = 620, | |
| CNTLZW8 = 621, | |
| CNTLZW8_rec = 622, | |
| CNTLZW_rec = 623, | |
| CNTTZD = 624, | |
| CNTTZDM = 625, | |
| CNTTZD_rec = 626, | |
| CNTTZW = 627, | |
| CNTTZW8 = 628, | |
| CNTTZW8_rec = 629, | |
| CNTTZW_rec = 630, | |
| CP_ABORT = 631, | |
| CP_COPY = 632, | |
| CP_COPY8 = 633, | |
| CP_PASTE8_rec = 634, | |
| CP_PASTE_rec = 635, | |
| CR6SET = 636, | |
| CR6UNSET = 637, | |
| CRAND = 638, | |
| CRANDC = 639, | |
| CREQV = 640, | |
| CRNAND = 641, | |
| CRNOR = 642, | |
| CRNOT = 643, | |
| CROR = 644, | |
| CRORC = 645, | |
| CRSET = 646, | |
| CRUNSET = 647, | |
| CRXOR = 648, | |
| CTRL_DEP = 649, | |
| DARN = 650, | |
| DCBA = 651, | |
| DCBF = 652, | |
| DCBFEP = 653, | |
| DCBI = 654, | |
| DCBST = 655, | |
| DCBSTEP = 656, | |
| DCBT = 657, | |
| DCBTEP = 658, | |
| DCBTST = 659, | |
| DCBTSTEP = 660, | |
| DCBZ = 661, | |
| DCBZEP = 662, | |
| DCBZL = 663, | |
| DCBZLEP = 664, | |
| DCCCI = 665, | |
| DIVD = 666, | |
| DIVDE = 667, | |
| DIVDEO = 668, | |
| DIVDEO_rec = 669, | |
| DIVDEU = 670, | |
| DIVDEUO = 671, | |
| DIVDEUO_rec = 672, | |
| DIVDEU_rec = 673, | |
| DIVDE_rec = 674, | |
| DIVDO = 675, | |
| DIVDO_rec = 676, | |
| DIVDU = 677, | |
| DIVDUO = 678, | |
| DIVDUO_rec = 679, | |
| DIVDU_rec = 680, | |
| DIVD_rec = 681, | |
| DIVW = 682, | |
| DIVWE = 683, | |
| DIVWEO = 684, | |
| DIVWEO_rec = 685, | |
| DIVWEU = 686, | |
| DIVWEUO = 687, | |
| DIVWEUO_rec = 688, | |
| DIVWEU_rec = 689, | |
| DIVWE_rec = 690, | |
| DIVWO = 691, | |
| DIVWO_rec = 692, | |
| DIVWU = 693, | |
| DIVWUO = 694, | |
| DIVWUO_rec = 695, | |
| DIVWU_rec = 696, | |
| DIVW_rec = 697, | |
| DMMR = 698, | |
| DMSETDMRZ = 699, | |
| DMXOR = 700, | |
| DMXXEXTFDMR256 = 701, | |
| DMXXEXTFDMR512 = 702, | |
| DMXXEXTFDMR512_HI = 703, | |
| DMXXINSTFDMR256 = 704, | |
| DMXXINSTFDMR512 = 705, | |
| DMXXINSTFDMR512_HI = 706, | |
| DSS = 707, | |
| DSSALL = 708, | |
| DST = 709, | |
| DST64 = 710, | |
| DSTST = 711, | |
| DSTST64 = 712, | |
| DSTSTT = 713, | |
| DSTSTT64 = 714, | |
| DSTT = 715, | |
| DSTT64 = 716, | |
| DYNALLOC = 717, | |
| DYNALLOC8 = 718, | |
| DYNAREAOFFSET = 719, | |
| DYNAREAOFFSET8 = 720, | |
| DecreaseCTR8loop = 721, | |
| DecreaseCTRloop = 722, | |
| EFDABS = 723, | |
| EFDADD = 724, | |
| EFDCFS = 725, | |
| EFDCFSF = 726, | |
| EFDCFSI = 727, | |
| EFDCFSID = 728, | |
| EFDCFUF = 729, | |
| EFDCFUI = 730, | |
| EFDCFUID = 731, | |
| EFDCMPEQ = 732, | |
| EFDCMPGT = 733, | |
| EFDCMPLT = 734, | |
| EFDCTSF = 735, | |
| EFDCTSI = 736, | |
| EFDCTSIDZ = 737, | |
| EFDCTSIZ = 738, | |
| EFDCTUF = 739, | |
| EFDCTUI = 740, | |
| EFDCTUIDZ = 741, | |
| EFDCTUIZ = 742, | |
| EFDDIV = 743, | |
| EFDMUL = 744, | |
| EFDNABS = 745, | |
| EFDNEG = 746, | |
| EFDSUB = 747, | |
| EFDTSTEQ = 748, | |
| EFDTSTGT = 749, | |
| EFDTSTLT = 750, | |
| EFSABS = 751, | |
| EFSADD = 752, | |
| EFSCFD = 753, | |
| EFSCFSF = 754, | |
| EFSCFSI = 755, | |
| EFSCFUF = 756, | |
| EFSCFUI = 757, | |
| EFSCMPEQ = 758, | |
| EFSCMPGT = 759, | |
| EFSCMPLT = 760, | |
| EFSCTSF = 761, | |
| EFSCTSI = 762, | |
| EFSCTSIZ = 763, | |
| EFSCTUF = 764, | |
| EFSCTUI = 765, | |
| EFSCTUIZ = 766, | |
| EFSDIV = 767, | |
| EFSMUL = 768, | |
| EFSNABS = 769, | |
| EFSNEG = 770, | |
| EFSSUB = 771, | |
| EFSTSTEQ = 772, | |
| EFSTSTGT = 773, | |
| EFSTSTLT = 774, | |
| EH_SjLj_LongJmp32 = 775, | |
| EH_SjLj_LongJmp64 = 776, | |
| EH_SjLj_SetJmp32 = 777, | |
| EH_SjLj_SetJmp64 = 778, | |
| EH_SjLj_Setup = 779, | |
| EQV = 780, | |
| EQV8 = 781, | |
| EQV8_rec = 782, | |
| EQV_rec = 783, | |
| EVABS = 784, | |
| EVADDIW = 785, | |
| EVADDSMIAAW = 786, | |
| EVADDSSIAAW = 787, | |
| EVADDUMIAAW = 788, | |
| EVADDUSIAAW = 789, | |
| EVADDW = 790, | |
| EVAND = 791, | |
| EVANDC = 792, | |
| EVCMPEQ = 793, | |
| EVCMPGTS = 794, | |
| EVCMPGTU = 795, | |
| EVCMPLTS = 796, | |
| EVCMPLTU = 797, | |
| EVCNTLSW = 798, | |
| EVCNTLZW = 799, | |
| EVDIVWS = 800, | |
| EVDIVWU = 801, | |
| EVEQV = 802, | |
| EVEXTSB = 803, | |
| EVEXTSH = 804, | |
| EVFSABS = 805, | |
| EVFSADD = 806, | |
| EVFSCFSF = 807, | |
| EVFSCFSI = 808, | |
| EVFSCFUF = 809, | |
| EVFSCFUI = 810, | |
| EVFSCMPEQ = 811, | |
| EVFSCMPGT = 812, | |
| EVFSCMPLT = 813, | |
| EVFSCTSF = 814, | |
| EVFSCTSI = 815, | |
| EVFSCTSIZ = 816, | |
| EVFSCTUF = 817, | |
| EVFSCTUI = 818, | |
| EVFSCTUIZ = 819, | |
| EVFSDIV = 820, | |
| EVFSMUL = 821, | |
| EVFSNABS = 822, | |
| EVFSNEG = 823, | |
| EVFSSUB = 824, | |
| EVFSTSTEQ = 825, | |
| EVFSTSTGT = 826, | |
| EVFSTSTLT = 827, | |
| EVLDD = 828, | |
| EVLDDX = 829, | |
| EVLDH = 830, | |
| EVLDHX = 831, | |
| EVLDW = 832, | |
| EVLDWX = 833, | |
| EVLHHESPLAT = 834, | |
| EVLHHESPLATX = 835, | |
| EVLHHOSSPLAT = 836, | |
| EVLHHOSSPLATX = 837, | |
| EVLHHOUSPLAT = 838, | |
| EVLHHOUSPLATX = 839, | |
| EVLWHE = 840, | |
| EVLWHEX = 841, | |
| EVLWHOS = 842, | |
| EVLWHOSX = 843, | |
| EVLWHOU = 844, | |
| EVLWHOUX = 845, | |
| EVLWHSPLAT = 846, | |
| EVLWHSPLATX = 847, | |
| EVLWWSPLAT = 848, | |
| EVLWWSPLATX = 849, | |
| EVMERGEHI = 850, | |
| EVMERGEHILO = 851, | |
| EVMERGELO = 852, | |
| EVMERGELOHI = 853, | |
| EVMHEGSMFAA = 854, | |
| EVMHEGSMFAN = 855, | |
| EVMHEGSMIAA = 856, | |
| EVMHEGSMIAN = 857, | |
| EVMHEGUMIAA = 858, | |
| EVMHEGUMIAN = 859, | |
| EVMHESMF = 860, | |
| EVMHESMFA = 861, | |
| EVMHESMFAAW = 862, | |
| EVMHESMFANW = 863, | |
| EVMHESMI = 864, | |
| EVMHESMIA = 865, | |
| EVMHESMIAAW = 866, | |
| EVMHESMIANW = 867, | |
| EVMHESSF = 868, | |
| EVMHESSFA = 869, | |
| EVMHESSFAAW = 870, | |
| EVMHESSFANW = 871, | |
| EVMHESSIAAW = 872, | |
| EVMHESSIANW = 873, | |
| EVMHEUMI = 874, | |
| EVMHEUMIA = 875, | |
| EVMHEUMIAAW = 876, | |
| EVMHEUMIANW = 877, | |
| EVMHEUSIAAW = 878, | |
| EVMHEUSIANW = 879, | |
| EVMHOGSMFAA = 880, | |
| EVMHOGSMFAN = 881, | |
| EVMHOGSMIAA = 882, | |
| EVMHOGSMIAN = 883, | |
| EVMHOGUMIAA = 884, | |
| EVMHOGUMIAN = 885, | |
| EVMHOSMF = 886, | |
| EVMHOSMFA = 887, | |
| EVMHOSMFAAW = 888, | |
| EVMHOSMFANW = 889, | |
| EVMHOSMI = 890, | |
| EVMHOSMIA = 891, | |
| EVMHOSMIAAW = 892, | |
| EVMHOSMIANW = 893, | |
| EVMHOSSF = 894, | |
| EVMHOSSFA = 895, | |
| EVMHOSSFAAW = 896, | |
| EVMHOSSFANW = 897, | |
| EVMHOSSIAAW = 898, | |
| EVMHOSSIANW = 899, | |
| EVMHOUMI = 900, | |
| EVMHOUMIA = 901, | |
| EVMHOUMIAAW = 902, | |
| EVMHOUMIANW = 903, | |
| EVMHOUSIAAW = 904, | |
| EVMHOUSIANW = 905, | |
| EVMRA = 906, | |
| EVMWHSMF = 907, | |
| EVMWHSMFA = 908, | |
| EVMWHSMI = 909, | |
| EVMWHSMIA = 910, | |
| EVMWHSSF = 911, | |
| EVMWHSSFA = 912, | |
| EVMWHUMI = 913, | |
| EVMWHUMIA = 914, | |
| EVMWLSMIAAW = 915, | |
| EVMWLSMIANW = 916, | |
| EVMWLSSIAAW = 917, | |
| EVMWLSSIANW = 918, | |
| EVMWLUMI = 919, | |
| EVMWLUMIA = 920, | |
| EVMWLUMIAAW = 921, | |
| EVMWLUMIANW = 922, | |
| EVMWLUSIAAW = 923, | |
| EVMWLUSIANW = 924, | |
| EVMWSMF = 925, | |
| EVMWSMFA = 926, | |
| EVMWSMFAA = 927, | |
| EVMWSMFAN = 928, | |
| EVMWSMI = 929, | |
| EVMWSMIA = 930, | |
| EVMWSMIAA = 931, | |
| EVMWSMIAN = 932, | |
| EVMWSSF = 933, | |
| EVMWSSFA = 934, | |
| EVMWSSFAA = 935, | |
| EVMWSSFAN = 936, | |
| EVMWUMI = 937, | |
| EVMWUMIA = 938, | |
| EVMWUMIAA = 939, | |
| EVMWUMIAN = 940, | |
| EVNAND = 941, | |
| EVNEG = 942, | |
| EVNOR = 943, | |
| EVOR = 944, | |
| EVORC = 945, | |
| EVRLW = 946, | |
| EVRLWI = 947, | |
| EVRNDW = 948, | |
| EVSEL = 949, | |
| EVSLW = 950, | |
| EVSLWI = 951, | |
| EVSPLATFI = 952, | |
| EVSPLATI = 953, | |
| EVSRWIS = 954, | |
| EVSRWIU = 955, | |
| EVSRWS = 956, | |
| EVSRWU = 957, | |
| EVSTDD = 958, | |
| EVSTDDX = 959, | |
| EVSTDH = 960, | |
| EVSTDHX = 961, | |
| EVSTDW = 962, | |
| EVSTDWX = 963, | |
| EVSTWHE = 964, | |
| EVSTWHEX = 965, | |
| EVSTWHO = 966, | |
| EVSTWHOX = 967, | |
| EVSTWWE = 968, | |
| EVSTWWEX = 969, | |
| EVSTWWO = 970, | |
| EVSTWWOX = 971, | |
| EVSUBFSMIAAW = 972, | |
| EVSUBFSSIAAW = 973, | |
| EVSUBFUMIAAW = 974, | |
| EVSUBFUSIAAW = 975, | |
| EVSUBFW = 976, | |
| EVSUBIFW = 977, | |
| EVXOR = 978, | |
| EXTSB = 979, | |
| EXTSB8 = 980, | |
| EXTSB8_32_64 = 981, | |
| EXTSB8_rec = 982, | |
| EXTSB_rec = 983, | |
| EXTSH = 984, | |
| EXTSH8 = 985, | |
| EXTSH8_32_64 = 986, | |
| EXTSH8_rec = 987, | |
| EXTSH_rec = 988, | |
| EXTSW = 989, | |
| EXTSWSLI = 990, | |
| EXTSWSLI_32_64 = 991, | |
| EXTSWSLI_32_64_rec = 992, | |
| EXTSWSLI_rec = 993, | |
| EXTSW_32 = 994, | |
| EXTSW_32_64 = 995, | |
| EXTSW_32_64_rec = 996, | |
| EXTSW_rec = 997, | |
| EnforceIEIO = 998, | |
| FABSD = 999, | |
| FABSD_rec = 1000, | |
| FABSS = 1001, | |
| FABSS_rec = 1002, | |
| FADD = 1003, | |
| FADDS = 1004, | |
| FADDS_rec = 1005, | |
| FADD_rec = 1006, | |
| FADDrtz = 1007, | |
| FCFID = 1008, | |
| FCFIDS = 1009, | |
| FCFIDS_rec = 1010, | |
| FCFIDU = 1011, | |
| FCFIDUS = 1012, | |
| FCFIDUS_rec = 1013, | |
| FCFIDU_rec = 1014, | |
| FCFID_rec = 1015, | |
| FCMPOD = 1016, | |
| FCMPOS = 1017, | |
| FCMPUD = 1018, | |
| FCMPUS = 1019, | |
| FCPSGND = 1020, | |
| FCPSGND_rec = 1021, | |
| FCPSGNS = 1022, | |
| FCPSGNS_rec = 1023, | |
| FCTID = 1024, | |
| FCTIDU = 1025, | |
| FCTIDUZ = 1026, | |
| FCTIDUZ_rec = 1027, | |
| FCTIDU_rec = 1028, | |
| FCTIDZ = 1029, | |
| FCTIDZ_rec = 1030, | |
| FCTID_rec = 1031, | |
| FCTIW = 1032, | |
| FCTIWU = 1033, | |
| FCTIWUZ = 1034, | |
| FCTIWUZ_rec = 1035, | |
| FCTIWU_rec = 1036, | |
| FCTIWZ = 1037, | |
| FCTIWZ_rec = 1038, | |
| FCTIW_rec = 1039, | |
| FDIV = 1040, | |
| FDIVS = 1041, | |
| FDIVS_rec = 1042, | |
| FDIV_rec = 1043, | |
| FMADD = 1044, | |
| FMADDS = 1045, | |
| FMADDS_rec = 1046, | |
| FMADD_rec = 1047, | |
| FMR = 1048, | |
| FMR_rec = 1049, | |
| FMSUB = 1050, | |
| FMSUBS = 1051, | |
| FMSUBS_rec = 1052, | |
| FMSUB_rec = 1053, | |
| FMUL = 1054, | |
| FMULS = 1055, | |
| FMULS_rec = 1056, | |
| FMUL_rec = 1057, | |
| FNABSD = 1058, | |
| FNABSD_rec = 1059, | |
| FNABSS = 1060, | |
| FNABSS_rec = 1061, | |
| FNEGD = 1062, | |
| FNEGD_rec = 1063, | |
| FNEGS = 1064, | |
| FNEGS_rec = 1065, | |
| FNMADD = 1066, | |
| FNMADDS = 1067, | |
| FNMADDS_rec = 1068, | |
| FNMADD_rec = 1069, | |
| FNMSUB = 1070, | |
| FNMSUBS = 1071, | |
| FNMSUBS_rec = 1072, | |
| FNMSUB_rec = 1073, | |
| FRE = 1074, | |
| FRES = 1075, | |
| FRES_rec = 1076, | |
| FRE_rec = 1077, | |
| FRIMD = 1078, | |
| FRIMD_rec = 1079, | |
| FRIMS = 1080, | |
| FRIMS_rec = 1081, | |
| FRIND = 1082, | |
| FRIND_rec = 1083, | |
| FRINS = 1084, | |
| FRINS_rec = 1085, | |
| FRIPD = 1086, | |
| FRIPD_rec = 1087, | |
| FRIPS = 1088, | |
| FRIPS_rec = 1089, | |
| FRIZD = 1090, | |
| FRIZD_rec = 1091, | |
| FRIZS = 1092, | |
| FRIZS_rec = 1093, | |
| FRSP = 1094, | |
| FRSP_rec = 1095, | |
| FRSQRTE = 1096, | |
| FRSQRTES = 1097, | |
| FRSQRTES_rec = 1098, | |
| FRSQRTE_rec = 1099, | |
| FSELD = 1100, | |
| FSELD_rec = 1101, | |
| FSELS = 1102, | |
| FSELS_rec = 1103, | |
| FSQRT = 1104, | |
| FSQRTS = 1105, | |
| FSQRTS_rec = 1106, | |
| FSQRT_rec = 1107, | |
| FSUB = 1108, | |
| FSUBS = 1109, | |
| FSUBS_rec = 1110, | |
| FSUB_rec = 1111, | |
| FTDIV = 1112, | |
| FTSQRT = 1113, | |
| GETtlsADDR = 1114, | |
| GETtlsADDR32 = 1115, | |
| GETtlsADDR32AIX = 1116, | |
| GETtlsADDR64AIX = 1117, | |
| GETtlsADDRPCREL = 1118, | |
| GETtlsldADDR = 1119, | |
| GETtlsldADDR32 = 1120, | |
| GETtlsldADDRPCREL = 1121, | |
| HASHCHK = 1122, | |
| HASHCHK8 = 1123, | |
| HASHCHKP = 1124, | |
| HASHCHKP8 = 1125, | |
| HASHST = 1126, | |
| HASHST8 = 1127, | |
| HASHSTP = 1128, | |
| HASHSTP8 = 1129, | |
| HRFID = 1130, | |
| ICBI = 1131, | |
| ICBIEP = 1132, | |
| ICBLC = 1133, | |
| ICBLQ = 1134, | |
| ICBT = 1135, | |
| ICBTLS = 1136, | |
| ICCCI = 1137, | |
| ISEL = 1138, | |
| ISEL8 = 1139, | |
| ISYNC = 1140, | |
| LA = 1141, | |
| LA8 = 1142, | |
| LBARX = 1143, | |
| LBARXL = 1144, | |
| LBEPX = 1145, | |
| LBZ = 1146, | |
| LBZ8 = 1147, | |
| LBZCIX = 1148, | |
| LBZU = 1149, | |
| LBZU8 = 1150, | |
| LBZUX = 1151, | |
| LBZUX8 = 1152, | |
| LBZX = 1153, | |
| LBZX8 = 1154, | |
| LBZXTLS = 1155, | |
| LBZXTLS_ = 1156, | |
| LBZXTLS_32 = 1157, | |
| LD = 1158, | |
| LDARX = 1159, | |
| LDARXL = 1160, | |
| LDAT = 1161, | |
| LDBRX = 1162, | |
| LDCIX = 1163, | |
| LDU = 1164, | |
| LDUX = 1165, | |
| LDX = 1166, | |
| LDXTLS = 1167, | |
| LDXTLS_ = 1168, | |
| LDgotTprelL = 1169, | |
| LDgotTprelL32 = 1170, | |
| LDtoc = 1171, | |
| LDtocBA = 1172, | |
| LDtocCPT = 1173, | |
| LDtocJTI = 1174, | |
| LDtocL = 1175, | |
| LFD = 1176, | |
| LFDEPX = 1177, | |
| LFDU = 1178, | |
| LFDUX = 1179, | |
| LFDX = 1180, | |
| LFIWAX = 1181, | |
| LFIWZX = 1182, | |
| LFS = 1183, | |
| LFSU = 1184, | |
| LFSUX = 1185, | |
| LFSX = 1186, | |
| LHA = 1187, | |
| LHA8 = 1188, | |
| LHARX = 1189, | |
| LHARXL = 1190, | |
| LHAU = 1191, | |
| LHAU8 = 1192, | |
| LHAUX = 1193, | |
| LHAUX8 = 1194, | |
| LHAX = 1195, | |
| LHAX8 = 1196, | |
| LHBRX = 1197, | |
| LHBRX8 = 1198, | |
| LHEPX = 1199, | |
| LHZ = 1200, | |
| LHZ8 = 1201, | |
| LHZCIX = 1202, | |
| LHZU = 1203, | |
| LHZU8 = 1204, | |
| LHZUX = 1205, | |
| LHZUX8 = 1206, | |
| LHZX = 1207, | |
| LHZX8 = 1208, | |
| LHZXTLS = 1209, | |
| LHZXTLS_ = 1210, | |
| LHZXTLS_32 = 1211, | |
| LI = 1212, | |
| LI8 = 1213, | |
| LIS = 1214, | |
| LIS8 = 1215, | |
| LMW = 1216, | |
| LQ = 1217, | |
| LQARX = 1218, | |
| LQARXL = 1219, | |
| LQX_PSEUDO = 1220, | |
| LSWI = 1221, | |
| LVEBX = 1222, | |
| LVEHX = 1223, | |
| LVEWX = 1224, | |
| LVSL = 1225, | |
| LVSR = 1226, | |
| LVX = 1227, | |
| LVXL = 1228, | |
| LWA = 1229, | |
| LWARX = 1230, | |
| LWARXL = 1231, | |
| LWAT = 1232, | |
| LWAUX = 1233, | |
| LWAX = 1234, | |
| LWAX_32 = 1235, | |
| LWA_32 = 1236, | |
| LWBRX = 1237, | |
| LWBRX8 = 1238, | |
| LWEPX = 1239, | |
| LWZ = 1240, | |
| LWZ8 = 1241, | |
| LWZCIX = 1242, | |
| LWZU = 1243, | |
| LWZU8 = 1244, | |
| LWZUX = 1245, | |
| LWZUX8 = 1246, | |
| LWZX = 1247, | |
| LWZX8 = 1248, | |
| LWZXTLS = 1249, | |
| LWZXTLS_ = 1250, | |
| LWZXTLS_32 = 1251, | |
| LWZtoc = 1252, | |
| LWZtocL = 1253, | |
| LXSD = 1254, | |
| LXSDX = 1255, | |
| LXSIBZX = 1256, | |
| LXSIHZX = 1257, | |
| LXSIWAX = 1258, | |
| LXSIWZX = 1259, | |
| LXSSP = 1260, | |
| LXSSPX = 1261, | |
| LXV = 1262, | |
| LXVB16X = 1263, | |
| LXVD2X = 1264, | |
| LXVDSX = 1265, | |
| LXVH8X = 1266, | |
| LXVKQ = 1267, | |
| LXVL = 1268, | |
| LXVLL = 1269, | |
| LXVP = 1270, | |
| LXVPRL = 1271, | |
| LXVPRLL = 1272, | |
| LXVPX = 1273, | |
| LXVRBX = 1274, | |
| LXVRDX = 1275, | |
| LXVRHX = 1276, | |
| LXVRL = 1277, | |
| LXVRLL = 1278, | |
| LXVRWX = 1279, | |
| LXVW4X = 1280, | |
| LXVWSX = 1281, | |
| LXVX = 1282, | |
| MADDHD = 1283, | |
| MADDHDU = 1284, | |
| MADDLD = 1285, | |
| MADDLD8 = 1286, | |
| MBAR = 1287, | |
| MCRF = 1288, | |
| MCRFS = 1289, | |
| MCRXRX = 1290, | |
| MFBHRBE = 1291, | |
| MFCR = 1292, | |
| MFCR8 = 1293, | |
| MFCTR = 1294, | |
| MFCTR8 = 1295, | |
| MFDCR = 1296, | |
| MFFS = 1297, | |
| MFFSCDRN = 1298, | |
| MFFSCDRNI = 1299, | |
| MFFSCE = 1300, | |
| MFFSCRN = 1301, | |
| MFFSCRNI = 1302, | |
| MFFSL = 1303, | |
| MFFS_rec = 1304, | |
| MFLR = 1305, | |
| MFLR8 = 1306, | |
| MFMSR = 1307, | |
| MFOCRF = 1308, | |
| MFOCRF8 = 1309, | |
| MFPMR = 1310, | |
| MFSPR = 1311, | |
| MFSPR8 = 1312, | |
| MFSR = 1313, | |
| MFSRIN = 1314, | |
| MFTB = 1315, | |
| MFTB8 = 1316, | |
| MFUDSCR = 1317, | |
| MFVRD = 1318, | |
| MFVRSAVE = 1319, | |
| MFVRSAVEv = 1320, | |
| MFVRWZ = 1321, | |
| MFVSCR = 1322, | |
| MFVSRD = 1323, | |
| MFVSRLD = 1324, | |
| MFVSRWZ = 1325, | |
| MODSD = 1326, | |
| MODSW = 1327, | |
| MODUD = 1328, | |
| MODUW = 1329, | |
| MSGSYNC = 1330, | |
| MSYNC = 1331, | |
| MTCRF = 1332, | |
| MTCRF8 = 1333, | |
| MTCTR = 1334, | |
| MTCTR8 = 1335, | |
| MTCTR8loop = 1336, | |
| MTCTRloop = 1337, | |
| MTDCR = 1338, | |
| MTFSB0 = 1339, | |
| MTFSB1 = 1340, | |
| MTFSF = 1341, | |
| MTFSFI = 1342, | |
| MTFSFI_rec = 1343, | |
| MTFSFIb = 1344, | |
| MTFSF_rec = 1345, | |
| MTFSFb = 1346, | |
| MTLR = 1347, | |
| MTLR8 = 1348, | |
| MTMSR = 1349, | |
| MTMSRD = 1350, | |
| MTOCRF = 1351, | |
| MTOCRF8 = 1352, | |
| MTPMR = 1353, | |
| MTSPR = 1354, | |
| MTSPR8 = 1355, | |
| MTSR = 1356, | |
| MTSRIN = 1357, | |
| MTUDSCR = 1358, | |
| MTVRD = 1359, | |
| MTVRSAVE = 1360, | |
| MTVRSAVEv = 1361, | |
| MTVRWA = 1362, | |
| MTVRWZ = 1363, | |
| MTVSCR = 1364, | |
| MTVSRBM = 1365, | |
| MTVSRBMI = 1366, | |
| MTVSRD = 1367, | |
| MTVSRDD = 1368, | |
| MTVSRDM = 1369, | |
| MTVSRHM = 1370, | |
| MTVSRQM = 1371, | |
| MTVSRWA = 1372, | |
| MTVSRWM = 1373, | |
| MTVSRWS = 1374, | |
| MTVSRWZ = 1375, | |
| MULHD = 1376, | |
| MULHDU = 1377, | |
| MULHDU_rec = 1378, | |
| MULHD_rec = 1379, | |
| MULHW = 1380, | |
| MULHWU = 1381, | |
| MULHWU_rec = 1382, | |
| MULHW_rec = 1383, | |
| MULLD = 1384, | |
| MULLDO = 1385, | |
| MULLDO_rec = 1386, | |
| MULLD_rec = 1387, | |
| MULLI = 1388, | |
| MULLI8 = 1389, | |
| MULLW = 1390, | |
| MULLWO = 1391, | |
| MULLWO_rec = 1392, | |
| MULLW_rec = 1393, | |
| MoveGOTtoLR = 1394, | |
| MovePCtoLR = 1395, | |
| MovePCtoLR8 = 1396, | |
| NAND = 1397, | |
| NAND8 = 1398, | |
| NAND8_rec = 1399, | |
| NAND_rec = 1400, | |
| NAP = 1401, | |
| NEG = 1402, | |
| NEG8 = 1403, | |
| NEG8O = 1404, | |
| NEG8O_rec = 1405, | |
| NEG8_rec = 1406, | |
| NEGO = 1407, | |
| NEGO_rec = 1408, | |
| NEG_rec = 1409, | |
| NOP = 1410, | |
| NOP_GT_PWR6 = 1411, | |
| NOP_GT_PWR7 = 1412, | |
| NOR = 1413, | |
| NOR8 = 1414, | |
| NOR8_rec = 1415, | |
| NOR_rec = 1416, | |
| OR = 1417, | |
| OR8 = 1418, | |
| OR8_rec = 1419, | |
| ORC = 1420, | |
| ORC8 = 1421, | |
| ORC8_rec = 1422, | |
| ORC_rec = 1423, | |
| ORI = 1424, | |
| ORI8 = 1425, | |
| ORIS = 1426, | |
| ORIS8 = 1427, | |
| OR_rec = 1428, | |
| PADDI = 1429, | |
| PADDI8 = 1430, | |
| PADDI8pc = 1431, | |
| PADDIdtprel = 1432, | |
| PADDIpc = 1433, | |
| PDEPD = 1434, | |
| PEXTD = 1435, | |
| PLBZ = 1436, | |
| PLBZ8 = 1437, | |
| PLBZ8pc = 1438, | |
| PLBZpc = 1439, | |
| PLD = 1440, | |
| PLDpc = 1441, | |
| PLFD = 1442, | |
| PLFDpc = 1443, | |
| PLFS = 1444, | |
| PLFSpc = 1445, | |
| PLHA = 1446, | |
| PLHA8 = 1447, | |
| PLHA8pc = 1448, | |
| PLHApc = 1449, | |
| PLHZ = 1450, | |
| PLHZ8 = 1451, | |
| PLHZ8pc = 1452, | |
| PLHZpc = 1453, | |
| PLI = 1454, | |
| PLI8 = 1455, | |
| PLWA = 1456, | |
| PLWA8 = 1457, | |
| PLWA8pc = 1458, | |
| PLWApc = 1459, | |
| PLWZ = 1460, | |
| PLWZ8 = 1461, | |
| PLWZ8pc = 1462, | |
| PLWZpc = 1463, | |
| PLXSD = 1464, | |
| PLXSDpc = 1465, | |
| PLXSSP = 1466, | |
| PLXSSPpc = 1467, | |
| PLXV = 1468, | |
| PLXVP = 1469, | |
| PLXVPpc = 1470, | |
| PLXVpc = 1471, | |
| PMXVBF16GER2 = 1472, | |
| PMXVBF16GER2NN = 1473, | |
| PMXVBF16GER2NP = 1474, | |
| PMXVBF16GER2PN = 1475, | |
| PMXVBF16GER2PP = 1476, | |
| PMXVBF16GER2W = 1477, | |
| PMXVBF16GER2WNN = 1478, | |
| PMXVBF16GER2WNP = 1479, | |
| PMXVBF16GER2WPN = 1480, | |
| PMXVBF16GER2WPP = 1481, | |
| PMXVF16GER2 = 1482, | |
| PMXVF16GER2NN = 1483, | |
| PMXVF16GER2NP = 1484, | |
| PMXVF16GER2PN = 1485, | |
| PMXVF16GER2PP = 1486, | |
| PMXVF16GER2W = 1487, | |
| PMXVF16GER2WNN = 1488, | |
| PMXVF16GER2WNP = 1489, | |
| PMXVF16GER2WPN = 1490, | |
| PMXVF16GER2WPP = 1491, | |
| PMXVF32GER = 1492, | |
| PMXVF32GERNN = 1493, | |
| PMXVF32GERNP = 1494, | |
| PMXVF32GERPN = 1495, | |
| PMXVF32GERPP = 1496, | |
| PMXVF32GERW = 1497, | |
| PMXVF32GERWNN = 1498, | |
| PMXVF32GERWNP = 1499, | |
| PMXVF32GERWPN = 1500, | |
| PMXVF32GERWPP = 1501, | |
| PMXVF64GER = 1502, | |
| PMXVF64GERNN = 1503, | |
| PMXVF64GERNP = 1504, | |
| PMXVF64GERPN = 1505, | |
| PMXVF64GERPP = 1506, | |
| PMXVF64GERW = 1507, | |
| PMXVF64GERWNN = 1508, | |
| PMXVF64GERWNP = 1509, | |
| PMXVF64GERWPN = 1510, | |
| PMXVF64GERWPP = 1511, | |
| PMXVI16GER2 = 1512, | |
| PMXVI16GER2PP = 1513, | |
| PMXVI16GER2S = 1514, | |
| PMXVI16GER2SPP = 1515, | |
| PMXVI16GER2SW = 1516, | |
| PMXVI16GER2SWPP = 1517, | |
| PMXVI16GER2W = 1518, | |
| PMXVI16GER2WPP = 1519, | |
| PMXVI4GER8 = 1520, | |
| PMXVI4GER8PP = 1521, | |
| PMXVI4GER8W = 1522, | |
| PMXVI4GER8WPP = 1523, | |
| PMXVI8GER4 = 1524, | |
| PMXVI8GER4PP = 1525, | |
| PMXVI8GER4SPP = 1526, | |
| PMXVI8GER4W = 1527, | |
| PMXVI8GER4WPP = 1528, | |
| PMXVI8GER4WSPP = 1529, | |
| POPCNTB = 1530, | |
| POPCNTB8 = 1531, | |
| POPCNTD = 1532, | |
| POPCNTW = 1533, | |
| PPC32GOT = 1534, | |
| PPC32PICGOT = 1535, | |
| PREPARE_PROBED_ALLOCA_32 = 1536, | |
| PREPARE_PROBED_ALLOCA_64 = 1537, | |
| PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 = 1538, | |
| PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 = 1539, | |
| PROBED_ALLOCA_32 = 1540, | |
| PROBED_ALLOCA_64 = 1541, | |
| PROBED_STACKALLOC_32 = 1542, | |
| PROBED_STACKALLOC_64 = 1543, | |
| PSTB = 1544, | |
| PSTB8 = 1545, | |
| PSTB8pc = 1546, | |
| PSTBpc = 1547, | |
| PSTD = 1548, | |
| PSTDpc = 1549, | |
| PSTFD = 1550, | |
| PSTFDpc = 1551, | |
| PSTFS = 1552, | |
| PSTFSpc = 1553, | |
| PSTH = 1554, | |
| PSTH8 = 1555, | |
| PSTH8pc = 1556, | |
| PSTHpc = 1557, | |
| PSTW = 1558, | |
| PSTW8 = 1559, | |
| PSTW8pc = 1560, | |
| PSTWpc = 1561, | |
| PSTXSD = 1562, | |
| PSTXSDpc = 1563, | |
| PSTXSSP = 1564, | |
| PSTXSSPpc = 1565, | |
| PSTXV = 1566, | |
| PSTXVP = 1567, | |
| PSTXVPpc = 1568, | |
| PSTXVpc = 1569, | |
| PseudoEIEIO = 1570, | |
| RESTORE_ACC = 1571, | |
| RESTORE_CR = 1572, | |
| RESTORE_CRBIT = 1573, | |
| RESTORE_QUADWORD = 1574, | |
| RESTORE_UACC = 1575, | |
| RESTORE_WACC = 1576, | |
| RFCI = 1577, | |
| RFDI = 1578, | |
| RFEBB = 1579, | |
| RFI = 1580, | |
| RFID = 1581, | |
| RFMCI = 1582, | |
| RLDCL = 1583, | |
| RLDCL_rec = 1584, | |
| RLDCR = 1585, | |
| RLDCR_rec = 1586, | |
| RLDIC = 1587, | |
| RLDICL = 1588, | |
| RLDICL_32 = 1589, | |
| RLDICL_32_64 = 1590, | |
| RLDICL_32_rec = 1591, | |
| RLDICL_rec = 1592, | |
| RLDICR = 1593, | |
| RLDICR_32 = 1594, | |
| RLDICR_rec = 1595, | |
| RLDIC_rec = 1596, | |
| RLDIMI = 1597, | |
| RLDIMI_rec = 1598, | |
| RLWIMI = 1599, | |
| RLWIMI8 = 1600, | |
| RLWIMI8_rec = 1601, | |
| RLWIMI_rec = 1602, | |
| RLWINM = 1603, | |
| RLWINM8 = 1604, | |
| RLWINM8_rec = 1605, | |
| RLWINM_rec = 1606, | |
| RLWNM = 1607, | |
| RLWNM8 = 1608, | |
| RLWNM8_rec = 1609, | |
| RLWNM_rec = 1610, | |
| ReadTB = 1611, | |
| SC = 1612, | |
| SELECT_CC_F16 = 1613, | |
| SELECT_CC_F4 = 1614, | |
| SELECT_CC_F8 = 1615, | |
| SELECT_CC_I4 = 1616, | |
| SELECT_CC_I8 = 1617, | |
| SELECT_CC_SPE = 1618, | |
| SELECT_CC_SPE4 = 1619, | |
| SELECT_CC_VRRC = 1620, | |
| SELECT_CC_VSFRC = 1621, | |
| SELECT_CC_VSRC = 1622, | |
| SELECT_CC_VSSRC = 1623, | |
| SELECT_F16 = 1624, | |
| SELECT_F4 = 1625, | |
| SELECT_F8 = 1626, | |
| SELECT_I4 = 1627, | |
| SELECT_I8 = 1628, | |
| SELECT_SPE = 1629, | |
| SELECT_SPE4 = 1630, | |
| SELECT_VRRC = 1631, | |
| SELECT_VSFRC = 1632, | |
| SELECT_VSRC = 1633, | |
| SELECT_VSSRC = 1634, | |
| SETB = 1635, | |
| SETB8 = 1636, | |
| SETBC = 1637, | |
| SETBC8 = 1638, | |
| SETBCR = 1639, | |
| SETBCR8 = 1640, | |
| SETFLM = 1641, | |
| SETNBC = 1642, | |
| SETNBC8 = 1643, | |
| SETNBCR = 1644, | |
| SETNBCR8 = 1645, | |
| SETRND = 1646, | |
| SETRNDi = 1647, | |
| SLBFEE_rec = 1648, | |
| SLBIA = 1649, | |
| SLBIE = 1650, | |
| SLBIEG = 1651, | |
| SLBMFEE = 1652, | |
| SLBMFEV = 1653, | |
| SLBMTE = 1654, | |
| SLBSYNC = 1655, | |
| SLD = 1656, | |
| SLD_rec = 1657, | |
| SLW = 1658, | |
| SLW8 = 1659, | |
| SLW8_rec = 1660, | |
| SLW_rec = 1661, | |
| SPELWZ = 1662, | |
| SPELWZX = 1663, | |
| SPESTW = 1664, | |
| SPESTWX = 1665, | |
| SPILL_ACC = 1666, | |
| SPILL_CR = 1667, | |
| SPILL_CRBIT = 1668, | |
| SPILL_QUADWORD = 1669, | |
| SPILL_UACC = 1670, | |
| SPILL_WACC = 1671, | |
| SPLIT_QUADWORD = 1672, | |
| SRAD = 1673, | |
| SRADI = 1674, | |
| SRADI_32 = 1675, | |
| SRADI_rec = 1676, | |
| SRAD_rec = 1677, | |
| SRAW = 1678, | |
| SRAWI = 1679, | |
| SRAWI_rec = 1680, | |
| SRAW_rec = 1681, | |
| SRD = 1682, | |
| SRD_rec = 1683, | |
| SRW = 1684, | |
| SRW8 = 1685, | |
| SRW8_rec = 1686, | |
| SRW_rec = 1687, | |
| STB = 1688, | |
| STB8 = 1689, | |
| STBCIX = 1690, | |
| STBCX = 1691, | |
| STBEPX = 1692, | |
| STBU = 1693, | |
| STBU8 = 1694, | |
| STBUX = 1695, | |
| STBUX8 = 1696, | |
| STBX = 1697, | |
| STBX8 = 1698, | |
| STBXTLS = 1699, | |
| STBXTLS_ = 1700, | |
| STBXTLS_32 = 1701, | |
| STD = 1702, | |
| STDAT = 1703, | |
| STDBRX = 1704, | |
| STDCIX = 1705, | |
| STDCX = 1706, | |
| STDU = 1707, | |
| STDUX = 1708, | |
| STDX = 1709, | |
| STDXTLS = 1710, | |
| STDXTLS_ = 1711, | |
| STFD = 1712, | |
| STFDEPX = 1713, | |
| STFDU = 1714, | |
| STFDUX = 1715, | |
| STFDX = 1716, | |
| STFIWX = 1717, | |
| STFS = 1718, | |
| STFSU = 1719, | |
| STFSUX = 1720, | |
| STFSX = 1721, | |
| STH = 1722, | |
| STH8 = 1723, | |
| STHBRX = 1724, | |
| STHCIX = 1725, | |
| STHCX = 1726, | |
| STHEPX = 1727, | |
| STHU = 1728, | |
| STHU8 = 1729, | |
| STHUX = 1730, | |
| STHUX8 = 1731, | |
| STHX = 1732, | |
| STHX8 = 1733, | |
| STHXTLS = 1734, | |
| STHXTLS_ = 1735, | |
| STHXTLS_32 = 1736, | |
| STMW = 1737, | |
| STOP = 1738, | |
| STQ = 1739, | |
| STQCX = 1740, | |
| STQX_PSEUDO = 1741, | |
| STSWI = 1742, | |
| STVEBX = 1743, | |
| STVEHX = 1744, | |
| STVEWX = 1745, | |
| STVX = 1746, | |
| STVXL = 1747, | |
| STW = 1748, | |
| STW8 = 1749, | |
| STWAT = 1750, | |
| STWBRX = 1751, | |
| STWCIX = 1752, | |
| STWCX = 1753, | |
| STWEPX = 1754, | |
| STWU = 1755, | |
| STWU8 = 1756, | |
| STWUX = 1757, | |
| STWUX8 = 1758, | |
| STWX = 1759, | |
| STWX8 = 1760, | |
| STWXTLS = 1761, | |
| STWXTLS_ = 1762, | |
| STWXTLS_32 = 1763, | |
| STXSD = 1764, | |
| STXSDX = 1765, | |
| STXSIBX = 1766, | |
| STXSIBXv = 1767, | |
| STXSIHX = 1768, | |
| STXSIHXv = 1769, | |
| STXSIWX = 1770, | |
| STXSSP = 1771, | |
| STXSSPX = 1772, | |
| STXV = 1773, | |
| STXVB16X = 1774, | |
| STXVD2X = 1775, | |
| STXVH8X = 1776, | |
| STXVL = 1777, | |
| STXVLL = 1778, | |
| STXVP = 1779, | |
| STXVPRL = 1780, | |
| STXVPRLL = 1781, | |
| STXVPX = 1782, | |
| STXVRBX = 1783, | |
| STXVRDX = 1784, | |
| STXVRHX = 1785, | |
| STXVRL = 1786, | |
| STXVRLL = 1787, | |
| STXVRWX = 1788, | |
| STXVW4X = 1789, | |
| STXVX = 1790, | |
| SUBF = 1791, | |
| SUBF8 = 1792, | |
| SUBF8O = 1793, | |
| SUBF8O_rec = 1794, | |
| SUBF8_rec = 1795, | |
| SUBFC = 1796, | |
| SUBFC8 = 1797, | |
| SUBFC8O = 1798, | |
| SUBFC8O_rec = 1799, | |
| SUBFC8_rec = 1800, | |
| SUBFCO = 1801, | |
| SUBFCO_rec = 1802, | |
| SUBFC_rec = 1803, | |
| SUBFE = 1804, | |
| SUBFE8 = 1805, | |
| SUBFE8O = 1806, | |
| SUBFE8O_rec = 1807, | |
| SUBFE8_rec = 1808, | |
| SUBFEO = 1809, | |
| SUBFEO_rec = 1810, | |
| SUBFE_rec = 1811, | |
| SUBFIC = 1812, | |
| SUBFIC8 = 1813, | |
| SUBFME = 1814, | |
| SUBFME8 = 1815, | |
| SUBFME8O = 1816, | |
| SUBFME8O_rec = 1817, | |
| SUBFME8_rec = 1818, | |
| SUBFMEO = 1819, | |
| SUBFMEO_rec = 1820, | |
| SUBFME_rec = 1821, | |
| SUBFO = 1822, | |
| SUBFO_rec = 1823, | |
| SUBFUS = 1824, | |
| SUBFUS_rec = 1825, | |
| SUBFZE = 1826, | |
| SUBFZE8 = 1827, | |
| SUBFZE8O = 1828, | |
| SUBFZE8O_rec = 1829, | |
| SUBFZE8_rec = 1830, | |
| SUBFZEO = 1831, | |
| SUBFZEO_rec = 1832, | |
| SUBFZE_rec = 1833, | |
| SUBF_rec = 1834, | |
| SYNC = 1835, | |
| TABORT = 1836, | |
| TABORTDC = 1837, | |
| TABORTDCI = 1838, | |
| TABORTWC = 1839, | |
| TABORTWCI = 1840, | |
| TAILB = 1841, | |
| TAILB8 = 1842, | |
| TAILBA = 1843, | |
| TAILBA8 = 1844, | |
| TAILBCTR = 1845, | |
| TAILBCTR8 = 1846, | |
| TBEGIN = 1847, | |
| TBEGIN_RET = 1848, | |
| TCHECK = 1849, | |
| TCHECK_RET = 1850, | |
| TCRETURNai = 1851, | |
| TCRETURNai8 = 1852, | |
| TCRETURNdi = 1853, | |
| TCRETURNdi8 = 1854, | |
| TCRETURNri = 1855, | |
| TCRETURNri8 = 1856, | |
| TD = 1857, | |
| TDI = 1858, | |
| TEND = 1859, | |
| TLBIA = 1860, | |
| TLBIE = 1861, | |
| TLBIEL = 1862, | |
| TLBIVAX = 1863, | |
| TLBLD = 1864, | |
| TLBLI = 1865, | |
| TLBRE = 1866, | |
| TLBRE2 = 1867, | |
| TLBSX = 1868, | |
| TLBSX2 = 1869, | |
| TLBSX2D = 1870, | |
| TLBSYNC = 1871, | |
| TLBWE = 1872, | |
| TLBWE2 = 1873, | |
| TLSGDAIX = 1874, | |
| TLSGDAIX8 = 1875, | |
| TRAP = 1876, | |
| TRECHKPT = 1877, | |
| TRECLAIM = 1878, | |
| TSR = 1879, | |
| TW = 1880, | |
| TWI = 1881, | |
| UNENCODED_NOP = 1882, | |
| UpdateGBR = 1883, | |
| VABSDUB = 1884, | |
| VABSDUH = 1885, | |
| VABSDUW = 1886, | |
| VADDCUQ = 1887, | |
| VADDCUW = 1888, | |
| VADDECUQ = 1889, | |
| VADDEUQM = 1890, | |
| VADDFP = 1891, | |
| VADDSBS = 1892, | |
| VADDSHS = 1893, | |
| VADDSWS = 1894, | |
| VADDUBM = 1895, | |
| VADDUBS = 1896, | |
| VADDUDM = 1897, | |
| VADDUHM = 1898, | |
| VADDUHS = 1899, | |
| VADDUQM = 1900, | |
| VADDUWM = 1901, | |
| VADDUWS = 1902, | |
| VAND = 1903, | |
| VANDC = 1904, | |
| VAVGSB = 1905, | |
| VAVGSH = 1906, | |
| VAVGSW = 1907, | |
| VAVGUB = 1908, | |
| VAVGUH = 1909, | |
| VAVGUW = 1910, | |
| VBPERMD = 1911, | |
| VBPERMQ = 1912, | |
| VCFSX = 1913, | |
| VCFSX_0 = 1914, | |
| VCFUGED = 1915, | |
| VCFUX = 1916, | |
| VCFUX_0 = 1917, | |
| VCIPHER = 1918, | |
| VCIPHERLAST = 1919, | |
| VCLRLB = 1920, | |
| VCLRRB = 1921, | |
| VCLZB = 1922, | |
| VCLZD = 1923, | |
| VCLZDM = 1924, | |
| VCLZH = 1925, | |
| VCLZLSBB = 1926, | |
| VCLZW = 1927, | |
| VCMPBFP = 1928, | |
| VCMPBFP_rec = 1929, | |
| VCMPEQFP = 1930, | |
| VCMPEQFP_rec = 1931, | |
| VCMPEQUB = 1932, | |
| VCMPEQUB_rec = 1933, | |
| VCMPEQUD = 1934, | |
| VCMPEQUD_rec = 1935, | |
| VCMPEQUH = 1936, | |
| VCMPEQUH_rec = 1937, | |
| VCMPEQUQ = 1938, | |
| VCMPEQUQ_rec = 1939, | |
| VCMPEQUW = 1940, | |
| VCMPEQUW_rec = 1941, | |
| VCMPGEFP = 1942, | |
| VCMPGEFP_rec = 1943, | |
| VCMPGTFP = 1944, | |
| VCMPGTFP_rec = 1945, | |
| VCMPGTSB = 1946, | |
| VCMPGTSB_rec = 1947, | |
| VCMPGTSD = 1948, | |
| VCMPGTSD_rec = 1949, | |
| VCMPGTSH = 1950, | |
| VCMPGTSH_rec = 1951, | |
| VCMPGTSQ = 1952, | |
| VCMPGTSQ_rec = 1953, | |
| VCMPGTSW = 1954, | |
| VCMPGTSW_rec = 1955, | |
| VCMPGTUB = 1956, | |
| VCMPGTUB_rec = 1957, | |
| VCMPGTUD = 1958, | |
| VCMPGTUD_rec = 1959, | |
| VCMPGTUH = 1960, | |
| VCMPGTUH_rec = 1961, | |
| VCMPGTUQ = 1962, | |
| VCMPGTUQ_rec = 1963, | |
| VCMPGTUW = 1964, | |
| VCMPGTUW_rec = 1965, | |
| VCMPNEB = 1966, | |
| VCMPNEB_rec = 1967, | |
| VCMPNEH = 1968, | |
| VCMPNEH_rec = 1969, | |
| VCMPNEW = 1970, | |
| VCMPNEW_rec = 1971, | |
| VCMPNEZB = 1972, | |
| VCMPNEZB_rec = 1973, | |
| VCMPNEZH = 1974, | |
| VCMPNEZH_rec = 1975, | |
| VCMPNEZW = 1976, | |
| VCMPNEZW_rec = 1977, | |
| VCMPSQ = 1978, | |
| VCMPUQ = 1979, | |
| VCNTMBB = 1980, | |
| VCNTMBD = 1981, | |
| VCNTMBH = 1982, | |
| VCNTMBW = 1983, | |
| VCTSXS = 1984, | |
| VCTSXS_0 = 1985, | |
| VCTUXS = 1986, | |
| VCTUXS_0 = 1987, | |
| VCTZB = 1988, | |
| VCTZD = 1989, | |
| VCTZDM = 1990, | |
| VCTZH = 1991, | |
| VCTZLSBB = 1992, | |
| VCTZW = 1993, | |
| VDIVESD = 1994, | |
| VDIVESQ = 1995, | |
| VDIVESW = 1996, | |
| VDIVEUD = 1997, | |
| VDIVEUQ = 1998, | |
| VDIVEUW = 1999, | |
| VDIVSD = 2000, | |
| VDIVSQ = 2001, | |
| VDIVSW = 2002, | |
| VDIVUD = 2003, | |
| VDIVUQ = 2004, | |
| VDIVUW = 2005, | |
| VEQV = 2006, | |
| VEXPANDBM = 2007, | |
| VEXPANDDM = 2008, | |
| VEXPANDHM = 2009, | |
| VEXPANDQM = 2010, | |
| VEXPANDWM = 2011, | |
| VEXPTEFP = 2012, | |
| VEXTDDVLX = 2013, | |
| VEXTDDVRX = 2014, | |
| VEXTDUBVLX = 2015, | |
| VEXTDUBVRX = 2016, | |
| VEXTDUHVLX = 2017, | |
| VEXTDUHVRX = 2018, | |
| VEXTDUWVLX = 2019, | |
| VEXTDUWVRX = 2020, | |
| VEXTRACTBM = 2021, | |
| VEXTRACTD = 2022, | |
| VEXTRACTDM = 2023, | |
| VEXTRACTHM = 2024, | |
| VEXTRACTQM = 2025, | |
| VEXTRACTUB = 2026, | |
| VEXTRACTUH = 2027, | |
| VEXTRACTUW = 2028, | |
| VEXTRACTWM = 2029, | |
| VEXTSB2D = 2030, | |
| VEXTSB2Ds = 2031, | |
| VEXTSB2W = 2032, | |
| VEXTSB2Ws = 2033, | |
| VEXTSD2Q = 2034, | |
| VEXTSH2D = 2035, | |
| VEXTSH2Ds = 2036, | |
| VEXTSH2W = 2037, | |
| VEXTSH2Ws = 2038, | |
| VEXTSW2D = 2039, | |
| VEXTSW2Ds = 2040, | |
| VEXTUBLX = 2041, | |
| VEXTUBRX = 2042, | |
| VEXTUHLX = 2043, | |
| VEXTUHRX = 2044, | |
| VEXTUWLX = 2045, | |
| VEXTUWRX = 2046, | |
| VGBBD = 2047, | |
| VGNB = 2048, | |
| VINSBLX = 2049, | |
| VINSBRX = 2050, | |
| VINSBVLX = 2051, | |
| VINSBVRX = 2052, | |
| VINSD = 2053, | |
| VINSDLX = 2054, | |
| VINSDRX = 2055, | |
| VINSERTB = 2056, | |
| VINSERTD = 2057, | |
| VINSERTH = 2058, | |
| VINSERTW = 2059, | |
| VINSHLX = 2060, | |
| VINSHRX = 2061, | |
| VINSHVLX = 2062, | |
| VINSHVRX = 2063, | |
| VINSW = 2064, | |
| VINSWLX = 2065, | |
| VINSWRX = 2066, | |
| VINSWVLX = 2067, | |
| VINSWVRX = 2068, | |
| VLOGEFP = 2069, | |
| VMADDFP = 2070, | |
| VMAXFP = 2071, | |
| VMAXSB = 2072, | |
| VMAXSD = 2073, | |
| VMAXSH = 2074, | |
| VMAXSW = 2075, | |
| VMAXUB = 2076, | |
| VMAXUD = 2077, | |
| VMAXUH = 2078, | |
| VMAXUW = 2079, | |
| VMHADDSHS = 2080, | |
| VMHRADDSHS = 2081, | |
| VMINFP = 2082, | |
| VMINSB = 2083, | |
| VMINSD = 2084, | |
| VMINSH = 2085, | |
| VMINSW = 2086, | |
| VMINUB = 2087, | |
| VMINUD = 2088, | |
| VMINUH = 2089, | |
| VMINUW = 2090, | |
| VMLADDUHM = 2091, | |
| VMODSD = 2092, | |
| VMODSQ = 2093, | |
| VMODSW = 2094, | |
| VMODUD = 2095, | |
| VMODUQ = 2096, | |
| VMODUW = 2097, | |
| VMRGEW = 2098, | |
| VMRGHB = 2099, | |
| VMRGHH = 2100, | |
| VMRGHW = 2101, | |
| VMRGLB = 2102, | |
| VMRGLH = 2103, | |
| VMRGLW = 2104, | |
| VMRGOW = 2105, | |
| VMSUMCUD = 2106, | |
| VMSUMMBM = 2107, | |
| VMSUMSHM = 2108, | |
| VMSUMSHS = 2109, | |
| VMSUMUBM = 2110, | |
| VMSUMUDM = 2111, | |
| VMSUMUHM = 2112, | |
| VMSUMUHS = 2113, | |
| VMUL10CUQ = 2114, | |
| VMUL10ECUQ = 2115, | |
| VMUL10EUQ = 2116, | |
| VMUL10UQ = 2117, | |
| VMULESB = 2118, | |
| VMULESD = 2119, | |
| VMULESH = 2120, | |
| VMULESW = 2121, | |
| VMULEUB = 2122, | |
| VMULEUD = 2123, | |
| VMULEUH = 2124, | |
| VMULEUW = 2125, | |
| VMULHSD = 2126, | |
| VMULHSW = 2127, | |
| VMULHUD = 2128, | |
| VMULHUW = 2129, | |
| VMULLD = 2130, | |
| VMULOSB = 2131, | |
| VMULOSD = 2132, | |
| VMULOSH = 2133, | |
| VMULOSW = 2134, | |
| VMULOUB = 2135, | |
| VMULOUD = 2136, | |
| VMULOUH = 2137, | |
| VMULOUW = 2138, | |
| VMULUWM = 2139, | |
| VNAND = 2140, | |
| VNCIPHER = 2141, | |
| VNCIPHERLAST = 2142, | |
| VNEGD = 2143, | |
| VNEGW = 2144, | |
| VNMSUBFP = 2145, | |
| VNOR = 2146, | |
| VOR = 2147, | |
| VORC = 2148, | |
| VPDEPD = 2149, | |
| VPERM = 2150, | |
| VPERMR = 2151, | |
| VPERMXOR = 2152, | |
| VPEXTD = 2153, | |
| VPKPX = 2154, | |
| VPKSDSS = 2155, | |
| VPKSDUS = 2156, | |
| VPKSHSS = 2157, | |
| VPKSHUS = 2158, | |
| VPKSWSS = 2159, | |
| VPKSWUS = 2160, | |
| VPKUDUM = 2161, | |
| VPKUDUS = 2162, | |
| VPKUHUM = 2163, | |
| VPKUHUS = 2164, | |
| VPKUWUM = 2165, | |
| VPKUWUS = 2166, | |
| VPMSUMB = 2167, | |
| VPMSUMD = 2168, | |
| VPMSUMH = 2169, | |
| VPMSUMW = 2170, | |
| VPOPCNTB = 2171, | |
| VPOPCNTD = 2172, | |
| VPOPCNTH = 2173, | |
| VPOPCNTW = 2174, | |
| VPRTYBD = 2175, | |
| VPRTYBQ = 2176, | |
| VPRTYBW = 2177, | |
| VREFP = 2178, | |
| VRFIM = 2179, | |
| VRFIN = 2180, | |
| VRFIP = 2181, | |
| VRFIZ = 2182, | |
| VRLB = 2183, | |
| VRLD = 2184, | |
| VRLDMI = 2185, | |
| VRLDNM = 2186, | |
| VRLH = 2187, | |
| VRLQ = 2188, | |
| VRLQMI = 2189, | |
| VRLQNM = 2190, | |
| VRLW = 2191, | |
| VRLWMI = 2192, | |
| VRLWNM = 2193, | |
| VRSQRTEFP = 2194, | |
| VSBOX = 2195, | |
| VSEL = 2196, | |
| VSHASIGMAD = 2197, | |
| VSHASIGMAW = 2198, | |
| VSL = 2199, | |
| VSLB = 2200, | |
| VSLD = 2201, | |
| VSLDBI = 2202, | |
| VSLDOI = 2203, | |
| VSLH = 2204, | |
| VSLO = 2205, | |
| VSLQ = 2206, | |
| VSLV = 2207, | |
| VSLW = 2208, | |
| VSPLTB = 2209, | |
| VSPLTBs = 2210, | |
| VSPLTH = 2211, | |
| VSPLTHs = 2212, | |
| VSPLTISB = 2213, | |
| VSPLTISH = 2214, | |
| VSPLTISW = 2215, | |
| VSPLTW = 2216, | |
| VSR = 2217, | |
| VSRAB = 2218, | |
| VSRAD = 2219, | |
| VSRAH = 2220, | |
| VSRAQ = 2221, | |
| VSRAW = 2222, | |
| VSRB = 2223, | |
| VSRD = 2224, | |
| VSRDBI = 2225, | |
| VSRH = 2226, | |
| VSRO = 2227, | |
| VSRQ = 2228, | |
| VSRV = 2229, | |
| VSRW = 2230, | |
| VSTRIBL = 2231, | |
| VSTRIBL_rec = 2232, | |
| VSTRIBR = 2233, | |
| VSTRIBR_rec = 2234, | |
| VSTRIHL = 2235, | |
| VSTRIHL_rec = 2236, | |
| VSTRIHR = 2237, | |
| VSTRIHR_rec = 2238, | |
| VSUBCUQ = 2239, | |
| VSUBCUW = 2240, | |
| VSUBECUQ = 2241, | |
| VSUBEUQM = 2242, | |
| VSUBFP = 2243, | |
| VSUBSBS = 2244, | |
| VSUBSHS = 2245, | |
| VSUBSWS = 2246, | |
| VSUBUBM = 2247, | |
| VSUBUBS = 2248, | |
| VSUBUDM = 2249, | |
| VSUBUHM = 2250, | |
| VSUBUHS = 2251, | |
| VSUBUQM = 2252, | |
| VSUBUWM = 2253, | |
| VSUBUWS = 2254, | |
| VSUM2SWS = 2255, | |
| VSUM4SBS = 2256, | |
| VSUM4SHS = 2257, | |
| VSUM4UBS = 2258, | |
| VSUMSWS = 2259, | |
| VUPKHPX = 2260, | |
| VUPKHSB = 2261, | |
| VUPKHSH = 2262, | |
| VUPKHSW = 2263, | |
| VUPKLPX = 2264, | |
| VUPKLSB = 2265, | |
| VUPKLSH = 2266, | |
| VUPKLSW = 2267, | |
| VXOR = 2268, | |
| V_SET0 = 2269, | |
| V_SET0B = 2270, | |
| V_SET0H = 2271, | |
| V_SETALLONES = 2272, | |
| V_SETALLONESB = 2273, | |
| V_SETALLONESH = 2274, | |
| WAIT = 2275, | |
| WRTEE = 2276, | |
| WRTEEI = 2277, | |
| XOR = 2278, | |
| XOR8 = 2279, | |
| XOR8_rec = 2280, | |
| XORI = 2281, | |
| XORI8 = 2282, | |
| XORIS = 2283, | |
| XORIS8 = 2284, | |
| XOR_rec = 2285, | |
| XSABSDP = 2286, | |
| XSABSQP = 2287, | |
| XSADDDP = 2288, | |
| XSADDQP = 2289, | |
| XSADDQPO = 2290, | |
| XSADDSP = 2291, | |
| XSCMPEQDP = 2292, | |
| XSCMPEQQP = 2293, | |
| XSCMPEXPDP = 2294, | |
| XSCMPEXPQP = 2295, | |
| XSCMPGEDP = 2296, | |
| XSCMPGEQP = 2297, | |
| XSCMPGTDP = 2298, | |
| XSCMPGTQP = 2299, | |
| XSCMPODP = 2300, | |
| XSCMPOQP = 2301, | |
| XSCMPUDP = 2302, | |
| XSCMPUQP = 2303, | |
| XSCPSGNDP = 2304, | |
| XSCPSGNQP = 2305, | |
| XSCVDPHP = 2306, | |
| XSCVDPQP = 2307, | |
| XSCVDPSP = 2308, | |
| XSCVDPSPN = 2309, | |
| XSCVDPSXDS = 2310, | |
| XSCVDPSXDSs = 2311, | |
| XSCVDPSXWS = 2312, | |
| XSCVDPSXWSs = 2313, | |
| XSCVDPUXDS = 2314, | |
| XSCVDPUXDSs = 2315, | |
| XSCVDPUXWS = 2316, | |
| XSCVDPUXWSs = 2317, | |
| XSCVHPDP = 2318, | |
| XSCVQPDP = 2319, | |
| XSCVQPDPO = 2320, | |
| XSCVQPSDZ = 2321, | |
| XSCVQPSQZ = 2322, | |
| XSCVQPSWZ = 2323, | |
| XSCVQPUDZ = 2324, | |
| XSCVQPUQZ = 2325, | |
| XSCVQPUWZ = 2326, | |
| XSCVSDQP = 2327, | |
| XSCVSPDP = 2328, | |
| XSCVSPDPN = 2329, | |
| XSCVSQQP = 2330, | |
| XSCVSXDDP = 2331, | |
| XSCVSXDSP = 2332, | |
| XSCVUDQP = 2333, | |
| XSCVUQQP = 2334, | |
| XSCVUXDDP = 2335, | |
| XSCVUXDSP = 2336, | |
| XSDIVDP = 2337, | |
| XSDIVQP = 2338, | |
| XSDIVQPO = 2339, | |
| XSDIVSP = 2340, | |
| XSIEXPDP = 2341, | |
| XSIEXPQP = 2342, | |
| XSMADDADP = 2343, | |
| XSMADDASP = 2344, | |
| XSMADDMDP = 2345, | |
| XSMADDMSP = 2346, | |
| XSMADDQP = 2347, | |
| XSMADDQPO = 2348, | |
| XSMAXCDP = 2349, | |
| XSMAXCQP = 2350, | |
| XSMAXDP = 2351, | |
| XSMAXJDP = 2352, | |
| XSMINCDP = 2353, | |
| XSMINCQP = 2354, | |
| XSMINDP = 2355, | |
| XSMINJDP = 2356, | |
| XSMSUBADP = 2357, | |
| XSMSUBASP = 2358, | |
| XSMSUBMDP = 2359, | |
| XSMSUBMSP = 2360, | |
| XSMSUBQP = 2361, | |
| XSMSUBQPO = 2362, | |
| XSMULDP = 2363, | |
| XSMULQP = 2364, | |
| XSMULQPO = 2365, | |
| XSMULSP = 2366, | |
| XSNABSDP = 2367, | |
| XSNABSDPs = 2368, | |
| XSNABSQP = 2369, | |
| XSNEGDP = 2370, | |
| XSNEGQP = 2371, | |
| XSNMADDADP = 2372, | |
| XSNMADDASP = 2373, | |
| XSNMADDMDP = 2374, | |
| XSNMADDMSP = 2375, | |
| XSNMADDQP = 2376, | |
| XSNMADDQPO = 2377, | |
| XSNMSUBADP = 2378, | |
| XSNMSUBASP = 2379, | |
| XSNMSUBMDP = 2380, | |
| XSNMSUBMSP = 2381, | |
| XSNMSUBQP = 2382, | |
| XSNMSUBQPO = 2383, | |
| XSRDPI = 2384, | |
| XSRDPIC = 2385, | |
| XSRDPIM = 2386, | |
| XSRDPIP = 2387, | |
| XSRDPIZ = 2388, | |
| XSREDP = 2389, | |
| XSRESP = 2390, | |
| XSRQPI = 2391, | |
| XSRQPIX = 2392, | |
| XSRQPXP = 2393, | |
| XSRSP = 2394, | |
| XSRSQRTEDP = 2395, | |
| XSRSQRTESP = 2396, | |
| XSSQRTDP = 2397, | |
| XSSQRTQP = 2398, | |
| XSSQRTQPO = 2399, | |
| XSSQRTSP = 2400, | |
| XSSUBDP = 2401, | |
| XSSUBQP = 2402, | |
| XSSUBQPO = 2403, | |
| XSSUBSP = 2404, | |
| XSTDIVDP = 2405, | |
| XSTSQRTDP = 2406, | |
| XSTSTDCDP = 2407, | |
| XSTSTDCQP = 2408, | |
| XSTSTDCSP = 2409, | |
| XSXEXPDP = 2410, | |
| XSXEXPQP = 2411, | |
| XSXSIGDP = 2412, | |
| XSXSIGQP = 2413, | |
| XVABSDP = 2414, | |
| XVABSSP = 2415, | |
| XVADDDP = 2416, | |
| XVADDSP = 2417, | |
| XVBF16GER2 = 2418, | |
| XVBF16GER2NN = 2419, | |
| XVBF16GER2NP = 2420, | |
| XVBF16GER2PN = 2421, | |
| XVBF16GER2PP = 2422, | |
| XVBF16GER2W = 2423, | |
| XVBF16GER2WNN = 2424, | |
| XVBF16GER2WNP = 2425, | |
| XVBF16GER2WPN = 2426, | |
| XVBF16GER2WPP = 2427, | |
| XVCMPEQDP = 2428, | |
| XVCMPEQDP_rec = 2429, | |
| XVCMPEQSP = 2430, | |
| XVCMPEQSP_rec = 2431, | |
| XVCMPGEDP = 2432, | |
| XVCMPGEDP_rec = 2433, | |
| XVCMPGESP = 2434, | |
| XVCMPGESP_rec = 2435, | |
| XVCMPGTDP = 2436, | |
| XVCMPGTDP_rec = 2437, | |
| XVCMPGTSP = 2438, | |
| XVCMPGTSP_rec = 2439, | |
| XVCPSGNDP = 2440, | |
| XVCPSGNSP = 2441, | |
| XVCVBF16SPN = 2442, | |
| XVCVDPSP = 2443, | |
| XVCVDPSXDS = 2444, | |
| XVCVDPSXWS = 2445, | |
| XVCVDPUXDS = 2446, | |
| XVCVDPUXWS = 2447, | |
| XVCVHPSP = 2448, | |
| XVCVSPBF16 = 2449, | |
| XVCVSPDP = 2450, | |
| XVCVSPHP = 2451, | |
| XVCVSPSXDS = 2452, | |
| XVCVSPSXWS = 2453, | |
| XVCVSPUXDS = 2454, | |
| XVCVSPUXWS = 2455, | |
| XVCVSXDDP = 2456, | |
| XVCVSXDSP = 2457, | |
| XVCVSXWDP = 2458, | |
| XVCVSXWSP = 2459, | |
| XVCVUXDDP = 2460, | |
| XVCVUXDSP = 2461, | |
| XVCVUXWDP = 2462, | |
| XVCVUXWSP = 2463, | |
| XVDIVDP = 2464, | |
| XVDIVSP = 2465, | |
| XVF16GER2 = 2466, | |
| XVF16GER2NN = 2467, | |
| XVF16GER2NP = 2468, | |
| XVF16GER2PN = 2469, | |
| XVF16GER2PP = 2470, | |
| XVF16GER2W = 2471, | |
| XVF16GER2WNN = 2472, | |
| XVF16GER2WNP = 2473, | |
| XVF16GER2WPN = 2474, | |
| XVF16GER2WPP = 2475, | |
| XVF32GER = 2476, | |
| XVF32GERNN = 2477, | |
| XVF32GERNP = 2478, | |
| XVF32GERPN = 2479, | |
| XVF32GERPP = 2480, | |
| XVF32GERW = 2481, | |
| XVF32GERWNN = 2482, | |
| XVF32GERWNP = 2483, | |
| XVF32GERWPN = 2484, | |
| XVF32GERWPP = 2485, | |
| XVF64GER = 2486, | |
| XVF64GERNN = 2487, | |
| XVF64GERNP = 2488, | |
| XVF64GERPN = 2489, | |
| XVF64GERPP = 2490, | |
| XVF64GERW = 2491, | |
| XVF64GERWNN = 2492, | |
| XVF64GERWNP = 2493, | |
| XVF64GERWPN = 2494, | |
| XVF64GERWPP = 2495, | |
| XVI16GER2 = 2496, | |
| XVI16GER2PP = 2497, | |
| XVI16GER2S = 2498, | |
| XVI16GER2SPP = 2499, | |
| XVI16GER2SW = 2500, | |
| XVI16GER2SWPP = 2501, | |
| XVI16GER2W = 2502, | |
| XVI16GER2WPP = 2503, | |
| XVI4GER8 = 2504, | |
| XVI4GER8PP = 2505, | |
| XVI4GER8W = 2506, | |
| XVI4GER8WPP = 2507, | |
| XVI8GER4 = 2508, | |
| XVI8GER4PP = 2509, | |
| XVI8GER4SPP = 2510, | |
| XVI8GER4W = 2511, | |
| XVI8GER4WPP = 2512, | |
| XVI8GER4WSPP = 2513, | |
| XVIEXPDP = 2514, | |
| XVIEXPSP = 2515, | |
| XVMADDADP = 2516, | |
| XVMADDASP = 2517, | |
| XVMADDMDP = 2518, | |
| XVMADDMSP = 2519, | |
| XVMAXDP = 2520, | |
| XVMAXSP = 2521, | |
| XVMINDP = 2522, | |
| XVMINSP = 2523, | |
| XVMSUBADP = 2524, | |
| XVMSUBASP = 2525, | |
| XVMSUBMDP = 2526, | |
| XVMSUBMSP = 2527, | |
| XVMULDP = 2528, | |
| XVMULSP = 2529, | |
| XVNABSDP = 2530, | |
| XVNABSSP = 2531, | |
| XVNEGDP = 2532, | |
| XVNEGSP = 2533, | |
| XVNMADDADP = 2534, | |
| XVNMADDASP = 2535, | |
| XVNMADDMDP = 2536, | |
| XVNMADDMSP = 2537, | |
| XVNMSUBADP = 2538, | |
| XVNMSUBASP = 2539, | |
| XVNMSUBMDP = 2540, | |
| XVNMSUBMSP = 2541, | |
| XVRDPI = 2542, | |
| XVRDPIC = 2543, | |
| XVRDPIM = 2544, | |
| XVRDPIP = 2545, | |
| XVRDPIZ = 2546, | |
| XVREDP = 2547, | |
| XVRESP = 2548, | |
| XVRSPI = 2549, | |
| XVRSPIC = 2550, | |
| XVRSPIM = 2551, | |
| XVRSPIP = 2552, | |
| XVRSPIZ = 2553, | |
| XVRSQRTEDP = 2554, | |
| XVRSQRTESP = 2555, | |
| XVSQRTDP = 2556, | |
| XVSQRTSP = 2557, | |
| XVSUBDP = 2558, | |
| XVSUBSP = 2559, | |
| XVTDIVDP = 2560, | |
| XVTDIVSP = 2561, | |
| XVTLSBB = 2562, | |
| XVTSQRTDP = 2563, | |
| XVTSQRTSP = 2564, | |
| XVTSTDCDP = 2565, | |
| XVTSTDCSP = 2566, | |
| XVXEXPDP = 2567, | |
| XVXEXPSP = 2568, | |
| XVXSIGDP = 2569, | |
| XVXSIGSP = 2570, | |
| XXBLENDVB = 2571, | |
| XXBLENDVD = 2572, | |
| XXBLENDVH = 2573, | |
| XXBLENDVW = 2574, | |
| XXBRD = 2575, | |
| XXBRH = 2576, | |
| XXBRQ = 2577, | |
| XXBRW = 2578, | |
| XXEVAL = 2579, | |
| XXEXTRACTUW = 2580, | |
| XXGENPCVBM = 2581, | |
| XXGENPCVDM = 2582, | |
| XXGENPCVHM = 2583, | |
| XXGENPCVWM = 2584, | |
| XXINSERTW = 2585, | |
| XXLAND = 2586, | |
| XXLANDC = 2587, | |
| XXLEQV = 2588, | |
| XXLEQVOnes = 2589, | |
| XXLNAND = 2590, | |
| XXLNOR = 2591, | |
| XXLOR = 2592, | |
| XXLORC = 2593, | |
| XXLORf = 2594, | |
| XXLXOR = 2595, | |
| XXLXORdpz = 2596, | |
| XXLXORspz = 2597, | |
| XXLXORz = 2598, | |
| XXMFACC = 2599, | |
| XXMFACCW = 2600, | |
| XXMRGHW = 2601, | |
| XXMRGLW = 2602, | |
| XXMTACC = 2603, | |
| XXMTACCW = 2604, | |
| XXPERM = 2605, | |
| XXPERMDI = 2606, | |
| XXPERMDIs = 2607, | |
| XXPERMR = 2608, | |
| XXPERMX = 2609, | |
| XXSEL = 2610, | |
| XXSETACCZ = 2611, | |
| XXSETACCZW = 2612, | |
| XXSLDWI = 2613, | |
| XXSLDWIs = 2614, | |
| XXSPLTI32DX = 2615, | |
| XXSPLTIB = 2616, | |
| XXSPLTIDP = 2617, | |
| XXSPLTIW = 2618, | |
| XXSPLTW = 2619, | |
| XXSPLTWs = 2620, | |
| gBC = 2621, | |
| gBCA = 2622, | |
| gBCAat = 2623, | |
| gBCCTR = 2624, | |
| gBCCTRL = 2625, | |
| gBCL = 2626, | |
| gBCLA = 2627, | |
| gBCLAat = 2628, | |
| gBCLR = 2629, | |
| gBCLRL = 2630, | |
| gBCLat = 2631, | |
| gBCat = 2632, | |
| INSTRUCTION_LIST_END = 2633 | |
| }; | |
| } // end namespace PPC | |
| } // end namespace llvm | |
| #endif // GET_INSTRINFO_ENUM | |
| #ifdef GET_INSTRINFO_SCHED_ENUM | |
| #undef GET_INSTRINFO_SCHED_ENUM | |
| namespace llvm { | |
| namespace PPC { | |
| namespace Sched { | |
| enum { | |
| NoInstrModel = 0, | |
| IIC_LdStSync = 1, | |
| IIC_IntSimple = 2, | |
| IIC_IntGeneral = 3, | |
| IIC_BrB = 4, | |
| IIC_VecFP = 5, | |
| IIC_IntRotate = 6, | |
| IIC_IntCompare = 7, | |
| IIC_SprABORT = 8, | |
| IIC_LdStCOPY = 9, | |
| IIC_LdStPASTE = 10, | |
| IIC_BrCR = 11, | |
| IIC_LdStLD = 12, | |
| IIC_LdStDCBF = 13, | |
| IIC_LdStLoad = 14, | |
| IIC_IntDivD = 15, | |
| IIC_IntDivW = 16, | |
| IIC_FPDGeneral = 17, | |
| IIC_FPAddSub = 18, | |
| IIC_FPDivD = 19, | |
| IIC_FPSGeneral = 20, | |
| IIC_FPCompare = 21, | |
| IIC_FPGeneral = 22, | |
| IIC_VecGeneral = 23, | |
| IIC_VecComplex = 24, | |
| IIC_LdStStore = 25, | |
| IIC_IntRotateDI = 26, | |
| IIC_FPDivS = 27, | |
| IIC_FPFused = 28, | |
| IIC_FPSqrtD = 29, | |
| IIC_FPSqrtS = 30, | |
| IIC_LdStICBI = 31, | |
| IIC_IntISEL = 32, | |
| IIC_SprISYNC = 33, | |
| IIC_LdStLWARX = 34, | |
| IIC_LdStLoadUpd = 35, | |
| IIC_LdStLoadUpdX = 36, | |
| IIC_LdStLDARX = 37, | |
| IIC_LdStLDU = 38, | |
| IIC_LdStLDUX = 39, | |
| IIC_LdStLFD = 40, | |
| IIC_LdStLFDU = 41, | |
| IIC_LdStLFDUX = 42, | |
| IIC_LdStLHA = 43, | |
| IIC_LdStLHAU = 44, | |
| IIC_LdStLHAUX = 45, | |
| IIC_LdStLMW = 46, | |
| IIC_LdStLQ = 47, | |
| IIC_LdStLQARX = 48, | |
| IIC_LdStLWA = 49, | |
| IIC_IntMulHD = 50, | |
| IIC_BrMCR = 51, | |
| IIC_BrMCRX = 52, | |
| IIC_SprMFCR = 53, | |
| IIC_SprMFSPR = 54, | |
| IIC_IntMFFS = 55, | |
| IIC_SprMFMSR = 56, | |
| IIC_SprMFCRF = 57, | |
| IIC_SprMFPMR = 58, | |
| IIC_SprMFSR = 59, | |
| IIC_SprMFTB = 60, | |
| IIC_SprMSGSYNC = 61, | |
| IIC_SprMTSPR = 62, | |
| IIC_IntMTFSB0 = 63, | |
| IIC_SprMTMSR = 64, | |
| IIC_SprMTMSRD = 65, | |
| IIC_SprMTPMR = 66, | |
| IIC_SprMTSR = 67, | |
| IIC_IntMulHW = 68, | |
| IIC_IntMulHWU = 69, | |
| IIC_IntMulLI = 70, | |
| IIC_SprRFI = 71, | |
| IIC_IntRFID = 72, | |
| IIC_IntRotateD = 73, | |
| IIC_SprSLBFEE = 74, | |
| IIC_SprSLBIA = 75, | |
| IIC_SprSLBIE = 76, | |
| IIC_SprSLBIEG = 77, | |
| IIC_SprSLBMFEE = 78, | |
| IIC_SprSLBMFEV = 79, | |
| IIC_SprSLBMTE = 80, | |
| IIC_SprSLBSYNC = 81, | |
| IIC_IntShift = 82, | |
| IIC_LdStSTWCX = 83, | |
| IIC_LdStSTU = 84, | |
| IIC_LdStSTUX = 85, | |
| IIC_LdStSTD = 86, | |
| IIC_LdStSTDCX = 87, | |
| IIC_LdStSTFD = 88, | |
| IIC_LdStSTFDU = 89, | |
| IIC_SprSTOP = 90, | |
| IIC_LdStSTQ = 91, | |
| IIC_LdStSTQCX = 92, | |
| IIC_IntTrapD = 93, | |
| IIC_SprTLBIA = 94, | |
| IIC_SprTLBIE = 95, | |
| IIC_SprTLBIEL = 96, | |
| IIC_SprTLBSYNC = 97, | |
| IIC_IntTrapW = 98, | |
| IIC_VecFPCompare = 99, | |
| IIC_VecPerm = 100, | |
| VADDUBM_VADDUDM_VADDUHM_VADDUWM_VEXTSB2D_VEXTSB2Ds_VEXTSB2W_VEXTSB2Ws_VEXTSH2D_VEXTSH2Ds_VEXTSH2W_VEXTSH2Ws_VEXTSW2D_VEXTSW2Ds_VSLD_VSRD_VSUBUBM_VSUBUDM_VSUBUHM_VSUBUWM_VPOPCNTB_VPOPCNTH_VSRAD_MTVSRDD_VEQV_VNAND_VNEGD_VNEGW_VORC_XXLAND_XXLANDC_XXLEQV_XXLEQVOnes_XXLNAND_XXLNOR_XXLOR_XXLORf_XXLORC_XXLXOR_XXLXORdpz_XXLXORspz_XXLXORz = 101, | |
| VAND_VANDC_V_SET0_V_SET0B_V_SET0H_VSLB_VSLH_VSLW_VSRB_VSRH_VSRW_VRLB_VRLD_VRLH_VRLW_VSRAB_VSRAH_VSRAW_XVABSDP_XVABSSP_XVNABSDP_XVNABSSP_XVCPSGNDP_XVCPSGNSP_XVIEXPDP_XVIEXPSP_XVXEXPDP_XVXEXPSP_VRLDMI_VRLDNM_VRLWMI_VRLWNM_VMRGEW_VMRGOW_VNOR_VOR_VSEL_VXOR_XVNEGDP_XVNEGSP_XSABSQP_XSCPSGNQP_XSIEXPQP_XSNABSQP_XSNEGQP_XSXEXPQP = 102, | |
| XXSEL = 103, | |
| TABORTDC_TABORTDCI_TABORTWC_TABORTWCI = 104, | |
| MTFSB0_MTFSB1 = 105, | |
| MFFSCDRN_MFFSCDRNI_MFFSCRN_MFFSCRNI = 106, | |
| CMPRB_CMPRB8_CMPEQB = 107, | |
| TD_TDI = 108, | |
| TW_TWI = 109, | |
| FCMPOD_FCMPOS_FCMPUD_FCMPUS_FTDIV_FTSQRT = 110, | |
| XSTSTDCDP_XSTSTDCSP = 111, | |
| XSMAXCDP_XSMAXDP_XSMAXJDP_XSMINCDP_XSMINDP_XSMINJDP_XSXSIGDP_XSCVSPDPN = 112, | |
| XSCMPEQDP_XSCMPEXPDP_XSCMPGEDP_XSCMPGTDP_XSCMPODP_XSCMPUDP_XSTDIVDP_XSTSQRTDP = 113, | |
| CNTLZD_CNTLZD_rec_CNTLZW_CNTLZW8_CNTLZW8_rec_CNTLZW_rec_CNTTZD_CNTTZD_rec_CNTTZW_CNTTZW8_CNTTZW8_rec_CNTTZW_rec_POPCNTD_POPCNTW_CMPB_CMPB8_SETB_SETB8_BPERMD = 114, | |
| SLD_SRD_SRAD = 115, | |
| SRADI_EXTSWSLI_32_64_EXTSWSLI_SRADI_32_RLDIC = 116, | |
| MFVRD_MFVSRD_MTVRD_MTVSRD_MTVRWA_MTVRWZ_MTVSRWA_MTVSRWZ_MFVSRWZ_MFVRWZ = 117, | |
| CMPLW_CMPLWI_CMPW_CMPWI_CMPD_CMPDI_CMPLD_CMPLDI = 118, | |
| SUBFC_SUBFC8_SUBFC8O_SUBFCO_SUBFIC_SUBFIC8_ANDI8_rec_ANDIS8_rec_ANDIS_rec_ANDI_rec_ADDC_ADDC8_ADDC8O_ADDCO_ADDIC_ADDIC8_ADDIC_rec_ADDE_ADDE8_ADDE8O_ADDE8O_rec_ADDE8_rec_ADDEO_ADDEO_rec_ADDE_rec_ADDME_ADDME8_ADDME8O_ADDME8O_rec_ADDME8_rec_ADDMEO_ADDMEO_rec_ADDME_rec_ADDZE_ADDZE8_ADDZE8O_ADDZE8O_rec_ADDZE8_rec_ADDZEO_ADDZEO_rec_ADDZE_rec_SUBF_SUBF8_SUBF8O_SUBF8O_rec_SUBF8_rec_SUBFE_SUBFE8_SUBFE8O_SUBFE8O_rec_SUBFE8_rec_SUBFEO_SUBFEO_rec_SUBFE_rec_SUBFME_SUBFME8_SUBFME8O_SUBFME8O_rec_SUBFME8_rec_SUBFMEO_SUBFMEO_rec_SUBFME_rec_SUBFO_SUBFO_rec_SUBFZE_SUBFZE8_SUBFZE8O_SUBFZE8O_rec_SUBFZE8_rec_SUBFZEO_SUBFZEO_rec_SUBFZE_rec_SUBF_rec_POPCNTB_POPCNTB8_LA_LA8 = 119, | |
| ADD4_ADD4O_ADD4O_rec_ADD4_rec_ADD8_ADD8O_ADD8O_rec_ADD8_rec_NEG_NEG8_NEG8O_NEG8O_rec_NEG8_rec_NEGO_NEGO_rec_NEG_rec_ADDI_ADDI8_ADDIS_ADDIS8_LI_LI8_LIS_LIS8_OR_OR8_OR8_rec_ORI_ORI8_ORIS_ORIS8_OR_rec_XOR_XOR8_XOR8_rec_XORI_XORI8_XORIS_XORIS8_XOR_rec_NAND_NAND8_NAND8_rec_NAND_rec_AND_AND8_AND8_rec_ANDC_ANDC8_ANDC8_rec_ANDC_rec_AND_rec_NOR_NOR8_NOR8_rec_NOR_rec_ORC_ORC8_ORC8_rec_ORC_rec_EQV_EQV8_EQV8_rec_EQV_rec_EXTSB_EXTSB8_EXTSB8_32_64_EXTSB8_rec_EXTSB_rec_EXTSH_EXTSH8_EXTSH8_32_64_EXTSH8_rec_EXTSH_rec_EXTSW_EXTSW_32_EXTSW_32_64_EXTSW_32_64_rec_EXTSW_rec_ADD4TLS_ADD8TLS_ADD8TLS__NOP = 120, | |
| ADDIStocHA_ADDIStocHA8_ADDItocL_COPY = 121, | |
| MCRF = 122, | |
| MCRXRX = 123, | |
| XSNABSDP_XSNABSDPs_XSXEXPDP_XSABSDP_XSNEGDP_XSCPSGNDP = 124, | |
| RFEBB = 125, | |
| TBEGIN_TRECHKPT = 126, | |
| WAIT = 127, | |
| RLDCL_RLDCR = 128, | |
| RLWIMI_RLWIMI8 = 129, | |
| RLDICL_RLDICL_32_RLDICL_32_64_RLDICR_RLDICR_32_RLDIMI = 130, | |
| MFOCRF_MFOCRF8 = 131, | |
| MTOCRF_MTOCRF8 = 132, | |
| CR6SET_CR6UNSET_CRSET_CRUNSET_CRAND_CRANDC_CRNAND_CRNOR_CROR_CRORC_CREQV_CRNOT_CRXOR = 133, | |
| SLW_SLW8_SRW_SRW8_RLWINM_RLWINM8_RLWNM_RLWNM8 = 134, | |
| FABSD_FABSS_FNABSD_FNABSS_FNEGD_FNEGS_FCPSGND_FCPSGNS_FMR = 135, | |
| SRAW_SRAWI = 136, | |
| ISEL_ISEL8 = 137, | |
| XSIEXPDP = 138, | |
| TRECLAIM_TSR_TABORT = 139, | |
| MFVSCR = 140, | |
| MTVSCR = 141, | |
| VCMPNEZB_VCMPNEZH_VCMPNEZW_VCMPEQUB_VCMPEQUD_VCMPEQUH_VCMPEQUW_VCMPNEB_VCMPNEH_VCMPNEW_VCMPEQFP_VCMPEQFP_rec_VCMPGEFP_VCMPGEFP_rec_VCMPGTFP_VCMPGTFP_rec_VCMPBFP_VCMPBFP_rec_VCMPGTSB_VCMPGTSB_rec_VCMPGTSD_VCMPGTSD_rec_VCMPGTSH_VCMPGTSH_rec_VCMPGTSW_VCMPGTSW_rec_VCMPGTUB_VCMPGTUB_rec_VCMPGTUD_VCMPGTUD_rec_VCMPGTUH_VCMPGTUH_rec_VCMPGTUW_VCMPGTUW_rec_VCMPNEB_rec_VCMPNEH_rec_VCMPNEW_rec_VCMPNEZB_rec_VCMPNEZH_rec_VCMPNEZW_rec_VCMPEQUB_rec_VCMPEQUD_rec_VCMPEQUH_rec_VCMPEQUW_rec_XVCMPEQDP_XVCMPEQDP_rec_XVCMPEQSP_XVCMPEQSP_rec_XVCMPGEDP_XVCMPGEDP_rec_XVCMPGESP_XVCMPGESP_rec_XVCMPGTDP_XVCMPGTDP_rec_XVCMPGTSP_XVCMPGTSP_rec = 142, | |
| VABSDUB_VABSDUH_VABSDUW_VCLZB_VCLZD_VCLZH_VCLZW_VCTZB_VCTZD_VCTZH_VCTZW_VPOPCNTW_VPOPCNTD_VPRTYBD_VPRTYBW = 143, | |
| VADDUBS_VADDUHS_VADDUWS_VAVGSB_VAVGSH_VAVGSW_VAVGUB_VAVGUH_VAVGUW_VADDSBS_VADDSHS_VADDSWS_VMAXFP_VMINFP_VMAXSB_VMAXSD_VMAXSH_VMAXSW_VMAXUB_VMAXUD_VMAXUH_VMAXUW_VMINSB_VMINSD_VMINSH_VMINSW_VMINUB_VMINUD_VMINUH_VMINUW_VBPERMD_VADDCUW_VSHASIGMAD_VSHASIGMAW_VSUBSBS_VSUBSHS_VSUBSWS_VSUBUBS_VSUBUHS_VSUBUWS_VSUBCUW_XVMAXDP_XVMAXSP_XVMINDP_XVMINSP_XVTSTDCDP_XVTSTDCSP_XVXSIGDP_XVXSIGSP = 144, | |
| XVTDIVDP_XVTDIVSP_XVTSQRTDP_XVTSQRTSP = 145, | |
| VADDFP_VCTSXS_VCTSXS_0_VCTUXS_VCTUXS_0_VEXPTEFP_VLOGEFP_VMADDFP_VMHADDSHS_VNMSUBFP_VREFP_VRFIM_VRFIN_VRFIP_VRFIZ_VRSQRTEFP_XVADDDP_XVADDSP_XVCVDPSP_XVCVDPSXDS_XVCVDPSXWS_XVCVDPUXDS_XVCVDPUXWS_XVCVHPSP_XVCVSPDP_XVCVSPHP_XVCVSPSXDS_XVCVSPSXWS_XVCVSPUXDS_XVCVSPUXWS_XVCVSXDDP_XVCVSXDSP_XVCVSXWDP_XVCVSXWSP_XVCVUXDDP_XVCVUXDSP_XVCVUXWDP_XVCVUXWSP_XVMADDADP_XVMADDASP_XVMADDMDP_XVMADDMSP_XVMSUBADP_XVMSUBASP_XVMSUBMDP_XVMSUBMSP_XVMULDP_XVMULSP_XVNMADDADP_XVNMADDASP_XVNMADDMDP_XVNMADDMSP_XVNMSUBADP_XVNMSUBASP_XVNMSUBMDP_XVNMSUBMSP_XVRDPI_XVRDPIC_XVRDPIM_XVRDPIP_XVRDPIZ_XVREDP_XVRESP_XVRSPI_XVRSPIC_XVRSPIM_XVRSPIP_XVRSPIZ_XVRSQRTEDP_XVRSQRTESP_XVSUBDP_XVSUBSP_VCFSX_VCFSX_0_VCFUX_VCFUX_0_VMHRADDSHS_VMLADDUHM_VMSUMMBM_VMSUMSHM_VMSUMSHS_VMSUMUBM_VMSUMUHM_VMSUMUDM_VMSUMUHS_VMULESB_VMULESH_VMULESW_VMULEUB_VMULEUH_VMULEUW_VMULOSB_VMULOSH_VMULOSW_VMULOUB_VMULOUH_VMULOUW_VSUM2SWS_VSUM4SBS_VSUM4SHS_VSUM4UBS_VSUMSWS = 146, | |
| VSUBFP_VMULUWM = 147, | |
| MADDHD_MADDHDU_MADDLD_MADDLD8_MULLD_MULLDO = 148, | |
| MULHD_MULHW_MULLW_MULLWO = 149, | |
| MULHDU_MULHWU = 150, | |
| MULLI_MULLI8 = 151, | |
| FRSP_FRIMD_FRIMS_FRIND_FRINS_FRIPD_FRIPS_FRIZD_FRIZS_FRE_FRES_FADDS_FMSUBS_FMADDS_FSUBS_FCFID_FCFIDS_FCFIDU_FCFIDUS_FCTID_FCTIDU_FCTIDUZ_FCTIDZ_FCTIW_FCTIWU_FCTIWUZ_FCTIWZ_FRSQRTE_FRSQRTES_FNMADDS_FNMSUBS_FSELD_FSELS_FMULS = 152, | |
| FADD_FSUB = 153, | |
| FMSUB_FMADD_FNMADD_FNMSUB_FMUL = 154, | |
| XSMADDADP_XSMADDASP_XSMADDMDP_XSMADDMSP_XSMSUBADP_XSMSUBASP_XSMSUBMDP_XSMSUBMSP_XSMULDP_XSMULSP_XSNMADDADP_XSNMADDASP_XSNMADDMDP_XSNMADDMSP_XSNMSUBADP_XSNMSUBASP_XSNMSUBMDP_XSNMSUBMSP = 155, | |
| FSELD_rec_FSELS_rec = 156, | |
| MULHDU_rec_MULHWU_rec = 157, | |
| MULHD_rec_MULHW_rec_MULLWO_rec_MULLW_rec = 158, | |
| MULLDO_rec_MULLD_rec = 159, | |
| FRIMD_rec_FRIMS_rec_FRIND_rec_FRINS_rec_FRIPD_rec_FRIPS_rec_FRIZD_rec_FRIZS_rec_FRES_rec_FRE_rec_FADDS_rec_FSUBS_rec_FMSUBS_rec_FNMSUBS_rec_FMADDS_rec_FNMADDS_rec_FCFIDS_rec_FCFIDUS_rec_FCFIDU_rec_FCFID_rec_FCTIDUZ_rec_FCTIDU_rec_FCTIDZ_rec_FCTID_rec_FCTIWUZ_rec_FCTIWU_rec_FCTIWZ_rec_FCTIW_rec_FMULS_rec_FRSQRTES_rec_FRSQRTE_rec_FRSP_rec = 160, | |
| FADD_rec_FSUB_rec = 161, | |
| FMSUB_rec_FNMSUB_rec_FMADD_rec_FNMADD_rec_FMUL_rec = 162, | |
| XSADDDP_XSADDSP_XSCVDPHP_XSCVDPSP_XSCVDPSXDS_XSCVDPSXDSs_XSCVDPSXWS_XSCVDPUXDS_XSCVDPUXDSs_XSCVDPUXWS_XSCVDPSXWSs_XSCVDPUXWSs_XSCVHPDP_XSCVSPDP_XSCVSXDDP_XSCVSXDSP_XSCVUXDDP_XSCVUXDSP_XSRDPI_XSRDPIC_XSRDPIM_XSRDPIP_XSRDPIZ_XSREDP_XSRESP_XSRSQRTEDP_XSRSQRTESP_XSSUBDP_XSSUBSP_XSCVDPSPN_XSRSP = 163, | |
| LVSL_LVSR = 164, | |
| VSPLTISB_VSPLTISH_VSPLTISW_VSPLTB_VSPLTBs_VSPLTH_VSPLTHs_VSPLTW_XXMRGHW_XXMRGLW_XXPERM_XXPERMR_XXSLDWI_XXSLDWIs_XXSPLTIB_XXSPLTW_XXSPLTWs_XXPERMDI_XXPERMDIs = 165, | |
| V_SETALLONES_V_SETALLONESB_V_SETALLONESH_VBPERMQ_VGBBD_VMRGHB_VMRGHH_VMRGHW_VMRGLB_VMRGLH_VMRGLW_VPERM_VPERMR_VPERMXOR_VPKPX_VPKSDSS_VPKSDUS_VPKSHSS_VPKSHUS_VPKSWSS_VPKSWUS_VPKUDUM_VPKUDUS_VPKUHUM_VPKUHUS_VPKUWUM_VPKUWUS_VSL_VSLDOI_VSLO_VSLV_VSR_VSRO_VSRV_VUPKHPX_VUPKHSB_VUPKHSH_VUPKHSW_VUPKLPX_VUPKLSB_VUPKLSH_VUPKLSW_XXBRD_XXBRH_XXBRQ_XXBRW_XXEXTRACTUW_XXINSERTW_VADDCUQ_VADDECUQ_VADDEUQM_VMUL10CUQ_VMUL10ECUQ_VMUL10EUQ_VMUL10UQ_VSUBCUQ_VSUBECUQ_VSUBEUQM_XSTSTDCQP_XSXSIGQP_BCDCFN_rec_BCDCFZ_rec_BCDCPSGN_rec_BCDCTN_rec_BCDCTZ_rec_BCDSETSGN_rec_BCDS_rec_BCDTRUNC_rec_BCDUS_rec_BCDUTRUNC_rec_BCDADD_rec_BCDSUB_rec = 166, | |
| VEXTRACTUB_VEXTRACTUH_VEXTRACTUW_VINSERTB_VINSERTD_VINSERTH_VINSERTW_MFVSRLD_MTVSRWS_VCLZLSBB_VCTZLSBB_VEXTRACTD_VEXTUBLX_VEXTUBRX_VEXTUHLX_VEXTUHRX_VEXTUWLX_VEXTUWRX_VPRTYBQ_VADDUQM_VSUBUQM = 167, | |
| XSCMPEXPQP_XSCMPOQP_XSCMPUQP = 168, | |
| BCDSR_rec_XSADDQP_XSADDQPO_XSCVDPQP_XSCVQPDP_XSCVQPDPO_XSCVQPSDZ_XSCVQPSWZ_XSCVQPUDZ_XSCVQPUWZ_XSCVSDQP_XSCVUDQP_XSRQPI_XSRQPIX_XSRQPXP_XSSUBQP_XSSUBQPO = 169, | |
| BCDCTSQ_rec = 170, | |
| XSMADDQP_XSMADDQPO_XSMSUBQP_XSMSUBQPO_XSMULQP_XSMULQPO_XSNMADDQP_XSNMADDQPO_XSNMSUBQP_XSNMSUBQPO = 171, | |
| BCDCFSQ_rec = 172, | |
| XSDIVQP_XSDIVQPO = 173, | |
| XSSQRTQP_XSSQRTQPO = 174, | |
| LXVL_LXVLL = 175, | |
| LVEBX_LVEHX_LVEWX_LVX_LVXL = 176, | |
| LXSIBZX_LXSIHZX_LXSDX_LXVB16X_LXVD2X_LXVWSX_LXSIWZX_LXV_LXVX_LXSD = 177, | |
| DFLOADf64_XFLOADf64_LIWZX = 178, | |
| DCBF_DCBFEP_DCBST_DCBSTEP_DCBT_DCBTEP_DCBZ_DCBZEP_DCBZL_DCBZLEP_DCBTST_DCBTSTEP = 179, | |
| CP_COPY_CP_COPY8 = 180, | |
| ICBI_ICBIEP = 181, | |
| ICBT_ICBTLS_LBZ_LBZ8_LBZCIX_LBZX_LBZX8_LBZXTLS_LBZXTLS__LBZXTLS_32_LDBRX_LDCIX_LHBRX_LHBRX8_LHZ_LHZ8_LHZCIX_LHZX_LHZX8_LHZXTLS_LHZXTLS__LHZXTLS_32_LWBRX_LWBRX8_LWZ_LWZ8_LWZCIX_LWZX_LWZX8_LWZXTLS_LWZXTLS__LWZXTLS_32_EnforceIEIO_LSWI = 182, | |
| LBARX_LBARXL_LHARX_LHARXL_LWARX_LWARXL = 183, | |
| LD_LDX_LDXTLS_LDXTLS__DARN = 184, | |
| LDARX_LDARXL = 185, | |
| CP_ABORT = 186, | |
| ISYNC = 187, | |
| MSGSYNC = 188, | |
| TLBSYNC = 189, | |
| SYNC = 190, | |
| LMW = 191, | |
| LFIWZX_LFDX_LFD = 192, | |
| SLBIA = 193, | |
| SLBIE = 194, | |
| SLBMFEE = 195, | |
| SLBMFEV = 196, | |
| SLBMTE = 197, | |
| TLBIEL = 198, | |
| LHZU_LHZU8_LWZU_LWZU8 = 199, | |
| LHZUX_LHZUX8_LWZUX_LWZUX8 = 200, | |
| TEND = 201, | |
| STBCX_STHCX_STWCX = 202, | |
| STDCX = 203, | |
| LHA_LHA8_LHAX_LHAX8_LWAX_LWAX_32 = 204, | |
| CP_PASTE8_rec_CP_PASTE_rec = 205, | |
| LWA_LWA_32 = 206, | |
| TCHECK = 207, | |
| LFIWAX = 208, | |
| LXSIWAX = 209, | |
| LIWAX = 210, | |
| LFSX_LFS = 211, | |
| LXSSP_LXSSPX = 212, | |
| XFLOADf32_DFLOADf32 = 213, | |
| LHAU_LHAU8 = 214, | |
| LHAUX_LHAUX8_LWAUX = 215, | |
| LXVH8X_LXVDSX_LXVW4X = 216, | |
| STFD_STFDX_STFIWX_STFS_STFSX_STXSD_STXSDX_STXSIBX_STXSIBXv_STXSIHX_STXSIHXv_STXSIWX_STXSSP_STXSSPX = 217, | |
| STW_STW8_STDBRX_STHBRX_STWBRX_STB_STB8_STH_STH8_STBX_STBX8_STBXTLS_STBXTLS__STBXTLS_32_STHX_STHX8_STHXTLS_STHXTLS__STHXTLS_32_STWX_STWX8_STWXTLS_STWXTLS__STWXTLS_32 = 218, | |
| DFSTOREf32_DFSTOREf64_XFSTOREf32_XFSTOREf64_STIWX = 219, | |
| STD_STDX_STDXTLS_STDXTLS_ = 220, | |
| STBCIX_STDCIX_STHCIX_STWCIX_STSWI = 221, | |
| SLBIEG = 222, | |
| STMW = 223, | |
| TLBIE = 224, | |
| STVEBX_STVEHX_STVEWX_STVX_STVXL = 225, | |
| STXV_STXVB16X_STXVD2X_STXVH8X_STXVW4X_STXVX = 226, | |
| STXVL_STXVLL = 227, | |
| MTCTR_MTCTR8_MTCTR8loop_MTCTRloop_MTLR_MTLR8 = 228, | |
| MFVRSAVE_MFVRSAVEv_MTVRSAVE_MTVRSAVEv = 229, | |
| MFPMR = 230, | |
| MTPMR = 231, | |
| MFTB_MFTB8 = 232, | |
| MFCTR_MFCTR8_MFLR_MFLR8_MFSPR_MFSPR8_MFUDSCR = 233, | |
| MFMSR = 234, | |
| MTMSR = 235, | |
| MTMSRD = 236, | |
| MTUDSCR_MTSPR_MTSPR8 = 237, | |
| DIVW_DIVWO_DIVWU_DIVWUO_MODSW = 238, | |
| DIVWE_DIVWEO_DIVWEU_DIVWEUO_MODSD_MODUD_MODUW = 239, | |
| DIVD_DIVDO_DIVDU_DIVDUO = 240, | |
| DIVDE_DIVDEO_DIVDEU_DIVDEUO = 241, | |
| DIVWO_rec_DIVWUO_rec_DIVWU_rec_DIVW_rec = 242, | |
| DIVD_rec_DIVDO_rec_DIVDU_rec_DIVDUO_rec = 243, | |
| DIVWE_rec_DIVWEO_rec_DIVWEU_rec_DIVWEUO_rec = 244, | |
| DIVDE_rec_DIVDEO_rec_DIVDEU_rec_DIVDEUO_rec = 245, | |
| MTCRF_MTCRF8 = 246, | |
| ADDC8O_rec_ADDC8_rec_ADDCO_rec_ADDC_rec_SUBFC8O_rec_SUBFC8_rec_SUBFCO_rec_SUBFC_rec = 247, | |
| FABSD_rec_FABSS_rec_FNABSD_rec_FNABSS_rec_FCPSGND_rec_FCPSGNS_rec_FNEGD_rec_FNEGS_rec_FMR_rec = 248, | |
| MCRFS = 249, | |
| MTFSF_MTFSF_rec_MTFSFI_MTFSFI_rec_MTFSFIb = 250, | |
| MTFSFb = 251, | |
| RLDCL_rec_RLDCR_rec = 252, | |
| RLDICL_rec_RLDICR_rec_RLDICL_32_rec_RLDIMI_rec = 253, | |
| RLWIMI8_rec_RLWIMI_rec = 254, | |
| RLWINM8_rec_RLWINM_rec_RLWNM8_rec_RLWNM_rec_SLW8_rec_SLW_rec_SRW8_rec_SRW_rec = 255, | |
| SRAWI_rec_SRAW_rec = 256, | |
| MFFS_MFFSCE_MFFSL_MFFS_rec = 257, | |
| MFCR_MFCR8 = 258, | |
| EXTSWSLI_32_64_rec_SRADI_rec_EXTSWSLI_rec_RLDIC_rec = 259, | |
| SRAD_rec_SLD_rec_SRD_rec = 260, | |
| FDIV = 261, | |
| FDIV_rec = 262, | |
| XSSQRTDP = 263, | |
| FSQRT = 264, | |
| XVSQRTDP = 265, | |
| XVSQRTSP = 266, | |
| FSQRT_rec = 267, | |
| XSSQRTSP = 268, | |
| FSQRTS = 269, | |
| FSQRTS_rec = 270, | |
| XSDIVDP = 271, | |
| FDIVS = 272, | |
| FDIVS_rec = 273, | |
| XSDIVSP = 274, | |
| XVDIVSP = 275, | |
| XVDIVDP = 276, | |
| LFSU = 277, | |
| LFSUX = 278, | |
| STFDU_STFDUX_STFSU_STFSUX = 279, | |
| STBU_STBU8_STDU_STHU_STHU8_STWU_STWU8 = 280, | |
| STBUX_STBUX8_STDUX_STHUX_STHUX8_STWUX_STWUX8 = 281, | |
| LBZU_LBZU8 = 282, | |
| LBZUX_LBZUX8 = 283, | |
| LDU = 284, | |
| LDUX = 285, | |
| LFDU = 286, | |
| LFDUX = 287, | |
| VPMSUMB_VPMSUMD_VPMSUMH_VPMSUMW_VCIPHER_VCIPHERLAST_VNCIPHER_VNCIPHERLAST_VSBOX = 288, | |
| BCCCTR_BCCCTR8_BCCCTRL_BCCCTRL8_BCCL_BCCLA_BCCLR_BCCLRL_BCCTR_BCCTR8_BCCTR8n_BCCTRL_BCCTRL8_BCCTRL8n_BCCTRLn_BCCTRn_BDNZ_BDNZ8_BDNZA_BDNZAm_BDNZAp_BDNZm_BDNZp_BDZ_BDZ8_BDZA_BDZAm_BDZAp_BDZm_BDZp_BDNZL_BDNZLA_BDNZLAm_BDNZLAp_BDNZLR_BDNZLR8_BDNZLRL_BDNZLRLm_BDNZLRLp_BDNZLRm_BDNZLRp_BDNZLm_BDNZLp_BDZL_BDZLA_BDZLAm_BDZLAp_BDZLR_BDZLR8_BDZLRL_BDZLRLm_BDZLRLp_BDZLRm_BDZLRp_BDZLm_BDZLp_BL_BL_NOP_BL_NOP_RM_BL_RM_BL_TLS_BL8_BL8_NOP_BL8_NOP_RM_BL8_NOP_TLS_BL8_RM_BL8_TLS_BL8_TLS__BLA_BLA8_BLA8_NOP_BLA8_NOP_RM_BLA8_RM_BLA_RM_BLR_BLR8_BLRL_TAILB_TAILB8_TAILBA_TAILBA8_TAILBCTR_TAILBCTR8_gBC_gBCA_gBCAat_gBCCTR_gBCCTRL_gBCL_gBCLA_gBCLAat_gBCLR_gBCLRL_gBCLat_gBCat_BCLR_BCLRL_BCLRLn_BCLRn_BCTR_BCTR8_BCTRL_BCTRL8_BCTRL8_RM_BCTRL_RM_B_BA_BC_BCC_BCCA_BCL_BCLalways_BCLn_BCTRL8_LDinto_toc_BCTRL_LWZinto_toc_BCTRL8_LDinto_toc_RM_BCTRL_LWZinto_toc_RM_BCn_CTRL_DEP = 289, | |
| ADDPCIS = 290, | |
| LDAT_LWAT = 291, | |
| STDAT_STWAT = 292, | |
| BRINC = 293, | |
| EVABS_EVEQV_EVNAND_EVNEG_EVADDIW_EVADDW_EVAND_EVANDC_EVCMPEQ_EVCMPGTS_EVCMPGTU_EVCMPLTS_EVCMPLTU_EVCNTLSW_EVCNTLZW_EVEXTSB_EVEXTSH_EVMERGEHI_EVMERGEHILO_EVMERGELO_EVMERGELOHI_EVNOR_EVOR_EVORC_EVXOR_EVRLW_EVRLWI_EVRNDW_EVSLW_EVSLWI_EVSPLATFI_EVSPLATI_EVSRWIS_EVSRWIU_EVSRWS_EVSRWU_EVSUBFW_EVSUBIFW = 294, | |
| EVMRA_EVADDSMIAAW_EVADDSSIAAW_EVADDUMIAAW_EVADDUSIAAW_EVDIVWS_EVDIVWU_EVMHEGSMFAA_EVMHEGSMFAN_EVMHEGSMIAA_EVMHEGSMIAN_EVMHEGUMIAA_EVMHEGUMIAN_EVMHESMF_EVMHESMFA_EVMHESMFAAW_EVMHESMFANW_EVMHESMI_EVMHESMIA_EVMHESMIAAW_EVMHESMIANW_EVMHESSF_EVMHESSFA_EVMHESSFAAW_EVMHESSFANW_EVMHESSIAAW_EVMHESSIANW_EVMHEUMI_EVMHEUMIA_EVMHEUMIAAW_EVMHEUMIANW_EVMHEUSIAAW_EVMHEUSIANW_EVMHOGSMFAA_EVMHOGSMFAN_EVMHOGSMIAA_EVMHOGSMIAN_EVMHOGUMIAA_EVMHOGUMIAN_EVMHOSMF_EVMHOSMFA_EVMHOSMFAAW_EVMHOSMFANW_EVMHOSMI_EVMHOSMIA_EVMHOSMIAAW_EVMHOSMIANW_EVMHOSSF_EVMHOSSFA_EVMHOSSFAAW_EVMHOSSFANW_EVMHOSSIAAW_EVMHOSSIANW_EVMHOUMI_EVMHOUMIA_EVMHOUMIAAW_EVMHOUMIANW_EVMHOUSIAAW_EVMHOUSIANW_EVMWHSMF_EVMWHSMFA_EVMWHSMI_EVMWHSMIA_EVMWHSSF_EVMWHSSFA_EVMWHUMI_EVMWHUMIA_EVMWLSMIAAW_EVMWLSMIANW_EVMWLSSIAAW_EVMWLSSIANW_EVMWLUMI_EVMWLUMIA_EVMWLUMIAAW_EVMWLUMIANW_EVMWLUSIAAW_EVMWLUSIANW_EVMWSMF_EVMWSMFA_EVMWSMFAA_EVMWSMFAN_EVMWSMI_EVMWSMIA_EVMWSMIAA_EVMWSMIAN_EVMWSSF_EVMWSSFA_EVMWSSFAA_EVMWSSFAN_EVMWUMI_EVMWUMIA_EVMWUMIAA_EVMWUMIAN_EVSUBFSMIAAW_EVSUBFSSIAAW_EVSUBFUMIAAW_EVSUBFUSIAAW = 295, | |
| EVLDD_EVLDDX_EVLDH_EVLDHX_EVLDW_EVLDWX_EVLHHESPLAT_EVLHHESPLATX_EVLHHOSSPLAT_EVLHHOSSPLATX_EVLHHOUSPLAT_EVLHHOUSPLATX_EVLWHE_EVLWHEX_EVLWHOS_EVLWHOSX_EVLWHOU_EVLWHOUX_EVLWHSPLAT_EVLWHSPLATX_EVLWWSPLAT_EVLWWSPLATX = 296, | |
| EVSTDD_EVSTDDX_EVSTDH_EVSTDHX_EVSTDW_EVSTDWX_EVSTWHE_EVSTWHEX_EVSTWHO_EVSTWHOX_EVSTWWE_EVSTWWEX_EVSTWWO_EVSTWWOX = 297, | |
| HRFID_ATTN_CLRBHRB_MFBHRBE_NAP_RFCI_RFDI_RFMCI_SC = 298, | |
| RFI = 299, | |
| RFID = 300, | |
| DSS_DSSALL_DST_DST64_DSTST_DSTST64_DSTSTT_DSTSTT64_DSTT_DSTT64_ICBLQ_LBEPX_LHEPX_LWEPX_TLBIVAX_TLBLD_TLBLI_TLBRE_TLBRE2_TLBSX_TLBSX2_TLBSX2D_TLBWE_TLBWE2_MBAR_TRAP_DCCCI_ICCCI = 301, | |
| ICBLC_STBEPX_STHEPX_STWEPX = 302, | |
| LFDEPX = 303, | |
| STFDEPX = 304, | |
| MFSR_MFSRIN = 305, | |
| MTSR_MTSRIN = 306, | |
| MFDCR = 307, | |
| MTDCR = 308, | |
| NOP_GT_PWR6_NOP_GT_PWR7 = 309, | |
| TLBIA = 310, | |
| WRTEE_WRTEEI = 311, | |
| HASHCHK_HASHCHK8_HASHCHKP_HASHCHKP8_HASHST_HASHST8_HASHSTP_HASHSTP8_ADDEX_ADDEX8 = 312, | |
| MSYNC = 313, | |
| SLBSYNC = 314, | |
| SLBFEE_rec = 315, | |
| STOP = 316, | |
| DCBA_DCBI = 317, | |
| FCFID_FCFIDS_FCFIDU_FCFIDUS_FCTID_FCTIDU_FCTIDUZ_FCTIDZ_FCTIW_FCTIWU_FCTIWUZ_FCTIWZ_FRE_FRES_FRIMD_FRIMS_FRIND_FRINS_FRIPD_FRIPS_FRIZD_FRIZS_FRSP_FRSQRTE_FRSQRTES = 318, | |
| VCFSX_VCFSX_0_VCFUX_VCFUX_0_VCTSXS_VCTSXS_0_VCTUXS_VCTUXS_0_VLOGEFP_VREFP_VRFIM_VRFIN_VRFIP_VRFIZ_VRSQRTEFP_XVCVDPSP_XVCVDPSXDS_XVCVDPSXWS_XVCVDPUXDS_XVCVDPUXWS_XVCVSPDP_XVCVSPHP_XVCVSPSXDS_XVCVSPSXWS_XVCVSPUXDS_XVCVSPUXWS_XVCVSXDDP_XVCVSXDSP_XVCVSXWDP_XVCVSXWSP_XVCVUXDDP_XVCVUXDSP_XVCVUXWDP_XVCVUXWSP_XVRDPI_XVRDPIC_XVRDPIM_XVRDPIP_XVRDPIZ_XVREDP_XVRESP_XVRSPI_XVRSPIC_XVRSPIM_XVRSPIP_XVRSPIZ_XVRSQRTEDP_XVRSQRTESP = 319, | |
| XSCVDPHP_XSCVDPSP_XSCVDPSPN_XSCVDPSXDS_XSCVDPSXDSs_XSCVDPSXWS_XSCVDPSXWSs_XSCVDPUXDS_XSCVDPUXDSs_XSCVDPUXWS_XSCVDPUXWSs_XSCVSPDP_XSCVSXDDP_XSCVSXDSP_XSCVUXDDP_XSCVUXDSP_XSRDPI_XSRDPIC_XSRDPIM_XSRDPIP_XSRDPIZ_XSREDP_XSRESP_XSRSP_XSRSQRTEDP_XSRSQRTESP = 320, | |
| XVCVSPBF16 = 321, | |
| FADDS_FMULS_FSUBS = 322, | |
| FMUL = 323, | |
| VADDFP_XVADDDP_XVADDSP_XVMULDP_XVMULSP_XVSUBDP_XVSUBSP = 324, | |
| VSUBFP = 325, | |
| XSADDDP_XSADDSP_XSSUBDP_XSSUBSP = 326, | |
| XSMULDP_XSMULSP = 327, | |
| VMADDFP_VNMSUBFP_XVMADDADP_XVMADDASP_XVMADDMDP_XVMADDMSP_XVMSUBADP_XVMSUBASP_XVMSUBMDP_XVMSUBMSP_XVNMADDADP_XVNMADDASP_XVNMADDMDP_XVNMADDMSP_XVNMSUBADP_XVNMSUBASP_XVNMSUBMDP_XVNMSUBMSP = 328, | |
| VEXPTEFP = 329, | |
| FADDS_rec_FMULS_rec_FSUBS_rec = 330, | |
| FMUL_rec = 331, | |
| FCFID_rec_FCFIDS_rec_FCFIDU_rec_FCFIDUS_rec_FCTID_rec_FCTIDU_rec_FCTIDUZ_rec_FCTIDZ_rec_FCTIW_rec_FCTIWU_rec_FCTIWUZ_rec_FCTIWZ_rec_FRE_rec_FRES_rec_FRIMD_rec_FRIMS_rec_FRIND_rec_FRINS_rec_FRIPD_rec_FRIPS_rec_FRIZD_rec_FRIZS_rec_FRSP_rec_FRSQRTE_rec_FRSQRTES_rec = 332, | |
| BCLR_BCLRn_BDNZLR_BDNZLR8_BDNZLRm_BDNZLRp_BDZLR_BDZLR8_BDZLRm_BDZLRp_gBCLR_BCLRL_BCLRLn_BDNZLRL_BDNZLRLm_BDNZLRLp_BDZLRL_BDZLRLm_BDZLRLp_gBCLRL_BL_BL8_BL8_NOP_BL8_NOP_RM_BL8_NOP_TLS_BL8_RM_BL8_TLS_BL8_TLS__BLR_BLR8_BLRL_BL_NOP_BL_NOP_RM_BL_RM_BL_TLS = 333, | |
| BL8_NOTOC_BL8_NOTOC_RM_BL8_NOTOC_TLS = 334, | |
| B_BCC_BCCA_BCCCTR_BCCCTR8_BCCCTRL_BCCCTRL8_BCCL_BCCLA_BCCLR_BCCLRL_CTRL_DEP_TAILB_TAILB8_BA_TAILBA_TAILBA8_BC_BCTR_BCTR8_BCTRL_BCTRL8_BCTRL8_LDinto_toc_BCTRL8_LDinto_toc_RM_BCTRL8_RM_BCTRL_LWZinto_toc_BCTRL_LWZinto_toc_RM_BCTRL_RM_BCn_BDNZ_BDNZ8_BDNZm_BDNZp_BDZ_BDZ8_BDZm_BDZp_TAILBCTR_TAILBCTR8_gBC_gBCat_BCL_BCLalways_BCLn_BDNZL_BDNZLm_BDNZLp_BDZL_BDZLm_BDZLp_gBCL_gBCLat_BLA_BLA8_BLA8_NOP_BLA8_NOP_RM_BLA8_RM_BLA_RM = 335, | |
| BCCTR_BCCTR8_BCCTR8n_BCCTRn_gBCCTR_BCCTRL_BCCTRL8_BCCTRL8n_BCCTRLn_gBCCTRL = 336, | |
| VSBOX = 337, | |
| CFUGED_CNTLZDM_CNTTZDM_PDEPD_PEXTD = 338, | |
| VCFUGED_VCLZDM_VCTZDM_VGNB_VPDEPD_VPEXTD = 339, | |
| XSCVDPQP_XSCVQPDP_XSCVQPDPO_XSCVQPSDZ_XSCVQPSWZ_XSCVQPUDZ_XSCVQPUWZ_XSCVSDQP_XSCVUDQP = 340, | |
| XSCVQPSQZ_XSCVQPUQZ_XSCVSQQP_XSCVUQQP = 341, | |
| XSADDQP_XSADDQPO_XSSUBQP_XSSUBQPO = 342, | |
| HASHST_HASHST8_HASHSTP_HASHSTP8 = 343, | |
| XSMULQP_XSMULQPO = 344, | |
| VDIVESQ_VDIVEUQ_VDIVSQ_VDIVUQ = 345, | |
| VMODSQ_VMODUQ = 346, | |
| DIVWE_DIVWEO_DIVWEU_DIVWEUO = 347, | |
| VDIVSD_VDIVUD = 348, | |
| VMODSD_VMODUD = 349, | |
| VDIVSW_VDIVUW = 350, | |
| VMODSW_VMODUW = 351, | |
| VDIVESD_VDIVEUD = 352, | |
| VDIVESW_VDIVEUW = 353, | |
| BCDCTN_rec_VMUL10CUQ_VMUL10UQ_XSXSIGQP = 354, | |
| BCDCFN_rec_BCDCFZ_rec_BCDCPSGN_rec_BCDCTZ_rec_BCDSETSGN_rec_BCDUS_rec_BCDUTRUNC_rec_VADDCUQ_VMUL10ECUQ_VMUL10EUQ_VSUBCUQ_XSTSTDCQP = 355, | |
| VADDUQM_VSUBUQM = 356, | |
| XSCMPEQQP_XSCMPGEQP_XSCMPGTQP_XSMAXCQP_XSMINCQP = 357, | |
| XXGENPCVBM = 358, | |
| BCDADD_rec_BCDS_rec_BCDSUB_rec_BCDTRUNC_rec_VADDECUQ_VADDEUQM_VSUBECUQ_VSUBEUQM = 359, | |
| TRAP = 360, | |
| TW = 361, | |
| CNTLZD_CNTLZD_rec_CNTLZW_CNTLZW8_CNTLZW8_rec_CNTLZW_rec_CNTTZD_CNTTZD_rec_CNTTZW_CNTTZW8_CNTTZW8_rec_CNTTZW_rec_POPCNTD_POPCNTW = 362, | |
| FTSQRT = 363, | |
| MTVSRBM_MTVSRBMI_MTVSRDM_MTVSRHM_MTVSRQM_MTVSRWM_VEXPANDBM_VEXPANDDM_VEXPANDHM_VEXPANDQM_VEXPANDWM_VEXTRACTBM_VEXTRACTDM_VEXTRACTHM_VEXTRACTQM_VEXTRACTWM_XVTLSBB = 364, | |
| POPCNTB_POPCNTB8 = 365, | |
| VCLZB_VCLZD_VCLZH_VCLZW_VCTZB_VCTZD_VCTZH_VCTZW_VPOPCNTD_VPOPCNTW_VPRTYBD_VPRTYBW = 366, | |
| VPOPCNTB_VPOPCNTH = 367, | |
| XSCVSPDPN = 368, | |
| XSTSQRTDP = 369, | |
| XVCVHPSP = 370, | |
| XVTSQRTDP_XVTSQRTSP = 371, | |
| CMPEQB = 372, | |
| EXTSWSLI_32_64_rec_EXTSWSLI_rec = 373, | |
| SLD_rec_SRD_rec = 374, | |
| SLW8_rec_SLW_rec_SRW8_rec_SRW_rec = 375, | |
| VADDCUW_VADDSBS_VADDSHS_VADDSWS_VADDUBS_VADDUHS_VADDUWS_VAVGSB_VAVGSH_VAVGSW_VAVGUB_VAVGUH_VAVGUW_VMAXFP_VMINFP_VSUBCUW_VSUBSBS_VSUBSHS_VSUBSWS_VSUBUBS_VSUBUHS_VSUBUWS_XVMAXDP_XVMAXSP_XVMINDP_XVMINSP_XVTSTDCDP_XVTSTDCSP = 376, | |
| VCMPBFP_VCMPBFP_rec_VCMPEQFP_VCMPEQFP_rec_VCMPEQUB_rec_VCMPEQUD_rec_VCMPEQUH_rec_VCMPEQUW_rec_VCMPGEFP_VCMPGEFP_rec_VCMPGTFP_VCMPGTFP_rec_VCMPGTSB_rec_VCMPGTSD_rec_VCMPGTSH_rec_VCMPGTSW_rec_VCMPGTUB_rec_VCMPGTUD_rec_VCMPGTUH_rec_VCMPGTUW_rec_VCMPNEB_rec_VCMPNEH_rec_VCMPNEW_rec_VCMPNEZB_rec_VCMPNEZH_rec_VCMPNEZW_rec_XVCMPEQDP_XVCMPEQDP_rec_XVCMPEQSP_XVCMPEQSP_rec_XVCMPGEDP_XVCMPGEDP_rec_XVCMPGESP_XVCMPGESP_rec_XVCMPGTDP_XVCMPGTDP_rec_XVCMPGTSP_XVCMPGTSP_rec = 377, | |
| VCMPEQUQ_VCMPEQUQ_rec_VCMPGTSQ_VCMPGTSQ_rec_VCMPGTUQ_VCMPGTUQ_rec = 378, | |
| VCMPSQ_VCMPUQ_VCNTMBB_VCNTMBD_VCNTMBH_VCNTMBW = 379, | |
| XSMAXCDP_XSMAXDP_XSMAXJDP_XSMINCDP_XSMINDP_XSMINJDP = 380, | |
| RLDIC_rec = 381, | |
| RLDICL_32_rec_RLDICL_rec_RLDICR_rec = 382, | |
| VSHASIGMAD_VSHASIGMAW = 383, | |
| VRLQ_VRLQNM_VSLQ_VSRAQ_VSRQ = 384, | |
| VRLQMI = 385, | |
| CR6SET_CREQV_CRSET = 386, | |
| DSS_DSSALL = 387, | |
| MFCTR_MFCTR8_MFLR_MFLR8 = 388, | |
| NOP_ORI_ORI8 = 389, | |
| VXOR_V_SET0_V_SET0B_V_SET0H = 390, | |
| XXLEQV_XXLEQVOnes_XXLXOR_XXLXORdpz_XXLXORspz_XXLXORz = 391, | |
| ADDI_ADDI8_LI_LI8_ADDIS_ADDIS8_LIS_LIS8_EXTSB_EXTSB8_EXTSB8_32_64_EXTSB8_rec_EXTSB_rec_EXTSH_EXTSH8_EXTSH8_32_64_EXTSH8_rec_EXTSH_rec_EXTSW_EXTSW_32_EXTSW_32_64_EXTSW_32_64_rec_EXTSW_rec_NEG_NEG8_NEG8_rec_NEG_rec_NEG8O_NEGO = 392, | |
| ADDIdtprelL32_ADDItlsldLADDR32_ADDISdtprelHA32 = 393, | |
| ADDItocL_ADDIStocHA_ADDIStocHA8 = 394, | |
| ADDME_ADDME8_ADDME8O_ADDMEO_ADDZE_ADDZE8_ADDZE8O_ADDZEO_SUBFME_SUBFME8_SUBFME8O_SUBFMEO_SUBFZE_SUBFZE8_SUBFZE8O_SUBFZEO = 395, | |
| FABSD_FABSS_FMR_FNABSD_FNABSS_FNEGD_FNEGS = 396, | |
| SETB_SETB8 = 397, | |
| SETBC_SETBC8_SETBCR_SETBCR8_SETNBC_SETNBC8_SETNBCR_SETNBCR8 = 398, | |
| VEXTSB2D_VEXTSB2Ds_VEXTSB2W_VEXTSB2Ws_VEXTSH2D_VEXTSH2Ds_VEXTSH2W_VEXTSH2Ws_VEXTSW2D_VEXTSW2Ds_VNEGD_VNEGW = 399, | |
| VEXTSD2Q = 400, | |
| XSABSDP_XSNABSDP_XSNABSDPs_XSNEGDP_XSXEXPDP = 401, | |
| XSABSQP_XSNABSQP_XSNEGQP_XSXEXPQP_XVABSDP_XVABSSP_XVNABSDP_XVNABSSP_XVNEGDP_XVNEGSP_XVXEXPDP_XVXEXPSP = 402, | |
| XVXSIGDP_XVXSIGSP = 403, | |
| ADD4_ADD4TLS_ADD8_ADD8TLS_ADD8TLS__ADD4_rec_ADD8_rec_ADD4O_ADD8O_AND_AND8_AND8_rec_AND_rec_ANDC_ANDC8_ANDC8_rec_ANDC_rec_EQV_EQV8_EQV8_rec_EQV_rec_NAND_NAND8_NAND8_rec_NAND_rec_NOR_NOR8_NOR8_rec_NOR_rec_OR_OR8_OR8_rec_OR_rec_ORC_ORC8_ORC8_rec_ORC_rec_ORIS_ORIS8_XOR_XOR8_XOR8_rec_XOR_rec_XORI_XORI8_XORIS_XORIS8 = 404, | |
| ADDE_ADDE8_ADDE8O_ADDEO_ADDIC_ADDIC8_ANDI8_rec_ANDI_rec_ANDIS8_rec_ANDIS_rec_SUBF_SUBF8_SUBF8_rec_SUBF_rec_SUBFE_SUBFE8_SUBFE8O_SUBFEO_SUBFIC_SUBFIC8_SUBF8O_SUBFO = 405, | |
| CMPB_CMPB8 = 406, | |
| CRAND_CRANDC_CRNAND_CRNOR_CROR_CRORC_CR6UNSET_CRUNSET_CRXOR = 407, | |
| EXTSWSLI_EXTSWSLI_32_64_SRADI_SRADI_32 = 408, | |
| SLW_SLW8_SRW_SRW8 = 409, | |
| VADDUBM_VADDUDM_VADDUHM_VADDUWM_VEQV_VNAND_VORC_VSLD_VSRAD_VSRD_VSUBUBM_VSUBUDM_VSUBUHM_VSUBUWM_XXLAND_XXLANDC_XXLNAND_XXLNOR_XXLOR_XXLORf_XXLORC = 410, | |
| VAND_VANDC_VMRGEW_VMRGOW_VNOR_VOR_VRLB_VRLD_VRLDNM_VRLH_VRLW_VRLWNM_VSLB_VSLH_VSLW_VSRAB_VSRAH_VSRAW_VSRB_VSRH_VSRW_XSCPSGNQP_XSIEXPQP_XVCPSGNDP_XVCPSGNSP_XVIEXPDP_XVIEXPSP = 411, | |
| VMAXSB_VMAXSD_VMAXSH_VMAXSW_VMAXUB_VMAXUD_VMAXUH_VMAXUW_VMINSB_VMINSD_VMINSH_VMINSW_VMINUB_VMINUD_VMINUH_VMINUW = 412, | |
| ADDEX_ADDEX8 = 413, | |
| DST_DST64_DSTT_DSTT64_DSTST_DSTST64_DSTSTT_DSTSTT64 = 414, | |
| RLDICL_RLDICL_32_RLDICL_32_64_RLDICR_RLDICR_32 = 415, | |
| MFFS_MFFS_rec_MFFSL = 416, | |
| TRECHKPT = 417, | |
| ADDME8_rec_ADDME_rec_ADDME8O_rec_ADDMEO_rec_ADDZE8_rec_ADDZE_rec_ADDZE8O_rec_ADDZEO_rec_SUBFME8_rec_SUBFME_rec_SUBFME8O_rec_SUBFMEO_rec_SUBFZE8_rec_SUBFZE_rec_SUBFZE8O_rec_SUBFZEO_rec = 418, | |
| MTFSB0 = 419, | |
| NEG8O_rec_NEGO_rec = 420, | |
| ADDE8_rec_ADDE_rec_ADDE8O_rec_ADDEO_rec_ADDIC_rec_SUBFE8_rec_SUBFE_rec_SUBFE8O_rec_SUBFEO_rec_SUBF8O_rec_SUBFO_rec = 421, | |
| HRFID = 422, | |
| FABSD_rec_FABSS_rec_FMR_rec_FNABSD_rec_FNABSS_rec_FNEGD_rec_FNEGS_rec = 423, | |
| SC = 424, | |
| ADDC_ADDC8_ADDC8O_ADDCO_SUBFC_SUBFC8_SUBFC8O_SUBFCO = 425, | |
| ADDC8_rec_ADDC_rec_SUBFC8_rec_SUBFC_rec = 426, | |
| MTFSF_MTFSFI_MTFSFIb = 427, | |
| MTFSFI_rec = 428, | |
| VSTRIBL_rec_VSTRIBR_rec_VSTRIHL_rec_VSTRIHR_rec = 429, | |
| LBZ_LBZ8_LDBRX_LHBRX_LHBRX8_LHZ_LHZ8_LWBRX_LWBRX8_LWZ_LWZ8 = 430, | |
| LD = 431, | |
| LDtoc_LDtocBA_LDtocCPT_LDtocJTI_LDtocL_SPILLTOVSR_LD_LWZtoc_LWZtocL = 432, | |
| LXVRBX_LXVRDX_LXVRHX_LXVRWX = 433, | |
| DCBT_DCBTST = 434, | |
| ICBT_LBZX_LBZX8_LBZXTLS_LBZXTLS__LBZXTLS_32_LHZX_LHZX8_LHZXTLS_LHZXTLS__LHZXTLS_32_LWZX_LWZX8_LWZXTLS_LWZXTLS__LWZXTLS_32 = 435, | |
| LDX_LDXTLS_LDXTLS_ = 436, | |
| SPILLTOVSR_LDX = 437, | |
| LBZCIX_LDCIX_LHZCIX_LWZCIX = 438, | |
| MTSR = 439, | |
| MTVRSAVE_MTVRSAVEv = 440, | |
| LSWI = 441, | |
| PLBZ_PLBZ8_PLBZ8pc_PLBZpc_PLD_PLDpc_PLFD_PLFDpc_PLFS_PLFSpc_PLHA_PLHA8_PLHA8pc_PLHApc_PLHZ_PLHZ8_PLHZ8pc_PLHZpc_PLWA_PLWA8_PLWA8pc_PLWApc_PLWZ_PLWZ8_PLWZ8pc_PLWZpc_PLXSD_PLXSDpc_PLXSSP_PLXSSPpc_PLXV_PLXVpc_PLXVP_PLXVPpc = 442, | |
| LXVP_LXVPX = 443, | |
| MFSR = 444, | |
| MFTB8 = 445, | |
| XXSETACCZ = 446, | |
| XVBF16GER2_XVF16GER2_XVF32GER_XVF64GER_XVI16GER2_XVI16GER2S_XVI4GER8_XVI8GER4 = 447, | |
| XVBF16GER2NN_XVBF16GER2NP_XVBF16GER2PN_XVBF16GER2PP_XVF16GER2NN_XVF16GER2NP_XVF16GER2PN_XVF16GER2PP_XVF32GERNN_XVF32GERNP_XVF32GERPN_XVF32GERPP_XVF64GERNN_XVF64GERNP_XVF64GERPN_XVF64GERPP_XVI16GER2PP_XVI16GER2SPP_XVI4GER8PP_XVI8GER4PP = 448, | |
| XVI8GER4SPP = 449, | |
| PMXVF32GER_PMXVF64GER = 450, | |
| PMXVBF16GER2_PMXVF16GER2_PMXVF32GERNN_PMXVF32GERNP_PMXVF32GERPN_PMXVF32GERPP_PMXVF64GERNN_PMXVF64GERNP_PMXVF64GERPN_PMXVF64GERPP_PMXVI16GER2_PMXVI16GER2S_PMXVI4GER8_PMXVI8GER4 = 451, | |
| PMXVBF16GER2NN_PMXVBF16GER2NP_PMXVBF16GER2PN_PMXVBF16GER2PP_PMXVF16GER2NN_PMXVF16GER2NP_PMXVF16GER2PN_PMXVF16GER2PP_PMXVI16GER2PP_PMXVI16GER2SPP_PMXVI4GER8PP_PMXVI8GER4PP = 452, | |
| PMXVI8GER4SPP = 453, | |
| XXMTACC = 454, | |
| XXMFACC = 455, | |
| MULLD_MULLDO = 456, | |
| VMULHSD_VMULHUD_VMULLD = 457, | |
| VSPLTISW = 458, | |
| V_SETALLONES_V_SETALLONESB_V_SETALLONESH = 459, | |
| BRD_BRH_BRH8_BRW_BRW8 = 460, | |
| LXVKQ_VSTRIBL_VSTRIBR_VSTRIHL_VSTRIHR = 461, | |
| MFVSRLD_MTVSRWS_VCLZLSBB_VCTZLSBB_VPRTYBQ = 462, | |
| VGBBD_VUPKHPX_VUPKHSB_VUPKHSH_VUPKHSW_VUPKLPX_VUPKLSB_VUPKLSH_VUPKLSW_XXBRD_XXBRH_XXBRQ_XXBRW = 463, | |
| VSPLTISB_VSPLTISH_XXSPLTIB = 464, | |
| XVCVBF16SPN = 465, | |
| VBPERMQ_VMRGHB_VMRGHH_VMRGHW_VMRGLB_VMRGLH_VMRGLW_VPKPX_VPKSDSS_VPKSDUS_VPKSHSS_VPKSHUS_VPKSWSS_VPKSWUS_VPKUDUM_VPKUDUS_VPKUHUM_VPKUHUS_VPKUWUM_VPKUWUS_VSL_VSLO_VSLV_VSR_VSRO_VSRV_XXEXTRACTUW = 466, | |
| VCLRLB_VCLRRB_XXGENPCVDM_XXGENPCVHM_XXGENPCVWM = 467, | |
| VEXTRACTD_VEXTRACTUB_VEXTRACTUH_VEXTRACTUW_VEXTUBLX_VEXTUBRX_VEXTUHLX_VEXTUHRX_VEXTUWLX_VEXTUWRX_VINSERTD_VINSERTW = 468, | |
| VSPLTB_VSPLTBs_VSPLTH_VSPLTHs_VSPLTW_XXMRGHW_XXMRGLW_XXPERMDI_XXPERMDIs_XXSLDWI_XXSLDWIs_XXSPLTW_XXSPLTWs = 469, | |
| VEXTDDVLX_VEXTDDVRX_VEXTDUBVLX_VEXTDUBVRX_VEXTDUHVLX_VEXTDUHVRX_VEXTDUWVLX_VEXTDUWVRX_VINSBLX_VINSBRX_VINSBVLX_VINSBVRX_VINSD_VINSDLX_VINSDRX_VINSHLX_VINSHRX_VINSHVLX_VINSHVRX_VINSW_VINSWLX_VINSWRX_VINSWVLX_VINSWVRX_VSLDBI_VSRDBI = 470, | |
| VSUMSWS = 471, | |
| XXSPLTIDP_XXSPLTIW = 472, | |
| XXBLENDVB_XXBLENDVD_XXBLENDVH_XXBLENDVW_XXSPLTI32DX = 473, | |
| XXEVAL = 474, | |
| XXPERMX = 475, | |
| DCBST_DCBZ = 476, | |
| ICBI = 477, | |
| DCBF = 478, | |
| PSTXVP_PSTXVPpc = 479, | |
| STB_STB8_STDBRX_STH_STH8_STHBRX_STW_STW8_STWBRX = 480, | |
| SPILLTOVSR_ST = 481, | |
| STD = 482, | |
| DFSTOREf32_DFSTOREf64_STIWX = 483, | |
| STXVRBX_STXVRDX_STXVRHX_STXVRWX = 484, | |
| SPILLTOVSR_STX = 485, | |
| EnforceIEIO = 486, | |
| STBCIX_STDCIX_STHCIX_STWCIX = 487, | |
| PSTB_PSTB8_PSTB8pc_PSTBpc_PSTD_PSTDpc_PSTFD_PSTFDpc_PSTFS_PSTFSpc_PSTH_PSTH8_PSTH8pc_PSTHpc_PSTW_PSTW8_PSTW8pc_PSTWpc_PSTXSD_PSTXSDpc_PSTXSSP_PSTXSSPpc_PSTXV_PSTXVpc = 488, | |
| STXVP_STXVPX = 489, | |
| ATTN_NAP = 490, | |
| DCBZL = 491, | |
| DCCCI_ICBLQ_ICCCI_TLBLD_TLBLI_TLBRE2_TLBSX2_TLBSX2D_TLBWE2 = 492, | |
| ICBLC = 493, | |
| CLRBHRB = 494, | |
| MFBHRBE = 495, | |
| PADDI_PADDI8_PADDI8pc_PADDIpc = 496, | |
| PLI_PLI8 = 497, | |
| VMULESB_VMULESH_VMULESW_VMULEUB_VMULEUH_VMULEUW_VMULOSB_VMULOSH_VMULOSW_VMULOUB_VMULOUH_VMULOUW_VSUM2SWS_VSUM4SBS_VSUM4SHS_VSUM4UBS = 498, | |
| VMULESD_VMULEUD_VMULHSW_VMULHUW_VMULOSD_VMULOUD = 499, | |
| VMSUMCUD = 500, | |
| SCHED_LIST_END = 501 | |
| }; | |
| } // end namespace Sched | |
| } // end namespace PPC | |
| } // end namespace llvm | |
| #endif // GET_INSTRINFO_SCHED_ENUM | |
| #ifdef GET_INSTRINFO_MC_DESC | |
| #undef GET_INSTRINFO_MC_DESC | |
| namespace llvm { | |
| static const MCPhysReg ImplicitList1[] = { PPC::CR0 }; | |
| static const MCPhysReg ImplicitList2[] = { PPC::CR7 }; | |
| static const MCPhysReg ImplicitList3[] = { PPC::XER }; | |
| static const MCPhysReg ImplicitList4[] = { PPC::XER, PPC::CR0 }; | |
| static const MCPhysReg ImplicitList5[] = { PPC::CARRY }; | |
| static const MCPhysReg ImplicitList6[] = { PPC::CARRY, PPC::XER }; | |
| static const MCPhysReg ImplicitList7[] = { PPC::CARRY, PPC::XER, PPC::CR0 }; | |
| static const MCPhysReg ImplicitList8[] = { PPC::CARRY, PPC::CR0 }; | |
| static const MCPhysReg ImplicitList9[] = { PPC::CARRY, PPC::CARRY }; | |
| static const MCPhysReg ImplicitList10[] = { PPC::CARRY, PPC::CARRY, PPC::XER }; | |
| static const MCPhysReg ImplicitList11[] = { PPC::CARRY, PPC::CARRY, PPC::XER, PPC::CR0 }; | |
| static const MCPhysReg ImplicitList12[] = { PPC::CARRY, PPC::CARRY, PPC::CR0 }; | |
| static const MCPhysReg ImplicitList13[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::LR8, PPC::CTR8, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7 }; | |
| static const MCPhysReg ImplicitList14[] = { PPC::R0, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7 }; | |
| static const MCPhysReg ImplicitList15[] = { PPC::R1, PPC::R1 }; | |
| static const MCPhysReg ImplicitList16[] = { PPC::CTR }; | |
| static const MCPhysReg ImplicitList17[] = { PPC::CTR8 }; | |
| static const MCPhysReg ImplicitList18[] = { PPC::CTR, PPC::RM, PPC::LR }; | |
| static const MCPhysReg ImplicitList19[] = { PPC::CTR8, PPC::RM, PPC::LR8 }; | |
| static const MCPhysReg ImplicitList20[] = { PPC::RM, PPC::LR }; | |
| static const MCPhysReg ImplicitList21[] = { PPC::LR, PPC::RM }; | |
| static const MCPhysReg ImplicitList22[] = { PPC::LR, PPC::RM, PPC::LR }; | |
| static const MCPhysReg ImplicitList23[] = { PPC::CR6 }; | |
| static const MCPhysReg ImplicitList24[] = { PPC::CTR8, PPC::RM, PPC::LR8, PPC::X2 }; | |
| static const MCPhysReg ImplicitList25[] = { PPC::CTR8, PPC::RM, PPC::LR8, PPC::X2, PPC::RM }; | |
| static const MCPhysReg ImplicitList26[] = { PPC::CTR8, PPC::RM, PPC::LR8, PPC::RM }; | |
| static const MCPhysReg ImplicitList27[] = { PPC::CTR, PPC::RM, PPC::LR, PPC::R2 }; | |
| static const MCPhysReg ImplicitList28[] = { PPC::CTR, PPC::RM, PPC::LR, PPC::R2, PPC::RM }; | |
| static const MCPhysReg ImplicitList29[] = { PPC::CTR, PPC::RM, PPC::LR, PPC::RM }; | |
| static const MCPhysReg ImplicitList30[] = { PPC::CTR, PPC::CTR }; | |
| static const MCPhysReg ImplicitList31[] = { PPC::CTR8, PPC::CTR8 }; | |
| static const MCPhysReg ImplicitList32[] = { PPC::CTR, PPC::RM, PPC::CTR }; | |
| static const MCPhysReg ImplicitList33[] = { PPC::CTR, PPC::LR, PPC::RM, PPC::CTR }; | |
| static const MCPhysReg ImplicitList34[] = { PPC::CTR8, PPC::LR8, PPC::RM, PPC::CTR8 }; | |
| static const MCPhysReg ImplicitList35[] = { PPC::RM, PPC::LR8 }; | |
| static const MCPhysReg ImplicitList36[] = { PPC::RM, PPC::LR8, PPC::RM }; | |
| static const MCPhysReg ImplicitList37[] = { PPC::RM, PPC::LR, PPC::RM }; | |
| static const MCPhysReg ImplicitList38[] = { PPC::LR8, PPC::RM }; | |
| static const MCPhysReg ImplicitList39[] = { PPC::CR1EQ }; | |
| static const MCPhysReg ImplicitList40[] = { PPC::X1, PPC::X1 }; | |
| static const MCPhysReg ImplicitList41[] = { PPC::CR1 }; | |
| static const MCPhysReg ImplicitList42[] = { PPC::RM }; | |
| static const MCPhysReg ImplicitList43[] = { PPC::RM, PPC::CR1 }; | |
| static const MCPhysReg ImplicitList44[] = { PPC::X0, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::LR8, PPC::CTR8, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7 }; | |
| static const MCPhysReg ImplicitList45[] = { PPC::R0, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7 }; | |
| static const MCPhysReg ImplicitList46[] = { PPC::R0, PPC::R4, PPC::R5, PPC::R11, PPC::LR, PPC::CR0 }; | |
| static const MCPhysReg ImplicitList47[] = { PPC::X0, PPC::X4, PPC::X5, PPC::X11, PPC::LR8, PPC::CR0 }; | |
| static const MCPhysReg ImplicitList48[] = { PPC::X0, PPC::X2, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::LR8, PPC::CTR8, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7 }; | |
| static const MCPhysReg ImplicitList49[] = { PPC::LR }; | |
| static const MCPhysReg ImplicitList50[] = { PPC::LR8 }; | |
| static const MCPhysReg ImplicitList51[] = { PPC::RM, PPC::RM }; | |
| static const MCPhysReg ImplicitList52[] = { PPC::CTR, PPC::RM }; | |
| static const MCPhysReg ImplicitList53[] = { PPC::CTR8, PPC::RM }; | |
| static const MCPhysReg ImplicitList54[] = { PPC::RM, PPC::CR6 }; | |
| static const MCPhysReg ImplicitList55[] = { PPC::CTR, PPC::LR, PPC::RM, PPC::LR, PPC::CTR }; | |
| static const MCPhysReg ImplicitList56[] = { PPC::CTR, PPC::RM, PPC::LR, PPC::CTR }; | |
| static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, }; | |
| static const MCOperandInfo OperandInfo10[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo11[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo12[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo13[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo14[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo15[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; | |
| static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo32[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo33[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; | |
| static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; | |
| static const MCOperandInfo OperandInfo35[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; | |
| static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; | |
| static const MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo38[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; | |
| static const MCOperandInfo OperandInfo39[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; | |
| static const MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; | |
| static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo42[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo43[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo44[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; | |
| static const MCOperandInfo OperandInfo45[] = { { PPC::G8pRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::G8pRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo46[] = { { PPC::G8pRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::G8pRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo47[] = { { PPC::G8pRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo48[] = { { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::UACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo49[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo50[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo51[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo52[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo53[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo54[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo55[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo56[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo57[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo58[] = { { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; | |
| static const MCOperandInfo OperandInfo59[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo60[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo61[] = { { PPC::SPILLTOVSRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo62[] = { { PPC::SPILLTOVSRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo63[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo64[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo65[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo66[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo67[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo68[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo69[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo70[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo71[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo72[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo73[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo74[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo75[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo76[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo77[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo78[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo79[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo80[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo81[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo82[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo83[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo84[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo85[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo86[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo87[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; | |
| static const MCOperandInfo OperandInfo88[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; | |
| static const MCOperandInfo OperandInfo89[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; | |
| static const MCOperandInfo OperandInfo90[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo91[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo92[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo93[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo94[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo95[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo96[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo97[] = { { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo98[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo99[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo100[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo101[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo102[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo103[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo104[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo105[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo106[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo107[] = { { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo108[] = { { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo109[] = { { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::DMRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo110[] = { { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::DMRROWpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo111[] = { { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo112[] = { { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::WACC_HIRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo113[] = { { PPC::DMRROWpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo114[] = { { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo115[] = { { PPC::WACC_HIRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo116[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo117[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo118[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo119[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo120[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo121[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo122[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo123[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo124[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo125[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo126[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo127[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo128[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo129[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo130[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo131[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo132[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo133[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo134[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo135[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo136[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo137[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo138[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo139[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo140[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo141[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo142[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo143[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo144[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo145[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo146[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo147[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo148[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo149[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo150[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo151[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo152[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo153[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, }; | |
| static const MCOperandInfo OperandInfo154[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, }; | |
| static const MCOperandInfo OperandInfo155[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo156[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo157[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo158[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo159[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo160[] = { { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo161[] = { { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo162[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo163[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo164[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo165[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, }; | |
| static const MCOperandInfo OperandInfo166[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo167[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo168[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, }; | |
| static const MCOperandInfo OperandInfo169[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo170[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo171[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo172[] = { { PPC::G8pRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo173[] = { { PPC::G8pRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo174[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo175[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo176[] = { { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo177[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo178[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo179[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo180[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo181[] = { { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo182[] = { { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo183[] = { { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo184[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo185[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo186[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo187[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo188[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo189[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo190[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo191[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo192[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo193[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo194[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo195[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRSAVERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo196[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo197[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo198[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo199[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo200[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo201[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo202[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo203[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo204[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo205[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo206[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo207[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo208[] = { { PPC::VRSAVERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo209[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo210[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo211[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo212[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo213[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo214[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo215[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo216[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo217[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo218[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo219[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo220[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo221[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo222[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo223[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo224[] = { { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo225[] = { { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo226[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo227[] = { { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo228[] = { { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo229[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo230[] = { { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo231[] = { { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo232[] = { { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo233[] = { { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo234[] = { { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo235[] = { { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo236[] = { { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo237[] = { { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo238[] = { { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo239[] = { { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo240[] = { { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo241[] = { { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo242[] = { { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo243[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo244[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo245[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo246[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo247[] = { { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo248[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo249[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo250[] = { { PPC::G8pRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo251[] = { { PPC::UACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo252[] = { { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo253[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo254[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo255[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo256[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo257[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo258[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo259[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo260[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo261[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo262[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo263[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo264[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo265[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo266[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo267[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo268[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo269[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo270[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo271[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo272[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo273[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo274[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo275[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo276[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo277[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo278[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo279[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo280[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo281[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo282[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo283[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo284[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8pRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo285[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, }; | |
| static const MCOperandInfo OperandInfo286[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, }; | |
| static const MCOperandInfo OperandInfo287[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo288[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo289[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, }; | |
| static const MCOperandInfo OperandInfo290[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo291[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, }; | |
| static const MCOperandInfo OperandInfo292[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, }; | |
| static const MCOperandInfo OperandInfo293[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo294[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo295[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo296[] = { { PPC::CTRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo297[] = { { PPC::CTRRC8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo298[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo299[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo300[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo301[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo302[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo303[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo304[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo305[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo306[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo307[] = { { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo308[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo309[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo310[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo311[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo312[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo313[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo314[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo315[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; | |
| static const MCOperandInfo OperandInfo316[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo317[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo318[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo319[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo320[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo321[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo322[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo323[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo324[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo325[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo326[] = { { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo327[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo328[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo329[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo330[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo331[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo332[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo333[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo334[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo335[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo336[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo337[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo338[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo339[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo340[] = { { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo341[] = { { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo342[] = { { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo343[] = { { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo344[] = { { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo345[] = { { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo346[] = { { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo347[] = { { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRpRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo348[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo349[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo350[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo351[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo352[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo353[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo354[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo355[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo356[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo357[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo358[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo359[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo360[] = { { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; | |
| static const MCOperandInfo OperandInfo361[] = { { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; | |
| static const MCOperandInfo OperandInfo362[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo363[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo364[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo365[] = { { PPC::ACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo366[] = { { PPC::WACCRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo367[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo368[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo369[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; | |
| static const MCOperandInfo OperandInfo370[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo371[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo372[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo373[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; | |
| extern const MCInstrDesc PPCInsts[] = { | |
| { 2632, 4, 0, 4, 335, 2, 1, 0|(1ULL<<MCID::Branch), 0x38ULL, ImplicitList32, OperandInfo373 }, // Inst #2632 = gBCat | |
| { 2631, 4, 0, 4, 335, 2, 2, 0|(1ULL<<MCID::Branch), 0x38ULL, ImplicitList56, OperandInfo373 }, // Inst #2631 = gBCLat | |
| { 2630, 3, 0, 4, 333, 3, 2, 0|(1ULL<<MCID::Branch), 0x38ULL, ImplicitList55, OperandInfo372 }, // Inst #2630 = gBCLRL | |
| { 2629, 3, 0, 4, 333, 3, 1, 0|(1ULL<<MCID::Branch), 0x38ULL, ImplicitList33, OperandInfo372 }, // Inst #2629 = gBCLR | |
| { 2628, 4, 0, 4, 289, 2, 2, 0|(1ULL<<MCID::Branch), 0x38ULL, ImplicitList56, OperandInfo371 }, // Inst #2628 = gBCLAat | |
| { 2627, 3, 0, 4, 289, 2, 2, 0|(1ULL<<MCID::Branch), 0x38ULL, ImplicitList56, OperandInfo370 }, // Inst #2627 = gBCLA | |
| { 2626, 3, 0, 4, 335, 2, 2, 0|(1ULL<<MCID::Branch), 0x38ULL, ImplicitList56, OperandInfo369 }, // Inst #2626 = gBCL | |
| { 2625, 3, 0, 4, 336, 3, 2, 0|(1ULL<<MCID::Branch), 0x38ULL, ImplicitList55, OperandInfo372 }, // Inst #2625 = gBCCTRL | |
| { 2624, 3, 0, 4, 336, 3, 1, 0|(1ULL<<MCID::Branch), 0x38ULL, ImplicitList33, OperandInfo372 }, // Inst #2624 = gBCCTR | |
| { 2623, 4, 0, 4, 289, 2, 1, 0|(1ULL<<MCID::Branch), 0x38ULL, ImplicitList32, OperandInfo371 }, // Inst #2623 = gBCAat | |
| { 2622, 3, 0, 4, 289, 2, 1, 0|(1ULL<<MCID::Branch), 0x38ULL, ImplicitList32, OperandInfo370 }, // Inst #2622 = gBCA | |
| { 2621, 3, 0, 4, 335, 2, 1, 0|(1ULL<<MCID::Branch), 0x38ULL, ImplicitList32, OperandInfo369 }, // Inst #2621 = gBC | |
| { 2620, 3, 1, 4, 469, 0, 0, 0, 0x0ULL, nullptr, OperandInfo364 }, // Inst #2620 = XXSPLTWs | |
| { 2619, 3, 1, 4, 469, 0, 0, 0, 0x0ULL, nullptr, OperandInfo368 }, // Inst #2619 = XXSPLTW | |
| { 2618, 2, 1, 8, 472, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x80ULL, nullptr, OperandInfo179 }, // Inst #2618 = XXSPLTIW | |
| { 2617, 2, 1, 8, 472, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x80ULL, nullptr, OperandInfo179 }, // Inst #2617 = XXSPLTIDP | |
| { 2616, 2, 1, 4, 464, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo179 }, // Inst #2616 = XXSPLTIB | |
| { 2615, 4, 1, 8, 473, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x80ULL, nullptr, OperandInfo367 }, // Inst #2615 = XXSPLTI32DX | |
| { 2614, 3, 1, 4, 469, 0, 0, 0, 0x0ULL, nullptr, OperandInfo364 }, // Inst #2614 = XXSLDWIs | |
| { 2613, 4, 1, 4, 469, 0, 0, 0, 0x0ULL, nullptr, OperandInfo363 }, // Inst #2613 = XXSLDWI | |
| { 2612, 1, 1, 4, 23, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo366 }, // Inst #2612 = XXSETACCZW | |
| { 2611, 1, 1, 4, 446, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo365 }, // Inst #2611 = XXSETACCZ | |
| { 2610, 4, 1, 4, 103, 0, 0, 0, 0x0ULL, nullptr, OperandInfo352 }, // Inst #2610 = XXSEL | |
| { 2609, 5, 1, 8, 475, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo353 }, // Inst #2609 = XXPERMX | |
| { 2608, 4, 1, 4, 165, 0, 0, 0, 0x0ULL, nullptr, OperandInfo362 }, // Inst #2608 = XXPERMR | |
| { 2607, 3, 1, 4, 469, 0, 0, 0, 0x0ULL, nullptr, OperandInfo364 }, // Inst #2607 = XXPERMDIs | |
| { 2606, 4, 1, 4, 469, 0, 0, 0, 0x0ULL, nullptr, OperandInfo363 }, // Inst #2606 = XXPERMDI | |
| { 2605, 4, 1, 4, 165, 0, 0, 0, 0x0ULL, nullptr, OperandInfo362 }, // Inst #2605 = XXPERM | |
| { 2604, 2, 1, 4, 23, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo361 }, // Inst #2604 = XXMTACCW | |
| { 2603, 2, 1, 4, 454, 0, 0, 0, 0x0ULL, nullptr, OperandInfo360 }, // Inst #2603 = XXMTACC | |
| { 2602, 3, 1, 4, 469, 0, 0, 0, 0x0ULL, nullptr, OperandInfo339 }, // Inst #2602 = XXMRGLW | |
| { 2601, 3, 1, 4, 469, 0, 0, 0, 0x0ULL, nullptr, OperandInfo339 }, // Inst #2601 = XXMRGHW | |
| { 2600, 2, 1, 4, 23, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo361 }, // Inst #2600 = XXMFACCW | |
| { 2599, 2, 1, 4, 455, 0, 0, 0, 0x0ULL, nullptr, OperandInfo360 }, // Inst #2599 = XXMFACC | |
| { 2598, 1, 1, 4, 391, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo357 }, // Inst #2598 = XXLXORz | |
| { 2597, 1, 1, 4, 391, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo359 }, // Inst #2597 = XXLXORspz | |
| { 2596, 1, 1, 4, 391, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo358 }, // Inst #2596 = XXLXORdpz | |
| { 2595, 3, 1, 4, 391, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo339 }, // Inst #2595 = XXLXOR | |
| { 2594, 3, 1, 4, 410, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo319 }, // Inst #2594 = XXLORf | |
| { 2593, 3, 1, 4, 410, 0, 0, 0, 0x0ULL, nullptr, OperandInfo339 }, // Inst #2593 = XXLORC | |
| { 2592, 3, 1, 4, 410, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo339 }, // Inst #2592 = XXLOR | |
| { 2591, 3, 1, 4, 410, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo339 }, // Inst #2591 = XXLNOR | |
| { 2590, 3, 1, 4, 410, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo339 }, // Inst #2590 = XXLNAND | |
| { 2589, 1, 1, 4, 391, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo357 }, // Inst #2589 = XXLEQVOnes | |
| { 2588, 3, 1, 4, 391, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo339 }, // Inst #2588 = XXLEQV | |
| { 2587, 3, 1, 4, 410, 0, 0, 0, 0x0ULL, nullptr, OperandInfo339 }, // Inst #2587 = XXLANDC | |
| { 2586, 3, 1, 4, 410, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo339 }, // Inst #2586 = XXLAND | |
| { 2585, 4, 1, 4, 166, 0, 0, 0, 0x0ULL, nullptr, OperandInfo356 }, // Inst #2585 = XXINSERTW | |
| { 2584, 3, 1, 4, 467, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo355 }, // Inst #2584 = XXGENPCVWM | |
| { 2583, 3, 1, 4, 467, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo355 }, // Inst #2583 = XXGENPCVHM | |
| { 2582, 3, 1, 4, 467, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo355 }, // Inst #2582 = XXGENPCVDM | |
| { 2581, 3, 1, 4, 358, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo355 }, // Inst #2581 = XXGENPCVBM | |
| { 2580, 3, 1, 4, 466, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo354 }, // Inst #2580 = XXEXTRACTUW | |
| { 2579, 5, 1, 8, 474, 0, 0, 0, 0x80ULL, nullptr, OperandInfo353 }, // Inst #2579 = XXEVAL | |
| { 2578, 2, 1, 4, 463, 0, 0, 0, 0x0ULL, nullptr, OperandInfo338 }, // Inst #2578 = XXBRW | |
| { 2577, 2, 1, 4, 463, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo338 }, // Inst #2577 = XXBRQ | |
| { 2576, 2, 1, 4, 463, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo338 }, // Inst #2576 = XXBRH | |
| { 2575, 2, 1, 4, 463, 0, 0, 0, 0x0ULL, nullptr, OperandInfo338 }, // Inst #2575 = XXBRD | |
| { 2574, 4, 1, 8, 473, 0, 0, 0, 0x80ULL, nullptr, OperandInfo352 }, // Inst #2574 = XXBLENDVW | |
| { 2573, 4, 1, 8, 473, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo352 }, // Inst #2573 = XXBLENDVH | |
| { 2572, 4, 1, 8, 473, 0, 0, 0, 0x80ULL, nullptr, OperandInfo352 }, // Inst #2572 = XXBLENDVD | |
| { 2571, 4, 1, 8, 473, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo352 }, // Inst #2571 = XXBLENDVB | |
| { 2570, 2, 1, 4, 403, 0, 0, 0, 0x0ULL, nullptr, OperandInfo338 }, // Inst #2570 = XVXSIGSP | |
| { 2569, 2, 1, 4, 403, 0, 0, 0, 0x0ULL, nullptr, OperandInfo338 }, // Inst #2569 = XVXSIGDP | |
| { 2568, 2, 1, 4, 402, 0, 0, 0, 0x0ULL, nullptr, OperandInfo338 }, // Inst #2568 = XVXEXPSP | |
| { 2567, 2, 1, 4, 402, 0, 0, 0, 0x0ULL, nullptr, OperandInfo338 }, // Inst #2567 = XVXEXPDP | |
| { 2566, 3, 1, 4, 376, 0, 0, 0, 0x0ULL, nullptr, OperandInfo351 }, // Inst #2566 = XVTSTDCSP | |
| { 2565, 3, 1, 4, 376, 0, 0, 0, 0x0ULL, nullptr, OperandInfo351 }, // Inst #2565 = XVTSTDCDP | |
| { 2564, 2, 1, 4, 371, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo350 }, // Inst #2564 = XVTSQRTSP | |
| { 2563, 2, 1, 4, 371, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo350 }, // Inst #2563 = XVTSQRTDP | |
| { 2562, 2, 1, 4, 364, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo350 }, // Inst #2562 = XVTLSBB | |
| { 2561, 3, 1, 4, 145, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo349 }, // Inst #2561 = XVTDIVSP | |
| { 2560, 3, 1, 4, 145, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo349 }, // Inst #2560 = XVTDIVDP | |
| { 2559, 3, 1, 4, 324, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo339 }, // Inst #2559 = XVSUBSP | |
| { 2558, 3, 1, 4, 324, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo339 }, // Inst #2558 = XVSUBDP | |
| { 2557, 2, 1, 4, 266, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2557 = XVSQRTSP | |
| { 2556, 2, 1, 4, 265, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2556 = XVSQRTDP | |
| { 2555, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2555 = XVRSQRTESP | |
| { 2554, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2554 = XVRSQRTEDP | |
| { 2553, 2, 1, 4, 319, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo338 }, // Inst #2553 = XVRSPIZ | |
| { 2552, 2, 1, 4, 319, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo338 }, // Inst #2552 = XVRSPIP | |
| { 2551, 2, 1, 4, 319, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo338 }, // Inst #2551 = XVRSPIM | |
| { 2550, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2550 = XVRSPIC | |
| { 2549, 2, 1, 4, 319, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo338 }, // Inst #2549 = XVRSPI | |
| { 2548, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2548 = XVRESP | |
| { 2547, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2547 = XVREDP | |
| { 2546, 2, 1, 4, 319, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo338 }, // Inst #2546 = XVRDPIZ | |
| { 2545, 2, 1, 4, 319, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo338 }, // Inst #2545 = XVRDPIP | |
| { 2544, 2, 1, 4, 319, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo338 }, // Inst #2544 = XVRDPIM | |
| { 2543, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2543 = XVRDPIC | |
| { 2542, 2, 1, 4, 319, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo338 }, // Inst #2542 = XVRDPI | |
| { 2541, 4, 1, 4, 328, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo348 }, // Inst #2541 = XVNMSUBMSP | |
| { 2540, 4, 1, 4, 328, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo348 }, // Inst #2540 = XVNMSUBMDP | |
| { 2539, 4, 1, 4, 328, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo348 }, // Inst #2539 = XVNMSUBASP | |
| { 2538, 4, 1, 4, 328, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo348 }, // Inst #2538 = XVNMSUBADP | |
| { 2537, 4, 1, 4, 328, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo348 }, // Inst #2537 = XVNMADDMSP | |
| { 2536, 4, 1, 4, 328, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo348 }, // Inst #2536 = XVNMADDMDP | |
| { 2535, 4, 1, 4, 328, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo348 }, // Inst #2535 = XVNMADDASP | |
| { 2534, 4, 1, 4, 328, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo348 }, // Inst #2534 = XVNMADDADP | |
| { 2533, 2, 1, 4, 402, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2533 = XVNEGSP | |
| { 2532, 2, 1, 4, 402, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2532 = XVNEGDP | |
| { 2531, 2, 1, 4, 402, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2531 = XVNABSSP | |
| { 2530, 2, 1, 4, 402, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2530 = XVNABSDP | |
| { 2529, 3, 1, 4, 324, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo339 }, // Inst #2529 = XVMULSP | |
| { 2528, 3, 1, 4, 324, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo339 }, // Inst #2528 = XVMULDP | |
| { 2527, 4, 1, 4, 328, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo348 }, // Inst #2527 = XVMSUBMSP | |
| { 2526, 4, 1, 4, 328, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo348 }, // Inst #2526 = XVMSUBMDP | |
| { 2525, 4, 1, 4, 328, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo348 }, // Inst #2525 = XVMSUBASP | |
| { 2524, 4, 1, 4, 328, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo348 }, // Inst #2524 = XVMSUBADP | |
| { 2523, 3, 1, 4, 376, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo339 }, // Inst #2523 = XVMINSP | |
| { 2522, 3, 1, 4, 376, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo339 }, // Inst #2522 = XVMINDP | |
| { 2521, 3, 1, 4, 376, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo339 }, // Inst #2521 = XVMAXSP | |
| { 2520, 3, 1, 4, 376, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo339 }, // Inst #2520 = XVMAXDP | |
| { 2519, 4, 1, 4, 328, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo348 }, // Inst #2519 = XVMADDMSP | |
| { 2518, 4, 1, 4, 328, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo348 }, // Inst #2518 = XVMADDMDP | |
| { 2517, 4, 1, 4, 328, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo348 }, // Inst #2517 = XVMADDASP | |
| { 2516, 4, 1, 4, 328, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo348 }, // Inst #2516 = XVMADDADP | |
| { 2515, 3, 1, 4, 411, 0, 0, 0, 0x0ULL, nullptr, OperandInfo339 }, // Inst #2515 = XVIEXPSP | |
| { 2514, 3, 1, 4, 411, 0, 0, 0, 0x0ULL, nullptr, OperandInfo339 }, // Inst #2514 = XVIEXPDP | |
| { 2513, 4, 1, 4, 23, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo343 }, // Inst #2513 = XVI8GER4WSPP | |
| { 2512, 4, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo343 }, // Inst #2512 = XVI8GER4WPP | |
| { 2511, 3, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo342 }, // Inst #2511 = XVI8GER4W | |
| { 2510, 4, 1, 4, 449, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo341 }, // Inst #2510 = XVI8GER4SPP | |
| { 2509, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo341 }, // Inst #2509 = XVI8GER4PP | |
| { 2508, 3, 1, 4, 447, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo340 }, // Inst #2508 = XVI8GER4 | |
| { 2507, 4, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo343 }, // Inst #2507 = XVI4GER8WPP | |
| { 2506, 3, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo342 }, // Inst #2506 = XVI4GER8W | |
| { 2505, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo341 }, // Inst #2505 = XVI4GER8PP | |
| { 2504, 3, 1, 4, 447, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo340 }, // Inst #2504 = XVI4GER8 | |
| { 2503, 4, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo343 }, // Inst #2503 = XVI16GER2WPP | |
| { 2502, 3, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo342 }, // Inst #2502 = XVI16GER2W | |
| { 2501, 4, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo343 }, // Inst #2501 = XVI16GER2SWPP | |
| { 2500, 3, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo342 }, // Inst #2500 = XVI16GER2SW | |
| { 2499, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo341 }, // Inst #2499 = XVI16GER2SPP | |
| { 2498, 3, 1, 4, 447, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo340 }, // Inst #2498 = XVI16GER2S | |
| { 2497, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo341 }, // Inst #2497 = XVI16GER2PP | |
| { 2496, 3, 1, 4, 447, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo340 }, // Inst #2496 = XVI16GER2 | |
| { 2495, 4, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo347 }, // Inst #2495 = XVF64GERWPP | |
| { 2494, 4, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo347 }, // Inst #2494 = XVF64GERWPN | |
| { 2493, 4, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo347 }, // Inst #2493 = XVF64GERWNP | |
| { 2492, 4, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo347 }, // Inst #2492 = XVF64GERWNN | |
| { 2491, 3, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo346 }, // Inst #2491 = XVF64GERW | |
| { 2490, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2490 = XVF64GERPP | |
| { 2489, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2489 = XVF64GERPN | |
| { 2488, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2488 = XVF64GERNP | |
| { 2487, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2487 = XVF64GERNN | |
| { 2486, 3, 1, 4, 447, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo344 }, // Inst #2486 = XVF64GER | |
| { 2485, 4, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo343 }, // Inst #2485 = XVF32GERWPP | |
| { 2484, 4, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo343 }, // Inst #2484 = XVF32GERWPN | |
| { 2483, 4, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo343 }, // Inst #2483 = XVF32GERWNP | |
| { 2482, 4, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo343 }, // Inst #2482 = XVF32GERWNN | |
| { 2481, 3, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo342 }, // Inst #2481 = XVF32GERW | |
| { 2480, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo341 }, // Inst #2480 = XVF32GERPP | |
| { 2479, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo341 }, // Inst #2479 = XVF32GERPN | |
| { 2478, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo341 }, // Inst #2478 = XVF32GERNP | |
| { 2477, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo341 }, // Inst #2477 = XVF32GERNN | |
| { 2476, 3, 1, 4, 447, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo340 }, // Inst #2476 = XVF32GER | |
| { 2475, 4, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo343 }, // Inst #2475 = XVF16GER2WPP | |
| { 2474, 4, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo343 }, // Inst #2474 = XVF16GER2WPN | |
| { 2473, 4, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo343 }, // Inst #2473 = XVF16GER2WNP | |
| { 2472, 4, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo343 }, // Inst #2472 = XVF16GER2WNN | |
| { 2471, 3, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo342 }, // Inst #2471 = XVF16GER2W | |
| { 2470, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo341 }, // Inst #2470 = XVF16GER2PP | |
| { 2469, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo341 }, // Inst #2469 = XVF16GER2PN | |
| { 2468, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo341 }, // Inst #2468 = XVF16GER2NP | |
| { 2467, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo341 }, // Inst #2467 = XVF16GER2NN | |
| { 2466, 3, 1, 4, 447, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo340 }, // Inst #2466 = XVF16GER2 | |
| { 2465, 3, 1, 4, 275, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo339 }, // Inst #2465 = XVDIVSP | |
| { 2464, 3, 1, 4, 276, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo339 }, // Inst #2464 = XVDIVDP | |
| { 2463, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2463 = XVCVUXWSP | |
| { 2462, 2, 1, 4, 319, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2462 = XVCVUXWDP | |
| { 2461, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2461 = XVCVUXDSP | |
| { 2460, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2460 = XVCVUXDDP | |
| { 2459, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2459 = XVCVSXWSP | |
| { 2458, 2, 1, 4, 319, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2458 = XVCVSXWDP | |
| { 2457, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2457 = XVCVSXDSP | |
| { 2456, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2456 = XVCVSXDDP | |
| { 2455, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2455 = XVCVSPUXWS | |
| { 2454, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2454 = XVCVSPUXDS | |
| { 2453, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2453 = XVCVSPSXWS | |
| { 2452, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2452 = XVCVSPSXDS | |
| { 2451, 2, 1, 4, 319, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo338 }, // Inst #2451 = XVCVSPHP | |
| { 2450, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2450 = XVCVSPDP | |
| { 2449, 2, 1, 4, 321, 0, 0, 0, 0x0ULL, nullptr, OperandInfo338 }, // Inst #2449 = XVCVSPBF16 | |
| { 2448, 2, 1, 4, 370, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo338 }, // Inst #2448 = XVCVHPSP | |
| { 2447, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2447 = XVCVDPUXWS | |
| { 2446, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2446 = XVCVDPUXDS | |
| { 2445, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2445 = XVCVDPSXWS | |
| { 2444, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2444 = XVCVDPSXDS | |
| { 2443, 2, 1, 4, 319, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2443 = XVCVDPSP | |
| { 2442, 2, 1, 4, 465, 0, 0, 0, 0x0ULL, nullptr, OperandInfo338 }, // Inst #2442 = XVCVBF16SPN | |
| { 2441, 3, 1, 4, 411, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo339 }, // Inst #2441 = XVCPSGNSP | |
| { 2440, 3, 1, 4, 411, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo339 }, // Inst #2440 = XVCPSGNDP | |
| { 2439, 3, 1, 4, 377, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList54, OperandInfo339 }, // Inst #2439 = XVCMPGTSP_rec | |
| { 2438, 3, 1, 4, 377, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo339 }, // Inst #2438 = XVCMPGTSP | |
| { 2437, 3, 1, 4, 377, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList54, OperandInfo339 }, // Inst #2437 = XVCMPGTDP_rec | |
| { 2436, 3, 1, 4, 377, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo339 }, // Inst #2436 = XVCMPGTDP | |
| { 2435, 3, 1, 4, 377, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList54, OperandInfo339 }, // Inst #2435 = XVCMPGESP_rec | |
| { 2434, 3, 1, 4, 377, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo339 }, // Inst #2434 = XVCMPGESP | |
| { 2433, 3, 1, 4, 377, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList54, OperandInfo339 }, // Inst #2433 = XVCMPGEDP_rec | |
| { 2432, 3, 1, 4, 377, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo339 }, // Inst #2432 = XVCMPGEDP | |
| { 2431, 3, 1, 4, 377, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList54, OperandInfo339 }, // Inst #2431 = XVCMPEQSP_rec | |
| { 2430, 3, 1, 4, 377, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo339 }, // Inst #2430 = XVCMPEQSP | |
| { 2429, 3, 1, 4, 377, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList54, OperandInfo339 }, // Inst #2429 = XVCMPEQDP_rec | |
| { 2428, 3, 1, 4, 377, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo339 }, // Inst #2428 = XVCMPEQDP | |
| { 2427, 4, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo343 }, // Inst #2427 = XVBF16GER2WPP | |
| { 2426, 4, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo343 }, // Inst #2426 = XVBF16GER2WPN | |
| { 2425, 4, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo343 }, // Inst #2425 = XVBF16GER2WNP | |
| { 2424, 4, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo343 }, // Inst #2424 = XVBF16GER2WNN | |
| { 2423, 3, 1, 4, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo342 }, // Inst #2423 = XVBF16GER2W | |
| { 2422, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo341 }, // Inst #2422 = XVBF16GER2PP | |
| { 2421, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo341 }, // Inst #2421 = XVBF16GER2PN | |
| { 2420, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo341 }, // Inst #2420 = XVBF16GER2NP | |
| { 2419, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo341 }, // Inst #2419 = XVBF16GER2NN | |
| { 2418, 3, 1, 4, 447, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo340 }, // Inst #2418 = XVBF16GER2 | |
| { 2417, 3, 1, 4, 324, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo339 }, // Inst #2417 = XVADDSP | |
| { 2416, 3, 1, 4, 324, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo339 }, // Inst #2416 = XVADDDP | |
| { 2415, 2, 1, 4, 402, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2415 = XVABSSP | |
| { 2414, 2, 1, 4, 402, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo338 }, // Inst #2414 = XVABSDP | |
| { 2413, 2, 1, 4, 354, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo96 }, // Inst #2413 = XSXSIGQP | |
| { 2412, 2, 1, 4, 112, 0, 0, 0, 0x0ULL, nullptr, OperandInfo198 }, // Inst #2412 = XSXSIGDP | |
| { 2411, 2, 1, 4, 402, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo96 }, // Inst #2411 = XSXEXPQP | |
| { 2410, 2, 1, 4, 401, 0, 0, 0, 0x0ULL, nullptr, OperandInfo198 }, // Inst #2410 = XSXEXPDP | |
| { 2409, 3, 1, 4, 111, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo336 }, // Inst #2409 = XSTSTDCSP | |
| { 2408, 3, 1, 4, 355, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo337 }, // Inst #2408 = XSTSTDCQP | |
| { 2407, 3, 1, 4, 111, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo336 }, // Inst #2407 = XSTSTDCDP | |
| { 2406, 2, 1, 4, 369, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo335 }, // Inst #2406 = XSTSQRTDP | |
| { 2405, 3, 1, 4, 113, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo322 }, // Inst #2405 = XSTDIVDP | |
| { 2404, 3, 1, 4, 326, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo320 }, // Inst #2404 = XSSUBSP | |
| { 2403, 3, 1, 4, 342, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2403 = XSSUBQPO | |
| { 2402, 3, 1, 4, 342, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2402 = XSSUBQP | |
| { 2401, 3, 1, 4, 326, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo319 }, // Inst #2401 = XSSUBDP | |
| { 2400, 2, 1, 4, 268, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo325 }, // Inst #2400 = XSSQRTSP | |
| { 2399, 2, 1, 4, 174, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo96 }, // Inst #2399 = XSSQRTQPO | |
| { 2398, 2, 1, 4, 174, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo96 }, // Inst #2398 = XSSQRTQP | |
| { 2397, 2, 1, 4, 263, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo318 }, // Inst #2397 = XSSQRTDP | |
| { 2396, 2, 1, 4, 320, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo325 }, // Inst #2396 = XSRSQRTESP | |
| { 2395, 2, 1, 4, 320, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo318 }, // Inst #2395 = XSRSQRTEDP | |
| { 2394, 2, 1, 4, 320, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo328 }, // Inst #2394 = XSRSP | |
| { 2393, 4, 1, 4, 169, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo334 }, // Inst #2393 = XSRQPXP | |
| { 2392, 4, 1, 4, 169, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo334 }, // Inst #2392 = XSRQPIX | |
| { 2391, 4, 1, 4, 169, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo334 }, // Inst #2391 = XSRQPI | |
| { 2390, 2, 1, 4, 320, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo325 }, // Inst #2390 = XSRESP | |
| { 2389, 2, 1, 4, 320, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo318 }, // Inst #2389 = XSREDP | |
| { 2388, 2, 1, 4, 320, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo318 }, // Inst #2388 = XSRDPIZ | |
| { 2387, 2, 1, 4, 320, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo318 }, // Inst #2387 = XSRDPIP | |
| { 2386, 2, 1, 4, 320, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo318 }, // Inst #2386 = XSRDPIM | |
| { 2385, 2, 1, 4, 320, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo318 }, // Inst #2385 = XSRDPIC | |
| { 2384, 2, 1, 4, 320, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo318 }, // Inst #2384 = XSRDPI | |
| { 2383, 4, 1, 4, 171, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo333 }, // Inst #2383 = XSNMSUBQPO | |
| { 2382, 4, 1, 4, 171, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo333 }, // Inst #2382 = XSNMSUBQP | |
| { 2381, 4, 1, 4, 155, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo332 }, // Inst #2381 = XSNMSUBMSP | |
| { 2380, 4, 1, 4, 155, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo331 }, // Inst #2380 = XSNMSUBMDP | |
| { 2379, 4, 1, 4, 155, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo332 }, // Inst #2379 = XSNMSUBASP | |
| { 2378, 4, 1, 4, 155, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo331 }, // Inst #2378 = XSNMSUBADP | |
| { 2377, 4, 1, 4, 171, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo333 }, // Inst #2377 = XSNMADDQPO | |
| { 2376, 4, 1, 4, 171, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo333 }, // Inst #2376 = XSNMADDQP | |
| { 2375, 4, 1, 4, 155, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo332 }, // Inst #2375 = XSNMADDMSP | |
| { 2374, 4, 1, 4, 155, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo331 }, // Inst #2374 = XSNMADDMDP | |
| { 2373, 4, 1, 4, 155, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo332 }, // Inst #2373 = XSNMADDASP | |
| { 2372, 4, 1, 4, 155, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo331 }, // Inst #2372 = XSNMADDADP | |
| { 2371, 2, 1, 4, 402, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2371 = XSNEGQP | |
| { 2370, 2, 1, 4, 401, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo318 }, // Inst #2370 = XSNEGDP | |
| { 2369, 2, 1, 4, 402, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2369 = XSNABSQP | |
| { 2368, 2, 1, 4, 401, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo325 }, // Inst #2368 = XSNABSDPs | |
| { 2367, 2, 1, 4, 401, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo318 }, // Inst #2367 = XSNABSDP | |
| { 2366, 3, 1, 4, 327, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo320 }, // Inst #2366 = XSMULSP | |
| { 2365, 3, 1, 4, 344, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2365 = XSMULQPO | |
| { 2364, 3, 1, 4, 344, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2364 = XSMULQP | |
| { 2363, 3, 1, 4, 327, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo319 }, // Inst #2363 = XSMULDP | |
| { 2362, 4, 1, 4, 171, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo333 }, // Inst #2362 = XSMSUBQPO | |
| { 2361, 4, 1, 4, 171, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo333 }, // Inst #2361 = XSMSUBQP | |
| { 2360, 4, 1, 4, 155, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo332 }, // Inst #2360 = XSMSUBMSP | |
| { 2359, 4, 1, 4, 155, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo331 }, // Inst #2359 = XSMSUBMDP | |
| { 2358, 4, 1, 4, 155, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo332 }, // Inst #2358 = XSMSUBASP | |
| { 2357, 4, 1, 4, 155, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo331 }, // Inst #2357 = XSMSUBADP | |
| { 2356, 3, 1, 4, 380, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo321 }, // Inst #2356 = XSMINJDP | |
| { 2355, 3, 1, 4, 380, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo319 }, // Inst #2355 = XSMINDP | |
| { 2354, 3, 1, 4, 357, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2354 = XSMINCQP | |
| { 2353, 3, 1, 4, 380, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo319 }, // Inst #2353 = XSMINCDP | |
| { 2352, 3, 1, 4, 380, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo321 }, // Inst #2352 = XSMAXJDP | |
| { 2351, 3, 1, 4, 380, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo319 }, // Inst #2351 = XSMAXDP | |
| { 2350, 3, 1, 4, 357, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2350 = XSMAXCQP | |
| { 2349, 3, 1, 4, 380, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo319 }, // Inst #2349 = XSMAXCDP | |
| { 2348, 4, 1, 4, 171, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo333 }, // Inst #2348 = XSMADDQPO | |
| { 2347, 4, 1, 4, 171, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo333 }, // Inst #2347 = XSMADDQP | |
| { 2346, 4, 1, 4, 155, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo332 }, // Inst #2346 = XSMADDMSP | |
| { 2345, 4, 1, 4, 155, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo331 }, // Inst #2345 = XSMADDMDP | |
| { 2344, 4, 1, 4, 155, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo332 }, // Inst #2344 = XSMADDASP | |
| { 2343, 4, 1, 4, 155, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo331 }, // Inst #2343 = XSMADDADP | |
| { 2342, 3, 1, 4, 411, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo330 }, // Inst #2342 = XSIEXPQP | |
| { 2341, 3, 1, 4, 138, 0, 0, 0, 0x0ULL, nullptr, OperandInfo329 }, // Inst #2341 = XSIEXPDP | |
| { 2340, 3, 1, 4, 274, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo320 }, // Inst #2340 = XSDIVSP | |
| { 2339, 3, 1, 4, 173, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2339 = XSDIVQPO | |
| { 2338, 3, 1, 4, 173, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2338 = XSDIVQP | |
| { 2337, 3, 1, 4, 271, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo319 }, // Inst #2337 = XSDIVDP | |
| { 2336, 2, 1, 4, 320, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo328 }, // Inst #2336 = XSCVUXDSP | |
| { 2335, 2, 1, 4, 320, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo318 }, // Inst #2335 = XSCVUXDDP | |
| { 2334, 2, 1, 4, 341, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2334 = XSCVUQQP | |
| { 2333, 2, 1, 4, 340, 0, 0, 0, 0x0ULL, nullptr, OperandInfo323 }, // Inst #2333 = XSCVUDQP | |
| { 2332, 2, 1, 4, 320, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo328 }, // Inst #2332 = XSCVSXDSP | |
| { 2331, 2, 1, 4, 320, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo318 }, // Inst #2331 = XSCVSXDDP | |
| { 2330, 2, 1, 4, 341, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2330 = XSCVSQQP | |
| { 2329, 2, 1, 4, 368, 0, 0, 0, 0x0ULL, nullptr, OperandInfo327 }, // Inst #2329 = XSCVSPDPN | |
| { 2328, 2, 1, 4, 320, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo318 }, // Inst #2328 = XSCVSPDP | |
| { 2327, 2, 1, 4, 340, 0, 0, 0, 0x0ULL, nullptr, OperandInfo323 }, // Inst #2327 = XSCVSDQP | |
| { 2326, 2, 1, 4, 340, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo96 }, // Inst #2326 = XSCVQPUWZ | |
| { 2325, 2, 1, 4, 341, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2325 = XSCVQPUQZ | |
| { 2324, 2, 1, 4, 340, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo96 }, // Inst #2324 = XSCVQPUDZ | |
| { 2323, 2, 1, 4, 340, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo96 }, // Inst #2323 = XSCVQPSWZ | |
| { 2322, 2, 1, 4, 341, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2322 = XSCVQPSQZ | |
| { 2321, 2, 1, 4, 340, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo96 }, // Inst #2321 = XSCVQPSDZ | |
| { 2320, 2, 1, 4, 340, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo326 }, // Inst #2320 = XSCVQPDPO | |
| { 2319, 2, 1, 4, 340, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo326 }, // Inst #2319 = XSCVQPDP | |
| { 2318, 2, 1, 4, 163, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo318 }, // Inst #2318 = XSCVHPDP | |
| { 2317, 2, 1, 4, 320, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo325 }, // Inst #2317 = XSCVDPUXWSs | |
| { 2316, 2, 1, 4, 320, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo318 }, // Inst #2316 = XSCVDPUXWS | |
| { 2315, 2, 1, 4, 320, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo325 }, // Inst #2315 = XSCVDPUXDSs | |
| { 2314, 2, 1, 4, 320, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo318 }, // Inst #2314 = XSCVDPUXDS | |
| { 2313, 2, 1, 4, 320, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo325 }, // Inst #2313 = XSCVDPSXWSs | |
| { 2312, 2, 1, 4, 320, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo318 }, // Inst #2312 = XSCVDPSXWS | |
| { 2311, 2, 1, 4, 320, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo325 }, // Inst #2311 = XSCVDPSXDSs | |
| { 2310, 2, 1, 4, 320, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo318 }, // Inst #2310 = XSCVDPSXDS | |
| { 2309, 2, 1, 4, 320, 0, 0, 0, 0x0ULL, nullptr, OperandInfo324 }, // Inst #2309 = XSCVDPSPN | |
| { 2308, 2, 1, 4, 320, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo318 }, // Inst #2308 = XSCVDPSP | |
| { 2307, 2, 1, 4, 340, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, nullptr, OperandInfo323 }, // Inst #2307 = XSCVDPQP | |
| { 2306, 2, 1, 4, 320, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo318 }, // Inst #2306 = XSCVDPHP | |
| { 2305, 3, 1, 4, 411, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2305 = XSCPSGNQP | |
| { 2304, 3, 1, 4, 124, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo319 }, // Inst #2304 = XSCPSGNDP | |
| { 2303, 3, 1, 4, 168, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo304 }, // Inst #2303 = XSCMPUQP | |
| { 2302, 3, 1, 4, 113, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo322 }, // Inst #2302 = XSCMPUDP | |
| { 2301, 3, 1, 4, 168, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo304 }, // Inst #2301 = XSCMPOQP | |
| { 2300, 3, 1, 4, 113, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x0ULL, ImplicitList42, OperandInfo322 }, // Inst #2300 = XSCMPODP | |
| { 2299, 3, 1, 4, 357, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2299 = XSCMPGTQP | |
| { 2298, 3, 1, 4, 113, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo321 }, // Inst #2298 = XSCMPGTDP | |
| { 2297, 3, 1, 4, 357, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2297 = XSCMPGEQP | |
| { 2296, 3, 1, 4, 113, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo321 }, // Inst #2296 = XSCMPGEDP | |
| { 2295, 3, 1, 4, 168, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo304 }, // Inst #2295 = XSCMPEXPQP | |
| { 2294, 3, 1, 4, 113, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo322 }, // Inst #2294 = XSCMPEXPDP | |
| { 2293, 3, 1, 4, 357, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2293 = XSCMPEQQP | |
| { 2292, 3, 1, 4, 113, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo321 }, // Inst #2292 = XSCMPEQDP | |
| { 2291, 3, 1, 4, 326, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo320 }, // Inst #2291 = XSADDSP | |
| { 2290, 3, 1, 4, 342, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2290 = XSADDQPO | |
| { 2289, 3, 1, 4, 342, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2289 = XSADDQP | |
| { 2288, 3, 1, 4, 326, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList42, OperandInfo319 }, // Inst #2288 = XSADDDP | |
| { 2287, 2, 1, 4, 402, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2287 = XSABSQP | |
| { 2286, 2, 1, 4, 401, 1, 0, 0, 0x0ULL, ImplicitList42, OperandInfo318 }, // Inst #2286 = XSABSDP | |
| { 2285, 3, 1, 4, 404, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList1, OperandInfo65 }, // Inst #2285 = XOR_rec | |
| { 2284, 3, 1, 4, 404, 0, 0, 0, 0x8ULL, nullptr, OperandInfo52 }, // Inst #2284 = XORIS8 | |
| { 2283, 3, 1, 4, 404, 0, 0, 0, 0x8ULL, nullptr, OperandInfo53 }, // Inst #2283 = XORIS | |
| { 2282, 3, 1, 4, 404, 0, 0, 0, 0x8ULL, nullptr, OperandInfo52 }, // Inst #2282 = XORI8 | |
| { 2281, 3, 1, 4, 404, 0, 0, 0, 0x8ULL, nullptr, OperandInfo53 }, // Inst #2281 = XORI | |
| { 2280, 3, 1, 4, 404, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList1, OperandInfo67 }, // Inst #2280 = XOR8_rec | |
| { 2279, 3, 1, 4, 404, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo67 }, // Inst #2279 = XOR8 | |
| { 2278, 3, 1, 4, 404, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo65 }, // Inst #2278 = XOR | |
| { 2277, 1, 0, 4, 311, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo3 }, // Inst #2277 = WRTEEI | |
| { 2276, 1, 0, 4, 311, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo189 }, // Inst #2276 = WRTEE | |
| { 2275, 1, 0, 4, 127, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo3 }, // Inst #2275 = WAIT | |
| { 2274, 1, 1, 4, 459, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, OperandInfo197 }, // Inst #2274 = V_SETALLONESH | |
| { 2273, 1, 1, 4, 459, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, OperandInfo197 }, // Inst #2273 = V_SETALLONESB | |
| { 2272, 1, 1, 4, 459, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, OperandInfo197 }, // Inst #2272 = V_SETALLONES | |
| { 2271, 1, 1, 4, 390, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, OperandInfo197 }, // Inst #2271 = V_SET0H | |
| { 2270, 1, 1, 4, 390, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, OperandInfo197 }, // Inst #2270 = V_SET0B | |
| { 2269, 1, 1, 4, 390, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, OperandInfo197 }, // Inst #2269 = V_SET0 | |
| { 2268, 3, 1, 4, 390, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2268 = VXOR | |
| { 2267, 2, 1, 4, 463, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2267 = VUPKLSW | |
| { 2266, 2, 1, 4, 463, 0, 0, 0, 0x28ULL, nullptr, OperandInfo96 }, // Inst #2266 = VUPKLSH | |
| { 2265, 2, 1, 4, 463, 0, 0, 0, 0x28ULL, nullptr, OperandInfo96 }, // Inst #2265 = VUPKLSB | |
| { 2264, 2, 1, 4, 463, 0, 0, 0, 0x28ULL, nullptr, OperandInfo96 }, // Inst #2264 = VUPKLPX | |
| { 2263, 2, 1, 4, 463, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2263 = VUPKHSW | |
| { 2262, 2, 1, 4, 463, 0, 0, 0, 0x28ULL, nullptr, OperandInfo96 }, // Inst #2262 = VUPKHSH | |
| { 2261, 2, 1, 4, 463, 0, 0, 0, 0x28ULL, nullptr, OperandInfo96 }, // Inst #2261 = VUPKHSB | |
| { 2260, 2, 1, 4, 463, 0, 0, 0, 0x28ULL, nullptr, OperandInfo96 }, // Inst #2260 = VUPKHPX | |
| { 2259, 3, 1, 4, 471, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2259 = VSUMSWS | |
| { 2258, 3, 1, 4, 498, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2258 = VSUM4UBS | |
| { 2257, 3, 1, 4, 498, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2257 = VSUM4SHS | |
| { 2256, 3, 1, 4, 498, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2256 = VSUM4SBS | |
| { 2255, 3, 1, 4, 498, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2255 = VSUM2SWS | |
| { 2254, 3, 1, 4, 376, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2254 = VSUBUWS | |
| { 2253, 3, 1, 4, 410, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2253 = VSUBUWM | |
| { 2252, 3, 1, 4, 356, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2252 = VSUBUQM | |
| { 2251, 3, 1, 4, 376, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2251 = VSUBUHS | |
| { 2250, 3, 1, 4, 410, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2250 = VSUBUHM | |
| { 2249, 3, 1, 4, 410, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2249 = VSUBUDM | |
| { 2248, 3, 1, 4, 376, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2248 = VSUBUBS | |
| { 2247, 3, 1, 4, 410, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2247 = VSUBUBM | |
| { 2246, 3, 1, 4, 376, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2246 = VSUBSWS | |
| { 2245, 3, 1, 4, 376, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2245 = VSUBSHS | |
| { 2244, 3, 1, 4, 376, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2244 = VSUBSBS | |
| { 2243, 3, 1, 4, 325, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2243 = VSUBFP | |
| { 2242, 4, 1, 4, 359, 0, 0, 0, 0x0ULL, nullptr, OperandInfo300 }, // Inst #2242 = VSUBEUQM | |
| { 2241, 4, 1, 4, 359, 0, 0, 0, 0x0ULL, nullptr, OperandInfo300 }, // Inst #2241 = VSUBECUQ | |
| { 2240, 3, 1, 4, 376, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2240 = VSUBCUW | |
| { 2239, 3, 1, 4, 355, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2239 = VSUBCUQ | |
| { 2238, 2, 1, 4, 429, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList23, OperandInfo96 }, // Inst #2238 = VSTRIHR_rec | |
| { 2237, 2, 1, 4, 461, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2237 = VSTRIHR | |
| { 2236, 2, 1, 4, 429, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList23, OperandInfo96 }, // Inst #2236 = VSTRIHL_rec | |
| { 2235, 2, 1, 4, 461, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2235 = VSTRIHL | |
| { 2234, 2, 1, 4, 429, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList23, OperandInfo96 }, // Inst #2234 = VSTRIBR_rec | |
| { 2233, 2, 1, 4, 461, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2233 = VSTRIBR | |
| { 2232, 2, 1, 4, 429, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList23, OperandInfo96 }, // Inst #2232 = VSTRIBL_rec | |
| { 2231, 2, 1, 4, 461, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2231 = VSTRIBL | |
| { 2230, 3, 1, 4, 411, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2230 = VSRW | |
| { 2229, 3, 1, 4, 466, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2229 = VSRV | |
| { 2228, 3, 1, 4, 384, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2228 = VSRQ | |
| { 2227, 3, 1, 4, 466, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2227 = VSRO | |
| { 2226, 3, 1, 4, 411, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2226 = VSRH | |
| { 2225, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo93 }, // Inst #2225 = VSRDBI | |
| { 2224, 3, 1, 4, 410, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2224 = VSRD | |
| { 2223, 3, 1, 4, 411, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2223 = VSRB | |
| { 2222, 3, 1, 4, 411, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2222 = VSRAW | |
| { 2221, 3, 1, 4, 384, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2221 = VSRAQ | |
| { 2220, 3, 1, 4, 411, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2220 = VSRAH | |
| { 2219, 3, 1, 4, 410, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2219 = VSRAD | |
| { 2218, 3, 1, 4, 411, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2218 = VSRAB | |
| { 2217, 3, 1, 4, 466, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2217 = VSR | |
| { 2216, 3, 1, 4, 469, 0, 0, 0, 0x28ULL, nullptr, OperandInfo301 }, // Inst #2216 = VSPLTW | |
| { 2215, 2, 1, 4, 458, 0, 0, 0, 0x28ULL, nullptr, OperandInfo211 }, // Inst #2215 = VSPLTISW | |
| { 2214, 2, 1, 4, 464, 0, 0, 0, 0x28ULL, nullptr, OperandInfo211 }, // Inst #2214 = VSPLTISH | |
| { 2213, 2, 1, 4, 464, 0, 0, 0, 0x28ULL, nullptr, OperandInfo211 }, // Inst #2213 = VSPLTISB | |
| { 2212, 3, 1, 4, 469, 0, 0, 0, 0x28ULL, nullptr, OperandInfo317 }, // Inst #2212 = VSPLTHs | |
| { 2211, 3, 1, 4, 469, 0, 0, 0, 0x28ULL, nullptr, OperandInfo301 }, // Inst #2211 = VSPLTH | |
| { 2210, 3, 1, 4, 469, 0, 0, 0, 0x28ULL, nullptr, OperandInfo317 }, // Inst #2210 = VSPLTBs | |
| { 2209, 3, 1, 4, 469, 0, 0, 0, 0x28ULL, nullptr, OperandInfo301 }, // Inst #2209 = VSPLTB | |
| { 2208, 3, 1, 4, 411, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2208 = VSLW | |
| { 2207, 3, 1, 4, 466, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2207 = VSLV | |
| { 2206, 3, 1, 4, 384, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2206 = VSLQ | |
| { 2205, 3, 1, 4, 466, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2205 = VSLO | |
| { 2204, 3, 1, 4, 411, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2204 = VSLH | |
| { 2203, 4, 1, 4, 166, 0, 0, 0, 0x28ULL, nullptr, OperandInfo93 }, // Inst #2203 = VSLDOI | |
| { 2202, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo93 }, // Inst #2202 = VSLDBI | |
| { 2201, 3, 1, 4, 410, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2201 = VSLD | |
| { 2200, 3, 1, 4, 411, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2200 = VSLB | |
| { 2199, 3, 1, 4, 466, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2199 = VSL | |
| { 2198, 4, 1, 4, 383, 0, 0, 0, 0x0ULL, nullptr, OperandInfo316 }, // Inst #2198 = VSHASIGMAW | |
| { 2197, 4, 1, 4, 383, 0, 0, 0, 0x0ULL, nullptr, OperandInfo316 }, // Inst #2197 = VSHASIGMAD | |
| { 2196, 4, 1, 4, 102, 0, 0, 0, 0x28ULL, nullptr, OperandInfo300 }, // Inst #2196 = VSEL | |
| { 2195, 2, 1, 4, 337, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2195 = VSBOX | |
| { 2194, 2, 1, 4, 319, 0, 0, 0, 0x28ULL, nullptr, OperandInfo96 }, // Inst #2194 = VRSQRTEFP | |
| { 2193, 3, 1, 4, 411, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2193 = VRLWNM | |
| { 2192, 4, 1, 4, 102, 0, 0, 0, 0x0ULL, nullptr, OperandInfo315 }, // Inst #2192 = VRLWMI | |
| { 2191, 3, 1, 4, 411, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2191 = VRLW | |
| { 2190, 3, 1, 4, 384, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2190 = VRLQNM | |
| { 2189, 4, 1, 4, 385, 0, 0, 0, 0x0ULL, nullptr, OperandInfo315 }, // Inst #2189 = VRLQMI | |
| { 2188, 3, 1, 4, 384, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2188 = VRLQ | |
| { 2187, 3, 1, 4, 411, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2187 = VRLH | |
| { 2186, 3, 1, 4, 411, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2186 = VRLDNM | |
| { 2185, 4, 1, 4, 102, 0, 0, 0, 0x0ULL, nullptr, OperandInfo315 }, // Inst #2185 = VRLDMI | |
| { 2184, 3, 1, 4, 411, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2184 = VRLD | |
| { 2183, 3, 1, 4, 411, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2183 = VRLB | |
| { 2182, 2, 1, 4, 319, 0, 0, 0, 0x28ULL, nullptr, OperandInfo96 }, // Inst #2182 = VRFIZ | |
| { 2181, 2, 1, 4, 319, 0, 0, 0, 0x28ULL, nullptr, OperandInfo96 }, // Inst #2181 = VRFIP | |
| { 2180, 2, 1, 4, 319, 0, 0, 0, 0x28ULL, nullptr, OperandInfo96 }, // Inst #2180 = VRFIN | |
| { 2179, 2, 1, 4, 319, 0, 0, 0, 0x28ULL, nullptr, OperandInfo96 }, // Inst #2179 = VRFIM | |
| { 2178, 2, 1, 4, 319, 0, 0, 0, 0x28ULL, nullptr, OperandInfo96 }, // Inst #2178 = VREFP | |
| { 2177, 2, 1, 4, 366, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2177 = VPRTYBW | |
| { 2176, 2, 1, 4, 462, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2176 = VPRTYBQ | |
| { 2175, 2, 1, 4, 366, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2175 = VPRTYBD | |
| { 2174, 2, 1, 4, 366, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2174 = VPOPCNTW | |
| { 2173, 2, 1, 4, 367, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2173 = VPOPCNTH | |
| { 2172, 2, 1, 4, 366, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2172 = VPOPCNTD | |
| { 2171, 2, 1, 4, 367, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2171 = VPOPCNTB | |
| { 2170, 3, 1, 4, 288, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2170 = VPMSUMW | |
| { 2169, 3, 1, 4, 288, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2169 = VPMSUMH | |
| { 2168, 3, 1, 4, 288, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2168 = VPMSUMD | |
| { 2167, 3, 1, 4, 288, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2167 = VPMSUMB | |
| { 2166, 3, 1, 4, 466, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2166 = VPKUWUS | |
| { 2165, 3, 1, 4, 466, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2165 = VPKUWUM | |
| { 2164, 3, 1, 4, 466, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2164 = VPKUHUS | |
| { 2163, 3, 1, 4, 466, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2163 = VPKUHUM | |
| { 2162, 3, 1, 4, 466, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2162 = VPKUDUS | |
| { 2161, 3, 1, 4, 466, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2161 = VPKUDUM | |
| { 2160, 3, 1, 4, 466, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2160 = VPKSWUS | |
| { 2159, 3, 1, 4, 466, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2159 = VPKSWSS | |
| { 2158, 3, 1, 4, 466, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2158 = VPKSHUS | |
| { 2157, 3, 1, 4, 466, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2157 = VPKSHSS | |
| { 2156, 3, 1, 4, 466, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2156 = VPKSDUS | |
| { 2155, 3, 1, 4, 466, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2155 = VPKSDSS | |
| { 2154, 3, 1, 4, 466, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2154 = VPKPX | |
| { 2153, 3, 1, 4, 339, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2153 = VPEXTD | |
| { 2152, 4, 1, 4, 166, 0, 0, 0, 0x0ULL, nullptr, OperandInfo300 }, // Inst #2152 = VPERMXOR | |
| { 2151, 4, 1, 4, 166, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo300 }, // Inst #2151 = VPERMR | |
| { 2150, 4, 1, 4, 166, 0, 0, 0, 0x28ULL, nullptr, OperandInfo300 }, // Inst #2150 = VPERM | |
| { 2149, 3, 1, 4, 339, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2149 = VPDEPD | |
| { 2148, 3, 1, 4, 410, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2148 = VORC | |
| { 2147, 3, 1, 4, 411, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2147 = VOR | |
| { 2146, 3, 1, 4, 411, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2146 = VNOR | |
| { 2145, 4, 1, 4, 328, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo300 }, // Inst #2145 = VNMSUBFP | |
| { 2144, 2, 1, 4, 399, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2144 = VNEGW | |
| { 2143, 2, 1, 4, 399, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2143 = VNEGD | |
| { 2142, 3, 1, 4, 288, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2142 = VNCIPHERLAST | |
| { 2141, 3, 1, 4, 288, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2141 = VNCIPHER | |
| { 2140, 3, 1, 4, 410, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2140 = VNAND | |
| { 2139, 3, 1, 4, 147, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2139 = VMULUWM | |
| { 2138, 3, 1, 4, 498, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2138 = VMULOUW | |
| { 2137, 3, 1, 4, 498, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2137 = VMULOUH | |
| { 2136, 3, 1, 4, 499, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2136 = VMULOUD | |
| { 2135, 3, 1, 4, 498, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2135 = VMULOUB | |
| { 2134, 3, 1, 4, 498, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2134 = VMULOSW | |
| { 2133, 3, 1, 4, 498, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2133 = VMULOSH | |
| { 2132, 3, 1, 4, 499, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2132 = VMULOSD | |
| { 2131, 3, 1, 4, 498, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2131 = VMULOSB | |
| { 2130, 3, 1, 4, 457, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2130 = VMULLD | |
| { 2129, 3, 1, 4, 499, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2129 = VMULHUW | |
| { 2128, 3, 1, 4, 457, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2128 = VMULHUD | |
| { 2127, 3, 1, 4, 499, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2127 = VMULHSW | |
| { 2126, 3, 1, 4, 457, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2126 = VMULHSD | |
| { 2125, 3, 1, 4, 498, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2125 = VMULEUW | |
| { 2124, 3, 1, 4, 498, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2124 = VMULEUH | |
| { 2123, 3, 1, 4, 499, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2123 = VMULEUD | |
| { 2122, 3, 1, 4, 498, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2122 = VMULEUB | |
| { 2121, 3, 1, 4, 498, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2121 = VMULESW | |
| { 2120, 3, 1, 4, 498, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2120 = VMULESH | |
| { 2119, 3, 1, 4, 499, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2119 = VMULESD | |
| { 2118, 3, 1, 4, 498, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2118 = VMULESB | |
| { 2117, 2, 1, 4, 354, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo96 }, // Inst #2117 = VMUL10UQ | |
| { 2116, 3, 1, 4, 355, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2116 = VMUL10EUQ | |
| { 2115, 3, 1, 4, 355, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2115 = VMUL10ECUQ | |
| { 2114, 2, 1, 4, 354, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo96 }, // Inst #2114 = VMUL10CUQ | |
| { 2113, 4, 1, 4, 146, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL, nullptr, OperandInfo300 }, // Inst #2113 = VMSUMUHS | |
| { 2112, 4, 1, 4, 146, 0, 0, 0, 0x28ULL, nullptr, OperandInfo300 }, // Inst #2112 = VMSUMUHM | |
| { 2111, 4, 1, 4, 146, 0, 0, 0, 0x0ULL, nullptr, OperandInfo300 }, // Inst #2111 = VMSUMUDM | |
| { 2110, 4, 1, 4, 146, 0, 0, 0, 0x28ULL, nullptr, OperandInfo300 }, // Inst #2110 = VMSUMUBM | |
| { 2109, 4, 1, 4, 146, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL, nullptr, OperandInfo300 }, // Inst #2109 = VMSUMSHS | |
| { 2108, 4, 1, 4, 146, 0, 0, 0, 0x28ULL, nullptr, OperandInfo300 }, // Inst #2108 = VMSUMSHM | |
| { 2107, 4, 1, 4, 146, 0, 0, 0, 0x28ULL, nullptr, OperandInfo300 }, // Inst #2107 = VMSUMMBM | |
| { 2106, 4, 1, 4, 500, 0, 0, 0, 0x0ULL, nullptr, OperandInfo300 }, // Inst #2106 = VMSUMCUD | |
| { 2105, 3, 1, 4, 411, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2105 = VMRGOW | |
| { 2104, 3, 1, 4, 466, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2104 = VMRGLW | |
| { 2103, 3, 1, 4, 466, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2103 = VMRGLH | |
| { 2102, 3, 1, 4, 466, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2102 = VMRGLB | |
| { 2101, 3, 1, 4, 466, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2101 = VMRGHW | |
| { 2100, 3, 1, 4, 466, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2100 = VMRGHH | |
| { 2099, 3, 1, 4, 466, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #2099 = VMRGHB | |
| { 2098, 3, 1, 4, 411, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2098 = VMRGEW | |
| { 2097, 3, 1, 4, 351, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2097 = VMODUW | |
| { 2096, 3, 1, 4, 346, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2096 = VMODUQ | |
| { 2095, 3, 1, 4, 349, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2095 = VMODUD | |
| { 2094, 3, 1, 4, 351, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2094 = VMODSW | |
| { 2093, 3, 1, 4, 346, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2093 = VMODSQ | |
| { 2092, 3, 1, 4, 349, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2092 = VMODSD | |
| { 2091, 4, 1, 4, 146, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo300 }, // Inst #2091 = VMLADDUHM | |
| { 2090, 3, 1, 4, 412, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2090 = VMINUW | |
| { 2089, 3, 1, 4, 412, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2089 = VMINUH | |
| { 2088, 3, 1, 4, 412, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2088 = VMINUD | |
| { 2087, 3, 1, 4, 412, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2087 = VMINUB | |
| { 2086, 3, 1, 4, 412, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2086 = VMINSW | |
| { 2085, 3, 1, 4, 412, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2085 = VMINSH | |
| { 2084, 3, 1, 4, 412, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2084 = VMINSD | |
| { 2083, 3, 1, 4, 412, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2083 = VMINSB | |
| { 2082, 3, 1, 4, 376, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2082 = VMINFP | |
| { 2081, 4, 1, 4, 146, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL, nullptr, OperandInfo300 }, // Inst #2081 = VMHRADDSHS | |
| { 2080, 4, 1, 4, 146, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28ULL, nullptr, OperandInfo300 }, // Inst #2080 = VMHADDSHS | |
| { 2079, 3, 1, 4, 412, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2079 = VMAXUW | |
| { 2078, 3, 1, 4, 412, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2078 = VMAXUH | |
| { 2077, 3, 1, 4, 412, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2077 = VMAXUD | |
| { 2076, 3, 1, 4, 412, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2076 = VMAXUB | |
| { 2075, 3, 1, 4, 412, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2075 = VMAXSW | |
| { 2074, 3, 1, 4, 412, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2074 = VMAXSH | |
| { 2073, 3, 1, 4, 412, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2073 = VMAXSD | |
| { 2072, 3, 1, 4, 412, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2072 = VMAXSB | |
| { 2071, 3, 1, 4, 376, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #2071 = VMAXFP | |
| { 2070, 4, 1, 4, 328, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo300 }, // Inst #2070 = VMADDFP | |
| { 2069, 2, 1, 4, 319, 0, 0, 0, 0x28ULL, nullptr, OperandInfo96 }, // Inst #2069 = VLOGEFP | |
| { 2068, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo310 }, // Inst #2068 = VINSWVRX | |
| { 2067, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo310 }, // Inst #2067 = VINSWVLX | |
| { 2066, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo309 }, // Inst #2066 = VINSWRX | |
| { 2065, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo309 }, // Inst #2065 = VINSWLX | |
| { 2064, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo314 }, // Inst #2064 = VINSW | |
| { 2063, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo310 }, // Inst #2063 = VINSHVRX | |
| { 2062, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo310 }, // Inst #2062 = VINSHVLX | |
| { 2061, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo309 }, // Inst #2061 = VINSHRX | |
| { 2060, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo309 }, // Inst #2060 = VINSHLX | |
| { 2059, 3, 1, 4, 468, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo301 }, // Inst #2059 = VINSERTW | |
| { 2058, 4, 1, 4, 167, 0, 0, 0, 0x0ULL, nullptr, OperandInfo313 }, // Inst #2058 = VINSERTH | |
| { 2057, 3, 1, 4, 468, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo301 }, // Inst #2057 = VINSERTD | |
| { 2056, 4, 1, 4, 167, 0, 0, 0, 0x0ULL, nullptr, OperandInfo313 }, // Inst #2056 = VINSERTB | |
| { 2055, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo312 }, // Inst #2055 = VINSDRX | |
| { 2054, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo312 }, // Inst #2054 = VINSDLX | |
| { 2053, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo311 }, // Inst #2053 = VINSD | |
| { 2052, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo310 }, // Inst #2052 = VINSBVRX | |
| { 2051, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo310 }, // Inst #2051 = VINSBVLX | |
| { 2050, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo309 }, // Inst #2050 = VINSBRX | |
| { 2049, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo309 }, // Inst #2049 = VINSBLX | |
| { 2048, 3, 1, 4, 339, 0, 0, 0, 0x0ULL, nullptr, OperandInfo305 }, // Inst #2048 = VGNB | |
| { 2047, 2, 1, 4, 463, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2047 = VGBBD | |
| { 2046, 3, 1, 4, 468, 0, 0, 0, 0x200ULL, nullptr, OperandInfo308 }, // Inst #2046 = VEXTUWRX | |
| { 2045, 3, 1, 4, 468, 0, 0, 0, 0x200ULL, nullptr, OperandInfo308 }, // Inst #2045 = VEXTUWLX | |
| { 2044, 3, 1, 4, 468, 0, 0, 0, 0x200ULL, nullptr, OperandInfo308 }, // Inst #2044 = VEXTUHRX | |
| { 2043, 3, 1, 4, 468, 0, 0, 0, 0x200ULL, nullptr, OperandInfo308 }, // Inst #2043 = VEXTUHLX | |
| { 2042, 3, 1, 4, 468, 0, 0, 0, 0x200ULL, nullptr, OperandInfo308 }, // Inst #2042 = VEXTUBRX | |
| { 2041, 3, 1, 4, 468, 0, 0, 0, 0x200ULL, nullptr, OperandInfo308 }, // Inst #2041 = VEXTUBLX | |
| { 2040, 2, 1, 4, 399, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo307 }, // Inst #2040 = VEXTSW2Ds | |
| { 2039, 2, 1, 4, 399, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2039 = VEXTSW2D | |
| { 2038, 2, 1, 4, 399, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo307 }, // Inst #2038 = VEXTSH2Ws | |
| { 2037, 2, 1, 4, 399, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2037 = VEXTSH2W | |
| { 2036, 2, 1, 4, 399, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo307 }, // Inst #2036 = VEXTSH2Ds | |
| { 2035, 2, 1, 4, 399, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2035 = VEXTSH2D | |
| { 2034, 2, 1, 4, 400, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2034 = VEXTSD2Q | |
| { 2033, 2, 1, 4, 399, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo307 }, // Inst #2033 = VEXTSB2Ws | |
| { 2032, 2, 1, 4, 399, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2032 = VEXTSB2W | |
| { 2031, 2, 1, 4, 399, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo307 }, // Inst #2031 = VEXTSB2Ds | |
| { 2030, 2, 1, 4, 399, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2030 = VEXTSB2D | |
| { 2029, 2, 1, 4, 364, 0, 0, 0, 0x200ULL, nullptr, OperandInfo303 }, // Inst #2029 = VEXTRACTWM | |
| { 2028, 3, 1, 4, 468, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo301 }, // Inst #2028 = VEXTRACTUW | |
| { 2027, 3, 1, 4, 468, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo301 }, // Inst #2027 = VEXTRACTUH | |
| { 2026, 3, 1, 4, 468, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo301 }, // Inst #2026 = VEXTRACTUB | |
| { 2025, 2, 1, 4, 364, 0, 0, 0, 0x0ULL, nullptr, OperandInfo303 }, // Inst #2025 = VEXTRACTQM | |
| { 2024, 2, 1, 4, 364, 0, 0, 0, 0x200ULL, nullptr, OperandInfo303 }, // Inst #2024 = VEXTRACTHM | |
| { 2023, 2, 1, 4, 364, 0, 0, 0, 0x200ULL, nullptr, OperandInfo303 }, // Inst #2023 = VEXTRACTDM | |
| { 2022, 3, 1, 4, 468, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo301 }, // Inst #2022 = VEXTRACTD | |
| { 2021, 2, 1, 4, 364, 0, 0, 0, 0x200ULL, nullptr, OperandInfo303 }, // Inst #2021 = VEXTRACTBM | |
| { 2020, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo306 }, // Inst #2020 = VEXTDUWVRX | |
| { 2019, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo306 }, // Inst #2019 = VEXTDUWVLX | |
| { 2018, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo306 }, // Inst #2018 = VEXTDUHVRX | |
| { 2017, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo306 }, // Inst #2017 = VEXTDUHVLX | |
| { 2016, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo306 }, // Inst #2016 = VEXTDUBVRX | |
| { 2015, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo306 }, // Inst #2015 = VEXTDUBVLX | |
| { 2014, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo306 }, // Inst #2014 = VEXTDDVRX | |
| { 2013, 4, 1, 4, 470, 0, 0, 0, 0x0ULL, nullptr, OperandInfo306 }, // Inst #2013 = VEXTDDVLX | |
| { 2012, 2, 1, 4, 329, 0, 0, 0, 0x28ULL, nullptr, OperandInfo96 }, // Inst #2012 = VEXPTEFP | |
| { 2011, 2, 1, 4, 364, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2011 = VEXPANDWM | |
| { 2010, 2, 1, 4, 364, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2010 = VEXPANDQM | |
| { 2009, 2, 1, 4, 364, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2009 = VEXPANDHM | |
| { 2008, 2, 1, 4, 364, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2008 = VEXPANDDM | |
| { 2007, 2, 1, 4, 364, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #2007 = VEXPANDBM | |
| { 2006, 3, 1, 4, 410, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo95 }, // Inst #2006 = VEQV | |
| { 2005, 3, 1, 4, 350, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2005 = VDIVUW | |
| { 2004, 3, 1, 4, 345, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2004 = VDIVUQ | |
| { 2003, 3, 1, 4, 348, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2003 = VDIVUD | |
| { 2002, 3, 1, 4, 350, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2002 = VDIVSW | |
| { 2001, 3, 1, 4, 345, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2001 = VDIVSQ | |
| { 2000, 3, 1, 4, 348, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #2000 = VDIVSD | |
| { 1999, 3, 1, 4, 353, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #1999 = VDIVEUW | |
| { 1998, 3, 1, 4, 345, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #1998 = VDIVEUQ | |
| { 1997, 3, 1, 4, 352, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #1997 = VDIVEUD | |
| { 1996, 3, 1, 4, 353, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #1996 = VDIVESW | |
| { 1995, 3, 1, 4, 345, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #1995 = VDIVESQ | |
| { 1994, 3, 1, 4, 352, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #1994 = VDIVESD | |
| { 1993, 2, 1, 4, 366, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #1993 = VCTZW | |
| { 1992, 2, 1, 4, 462, 0, 0, 0, 0x0ULL, nullptr, OperandInfo303 }, // Inst #1992 = VCTZLSBB | |
| { 1991, 2, 1, 4, 366, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #1991 = VCTZH | |
| { 1990, 3, 1, 4, 339, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #1990 = VCTZDM | |
| { 1989, 2, 1, 4, 366, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #1989 = VCTZD | |
| { 1988, 2, 1, 4, 366, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #1988 = VCTZB | |
| { 1987, 2, 1, 4, 319, 0, 0, 0, 0x28ULL, nullptr, OperandInfo96 }, // Inst #1987 = VCTUXS_0 | |
| { 1986, 3, 1, 4, 319, 0, 0, 0, 0x28ULL, nullptr, OperandInfo301 }, // Inst #1986 = VCTUXS | |
| { 1985, 2, 1, 4, 319, 0, 0, 0, 0x28ULL, nullptr, OperandInfo96 }, // Inst #1985 = VCTSXS_0 | |
| { 1984, 3, 1, 4, 319, 0, 0, 0, 0x28ULL, nullptr, OperandInfo301 }, // Inst #1984 = VCTSXS | |
| { 1983, 3, 1, 4, 379, 0, 0, 0, 0x0ULL, nullptr, OperandInfo305 }, // Inst #1983 = VCNTMBW | |
| { 1982, 3, 1, 4, 379, 0, 0, 0, 0x0ULL, nullptr, OperandInfo305 }, // Inst #1982 = VCNTMBH | |
| { 1981, 3, 1, 4, 379, 0, 0, 0, 0x0ULL, nullptr, OperandInfo305 }, // Inst #1981 = VCNTMBD | |
| { 1980, 3, 1, 4, 379, 0, 0, 0, 0x0ULL, nullptr, OperandInfo305 }, // Inst #1980 = VCNTMBB | |
| { 1979, 3, 1, 4, 379, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo304 }, // Inst #1979 = VCMPUQ | |
| { 1978, 3, 1, 4, 379, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo304 }, // Inst #1978 = VCMPSQ | |
| { 1977, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1977 = VCMPNEZW_rec | |
| { 1976, 3, 1, 4, 142, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1976 = VCMPNEZW | |
| { 1975, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1975 = VCMPNEZH_rec | |
| { 1974, 3, 1, 4, 142, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1974 = VCMPNEZH | |
| { 1973, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1973 = VCMPNEZB_rec | |
| { 1972, 3, 1, 4, 142, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1972 = VCMPNEZB | |
| { 1971, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1971 = VCMPNEW_rec | |
| { 1970, 3, 1, 4, 142, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1970 = VCMPNEW | |
| { 1969, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1969 = VCMPNEH_rec | |
| { 1968, 3, 1, 4, 142, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1968 = VCMPNEH | |
| { 1967, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1967 = VCMPNEB_rec | |
| { 1966, 3, 1, 4, 142, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1966 = VCMPNEB | |
| { 1965, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1965 = VCMPGTUW_rec | |
| { 1964, 3, 1, 4, 142, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1964 = VCMPGTUW | |
| { 1963, 3, 1, 4, 378, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1963 = VCMPGTUQ_rec | |
| { 1962, 3, 1, 4, 378, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1962 = VCMPGTUQ | |
| { 1961, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1961 = VCMPGTUH_rec | |
| { 1960, 3, 1, 4, 142, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1960 = VCMPGTUH | |
| { 1959, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1959 = VCMPGTUD_rec | |
| { 1958, 3, 1, 4, 142, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1958 = VCMPGTUD | |
| { 1957, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1957 = VCMPGTUB_rec | |
| { 1956, 3, 1, 4, 142, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1956 = VCMPGTUB | |
| { 1955, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1955 = VCMPGTSW_rec | |
| { 1954, 3, 1, 4, 142, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1954 = VCMPGTSW | |
| { 1953, 3, 1, 4, 378, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1953 = VCMPGTSQ_rec | |
| { 1952, 3, 1, 4, 378, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1952 = VCMPGTSQ | |
| { 1951, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1951 = VCMPGTSH_rec | |
| { 1950, 3, 1, 4, 142, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1950 = VCMPGTSH | |
| { 1949, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1949 = VCMPGTSD_rec | |
| { 1948, 3, 1, 4, 142, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1948 = VCMPGTSD | |
| { 1947, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1947 = VCMPGTSB_rec | |
| { 1946, 3, 1, 4, 142, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1946 = VCMPGTSB | |
| { 1945, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1945 = VCMPGTFP_rec | |
| { 1944, 3, 1, 4, 377, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1944 = VCMPGTFP | |
| { 1943, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1943 = VCMPGEFP_rec | |
| { 1942, 3, 1, 4, 377, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1942 = VCMPGEFP | |
| { 1941, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1941 = VCMPEQUW_rec | |
| { 1940, 3, 1, 4, 142, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1940 = VCMPEQUW | |
| { 1939, 3, 1, 4, 378, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1939 = VCMPEQUQ_rec | |
| { 1938, 3, 1, 4, 378, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1938 = VCMPEQUQ | |
| { 1937, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1937 = VCMPEQUH_rec | |
| { 1936, 3, 1, 4, 142, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1936 = VCMPEQUH | |
| { 1935, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1935 = VCMPEQUD_rec | |
| { 1934, 3, 1, 4, 142, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1934 = VCMPEQUD | |
| { 1933, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1933 = VCMPEQUB_rec | |
| { 1932, 3, 1, 4, 142, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1932 = VCMPEQUB | |
| { 1931, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1931 = VCMPEQFP_rec | |
| { 1930, 3, 1, 4, 377, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1930 = VCMPEQFP | |
| { 1929, 3, 1, 4, 377, 0, 1, 0, 0x28ULL, ImplicitList23, OperandInfo95 }, // Inst #1929 = VCMPBFP_rec | |
| { 1928, 3, 1, 4, 377, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1928 = VCMPBFP | |
| { 1927, 2, 1, 4, 366, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #1927 = VCLZW | |
| { 1926, 2, 1, 4, 462, 0, 0, 0, 0x0ULL, nullptr, OperandInfo303 }, // Inst #1926 = VCLZLSBB | |
| { 1925, 2, 1, 4, 366, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #1925 = VCLZH | |
| { 1924, 3, 1, 4, 339, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #1924 = VCLZDM | |
| { 1923, 2, 1, 4, 366, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #1923 = VCLZD | |
| { 1922, 2, 1, 4, 366, 0, 0, 0, 0x0ULL, nullptr, OperandInfo96 }, // Inst #1922 = VCLZB | |
| { 1921, 3, 1, 4, 467, 0, 0, 0, 0x0ULL, nullptr, OperandInfo302 }, // Inst #1921 = VCLRRB | |
| { 1920, 3, 1, 4, 467, 0, 0, 0, 0x0ULL, nullptr, OperandInfo302 }, // Inst #1920 = VCLRLB | |
| { 1919, 3, 1, 4, 288, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #1919 = VCIPHERLAST | |
| { 1918, 3, 1, 4, 288, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #1918 = VCIPHER | |
| { 1917, 2, 1, 4, 319, 0, 0, 0, 0x28ULL, nullptr, OperandInfo96 }, // Inst #1917 = VCFUX_0 | |
| { 1916, 3, 1, 4, 319, 0, 0, 0, 0x28ULL, nullptr, OperandInfo301 }, // Inst #1916 = VCFUX | |
| { 1915, 3, 1, 4, 339, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #1915 = VCFUGED | |
| { 1914, 2, 1, 4, 319, 0, 0, 0, 0x28ULL, nullptr, OperandInfo96 }, // Inst #1914 = VCFSX_0 | |
| { 1913, 3, 1, 4, 319, 0, 0, 0, 0x28ULL, nullptr, OperandInfo301 }, // Inst #1913 = VCFSX | |
| { 1912, 3, 1, 4, 466, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #1912 = VBPERMQ | |
| { 1911, 3, 1, 4, 144, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #1911 = VBPERMD | |
| { 1910, 3, 1, 4, 376, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #1910 = VAVGUW | |
| { 1909, 3, 1, 4, 376, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #1909 = VAVGUH | |
| { 1908, 3, 1, 4, 376, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #1908 = VAVGUB | |
| { 1907, 3, 1, 4, 376, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #1907 = VAVGSW | |
| { 1906, 3, 1, 4, 376, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #1906 = VAVGSH | |
| { 1905, 3, 1, 4, 376, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #1905 = VAVGSB | |
| { 1904, 3, 1, 4, 411, 0, 0, 0, 0x28ULL, nullptr, OperandInfo95 }, // Inst #1904 = VANDC | |
| { 1903, 3, 1, 4, 411, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #1903 = VAND | |
| { 1902, 3, 1, 4, 376, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #1902 = VADDUWS | |
| { 1901, 3, 1, 4, 410, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #1901 = VADDUWM | |
| { 1900, 3, 1, 4, 356, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo95 }, // Inst #1900 = VADDUQM | |
| { 1899, 3, 1, 4, 376, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #1899 = VADDUHS | |
| { 1898, 3, 1, 4, 410, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #1898 = VADDUHM | |
| { 1897, 3, 1, 4, 410, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo95 }, // Inst #1897 = VADDUDM | |
| { 1896, 3, 1, 4, 376, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #1896 = VADDUBS | |
| { 1895, 3, 1, 4, 410, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #1895 = VADDUBM | |
| { 1894, 3, 1, 4, 376, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #1894 = VADDSWS | |
| { 1893, 3, 1, 4, 376, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #1893 = VADDSHS | |
| { 1892, 3, 1, 4, 376, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #1892 = VADDSBS | |
| { 1891, 3, 1, 4, 324, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #1891 = VADDFP | |
| { 1890, 4, 1, 4, 359, 0, 0, 0, 0x0ULL, nullptr, OperandInfo300 }, // Inst #1890 = VADDEUQM | |
| { 1889, 4, 1, 4, 359, 0, 0, 0, 0x0ULL, nullptr, OperandInfo300 }, // Inst #1889 = VADDECUQ | |
| { 1888, 3, 1, 4, 376, 0, 0, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, OperandInfo95 }, // Inst #1888 = VADDCUW | |
| { 1887, 3, 1, 4, 355, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #1887 = VADDCUQ | |
| { 1886, 3, 1, 4, 143, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #1886 = VABSDUW | |
| { 1885, 3, 1, 4, 143, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #1885 = VABSDUH | |
| { 1884, 3, 1, 4, 143, 0, 0, 0, 0x0ULL, nullptr, OperandInfo95 }, // Inst #1884 = VABSDUB | |
| { 1883, 3, 2, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo65 }, // Inst #1883 = UpdateGBR | |
| { 1882, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1882 = UNENCODED_NOP | |
| { 1881, 3, 0, 4, 109, 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo293 }, // Inst #1881 = TWI | |
| { 1880, 3, 0, 4, 361, 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo116 }, // Inst #1880 = TW | |
| { 1879, 1, 0, 4, 139, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo3 }, // Inst #1879 = TSR | |
| { 1878, 1, 0, 4, 139, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo189 }, // Inst #1878 = TRECLAIM | |
| { 1877, 0, 0, 4, 417, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr }, // Inst #1877 = TRECHKPT | |
| { 1876, 0, 0, 4, 360, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1876 = TRAP | |
| { 1875, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo67 }, // Inst #1875 = TLSGDAIX8 | |
| { 1874, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo65 }, // Inst #1874 = TLSGDAIX | |
| { 1873, 3, 0, 4, 492, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #1873 = TLBWE2 | |
| { 1872, 0, 0, 4, 301, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1872 = TLBWE | |
| { 1871, 0, 0, 4, 189, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1871 = TLBSYNC | |
| { 1870, 3, 0, 4, 492, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo65 }, // Inst #1870 = TLBSX2D | |
| { 1869, 3, 0, 4, 492, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo65 }, // Inst #1869 = TLBSX2 | |
| { 1868, 2, 0, 4, 301, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo79 }, // Inst #1868 = TLBSX | |
| { 1867, 3, 1, 4, 492, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #1867 = TLBRE2 | |
| { 1866, 0, 0, 4, 301, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1866 = TLBRE | |
| { 1865, 1, 0, 4, 492, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo189 }, // Inst #1865 = TLBLI | |
| { 1864, 1, 0, 4, 492, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo189 }, // Inst #1864 = TLBLD | |
| { 1863, 2, 0, 4, 301, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo79 }, // Inst #1863 = TLBIVAX | |
| { 1862, 1, 0, 4, 198, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo189 }, // Inst #1862 = TLBIEL | |
| { 1861, 2, 0, 4, 224, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo79 }, // Inst #1861 = TLBIE | |
| { 1860, 0, 0, 4, 310, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1860 = TLBIA | |
| { 1859, 1, 0, 4, 201, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo3 }, // Inst #1859 = TEND | |
| { 1858, 3, 0, 4, 108, 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo299 }, // Inst #1858 = TDI | |
| { 1857, 3, 0, 4, 108, 0, 0, 0|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo298 }, // Inst #1857 = TD | |
| { 1856, 2, 0, 4, 0, 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList42, OperandInfo297 }, // Inst #1856 = TCRETURNri8 | |
| { 1855, 2, 0, 4, 0, 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList42, OperandInfo296 }, // Inst #1855 = TCRETURNri | |
| { 1854, 2, 0, 4, 0, 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList42, OperandInfo295 }, // Inst #1854 = TCRETURNdi8 | |
| { 1853, 2, 0, 4, 0, 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList42, OperandInfo295 }, // Inst #1853 = TCRETURNdi | |
| { 1852, 2, 0, 4, 0, 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList42, OperandInfo294 }, // Inst #1852 = TCRETURNai8 | |
| { 1851, 2, 0, 4, 0, 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList42, OperandInfo294 }, // Inst #1851 = TCRETURNai | |
| { 1850, 1, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo189 }, // Inst #1850 = TCHECK_RET | |
| { 1849, 1, 1, 4, 207, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo187 }, // Inst #1849 = TCHECK | |
| { 1848, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo171 }, // Inst #1848 = TBEGIN_RET | |
| { 1847, 1, 0, 4, 126, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo3 }, // Inst #1847 = TBEGIN | |
| { 1846, 0, 0, 4, 335, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList53, nullptr }, // Inst #1846 = TAILBCTR8 | |
| { 1845, 0, 0, 4, 335, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList52, nullptr }, // Inst #1845 = TAILBCTR | |
| { 1844, 1, 0, 4, 335, 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList42, OperandInfo2 }, // Inst #1844 = TAILBA8 | |
| { 1843, 1, 0, 4, 335, 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList42, OperandInfo2 }, // Inst #1843 = TAILBA | |
| { 1842, 1, 0, 4, 335, 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList42, OperandInfo87 }, // Inst #1842 = TAILB8 | |
| { 1841, 1, 0, 4, 335, 1, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList42, OperandInfo87 }, // Inst #1841 = TAILB | |
| { 1840, 3, 0, 4, 104, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo293 }, // Inst #1840 = TABORTWCI | |
| { 1839, 3, 0, 4, 104, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo116 }, // Inst #1839 = TABORTWC | |
| { 1838, 3, 0, 4, 104, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo293 }, // Inst #1838 = TABORTDCI | |
| { 1837, 3, 0, 4, 104, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo116 }, // Inst #1837 = TABORTDC | |
| { 1836, 1, 0, 4, 139, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo189 }, // Inst #1836 = TABORT | |
| { 1835, 1, 0, 4, 190, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo3 }, // Inst #1835 = SYNC | |
| { 1834, 3, 1, 4, 405, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo65 }, // Inst #1834 = SUBF_rec | |
| { 1833, 2, 1, 4, 418, 1, 2, 0, 0x8ULL, ImplicitList12, OperandInfo79 }, // Inst #1833 = SUBFZE_rec | |
| { 1832, 2, 1, 4, 418, 1, 3, 0, 0x8ULL, ImplicitList11, OperandInfo79 }, // Inst #1832 = SUBFZEO_rec | |
| { 1831, 2, 1, 4, 395, 1, 2, 0, 0x8ULL, ImplicitList10, OperandInfo79 }, // Inst #1831 = SUBFZEO | |
| { 1830, 2, 1, 4, 418, 1, 2, 0, 0x8ULL, ImplicitList12, OperandInfo80 }, // Inst #1830 = SUBFZE8_rec | |
| { 1829, 2, 1, 4, 418, 1, 3, 0, 0x8ULL, ImplicitList11, OperandInfo80 }, // Inst #1829 = SUBFZE8O_rec | |
| { 1828, 2, 1, 4, 395, 1, 2, 0, 0x8ULL, ImplicitList10, OperandInfo80 }, // Inst #1828 = SUBFZE8O | |
| { 1827, 2, 1, 4, 395, 1, 1, 0, 0x8ULL, ImplicitList9, OperandInfo80 }, // Inst #1827 = SUBFZE8 | |
| { 1826, 2, 1, 4, 395, 1, 1, 0, 0x8ULL, ImplicitList9, OperandInfo79 }, // Inst #1826 = SUBFZE | |
| { 1825, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo71 }, // Inst #1825 = SUBFUS_rec | |
| { 1824, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo71 }, // Inst #1824 = SUBFUS | |
| { 1823, 3, 1, 4, 421, 0, 2, 0, 0x8ULL, ImplicitList4, OperandInfo65 }, // Inst #1823 = SUBFO_rec | |
| { 1822, 3, 1, 4, 405, 0, 1, 0, 0x8ULL, ImplicitList3, OperandInfo65 }, // Inst #1822 = SUBFO | |
| { 1821, 2, 1, 4, 418, 1, 2, 0, 0x8ULL, ImplicitList12, OperandInfo79 }, // Inst #1821 = SUBFME_rec | |
| { 1820, 2, 1, 4, 418, 1, 3, 0, 0x8ULL, ImplicitList11, OperandInfo79 }, // Inst #1820 = SUBFMEO_rec | |
| { 1819, 2, 1, 4, 395, 1, 2, 0, 0x8ULL, ImplicitList10, OperandInfo79 }, // Inst #1819 = SUBFMEO | |
| { 1818, 2, 1, 4, 418, 1, 2, 0, 0x8ULL, ImplicitList12, OperandInfo80 }, // Inst #1818 = SUBFME8_rec | |
| { 1817, 2, 1, 4, 418, 1, 3, 0, 0x8ULL, ImplicitList11, OperandInfo80 }, // Inst #1817 = SUBFME8O_rec | |
| { 1816, 2, 1, 4, 395, 1, 2, 0, 0x8ULL, ImplicitList10, OperandInfo80 }, // Inst #1816 = SUBFME8O | |
| { 1815, 2, 1, 4, 395, 1, 1, 0, 0x8ULL, ImplicitList9, OperandInfo80 }, // Inst #1815 = SUBFME8 | |
| { 1814, 2, 1, 4, 395, 1, 1, 0, 0x8ULL, ImplicitList9, OperandInfo79 }, // Inst #1814 = SUBFME | |
| { 1813, 3, 1, 4, 405, 0, 1, 0, 0x8ULL, ImplicitList5, OperandInfo52 }, // Inst #1813 = SUBFIC8 | |
| { 1812, 3, 1, 4, 405, 0, 1, 0, 0x8ULL, ImplicitList5, OperandInfo53 }, // Inst #1812 = SUBFIC | |
| { 1811, 3, 1, 4, 421, 1, 2, 0, 0x8ULL, ImplicitList12, OperandInfo65 }, // Inst #1811 = SUBFE_rec | |
| { 1810, 3, 1, 4, 421, 1, 3, 0, 0x8ULL, ImplicitList11, OperandInfo65 }, // Inst #1810 = SUBFEO_rec | |
| { 1809, 3, 1, 4, 405, 1, 2, 0, 0x8ULL, ImplicitList10, OperandInfo65 }, // Inst #1809 = SUBFEO | |
| { 1808, 3, 1, 4, 421, 1, 2, 0, 0x8ULL, ImplicitList12, OperandInfo67 }, // Inst #1808 = SUBFE8_rec | |
| { 1807, 3, 1, 4, 421, 1, 3, 0, 0x8ULL, ImplicitList11, OperandInfo67 }, // Inst #1807 = SUBFE8O_rec | |
| { 1806, 3, 1, 4, 405, 1, 2, 0, 0x8ULL, ImplicitList10, OperandInfo67 }, // Inst #1806 = SUBFE8O | |
| { 1805, 3, 1, 4, 405, 1, 1, 0, 0x8ULL, ImplicitList9, OperandInfo67 }, // Inst #1805 = SUBFE8 | |
| { 1804, 3, 1, 4, 405, 1, 1, 0, 0x8ULL, ImplicitList9, OperandInfo65 }, // Inst #1804 = SUBFE | |
| { 1803, 3, 1, 4, 426, 0, 2, 0, 0xcULL, ImplicitList8, OperandInfo65 }, // Inst #1803 = SUBFC_rec | |
| { 1802, 3, 1, 4, 247, 0, 3, 0, 0xcULL, ImplicitList7, OperandInfo65 }, // Inst #1802 = SUBFCO_rec | |
| { 1801, 3, 1, 4, 425, 0, 2, 0, 0xcULL, ImplicitList6, OperandInfo65 }, // Inst #1801 = SUBFCO | |
| { 1800, 3, 1, 4, 426, 0, 2, 0, 0xcULL, ImplicitList8, OperandInfo67 }, // Inst #1800 = SUBFC8_rec | |
| { 1799, 3, 1, 4, 247, 0, 3, 0, 0xcULL, ImplicitList7, OperandInfo67 }, // Inst #1799 = SUBFC8O_rec | |
| { 1798, 3, 1, 4, 425, 0, 2, 0, 0xcULL, ImplicitList6, OperandInfo67 }, // Inst #1798 = SUBFC8O | |
| { 1797, 3, 1, 4, 425, 0, 1, 0, 0xcULL, ImplicitList5, OperandInfo67 }, // Inst #1797 = SUBFC8 | |
| { 1796, 3, 1, 4, 425, 0, 1, 0, 0xcULL, ImplicitList5, OperandInfo65 }, // Inst #1796 = SUBFC | |
| { 1795, 3, 1, 4, 405, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo67 }, // Inst #1795 = SUBF8_rec | |
| { 1794, 3, 1, 4, 421, 0, 2, 0, 0x8ULL, ImplicitList4, OperandInfo67 }, // Inst #1794 = SUBF8O_rec | |
| { 1793, 3, 1, 4, 405, 0, 1, 0, 0x8ULL, ImplicitList3, OperandInfo67 }, // Inst #1793 = SUBF8O | |
| { 1792, 3, 1, 4, 405, 0, 0, 0, 0x8ULL, nullptr, OperandInfo67 }, // Inst #1792 = SUBF8 | |
| { 1791, 3, 1, 4, 405, 0, 0, 0, 0x8ULL, nullptr, OperandInfo65 }, // Inst #1791 = SUBF | |
| { 1790, 3, 0, 4, 226, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1790 = STXVX | |
| { 1789, 3, 0, 4, 226, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1789 = STXVW4X | |
| { 1788, 3, 0, 4, 484, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1788 = STXVRWX | |
| { 1787, 3, 0, 4, 14, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL, nullptr, OperandInfo180 }, // Inst #1787 = STXVRLL | |
| { 1786, 3, 0, 4, 14, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL, nullptr, OperandInfo180 }, // Inst #1786 = STXVRL | |
| { 1785, 3, 0, 4, 484, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1785 = STXVRHX | |
| { 1784, 3, 0, 4, 484, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1784 = STXVRDX | |
| { 1783, 3, 0, 4, 484, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1783 = STXVRBX | |
| { 1782, 3, 0, 4, 489, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo183 }, // Inst #1782 = STXVPX | |
| { 1781, 3, 0, 4, 40, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL, nullptr, OperandInfo182 }, // Inst #1781 = STXVPRLL | |
| { 1780, 3, 0, 4, 40, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL, nullptr, OperandInfo182 }, // Inst #1780 = STXVPRL | |
| { 1779, 3, 0, 4, 489, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo181 }, // Inst #1779 = STXVP | |
| { 1778, 3, 0, 4, 227, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo180 }, // Inst #1778 = STXVLL | |
| { 1777, 3, 0, 4, 227, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo180 }, // Inst #1777 = STXVL | |
| { 1776, 3, 0, 4, 226, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1776 = STXVH8X | |
| { 1775, 3, 0, 4, 226, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1775 = STXVD2X | |
| { 1774, 3, 0, 4, 226, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1774 = STXVB16X | |
| { 1773, 3, 0, 4, 226, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo177 }, // Inst #1773 = STXV | |
| { 1772, 3, 0, 4, 217, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo64 }, // Inst #1772 = STXSSPX | |
| { 1771, 3, 0, 4, 217, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo176 }, // Inst #1771 = STXSSP | |
| { 1770, 3, 0, 4, 217, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo60 }, // Inst #1770 = STXSIWX | |
| { 1769, 3, 0, 4, 217, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1769 = STXSIHXv | |
| { 1768, 3, 0, 4, 217, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo60 }, // Inst #1768 = STXSIHX | |
| { 1767, 3, 0, 4, 217, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1767 = STXSIBXv | |
| { 1766, 3, 0, 4, 217, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo60 }, // Inst #1766 = STXSIBX | |
| { 1765, 3, 0, 4, 217, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo60 }, // Inst #1765 = STXSDX | |
| { 1764, 3, 0, 4, 217, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo176 }, // Inst #1764 = STXSD | |
| { 1763, 3, 0, 4, 218, 0, 0, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, OperandInfo159 }, // Inst #1763 = STWXTLS_32 | |
| { 1762, 3, 0, 4, 218, 0, 0, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, OperandInfo158 }, // Inst #1762 = STWXTLS_ | |
| { 1761, 3, 0, 4, 218, 0, 0, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, OperandInfo158 }, // Inst #1761 = STWXTLS | |
| { 1760, 3, 0, 4, 218, 0, 0, 0|(1ULL<<MCID::MayStore), 0x54ULL, nullptr, OperandInfo157 }, // Inst #1760 = STWX8 | |
| { 1759, 3, 0, 4, 218, 0, 0, 0|(1ULL<<MCID::MayStore), 0x54ULL, nullptr, OperandInfo152 }, // Inst #1759 = STWX | |
| { 1758, 4, 1, 4, 281, 0, 0, 0|(1ULL<<MCID::MayStore), 0x54ULL, nullptr, OperandInfo288 }, // Inst #1758 = STWUX8 | |
| { 1757, 4, 1, 4, 281, 0, 0, 0|(1ULL<<MCID::MayStore), 0x54ULL, nullptr, OperandInfo287 }, // Inst #1757 = STWUX | |
| { 1756, 4, 1, 4, 280, 0, 0, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, OperandInfo286 }, // Inst #1756 = STWU8 | |
| { 1755, 4, 1, 4, 280, 0, 0, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, OperandInfo285 }, // Inst #1755 = STWU | |
| { 1754, 3, 0, 4, 302, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo152 }, // Inst #1754 = STWEPX | |
| { 1753, 3, 0, 4, 202, 0, 1, 0|(1ULL<<MCID::MayStore), 0x40ULL, ImplicitList1, OperandInfo152 }, // Inst #1753 = STWCX | |
| { 1752, 3, 0, 4, 487, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL, nullptr, OperandInfo65 }, // Inst #1752 = STWCIX | |
| { 1751, 3, 0, 4, 480, 0, 0, 0|(1ULL<<MCID::MayStore), 0x54ULL, nullptr, OperandInfo152 }, // Inst #1751 = STWBRX | |
| { 1750, 3, 0, 4, 292, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo53 }, // Inst #1750 = STWAT | |
| { 1749, 3, 0, 4, 480, 0, 0, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, OperandInfo149 }, // Inst #1749 = STW8 | |
| { 1748, 3, 0, 4, 480, 0, 0, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, OperandInfo59 }, // Inst #1748 = STW | |
| { 1747, 3, 0, 4, 225, 0, 0, 0|(1ULL<<MCID::MayStore), 0x50ULL, nullptr, OperandInfo174 }, // Inst #1747 = STVXL | |
| { 1746, 3, 0, 4, 225, 0, 0, 0|(1ULL<<MCID::MayStore), 0x50ULL, nullptr, OperandInfo174 }, // Inst #1746 = STVX | |
| { 1745, 3, 0, 4, 225, 0, 0, 0|(1ULL<<MCID::MayStore), 0x50ULL, nullptr, OperandInfo174 }, // Inst #1745 = STVEWX | |
| { 1744, 3, 0, 4, 225, 0, 0, 0|(1ULL<<MCID::MayStore), 0x50ULL, nullptr, OperandInfo174 }, // Inst #1744 = STVEHX | |
| { 1743, 3, 0, 4, 225, 0, 0, 0|(1ULL<<MCID::MayStore), 0x50ULL, nullptr, OperandInfo174 }, // Inst #1743 = STVEBX | |
| { 1742, 3, 0, 4, 221, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL, nullptr, OperandInfo53 }, // Inst #1742 = STSWI | |
| { 1741, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo173 }, // Inst #1741 = STQX_PSEUDO | |
| { 1740, 3, 0, 4, 92, 0, 1, 0|(1ULL<<MCID::MayStore), 0x40ULL, ImplicitList1, OperandInfo173 }, // Inst #1740 = STQCX | |
| { 1739, 3, 0, 4, 91, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo250 }, // Inst #1739 = STQ | |
| { 1738, 0, 0, 4, 316, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1738 = STOP | |
| { 1737, 3, 0, 4, 223, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #1737 = STMW | |
| { 1736, 3, 0, 4, 218, 0, 0, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, OperandInfo159 }, // Inst #1736 = STHXTLS_32 | |
| { 1735, 3, 0, 4, 218, 0, 0, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, OperandInfo158 }, // Inst #1735 = STHXTLS_ | |
| { 1734, 3, 0, 4, 218, 0, 0, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, OperandInfo158 }, // Inst #1734 = STHXTLS | |
| { 1733, 3, 0, 4, 218, 0, 0, 0|(1ULL<<MCID::MayStore), 0x54ULL, nullptr, OperandInfo157 }, // Inst #1733 = STHX8 | |
| { 1732, 3, 0, 4, 218, 0, 0, 0|(1ULL<<MCID::MayStore), 0x54ULL, nullptr, OperandInfo152 }, // Inst #1732 = STHX | |
| { 1731, 4, 1, 4, 281, 0, 0, 0|(1ULL<<MCID::MayStore), 0x54ULL, nullptr, OperandInfo288 }, // Inst #1731 = STHUX8 | |
| { 1730, 4, 1, 4, 281, 0, 0, 0|(1ULL<<MCID::MayStore), 0x54ULL, nullptr, OperandInfo287 }, // Inst #1730 = STHUX | |
| { 1729, 4, 1, 4, 280, 0, 0, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, OperandInfo286 }, // Inst #1729 = STHU8 | |
| { 1728, 4, 1, 4, 280, 0, 0, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, OperandInfo285 }, // Inst #1728 = STHU | |
| { 1727, 3, 0, 4, 302, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo152 }, // Inst #1727 = STHEPX | |
| { 1726, 3, 0, 4, 202, 0, 1, 0|(1ULL<<MCID::MayStore), 0x40ULL, ImplicitList1, OperandInfo152 }, // Inst #1726 = STHCX | |
| { 1725, 3, 0, 4, 487, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL, nullptr, OperandInfo65 }, // Inst #1725 = STHCIX | |
| { 1724, 3, 0, 4, 480, 0, 0, 0|(1ULL<<MCID::MayStore), 0x54ULL, nullptr, OperandInfo152 }, // Inst #1724 = STHBRX | |
| { 1723, 3, 0, 4, 480, 0, 0, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, OperandInfo149 }, // Inst #1723 = STH8 | |
| { 1722, 3, 0, 4, 480, 0, 0, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, OperandInfo59 }, // Inst #1722 = STH | |
| { 1721, 3, 0, 4, 217, 0, 0, 0|(1ULL<<MCID::MayStore), 0x50ULL, nullptr, OperandInfo170 }, // Inst #1721 = STFSX | |
| { 1720, 4, 1, 4, 279, 0, 0, 0|(1ULL<<MCID::MayStore), 0x54ULL, nullptr, OperandInfo292 }, // Inst #1720 = STFSUX | |
| { 1719, 4, 1, 4, 279, 0, 0, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, OperandInfo291 }, // Inst #1719 = STFSU | |
| { 1718, 3, 0, 4, 217, 0, 0, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, OperandInfo167 }, // Inst #1718 = STFS | |
| { 1717, 3, 0, 4, 217, 0, 0, 0|(1ULL<<MCID::MayStore), 0x50ULL, nullptr, OperandInfo164 }, // Inst #1717 = STFIWX | |
| { 1716, 3, 0, 4, 217, 0, 0, 0|(1ULL<<MCID::MayStore), 0x50ULL, nullptr, OperandInfo164 }, // Inst #1716 = STFDX | |
| { 1715, 4, 1, 4, 279, 0, 0, 0|(1ULL<<MCID::MayStore), 0x54ULL, nullptr, OperandInfo290 }, // Inst #1715 = STFDUX | |
| { 1714, 4, 1, 4, 279, 0, 0, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, OperandInfo289 }, // Inst #1714 = STFDU | |
| { 1713, 3, 0, 4, 304, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL, nullptr, OperandInfo164 }, // Inst #1713 = STFDEPX | |
| { 1712, 3, 0, 4, 217, 0, 0, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, OperandInfo163 }, // Inst #1712 = STFD | |
| { 1711, 3, 0, 4, 220, 0, 0, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, OperandInfo158 }, // Inst #1711 = STDXTLS_ | |
| { 1710, 3, 0, 4, 220, 0, 0, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, OperandInfo158 }, // Inst #1710 = STDXTLS | |
| { 1709, 3, 0, 4, 220, 0, 0, 0|(1ULL<<MCID::MayStore), 0x54ULL, nullptr, OperandInfo157 }, // Inst #1709 = STDX | |
| { 1708, 4, 1, 4, 281, 0, 0, 0|(1ULL<<MCID::MayStore), 0x54ULL, nullptr, OperandInfo288 }, // Inst #1708 = STDUX | |
| { 1707, 4, 1, 4, 280, 0, 0, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, OperandInfo286 }, // Inst #1707 = STDU | |
| { 1706, 3, 0, 4, 203, 0, 1, 0|(1ULL<<MCID::MayStore), 0x40ULL, ImplicitList1, OperandInfo157 }, // Inst #1706 = STDCX | |
| { 1705, 3, 0, 4, 487, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL, nullptr, OperandInfo65 }, // Inst #1705 = STDCIX | |
| { 1704, 3, 0, 4, 480, 0, 0, 0|(1ULL<<MCID::MayStore), 0x54ULL, nullptr, OperandInfo157 }, // Inst #1704 = STDBRX | |
| { 1703, 3, 0, 4, 292, 0, 0, 0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo52 }, // Inst #1703 = STDAT | |
| { 1702, 3, 0, 4, 482, 0, 0, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, OperandInfo149 }, // Inst #1702 = STD | |
| { 1701, 3, 0, 4, 218, 0, 0, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, OperandInfo159 }, // Inst #1701 = STBXTLS_32 | |
| { 1700, 3, 0, 4, 218, 0, 0, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, OperandInfo158 }, // Inst #1700 = STBXTLS_ | |
| { 1699, 3, 0, 4, 218, 0, 0, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, OperandInfo158 }, // Inst #1699 = STBXTLS | |
| { 1698, 3, 0, 4, 218, 0, 0, 0|(1ULL<<MCID::MayStore), 0x54ULL, nullptr, OperandInfo157 }, // Inst #1698 = STBX8 | |
| { 1697, 3, 0, 4, 218, 0, 0, 0|(1ULL<<MCID::MayStore), 0x54ULL, nullptr, OperandInfo152 }, // Inst #1697 = STBX | |
| { 1696, 4, 1, 4, 281, 0, 0, 0|(1ULL<<MCID::MayStore), 0x54ULL, nullptr, OperandInfo288 }, // Inst #1696 = STBUX8 | |
| { 1695, 4, 1, 4, 281, 0, 0, 0|(1ULL<<MCID::MayStore), 0x54ULL, nullptr, OperandInfo287 }, // Inst #1695 = STBUX | |
| { 1694, 4, 1, 4, 280, 0, 0, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, OperandInfo286 }, // Inst #1694 = STBU8 | |
| { 1693, 4, 1, 4, 280, 0, 0, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, OperandInfo285 }, // Inst #1693 = STBU | |
| { 1692, 3, 0, 4, 302, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo152 }, // Inst #1692 = STBEPX | |
| { 1691, 3, 0, 4, 202, 0, 1, 0|(1ULL<<MCID::MayStore), 0x40ULL, ImplicitList1, OperandInfo152 }, // Inst #1691 = STBCX | |
| { 1690, 3, 0, 4, 487, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL, nullptr, OperandInfo65 }, // Inst #1690 = STBCIX | |
| { 1689, 3, 0, 4, 480, 0, 0, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, OperandInfo149 }, // Inst #1689 = STB8 | |
| { 1688, 3, 0, 4, 480, 0, 0, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, OperandInfo59 }, // Inst #1688 = STB | |
| { 1687, 3, 1, 4, 375, 0, 1, 0, 0x208ULL, ImplicitList1, OperandInfo65 }, // Inst #1687 = SRW_rec | |
| { 1686, 3, 1, 4, 375, 0, 1, 0, 0x208ULL, ImplicitList1, OperandInfo67 }, // Inst #1686 = SRW8_rec | |
| { 1685, 3, 1, 4, 409, 0, 0, 0, 0x208ULL, nullptr, OperandInfo67 }, // Inst #1685 = SRW8 | |
| { 1684, 3, 1, 4, 409, 0, 0, 0, 0x208ULL, nullptr, OperandInfo65 }, // Inst #1684 = SRW | |
| { 1683, 3, 1, 4, 374, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo283 }, // Inst #1683 = SRD_rec | |
| { 1682, 3, 1, 4, 115, 0, 0, 0, 0x8ULL, nullptr, OperandInfo283 }, // Inst #1682 = SRD | |
| { 1681, 3, 1, 4, 256, 0, 2, 0, 0x108ULL, ImplicitList8, OperandInfo65 }, // Inst #1681 = SRAW_rec | |
| { 1680, 3, 1, 4, 256, 0, 2, 0, 0x108ULL, ImplicitList8, OperandInfo53 }, // Inst #1680 = SRAWI_rec | |
| { 1679, 3, 1, 4, 136, 0, 1, 0, 0x108ULL, ImplicitList5, OperandInfo53 }, // Inst #1679 = SRAWI | |
| { 1678, 3, 1, 4, 136, 0, 1, 0, 0x108ULL, ImplicitList5, OperandInfo65 }, // Inst #1678 = SRAW | |
| { 1677, 3, 1, 4, 260, 0, 2, 0, 0x8ULL, ImplicitList8, OperandInfo283 }, // Inst #1677 = SRAD_rec | |
| { 1676, 3, 1, 4, 259, 0, 2, 0, 0x8ULL, ImplicitList8, OperandInfo52 }, // Inst #1676 = SRADI_rec | |
| { 1675, 3, 1, 4, 408, 0, 1, 0, 0x8ULL, ImplicitList5, OperandInfo53 }, // Inst #1675 = SRADI_32 | |
| { 1674, 3, 1, 4, 408, 0, 1, 0, 0x8ULL, ImplicitList5, OperandInfo52 }, // Inst #1674 = SRADI | |
| { 1673, 3, 1, 4, 115, 0, 1, 0, 0x8ULL, ImplicitList5, OperandInfo283 }, // Inst #1673 = SRAD | |
| { 1672, 3, 2, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo284 }, // Inst #1672 = SPLIT_QUADWORD | |
| { 1671, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo252 }, // Inst #1671 = SPILL_WACC | |
| { 1670, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo251 }, // Inst #1670 = SPILL_UACC | |
| { 1669, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo250 }, // Inst #1669 = SPILL_QUADWORD | |
| { 1668, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo249 }, // Inst #1668 = SPILL_CRBIT | |
| { 1667, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo248 }, // Inst #1667 = SPILL_CR | |
| { 1666, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo247 }, // Inst #1666 = SPILL_ACC | |
| { 1665, 3, 0, 4, 25, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo152 }, // Inst #1665 = SPESTWX | |
| { 1664, 3, 0, 4, 25, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo59 }, // Inst #1664 = SPESTW | |
| { 1663, 3, 1, 4, 14, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo152 }, // Inst #1663 = SPELWZX | |
| { 1662, 3, 1, 4, 14, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo59 }, // Inst #1662 = SPELWZ | |
| { 1661, 3, 1, 4, 375, 0, 1, 0, 0x208ULL, ImplicitList1, OperandInfo65 }, // Inst #1661 = SLW_rec | |
| { 1660, 3, 1, 4, 375, 0, 1, 0, 0x208ULL, ImplicitList1, OperandInfo67 }, // Inst #1660 = SLW8_rec | |
| { 1659, 3, 1, 4, 409, 0, 0, 0, 0x208ULL, nullptr, OperandInfo67 }, // Inst #1659 = SLW8 | |
| { 1658, 3, 1, 4, 409, 0, 0, 0, 0x208ULL, nullptr, OperandInfo65 }, // Inst #1658 = SLW | |
| { 1657, 3, 1, 4, 374, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo283 }, // Inst #1657 = SLD_rec | |
| { 1656, 3, 1, 4, 115, 0, 0, 0, 0x8ULL, nullptr, OperandInfo283 }, // Inst #1656 = SLD | |
| { 1655, 0, 0, 4, 314, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1655 = SLBSYNC | |
| { 1654, 2, 0, 4, 197, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo79 }, // Inst #1654 = SLBMTE | |
| { 1653, 2, 1, 4, 196, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo79 }, // Inst #1653 = SLBMFEV | |
| { 1652, 2, 1, 4, 195, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo79 }, // Inst #1652 = SLBMFEE | |
| { 1651, 2, 0, 4, 222, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo79 }, // Inst #1651 = SLBIEG | |
| { 1650, 1, 0, 4, 194, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo189 }, // Inst #1650 = SLBIE | |
| { 1649, 0, 0, 4, 193, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1649 = SLBIA | |
| { 1648, 2, 1, 4, 315, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo79 }, // Inst #1648 = SLBFEE_rec | |
| { 1647, 2, 1, 4, 0, 1, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList51, OperandInfo191 }, // Inst #1647 = SETRNDi | |
| { 1646, 2, 1, 4, 0, 1, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList51, OperandInfo282 }, // Inst #1646 = SETRND | |
| { 1645, 2, 1, 4, 398, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, OperandInfo281 }, // Inst #1645 = SETNBCR8 | |
| { 1644, 2, 1, 4, 398, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, OperandInfo280 }, // Inst #1644 = SETNBCR | |
| { 1643, 2, 1, 4, 398, 0, 0, 0, 0x100ULL, nullptr, OperandInfo281 }, // Inst #1643 = SETNBC8 | |
| { 1642, 2, 1, 4, 398, 0, 0, 0, 0x100ULL, nullptr, OperandInfo280 }, // Inst #1642 = SETNBC | |
| { 1641, 2, 1, 4, 0, 1, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList51, OperandInfo138 }, // Inst #1641 = SETFLM | |
| { 1640, 2, 1, 4, 398, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, OperandInfo281 }, // Inst #1640 = SETBCR8 | |
| { 1639, 2, 1, 4, 398, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x300ULL, nullptr, OperandInfo280 }, // Inst #1639 = SETBCR | |
| { 1638, 2, 1, 4, 398, 0, 0, 0, 0x300ULL, nullptr, OperandInfo281 }, // Inst #1638 = SETBC8 | |
| { 1637, 2, 1, 4, 398, 0, 0, 0, 0x300ULL, nullptr, OperandInfo280 }, // Inst #1637 = SETBC | |
| { 1636, 2, 1, 4, 397, 0, 0, 0, 0x108ULL, nullptr, OperandInfo279 }, // Inst #1636 = SETB8 | |
| { 1635, 2, 1, 4, 397, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, OperandInfo278 }, // Inst #1635 = SETB | |
| { 1634, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, OperandInfo271 }, // Inst #1634 = SELECT_VSSRC | |
| { 1633, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, OperandInfo277 }, // Inst #1633 = SELECT_VSRC | |
| { 1632, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, OperandInfo272 }, // Inst #1632 = SELECT_VSFRC | |
| { 1631, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, OperandInfo270 }, // Inst #1631 = SELECT_VRRC | |
| { 1630, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo276 }, // Inst #1630 = SELECT_SPE4 | |
| { 1629, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo275 }, // Inst #1629 = SELECT_SPE | |
| { 1628, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, OperandInfo274 }, // Inst #1628 = SELECT_I8 | |
| { 1627, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, OperandInfo273 }, // Inst #1627 = SELECT_I4 | |
| { 1626, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, OperandInfo272 }, // Inst #1626 = SELECT_F8 | |
| { 1625, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, OperandInfo271 }, // Inst #1625 = SELECT_F4 | |
| { 1624, 4, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, OperandInfo270 }, // Inst #1624 = SELECT_F16 | |
| { 1623, 5, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo263 }, // Inst #1623 = SELECT_CC_VSSRC | |
| { 1622, 5, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo269 }, // Inst #1622 = SELECT_CC_VSRC | |
| { 1621, 5, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo264 }, // Inst #1621 = SELECT_CC_VSFRC | |
| { 1620, 5, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo262 }, // Inst #1620 = SELECT_CC_VRRC | |
| { 1619, 5, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo268 }, // Inst #1619 = SELECT_CC_SPE4 | |
| { 1618, 5, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo267 }, // Inst #1618 = SELECT_CC_SPE | |
| { 1617, 5, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo266 }, // Inst #1617 = SELECT_CC_I8 | |
| { 1616, 5, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo265 }, // Inst #1616 = SELECT_CC_I4 | |
| { 1615, 5, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo264 }, // Inst #1615 = SELECT_CC_F8 | |
| { 1614, 5, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo263 }, // Inst #1614 = SELECT_CC_F4 | |
| { 1613, 5, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo262 }, // Inst #1613 = SELECT_CC_F16 | |
| { 1612, 1, 0, 4, 424, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, OperandInfo3 }, // Inst #1612 = SC | |
| { 1611, 2, 2, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo79 }, // Inst #1611 = ReadTB | |
| { 1610, 5, 1, 4, 255, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo260 }, // Inst #1610 = RLWNM_rec | |
| { 1609, 5, 1, 4, 255, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo261 }, // Inst #1609 = RLWNM8_rec | |
| { 1608, 5, 1, 4, 134, 0, 0, 0, 0x8ULL, nullptr, OperandInfo261 }, // Inst #1608 = RLWNM8 | |
| { 1607, 5, 1, 4, 134, 0, 0, 0, 0x8ULL, nullptr, OperandInfo260 }, // Inst #1607 = RLWNM | |
| { 1606, 5, 1, 4, 255, 0, 1, 0, 0xcULL, ImplicitList1, OperandInfo258 }, // Inst #1606 = RLWINM_rec | |
| { 1605, 5, 1, 4, 255, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo259 }, // Inst #1605 = RLWINM8_rec | |
| { 1604, 5, 1, 4, 134, 0, 0, 0, 0x8ULL, nullptr, OperandInfo259 }, // Inst #1604 = RLWINM8 | |
| { 1603, 5, 1, 4, 134, 0, 0, 0, 0x8ULL, nullptr, OperandInfo258 }, // Inst #1603 = RLWINM | |
| { 1602, 6, 1, 4, 254, 0, 1, 0|(1ULL<<MCID::Commutable), 0xcULL, ImplicitList1, OperandInfo256 }, // Inst #1602 = RLWIMI_rec | |
| { 1601, 6, 1, 4, 254, 0, 1, 0, 0xcULL, ImplicitList1, OperandInfo257 }, // Inst #1601 = RLWIMI8_rec | |
| { 1600, 6, 1, 4, 129, 0, 0, 0, 0xcULL, nullptr, OperandInfo257 }, // Inst #1600 = RLWIMI8 | |
| { 1599, 6, 1, 4, 129, 0, 0, 0|(1ULL<<MCID::Commutable), 0xcULL, nullptr, OperandInfo256 }, // Inst #1599 = RLWIMI | |
| { 1598, 5, 1, 4, 253, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo255 }, // Inst #1598 = RLDIMI_rec | |
| { 1597, 5, 1, 4, 130, 0, 0, 0, 0x8ULL, nullptr, OperandInfo255 }, // Inst #1597 = RLDIMI | |
| { 1596, 4, 1, 4, 381, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo50 }, // Inst #1596 = RLDIC_rec | |
| { 1595, 4, 1, 4, 382, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo50 }, // Inst #1595 = RLDICR_rec | |
| { 1594, 4, 1, 4, 415, 0, 0, 0, 0x8ULL, nullptr, OperandInfo51 }, // Inst #1594 = RLDICR_32 | |
| { 1593, 4, 1, 4, 415, 0, 0, 0, 0x8ULL, nullptr, OperandInfo50 }, // Inst #1593 = RLDICR | |
| { 1592, 4, 1, 4, 382, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo50 }, // Inst #1592 = RLDICL_rec | |
| { 1591, 4, 1, 4, 382, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo51 }, // Inst #1591 = RLDICL_32_rec | |
| { 1590, 4, 1, 4, 415, 0, 0, 0, 0x8ULL, nullptr, OperandInfo254 }, // Inst #1590 = RLDICL_32_64 | |
| { 1589, 4, 1, 4, 415, 0, 0, 0, 0x8ULL, nullptr, OperandInfo51 }, // Inst #1589 = RLDICL_32 | |
| { 1588, 4, 1, 4, 415, 0, 0, 0, 0x8ULL, nullptr, OperandInfo50 }, // Inst #1588 = RLDICL | |
| { 1587, 4, 1, 4, 116, 0, 0, 0, 0x8ULL, nullptr, OperandInfo50 }, // Inst #1587 = RLDIC | |
| { 1586, 4, 1, 4, 252, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo253 }, // Inst #1586 = RLDCR_rec | |
| { 1585, 4, 1, 4, 128, 0, 0, 0, 0x8ULL, nullptr, OperandInfo253 }, // Inst #1585 = RLDCR | |
| { 1584, 4, 1, 4, 252, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo253 }, // Inst #1584 = RLDCL_rec | |
| { 1583, 4, 1, 4, 128, 0, 0, 0, 0x8ULL, nullptr, OperandInfo253 }, // Inst #1583 = RLDCL | |
| { 1582, 0, 0, 4, 298, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1582 = RFMCI | |
| { 1581, 0, 0, 4, 300, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1581 = RFID | |
| { 1580, 0, 0, 4, 299, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1580 = RFI | |
| { 1579, 1, 0, 4, 125, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo3 }, // Inst #1579 = RFEBB | |
| { 1578, 0, 0, 4, 298, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1578 = RFDI | |
| { 1577, 0, 0, 4, 298, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1577 = RFCI | |
| { 1576, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo252 }, // Inst #1576 = RESTORE_WACC | |
| { 1575, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo251 }, // Inst #1575 = RESTORE_UACC | |
| { 1574, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo250 }, // Inst #1574 = RESTORE_QUADWORD | |
| { 1573, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo249 }, // Inst #1573 = RESTORE_CRBIT | |
| { 1572, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo248 }, // Inst #1572 = RESTORE_CR | |
| { 1571, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo247 }, // Inst #1571 = RESTORE_ACC | |
| { 1570, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1570 = PseudoEIEIO | |
| { 1569, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo229 }, // Inst #1569 = PSTXVpc | |
| { 1568, 3, 0, 8, 479, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo228 }, // Inst #1568 = PSTXVPpc | |
| { 1567, 3, 0, 8, 479, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo227 }, // Inst #1567 = PSTXVP | |
| { 1566, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo226 }, // Inst #1566 = PSTXV | |
| { 1565, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo225 }, // Inst #1565 = PSTXSSPpc | |
| { 1564, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo224 }, // Inst #1564 = PSTXSSP | |
| { 1563, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo225 }, // Inst #1563 = PSTXSDpc | |
| { 1562, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo224 }, // Inst #1562 = PSTXSD | |
| { 1561, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo219 }, // Inst #1561 = PSTWpc | |
| { 1560, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo218 }, // Inst #1560 = PSTW8pc | |
| { 1559, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo217 }, // Inst #1559 = PSTW8 | |
| { 1558, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo216 }, // Inst #1558 = PSTW | |
| { 1557, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo219 }, // Inst #1557 = PSTHpc | |
| { 1556, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo218 }, // Inst #1556 = PSTH8pc | |
| { 1555, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo217 }, // Inst #1555 = PSTH8 | |
| { 1554, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo216 }, // Inst #1554 = PSTH | |
| { 1553, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo223 }, // Inst #1553 = PSTFSpc | |
| { 1552, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo222 }, // Inst #1552 = PSTFS | |
| { 1551, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo221 }, // Inst #1551 = PSTFDpc | |
| { 1550, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo220 }, // Inst #1550 = PSTFD | |
| { 1549, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo218 }, // Inst #1549 = PSTDpc | |
| { 1548, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo217 }, // Inst #1548 = PSTD | |
| { 1547, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo219 }, // Inst #1547 = PSTBpc | |
| { 1546, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo218 }, // Inst #1546 = PSTB8pc | |
| { 1545, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo217 }, // Inst #1545 = PSTB8 | |
| { 1544, 3, 0, 8, 488, 0, 0, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, OperandInfo216 }, // Inst #1544 = PSTB | |
| { 1543, 3, 2, 4, 0, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList40, OperandInfo52 }, // Inst #1543 = PROBED_STACKALLOC_64 | |
| { 1542, 3, 2, 4, 0, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList15, OperandInfo53 }, // Inst #1542 = PROBED_STACKALLOC_32 | |
| { 1541, 4, 1, 4, 0, 1, 1, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList40, OperandInfo119 }, // Inst #1541 = PROBED_ALLOCA_64 | |
| { 1540, 4, 1, 4, 0, 1, 1, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList15, OperandInfo118 }, // Inst #1540 = PROBED_ALLOCA_32 | |
| { 1539, 5, 2, 4, 0, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList40, OperandInfo246 }, // Inst #1539 = PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 | |
| { 1538, 5, 2, 4, 0, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList15, OperandInfo245 }, // Inst #1538 = PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 | |
| { 1537, 5, 2, 4, 0, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList40, OperandInfo244 }, // Inst #1537 = PREPARE_PROBED_ALLOCA_64 | |
| { 1536, 5, 2, 4, 0, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList15, OperandInfo243 }, // Inst #1536 = PREPARE_PROBED_ALLOCA_32 | |
| { 1535, 2, 2, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo79 }, // Inst #1535 = PPC32PICGOT | |
| { 1534, 1, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo189 }, // Inst #1534 = PPC32GOT | |
| { 1533, 2, 1, 4, 362, 0, 0, 0, 0x8ULL, nullptr, OperandInfo79 }, // Inst #1533 = POPCNTW | |
| { 1532, 2, 1, 4, 362, 0, 0, 0, 0x308ULL, nullptr, OperandInfo80 }, // Inst #1532 = POPCNTD | |
| { 1531, 2, 1, 4, 365, 0, 0, 0, 0x8ULL, nullptr, OperandInfo80 }, // Inst #1531 = POPCNTB8 | |
| { 1530, 2, 1, 4, 365, 0, 0, 0, 0x0ULL, nullptr, OperandInfo79 }, // Inst #1530 = POPCNTB | |
| { 1529, 7, 1, 8, 23, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo233 }, // Inst #1529 = PMXVI8GER4WSPP | |
| { 1528, 7, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo233 }, // Inst #1528 = PMXVI8GER4WPP | |
| { 1527, 6, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo232 }, // Inst #1527 = PMXVI8GER4W | |
| { 1526, 7, 1, 8, 453, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo231 }, // Inst #1526 = PMXVI8GER4SPP | |
| { 1525, 7, 1, 8, 452, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo231 }, // Inst #1525 = PMXVI8GER4PP | |
| { 1524, 6, 1, 8, 451, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo230 }, // Inst #1524 = PMXVI8GER4 | |
| { 1523, 7, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo233 }, // Inst #1523 = PMXVI4GER8WPP | |
| { 1522, 6, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo232 }, // Inst #1522 = PMXVI4GER8W | |
| { 1521, 7, 1, 8, 452, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo231 }, // Inst #1521 = PMXVI4GER8PP | |
| { 1520, 6, 1, 8, 451, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo230 }, // Inst #1520 = PMXVI4GER8 | |
| { 1519, 7, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo242 }, // Inst #1519 = PMXVI16GER2WPP | |
| { 1518, 6, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo232 }, // Inst #1518 = PMXVI16GER2W | |
| { 1517, 7, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo233 }, // Inst #1517 = PMXVI16GER2SWPP | |
| { 1516, 6, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo232 }, // Inst #1516 = PMXVI16GER2SW | |
| { 1515, 7, 1, 8, 452, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo231 }, // Inst #1515 = PMXVI16GER2SPP | |
| { 1514, 6, 1, 8, 451, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo230 }, // Inst #1514 = PMXVI16GER2S | |
| { 1513, 7, 1, 8, 452, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo231 }, // Inst #1513 = PMXVI16GER2PP | |
| { 1512, 6, 1, 8, 451, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo230 }, // Inst #1512 = PMXVI16GER2 | |
| { 1511, 6, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo241 }, // Inst #1511 = PMXVF64GERWPP | |
| { 1510, 6, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo241 }, // Inst #1510 = PMXVF64GERWPN | |
| { 1509, 6, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo241 }, // Inst #1509 = PMXVF64GERWNP | |
| { 1508, 6, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo241 }, // Inst #1508 = PMXVF64GERWNN | |
| { 1507, 5, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo240 }, // Inst #1507 = PMXVF64GERW | |
| { 1506, 6, 1, 8, 451, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo239 }, // Inst #1506 = PMXVF64GERPP | |
| { 1505, 6, 1, 8, 451, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo239 }, // Inst #1505 = PMXVF64GERPN | |
| { 1504, 6, 1, 8, 451, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo239 }, // Inst #1504 = PMXVF64GERNP | |
| { 1503, 6, 1, 8, 451, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo239 }, // Inst #1503 = PMXVF64GERNN | |
| { 1502, 5, 1, 8, 450, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo238 }, // Inst #1502 = PMXVF64GER | |
| { 1501, 6, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo237 }, // Inst #1501 = PMXVF32GERWPP | |
| { 1500, 6, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo237 }, // Inst #1500 = PMXVF32GERWPN | |
| { 1499, 6, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo237 }, // Inst #1499 = PMXVF32GERWNP | |
| { 1498, 6, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo237 }, // Inst #1498 = PMXVF32GERWNN | |
| { 1497, 5, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo236 }, // Inst #1497 = PMXVF32GERW | |
| { 1496, 6, 1, 8, 451, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo235 }, // Inst #1496 = PMXVF32GERPP | |
| { 1495, 6, 1, 8, 451, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo235 }, // Inst #1495 = PMXVF32GERPN | |
| { 1494, 6, 1, 8, 451, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo235 }, // Inst #1494 = PMXVF32GERNP | |
| { 1493, 6, 1, 8, 451, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo235 }, // Inst #1493 = PMXVF32GERNN | |
| { 1492, 5, 1, 8, 450, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo234 }, // Inst #1492 = PMXVF32GER | |
| { 1491, 7, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo233 }, // Inst #1491 = PMXVF16GER2WPP | |
| { 1490, 7, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo233 }, // Inst #1490 = PMXVF16GER2WPN | |
| { 1489, 7, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo233 }, // Inst #1489 = PMXVF16GER2WNP | |
| { 1488, 7, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo233 }, // Inst #1488 = PMXVF16GER2WNN | |
| { 1487, 6, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo232 }, // Inst #1487 = PMXVF16GER2W | |
| { 1486, 7, 1, 8, 452, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo231 }, // Inst #1486 = PMXVF16GER2PP | |
| { 1485, 7, 1, 8, 452, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo231 }, // Inst #1485 = PMXVF16GER2PN | |
| { 1484, 7, 1, 8, 452, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo231 }, // Inst #1484 = PMXVF16GER2NP | |
| { 1483, 7, 1, 8, 452, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo231 }, // Inst #1483 = PMXVF16GER2NN | |
| { 1482, 6, 1, 8, 451, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo230 }, // Inst #1482 = PMXVF16GER2 | |
| { 1481, 7, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo233 }, // Inst #1481 = PMXVBF16GER2WPP | |
| { 1480, 7, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo233 }, // Inst #1480 = PMXVBF16GER2WPN | |
| { 1479, 7, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo233 }, // Inst #1479 = PMXVBF16GER2WNP | |
| { 1478, 7, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo233 }, // Inst #1478 = PMXVBF16GER2WNN | |
| { 1477, 6, 1, 8, 5, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo232 }, // Inst #1477 = PMXVBF16GER2W | |
| { 1476, 7, 1, 8, 452, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo231 }, // Inst #1476 = PMXVBF16GER2PP | |
| { 1475, 7, 1, 8, 452, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo231 }, // Inst #1475 = PMXVBF16GER2PN | |
| { 1474, 7, 1, 8, 452, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo231 }, // Inst #1474 = PMXVBF16GER2NP | |
| { 1473, 7, 1, 8, 452, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo231 }, // Inst #1473 = PMXVBF16GER2NN | |
| { 1472, 6, 1, 8, 451, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo230 }, // Inst #1472 = PMXVBF16GER2 | |
| { 1471, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo229 }, // Inst #1471 = PLXVpc | |
| { 1470, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo228 }, // Inst #1470 = PLXVPpc | |
| { 1469, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo227 }, // Inst #1469 = PLXVP | |
| { 1468, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo226 }, // Inst #1468 = PLXV | |
| { 1467, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo225 }, // Inst #1467 = PLXSSPpc | |
| { 1466, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo224 }, // Inst #1466 = PLXSSP | |
| { 1465, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo225 }, // Inst #1465 = PLXSDpc | |
| { 1464, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo224 }, // Inst #1464 = PLXSD | |
| { 1463, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo219 }, // Inst #1463 = PLWZpc | |
| { 1462, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo218 }, // Inst #1462 = PLWZ8pc | |
| { 1461, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo217 }, // Inst #1461 = PLWZ8 | |
| { 1460, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo216 }, // Inst #1460 = PLWZ | |
| { 1459, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo219 }, // Inst #1459 = PLWApc | |
| { 1458, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo218 }, // Inst #1458 = PLWA8pc | |
| { 1457, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo217 }, // Inst #1457 = PLWA8 | |
| { 1456, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo216 }, // Inst #1456 = PLWA | |
| { 1455, 2, 1, 8, 497, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x80ULL, nullptr, OperandInfo63 }, // Inst #1455 = PLI8 | |
| { 1454, 2, 1, 8, 497, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x80ULL, nullptr, OperandInfo171 }, // Inst #1454 = PLI | |
| { 1453, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo219 }, // Inst #1453 = PLHZpc | |
| { 1452, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo218 }, // Inst #1452 = PLHZ8pc | |
| { 1451, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo217 }, // Inst #1451 = PLHZ8 | |
| { 1450, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo216 }, // Inst #1450 = PLHZ | |
| { 1449, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo219 }, // Inst #1449 = PLHApc | |
| { 1448, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo218 }, // Inst #1448 = PLHA8pc | |
| { 1447, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo217 }, // Inst #1447 = PLHA8 | |
| { 1446, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo216 }, // Inst #1446 = PLHA | |
| { 1445, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo223 }, // Inst #1445 = PLFSpc | |
| { 1444, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo222 }, // Inst #1444 = PLFS | |
| { 1443, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo221 }, // Inst #1443 = PLFDpc | |
| { 1442, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo220 }, // Inst #1442 = PLFD | |
| { 1441, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo218 }, // Inst #1441 = PLDpc | |
| { 1440, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo217 }, // Inst #1440 = PLD | |
| { 1439, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo219 }, // Inst #1439 = PLBZpc | |
| { 1438, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo218 }, // Inst #1438 = PLBZ8pc | |
| { 1437, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo217 }, // Inst #1437 = PLBZ8 | |
| { 1436, 3, 1, 8, 442, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, OperandInfo216 }, // Inst #1436 = PLBZ | |
| { 1435, 3, 1, 4, 338, 0, 0, 0, 0x0ULL, nullptr, OperandInfo67 }, // Inst #1435 = PEXTD | |
| { 1434, 3, 1, 4, 338, 0, 0, 0, 0x0ULL, nullptr, OperandInfo67 }, // Inst #1434 = PDEPD | |
| { 1433, 3, 1, 8, 496, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo188 }, // Inst #1433 = PADDIpc | |
| { 1432, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo73 }, // Inst #1432 = PADDIdtprel | |
| { 1431, 3, 1, 8, 496, 0, 0, 0, 0x80ULL, nullptr, OperandInfo215 }, // Inst #1431 = PADDI8pc | |
| { 1430, 3, 1, 8, 496, 0, 0, 0, 0x80ULL, nullptr, OperandInfo52 }, // Inst #1430 = PADDI8 | |
| { 1429, 3, 1, 8, 496, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, OperandInfo53 }, // Inst #1429 = PADDI | |
| { 1428, 3, 1, 4, 404, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList1, OperandInfo65 }, // Inst #1428 = OR_rec | |
| { 1427, 3, 1, 4, 404, 0, 0, 0, 0x8ULL, nullptr, OperandInfo52 }, // Inst #1427 = ORIS8 | |
| { 1426, 3, 1, 4, 404, 0, 0, 0, 0x8ULL, nullptr, OperandInfo53 }, // Inst #1426 = ORIS | |
| { 1425, 3, 1, 4, 389, 0, 0, 0, 0x8ULL, nullptr, OperandInfo52 }, // Inst #1425 = ORI8 | |
| { 1424, 3, 1, 4, 389, 0, 0, 0, 0x8ULL, nullptr, OperandInfo53 }, // Inst #1424 = ORI | |
| { 1423, 3, 1, 4, 404, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo65 }, // Inst #1423 = ORC_rec | |
| { 1422, 3, 1, 4, 404, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo67 }, // Inst #1422 = ORC8_rec | |
| { 1421, 3, 1, 4, 404, 0, 0, 0, 0x8ULL, nullptr, OperandInfo67 }, // Inst #1421 = ORC8 | |
| { 1420, 3, 1, 4, 404, 0, 0, 0, 0x8ULL, nullptr, OperandInfo65 }, // Inst #1420 = ORC | |
| { 1419, 3, 1, 4, 404, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList1, OperandInfo67 }, // Inst #1419 = OR8_rec | |
| { 1418, 3, 1, 4, 404, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo67 }, // Inst #1418 = OR8 | |
| { 1417, 3, 1, 4, 404, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo65 }, // Inst #1417 = OR | |
| { 1416, 3, 1, 4, 404, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList1, OperandInfo65 }, // Inst #1416 = NOR_rec | |
| { 1415, 3, 1, 4, 404, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList1, OperandInfo67 }, // Inst #1415 = NOR8_rec | |
| { 1414, 3, 1, 4, 404, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo67 }, // Inst #1414 = NOR8 | |
| { 1413, 3, 1, 4, 404, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo65 }, // Inst #1413 = NOR | |
| { 1412, 0, 0, 4, 309, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL, nullptr, nullptr }, // Inst #1412 = NOP_GT_PWR7 | |
| { 1411, 0, 0, 4, 309, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL, nullptr, nullptr }, // Inst #1411 = NOP_GT_PWR6 | |
| { 1410, 0, 0, 4, 389, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL, nullptr, nullptr }, // Inst #1410 = NOP | |
| { 1409, 2, 1, 4, 392, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo79 }, // Inst #1409 = NEG_rec | |
| { 1408, 2, 1, 4, 420, 0, 2, 0, 0x8ULL, ImplicitList4, OperandInfo79 }, // Inst #1408 = NEGO_rec | |
| { 1407, 2, 1, 4, 392, 0, 1, 0, 0x8ULL, ImplicitList3, OperandInfo79 }, // Inst #1407 = NEGO | |
| { 1406, 2, 1, 4, 392, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo80 }, // Inst #1406 = NEG8_rec | |
| { 1405, 2, 1, 4, 420, 0, 2, 0, 0x8ULL, ImplicitList4, OperandInfo80 }, // Inst #1405 = NEG8O_rec | |
| { 1404, 2, 1, 4, 392, 0, 1, 0, 0x8ULL, ImplicitList3, OperandInfo80 }, // Inst #1404 = NEG8O | |
| { 1403, 2, 1, 4, 392, 0, 0, 0, 0x8ULL, nullptr, OperandInfo80 }, // Inst #1403 = NEG8 | |
| { 1402, 2, 1, 4, 392, 0, 0, 0, 0x8ULL, nullptr, OperandInfo79 }, // Inst #1402 = NEG | |
| { 1401, 0, 0, 4, 490, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1401 = NAP | |
| { 1400, 3, 1, 4, 404, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList1, OperandInfo65 }, // Inst #1400 = NAND_rec | |
| { 1399, 3, 1, 4, 404, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList1, OperandInfo67 }, // Inst #1399 = NAND8_rec | |
| { 1398, 3, 1, 4, 404, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo67 }, // Inst #1398 = NAND8 | |
| { 1397, 3, 1, 4, 404, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo65 }, // Inst #1397 = NAND | |
| { 1396, 0, 0, 4, 0, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList50, nullptr }, // Inst #1396 = MovePCtoLR8 | |
| { 1395, 0, 0, 4, 0, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList49, nullptr }, // Inst #1395 = MovePCtoLR | |
| { 1394, 0, 0, 4, 0, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList49, nullptr }, // Inst #1394 = MoveGOTtoLR | |
| { 1393, 3, 1, 4, 158, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList1, OperandInfo65 }, // Inst #1393 = MULLW_rec | |
| { 1392, 3, 1, 4, 158, 0, 2, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList4, OperandInfo65 }, // Inst #1392 = MULLWO_rec | |
| { 1391, 3, 1, 4, 149, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList3, OperandInfo65 }, // Inst #1391 = MULLWO | |
| { 1390, 3, 1, 4, 149, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo65 }, // Inst #1390 = MULLW | |
| { 1389, 3, 1, 4, 151, 0, 0, 0, 0x8ULL, nullptr, OperandInfo52 }, // Inst #1389 = MULLI8 | |
| { 1388, 3, 1, 4, 151, 0, 0, 0, 0x8ULL, nullptr, OperandInfo53 }, // Inst #1388 = MULLI | |
| { 1387, 3, 1, 4, 159, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList1, OperandInfo67 }, // Inst #1387 = MULLD_rec | |
| { 1386, 3, 1, 4, 159, 0, 2, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList4, OperandInfo67 }, // Inst #1386 = MULLDO_rec | |
| { 1385, 3, 1, 4, 456, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList3, OperandInfo67 }, // Inst #1385 = MULLDO | |
| { 1384, 3, 1, 4, 456, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo67 }, // Inst #1384 = MULLD | |
| { 1383, 3, 1, 4, 158, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList1, OperandInfo65 }, // Inst #1383 = MULHW_rec | |
| { 1382, 3, 1, 4, 157, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList1, OperandInfo65 }, // Inst #1382 = MULHWU_rec | |
| { 1381, 3, 1, 4, 150, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo65 }, // Inst #1381 = MULHWU | |
| { 1380, 3, 1, 4, 149, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo65 }, // Inst #1380 = MULHW | |
| { 1379, 3, 1, 4, 158, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList1, OperandInfo67 }, // Inst #1379 = MULHD_rec | |
| { 1378, 3, 1, 4, 157, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList1, OperandInfo67 }, // Inst #1378 = MULHDU_rec | |
| { 1377, 3, 1, 4, 150, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo67 }, // Inst #1377 = MULHDU | |
| { 1376, 3, 1, 4, 149, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo67 }, // Inst #1376 = MULHD | |
| { 1375, 2, 1, 4, 117, 0, 0, 0, 0x0ULL, nullptr, OperandInfo214 }, // Inst #1375 = MTVSRWZ | |
| { 1374, 2, 1, 4, 462, 0, 0, 0, 0x0ULL, nullptr, OperandInfo209 }, // Inst #1374 = MTVSRWS | |
| { 1373, 2, 1, 4, 364, 0, 0, 0, 0x0ULL, nullptr, OperandInfo210 }, // Inst #1373 = MTVSRWM | |
| { 1372, 2, 1, 4, 117, 0, 0, 0, 0x0ULL, nullptr, OperandInfo214 }, // Inst #1372 = MTVSRWA | |
| { 1371, 2, 1, 4, 364, 0, 0, 0, 0x0ULL, nullptr, OperandInfo210 }, // Inst #1371 = MTVSRQM | |
| { 1370, 2, 1, 4, 364, 0, 0, 0, 0x0ULL, nullptr, OperandInfo210 }, // Inst #1370 = MTVSRHM | |
| { 1369, 2, 1, 4, 364, 0, 0, 0, 0x0ULL, nullptr, OperandInfo210 }, // Inst #1369 = MTVSRDM | |
| { 1368, 3, 1, 4, 101, 0, 0, 0, 0x0ULL, nullptr, OperandInfo213 }, // Inst #1368 = MTVSRDD | |
| { 1367, 2, 1, 4, 117, 0, 0, 0, 0x0ULL, nullptr, OperandInfo212 }, // Inst #1367 = MTVSRD | |
| { 1366, 2, 1, 4, 364, 0, 0, 0, 0x0ULL, nullptr, OperandInfo211 }, // Inst #1366 = MTVSRBMI | |
| { 1365, 2, 1, 4, 364, 0, 0, 0, 0x0ULL, nullptr, OperandInfo210 }, // Inst #1365 = MTVSRBM | |
| { 1364, 1, 0, 4, 141, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo197 }, // Inst #1364 = MTVSCR | |
| { 1363, 2, 1, 4, 117, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo209 }, // Inst #1363 = MTVRWZ | |
| { 1362, 2, 1, 4, 117, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo209 }, // Inst #1362 = MTVRWA | |
| { 1361, 2, 1, 4, 440, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xaULL, nullptr, OperandInfo208 }, // Inst #1361 = MTVRSAVEv | |
| { 1360, 1, 0, 4, 440, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xaULL, nullptr, OperandInfo189 }, // Inst #1360 = MTVRSAVE | |
| { 1359, 2, 1, 4, 117, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo207 }, // Inst #1359 = MTVRD | |
| { 1358, 1, 0, 4, 237, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xaULL, nullptr, OperandInfo189 }, // Inst #1358 = MTUDSCR | |
| { 1357, 2, 0, 4, 306, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo79 }, // Inst #1357 = MTSRIN | |
| { 1356, 2, 0, 4, 439, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo171 }, // Inst #1356 = MTSR | |
| { 1355, 2, 0, 4, 237, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo201 }, // Inst #1355 = MTSPR8 | |
| { 1354, 2, 0, 4, 237, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo200 }, // Inst #1354 = MTSPR | |
| { 1353, 2, 0, 4, 231, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo200 }, // Inst #1353 = MTPMR | |
| { 1352, 2, 1, 4, 132, 0, 0, 0|(1ULL<<MCID::ExtraDefRegAllocReq), 0x21ULL, nullptr, OperandInfo206 }, // Inst #1352 = MTOCRF8 | |
| { 1351, 2, 1, 4, 132, 0, 0, 0|(1ULL<<MCID::ExtraDefRegAllocReq), 0x21ULL, nullptr, OperandInfo205 }, // Inst #1351 = MTOCRF | |
| { 1350, 2, 0, 4, 236, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo171 }, // Inst #1350 = MTMSRD | |
| { 1349, 2, 0, 4, 235, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo171 }, // Inst #1349 = MTMSR | |
| { 1348, 1, 0, 4, 228, 0, 1, 0, 0x9ULL, ImplicitList50, OperandInfo49 }, // Inst #1348 = MTLR8 | |
| { 1347, 1, 0, 4, 228, 0, 1, 0, 0x9ULL, ImplicitList49, OperandInfo189 }, // Inst #1347 = MTLR | |
| { 1346, 2, 0, 4, 251, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList42, OperandInfo204 }, // Inst #1346 = MTFSFb | |
| { 1345, 4, 0, 4, 250, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList41, OperandInfo202 }, // Inst #1345 = MTFSF_rec | |
| { 1344, 2, 0, 4, 427, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList42, OperandInfo10 }, // Inst #1344 = MTFSFIb | |
| { 1343, 3, 0, 4, 428, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList41, OperandInfo203 }, // Inst #1343 = MTFSFI_rec | |
| { 1342, 3, 0, 4, 427, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList42, OperandInfo203 }, // Inst #1342 = MTFSFI | |
| { 1341, 4, 0, 4, 427, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList42, OperandInfo202 }, // Inst #1341 = MTFSF | |
| { 1340, 1, 0, 4, 105, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList42, OperandInfo3 }, // Inst #1340 = MTFSB1 | |
| { 1339, 1, 0, 4, 419, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList42, OperandInfo3 }, // Inst #1339 = MTFSB0 | |
| { 1338, 2, 0, 4, 308, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo171 }, // Inst #1338 = MTDCR | |
| { 1337, 1, 0, 4, 228, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, ImplicitList16, OperandInfo189 }, // Inst #1337 = MTCTRloop | |
| { 1336, 1, 0, 4, 228, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, ImplicitList17, OperandInfo49 }, // Inst #1336 = MTCTR8loop | |
| { 1335, 1, 0, 4, 228, 0, 1, 0, 0x9ULL, ImplicitList17, OperandInfo49 }, // Inst #1335 = MTCTR8 | |
| { 1334, 1, 0, 4, 228, 0, 1, 0, 0x9ULL, ImplicitList16, OperandInfo189 }, // Inst #1334 = MTCTR | |
| { 1333, 2, 0, 4, 246, 0, 0, 0|(1ULL<<MCID::ExtraDefRegAllocReq), 0x20ULL, nullptr, OperandInfo201 }, // Inst #1333 = MTCRF8 | |
| { 1332, 2, 0, 4, 246, 0, 0, 0|(1ULL<<MCID::ExtraDefRegAllocReq), 0x20ULL, nullptr, OperandInfo200 }, // Inst #1332 = MTCRF | |
| { 1331, 0, 0, 4, 313, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1331 = MSYNC | |
| { 1330, 0, 0, 4, 188, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1330 = MSGSYNC | |
| { 1329, 3, 1, 4, 239, 0, 0, 0, 0x0ULL, nullptr, OperandInfo65 }, // Inst #1329 = MODUW | |
| { 1328, 3, 1, 4, 239, 0, 0, 0, 0x8ULL, nullptr, OperandInfo67 }, // Inst #1328 = MODUD | |
| { 1327, 3, 1, 4, 238, 0, 0, 0, 0x0ULL, nullptr, OperandInfo65 }, // Inst #1327 = MODSW | |
| { 1326, 3, 1, 4, 239, 0, 0, 0, 0x8ULL, nullptr, OperandInfo67 }, // Inst #1326 = MODSD | |
| { 1325, 2, 1, 4, 117, 0, 0, 0, 0x200ULL, nullptr, OperandInfo199 }, // Inst #1325 = MFVSRWZ | |
| { 1324, 2, 1, 4, 462, 0, 0, 0, 0x0ULL, nullptr, OperandInfo194 }, // Inst #1324 = MFVSRLD | |
| { 1323, 2, 1, 4, 117, 0, 0, 0, 0x0ULL, nullptr, OperandInfo198 }, // Inst #1323 = MFVSRD | |
| { 1322, 1, 1, 4, 140, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo197 }, // Inst #1322 = MFVSCR | |
| { 1321, 2, 1, 4, 117, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo196 }, // Inst #1321 = MFVRWZ | |
| { 1320, 2, 1, 4, 229, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, OperandInfo195 }, // Inst #1320 = MFVRSAVEv | |
| { 1319, 1, 1, 4, 229, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, OperandInfo189 }, // Inst #1319 = MFVRSAVE | |
| { 1318, 2, 1, 4, 117, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo194 }, // Inst #1318 = MFVRD | |
| { 1317, 1, 1, 4, 233, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, OperandInfo189 }, // Inst #1317 = MFUDSCR | |
| { 1316, 1, 1, 4, 445, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, OperandInfo49 }, // Inst #1316 = MFTB8 | |
| { 1315, 2, 1, 4, 232, 0, 0, 0, 0x0ULL, nullptr, OperandInfo171 }, // Inst #1315 = MFTB | |
| { 1314, 2, 1, 4, 305, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo79 }, // Inst #1314 = MFSRIN | |
| { 1313, 2, 1, 4, 444, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo171 }, // Inst #1313 = MFSR | |
| { 1312, 2, 1, 4, 233, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo63 }, // Inst #1312 = MFSPR8 | |
| { 1311, 2, 1, 4, 233, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo171 }, // Inst #1311 = MFSPR | |
| { 1310, 2, 1, 4, 230, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo171 }, // Inst #1310 = MFPMR | |
| { 1309, 2, 1, 4, 131, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x21ULL, nullptr, OperandInfo193 }, // Inst #1309 = MFOCRF8 | |
| { 1308, 2, 1, 4, 131, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x21ULL, nullptr, OperandInfo192 }, // Inst #1308 = MFOCRF | |
| { 1307, 1, 1, 4, 234, 0, 0, 0, 0x0ULL, nullptr, OperandInfo189 }, // Inst #1307 = MFMSR | |
| { 1306, 1, 1, 4, 388, 1, 0, 0, 0x9ULL, ImplicitList50, OperandInfo49 }, // Inst #1306 = MFLR8 | |
| { 1305, 1, 1, 4, 388, 1, 0, 0, 0x9ULL, ImplicitList49, OperandInfo189 }, // Inst #1305 = MFLR | |
| { 1304, 1, 1, 4, 416, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList43, OperandInfo190 }, // Inst #1304 = MFFS_rec | |
| { 1303, 1, 1, 4, 416, 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList42, OperandInfo190 }, // Inst #1303 = MFFSL | |
| { 1302, 2, 1, 4, 106, 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList42, OperandInfo191 }, // Inst #1302 = MFFSCRNI | |
| { 1301, 2, 1, 4, 106, 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList42, OperandInfo138 }, // Inst #1301 = MFFSCRN | |
| { 1300, 1, 1, 4, 257, 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList42, OperandInfo190 }, // Inst #1300 = MFFSCE | |
| { 1299, 2, 1, 4, 106, 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList42, OperandInfo191 }, // Inst #1299 = MFFSCDRNI | |
| { 1298, 2, 1, 4, 106, 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList42, OperandInfo138 }, // Inst #1298 = MFFSCDRN | |
| { 1297, 1, 1, 4, 416, 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList42, OperandInfo190 }, // Inst #1297 = MFFS | |
| { 1296, 2, 1, 4, 307, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo171 }, // Inst #1296 = MFDCR | |
| { 1295, 1, 1, 4, 388, 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, ImplicitList17, OperandInfo49 }, // Inst #1295 = MFCTR8 | |
| { 1294, 1, 1, 4, 388, 1, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, ImplicitList16, OperandInfo189 }, // Inst #1294 = MFCTR | |
| { 1293, 1, 1, 4, 258, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x20ULL, nullptr, OperandInfo49 }, // Inst #1293 = MFCR8 | |
| { 1292, 1, 1, 4, 258, 0, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x20ULL, nullptr, OperandInfo189 }, // Inst #1292 = MFCR | |
| { 1291, 3, 1, 4, 495, 0, 0, 0, 0x1ULL, nullptr, OperandInfo188 }, // Inst #1291 = MFBHRBE | |
| { 1290, 1, 1, 4, 123, 0, 0, 0, 0x0ULL, nullptr, OperandInfo187 }, // Inst #1290 = MCRXRX | |
| { 1289, 2, 1, 4, 249, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo186 }, // Inst #1289 = MCRFS | |
| { 1288, 2, 1, 4, 122, 0, 0, 0, 0x21ULL, nullptr, OperandInfo186 }, // Inst #1288 = MCRF | |
| { 1287, 1, 0, 4, 301, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo3 }, // Inst #1287 = MBAR | |
| { 1286, 4, 1, 4, 148, 0, 0, 0, 0x8ULL, nullptr, OperandInfo184 }, // Inst #1286 = MADDLD8 | |
| { 1285, 4, 1, 4, 148, 0, 0, 0, 0x8ULL, nullptr, OperandInfo185 }, // Inst #1285 = MADDLD | |
| { 1284, 4, 1, 4, 148, 0, 0, 0, 0x8ULL, nullptr, OperandInfo184 }, // Inst #1284 = MADDHDU | |
| { 1283, 4, 1, 4, 148, 0, 0, 0, 0x8ULL, nullptr, OperandInfo184 }, // Inst #1283 = MADDHD | |
| { 1282, 3, 1, 4, 177, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1282 = LXVX | |
| { 1281, 3, 1, 4, 177, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1281 = LXVWSX | |
| { 1280, 3, 1, 4, 216, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1280 = LXVW4X | |
| { 1279, 3, 1, 4, 433, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1279 = LXVRWX | |
| { 1278, 3, 1, 4, 14, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL, nullptr, OperandInfo180 }, // Inst #1278 = LXVRLL | |
| { 1277, 3, 1, 4, 14, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL, nullptr, OperandInfo180 }, // Inst #1277 = LXVRL | |
| { 1276, 3, 1, 4, 433, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1276 = LXVRHX | |
| { 1275, 3, 1, 4, 433, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1275 = LXVRDX | |
| { 1274, 3, 1, 4, 433, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1274 = LXVRBX | |
| { 1273, 3, 1, 4, 443, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo183 }, // Inst #1273 = LXVPX | |
| { 1272, 3, 1, 4, 40, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL, nullptr, OperandInfo182 }, // Inst #1272 = LXVPRLL | |
| { 1271, 3, 1, 4, 40, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL, nullptr, OperandInfo182 }, // Inst #1271 = LXVPRL | |
| { 1270, 3, 1, 4, 443, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo181 }, // Inst #1270 = LXVP | |
| { 1269, 3, 1, 4, 175, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo180 }, // Inst #1269 = LXVLL | |
| { 1268, 3, 1, 4, 175, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo180 }, // Inst #1268 = LXVL | |
| { 1267, 2, 1, 4, 461, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo179 }, // Inst #1267 = LXVKQ | |
| { 1266, 3, 1, 4, 216, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1266 = LXVH8X | |
| { 1265, 3, 1, 4, 216, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1265 = LXVDSX | |
| { 1264, 3, 1, 4, 177, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1264 = LXVD2X | |
| { 1263, 3, 1, 4, 177, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo178 }, // Inst #1263 = LXVB16X | |
| { 1262, 3, 1, 4, 177, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo177 }, // Inst #1262 = LXV | |
| { 1261, 3, 1, 4, 212, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo64 }, // Inst #1261 = LXSSPX | |
| { 1260, 3, 1, 4, 212, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo176 }, // Inst #1260 = LXSSP | |
| { 1259, 3, 1, 4, 177, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo60 }, // Inst #1259 = LXSIWZX | |
| { 1258, 3, 1, 4, 209, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo60 }, // Inst #1258 = LXSIWAX | |
| { 1257, 3, 1, 4, 177, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo60 }, // Inst #1257 = LXSIHZX | |
| { 1256, 3, 1, 4, 177, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo60 }, // Inst #1256 = LXSIBZX | |
| { 1255, 3, 1, 4, 177, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo60 }, // Inst #1255 = LXSDX | |
| { 1254, 3, 1, 4, 177, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo176 }, // Inst #1254 = LXSD | |
| { 1253, 3, 1, 4, 432, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo175 }, // Inst #1253 = LWZtocL | |
| { 1252, 3, 1, 4, 432, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo77 }, // Inst #1252 = LWZtoc | |
| { 1251, 3, 1, 4, 435, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, OperandInfo159 }, // Inst #1251 = LWZXTLS_32 | |
| { 1250, 3, 1, 4, 435, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, OperandInfo158 }, // Inst #1250 = LWZXTLS_ | |
| { 1249, 3, 1, 4, 435, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, OperandInfo158 }, // Inst #1249 = LWZXTLS | |
| { 1248, 3, 1, 4, 435, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x250ULL, nullptr, OperandInfo157 }, // Inst #1248 = LWZX8 | |
| { 1247, 3, 1, 4, 435, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x250ULL, nullptr, OperandInfo152 }, // Inst #1247 = LWZX | |
| { 1246, 4, 2, 4, 200, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo156 }, // Inst #1246 = LWZUX8 | |
| { 1245, 4, 2, 4, 200, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo155 }, // Inst #1245 = LWZUX | |
| { 1244, 4, 2, 4, 199, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, OperandInfo154 }, // Inst #1244 = LWZU8 | |
| { 1243, 4, 2, 4, 199, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, OperandInfo153 }, // Inst #1243 = LWZU | |
| { 1242, 3, 1, 4, 438, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL, nullptr, OperandInfo65 }, // Inst #1242 = LWZCIX | |
| { 1241, 3, 1, 4, 430, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x210ULL, nullptr, OperandInfo149 }, // Inst #1241 = LWZ8 | |
| { 1240, 3, 1, 4, 430, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x210ULL, nullptr, OperandInfo59 }, // Inst #1240 = LWZ | |
| { 1239, 3, 1, 4, 301, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo152 }, // Inst #1239 = LWEPX | |
| { 1238, 3, 1, 4, 430, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x250ULL, nullptr, OperandInfo157 }, // Inst #1238 = LWBRX8 | |
| { 1237, 3, 1, 4, 430, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x250ULL, nullptr, OperandInfo152 }, // Inst #1237 = LWBRX | |
| { 1236, 3, 1, 4, 206, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x114ULL, nullptr, OperandInfo59 }, // Inst #1236 = LWA_32 | |
| { 1235, 3, 1, 4, 204, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x154ULL, nullptr, OperandInfo152 }, // Inst #1235 = LWAX_32 | |
| { 1234, 3, 1, 4, 204, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x154ULL, nullptr, OperandInfo157 }, // Inst #1234 = LWAX | |
| { 1233, 4, 2, 4, 215, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo156 }, // Inst #1233 = LWAUX | |
| { 1232, 3, 1, 4, 291, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x40ULL, nullptr, OperandInfo53 }, // Inst #1232 = LWAT | |
| { 1231, 3, 1, 4, 183, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo152 }, // Inst #1231 = LWARXL | |
| { 1230, 3, 1, 4, 183, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo152 }, // Inst #1230 = LWARX | |
| { 1229, 3, 1, 4, 206, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x114ULL, nullptr, OperandInfo149 }, // Inst #1229 = LWA | |
| { 1228, 3, 1, 4, 176, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo174 }, // Inst #1228 = LVXL | |
| { 1227, 3, 1, 4, 176, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo174 }, // Inst #1227 = LVX | |
| { 1226, 3, 1, 4, 164, 0, 0, 0, 0x50ULL, nullptr, OperandInfo174 }, // Inst #1226 = LVSR | |
| { 1225, 3, 1, 4, 164, 0, 0, 0, 0x50ULL, nullptr, OperandInfo174 }, // Inst #1225 = LVSL | |
| { 1224, 3, 1, 4, 176, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo174 }, // Inst #1224 = LVEWX | |
| { 1223, 3, 1, 4, 176, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo174 }, // Inst #1223 = LVEHX | |
| { 1222, 3, 1, 4, 176, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo174 }, // Inst #1222 = LVEBX | |
| { 1221, 3, 1, 4, 441, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL, nullptr, OperandInfo53 }, // Inst #1221 = LSWI | |
| { 1220, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo173 }, // Inst #1220 = LQX_PSEUDO | |
| { 1219, 3, 1, 4, 48, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo173 }, // Inst #1219 = LQARXL | |
| { 1218, 3, 1, 4, 48, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo173 }, // Inst #1218 = LQARX | |
| { 1217, 3, 1, 4, 47, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo172 }, // Inst #1217 = LQ | |
| { 1216, 3, 1, 4, 191, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo59 }, // Inst #1216 = LMW | |
| { 1215, 2, 1, 4, 392, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x108ULL, nullptr, OperandInfo63 }, // Inst #1215 = LIS8 | |
| { 1214, 2, 1, 4, 392, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x108ULL, nullptr, OperandInfo171 }, // Inst #1214 = LIS | |
| { 1213, 2, 1, 4, 392, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x108ULL, nullptr, OperandInfo63 }, // Inst #1213 = LI8 | |
| { 1212, 2, 1, 4, 392, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x108ULL, nullptr, OperandInfo171 }, // Inst #1212 = LI | |
| { 1211, 3, 1, 4, 435, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, OperandInfo159 }, // Inst #1211 = LHZXTLS_32 | |
| { 1210, 3, 1, 4, 435, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, OperandInfo158 }, // Inst #1210 = LHZXTLS_ | |
| { 1209, 3, 1, 4, 435, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, OperandInfo158 }, // Inst #1209 = LHZXTLS | |
| { 1208, 3, 1, 4, 435, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x350ULL, nullptr, OperandInfo157 }, // Inst #1208 = LHZX8 | |
| { 1207, 3, 1, 4, 435, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x350ULL, nullptr, OperandInfo152 }, // Inst #1207 = LHZX | |
| { 1206, 4, 2, 4, 200, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo156 }, // Inst #1206 = LHZUX8 | |
| { 1205, 4, 2, 4, 200, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo155 }, // Inst #1205 = LHZUX | |
| { 1204, 4, 2, 4, 199, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, OperandInfo154 }, // Inst #1204 = LHZU8 | |
| { 1203, 4, 2, 4, 199, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, OperandInfo153 }, // Inst #1203 = LHZU | |
| { 1202, 3, 1, 4, 438, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL, nullptr, OperandInfo65 }, // Inst #1202 = LHZCIX | |
| { 1201, 3, 1, 4, 430, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x310ULL, nullptr, OperandInfo149 }, // Inst #1201 = LHZ8 | |
| { 1200, 3, 1, 4, 430, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x310ULL, nullptr, OperandInfo59 }, // Inst #1200 = LHZ | |
| { 1199, 3, 1, 4, 301, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo152 }, // Inst #1199 = LHEPX | |
| { 1198, 3, 1, 4, 430, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x250ULL, nullptr, OperandInfo157 }, // Inst #1198 = LHBRX8 | |
| { 1197, 3, 1, 4, 430, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x250ULL, nullptr, OperandInfo152 }, // Inst #1197 = LHBRX | |
| { 1196, 3, 1, 4, 204, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x154ULL, nullptr, OperandInfo157 }, // Inst #1196 = LHAX8 | |
| { 1195, 3, 1, 4, 204, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x154ULL, nullptr, OperandInfo152 }, // Inst #1195 = LHAX | |
| { 1194, 4, 2, 4, 215, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo156 }, // Inst #1194 = LHAUX8 | |
| { 1193, 4, 2, 4, 215, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo155 }, // Inst #1193 = LHAUX | |
| { 1192, 4, 2, 4, 214, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, OperandInfo154 }, // Inst #1192 = LHAU8 | |
| { 1191, 4, 2, 4, 214, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, OperandInfo153 }, // Inst #1191 = LHAU | |
| { 1190, 3, 1, 4, 183, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo152 }, // Inst #1190 = LHARXL | |
| { 1189, 3, 1, 4, 183, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo152 }, // Inst #1189 = LHARX | |
| { 1188, 3, 1, 4, 204, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x114ULL, nullptr, OperandInfo149 }, // Inst #1188 = LHA8 | |
| { 1187, 3, 1, 4, 204, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x114ULL, nullptr, OperandInfo59 }, // Inst #1187 = LHA | |
| { 1186, 3, 1, 4, 211, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo170 }, // Inst #1186 = LFSX | |
| { 1185, 4, 2, 4, 278, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo169 }, // Inst #1185 = LFSUX | |
| { 1184, 4, 2, 4, 277, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, OperandInfo168 }, // Inst #1184 = LFSU | |
| { 1183, 3, 1, 4, 211, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, OperandInfo167 }, // Inst #1183 = LFS | |
| { 1182, 3, 1, 4, 192, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo164 }, // Inst #1182 = LFIWZX | |
| { 1181, 3, 1, 4, 208, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo164 }, // Inst #1181 = LFIWAX | |
| { 1180, 3, 1, 4, 192, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo164 }, // Inst #1180 = LFDX | |
| { 1179, 4, 2, 4, 287, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo166 }, // Inst #1179 = LFDUX | |
| { 1178, 4, 2, 4, 286, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, OperandInfo165 }, // Inst #1178 = LFDU | |
| { 1177, 3, 1, 4, 303, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo164 }, // Inst #1177 = LFDEPX | |
| { 1176, 3, 1, 4, 192, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, OperandInfo163 }, // Inst #1176 = LFD | |
| { 1175, 3, 1, 4, 432, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo78 }, // Inst #1175 = LDtocL | |
| { 1174, 3, 1, 4, 432, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, OperandInfo162 }, // Inst #1174 = LDtocJTI | |
| { 1173, 3, 1, 4, 432, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, OperandInfo162 }, // Inst #1173 = LDtocCPT | |
| { 1172, 3, 1, 4, 432, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, OperandInfo162 }, // Inst #1172 = LDtocBA | |
| { 1171, 3, 1, 4, 432, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, OperandInfo162 }, // Inst #1171 = LDtoc | |
| { 1170, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo161 }, // Inst #1170 = LDgotTprelL32 | |
| { 1169, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo160 }, // Inst #1169 = LDgotTprelL | |
| { 1168, 3, 1, 4, 436, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, OperandInfo158 }, // Inst #1168 = LDXTLS_ | |
| { 1167, 3, 1, 4, 436, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, OperandInfo158 }, // Inst #1167 = LDXTLS | |
| { 1166, 3, 1, 4, 436, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo157 }, // Inst #1166 = LDX | |
| { 1165, 4, 2, 4, 285, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo156 }, // Inst #1165 = LDUX | |
| { 1164, 4, 2, 4, 284, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, OperandInfo154 }, // Inst #1164 = LDU | |
| { 1163, 3, 1, 4, 438, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL, nullptr, OperandInfo65 }, // Inst #1163 = LDCIX | |
| { 1162, 3, 1, 4, 430, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo157 }, // Inst #1162 = LDBRX | |
| { 1161, 3, 1, 4, 291, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x40ULL, nullptr, OperandInfo52 }, // Inst #1161 = LDAT | |
| { 1160, 3, 1, 4, 185, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo157 }, // Inst #1160 = LDARXL | |
| { 1159, 3, 1, 4, 185, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo157 }, // Inst #1159 = LDARX | |
| { 1158, 3, 1, 4, 431, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, OperandInfo149 }, // Inst #1158 = LD | |
| { 1157, 3, 1, 4, 435, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, OperandInfo159 }, // Inst #1157 = LBZXTLS_32 | |
| { 1156, 3, 1, 4, 435, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, OperandInfo158 }, // Inst #1156 = LBZXTLS_ | |
| { 1155, 3, 1, 4, 435, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, OperandInfo158 }, // Inst #1155 = LBZXTLS | |
| { 1154, 3, 1, 4, 435, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x350ULL, nullptr, OperandInfo157 }, // Inst #1154 = LBZX8 | |
| { 1153, 3, 1, 4, 435, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x350ULL, nullptr, OperandInfo152 }, // Inst #1153 = LBZX | |
| { 1152, 4, 2, 4, 283, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo156 }, // Inst #1152 = LBZUX8 | |
| { 1151, 4, 2, 4, 283, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x50ULL, nullptr, OperandInfo155 }, // Inst #1151 = LBZUX | |
| { 1150, 4, 2, 4, 282, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, OperandInfo154 }, // Inst #1150 = LBZU8 | |
| { 1149, 4, 2, 4, 282, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, OperandInfo153 }, // Inst #1149 = LBZU | |
| { 1148, 3, 1, 4, 438, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x40ULL, nullptr, OperandInfo65 }, // Inst #1148 = LBZCIX | |
| { 1147, 3, 1, 4, 430, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x310ULL, nullptr, OperandInfo149 }, // Inst #1147 = LBZ8 | |
| { 1146, 3, 1, 4, 430, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x310ULL, nullptr, OperandInfo59 }, // Inst #1146 = LBZ | |
| { 1145, 3, 1, 4, 301, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo152 }, // Inst #1145 = LBEPX | |
| { 1144, 3, 1, 4, 183, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo152 }, // Inst #1144 = LBARXL | |
| { 1143, 3, 1, 4, 183, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo152 }, // Inst #1143 = LBARX | |
| { 1142, 3, 1, 4, 119, 0, 0, 0, 0x8ULL, nullptr, OperandInfo73 }, // Inst #1142 = LA8 | |
| { 1141, 3, 1, 4, 119, 0, 0, 0, 0x8ULL, nullptr, OperandInfo72 }, // Inst #1141 = LA | |
| { 1140, 0, 0, 4, 187, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1140 = ISYNC | |
| { 1139, 4, 1, 4, 137, 0, 0, 0|(1ULL<<MCID::Select), 0x8ULL, nullptr, OperandInfo151 }, // Inst #1139 = ISEL8 | |
| { 1138, 4, 1, 4, 137, 0, 0, 0|(1ULL<<MCID::Select), 0x8ULL, nullptr, OperandInfo150 }, // Inst #1138 = ISEL | |
| { 1137, 2, 0, 4, 492, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo79 }, // Inst #1137 = ICCCI | |
| { 1136, 3, 0, 4, 182, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo106 }, // Inst #1136 = ICBTLS | |
| { 1135, 3, 0, 4, 435, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo106 }, // Inst #1135 = ICBT | |
| { 1134, 3, 0, 4, 492, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo106 }, // Inst #1134 = ICBLQ | |
| { 1133, 3, 0, 4, 493, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo106 }, // Inst #1133 = ICBLC | |
| { 1132, 2, 0, 4, 181, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #1132 = ICBIEP | |
| { 1131, 2, 0, 4, 477, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #1131 = ICBI | |
| { 1130, 0, 0, 4, 422, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1130 = HRFID | |
| { 1129, 3, 0, 4, 343, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo149 }, // Inst #1129 = HASHSTP8 | |
| { 1128, 3, 0, 4, 343, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #1128 = HASHSTP | |
| { 1127, 3, 0, 4, 343, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo149 }, // Inst #1127 = HASHST8 | |
| { 1126, 3, 0, 4, 343, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #1126 = HASHST | |
| { 1125, 3, 0, 4, 312, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo149 }, // Inst #1125 = HASHCHKP8 | |
| { 1124, 3, 0, 4, 312, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #1124 = HASHCHKP | |
| { 1123, 3, 0, 4, 312, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo149 }, // Inst #1123 = HASHCHK8 | |
| { 1122, 3, 0, 4, 312, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #1122 = HASHCHK | |
| { 1121, 3, 1, 4, 0, 0, 18, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList48, OperandInfo69 }, // Inst #1121 = GETtlsldADDRPCREL | |
| { 1120, 3, 1, 4, 0, 0, 17, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList45, OperandInfo66 }, // Inst #1120 = GETtlsldADDR32 | |
| { 1119, 3, 1, 4, 0, 0, 17, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList44, OperandInfo69 }, // Inst #1119 = GETtlsldADDR | |
| { 1118, 3, 1, 8, 0, 0, 18, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList48, OperandInfo69 }, // Inst #1118 = GETtlsADDRPCREL | |
| { 1117, 3, 1, 4, 0, 0, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList47, OperandInfo67 }, // Inst #1117 = GETtlsADDR64AIX | |
| { 1116, 3, 1, 4, 0, 0, 6, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList46, OperandInfo65 }, // Inst #1116 = GETtlsADDR32AIX | |
| { 1115, 3, 1, 4, 0, 0, 17, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList45, OperandInfo66 }, // Inst #1115 = GETtlsADDR32 | |
| { 1114, 3, 1, 8, 0, 0, 17, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList44, OperandInfo69 }, // Inst #1114 = GETtlsADDR | |
| { 1113, 2, 1, 4, 363, 0, 0, 0, 0x18ULL, nullptr, OperandInfo148 }, // Inst #1113 = FTSQRT | |
| { 1112, 3, 1, 4, 110, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x18ULL, nullptr, OperandInfo143 }, // Inst #1112 = FTDIV | |
| { 1111, 3, 1, 4, 161, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList43, OperandInfo140 }, // Inst #1111 = FSUB_rec | |
| { 1110, 3, 1, 4, 330, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList43, OperandInfo141 }, // Inst #1110 = FSUBS_rec | |
| { 1109, 3, 1, 4, 322, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList42, OperandInfo141 }, // Inst #1109 = FSUBS | |
| { 1108, 3, 1, 4, 153, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList42, OperandInfo140 }, // Inst #1108 = FSUB | |
| { 1107, 2, 1, 4, 267, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList43, OperandInfo138 }, // Inst #1107 = FSQRT_rec | |
| { 1106, 2, 1, 4, 270, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList43, OperandInfo139 }, // Inst #1106 = FSQRTS_rec | |
| { 1105, 2, 1, 4, 269, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList42, OperandInfo139 }, // Inst #1105 = FSQRTS | |
| { 1104, 2, 1, 4, 264, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList42, OperandInfo138 }, // Inst #1104 = FSQRT | |
| { 1103, 4, 1, 4, 156, 0, 1, 0, 0x18ULL, ImplicitList41, OperandInfo147 }, // Inst #1103 = FSELS_rec | |
| { 1102, 4, 1, 4, 152, 0, 0, 0, 0x18ULL, nullptr, OperandInfo147 }, // Inst #1102 = FSELS | |
| { 1101, 4, 1, 4, 156, 0, 1, 0, 0x18ULL, ImplicitList41, OperandInfo145 }, // Inst #1101 = FSELD_rec | |
| { 1100, 4, 1, 4, 152, 0, 0, 0, 0x18ULL, nullptr, OperandInfo145 }, // Inst #1100 = FSELD | |
| { 1099, 2, 1, 4, 332, 0, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList41, OperandInfo138 }, // Inst #1099 = FRSQRTE_rec | |
| { 1098, 2, 1, 4, 332, 0, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList41, OperandInfo139 }, // Inst #1098 = FRSQRTES_rec | |
| { 1097, 2, 1, 4, 318, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, nullptr, OperandInfo139 }, // Inst #1097 = FRSQRTES | |
| { 1096, 2, 1, 4, 318, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, nullptr, OperandInfo138 }, // Inst #1096 = FRSQRTE | |
| { 1095, 2, 1, 4, 332, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList43, OperandInfo142 }, // Inst #1095 = FRSP_rec | |
| { 1094, 2, 1, 4, 318, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList42, OperandInfo142 }, // Inst #1094 = FRSP | |
| { 1093, 2, 1, 4, 332, 0, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList41, OperandInfo139 }, // Inst #1093 = FRIZS_rec | |
| { 1092, 2, 1, 4, 318, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, nullptr, OperandInfo139 }, // Inst #1092 = FRIZS | |
| { 1091, 2, 1, 4, 332, 0, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList41, OperandInfo138 }, // Inst #1091 = FRIZD_rec | |
| { 1090, 2, 1, 4, 318, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, nullptr, OperandInfo138 }, // Inst #1090 = FRIZD | |
| { 1089, 2, 1, 4, 332, 0, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList41, OperandInfo139 }, // Inst #1089 = FRIPS_rec | |
| { 1088, 2, 1, 4, 318, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, nullptr, OperandInfo139 }, // Inst #1088 = FRIPS | |
| { 1087, 2, 1, 4, 332, 0, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList41, OperandInfo138 }, // Inst #1087 = FRIPD_rec | |
| { 1086, 2, 1, 4, 318, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, nullptr, OperandInfo138 }, // Inst #1086 = FRIPD | |
| { 1085, 2, 1, 4, 332, 0, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList41, OperandInfo139 }, // Inst #1085 = FRINS_rec | |
| { 1084, 2, 1, 4, 318, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, nullptr, OperandInfo139 }, // Inst #1084 = FRINS | |
| { 1083, 2, 1, 4, 332, 0, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList41, OperandInfo138 }, // Inst #1083 = FRIND_rec | |
| { 1082, 2, 1, 4, 318, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, nullptr, OperandInfo138 }, // Inst #1082 = FRIND | |
| { 1081, 2, 1, 4, 332, 0, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList41, OperandInfo139 }, // Inst #1081 = FRIMS_rec | |
| { 1080, 2, 1, 4, 318, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, nullptr, OperandInfo139 }, // Inst #1080 = FRIMS | |
| { 1079, 2, 1, 4, 332, 0, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList41, OperandInfo138 }, // Inst #1079 = FRIMD_rec | |
| { 1078, 2, 1, 4, 318, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, nullptr, OperandInfo138 }, // Inst #1078 = FRIMD | |
| { 1077, 2, 1, 4, 332, 0, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList41, OperandInfo138 }, // Inst #1077 = FRE_rec | |
| { 1076, 2, 1, 4, 332, 0, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList41, OperandInfo139 }, // Inst #1076 = FRES_rec | |
| { 1075, 2, 1, 4, 318, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, nullptr, OperandInfo139 }, // Inst #1075 = FRES | |
| { 1074, 2, 1, 4, 318, 0, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, nullptr, OperandInfo138 }, // Inst #1074 = FRE | |
| { 1073, 4, 1, 4, 162, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList43, OperandInfo145 }, // Inst #1073 = FNMSUB_rec | |
| { 1072, 4, 1, 4, 160, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList43, OperandInfo146 }, // Inst #1072 = FNMSUBS_rec | |
| { 1071, 4, 1, 4, 152, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList42, OperandInfo146 }, // Inst #1071 = FNMSUBS | |
| { 1070, 4, 1, 4, 154, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList42, OperandInfo145 }, // Inst #1070 = FNMSUB | |
| { 1069, 4, 1, 4, 162, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList43, OperandInfo145 }, // Inst #1069 = FNMADD_rec | |
| { 1068, 4, 1, 4, 160, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList43, OperandInfo146 }, // Inst #1068 = FNMADDS_rec | |
| { 1067, 4, 1, 4, 152, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList42, OperandInfo146 }, // Inst #1067 = FNMADDS | |
| { 1066, 4, 1, 4, 154, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList42, OperandInfo145 }, // Inst #1066 = FNMADD | |
| { 1065, 2, 1, 4, 423, 0, 1, 0, 0x18ULL, ImplicitList41, OperandInfo139 }, // Inst #1065 = FNEGS_rec | |
| { 1064, 2, 1, 4, 396, 0, 0, 0, 0x18ULL, nullptr, OperandInfo139 }, // Inst #1064 = FNEGS | |
| { 1063, 2, 1, 4, 423, 0, 1, 0, 0x18ULL, ImplicitList41, OperandInfo138 }, // Inst #1063 = FNEGD_rec | |
| { 1062, 2, 1, 4, 396, 0, 0, 0, 0x18ULL, nullptr, OperandInfo138 }, // Inst #1062 = FNEGD | |
| { 1061, 2, 1, 4, 423, 0, 1, 0, 0x18ULL, ImplicitList41, OperandInfo139 }, // Inst #1061 = FNABSS_rec | |
| { 1060, 2, 1, 4, 396, 0, 0, 0, 0x18ULL, nullptr, OperandInfo139 }, // Inst #1060 = FNABSS | |
| { 1059, 2, 1, 4, 423, 0, 1, 0, 0x18ULL, ImplicitList41, OperandInfo138 }, // Inst #1059 = FNABSD_rec | |
| { 1058, 2, 1, 4, 396, 0, 0, 0, 0x18ULL, nullptr, OperandInfo138 }, // Inst #1058 = FNABSD | |
| { 1057, 3, 1, 4, 331, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList43, OperandInfo140 }, // Inst #1057 = FMUL_rec | |
| { 1056, 3, 1, 4, 330, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList43, OperandInfo141 }, // Inst #1056 = FMULS_rec | |
| { 1055, 3, 1, 4, 322, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList42, OperandInfo141 }, // Inst #1055 = FMULS | |
| { 1054, 3, 1, 4, 323, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList42, OperandInfo140 }, // Inst #1054 = FMUL | |
| { 1053, 4, 1, 4, 162, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList43, OperandInfo145 }, // Inst #1053 = FMSUB_rec | |
| { 1052, 4, 1, 4, 160, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList43, OperandInfo146 }, // Inst #1052 = FMSUBS_rec | |
| { 1051, 4, 1, 4, 152, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList42, OperandInfo146 }, // Inst #1051 = FMSUBS | |
| { 1050, 4, 1, 4, 154, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList42, OperandInfo145 }, // Inst #1050 = FMSUB | |
| { 1049, 2, 1, 4, 423, 0, 1, 0, 0x0ULL, ImplicitList41, OperandInfo139 }, // Inst #1049 = FMR_rec | |
| { 1048, 2, 1, 4, 396, 0, 0, 0, 0x0ULL, nullptr, OperandInfo139 }, // Inst #1048 = FMR | |
| { 1047, 4, 1, 4, 162, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList43, OperandInfo145 }, // Inst #1047 = FMADD_rec | |
| { 1046, 4, 1, 4, 160, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList43, OperandInfo146 }, // Inst #1046 = FMADDS_rec | |
| { 1045, 4, 1, 4, 152, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList42, OperandInfo146 }, // Inst #1045 = FMADDS | |
| { 1044, 4, 1, 4, 154, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList42, OperandInfo145 }, // Inst #1044 = FMADD | |
| { 1043, 3, 1, 4, 262, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList43, OperandInfo140 }, // Inst #1043 = FDIV_rec | |
| { 1042, 3, 1, 4, 273, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList43, OperandInfo141 }, // Inst #1042 = FDIVS_rec | |
| { 1041, 3, 1, 4, 272, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList42, OperandInfo141 }, // Inst #1041 = FDIVS | |
| { 1040, 3, 1, 4, 261, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList42, OperandInfo140 }, // Inst #1040 = FDIV | |
| { 1039, 2, 1, 4, 332, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList43, OperandInfo138 }, // Inst #1039 = FCTIW_rec | |
| { 1038, 2, 1, 4, 332, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList43, OperandInfo138 }, // Inst #1038 = FCTIWZ_rec | |
| { 1037, 2, 1, 4, 318, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList42, OperandInfo138 }, // Inst #1037 = FCTIWZ | |
| { 1036, 2, 1, 4, 332, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList43, OperandInfo138 }, // Inst #1036 = FCTIWU_rec | |
| { 1035, 2, 1, 4, 332, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList43, OperandInfo138 }, // Inst #1035 = FCTIWUZ_rec | |
| { 1034, 2, 1, 4, 318, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList42, OperandInfo138 }, // Inst #1034 = FCTIWUZ | |
| { 1033, 2, 1, 4, 318, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList42, OperandInfo138 }, // Inst #1033 = FCTIWU | |
| { 1032, 2, 1, 4, 318, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList42, OperandInfo138 }, // Inst #1032 = FCTIW | |
| { 1031, 2, 1, 4, 332, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList43, OperandInfo138 }, // Inst #1031 = FCTID_rec | |
| { 1030, 2, 1, 4, 332, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList43, OperandInfo138 }, // Inst #1030 = FCTIDZ_rec | |
| { 1029, 2, 1, 4, 318, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList42, OperandInfo138 }, // Inst #1029 = FCTIDZ | |
| { 1028, 2, 1, 4, 332, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList43, OperandInfo138 }, // Inst #1028 = FCTIDU_rec | |
| { 1027, 2, 1, 4, 332, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList43, OperandInfo138 }, // Inst #1027 = FCTIDUZ_rec | |
| { 1026, 2, 1, 4, 318, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList42, OperandInfo138 }, // Inst #1026 = FCTIDUZ | |
| { 1025, 2, 1, 4, 318, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList42, OperandInfo138 }, // Inst #1025 = FCTIDU | |
| { 1024, 2, 1, 4, 318, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList42, OperandInfo138 }, // Inst #1024 = FCTID | |
| { 1023, 3, 1, 4, 248, 0, 1, 0, 0x18ULL, ImplicitList41, OperandInfo141 }, // Inst #1023 = FCPSGNS_rec | |
| { 1022, 3, 1, 4, 135, 0, 0, 0, 0x18ULL, nullptr, OperandInfo141 }, // Inst #1022 = FCPSGNS | |
| { 1021, 3, 1, 4, 248, 0, 1, 0, 0x18ULL, ImplicitList41, OperandInfo140 }, // Inst #1021 = FCPSGND_rec | |
| { 1020, 3, 1, 4, 135, 0, 0, 0, 0x18ULL, nullptr, OperandInfo140 }, // Inst #1020 = FCPSGND | |
| { 1019, 3, 1, 4, 110, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, nullptr, OperandInfo144 }, // Inst #1019 = FCMPUS | |
| { 1018, 3, 1, 4, 110, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, nullptr, OperandInfo143 }, // Inst #1018 = FCMPUD | |
| { 1017, 3, 1, 4, 110, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, nullptr, OperandInfo144 }, // Inst #1017 = FCMPOS | |
| { 1016, 3, 1, 4, 110, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, nullptr, OperandInfo143 }, // Inst #1016 = FCMPOD | |
| { 1015, 2, 1, 4, 332, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList43, OperandInfo138 }, // Inst #1015 = FCFID_rec | |
| { 1014, 2, 1, 4, 332, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList43, OperandInfo138 }, // Inst #1014 = FCFIDU_rec | |
| { 1013, 2, 1, 4, 332, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList43, OperandInfo142 }, // Inst #1013 = FCFIDUS_rec | |
| { 1012, 2, 1, 4, 318, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList42, OperandInfo142 }, // Inst #1012 = FCFIDUS | |
| { 1011, 2, 1, 4, 318, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList42, OperandInfo138 }, // Inst #1011 = FCFIDU | |
| { 1010, 2, 1, 4, 332, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList43, OperandInfo142 }, // Inst #1010 = FCFIDS_rec | |
| { 1009, 2, 1, 4, 318, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList42, OperandInfo142 }, // Inst #1009 = FCFIDS | |
| { 1008, 2, 1, 4, 318, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException), 0x18ULL, ImplicitList42, OperandInfo138 }, // Inst #1008 = FCFID | |
| { 1007, 3, 1, 4, 0, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList42, OperandInfo140 }, // Inst #1007 = FADDrtz | |
| { 1006, 3, 1, 4, 161, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList43, OperandInfo140 }, // Inst #1006 = FADD_rec | |
| { 1005, 3, 1, 4, 330, 1, 1, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList43, OperandInfo141 }, // Inst #1005 = FADDS_rec | |
| { 1004, 3, 1, 4, 322, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList42, OperandInfo141 }, // Inst #1004 = FADDS | |
| { 1003, 3, 1, 4, 153, 1, 0, 0|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList42, OperandInfo140 }, // Inst #1003 = FADD | |
| { 1002, 2, 1, 4, 423, 0, 1, 0, 0x18ULL, ImplicitList41, OperandInfo139 }, // Inst #1002 = FABSS_rec | |
| { 1001, 2, 1, 4, 396, 0, 0, 0, 0x18ULL, nullptr, OperandInfo139 }, // Inst #1001 = FABSS | |
| { 1000, 2, 1, 4, 423, 0, 1, 0, 0x18ULL, ImplicitList41, OperandInfo138 }, // Inst #1000 = FABSD_rec | |
| { 999, 2, 1, 4, 396, 0, 0, 0, 0x18ULL, nullptr, OperandInfo138 }, // Inst #999 = FABSD | |
| { 998, 0, 0, 4, 486, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #998 = EnforceIEIO | |
| { 997, 2, 1, 4, 392, 0, 1, 0, 0x108ULL, ImplicitList1, OperandInfo80 }, // Inst #997 = EXTSW_rec | |
| { 996, 2, 1, 4, 392, 0, 1, 0, 0x108ULL, ImplicitList1, OperandInfo136 }, // Inst #996 = EXTSW_32_64_rec | |
| { 995, 2, 1, 4, 392, 0, 0, 0, 0x108ULL, nullptr, OperandInfo136 }, // Inst #995 = EXTSW_32_64 | |
| { 994, 2, 1, 4, 392, 0, 0, 0, 0x8ULL, nullptr, OperandInfo79 }, // Inst #994 = EXTSW_32 | |
| { 993, 3, 1, 4, 373, 0, 2, 0, 0x8ULL, ImplicitList8, OperandInfo52 }, // Inst #993 = EXTSWSLI_rec | |
| { 992, 3, 1, 4, 373, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo137 }, // Inst #992 = EXTSWSLI_32_64_rec | |
| { 991, 3, 1, 4, 408, 0, 0, 0, 0x8ULL, nullptr, OperandInfo137 }, // Inst #991 = EXTSWSLI_32_64 | |
| { 990, 3, 1, 4, 408, 0, 1, 0, 0x8ULL, ImplicitList5, OperandInfo52 }, // Inst #990 = EXTSWSLI | |
| { 989, 2, 1, 4, 392, 0, 0, 0, 0x108ULL, nullptr, OperandInfo80 }, // Inst #989 = EXTSW | |
| { 988, 2, 1, 4, 392, 0, 1, 0, 0x108ULL, ImplicitList1, OperandInfo79 }, // Inst #988 = EXTSH_rec | |
| { 987, 2, 1, 4, 392, 0, 1, 0, 0x108ULL, ImplicitList1, OperandInfo80 }, // Inst #987 = EXTSH8_rec | |
| { 986, 2, 1, 4, 392, 0, 0, 0, 0x108ULL, nullptr, OperandInfo136 }, // Inst #986 = EXTSH8_32_64 | |
| { 985, 2, 1, 4, 392, 0, 0, 0, 0x108ULL, nullptr, OperandInfo80 }, // Inst #985 = EXTSH8 | |
| { 984, 2, 1, 4, 392, 0, 0, 0, 0x108ULL, nullptr, OperandInfo79 }, // Inst #984 = EXTSH | |
| { 983, 2, 1, 4, 392, 0, 1, 0, 0x108ULL, ImplicitList1, OperandInfo79 }, // Inst #983 = EXTSB_rec | |
| { 982, 2, 1, 4, 392, 0, 1, 0, 0x108ULL, ImplicitList1, OperandInfo80 }, // Inst #982 = EXTSB8_rec | |
| { 981, 2, 1, 4, 392, 0, 0, 0, 0x108ULL, nullptr, OperandInfo136 }, // Inst #981 = EXTSB8_32_64 | |
| { 980, 2, 1, 4, 392, 0, 0, 0, 0x108ULL, nullptr, OperandInfo80 }, // Inst #980 = EXTSB8 | |
| { 979, 2, 1, 4, 392, 0, 0, 0, 0x108ULL, nullptr, OperandInfo79 }, // Inst #979 = EXTSB | |
| { 978, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #978 = EVXOR | |
| { 977, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo135 }, // Inst #977 = EVSUBIFW | |
| { 976, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #976 = EVSUBFW | |
| { 975, 2, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #975 = EVSUBFUSIAAW | |
| { 974, 2, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #974 = EVSUBFUMIAAW | |
| { 973, 2, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #973 = EVSUBFSSIAAW | |
| { 972, 2, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #972 = EVSUBFSMIAAW | |
| { 971, 3, 0, 4, 297, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo131 }, // Inst #971 = EVSTWWOX | |
| { 970, 3, 0, 4, 297, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo130 }, // Inst #970 = EVSTWWO | |
| { 969, 3, 0, 4, 297, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo131 }, // Inst #969 = EVSTWWEX | |
| { 968, 3, 0, 4, 297, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo130 }, // Inst #968 = EVSTWWE | |
| { 967, 3, 0, 4, 297, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo131 }, // Inst #967 = EVSTWHOX | |
| { 966, 3, 0, 4, 297, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo130 }, // Inst #966 = EVSTWHO | |
| { 965, 3, 0, 4, 297, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo131 }, // Inst #965 = EVSTWHEX | |
| { 964, 3, 0, 4, 297, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo130 }, // Inst #964 = EVSTWHE | |
| { 963, 3, 0, 4, 297, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo131 }, // Inst #963 = EVSTDWX | |
| { 962, 3, 0, 4, 297, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo130 }, // Inst #962 = EVSTDW | |
| { 961, 3, 0, 4, 297, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo131 }, // Inst #961 = EVSTDHX | |
| { 960, 3, 0, 4, 297, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo130 }, // Inst #960 = EVSTDH | |
| { 959, 3, 0, 4, 297, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo131 }, // Inst #959 = EVSTDDX | |
| { 958, 3, 0, 4, 297, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo130 }, // Inst #958 = EVSTDD | |
| { 957, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #957 = EVSRWU | |
| { 956, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #956 = EVSRWS | |
| { 955, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo129 }, // Inst #955 = EVSRWIU | |
| { 954, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo129 }, // Inst #954 = EVSRWIS | |
| { 953, 2, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo134 }, // Inst #953 = EVSPLATI | |
| { 952, 2, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo134 }, // Inst #952 = EVSPLATFI | |
| { 951, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo129 }, // Inst #951 = EVSLWI | |
| { 950, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #950 = EVSLW | |
| { 949, 4, 1, 4, 23, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo133 }, // Inst #949 = EVSEL | |
| { 948, 2, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #948 = EVRNDW | |
| { 947, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo129 }, // Inst #947 = EVRLWI | |
| { 946, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #946 = EVRLW | |
| { 945, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #945 = EVORC | |
| { 944, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #944 = EVOR | |
| { 943, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #943 = EVNOR | |
| { 942, 2, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #942 = EVNEG | |
| { 941, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #941 = EVNAND | |
| { 940, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #940 = EVMWUMIAN | |
| { 939, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #939 = EVMWUMIAA | |
| { 938, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #938 = EVMWUMIA | |
| { 937, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #937 = EVMWUMI | |
| { 936, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #936 = EVMWSSFAN | |
| { 935, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #935 = EVMWSSFAA | |
| { 934, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #934 = EVMWSSFA | |
| { 933, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #933 = EVMWSSF | |
| { 932, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #932 = EVMWSMIAN | |
| { 931, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #931 = EVMWSMIAA | |
| { 930, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #930 = EVMWSMIA | |
| { 929, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #929 = EVMWSMI | |
| { 928, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #928 = EVMWSMFAN | |
| { 927, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #927 = EVMWSMFAA | |
| { 926, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #926 = EVMWSMFA | |
| { 925, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #925 = EVMWSMF | |
| { 924, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #924 = EVMWLUSIANW | |
| { 923, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #923 = EVMWLUSIAAW | |
| { 922, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #922 = EVMWLUMIANW | |
| { 921, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #921 = EVMWLUMIAAW | |
| { 920, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #920 = EVMWLUMIA | |
| { 919, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #919 = EVMWLUMI | |
| { 918, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #918 = EVMWLSSIANW | |
| { 917, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #917 = EVMWLSSIAAW | |
| { 916, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #916 = EVMWLSMIANW | |
| { 915, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #915 = EVMWLSMIAAW | |
| { 914, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #914 = EVMWHUMIA | |
| { 913, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #913 = EVMWHUMI | |
| { 912, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #912 = EVMWHSSFA | |
| { 911, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #911 = EVMWHSSF | |
| { 910, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #910 = EVMWHSMIA | |
| { 909, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #909 = EVMWHSMI | |
| { 908, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #908 = EVMWHSMFA | |
| { 907, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #907 = EVMWHSMF | |
| { 906, 2, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #906 = EVMRA | |
| { 905, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #905 = EVMHOUSIANW | |
| { 904, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #904 = EVMHOUSIAAW | |
| { 903, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #903 = EVMHOUMIANW | |
| { 902, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #902 = EVMHOUMIAAW | |
| { 901, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #901 = EVMHOUMIA | |
| { 900, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #900 = EVMHOUMI | |
| { 899, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #899 = EVMHOSSIANW | |
| { 898, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #898 = EVMHOSSIAAW | |
| { 897, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #897 = EVMHOSSFANW | |
| { 896, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #896 = EVMHOSSFAAW | |
| { 895, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #895 = EVMHOSSFA | |
| { 894, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #894 = EVMHOSSF | |
| { 893, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #893 = EVMHOSMIANW | |
| { 892, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #892 = EVMHOSMIAAW | |
| { 891, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #891 = EVMHOSMIA | |
| { 890, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #890 = EVMHOSMI | |
| { 889, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #889 = EVMHOSMFANW | |
| { 888, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #888 = EVMHOSMFAAW | |
| { 887, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #887 = EVMHOSMFA | |
| { 886, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #886 = EVMHOSMF | |
| { 885, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #885 = EVMHOGUMIAN | |
| { 884, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #884 = EVMHOGUMIAA | |
| { 883, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #883 = EVMHOGSMIAN | |
| { 882, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #882 = EVMHOGSMIAA | |
| { 881, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #881 = EVMHOGSMFAN | |
| { 880, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #880 = EVMHOGSMFAA | |
| { 879, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #879 = EVMHEUSIANW | |
| { 878, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #878 = EVMHEUSIAAW | |
| { 877, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #877 = EVMHEUMIANW | |
| { 876, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #876 = EVMHEUMIAAW | |
| { 875, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #875 = EVMHEUMIA | |
| { 874, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #874 = EVMHEUMI | |
| { 873, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #873 = EVMHESSIANW | |
| { 872, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #872 = EVMHESSIAAW | |
| { 871, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #871 = EVMHESSFANW | |
| { 870, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #870 = EVMHESSFAAW | |
| { 869, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #869 = EVMHESSFA | |
| { 868, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #868 = EVMHESSF | |
| { 867, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #867 = EVMHESMIANW | |
| { 866, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #866 = EVMHESMIAAW | |
| { 865, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #865 = EVMHESMIA | |
| { 864, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #864 = EVMHESMI | |
| { 863, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #863 = EVMHESMFANW | |
| { 862, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #862 = EVMHESMFAAW | |
| { 861, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #861 = EVMHESMFA | |
| { 860, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #860 = EVMHESMF | |
| { 859, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #859 = EVMHEGUMIAN | |
| { 858, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #858 = EVMHEGUMIAA | |
| { 857, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #857 = EVMHEGSMIAN | |
| { 856, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #856 = EVMHEGSMIAA | |
| { 855, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #855 = EVMHEGSMFAN | |
| { 854, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #854 = EVMHEGSMFAA | |
| { 853, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #853 = EVMERGELOHI | |
| { 852, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo132 }, // Inst #852 = EVMERGELO | |
| { 851, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #851 = EVMERGEHILO | |
| { 850, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #850 = EVMERGEHI | |
| { 849, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo131 }, // Inst #849 = EVLWWSPLATX | |
| { 848, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo130 }, // Inst #848 = EVLWWSPLAT | |
| { 847, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo131 }, // Inst #847 = EVLWHSPLATX | |
| { 846, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo130 }, // Inst #846 = EVLWHSPLAT | |
| { 845, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo131 }, // Inst #845 = EVLWHOUX | |
| { 844, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo130 }, // Inst #844 = EVLWHOU | |
| { 843, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo131 }, // Inst #843 = EVLWHOSX | |
| { 842, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo130 }, // Inst #842 = EVLWHOS | |
| { 841, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo131 }, // Inst #841 = EVLWHEX | |
| { 840, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo130 }, // Inst #840 = EVLWHE | |
| { 839, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo131 }, // Inst #839 = EVLHHOUSPLATX | |
| { 838, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo130 }, // Inst #838 = EVLHHOUSPLAT | |
| { 837, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo131 }, // Inst #837 = EVLHHOSSPLATX | |
| { 836, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo130 }, // Inst #836 = EVLHHOSSPLAT | |
| { 835, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo131 }, // Inst #835 = EVLHHESPLATX | |
| { 834, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo130 }, // Inst #834 = EVLHHESPLAT | |
| { 833, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo131 }, // Inst #833 = EVLDWX | |
| { 832, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo130 }, // Inst #832 = EVLDW | |
| { 831, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo131 }, // Inst #831 = EVLDHX | |
| { 830, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo130 }, // Inst #830 = EVLDH | |
| { 829, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo131 }, // Inst #829 = EVLDDX | |
| { 828, 3, 1, 4, 296, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo130 }, // Inst #828 = EVLDD | |
| { 827, 3, 1, 4, 23, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo125 }, // Inst #827 = EVFSTSTLT | |
| { 826, 3, 1, 4, 23, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo125 }, // Inst #826 = EVFSTSTGT | |
| { 825, 3, 1, 4, 23, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo125 }, // Inst #825 = EVFSTSTEQ | |
| { 824, 3, 1, 4, 24, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #824 = EVFSSUB | |
| { 823, 2, 1, 4, 23, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #823 = EVFSNEG | |
| { 822, 2, 1, 4, 23, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #822 = EVFSNABS | |
| { 821, 3, 1, 4, 24, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #821 = EVFSMUL | |
| { 820, 3, 1, 4, 19, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #820 = EVFSDIV | |
| { 819, 2, 1, 4, 24, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #819 = EVFSCTUIZ | |
| { 818, 2, 1, 4, 24, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #818 = EVFSCTUI | |
| { 817, 2, 1, 4, 24, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #817 = EVFSCTUF | |
| { 816, 2, 1, 4, 24, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #816 = EVFSCTSIZ | |
| { 815, 2, 1, 4, 24, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #815 = EVFSCTSI | |
| { 814, 2, 1, 4, 24, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #814 = EVFSCTSF | |
| { 813, 3, 1, 4, 20, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo125 }, // Inst #813 = EVFSCMPLT | |
| { 812, 3, 1, 4, 20, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo125 }, // Inst #812 = EVFSCMPGT | |
| { 811, 3, 1, 4, 20, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo125 }, // Inst #811 = EVFSCMPEQ | |
| { 810, 2, 1, 4, 24, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #810 = EVFSCFUI | |
| { 809, 2, 1, 4, 24, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #809 = EVFSCFUF | |
| { 808, 2, 1, 4, 24, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #808 = EVFSCFSI | |
| { 807, 2, 1, 4, 24, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #807 = EVFSCFSF | |
| { 806, 3, 1, 4, 24, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #806 = EVFSADD | |
| { 805, 2, 1, 4, 23, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #805 = EVFSABS | |
| { 804, 2, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #804 = EVEXTSH | |
| { 803, 2, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #803 = EVEXTSB | |
| { 802, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #802 = EVEQV | |
| { 801, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #801 = EVDIVWU | |
| { 800, 3, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #800 = EVDIVWS | |
| { 799, 2, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #799 = EVCNTLZW | |
| { 798, 2, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #798 = EVCNTLSW | |
| { 797, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo125 }, // Inst #797 = EVCMPLTU | |
| { 796, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo125 }, // Inst #796 = EVCMPLTS | |
| { 795, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo125 }, // Inst #795 = EVCMPGTU | |
| { 794, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo125 }, // Inst #794 = EVCMPGTS | |
| { 793, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo125 }, // Inst #793 = EVCMPEQ | |
| { 792, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #792 = EVANDC | |
| { 791, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #791 = EVAND | |
| { 790, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo123 }, // Inst #790 = EVADDW | |
| { 789, 2, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #789 = EVADDUSIAAW | |
| { 788, 2, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #788 = EVADDUMIAAW | |
| { 787, 2, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #787 = EVADDSSIAAW | |
| { 786, 2, 1, 4, 295, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #786 = EVADDSMIAAW | |
| { 785, 3, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo129 }, // Inst #785 = EVADDIW | |
| { 784, 2, 1, 4, 294, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo122 }, // Inst #784 = EVABS | |
| { 783, 3, 1, 4, 404, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList1, OperandInfo65 }, // Inst #783 = EQV_rec | |
| { 782, 3, 1, 4, 404, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList1, OperandInfo67 }, // Inst #782 = EQV8_rec | |
| { 781, 3, 1, 4, 404, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo67 }, // Inst #781 = EQV8 | |
| { 780, 3, 1, 4, 404, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo65 }, // Inst #780 = EQV | |
| { 779, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo87 }, // Inst #779 = EH_SjLj_Setup | |
| { 778, 2, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList17, OperandInfo128 }, // Inst #778 = EH_SjLj_SetJmp64 | |
| { 777, 2, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList16, OperandInfo128 }, // Inst #777 = EH_SjLj_SetJmp32 | |
| { 776, 1, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo127 }, // Inst #776 = EH_SjLj_LongJmp64 | |
| { 775, 1, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo127 }, // Inst #775 = EH_SjLj_LongJmp32 | |
| { 774, 3, 1, 4, 21, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo125 }, // Inst #774 = EFSTSTLT | |
| { 773, 3, 1, 4, 21, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo125 }, // Inst #773 = EFSTSTGT | |
| { 772, 3, 1, 4, 21, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo125 }, // Inst #772 = EFSTSTEQ | |
| { 771, 3, 1, 4, 20, 0, 0, 0, 0x0ULL, nullptr, OperandInfo65 }, // Inst #771 = EFSSUB | |
| { 770, 2, 1, 4, 22, 0, 0, 0, 0x0ULL, nullptr, OperandInfo79 }, // Inst #770 = EFSNEG | |
| { 769, 2, 1, 4, 22, 0, 0, 0, 0x0ULL, nullptr, OperandInfo79 }, // Inst #769 = EFSNABS | |
| { 768, 3, 1, 4, 22, 0, 0, 0, 0x0ULL, nullptr, OperandInfo65 }, // Inst #768 = EFSMUL | |
| { 767, 3, 1, 4, 19, 0, 0, 0, 0x0ULL, nullptr, OperandInfo65 }, // Inst #767 = EFSDIV | |
| { 766, 2, 1, 4, 20, 0, 0, 0, 0x0ULL, nullptr, OperandInfo79 }, // Inst #766 = EFSCTUIZ | |
| { 765, 2, 1, 4, 20, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo79 }, // Inst #765 = EFSCTUI | |
| { 764, 2, 1, 4, 20, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo124 }, // Inst #764 = EFSCTUF | |
| { 763, 2, 1, 4, 20, 0, 0, 0, 0x0ULL, nullptr, OperandInfo79 }, // Inst #763 = EFSCTSIZ | |
| { 762, 2, 1, 4, 20, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo79 }, // Inst #762 = EFSCTSI | |
| { 761, 2, 1, 4, 20, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo79 }, // Inst #761 = EFSCTSF | |
| { 760, 3, 1, 4, 21, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo100 }, // Inst #760 = EFSCMPLT | |
| { 759, 3, 1, 4, 21, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo100 }, // Inst #759 = EFSCMPGT | |
| { 758, 3, 1, 4, 21, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo100 }, // Inst #758 = EFSCMPEQ | |
| { 757, 2, 1, 4, 20, 0, 0, 0, 0x0ULL, nullptr, OperandInfo79 }, // Inst #757 = EFSCFUI | |
| { 756, 2, 1, 4, 20, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo79 }, // Inst #756 = EFSCFUF | |
| { 755, 2, 1, 4, 20, 0, 0, 0, 0x0ULL, nullptr, OperandInfo79 }, // Inst #755 = EFSCFSI | |
| { 754, 2, 1, 4, 20, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo79 }, // Inst #754 = EFSCFSF | |
| { 753, 2, 1, 4, 20, 0, 0, 0, 0x0ULL, nullptr, OperandInfo126 }, // Inst #753 = EFSCFD | |
| { 752, 3, 1, 4, 18, 0, 0, 0, 0x0ULL, nullptr, OperandInfo65 }, // Inst #752 = EFSADD | |
| { 751, 2, 1, 4, 20, 0, 0, 0, 0x0ULL, nullptr, OperandInfo79 }, // Inst #751 = EFSABS | |
| { 750, 3, 1, 4, 17, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo125 }, // Inst #750 = EFDTSTLT | |
| { 749, 3, 1, 4, 17, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo125 }, // Inst #749 = EFDTSTGT | |
| { 748, 3, 1, 4, 17, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo125 }, // Inst #748 = EFDTSTEQ | |
| { 747, 3, 1, 4, 17, 0, 0, 0, 0x0ULL, nullptr, OperandInfo123 }, // Inst #747 = EFDSUB | |
| { 746, 2, 1, 4, 17, 0, 0, 0, 0x0ULL, nullptr, OperandInfo122 }, // Inst #746 = EFDNEG | |
| { 745, 2, 1, 4, 17, 0, 0, 0, 0x0ULL, nullptr, OperandInfo122 }, // Inst #745 = EFDNABS | |
| { 744, 3, 1, 4, 17, 0, 0, 0, 0x0ULL, nullptr, OperandInfo123 }, // Inst #744 = EFDMUL | |
| { 743, 3, 1, 4, 19, 0, 0, 0, 0x0ULL, nullptr, OperandInfo123 }, // Inst #743 = EFDDIV | |
| { 742, 2, 1, 4, 17, 0, 0, 0, 0x0ULL, nullptr, OperandInfo126 }, // Inst #742 = EFDCTUIZ | |
| { 741, 2, 1, 4, 17, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo126 }, // Inst #741 = EFDCTUIDZ | |
| { 740, 2, 1, 4, 17, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo126 }, // Inst #740 = EFDCTUI | |
| { 739, 2, 1, 4, 17, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo124 }, // Inst #739 = EFDCTUF | |
| { 738, 2, 1, 4, 17, 0, 0, 0, 0x0ULL, nullptr, OperandInfo126 }, // Inst #738 = EFDCTSIZ | |
| { 737, 2, 1, 4, 17, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo126 }, // Inst #737 = EFDCTSIDZ | |
| { 736, 2, 1, 4, 17, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo126 }, // Inst #736 = EFDCTSI | |
| { 735, 2, 1, 4, 17, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo124 }, // Inst #735 = EFDCTSF | |
| { 734, 3, 1, 4, 17, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo125 }, // Inst #734 = EFDCMPLT | |
| { 733, 3, 1, 4, 17, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo125 }, // Inst #733 = EFDCMPGT | |
| { 732, 3, 1, 4, 17, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo125 }, // Inst #732 = EFDCMPEQ | |
| { 731, 2, 1, 4, 17, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo124 }, // Inst #731 = EFDCFUID | |
| { 730, 2, 1, 4, 17, 0, 0, 0, 0x0ULL, nullptr, OperandInfo124 }, // Inst #730 = EFDCFUI | |
| { 729, 2, 1, 4, 17, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo124 }, // Inst #729 = EFDCFUF | |
| { 728, 2, 1, 4, 17, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo124 }, // Inst #728 = EFDCFSID | |
| { 727, 2, 1, 4, 17, 0, 0, 0, 0x0ULL, nullptr, OperandInfo124 }, // Inst #727 = EFDCFSI | |
| { 726, 2, 1, 4, 17, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo124 }, // Inst #726 = EFDCFSF | |
| { 725, 2, 1, 4, 17, 0, 0, 0, 0x0ULL, nullptr, OperandInfo124 }, // Inst #725 = EFDCFS | |
| { 724, 3, 1, 4, 18, 0, 0, 0, 0x0ULL, nullptr, OperandInfo123 }, // Inst #724 = EFDADD | |
| { 723, 2, 1, 4, 17, 0, 0, 0, 0x0ULL, nullptr, OperandInfo122 }, // Inst #723 = EFDABS | |
| { 722, 2, 1, 4, 0, 1, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList30, OperandInfo121 }, // Inst #722 = DecreaseCTRloop | |
| { 721, 2, 1, 4, 0, 1, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList31, OperandInfo121 }, // Inst #721 = DecreaseCTR8loop | |
| { 720, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo120 }, // Inst #720 = DYNAREAOFFSET8 | |
| { 719, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo120 }, // Inst #719 = DYNAREAOFFSET | |
| { 718, 4, 1, 4, 0, 1, 1, 0, 0x0ULL, ImplicitList40, OperandInfo119 }, // Inst #718 = DYNALLOC8 | |
| { 717, 4, 1, 4, 0, 1, 1, 0, 0x0ULL, ImplicitList15, OperandInfo118 }, // Inst #717 = DYNALLOC | |
| { 716, 3, 0, 4, 414, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo117 }, // Inst #716 = DSTT64 | |
| { 715, 3, 0, 4, 414, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo116 }, // Inst #715 = DSTT | |
| { 714, 3, 0, 4, 414, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo117 }, // Inst #714 = DSTSTT64 | |
| { 713, 3, 0, 4, 414, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo116 }, // Inst #713 = DSTSTT | |
| { 712, 3, 0, 4, 414, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo117 }, // Inst #712 = DSTST64 | |
| { 711, 3, 0, 4, 414, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo116 }, // Inst #711 = DSTST | |
| { 710, 3, 0, 4, 414, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo117 }, // Inst #710 = DST64 | |
| { 709, 3, 0, 4, 414, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo116 }, // Inst #709 = DST | |
| { 708, 0, 0, 4, 387, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #708 = DSSALL | |
| { 707, 1, 0, 4, 387, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo3 }, // Inst #707 = DSS | |
| { 706, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo115 }, // Inst #706 = DMXXINSTFDMR512_HI | |
| { 705, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo114 }, // Inst #705 = DMXXINSTFDMR512 | |
| { 704, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo113 }, // Inst #704 = DMXXINSTFDMR256 | |
| { 703, 3, 2, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo112 }, // Inst #703 = DMXXEXTFDMR512_HI | |
| { 702, 3, 2, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo111 }, // Inst #702 = DMXXEXTFDMR512 | |
| { 701, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo110 }, // Inst #701 = DMXXEXTFDMR256 | |
| { 700, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo109 }, // Inst #700 = DMXOR | |
| { 699, 1, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo108 }, // Inst #699 = DMSETDMRZ | |
| { 698, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo107 }, // Inst #698 = DMMR | |
| { 697, 3, 1, 4, 242, 0, 1, 0, 0xdULL, ImplicitList1, OperandInfo65 }, // Inst #697 = DIVW_rec | |
| { 696, 3, 1, 4, 242, 0, 1, 0, 0xdULL, ImplicitList1, OperandInfo65 }, // Inst #696 = DIVWU_rec | |
| { 695, 3, 1, 4, 242, 0, 2, 0, 0x8ULL, ImplicitList4, OperandInfo65 }, // Inst #695 = DIVWUO_rec | |
| { 694, 3, 1, 4, 238, 0, 1, 0, 0x8ULL, ImplicitList3, OperandInfo65 }, // Inst #694 = DIVWUO | |
| { 693, 3, 1, 4, 238, 0, 0, 0, 0x8ULL, nullptr, OperandInfo65 }, // Inst #693 = DIVWU | |
| { 692, 3, 1, 4, 242, 0, 2, 0, 0x8ULL, ImplicitList4, OperandInfo65 }, // Inst #692 = DIVWO_rec | |
| { 691, 3, 1, 4, 238, 0, 1, 0, 0x8ULL, ImplicitList3, OperandInfo65 }, // Inst #691 = DIVWO | |
| { 690, 3, 1, 4, 244, 0, 1, 0, 0xdULL, ImplicitList1, OperandInfo65 }, // Inst #690 = DIVWE_rec | |
| { 689, 3, 1, 4, 244, 0, 1, 0, 0xdULL, ImplicitList1, OperandInfo65 }, // Inst #689 = DIVWEU_rec | |
| { 688, 3, 1, 4, 244, 0, 2, 0, 0x8ULL, ImplicitList4, OperandInfo65 }, // Inst #688 = DIVWEUO_rec | |
| { 687, 3, 1, 4, 347, 0, 1, 0, 0x8ULL, ImplicitList3, OperandInfo65 }, // Inst #687 = DIVWEUO | |
| { 686, 3, 1, 4, 347, 0, 0, 0, 0x8ULL, nullptr, OperandInfo65 }, // Inst #686 = DIVWEU | |
| { 685, 3, 1, 4, 244, 0, 2, 0, 0x8ULL, ImplicitList4, OperandInfo65 }, // Inst #685 = DIVWEO_rec | |
| { 684, 3, 1, 4, 347, 0, 1, 0, 0x8ULL, ImplicitList3, OperandInfo65 }, // Inst #684 = DIVWEO | |
| { 683, 3, 1, 4, 347, 0, 0, 0, 0x8ULL, nullptr, OperandInfo65 }, // Inst #683 = DIVWE | |
| { 682, 3, 1, 4, 238, 0, 0, 0, 0x8ULL, nullptr, OperandInfo65 }, // Inst #682 = DIVW | |
| { 681, 3, 1, 4, 243, 0, 1, 0, 0xdULL, ImplicitList1, OperandInfo67 }, // Inst #681 = DIVD_rec | |
| { 680, 3, 1, 4, 243, 0, 1, 0, 0xdULL, ImplicitList1, OperandInfo67 }, // Inst #680 = DIVDU_rec | |
| { 679, 3, 1, 4, 243, 0, 2, 0, 0x8ULL, ImplicitList4, OperandInfo67 }, // Inst #679 = DIVDUO_rec | |
| { 678, 3, 1, 4, 240, 0, 1, 0, 0x8ULL, ImplicitList3, OperandInfo67 }, // Inst #678 = DIVDUO | |
| { 677, 3, 1, 4, 240, 0, 0, 0, 0x8ULL, nullptr, OperandInfo67 }, // Inst #677 = DIVDU | |
| { 676, 3, 1, 4, 243, 0, 2, 0, 0x8ULL, ImplicitList4, OperandInfo67 }, // Inst #676 = DIVDO_rec | |
| { 675, 3, 1, 4, 240, 0, 1, 0, 0x8ULL, ImplicitList3, OperandInfo67 }, // Inst #675 = DIVDO | |
| { 674, 3, 1, 4, 245, 0, 1, 0, 0xdULL, ImplicitList1, OperandInfo67 }, // Inst #674 = DIVDE_rec | |
| { 673, 3, 1, 4, 245, 0, 1, 0, 0xdULL, ImplicitList1, OperandInfo67 }, // Inst #673 = DIVDEU_rec | |
| { 672, 3, 1, 4, 245, 0, 2, 0, 0x8ULL, ImplicitList4, OperandInfo67 }, // Inst #672 = DIVDEUO_rec | |
| { 671, 3, 1, 4, 241, 0, 1, 0, 0x8ULL, ImplicitList3, OperandInfo67 }, // Inst #671 = DIVDEUO | |
| { 670, 3, 1, 4, 241, 0, 0, 0, 0x8ULL, nullptr, OperandInfo67 }, // Inst #670 = DIVDEU | |
| { 669, 3, 1, 4, 245, 0, 2, 0, 0x8ULL, ImplicitList4, OperandInfo67 }, // Inst #669 = DIVDEO_rec | |
| { 668, 3, 1, 4, 241, 0, 1, 0, 0x8ULL, ImplicitList3, OperandInfo67 }, // Inst #668 = DIVDEO | |
| { 667, 3, 1, 4, 241, 0, 0, 0, 0x8ULL, nullptr, OperandInfo67 }, // Inst #667 = DIVDE | |
| { 666, 3, 1, 4, 240, 0, 0, 0, 0x8ULL, nullptr, OperandInfo67 }, // Inst #666 = DIVD | |
| { 665, 2, 0, 4, 492, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo79 }, // Inst #665 = DCCCI | |
| { 664, 2, 0, 4, 179, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #664 = DCBZLEP | |
| { 663, 2, 0, 4, 491, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo54 }, // Inst #663 = DCBZL | |
| { 662, 2, 0, 4, 179, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #662 = DCBZEP | |
| { 661, 2, 0, 4, 476, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo54 }, // Inst #661 = DCBZ | |
| { 660, 3, 0, 4, 179, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo55 }, // Inst #660 = DCBTSTEP | |
| { 659, 3, 0, 4, 434, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo106 }, // Inst #659 = DCBTST | |
| { 658, 3, 0, 4, 179, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo55 }, // Inst #658 = DCBTEP | |
| { 657, 3, 0, 4, 434, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo106 }, // Inst #657 = DCBT | |
| { 656, 2, 0, 4, 179, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #656 = DCBSTEP | |
| { 655, 2, 0, 4, 476, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo54 }, // Inst #655 = DCBST | |
| { 654, 2, 0, 4, 317, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo54 }, // Inst #654 = DCBI | |
| { 653, 2, 0, 4, 179, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #653 = DCBFEP | |
| { 652, 3, 0, 4, 478, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo106 }, // Inst #652 = DCBF | |
| { 651, 2, 0, 4, 317, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo54 }, // Inst #651 = DCBA | |
| { 650, 2, 1, 4, 184, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL, nullptr, OperandInfo63 }, // Inst #650 = DARN | |
| { 649, 3, 0, 4, 335, 0, 0, 0|(1ULL<<MCID::Branch), 0x38ULL, nullptr, OperandInfo89 }, // Inst #649 = CTRL_DEP | |
| { 648, 3, 1, 4, 407, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo104 }, // Inst #648 = CRXOR | |
| { 647, 1, 1, 4, 407, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo92 }, // Inst #647 = CRUNSET | |
| { 646, 1, 1, 4, 386, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo92 }, // Inst #646 = CRSET | |
| { 645, 3, 1, 4, 407, 0, 0, 0, 0x0ULL, nullptr, OperandInfo104 }, // Inst #645 = CRORC | |
| { 644, 3, 1, 4, 407, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo104 }, // Inst #644 = CROR | |
| { 643, 2, 1, 4, 133, 0, 0, 0, 0x0ULL, nullptr, OperandInfo105 }, // Inst #643 = CRNOT | |
| { 642, 3, 1, 4, 407, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo104 }, // Inst #642 = CRNOR | |
| { 641, 3, 1, 4, 407, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo104 }, // Inst #641 = CRNAND | |
| { 640, 3, 1, 4, 386, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo104 }, // Inst #640 = CREQV | |
| { 639, 3, 1, 4, 407, 0, 0, 0, 0x0ULL, nullptr, OperandInfo104 }, // Inst #639 = CRANDC | |
| { 638, 3, 1, 4, 407, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo104 }, // Inst #638 = CRAND | |
| { 637, 0, 0, 4, 407, 0, 1, 0, 0x0ULL, ImplicitList39, nullptr }, // Inst #637 = CR6UNSET | |
| { 636, 0, 0, 4, 386, 0, 1, 0, 0x0ULL, ImplicitList39, nullptr }, // Inst #636 = CR6SET | |
| { 635, 3, 0, 4, 205, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo53 }, // Inst #635 = CP_PASTE_rec | |
| { 634, 3, 0, 4, 205, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #634 = CP_PASTE8_rec | |
| { 633, 3, 0, 4, 180, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #633 = CP_COPY8 | |
| { 632, 3, 0, 4, 180, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #632 = CP_COPY | |
| { 631, 0, 0, 4, 186, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #631 = CP_ABORT | |
| { 630, 2, 1, 4, 362, 0, 1, 0, 0x208ULL, ImplicitList1, OperandInfo79 }, // Inst #630 = CNTTZW_rec | |
| { 629, 2, 1, 4, 362, 0, 1, 0, 0x308ULL, ImplicitList1, OperandInfo80 }, // Inst #629 = CNTTZW8_rec | |
| { 628, 2, 1, 4, 362, 0, 0, 0, 0x308ULL, nullptr, OperandInfo80 }, // Inst #628 = CNTTZW8 | |
| { 627, 2, 1, 4, 362, 0, 0, 0, 0x208ULL, nullptr, OperandInfo79 }, // Inst #627 = CNTTZW | |
| { 626, 2, 1, 4, 362, 0, 1, 0, 0x308ULL, ImplicitList1, OperandInfo80 }, // Inst #626 = CNTTZD_rec | |
| { 625, 3, 1, 4, 338, 0, 0, 0, 0x0ULL, nullptr, OperandInfo67 }, // Inst #625 = CNTTZDM | |
| { 624, 2, 1, 4, 362, 0, 0, 0, 0x308ULL, nullptr, OperandInfo80 }, // Inst #624 = CNTTZD | |
| { 623, 2, 1, 4, 362, 0, 1, 0, 0x208ULL, ImplicitList1, OperandInfo79 }, // Inst #623 = CNTLZW_rec | |
| { 622, 2, 1, 4, 362, 0, 1, 0, 0x308ULL, ImplicitList1, OperandInfo80 }, // Inst #622 = CNTLZW8_rec | |
| { 621, 2, 1, 4, 362, 0, 0, 0, 0x308ULL, nullptr, OperandInfo80 }, // Inst #621 = CNTLZW8 | |
| { 620, 2, 1, 4, 362, 0, 0, 0, 0x208ULL, nullptr, OperandInfo79 }, // Inst #620 = CNTLZW | |
| { 619, 2, 1, 4, 362, 0, 1, 0, 0x308ULL, ImplicitList1, OperandInfo80 }, // Inst #619 = CNTLZD_rec | |
| { 618, 3, 1, 4, 338, 0, 0, 0, 0x0ULL, nullptr, OperandInfo67 }, // Inst #618 = CNTLZDM | |
| { 617, 2, 1, 4, 362, 0, 0, 0, 0x308ULL, nullptr, OperandInfo80 }, // Inst #617 = CNTLZD | |
| { 616, 3, 1, 4, 118, 0, 0, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, OperandInfo101 }, // Inst #616 = CMPWI | |
| { 615, 3, 1, 4, 118, 0, 0, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, OperandInfo100 }, // Inst #615 = CMPW | |
| { 614, 4, 1, 4, 107, 0, 0, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, OperandInfo103 }, // Inst #614 = CMPRB8 | |
| { 613, 4, 1, 4, 107, 0, 0, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, OperandInfo102 }, // Inst #613 = CMPRB | |
| { 612, 3, 1, 4, 118, 0, 0, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, OperandInfo101 }, // Inst #612 = CMPLWI | |
| { 611, 3, 1, 4, 118, 0, 0, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, OperandInfo100 }, // Inst #611 = CMPLW | |
| { 610, 3, 1, 4, 118, 0, 0, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, OperandInfo99 }, // Inst #610 = CMPLDI | |
| { 609, 3, 1, 4, 118, 0, 0, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, OperandInfo98 }, // Inst #609 = CMPLD | |
| { 608, 3, 1, 4, 372, 0, 0, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, OperandInfo98 }, // Inst #608 = CMPEQB | |
| { 607, 3, 1, 4, 118, 0, 0, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, OperandInfo99 }, // Inst #607 = CMPDI | |
| { 606, 3, 1, 4, 118, 0, 0, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, OperandInfo98 }, // Inst #606 = CMPD | |
| { 605, 3, 1, 4, 406, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo67 }, // Inst #605 = CMPB8 | |
| { 604, 3, 1, 4, 406, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo65 }, // Inst #604 = CMPB | |
| { 603, 0, 0, 4, 494, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr }, // Inst #603 = CLRBHRB | |
| { 602, 3, 1, 4, 338, 0, 0, 0, 0x0ULL, nullptr, OperandInfo67 }, // Inst #602 = CFUGED | |
| { 601, 2, 1, 4, 460, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo80 }, // Inst #601 = BRW8 | |
| { 600, 2, 1, 4, 460, 0, 0, 0, 0x0ULL, nullptr, OperandInfo79 }, // Inst #600 = BRW | |
| { 599, 3, 1, 4, 293, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo65 }, // Inst #599 = BRINC | |
| { 598, 2, 1, 4, 460, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo80 }, // Inst #598 = BRH8 | |
| { 597, 2, 1, 4, 460, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo79 }, // Inst #597 = BRH | |
| { 596, 2, 1, 4, 460, 0, 0, 0, 0x0ULL, nullptr, OperandInfo80 }, // Inst #596 = BRD | |
| { 595, 3, 1, 4, 114, 0, 0, 0, 0x8ULL, nullptr, OperandInfo67 }, // Inst #595 = BPERMD | |
| { 594, 2, 0, 4, 333, 1, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList20, OperandInfo7 }, // Inst #594 = BL_TLS | |
| { 593, 1, 0, 4, 333, 1, 2, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList37, OperandInfo87 }, // Inst #593 = BL_RM | |
| { 592, 1, 0, 8, 333, 1, 2, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList37, OperandInfo87 }, // Inst #592 = BL_NOP_RM | |
| { 591, 1, 0, 8, 333, 1, 1, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList20, OperandInfo87 }, // Inst #591 = BL_NOP | |
| { 590, 0, 0, 4, 333, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList22, nullptr }, // Inst #590 = BLRL | |
| { 589, 0, 0, 4, 333, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList38, nullptr }, // Inst #589 = BLR8 | |
| { 588, 0, 0, 4, 333, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList21, nullptr }, // Inst #588 = BLR | |
| { 587, 1, 0, 4, 335, 1, 2, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList37, OperandInfo2 }, // Inst #587 = BLA_RM | |
| { 586, 1, 0, 4, 335, 1, 2, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList36, OperandInfo2 }, // Inst #586 = BLA8_RM | |
| { 585, 1, 0, 8, 335, 1, 2, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList36, OperandInfo2 }, // Inst #585 = BLA8_NOP_RM | |
| { 584, 1, 0, 8, 335, 1, 1, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList35, OperandInfo2 }, // Inst #584 = BLA8_NOP | |
| { 583, 1, 0, 4, 335, 1, 1, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList35, OperandInfo2 }, // Inst #583 = BLA8 | |
| { 582, 1, 0, 4, 335, 1, 1, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList20, OperandInfo2 }, // Inst #582 = BLA | |
| { 581, 2, 0, 4, 333, 1, 1, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList35, OperandInfo7 }, // Inst #581 = BL8_TLS_ | |
| { 580, 2, 0, 4, 333, 1, 1, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList35, OperandInfo7 }, // Inst #580 = BL8_TLS | |
| { 579, 1, 0, 4, 333, 1, 2, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList36, OperandInfo87 }, // Inst #579 = BL8_RM | |
| { 578, 2, 0, 4, 334, 1, 1, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList35, OperandInfo7 }, // Inst #578 = BL8_NOTOC_TLS | |
| { 577, 1, 0, 4, 334, 1, 2, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList36, OperandInfo87 }, // Inst #577 = BL8_NOTOC_RM | |
| { 576, 1, 0, 4, 334, 1, 1, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList35, OperandInfo87 }, // Inst #576 = BL8_NOTOC | |
| { 575, 2, 0, 8, 333, 1, 1, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList35, OperandInfo7 }, // Inst #575 = BL8_NOP_TLS | |
| { 574, 1, 0, 8, 333, 1, 2, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList36, OperandInfo87 }, // Inst #574 = BL8_NOP_RM | |
| { 573, 1, 0, 8, 333, 1, 1, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList35, OperandInfo87 }, // Inst #573 = BL8_NOP | |
| { 572, 1, 0, 4, 333, 1, 1, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList35, OperandInfo87 }, // Inst #572 = BL8 | |
| { 571, 1, 0, 4, 333, 1, 1, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList20, OperandInfo87 }, // Inst #571 = BL | |
| { 570, 1, 0, 4, 335, 1, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList30, OperandInfo87 }, // Inst #570 = BDZp | |
| { 569, 1, 0, 4, 335, 1, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList30, OperandInfo87 }, // Inst #569 = BDZm | |
| { 568, 1, 0, 4, 335, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList32, OperandInfo87 }, // Inst #568 = BDZLp | |
| { 567, 1, 0, 4, 335, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList32, OperandInfo87 }, // Inst #567 = BDZLm | |
| { 566, 0, 0, 4, 333, 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList33, nullptr }, // Inst #566 = BDZLRp | |
| { 565, 0, 0, 4, 333, 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList33, nullptr }, // Inst #565 = BDZLRm | |
| { 564, 0, 0, 4, 333, 3, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList33, nullptr }, // Inst #564 = BDZLRLp | |
| { 563, 0, 0, 4, 333, 3, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList33, nullptr }, // Inst #563 = BDZLRLm | |
| { 562, 0, 0, 4, 333, 3, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList33, nullptr }, // Inst #562 = BDZLRL | |
| { 561, 0, 0, 4, 333, 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList34, nullptr }, // Inst #561 = BDZLR8 | |
| { 560, 0, 0, 4, 333, 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList33, nullptr }, // Inst #560 = BDZLR | |
| { 559, 1, 0, 4, 289, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList32, OperandInfo2 }, // Inst #559 = BDZLAp | |
| { 558, 1, 0, 4, 289, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList32, OperandInfo2 }, // Inst #558 = BDZLAm | |
| { 557, 1, 0, 4, 289, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList32, OperandInfo2 }, // Inst #557 = BDZLA | |
| { 556, 1, 0, 4, 335, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList32, OperandInfo87 }, // Inst #556 = BDZL | |
| { 555, 1, 0, 4, 289, 1, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList30, OperandInfo2 }, // Inst #555 = BDZAp | |
| { 554, 1, 0, 4, 289, 1, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList30, OperandInfo2 }, // Inst #554 = BDZAm | |
| { 553, 1, 0, 4, 289, 1, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList30, OperandInfo2 }, // Inst #553 = BDZA | |
| { 552, 1, 0, 4, 335, 1, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList31, OperandInfo87 }, // Inst #552 = BDZ8 | |
| { 551, 1, 0, 4, 335, 1, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList30, OperandInfo87 }, // Inst #551 = BDZ | |
| { 550, 1, 0, 4, 335, 1, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList30, OperandInfo87 }, // Inst #550 = BDNZp | |
| { 549, 1, 0, 4, 335, 1, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList30, OperandInfo87 }, // Inst #549 = BDNZm | |
| { 548, 1, 0, 4, 335, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList32, OperandInfo87 }, // Inst #548 = BDNZLp | |
| { 547, 1, 0, 4, 335, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList32, OperandInfo87 }, // Inst #547 = BDNZLm | |
| { 546, 0, 0, 4, 333, 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList33, nullptr }, // Inst #546 = BDNZLRp | |
| { 545, 0, 0, 4, 333, 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList33, nullptr }, // Inst #545 = BDNZLRm | |
| { 544, 0, 0, 4, 333, 3, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList33, nullptr }, // Inst #544 = BDNZLRLp | |
| { 543, 0, 0, 4, 333, 3, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList33, nullptr }, // Inst #543 = BDNZLRLm | |
| { 542, 0, 0, 4, 333, 3, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList33, nullptr }, // Inst #542 = BDNZLRL | |
| { 541, 0, 0, 4, 333, 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList34, nullptr }, // Inst #541 = BDNZLR8 | |
| { 540, 0, 0, 4, 333, 3, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList33, nullptr }, // Inst #540 = BDNZLR | |
| { 539, 1, 0, 4, 289, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList32, OperandInfo2 }, // Inst #539 = BDNZLAp | |
| { 538, 1, 0, 4, 289, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList32, OperandInfo2 }, // Inst #538 = BDNZLAm | |
| { 537, 1, 0, 4, 289, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList32, OperandInfo2 }, // Inst #537 = BDNZLA | |
| { 536, 1, 0, 4, 335, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList32, OperandInfo87 }, // Inst #536 = BDNZL | |
| { 535, 1, 0, 4, 289, 1, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList30, OperandInfo2 }, // Inst #535 = BDNZAp | |
| { 534, 1, 0, 4, 289, 1, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList30, OperandInfo2 }, // Inst #534 = BDNZAm | |
| { 533, 1, 0, 4, 289, 1, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList30, OperandInfo2 }, // Inst #533 = BDNZA | |
| { 532, 1, 0, 4, 335, 1, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList31, OperandInfo87 }, // Inst #532 = BDNZ8 | |
| { 531, 1, 0, 4, 335, 1, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList30, OperandInfo87 }, // Inst #531 = BDNZ | |
| { 530, 2, 0, 4, 335, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, nullptr, OperandInfo88 }, // Inst #530 = BCn | |
| { 529, 0, 0, 4, 335, 2, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x38ULL, ImplicitList29, nullptr }, // Inst #529 = BCTRL_RM | |
| { 528, 2, 0, 8, 335, 2, 3, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList28, OperandInfo97 }, // Inst #528 = BCTRL_LWZinto_toc_RM | |
| { 527, 2, 0, 8, 335, 2, 2, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList27, OperandInfo97 }, // Inst #527 = BCTRL_LWZinto_toc | |
| { 526, 0, 0, 4, 335, 2, 2, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x38ULL, ImplicitList26, nullptr }, // Inst #526 = BCTRL8_RM | |
| { 525, 2, 0, 8, 335, 2, 3, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList25, OperandInfo97 }, // Inst #525 = BCTRL8_LDinto_toc_RM | |
| { 524, 2, 0, 8, 335, 2, 2, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList24, OperandInfo97 }, // Inst #524 = BCTRL8_LDinto_toc | |
| { 523, 0, 0, 4, 335, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x38ULL, ImplicitList19, nullptr }, // Inst #523 = BCTRL8 | |
| { 522, 0, 0, 4, 335, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x38ULL, ImplicitList18, nullptr }, // Inst #522 = BCTRL | |
| { 521, 0, 0, 4, 335, 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList17, nullptr }, // Inst #521 = BCTR8 | |
| { 520, 0, 0, 4, 335, 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList16, nullptr }, // Inst #520 = BCTR | |
| { 519, 2, 0, 4, 335, 1, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList20, OperandInfo88 }, // Inst #519 = BCLn | |
| { 518, 1, 0, 4, 335, 1, 1, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList20, OperandInfo87 }, // Inst #518 = BCLalways | |
| { 517, 1, 0, 4, 333, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList21, OperandInfo92 }, // Inst #517 = BCLRn | |
| { 516, 1, 0, 4, 333, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList22, OperandInfo92 }, // Inst #516 = BCLRLn | |
| { 515, 1, 0, 4, 333, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList22, OperandInfo92 }, // Inst #515 = BCLRL | |
| { 514, 1, 0, 4, 333, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList21, OperandInfo92 }, // Inst #514 = BCLR | |
| { 513, 2, 0, 4, 335, 1, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList20, OperandInfo88 }, // Inst #513 = BCL | |
| { 512, 3, 1, 4, 355, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList23, OperandInfo95 }, // Inst #512 = BCDUTRUNC_rec | |
| { 511, 3, 1, 4, 355, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList23, OperandInfo95 }, // Inst #511 = BCDUS_rec | |
| { 510, 4, 1, 4, 359, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList23, OperandInfo93 }, // Inst #510 = BCDTRUNC_rec | |
| { 509, 4, 1, 4, 359, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList23, OperandInfo93 }, // Inst #509 = BCDS_rec | |
| { 508, 4, 1, 4, 359, 0, 1, 0, 0x0ULL, ImplicitList23, OperandInfo93 }, // Inst #508 = BCDSUB_rec | |
| { 507, 4, 1, 4, 169, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList23, OperandInfo93 }, // Inst #507 = BCDSR_rec | |
| { 506, 3, 1, 4, 355, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList23, OperandInfo94 }, // Inst #506 = BCDSETSGN_rec | |
| { 505, 3, 1, 4, 355, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList23, OperandInfo94 }, // Inst #505 = BCDCTZ_rec | |
| { 504, 2, 1, 4, 170, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList23, OperandInfo96 }, // Inst #504 = BCDCTSQ_rec | |
| { 503, 2, 1, 4, 354, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList23, OperandInfo96 }, // Inst #503 = BCDCTN_rec | |
| { 502, 3, 1, 4, 355, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList23, OperandInfo95 }, // Inst #502 = BCDCPSGN_rec | |
| { 501, 3, 1, 4, 355, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList23, OperandInfo94 }, // Inst #501 = BCDCFZ_rec | |
| { 500, 3, 1, 4, 172, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList23, OperandInfo94 }, // Inst #500 = BCDCFSQ_rec | |
| { 499, 3, 1, 4, 355, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList23, OperandInfo94 }, // Inst #499 = BCDCFN_rec | |
| { 498, 4, 1, 4, 359, 0, 1, 0, 0x0ULL, ImplicitList23, OperandInfo93 }, // Inst #498 = BCDADD_rec | |
| { 497, 1, 0, 4, 336, 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList16, OperandInfo92 }, // Inst #497 = BCCTRn | |
| { 496, 1, 0, 4, 336, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, OperandInfo92 }, // Inst #496 = BCCTRLn | |
| { 495, 1, 0, 4, 336, 2, 1, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList19, OperandInfo92 }, // Inst #495 = BCCTRL8n | |
| { 494, 1, 0, 4, 336, 2, 1, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList19, OperandInfo92 }, // Inst #494 = BCCTRL8 | |
| { 493, 1, 0, 4, 336, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, OperandInfo92 }, // Inst #493 = BCCTRL | |
| { 492, 1, 0, 4, 336, 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList17, OperandInfo92 }, // Inst #492 = BCCTR8n | |
| { 491, 1, 0, 4, 336, 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList17, OperandInfo92 }, // Inst #491 = BCCTR8 | |
| { 490, 1, 0, 4, 336, 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList16, OperandInfo92 }, // Inst #490 = BCCTR | |
| { 489, 2, 0, 4, 335, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList22, OperandInfo91 }, // Inst #489 = BCCLRL | |
| { 488, 2, 0, 4, 335, 2, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList21, OperandInfo91 }, // Inst #488 = BCCLR | |
| { 487, 3, 0, 4, 335, 1, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList20, OperandInfo90 }, // Inst #487 = BCCLA | |
| { 486, 3, 0, 4, 335, 1, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList20, OperandInfo89 }, // Inst #486 = BCCL | |
| { 485, 2, 0, 4, 335, 2, 1, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList19, OperandInfo91 }, // Inst #485 = BCCCTRL8 | |
| { 484, 2, 0, 4, 335, 2, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, OperandInfo91 }, // Inst #484 = BCCCTRL | |
| { 483, 2, 0, 4, 335, 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList17, OperandInfo91 }, // Inst #483 = BCCCTR8 | |
| { 482, 2, 0, 4, 335, 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList16, OperandInfo91 }, // Inst #482 = BCCCTR | |
| { 481, 3, 0, 4, 335, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, nullptr, OperandInfo90 }, // Inst #481 = BCCA | |
| { 480, 3, 0, 4, 335, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, nullptr, OperandInfo89 }, // Inst #480 = BCC | |
| { 479, 2, 0, 4, 335, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, nullptr, OperandInfo88 }, // Inst #479 = BC | |
| { 478, 1, 0, 4, 335, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL, nullptr, OperandInfo2 }, // Inst #478 = BA | |
| { 477, 1, 0, 4, 335, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x38ULL, nullptr, OperandInfo87 }, // Inst #477 = B | |
| { 476, 0, 0, 4, 490, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #476 = ATTN | |
| { 475, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #475 = ATOMIC_SWAP_I8 | |
| { 474, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo86 }, // Inst #474 = ATOMIC_SWAP_I64 | |
| { 473, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #473 = ATOMIC_SWAP_I32 | |
| { 472, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #472 = ATOMIC_SWAP_I16 | |
| { 471, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #471 = ATOMIC_LOAD_XOR_I8 | |
| { 470, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo86 }, // Inst #470 = ATOMIC_LOAD_XOR_I64 | |
| { 469, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #469 = ATOMIC_LOAD_XOR_I32 | |
| { 468, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #468 = ATOMIC_LOAD_XOR_I16 | |
| { 467, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #467 = ATOMIC_LOAD_UMIN_I8 | |
| { 466, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo86 }, // Inst #466 = ATOMIC_LOAD_UMIN_I64 | |
| { 465, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #465 = ATOMIC_LOAD_UMIN_I32 | |
| { 464, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #464 = ATOMIC_LOAD_UMIN_I16 | |
| { 463, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #463 = ATOMIC_LOAD_UMAX_I8 | |
| { 462, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo86 }, // Inst #462 = ATOMIC_LOAD_UMAX_I64 | |
| { 461, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #461 = ATOMIC_LOAD_UMAX_I32 | |
| { 460, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #460 = ATOMIC_LOAD_UMAX_I16 | |
| { 459, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #459 = ATOMIC_LOAD_SUB_I8 | |
| { 458, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo86 }, // Inst #458 = ATOMIC_LOAD_SUB_I64 | |
| { 457, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #457 = ATOMIC_LOAD_SUB_I32 | |
| { 456, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #456 = ATOMIC_LOAD_SUB_I16 | |
| { 455, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #455 = ATOMIC_LOAD_OR_I8 | |
| { 454, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo86 }, // Inst #454 = ATOMIC_LOAD_OR_I64 | |
| { 453, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #453 = ATOMIC_LOAD_OR_I32 | |
| { 452, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #452 = ATOMIC_LOAD_OR_I16 | |
| { 451, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #451 = ATOMIC_LOAD_NAND_I8 | |
| { 450, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo86 }, // Inst #450 = ATOMIC_LOAD_NAND_I64 | |
| { 449, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #449 = ATOMIC_LOAD_NAND_I32 | |
| { 448, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #448 = ATOMIC_LOAD_NAND_I16 | |
| { 447, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #447 = ATOMIC_LOAD_MIN_I8 | |
| { 446, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo86 }, // Inst #446 = ATOMIC_LOAD_MIN_I64 | |
| { 445, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #445 = ATOMIC_LOAD_MIN_I32 | |
| { 444, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #444 = ATOMIC_LOAD_MIN_I16 | |
| { 443, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #443 = ATOMIC_LOAD_MAX_I8 | |
| { 442, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo86 }, // Inst #442 = ATOMIC_LOAD_MAX_I64 | |
| { 441, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #441 = ATOMIC_LOAD_MAX_I32 | |
| { 440, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #440 = ATOMIC_LOAD_MAX_I16 | |
| { 439, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #439 = ATOMIC_LOAD_AND_I8 | |
| { 438, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo86 }, // Inst #438 = ATOMIC_LOAD_AND_I64 | |
| { 437, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #437 = ATOMIC_LOAD_AND_I32 | |
| { 436, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #436 = ATOMIC_LOAD_AND_I16 | |
| { 435, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #435 = ATOMIC_LOAD_ADD_I8 | |
| { 434, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo86 }, // Inst #434 = ATOMIC_LOAD_ADD_I64 | |
| { 433, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #433 = ATOMIC_LOAD_ADD_I32 | |
| { 432, 4, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo85 }, // Inst #432 = ATOMIC_LOAD_ADD_I16 | |
| { 431, 5, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo83 }, // Inst #431 = ATOMIC_CMP_SWAP_I8 | |
| { 430, 5, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo84 }, // Inst #430 = ATOMIC_CMP_SWAP_I64 | |
| { 429, 5, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo83 }, // Inst #429 = ATOMIC_CMP_SWAP_I32 | |
| { 428, 5, 1, 4, 0, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, OperandInfo83 }, // Inst #428 = ATOMIC_CMP_SWAP_I16 | |
| { 427, 3, 1, 4, 404, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList1, OperandInfo65 }, // Inst #427 = AND_rec | |
| { 426, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo82 }, // Inst #426 = ANDI_rec_1_GT_BIT8 | |
| { 425, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo81 }, // Inst #425 = ANDI_rec_1_GT_BIT | |
| { 424, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo82 }, // Inst #424 = ANDI_rec_1_EQ_BIT8 | |
| { 423, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo81 }, // Inst #423 = ANDI_rec_1_EQ_BIT | |
| { 422, 3, 1, 4, 405, 0, 1, 0, 0x308ULL, ImplicitList1, OperandInfo53 }, // Inst #422 = ANDI_rec | |
| { 421, 3, 1, 4, 405, 0, 1, 0, 0x208ULL, ImplicitList1, OperandInfo53 }, // Inst #421 = ANDIS_rec | |
| { 420, 3, 1, 4, 405, 0, 1, 0, 0x208ULL, ImplicitList1, OperandInfo52 }, // Inst #420 = ANDIS8_rec | |
| { 419, 3, 1, 4, 405, 0, 1, 0, 0x308ULL, ImplicitList1, OperandInfo52 }, // Inst #419 = ANDI8_rec | |
| { 418, 3, 1, 4, 404, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo65 }, // Inst #418 = ANDC_rec | |
| { 417, 3, 1, 4, 404, 0, 1, 0, 0x8ULL, ImplicitList1, OperandInfo67 }, // Inst #417 = ANDC8_rec | |
| { 416, 3, 1, 4, 404, 0, 0, 0, 0x8ULL, nullptr, OperandInfo67 }, // Inst #416 = ANDC8 | |
| { 415, 3, 1, 4, 404, 0, 0, 0, 0x8ULL, nullptr, OperandInfo65 }, // Inst #415 = ANDC | |
| { 414, 3, 1, 4, 404, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList1, OperandInfo67 }, // Inst #414 = AND8_rec | |
| { 413, 3, 1, 4, 404, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo67 }, // Inst #413 = AND8 | |
| { 412, 3, 1, 4, 404, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo65 }, // Inst #412 = AND | |
| { 411, 2, 0, 4, 0, 1, 1, 0, 0x0ULL, ImplicitList15, OperandInfo10 }, // Inst #411 = ADJCALLSTACKUP | |
| { 410, 2, 0, 4, 0, 1, 1, 0, 0x0ULL, ImplicitList15, OperandInfo10 }, // Inst #410 = ADJCALLSTACKDOWN | |
| { 409, 2, 1, 4, 418, 1, 2, 0, 0x8ULL, ImplicitList12, OperandInfo79 }, // Inst #409 = ADDZE_rec | |
| { 408, 2, 1, 4, 418, 1, 3, 0, 0x8ULL, ImplicitList11, OperandInfo79 }, // Inst #408 = ADDZEO_rec | |
| { 407, 2, 1, 4, 395, 1, 2, 0, 0x8ULL, ImplicitList10, OperandInfo79 }, // Inst #407 = ADDZEO | |
| { 406, 2, 1, 4, 418, 1, 2, 0, 0x8ULL, ImplicitList12, OperandInfo80 }, // Inst #406 = ADDZE8_rec | |
| { 405, 2, 1, 4, 418, 1, 3, 0, 0x8ULL, ImplicitList11, OperandInfo80 }, // Inst #405 = ADDZE8O_rec | |
| { 404, 2, 1, 4, 395, 1, 2, 0, 0x8ULL, ImplicitList10, OperandInfo80 }, // Inst #404 = ADDZE8O | |
| { 403, 2, 1, 4, 395, 1, 1, 0, 0x8ULL, ImplicitList9, OperandInfo80 }, // Inst #403 = ADDZE8 | |
| { 402, 2, 1, 4, 395, 1, 1, 0, 0x8ULL, ImplicitList9, OperandInfo79 }, // Inst #402 = ADDZE | |
| { 401, 2, 1, 4, 290, 0, 0, 0, 0x8ULL, nullptr, OperandInfo63 }, // Inst #401 = ADDPCIS | |
| { 400, 2, 1, 4, 418, 1, 2, 0, 0x8ULL, ImplicitList12, OperandInfo79 }, // Inst #400 = ADDME_rec | |
| { 399, 2, 1, 4, 418, 1, 3, 0, 0x8ULL, ImplicitList11, OperandInfo79 }, // Inst #399 = ADDMEO_rec | |
| { 398, 2, 1, 4, 395, 1, 2, 0, 0x8ULL, ImplicitList10, OperandInfo79 }, // Inst #398 = ADDMEO | |
| { 397, 2, 1, 4, 418, 1, 2, 0, 0x8ULL, ImplicitList12, OperandInfo80 }, // Inst #397 = ADDME8_rec | |
| { 396, 2, 1, 4, 418, 1, 3, 0, 0x8ULL, ImplicitList11, OperandInfo80 }, // Inst #396 = ADDME8O_rec | |
| { 395, 2, 1, 4, 395, 1, 2, 0, 0x8ULL, ImplicitList10, OperandInfo80 }, // Inst #395 = ADDME8O | |
| { 394, 2, 1, 4, 395, 1, 1, 0, 0x8ULL, ImplicitList9, OperandInfo80 }, // Inst #394 = ADDME8 | |
| { 393, 2, 1, 4, 395, 1, 1, 0, 0x8ULL, ImplicitList9, OperandInfo79 }, // Inst #393 = ADDME | |
| { 392, 3, 1, 4, 394, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo68 }, // Inst #392 = ADDItocL | |
| { 391, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo78 }, // Inst #391 = ADDItoc8 | |
| { 390, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo77 }, // Inst #390 = ADDItoc | |
| { 389, 4, 1, 4, 393, 0, 18, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList14, OperandInfo76 }, // Inst #389 = ADDItlsldLADDR32 | |
| { 388, 4, 1, 4, 0, 0, 18, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList13, OperandInfo75 }, // Inst #388 = ADDItlsldLADDR | |
| { 387, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #387 = ADDItlsldL32 | |
| { 386, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo73 }, // Inst #386 = ADDItlsldL | |
| { 385, 4, 1, 4, 0, 0, 18, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList14, OperandInfo76 }, // Inst #385 = ADDItlsgdLADDR32 | |
| { 384, 4, 1, 4, 0, 0, 18, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList13, OperandInfo75 }, // Inst #384 = ADDItlsgdLADDR | |
| { 383, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #383 = ADDItlsgdL32 | |
| { 382, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo73 }, // Inst #382 = ADDItlsgdL | |
| { 381, 3, 1, 4, 393, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #381 = ADDIdtprelL32 | |
| { 380, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo73 }, // Inst #380 = ADDIdtprelL | |
| { 379, 3, 1, 4, 394, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo68 }, // Inst #379 = ADDIStocHA8 | |
| { 378, 3, 1, 4, 394, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo74 }, // Inst #378 = ADDIStocHA | |
| { 377, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo73 }, // Inst #377 = ADDIStlsldHA | |
| { 376, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo73 }, // Inst #376 = ADDIStlsgdHA | |
| { 375, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo73 }, // Inst #375 = ADDISgotTprelHA | |
| { 374, 3, 1, 4, 393, 0, 0, 0, 0x0ULL, nullptr, OperandInfo72 }, // Inst #374 = ADDISdtprelHA32 | |
| { 373, 3, 1, 4, 0, 0, 0, 0, 0x0ULL, nullptr, OperandInfo73 }, // Inst #373 = ADDISdtprelHA | |
| { 372, 3, 1, 4, 392, 0, 0, 0, 0x8ULL, nullptr, OperandInfo73 }, // Inst #372 = ADDIS8 | |
| { 371, 3, 1, 4, 392, 0, 0, 0, 0x8ULL, nullptr, OperandInfo72 }, // Inst #371 = ADDIS | |
| { 370, 3, 1, 4, 421, 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL, ImplicitList8, OperandInfo53 }, // Inst #370 = ADDIC_rec | |
| { 369, 3, 1, 4, 405, 0, 1, 0, 0x8ULL, ImplicitList5, OperandInfo52 }, // Inst #369 = ADDIC8 | |
| { 368, 3, 1, 4, 405, 0, 1, 0, 0xcULL, ImplicitList5, OperandInfo53 }, // Inst #368 = ADDIC | |
| { 367, 3, 1, 4, 392, 0, 0, 0, 0x8ULL, nullptr, OperandInfo73 }, // Inst #367 = ADDI8 | |
| { 366, 3, 1, 4, 392, 0, 0, 0, 0x8ULL, nullptr, OperandInfo72 }, // Inst #366 = ADDI | |
| { 365, 3, 1, 4, 421, 1, 2, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList12, OperandInfo65 }, // Inst #365 = ADDE_rec | |
| { 364, 4, 1, 4, 413, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo71 }, // Inst #364 = ADDEX8 | |
| { 363, 4, 1, 4, 413, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #363 = ADDEX | |
| { 362, 3, 1, 4, 421, 1, 3, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList11, OperandInfo65 }, // Inst #362 = ADDEO_rec | |
| { 361, 3, 1, 4, 405, 1, 2, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList10, OperandInfo65 }, // Inst #361 = ADDEO | |
| { 360, 3, 1, 4, 421, 1, 2, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList12, OperandInfo67 }, // Inst #360 = ADDE8_rec | |
| { 359, 3, 1, 4, 421, 1, 3, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList11, OperandInfo67 }, // Inst #359 = ADDE8O_rec | |
| { 358, 3, 1, 4, 405, 1, 2, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList10, OperandInfo67 }, // Inst #358 = ADDE8O | |
| { 357, 3, 1, 4, 405, 1, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList9, OperandInfo67 }, // Inst #357 = ADDE8 | |
| { 356, 3, 1, 4, 405, 1, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList9, OperandInfo65 }, // Inst #356 = ADDE | |
| { 355, 3, 1, 4, 426, 0, 2, 0|(1ULL<<MCID::Commutable), 0xcULL, ImplicitList8, OperandInfo65 }, // Inst #355 = ADDC_rec | |
| { 354, 3, 1, 4, 247, 0, 3, 0|(1ULL<<MCID::Commutable), 0xcULL, ImplicitList7, OperandInfo65 }, // Inst #354 = ADDCO_rec | |
| { 353, 3, 1, 4, 425, 0, 2, 0|(1ULL<<MCID::Commutable), 0xcULL, ImplicitList6, OperandInfo65 }, // Inst #353 = ADDCO | |
| { 352, 3, 1, 4, 426, 0, 2, 0|(1ULL<<MCID::Commutable), 0xcULL, ImplicitList8, OperandInfo67 }, // Inst #352 = ADDC8_rec | |
| { 351, 3, 1, 4, 247, 0, 3, 0|(1ULL<<MCID::Commutable), 0xcULL, ImplicitList7, OperandInfo67 }, // Inst #351 = ADDC8O_rec | |
| { 350, 3, 1, 4, 425, 0, 2, 0|(1ULL<<MCID::Commutable), 0xcULL, ImplicitList6, OperandInfo67 }, // Inst #350 = ADDC8O | |
| { 349, 3, 1, 4, 425, 0, 1, 0|(1ULL<<MCID::Commutable), 0xcULL, ImplicitList5, OperandInfo67 }, // Inst #349 = ADDC8 | |
| { 348, 3, 1, 4, 425, 0, 1, 0|(1ULL<<MCID::Commutable), 0xcULL, ImplicitList5, OperandInfo65 }, // Inst #348 = ADDC | |
| { 347, 3, 1, 4, 404, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList1, OperandInfo67 }, // Inst #347 = ADD8_rec | |
| { 346, 3, 1, 4, 404, 0, 0, 0, 0x8ULL, nullptr, OperandInfo69 }, // Inst #346 = ADD8TLS_ | |
| { 345, 3, 1, 4, 404, 0, 0, 0, 0x8ULL, nullptr, OperandInfo68 }, // Inst #345 = ADD8TLS | |
| { 344, 3, 1, 4, 120, 0, 2, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList4, OperandInfo67 }, // Inst #344 = ADD8O_rec | |
| { 343, 3, 1, 4, 404, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList3, OperandInfo67 }, // Inst #343 = ADD8O | |
| { 342, 3, 1, 4, 404, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo67 }, // Inst #342 = ADD8 | |
| { 341, 3, 1, 4, 404, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList1, OperandInfo65 }, // Inst #341 = ADD4_rec | |
| { 340, 3, 1, 4, 404, 0, 0, 0, 0x8ULL, nullptr, OperandInfo66 }, // Inst #340 = ADD4TLS | |
| { 339, 3, 1, 4, 120, 0, 2, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList4, OperandInfo65 }, // Inst #339 = ADD4O_rec | |
| { 338, 3, 1, 4, 404, 0, 1, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList3, OperandInfo65 }, // Inst #338 = ADD4O | |
| { 337, 3, 1, 4, 404, 0, 0, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, OperandInfo65 }, // Inst #337 = ADD4 | |
| { 336, 3, 0, 4, 219, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo60 }, // Inst #336 = XFSTOREf64 | |
| { 335, 3, 0, 4, 219, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo64 }, // Inst #335 = XFSTOREf32 | |
| { 334, 3, 1, 4, 178, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo60 }, // Inst #334 = XFLOADf64 | |
| { 333, 3, 1, 4, 213, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo64 }, // Inst #333 = XFLOADf32 | |
| { 332, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo63 }, // Inst #332 = SUBPCIS | |
| { 331, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #331 = SUBIS | |
| { 330, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #330 = SUBIC_rec | |
| { 329, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #329 = SUBIC | |
| { 328, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #328 = SUBI | |
| { 327, 3, 0, 4, 483, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo60 }, // Inst #327 = STIWX | |
| { 326, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #326 = SRWI_rec | |
| { 325, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #325 = SRWI | |
| { 324, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #324 = SRDI_rec | |
| { 323, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #323 = SRDI | |
| { 322, 3, 0, 4, 485, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, OperandInfo62 }, // Inst #322 = SPILLTOVSR_STX | |
| { 321, 3, 0, 4, 481, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo61 }, // Inst #321 = SPILLTOVSR_ST | |
| { 320, 3, 1, 4, 437, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo62 }, // Inst #320 = SPILLTOVSR_LDX | |
| { 319, 3, 1, 4, 432, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo61 }, // Inst #319 = SPILLTOVSR_LD | |
| { 318, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #318 = SLWI_rec | |
| { 317, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #317 = SLWI | |
| { 316, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #316 = SLDI_rec | |
| { 315, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #315 = SLDI | |
| { 314, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #314 = ROTRWI_rec | |
| { 313, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #313 = ROTRWI | |
| { 312, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #312 = ROTRDI_rec | |
| { 311, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #311 = ROTRDI | |
| { 310, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #310 = RLWNMbm_rec | |
| { 309, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #309 = RLWNMbm | |
| { 308, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #308 = RLWINMbm_rec | |
| { 307, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #307 = RLWINMbm | |
| { 306, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #306 = RLWIMIbm_rec | |
| { 305, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #305 = RLWIMIbm | |
| { 304, 3, 1, 4, 178, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo60 }, // Inst #304 = LIWZX | |
| { 303, 3, 1, 4, 210, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, OperandInfo60 }, // Inst #303 = LIWAX | |
| { 302, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo59 }, // Inst #302 = LAx | |
| { 301, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo58 }, // Inst #301 = KILL_PAIR | |
| { 300, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo51 }, // Inst #300 = INSRWI_rec | |
| { 299, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo51 }, // Inst #299 = INSRWI | |
| { 298, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #298 = INSRDI_rec | |
| { 297, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #297 = INSRDI | |
| { 296, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo51 }, // Inst #296 = INSLWI_rec | |
| { 295, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo51 }, // Inst #295 = INSLWI | |
| { 294, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo51 }, // Inst #294 = EXTRWI_rec | |
| { 293, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo51 }, // Inst #293 = EXTRWI | |
| { 292, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #292 = EXTRDI_rec | |
| { 291, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #291 = EXTRDI | |
| { 290, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo51 }, // Inst #290 = EXTLWI_rec | |
| { 289, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo51 }, // Inst #289 = EXTLWI | |
| { 288, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #288 = EXTLDI_rec | |
| { 287, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #287 = EXTLDI | |
| { 286, 3, 0, 4, 483, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo57 }, // Inst #286 = DFSTOREf64 | |
| { 285, 3, 0, 4, 483, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo56 }, // Inst #285 = DFSTOREf32 | |
| { 284, 3, 1, 4, 178, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo57 }, // Inst #284 = DFLOADf64 | |
| { 283, 3, 1, 4, 213, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo56 }, // Inst #283 = DFLOADf32 | |
| { 282, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #282 = DCBTx | |
| { 281, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #281 = DCBTT | |
| { 280, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #280 = DCBTSTx | |
| { 279, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #279 = DCBTSTT | |
| { 278, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo55 }, // Inst #278 = DCBTSTDS | |
| { 277, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo55 }, // Inst #277 = DCBTSTCT | |
| { 276, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo55 }, // Inst #276 = DCBTDS | |
| { 275, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo55 }, // Inst #275 = DCBTCT | |
| { 274, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #274 = DCBSTPS | |
| { 273, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #273 = DCBFx | |
| { 272, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #272 = DCBFPS | |
| { 271, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #271 = DCBFLP | |
| { 270, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #270 = DCBFL | |
| { 269, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #269 = CLRRWI_rec | |
| { 268, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #268 = CLRRWI | |
| { 267, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #267 = CLRRDI_rec | |
| { 266, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #266 = CLRRDI | |
| { 265, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo51 }, // Inst #265 = CLRLSLWI_rec | |
| { 264, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo51 }, // Inst #264 = CLRLSLWI | |
| { 263, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #263 = CLRLSLDI_rec | |
| { 262, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #262 = CLRLSLDI | |
| { 261, 1, 0, 4, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo49 }, // Inst #261 = CFENCE8 | |
| { 260, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo48 }, // Inst #260 = BUILD_UACC | |
| { 259, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo47 }, // Inst #259 = BUILD_QUADWORD | |
| { 258, 6, 2, 4, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo46 }, // Inst #258 = ATOMIC_SWAP_I128 | |
| { 257, 6, 2, 4, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo46 }, // Inst #257 = ATOMIC_LOAD_XOR_I128 | |
| { 256, 6, 2, 4, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo46 }, // Inst #256 = ATOMIC_LOAD_SUB_I128 | |
| { 255, 6, 2, 4, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo46 }, // Inst #255 = ATOMIC_LOAD_OR_I128 | |
| { 254, 6, 2, 4, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo46 }, // Inst #254 = ATOMIC_LOAD_NAND_I128 | |
| { 253, 6, 2, 4, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo46 }, // Inst #253 = ATOMIC_LOAD_AND_I128 | |
| { 252, 6, 2, 4, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo46 }, // Inst #252 = ATOMIC_LOAD_ADD_I128 | |
| { 251, 8, 2, 4, 0, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo45 }, // Inst #251 = ATOMIC_CMP_SWAP_I128 | |
| { 250, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo44 }, // Inst #250 = G_UBFX | |
| { 249, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo44 }, // Inst #249 = G_SBFX | |
| { 248, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #248 = G_VECREDUCE_UMIN | |
| { 247, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #247 = G_VECREDUCE_UMAX | |
| { 246, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #246 = G_VECREDUCE_SMIN | |
| { 245, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #245 = G_VECREDUCE_SMAX | |
| { 244, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #244 = G_VECREDUCE_XOR | |
| { 243, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #243 = G_VECREDUCE_OR | |
| { 242, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #242 = G_VECREDUCE_AND | |
| { 241, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #241 = G_VECREDUCE_MUL | |
| { 240, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #240 = G_VECREDUCE_ADD | |
| { 239, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #239 = G_VECREDUCE_FMIN | |
| { 238, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #238 = G_VECREDUCE_FMAX | |
| { 237, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #237 = G_VECREDUCE_FMUL | |
| { 236, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #236 = G_VECREDUCE_FADD | |
| { 235, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo40 }, // Inst #235 = G_VECREDUCE_SEQ_FMUL | |
| { 234, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo40 }, // Inst #234 = G_VECREDUCE_SEQ_FADD | |
| { 233, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo22 }, // Inst #233 = G_BZERO | |
| { 232, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo43 }, // Inst #232 = G_MEMSET | |
| { 231, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo43 }, // Inst #231 = G_MEMMOVE | |
| { 230, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo40 }, // Inst #230 = G_MEMCPY_INLINE | |
| { 229, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo43 }, // Inst #229 = G_MEMCPY | |
| { 228, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, OperandInfo42 }, // Inst #228 = G_WRITE_REGISTER | |
| { 227, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, OperandInfo21 }, // Inst #227 = G_READ_REGISTER | |
| { 226, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo25 }, // Inst #226 = G_STRICT_FSQRT | |
| { 225, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo19 }, // Inst #225 = G_STRICT_FMA | |
| { 224, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #224 = G_STRICT_FREM | |
| { 223, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #223 = G_STRICT_FDIV | |
| { 222, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #222 = G_STRICT_FMUL | |
| { 221, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #221 = G_STRICT_FSUB | |
| { 220, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #220 = G_STRICT_FADD | |
| { 219, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo26 }, // Inst #219 = G_DYN_STACKALLOC | |
| { 218, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #218 = G_JUMP_TABLE | |
| { 217, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #217 = G_BLOCK_ADDR | |
| { 216, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #216 = G_ADDRSPACE_CAST | |
| { 215, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #215 = G_FNEARBYINT | |
| { 214, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #214 = G_FRINT | |
| { 213, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #213 = G_FFLOOR | |
| { 212, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #212 = G_FSQRT | |
| { 211, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #211 = G_FSIN | |
| { 210, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #210 = G_FCOS | |
| { 209, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #209 = G_FCEIL | |
| { 208, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #208 = G_BITREVERSE | |
| { 207, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #207 = G_BSWAP | |
| { 206, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #206 = G_CTPOP | |
| { 205, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #205 = G_CTLZ_ZERO_UNDEF | |
| { 204, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #204 = G_CTLZ | |
| { 203, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #203 = G_CTTZ_ZERO_UNDEF | |
| { 202, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #202 = G_CTTZ | |
| { 201, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo41 }, // Inst #201 = G_SHUFFLE_VECTOR | |
| { 200, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo40 }, // Inst #200 = G_EXTRACT_VECTOR_ELT | |
| { 199, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo39 }, // Inst #199 = G_INSERT_VECTOR_ELT | |
| { 198, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo38 }, // Inst #198 = G_BRJT | |
| { 197, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo2 }, // Inst #197 = G_BR | |
| { 196, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #196 = G_LLROUND | |
| { 195, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #195 = G_LROUND | |
| { 194, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #194 = G_ABS | |
| { 193, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #193 = G_UMAX | |
| { 192, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #192 = G_UMIN | |
| { 191, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #191 = G_SMAX | |
| { 190, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #190 = G_SMIN | |
| { 189, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #189 = G_PTRMASK | |
| { 188, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #188 = G_PTR_ADD | |
| { 187, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #187 = G_FMAXIMUM | |
| { 186, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #186 = G_FMINIMUM | |
| { 185, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #185 = G_FMAXNUM_IEEE | |
| { 184, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #184 = G_FMINNUM_IEEE | |
| { 183, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #183 = G_FMAXNUM | |
| { 182, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #182 = G_FMINNUM | |
| { 181, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #181 = G_FCANONICALIZE | |
| { 180, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo32 }, // Inst #180 = G_IS_FPCLASS | |
| { 179, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #179 = G_FCOPYSIGN | |
| { 178, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #178 = G_FABS | |
| { 177, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #177 = G_UITOFP | |
| { 176, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #176 = G_SITOFP | |
| { 175, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #175 = G_FPTOUI | |
| { 174, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #174 = G_FPTOSI | |
| { 173, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #173 = G_FPTRUNC | |
| { 172, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #172 = G_FPEXT | |
| { 171, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #171 = G_FNEG | |
| { 170, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #170 = G_FLOG10 | |
| { 169, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #169 = G_FLOG2 | |
| { 168, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #168 = G_FLOG | |
| { 167, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #167 = G_FEXP2 | |
| { 166, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #166 = G_FEXP | |
| { 165, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #165 = G_FPOWI | |
| { 164, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #164 = G_FPOW | |
| { 163, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #163 = G_FREM | |
| { 162, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #162 = G_FDIV | |
| { 161, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo19 }, // Inst #161 = G_FMAD | |
| { 160, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo19 }, // Inst #160 = G_FMA | |
| { 159, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #159 = G_FMUL | |
| { 158, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #158 = G_FSUB | |
| { 157, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #157 = G_FADD | |
| { 156, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo37 }, // Inst #156 = G_UDIVFIXSAT | |
| { 155, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo37 }, // Inst #155 = G_SDIVFIXSAT | |
| { 154, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo37 }, // Inst #154 = G_UDIVFIX | |
| { 153, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo37 }, // Inst #153 = G_SDIVFIX | |
| { 152, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo37 }, // Inst #152 = G_UMULFIXSAT | |
| { 151, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo37 }, // Inst #151 = G_SMULFIXSAT | |
| { 150, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo37 }, // Inst #150 = G_UMULFIX | |
| { 149, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo37 }, // Inst #149 = G_SMULFIX | |
| { 148, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #148 = G_SSHLSAT | |
| { 147, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #147 = G_USHLSAT | |
| { 146, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #146 = G_SSUBSAT | |
| { 145, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #145 = G_USUBSAT | |
| { 144, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #144 = G_SADDSAT | |
| { 143, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #143 = G_UADDSAT | |
| { 142, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #142 = G_SMULH | |
| { 141, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #141 = G_UMULH | |
| { 140, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo30 }, // Inst #140 = G_SMULO | |
| { 139, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo30 }, // Inst #139 = G_UMULO | |
| { 138, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo36 }, // Inst #138 = G_SSUBE | |
| { 137, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo30 }, // Inst #137 = G_SSUBO | |
| { 136, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo36 }, // Inst #136 = G_SADDE | |
| { 135, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo30 }, // Inst #135 = G_SADDO | |
| { 134, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo36 }, // Inst #134 = G_USUBE | |
| { 133, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo30 }, // Inst #133 = G_USUBO | |
| { 132, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo36 }, // Inst #132 = G_UADDE | |
| { 131, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo30 }, // Inst #131 = G_UADDO | |
| { 130, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo30 }, // Inst #130 = G_SELECT | |
| { 129, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo35 }, // Inst #129 = G_FCMP | |
| { 128, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo35 }, // Inst #128 = G_ICMP | |
| { 127, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #127 = G_ROTL | |
| { 126, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #126 = G_ROTR | |
| { 125, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo34 }, // Inst #125 = G_FSHR | |
| { 124, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo34 }, // Inst #124 = G_FSHL | |
| { 123, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #123 = G_ASHR | |
| { 122, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #122 = G_LSHR | |
| { 121, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #121 = G_SHL | |
| { 120, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #120 = G_ZEXT | |
| { 119, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo17 }, // Inst #119 = G_SEXT_INREG | |
| { 118, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #118 = G_SEXT | |
| { 117, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo32 }, // Inst #117 = G_VAARG | |
| { 116, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo20 }, // Inst #116 = G_VASTART | |
| { 115, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #115 = G_FCONSTANT | |
| { 114, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #114 = G_CONSTANT | |
| { 113, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #113 = G_TRUNC | |
| { 112, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #112 = G_ANYEXT | |
| { 111, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, OperandInfo2 }, // Inst #111 = G_INTRINSIC_W_SIDE_EFFECTS | |
| { 110, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, OperandInfo2 }, // Inst #110 = G_INTRINSIC | |
| { 109, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr }, // Inst #109 = G_INVOKE_REGION_START | |
| { 108, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo20 }, // Inst #108 = G_BRINDIRECT | |
| { 107, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo21 }, // Inst #107 = G_BRCOND | |
| { 106, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo10 }, // Inst #106 = G_FENCE | |
| { 105, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #105 = G_ATOMICRMW_UDEC_WRAP | |
| { 104, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #104 = G_ATOMICRMW_UINC_WRAP | |
| { 103, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #103 = G_ATOMICRMW_FMIN | |
| { 102, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #102 = G_ATOMICRMW_FMAX | |
| { 101, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #101 = G_ATOMICRMW_FSUB | |
| { 100, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #100 = G_ATOMICRMW_FADD | |
| { 99, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #99 = G_ATOMICRMW_UMIN | |
| { 98, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #98 = G_ATOMICRMW_UMAX | |
| { 97, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #97 = G_ATOMICRMW_MIN | |
| { 96, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #96 = G_ATOMICRMW_MAX | |
| { 95, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #95 = G_ATOMICRMW_XOR | |
| { 94, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #94 = G_ATOMICRMW_OR | |
| { 93, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #93 = G_ATOMICRMW_NAND | |
| { 92, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #92 = G_ATOMICRMW_AND | |
| { 91, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #91 = G_ATOMICRMW_SUB | |
| { 90, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #90 = G_ATOMICRMW_ADD | |
| { 89, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #89 = G_ATOMICRMW_XCHG | |
| { 88, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo30 }, // Inst #88 = G_ATOMIC_CMPXCHG | |
| { 87, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo29 }, // Inst #87 = G_ATOMIC_CMPXCHG_WITH_SUCCESS | |
| { 86, 5, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo28 }, // Inst #86 = G_INDEXED_STORE | |
| { 85, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo23 }, // Inst #85 = G_STORE | |
| { 84, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo27 }, // Inst #84 = G_INDEXED_ZEXTLOAD | |
| { 83, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo27 }, // Inst #83 = G_INDEXED_SEXTLOAD | |
| { 82, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo27 }, // Inst #82 = G_INDEXED_LOAD | |
| { 81, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo23 }, // Inst #81 = G_ZEXTLOAD | |
| { 80, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo23 }, // Inst #80 = G_SEXTLOAD | |
| { 79, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo23 }, // Inst #79 = G_LOAD | |
| { 78, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo20 }, // Inst #78 = G_READCYCLECOUNTER | |
| { 77, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #77 = G_INTRINSIC_ROUNDEVEN | |
| { 76, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #76 = G_INTRINSIC_LRINT | |
| { 75, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #75 = G_INTRINSIC_ROUND | |
| { 74, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #74 = G_INTRINSIC_TRUNC | |
| { 73, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo26 }, // Inst #73 = G_INTRINSIC_FPTRUNC_ROUND | |
| { 72, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #72 = G_FREEZE | |
| { 71, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #71 = G_BITCAST | |
| { 70, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #70 = G_INTTOPTR | |
| { 69, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #69 = G_PTRTOINT | |
| { 68, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #68 = G_CONCAT_VECTORS | |
| { 67, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #67 = G_BUILD_VECTOR_TRUNC | |
| { 66, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #66 = G_BUILD_VECTOR | |
| { 65, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #65 = G_MERGE_VALUES | |
| { 64, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo24 }, // Inst #64 = G_INSERT | |
| { 63, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #63 = G_UNMERGE_VALUES | |
| { 62, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo22 }, // Inst #62 = G_EXTRACT | |
| { 61, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #61 = G_GLOBAL_VALUE | |
| { 60, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #60 = G_FRAME_INDEX | |
| { 59, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo20 }, // Inst #59 = G_PHI | |
| { 58, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo20 }, // Inst #58 = G_IMPLICIT_DEF | |
| { 57, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #57 = G_XOR | |
| { 56, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #56 = G_OR | |
| { 55, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #55 = G_AND | |
| { 54, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo19 }, // Inst #54 = G_UDIVREM | |
| { 53, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo19 }, // Inst #53 = G_SDIVREM | |
| { 52, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #52 = G_UREM | |
| { 51, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #51 = G_SREM | |
| { 50, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #50 = G_UDIV | |
| { 49, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #49 = G_SDIV | |
| { 48, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #48 = G_MUL | |
| { 47, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #47 = G_SUB | |
| { 46, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #46 = G_ADD | |
| { 45, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo17 }, // Inst #45 = G_ASSERT_ALIGN | |
| { 44, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo17 }, // Inst #44 = G_ASSERT_ZEXT | |
| { 43, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo17 }, // Inst #43 = G_ASSERT_SEXT | |
| { 42, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #42 = MEMBARRIER | |
| { 41, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #41 = ICALL_BRANCH_FUNNEL | |
| { 40, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo16 }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL | |
| { 39, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo15 }, // Inst #39 = PATCHABLE_EVENT_CALL | |
| { 38, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #38 = PATCHABLE_TAIL_CALL | |
| { 37, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #37 = PATCHABLE_FUNCTION_EXIT | |
| { 36, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #36 = PATCHABLE_RET | |
| { 35, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #35 = PATCHABLE_FUNCTION_ENTER | |
| { 34, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #34 = PATCHABLE_OP | |
| { 33, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #33 = FAULTING_OP | |
| { 32, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo14 }, // Inst #32 = LOCAL_ESCAPE | |
| { 31, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #31 = STATEPOINT | |
| { 30, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo13 }, // Inst #30 = PREALLOCATED_ARG | |
| { 29, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo3 }, // Inst #29 = PREALLOCATED_SETUP | |
| { 28, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo12 }, // Inst #28 = LOAD_STACK_GUARD | |
| { 27, 6, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo11 }, // Inst #27 = PATCHPOINT | |
| { 26, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #26 = FENTRY_CALL | |
| { 25, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo10 }, // Inst #25 = STACKMAP | |
| { 24, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL, nullptr, OperandInfo9 }, // Inst #24 = ARITH_FENCE | |
| { 23, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo8 }, // Inst #23 = PSEUDO_PROBE | |
| { 22, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL, nullptr, OperandInfo3 }, // Inst #22 = LIFETIME_END | |
| { 21, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL, nullptr, OperandInfo3 }, // Inst #21 = LIFETIME_START | |
| { 20, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #20 = BUNDLE | |
| { 19, 2, 1, 0, 121, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo7 }, // Inst #19 = COPY | |
| { 18, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo7 }, // Inst #18 = REG_SEQUENCE | |
| { 17, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL, nullptr, OperandInfo2 }, // Inst #17 = DBG_LABEL | |
| { 16, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #16 = DBG_PHI | |
| { 15, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #15 = DBG_INSTR_REF | |
| { 14, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #14 = DBG_VALUE_LIST | |
| { 13, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #13 = DBG_VALUE | |
| { 12, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo4 }, // Inst #12 = COPY_TO_REGCLASS | |
| { 11, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo6 }, // Inst #11 = SUBREG_TO_REG | |
| { 10, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo2 }, // Inst #10 = IMPLICIT_DEF | |
| { 9, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo5 }, // Inst #9 = INSERT_SUBREG | |
| { 8, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo4 }, // Inst #8 = EXTRACT_SUBREG | |
| { 7, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #7 = KILL | |
| { 6, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo3 }, // Inst #6 = ANNOTATION_LABEL | |
| { 5, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo3 }, // Inst #5 = GC_LABEL | |
| { 4, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo3 }, // Inst #4 = EH_LABEL | |
| { 3, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo3 }, // Inst #3 = CFI_INSTRUCTION | |
| { 2, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #2 = INLINEASM_BR | |
| { 1, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #1 = INLINEASM | |
| { 0, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo2 }, // Inst #0 = PHI | |
| }; | |
| #ifdef __GNUC__ | |
| #pragma GCC diagnostic push | |
| #pragma GCC diagnostic ignored "-Woverlength-strings" | |
| #endif | |
| extern const char PPCInstrNameData[] = { | |
| /* 0 */ "G_FLOG10\0" | |
| /* 9 */ "MTFSB0\0" | |
| /* 16 */ "V_SET0\0" | |
| /* 23 */ "VCTSXS_0\0" | |
| /* 32 */ "VCTUXS_0\0" | |
| /* 41 */ "VCFSX_0\0" | |
| /* 49 */ "VCFUX_0\0" | |
| /* 57 */ "MTFSB1\0" | |
| /* 64 */ "DMXXINSTFDMR512\0" | |
| /* 80 */ "DMXXEXTFDMR512\0" | |
| /* 95 */ "ADDISdtprelHA32\0" | |
| /* 111 */ "ATOMIC_LOAD_SUB_I32\0" | |
| /* 131 */ "ATOMIC_LOAD_ADD_I32\0" | |
| /* 151 */ "ATOMIC_LOAD_NAND_I32\0" | |
| /* 172 */ "ATOMIC_LOAD_AND_I32\0" | |
| /* 192 */ "ATOMIC_LOAD_UMIN_I32\0" | |
| /* 213 */ "ATOMIC_LOAD_MIN_I32\0" | |
| /* 233 */ "ATOMIC_SWAP_I32\0" | |
| /* 249 */ "ATOMIC_CMP_SWAP_I32\0" | |
| /* 269 */ "ATOMIC_LOAD_XOR_I32\0" | |
| /* 289 */ "ATOMIC_LOAD_OR_I32\0" | |
| /* 308 */ "ATOMIC_LOAD_UMAX_I32\0" | |
| /* 329 */ "ATOMIC_LOAD_MAX_I32\0" | |
| /* 349 */ "ADDItlsgdL32\0" | |
| /* 362 */ "ADDItlsldL32\0" | |
| /* 375 */ "LDgotTprelL32\0" | |
| /* 389 */ "ADDIdtprelL32\0" | |
| /* 403 */ "ADDItlsgdLADDR32\0" | |
| /* 420 */ "ADDItlsldLADDR32\0" | |
| /* 437 */ "GETtlsldADDR32\0" | |
| /* 452 */ "GETtlsADDR32\0" | |
| /* 465 */ "PREPARE_PROBED_ALLOCA_32\0" | |
| /* 490 */ "LWA_32\0" | |
| /* 497 */ "PROBED_STACKALLOC_32\0" | |
| /* 518 */ "PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32\0" | |
| /* 560 */ "SRADI_32\0" | |
| /* 569 */ "RLDICL_32\0" | |
| /* 579 */ "RLDICR_32\0" | |
| /* 589 */ "STBXTLS_32\0" | |
| /* 600 */ "STHXTLS_32\0" | |
| /* 611 */ "STWXTLS_32\0" | |
| /* 622 */ "LBZXTLS_32\0" | |
| /* 633 */ "LHZXTLS_32\0" | |
| /* 644 */ "LWZXTLS_32\0" | |
| /* 655 */ "EXTSW_32\0" | |
| /* 664 */ "LWAX_32\0" | |
| /* 672 */ "DFLOADf32\0" | |
| /* 682 */ "XFLOADf32\0" | |
| /* 692 */ "DFSTOREf32\0" | |
| /* 703 */ "XFSTOREf32\0" | |
| /* 714 */ "EH_SjLj_LongJmp32\0" | |
| /* 732 */ "EH_SjLj_SetJmp32\0" | |
| /* 749 */ "TLBRE2\0" | |
| /* 756 */ "TLBWE2\0" | |
| /* 763 */ "G_FLOG2\0" | |
| /* 771 */ "G_FEXP2\0" | |
| /* 779 */ "PMXVBF16GER2\0" | |
| /* 792 */ "PMXVF16GER2\0" | |
| /* 804 */ "PMXVI16GER2\0" | |
| /* 816 */ "TLBSX2\0" | |
| /* 823 */ "ATOMIC_LOAD_SUB_I64\0" | |
| /* 843 */ "ATOMIC_LOAD_ADD_I64\0" | |
| /* 863 */ "ATOMIC_LOAD_NAND_I64\0" | |
| /* 884 */ "ATOMIC_LOAD_AND_I64\0" | |
| /* 904 */ "ATOMIC_LOAD_UMIN_I64\0" | |
| /* 925 */ "ATOMIC_LOAD_MIN_I64\0" | |
| /* 945 */ "ATOMIC_SWAP_I64\0" | |
| /* 961 */ "ATOMIC_CMP_SWAP_I64\0" | |
| /* 981 */ "ATOMIC_LOAD_XOR_I64\0" | |
| /* 1001 */ "ATOMIC_LOAD_OR_I64\0" | |
| /* 1020 */ "ATOMIC_LOAD_UMAX_I64\0" | |
| /* 1041 */ "ATOMIC_LOAD_MAX_I64\0" | |
| /* 1061 */ "DST64\0" | |
| /* 1067 */ "DSTST64\0" | |
| /* 1075 */ "DSTT64\0" | |
| /* 1082 */ "DSTSTT64\0" | |
| /* 1091 */ "EXTSB8_32_64\0" | |
| /* 1104 */ "EXTSH8_32_64\0" | |
| /* 1117 */ "EXTSWSLI_32_64\0" | |
| /* 1132 */ "RLDICL_32_64\0" | |
| /* 1145 */ "EXTSW_32_64\0" | |
| /* 1157 */ "PREPARE_PROBED_ALLOCA_64\0" | |
| /* 1182 */ "PROBED_STACKALLOC_64\0" | |
| /* 1203 */ "PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64\0" | |
| /* 1245 */ "DFLOADf64\0" | |
| /* 1255 */ "XFLOADf64\0" | |
| /* 1265 */ "DFSTOREf64\0" | |
| /* 1276 */ "XFSTOREf64\0" | |
| /* 1287 */ "EH_SjLj_LongJmp64\0" | |
| /* 1305 */ "EH_SjLj_SetJmp64\0" | |
| /* 1322 */ "ADD4\0" | |
| /* 1327 */ "SELECT_CC_SPE4\0" | |
| /* 1342 */ "SELECT_SPE4\0" | |
| /* 1354 */ "SELECT_CC_F4\0" | |
| /* 1367 */ "SELECT_F4\0" | |
| /* 1377 */ "SELECT_CC_I4\0" | |
| /* 1390 */ "SELECT_I4\0" | |
| /* 1400 */ "PMXVI8GER4\0" | |
| /* 1411 */ "XVCVSPBF16\0" | |
| /* 1422 */ "SELECT_CC_F16\0" | |
| /* 1436 */ "SELECT_F16\0" | |
| /* 1447 */ "ATOMIC_LOAD_SUB_I16\0" | |
| /* 1467 */ "ATOMIC_LOAD_ADD_I16\0" | |
| /* 1487 */ "ATOMIC_LOAD_NAND_I16\0" | |
| /* 1508 */ "ATOMIC_LOAD_AND_I16\0" | |
| /* 1528 */ "ATOMIC_LOAD_UMIN_I16\0" | |
| /* 1549 */ "ATOMIC_LOAD_MIN_I16\0" | |
| /* 1569 */ "ATOMIC_SWAP_I16\0" | |
| /* 1585 */ "ATOMIC_CMP_SWAP_I16\0" | |
| /* 1605 */ "ATOMIC_LOAD_XOR_I16\0" | |
| /* 1625 */ "ATOMIC_LOAD_OR_I16\0" | |
| /* 1644 */ "ATOMIC_LOAD_UMAX_I16\0" | |
| /* 1665 */ "ATOMIC_LOAD_MAX_I16\0" | |
| /* 1685 */ "DMXXINSTFDMR256\0" | |
| /* 1701 */ "DMXXEXTFDMR256\0" | |
| /* 1716 */ "NOP_GT_PWR6\0" | |
| /* 1728 */ "NOP_GT_PWR7\0" | |
| /* 1740 */ "ATOMIC_LOAD_SUB_I128\0" | |
| /* 1761 */ "ATOMIC_LOAD_ADD_I128\0" | |
| /* 1782 */ "ATOMIC_LOAD_NAND_I128\0" | |
| /* 1804 */ "ATOMIC_LOAD_AND_I128\0" | |
| /* 1825 */ "ATOMIC_SWAP_I128\0" | |
| /* 1842 */ "ATOMIC_CMP_SWAP_I128\0" | |
| /* 1863 */ "ATOMIC_LOAD_XOR_I128\0" | |
| /* 1884 */ "ATOMIC_LOAD_OR_I128\0" | |
| /* 1904 */ "TAILBA8\0" | |
| /* 1912 */ "PLHA8\0" | |
| /* 1918 */ "ADDIStocHA8\0" | |
| /* 1930 */ "BLA8\0" | |
| /* 1935 */ "PLWA8\0" | |
| /* 1941 */ "TAILB8\0" | |
| /* 1948 */ "CMPB8\0" | |
| /* 1954 */ "CMPRB8\0" | |
| /* 1961 */ "EXTSB8\0" | |
| /* 1968 */ "SETB8\0" | |
| /* 1974 */ "MFTB8\0" | |
| /* 1980 */ "POPCNTB8\0" | |
| /* 1989 */ "PSTB8\0" | |
| /* 1995 */ "SETNBC8\0" | |
| /* 2003 */ "SETBC8\0" | |
| /* 2010 */ "ADDC8\0" | |
| /* 2016 */ "ANDC8\0" | |
| /* 2022 */ "SUBFC8\0" | |
| /* 2029 */ "ADDIC8\0" | |
| /* 2036 */ "SUBFIC8\0" | |
| /* 2044 */ "DYNALLOC8\0" | |
| /* 2054 */ "ORC8\0" | |
| /* 2059 */ "ADD8\0" | |
| /* 2064 */ "MADDLD8\0" | |
| /* 2072 */ "NAND8\0" | |
| /* 2078 */ "CFENCE8\0" | |
| /* 2086 */ "ADDE8\0" | |
| /* 2092 */ "SUBFE8\0" | |
| /* 2099 */ "ADDME8\0" | |
| /* 2106 */ "SUBFME8\0" | |
| /* 2114 */ "ADDZE8\0" | |
| /* 2121 */ "SUBFZE8\0" | |
| /* 2129 */ "SUBF8\0" | |
| /* 2135 */ "MFOCRF8\0" | |
| /* 2143 */ "MTOCRF8\0" | |
| /* 2151 */ "MTCRF8\0" | |
| /* 2158 */ "SELECT_CC_F8\0" | |
| /* 2171 */ "SELECT_F8\0" | |
| /* 2181 */ "NEG8\0" | |
| /* 2186 */ "BRH8\0" | |
| /* 2191 */ "EXTSH8\0" | |
| /* 2198 */ "PSTH8\0" | |
| /* 2204 */ "PADDI8\0" | |
| /* 2211 */ "MULLI8\0" | |
| /* 2218 */ "PLI8\0" | |
| /* 2223 */ "RLWIMI8\0" | |
| /* 2231 */ "XORI8\0" | |
| /* 2237 */ "ATOMIC_LOAD_SUB_I8\0" | |
| /* 2256 */ "SELECT_CC_I8\0" | |
| /* 2269 */ "ATOMIC_LOAD_ADD_I8\0" | |
| /* 2288 */ "ATOMIC_LOAD_NAND_I8\0" | |
| /* 2308 */ "ATOMIC_LOAD_AND_I8\0" | |
| /* 2327 */ "ATOMIC_LOAD_UMIN_I8\0" | |
| /* 2347 */ "ATOMIC_LOAD_MIN_I8\0" | |
| /* 2366 */ "ATOMIC_SWAP_I8\0" | |
| /* 2381 */ "ATOMIC_CMP_SWAP_I8\0" | |
| /* 2400 */ "ATOMIC_LOAD_XOR_I8\0" | |
| /* 2419 */ "ATOMIC_LOAD_OR_I8\0" | |
| /* 2437 */ "SELECT_I8\0" | |
| /* 2447 */ "ATOMIC_LOAD_UMAX_I8\0" | |
| /* 2467 */ "ATOMIC_LOAD_MAX_I8\0" | |
| /* 2486 */ "HASHCHK8\0" | |
| /* 2495 */ "BL8\0" | |
| /* 2499 */ "ISEL8\0" | |
| /* 2505 */ "BCTRL8\0" | |
| /* 2512 */ "BCCTRL8\0" | |
| /* 2520 */ "BCCCTRL8\0" | |
| /* 2529 */ "RLWINM8\0" | |
| /* 2537 */ "RLWNM8\0" | |
| /* 2544 */ "HASHCHKP8\0" | |
| /* 2554 */ "HASHSTP8\0" | |
| /* 2563 */ "SETNBCR8\0" | |
| /* 2572 */ "SETBCR8\0" | |
| /* 2580 */ "MFCR8\0" | |
| /* 2586 */ "PMXVI4GER8\0" | |
| /* 2597 */ "BLR8\0" | |
| /* 2602 */ "MFLR8\0" | |
| /* 2608 */ "MTLR8\0" | |
| /* 2614 */ "BDZLR8\0" | |
| /* 2621 */ "BDNZLR8\0" | |
| /* 2629 */ "MovePCtoLR8\0" | |
| /* 2641 */ "NOR8\0" | |
| /* 2646 */ "XOR8\0" | |
| /* 2651 */ "MFSPR8\0" | |
| /* 2658 */ "MTSPR8\0" | |
| /* 2665 */ "TAILBCTR8\0" | |
| /* 2675 */ "BCCTR8\0" | |
| /* 2682 */ "BCCCTR8\0" | |
| /* 2690 */ "MFCTR8\0" | |
| /* 2697 */ "MTCTR8\0" | |
| /* 2704 */ "ADDIS8\0" | |
| /* 2711 */ "LIS8\0" | |
| /* 2716 */ "XORIS8\0" | |
| /* 2723 */ "DYNAREAOFFSET8\0" | |
| /* 2738 */ "ANDI_rec_1_EQ_BIT8\0" | |
| /* 2757 */ "ANDI_rec_1_GT_BIT8\0" | |
| /* 2776 */ "HASHST8\0" | |
| /* 2784 */ "LHAU8\0" | |
| /* 2790 */ "STBU8\0" | |
| /* 2796 */ "STHU8\0" | |
| /* 2802 */ "STWU8\0" | |
| /* 2808 */ "LBZU8\0" | |
| /* 2814 */ "LHZU8\0" | |
| /* 2820 */ "LWZU8\0" | |
| /* 2826 */ "EQV8\0" | |
| /* 2831 */ "SLW8\0" | |
| /* 2836 */ "BRW8\0" | |
| /* 2841 */ "SRW8\0" | |
| /* 2846 */ "PSTW8\0" | |
| /* 2852 */ "CNTLZW8\0" | |
| /* 2860 */ "CNTTZW8\0" | |
| /* 2868 */ "LHAX8\0" | |
| /* 2874 */ "STBX8\0" | |
| /* 2880 */ "ADDEX8\0" | |
| /* 2887 */ "STHX8\0" | |
| /* 2893 */ "TLSGDAIX8\0" | |
| /* 2903 */ "LHBRX8\0" | |
| /* 2910 */ "LWBRX8\0" | |
| /* 2917 */ "LHAUX8\0" | |
| /* 2924 */ "STBUX8\0" | |
| /* 2931 */ "STHUX8\0" | |
| /* 2938 */ "STWUX8\0" | |
| /* 2945 */ "LBZUX8\0" | |
| /* 2952 */ "LHZUX8\0" | |
| /* 2959 */ "LWZUX8\0" | |
| /* 2966 */ "STWX8\0" | |
| /* 2972 */ "LBZX8\0" | |
| /* 2978 */ "LHZX8\0" | |
| /* 2984 */ "LWZX8\0" | |
| /* 2990 */ "CP_COPY8\0" | |
| /* 2999 */ "PLBZ8\0" | |
| /* 3005 */ "BDZ8\0" | |
| /* 3010 */ "PLHZ8\0" | |
| /* 3016 */ "BDNZ8\0" | |
| /* 3022 */ "PLWZ8\0" | |
| /* 3028 */ "ADDItoc8\0" | |
| /* 3037 */ "TCRETURNai8\0" | |
| /* 3049 */ "TCRETURNdi8\0" | |
| /* 3061 */ "TCRETURNri8\0" | |
| /* 3073 */ "EVMHEGSMFAA\0" | |
| /* 3085 */ "EVMHOGSMFAA\0" | |
| /* 3097 */ "EVMWSMFAA\0" | |
| /* 3107 */ "EVMWSSFAA\0" | |
| /* 3117 */ "EVMHEGSMIAA\0" | |
| /* 3129 */ "EVMHOGSMIAA\0" | |
| /* 3141 */ "EVMWSMIAA\0" | |
| /* 3151 */ "EVMHEGUMIAA\0" | |
| /* 3163 */ "EVMHOGUMIAA\0" | |
| /* 3175 */ "EVMWUMIAA\0" | |
| /* 3185 */ "DCBA\0" | |
| /* 3190 */ "TAILBA\0" | |
| /* 3197 */ "LDtocBA\0" | |
| /* 3205 */ "gBCA\0" | |
| /* 3210 */ "BCCA\0" | |
| /* 3215 */ "EVMHESMFA\0" | |
| /* 3225 */ "EVMWHSMFA\0" | |
| /* 3235 */ "EVMHOSMFA\0" | |
| /* 3245 */ "EVMWSMFA\0" | |
| /* 3254 */ "EVMHESSFA\0" | |
| /* 3264 */ "EVMWHSSFA\0" | |
| /* 3274 */ "EVMHOSSFA\0" | |
| /* 3284 */ "EVMWSSFA\0" | |
| /* 3293 */ "PLHA\0" | |
| /* 3298 */ "ADDIStocHA\0" | |
| /* 3309 */ "ADDIStlsgdHA\0" | |
| /* 3322 */ "ADDIStlsldHA\0" | |
| /* 3335 */ "ADDISgotTprelHA\0" | |
| /* 3351 */ "ADDISdtprelHA\0" | |
| /* 3365 */ "SLBIA\0" | |
| /* 3371 */ "TLBIA\0" | |
| /* 3377 */ "EVMHESMIA\0" | |
| /* 3387 */ "EVMWHSMIA\0" | |
| /* 3397 */ "EVMHOSMIA\0" | |
| /* 3407 */ "EVMWSMIA\0" | |
| /* 3416 */ "EVMHEUMIA\0" | |
| /* 3426 */ "EVMWHUMIA\0" | |
| /* 3436 */ "EVMWLUMIA\0" | |
| /* 3446 */ "EVMHOUMIA\0" | |
| /* 3456 */ "EVMWUMIA\0" | |
| /* 3465 */ "BLA\0" | |
| /* 3469 */ "gBCLA\0" | |
| /* 3475 */ "BCCLA\0" | |
| /* 3481 */ "BDZLA\0" | |
| /* 3487 */ "BDNZLA\0" | |
| /* 3494 */ "G_FMA\0" | |
| /* 3500 */ "G_STRICT_FMA\0" | |
| /* 3513 */ "EVMRA\0" | |
| /* 3519 */ "PLWA\0" | |
| /* 3524 */ "MTVSRWA\0" | |
| /* 3532 */ "MTVRWA\0" | |
| /* 3539 */ "BDZA\0" | |
| /* 3544 */ "BDNZA\0" | |
| /* 3550 */ "V_SET0B\0" | |
| /* 3558 */ "VSRAB\0" | |
| /* 3564 */ "RFEBB\0" | |
| /* 3570 */ "VCNTMBB\0" | |
| /* 3578 */ "XVTLSBB\0" | |
| /* 3586 */ "VCLZLSBB\0" | |
| /* 3595 */ "VCTZLSBB\0" | |
| /* 3604 */ "VCMPNEB\0" | |
| /* 3612 */ "VMRGHB\0" | |
| /* 3619 */ "XXSPLTIB\0" | |
| /* 3628 */ "VMRGLB\0" | |
| /* 3635 */ "TAILB\0" | |
| /* 3641 */ "VCLRLB\0" | |
| /* 3648 */ "VRLB\0" | |
| /* 3653 */ "VSLB\0" | |
| /* 3658 */ "VPMSUMB\0" | |
| /* 3666 */ "VGNB\0" | |
| /* 3671 */ "CMPB\0" | |
| /* 3676 */ "CMPEQB\0" | |
| /* 3683 */ "CLRBHRB\0" | |
| /* 3691 */ "CMPRB\0" | |
| /* 3697 */ "VCLRRB\0" | |
| /* 3704 */ "VSRB\0" | |
| /* 3709 */ "VMULESB\0" | |
| /* 3717 */ "V_SETALLONESB\0" | |
| /* 3731 */ "VAVGSB\0" | |
| /* 3738 */ "VUPKHSB\0" | |
| /* 3746 */ "VSPLTISB\0" | |
| /* 3755 */ "VUPKLSB\0" | |
| /* 3763 */ "VMINSB\0" | |
| /* 3770 */ "VMULOSB\0" | |
| /* 3778 */ "VCMPGTSB\0" | |
| /* 3787 */ "EVEXTSB\0" | |
| /* 3795 */ "VMAXSB\0" | |
| /* 3802 */ "SETB\0" | |
| /* 3807 */ "MFTB\0" | |
| /* 3812 */ "VSPLTB\0" | |
| /* 3819 */ "VPOPCNTB\0" | |
| /* 3828 */ "VINSERTB\0" | |
| /* 3837 */ "PSTB\0" | |
| /* 3842 */ "ReadTB\0" | |
| /* 3849 */ "VABSDUB\0" | |
| /* 3857 */ "VMULEUB\0" | |
| /* 3865 */ "VAVGUB\0" | |
| /* 3872 */ "VMINUB\0" | |
| /* 3879 */ "VMULOUB\0" | |
| /* 3887 */ "VCMPEQUB\0" | |
| /* 3896 */ "EFDSUB\0" | |
| /* 3903 */ "G_FSUB\0" | |
| /* 3910 */ "G_STRICT_FSUB\0" | |
| /* 3924 */ "G_ATOMICRMW_FSUB\0" | |
| /* 3941 */ "FMSUB\0" | |
| /* 3947 */ "FNMSUB\0" | |
| /* 3954 */ "EFSSUB\0" | |
| /* 3961 */ "EVFSSUB\0" | |
| /* 3969 */ "G_SUB\0" | |
| /* 3975 */ "G_ATOMICRMW_SUB\0" | |
| /* 3991 */ "VEXTRACTUB\0" | |
| /* 4002 */ "VCMPGTUB\0" | |
| /* 4011 */ "VMAXUB\0" | |
| /* 4018 */ "XXBLENDVB\0" | |
| /* 4028 */ "VCMPNEZB\0" | |
| /* 4037 */ "VCLZB\0" | |
| /* 4043 */ "VCTZB\0" | |
| /* 4049 */ "SETNBC\0" | |
| /* 4056 */ "SETBC\0" | |
| /* 4062 */ "gBC\0" | |
| /* 4066 */ "XXMFACC\0" | |
| /* 4074 */ "XXMTACC\0" | |
| /* 4082 */ "BUILD_UACC\0" | |
| /* 4093 */ "RESTORE_UACC\0" | |
| /* 4106 */ "SPILL_UACC\0" | |
| /* 4117 */ "RESTORE_WACC\0" | |
| /* 4130 */ "SPILL_WACC\0" | |
| /* 4141 */ "RESTORE_ACC\0" | |
| /* 4153 */ "SPILL_ACC\0" | |
| /* 4163 */ "BCC\0" | |
| /* 4167 */ "ADDC\0" | |
| /* 4172 */ "XXLANDC\0" | |
| /* 4180 */ "CRANDC\0" | |
| /* 4187 */ "EVANDC\0" | |
| /* 4194 */ "TABORTDC\0" | |
| /* 4203 */ "SUBFC\0" | |
| /* 4209 */ "SUBIC\0" | |
| /* 4215 */ "ADDIC\0" | |
| /* 4221 */ "RLDIC\0" | |
| /* 4227 */ "SUBFIC\0" | |
| /* 4234 */ "XSRDPIC\0" | |
| /* 4242 */ "XVRDPIC\0" | |
| /* 4250 */ "XVRSPIC\0" | |
| /* 4258 */ "G_INTRINSIC\0" | |
| /* 4270 */ "ICBLC\0" | |
| /* 4276 */ "BRINC\0" | |
| /* 4282 */ "G_FPTRUNC\0" | |
| /* 4292 */ "G_INTRINSIC_TRUNC\0" | |
| /* 4310 */ "G_TRUNC\0" | |
| /* 4318 */ "G_BUILD_VECTOR_TRUNC\0" | |
| /* 4339 */ "SLBSYNC\0" | |
| /* 4347 */ "TLBSYNC\0" | |
| /* 4355 */ "MSGSYNC\0" | |
| /* 4363 */ "ISYNC\0" | |
| /* 4369 */ "MSYNC\0" | |
| /* 4375 */ "G_DYN_STACKALLOC\0" | |
| /* 4392 */ "DYNALLOC\0" | |
| /* 4401 */ "BL8_NOTOC\0" | |
| /* 4411 */ "SELECT_CC_VSFRC\0" | |
| /* 4427 */ "SELECT_VSFRC\0" | |
| /* 4440 */ "XXLORC\0" | |
| /* 4447 */ "CRORC\0" | |
| /* 4453 */ "EVORC\0" | |
| /* 4459 */ "SELECT_CC_VRRC\0" | |
| /* 4474 */ "SELECT_VRRC\0" | |
| /* 4486 */ "SELECT_CC_VSSRC\0" | |
| /* 4502 */ "SELECT_VSSRC\0" | |
| /* 4515 */ "SELECT_CC_VSRC\0" | |
| /* 4530 */ "SELECT_VSRC\0" | |
| /* 4542 */ "SC\0" | |
| /* 4545 */ "TABORTWC\0" | |
| /* 4554 */ "VEXTSB2D\0" | |
| /* 4563 */ "VEXTSH2D\0" | |
| /* 4572 */ "VEXTSW2D\0" | |
| /* 4581 */ "TLBSX2D\0" | |
| /* 4589 */ "G_FMAD\0" | |
| /* 4596 */ "VSHASIGMAD\0" | |
| /* 4607 */ "G_INDEXED_SEXTLOAD\0" | |
| /* 4626 */ "G_SEXTLOAD\0" | |
| /* 4637 */ "G_INDEXED_ZEXTLOAD\0" | |
| /* 4656 */ "G_ZEXTLOAD\0" | |
| /* 4667 */ "G_INDEXED_LOAD\0" | |
| /* 4682 */ "G_LOAD\0" | |
| /* 4689 */ "VSRAD\0" | |
| /* 4695 */ "VGBBD\0" | |
| /* 4701 */ "VCNTMBD\0" | |
| /* 4709 */ "VPRTYBD\0" | |
| /* 4717 */ "EFDADD\0" | |
| /* 4724 */ "G_VECREDUCE_FADD\0" | |
| /* 4741 */ "G_FADD\0" | |
| /* 4748 */ "G_VECREDUCE_SEQ_FADD\0" | |
| /* 4769 */ "G_STRICT_FADD\0" | |
| /* 4783 */ "G_ATOMICRMW_FADD\0" | |
| /* 4800 */ "FMADD\0" | |
| /* 4806 */ "FNMADD\0" | |
| /* 4813 */ "EFSADD\0" | |
| /* 4820 */ "EVFSADD\0" | |
| /* 4828 */ "G_VECREDUCE_ADD\0" | |
| /* 4844 */ "G_ADD\0" | |
| /* 4850 */ "G_PTR_ADD\0" | |
| /* 4860 */ "G_ATOMICRMW_ADD\0" | |
| /* 4876 */ "EVLDD\0" | |
| /* 4882 */ "MTVSRDD\0" | |
| /* 4890 */ "EVSTDD\0" | |
| /* 4897 */ "VCFUGED\0" | |
| /* 4905 */ "EFSCFD\0" | |
| /* 4912 */ "PLFD\0" | |
| /* 4917 */ "PSTFD\0" | |
| /* 4923 */ "FNEGD\0" | |
| /* 4929 */ "VNEGD\0" | |
| /* 4935 */ "MADDHD\0" | |
| /* 4942 */ "MULHD\0" | |
| /* 4948 */ "FCFID\0" | |
| /* 4954 */ "HRFID\0" | |
| /* 4960 */ "EFDCFSID\0" | |
| /* 4969 */ "FCTID\0" | |
| /* 4975 */ "EFDCFUID\0" | |
| /* 4984 */ "TLBLD\0" | |
| /* 4990 */ "MADDLD\0" | |
| /* 4997 */ "FSELD\0" | |
| /* 5003 */ "VMULLD\0" | |
| /* 5010 */ "CMPLD\0" | |
| /* 5016 */ "MFVSRLD\0" | |
| /* 5024 */ "VRLD\0" | |
| /* 5029 */ "VSLD\0" | |
| /* 5034 */ "SPILLTOVSR_LD\0" | |
| /* 5048 */ "FRIMD\0" | |
| /* 5054 */ "VBPERMD\0" | |
| /* 5062 */ "VPMSUMD\0" | |
| /* 5070 */ "XXLAND\0" | |
| /* 5077 */ "XXLNAND\0" | |
| /* 5085 */ "CRNAND\0" | |
| /* 5092 */ "EVNAND\0" | |
| /* 5099 */ "G_ATOMICRMW_NAND\0" | |
| /* 5116 */ "CRAND\0" | |
| /* 5122 */ "EVAND\0" | |
| /* 5128 */ "G_VECREDUCE_AND\0" | |
| /* 5144 */ "G_AND\0" | |
| /* 5150 */ "G_ATOMICRMW_AND\0" | |
| /* 5166 */ "TEND\0" | |
| /* 5171 */ "LIFETIME_END\0" | |
| /* 5184 */ "FCPSGND\0" | |
| /* 5192 */ "FRIND\0" | |
| /* 5198 */ "G_BRCOND\0" | |
| /* 5207 */ "SETRND\0" | |
| /* 5214 */ "G_LLROUND\0" | |
| /* 5224 */ "G_LROUND\0" | |
| /* 5233 */ "G_INTRINSIC_ROUND\0" | |
| /* 5251 */ "G_INTRINSIC_FPTRUNC_ROUND\0" | |
| /* 5277 */ "FCMPOD\0" | |
| /* 5284 */ "VPDEPD\0" | |
| /* 5291 */ "FRIPD\0" | |
| /* 5297 */ "CMPD\0" | |
| /* 5302 */ "LOAD_STACK_GUARD\0" | |
| /* 5319 */ "XXBRD\0" | |
| /* 5325 */ "BUILD_QUADWORD\0" | |
| /* 5340 */ "RESTORE_QUADWORD\0" | |
| /* 5357 */ "SPILL_QUADWORD\0" | |
| /* 5372 */ "SPLIT_QUADWORD\0" | |
| /* 5387 */ "MTMSRD\0" | |
| /* 5394 */ "MFVSRD\0" | |
| /* 5401 */ "MTVSRD\0" | |
| /* 5408 */ "MFVRD\0" | |
| /* 5414 */ "MTVRD\0" | |
| /* 5420 */ "FABSD\0" | |
| /* 5426 */ "FNABSD\0" | |
| /* 5433 */ "VMODSD\0" | |
| /* 5440 */ "VMULESD\0" | |
| /* 5448 */ "VDIVESD\0" | |
| /* 5456 */ "VMULHSD\0" | |
| /* 5464 */ "VMINSD\0" | |
| /* 5471 */ "VINSD\0" | |
| /* 5477 */ "VMULOSD\0" | |
| /* 5485 */ "VCMPGTSD\0" | |
| /* 5494 */ "VDIVSD\0" | |
| /* 5501 */ "VMAXSD\0" | |
| /* 5508 */ "PLXSD\0" | |
| /* 5514 */ "PSTXSD\0" | |
| /* 5521 */ "VEXTRACTD\0" | |
| /* 5531 */ "VPOPCNTD\0" | |
| /* 5540 */ "VINSERTD\0" | |
| /* 5549 */ "PSTD\0" | |
| /* 5554 */ "VPEXTD\0" | |
| /* 5561 */ "VMSUMCUD\0" | |
| /* 5570 */ "VMODUD\0" | |
| /* 5577 */ "VMULEUD\0" | |
| /* 5585 */ "VDIVEUD\0" | |
| /* 5593 */ "VMULHUD\0" | |
| /* 5601 */ "VMINUD\0" | |
| /* 5608 */ "VMULOUD\0" | |
| /* 5616 */ "FCMPUD\0" | |
| /* 5623 */ "VCMPEQUD\0" | |
| /* 5632 */ "VCMPGTUD\0" | |
| /* 5641 */ "VDIVUD\0" | |
| /* 5648 */ "VMAXUD\0" | |
| /* 5655 */ "XXBLENDVD\0" | |
| /* 5665 */ "DIVD\0" | |
| /* 5670 */ "FRIZD\0" | |
| /* 5676 */ "VCLZD\0" | |
| /* 5682 */ "CNTLZD\0" | |
| /* 5689 */ "VCTZD\0" | |
| /* 5695 */ "CNTTZD\0" | |
| /* 5702 */ "PSEUDO_PROBE\0" | |
| /* 5715 */ "MFBHRBE\0" | |
| /* 5723 */ "G_SSUBE\0" | |
| /* 5731 */ "G_USUBE\0" | |
| /* 5739 */ "G_FENCE\0" | |
| /* 5747 */ "ARITH_FENCE\0" | |
| /* 5759 */ "REG_SEQUENCE\0" | |
| /* 5772 */ "MFFSCE\0" | |
| /* 5779 */ "G_SADDE\0" | |
| /* 5787 */ "G_UADDE\0" | |
| /* 5795 */ "DIVDE\0" | |
| /* 5801 */ "G_FMINNUM_IEEE\0" | |
| /* 5816 */ "G_FMAXNUM_IEEE\0" | |
| /* 5831 */ "SLBMFEE\0" | |
| /* 5839 */ "WRTEE\0" | |
| /* 5845 */ "SUBFE\0" | |
| /* 5851 */ "EVLWHE\0" | |
| /* 5858 */ "EVSTWHE\0" | |
| /* 5866 */ "SLBIE\0" | |
| /* 5872 */ "TLBIE\0" | |
| /* 5878 */ "G_JUMP_TABLE\0" | |
| /* 5891 */ "BUNDLE\0" | |
| /* 5898 */ "ADDME\0" | |
| /* 5904 */ "SUBFME\0" | |
| /* 5911 */ "G_MEMCPY_INLINE\0" | |
| /* 5927 */ "LOCAL_ESCAPE\0" | |
| /* 5940 */ "SELECT_CC_SPE\0" | |
| /* 5954 */ "SELECT_SPE\0" | |
| /* 5965 */ "TLBRE\0" | |
| /* 5971 */ "FRE\0" | |
| /* 5975 */ "G_INDEXED_STORE\0" | |
| /* 5991 */ "G_STORE\0" | |
| /* 5999 */ "G_BITREVERSE\0" | |
| /* 6012 */ "SLBMTE\0" | |
| /* 6019 */ "FRSQRTE\0" | |
| /* 6027 */ "DBG_VALUE\0" | |
| /* 6037 */ "G_GLOBAL_VALUE\0" | |
| /* 6052 */ "MFVRSAVE\0" | |
| /* 6061 */ "MTVRSAVE\0" | |
| /* 6070 */ "G_MEMMOVE\0" | |
| /* 6080 */ "TLBWE\0" | |
| /* 6086 */ "DIVWE\0" | |
| /* 6092 */ "EVSTWWE\0" | |
| /* 6100 */ "ADDZE\0" | |
| /* 6106 */ "G_FREEZE\0" | |
| /* 6115 */ "SUBFZE\0" | |
| /* 6122 */ "G_FCANONICALIZE\0" | |
| /* 6138 */ "DCBF\0" | |
| /* 6143 */ "SUBF\0" | |
| /* 6148 */ "G_CTLZ_ZERO_UNDEF\0" | |
| /* 6166 */ "G_CTTZ_ZERO_UNDEF\0" | |
| /* 6184 */ "G_IMPLICIT_DEF\0" | |
| /* 6199 */ "DBG_INSTR_REF\0" | |
| /* 6213 */ "EVMHESMF\0" | |
| /* 6222 */ "EVMWHSMF\0" | |
| /* 6231 */ "EVMHOSMF\0" | |
| /* 6240 */ "EVMWSMF\0" | |
| /* 6248 */ "MCRF\0" | |
| /* 6253 */ "MFOCRF\0" | |
| /* 6260 */ "MTOCRF\0" | |
| /* 6267 */ "MTCRF\0" | |
| /* 6273 */ "EFDCFSF\0" | |
| /* 6281 */ "EFSCFSF\0" | |
| /* 6289 */ "EVFSCFSF\0" | |
| /* 6298 */ "MTFSF\0" | |
| /* 6304 */ "EVMHESSF\0" | |
| /* 6313 */ "EVMWHSSF\0" | |
| /* 6322 */ "EVMHOSSF\0" | |
| /* 6331 */ "EVMWSSF\0" | |
| /* 6339 */ "EFDCTSF\0" | |
| /* 6347 */ "EFSCTSF\0" | |
| /* 6355 */ "EVFSCTSF\0" | |
| /* 6364 */ "EFDCFUF\0" | |
| /* 6372 */ "EFSCFUF\0" | |
| /* 6380 */ "EVFSCFUF\0" | |
| /* 6389 */ "EFDCTUF\0" | |
| /* 6397 */ "EFSCTUF\0" | |
| /* 6405 */ "EVFSCTUF\0" | |
| /* 6414 */ "SLBIEG\0" | |
| /* 6421 */ "EFDNEG\0" | |
| /* 6428 */ "G_FNEG\0" | |
| /* 6435 */ "EFSNEG\0" | |
| /* 6442 */ "EVFSNEG\0" | |
| /* 6450 */ "EVNEG\0" | |
| /* 6456 */ "EXTRACT_SUBREG\0" | |
| /* 6471 */ "INSERT_SUBREG\0" | |
| /* 6485 */ "G_SEXT_INREG\0" | |
| /* 6498 */ "SUBREG_TO_REG\0" | |
| /* 6512 */ "G_ATOMIC_CMPXCHG\0" | |
| /* 6529 */ "G_ATOMICRMW_XCHG\0" | |
| /* 6546 */ "G_FLOG\0" | |
| /* 6553 */ "G_VAARG\0" | |
| /* 6561 */ "PREALLOCATED_ARG\0" | |
| /* 6578 */ "V_SET0H\0" | |
| /* 6586 */ "VSRAH\0" | |
| /* 6592 */ "VCNTMBH\0" | |
| /* 6600 */ "EVLDH\0" | |
| /* 6606 */ "EVSTDH\0" | |
| /* 6613 */ "VCMPNEH\0" | |
| /* 6621 */ "VMRGHH\0" | |
| /* 6628 */ "VMRGLH\0" | |
| /* 6635 */ "VRLH\0" | |
| /* 6640 */ "VSLH\0" | |
| /* 6645 */ "G_SMULH\0" | |
| /* 6653 */ "G_UMULH\0" | |
| /* 6661 */ "VPMSUMH\0" | |
| /* 6669 */ "XXBRH\0" | |
| /* 6675 */ "VSRH\0" | |
| /* 6680 */ "VMULESH\0" | |
| /* 6688 */ "V_SETALLONESH\0" | |
| /* 6702 */ "VAVGSH\0" | |
| /* 6709 */ "VUPKHSH\0" | |
| /* 6717 */ "VSPLTISH\0" | |
| /* 6726 */ "VUPKLSH\0" | |
| /* 6734 */ "VMINSH\0" | |
| /* 6741 */ "VMULOSH\0" | |
| /* 6749 */ "VCMPGTSH\0" | |
| /* 6758 */ "EVEXTSH\0" | |
| /* 6766 */ "VMAXSH\0" | |
| /* 6773 */ "VSPLTH\0" | |
| /* 6780 */ "VPOPCNTH\0" | |
| /* 6789 */ "VINSERTH\0" | |
| /* 6798 */ "PSTH\0" | |
| /* 6803 */ "VABSDUH\0" | |
| /* 6811 */ "VMULEUH\0" | |
| /* 6819 */ "VAVGUH\0" | |
| /* 6826 */ "VMINUH\0" | |
| /* 6833 */ "VMULOUH\0" | |
| /* 6841 */ "VCMPEQUH\0" | |
| /* 6850 */ "VEXTRACTUH\0" | |
| /* 6861 */ "VCMPGTUH\0" | |
| /* 6870 */ "VMAXUH\0" | |
| /* 6877 */ "XXBLENDVH\0" | |
| /* 6887 */ "VCMPNEZH\0" | |
| /* 6896 */ "VCLZH\0" | |
| /* 6902 */ "VCTZH\0" | |
| /* 6908 */ "DCBI\0" | |
| /* 6913 */ "ICBI\0" | |
| /* 6918 */ "VSLDBI\0" | |
| /* 6925 */ "VSRDBI\0" | |
| /* 6932 */ "SUBI\0" | |
| /* 6937 */ "DCCCI\0" | |
| /* 6943 */ "ICCCI\0" | |
| /* 6949 */ "TABORTDCI\0" | |
| /* 6959 */ "RFCI\0" | |
| /* 6964 */ "RFMCI\0" | |
| /* 6970 */ "TABORTWCI\0" | |
| /* 6980 */ "SRADI\0" | |
| /* 6986 */ "PADDI\0" | |
| /* 6992 */ "RFDI\0" | |
| /* 6997 */ "CMPLDI\0" | |
| /* 7004 */ "CLRLSLDI\0" | |
| /* 7013 */ "EXTLDI\0" | |
| /* 7020 */ "XXPERMDI\0" | |
| /* 7029 */ "CMPDI\0" | |
| /* 7035 */ "CLRRDI\0" | |
| /* 7042 */ "INSRDI\0" | |
| /* 7049 */ "ROTRDI\0" | |
| /* 7056 */ "EXTRDI\0" | |
| /* 7063 */ "TDI\0" | |
| /* 7067 */ "WRTEEI\0" | |
| /* 7074 */ "RFI\0" | |
| /* 7078 */ "MTFSFI\0" | |
| /* 7085 */ "EVSPLATFI\0" | |
| /* 7095 */ "EVMERGEHI\0" | |
| /* 7105 */ "EVMERGELOHI\0" | |
| /* 7117 */ "DBG_PHI\0" | |
| /* 7125 */ "DMXXINSTFDMR512_HI\0" | |
| /* 7144 */ "DMXXEXTFDMR512_HI\0" | |
| /* 7162 */ "TLBLI\0" | |
| /* 7168 */ "MULLI\0" | |
| /* 7174 */ "PLI\0" | |
| /* 7178 */ "EXTSWSLI\0" | |
| /* 7187 */ "MTVSRBMI\0" | |
| /* 7196 */ "VRLDMI\0" | |
| /* 7203 */ "RLDIMI\0" | |
| /* 7210 */ "RLWIMI\0" | |
| /* 7217 */ "VRLQMI\0" | |
| /* 7224 */ "EVMHESMI\0" | |
| /* 7233 */ "EVMWHSMI\0" | |
| /* 7242 */ "EVMHOSMI\0" | |
| /* 7251 */ "EVMWSMI\0" | |
| /* 7259 */ "EVMHEUMI\0" | |
| /* 7268 */ "EVMWHUMI\0" | |
| /* 7277 */ "EVMWLUMI\0" | |
| /* 7286 */ "EVMHOUMI\0" | |
| /* 7295 */ "EVMWUMI\0" | |
| /* 7303 */ "VRLWMI\0" | |
| /* 7310 */ "MFFSCRNI\0" | |
| /* 7319 */ "MFFSCDRNI\0" | |
| /* 7329 */ "VSLDOI\0" | |
| /* 7336 */ "XSRDPI\0" | |
| /* 7343 */ "XVRDPI\0" | |
| /* 7350 */ "XSRQPI\0" | |
| /* 7357 */ "XVRSPI\0" | |
| /* 7364 */ "XORI\0" | |
| /* 7369 */ "EFDCFSI\0" | |
| /* 7377 */ "EFSCFSI\0" | |
| /* 7385 */ "EVFSCFSI\0" | |
| /* 7394 */ "G_FPTOSI\0" | |
| /* 7403 */ "EFDCTSI\0" | |
| /* 7411 */ "EFSCTSI\0" | |
| /* 7419 */ "EVFSCTSI\0" | |
| /* 7428 */ "EVSPLATI\0" | |
| /* 7437 */ "LDtocJTI\0" | |
| /* 7446 */ "EFDCFUI\0" | |
| /* 7454 */ "EFSCFUI\0" | |
| /* 7462 */ "EVFSCFUI\0" | |
| /* 7471 */ "G_FPTOUI\0" | |
| /* 7480 */ "EFDCTUI\0" | |
| /* 7488 */ "EFSCTUI\0" | |
| /* 7496 */ "EVFSCTUI\0" | |
| /* 7505 */ "SRAWI\0" | |
| /* 7511 */ "XXSLDWI\0" | |
| /* 7519 */ "CMPLWI\0" | |
| /* 7526 */ "EVRLWI\0" | |
| /* 7533 */ "CLRLSLWI\0" | |
| /* 7542 */ "INSLWI\0" | |
| /* 7549 */ "EVSLWI\0" | |
| /* 7556 */ "EXTLWI\0" | |
| /* 7563 */ "G_FPOWI\0" | |
| /* 7571 */ "CMPWI\0" | |
| /* 7577 */ "CLRRWI\0" | |
| /* 7584 */ "INSRWI\0" | |
| /* 7591 */ "ROTRWI\0" | |
| /* 7598 */ "EXTRWI\0" | |
| /* 7605 */ "LSWI\0" | |
| /* 7610 */ "STSWI\0" | |
| /* 7616 */ "TWI\0" | |
| /* 7620 */ "TCHECK\0" | |
| /* 7627 */ "HASHCHK\0" | |
| /* 7635 */ "G_PTRMASK\0" | |
| /* 7645 */ "XXEVAL\0" | |
| /* 7652 */ "VSTRIBL\0" | |
| /* 7660 */ "gBCL\0" | |
| /* 7665 */ "BCCL\0" | |
| /* 7670 */ "RLDCL\0" | |
| /* 7676 */ "RLDICL\0" | |
| /* 7683 */ "GC_LABEL\0" | |
| /* 7692 */ "DBG_LABEL\0" | |
| /* 7702 */ "EH_LABEL\0" | |
| /* 7711 */ "ANNOTATION_LABEL\0" | |
| /* 7728 */ "TLBIEL\0" | |
| /* 7735 */ "ICALL_BRANCH_FUNNEL\0" | |
| /* 7755 */ "GETtlsldADDRPCREL\0" | |
| /* 7773 */ "GETtlsADDRPCREL\0" | |
| /* 7789 */ "ISEL\0" | |
| /* 7794 */ "EVSEL\0" | |
| /* 7800 */ "XXSEL\0" | |
| /* 7806 */ "DCBFL\0" | |
| /* 7812 */ "VSTRIHL\0" | |
| /* 7820 */ "G_FSHL\0" | |
| /* 7827 */ "G_SHL\0" | |
| /* 7833 */ "G_FCEIL\0" | |
| /* 7841 */ "PATCHABLE_TAIL_CALL\0" | |
| /* 7861 */ "PATCHABLE_TYPED_EVENT_CALL\0" | |
| /* 7888 */ "PATCHABLE_EVENT_CALL\0" | |
| /* 7909 */ "FENTRY_CALL\0" | |
| /* 7921 */ "DSSALL\0" | |
| /* 7928 */ "KILL\0" | |
| /* 7933 */ "LXVPRLL\0" | |
| /* 7941 */ "STXVPRLL\0" | |
| /* 7950 */ "LXVRLL\0" | |
| /* 7957 */ "STXVRLL\0" | |
| /* 7965 */ "LXVLL\0" | |
| /* 7971 */ "STXVLL\0" | |
| /* 7978 */ "BLRL\0" | |
| /* 7983 */ "gBCLRL\0" | |
| /* 7990 */ "BCCLRL\0" | |
| /* 7997 */ "BDZLRL\0" | |
| /* 8004 */ "BDNZLRL\0" | |
| /* 8012 */ "LXVPRL\0" | |
| /* 8019 */ "STXVPRL\0" | |
| /* 8027 */ "BCTRL\0" | |
| /* 8033 */ "gBCCTRL\0" | |
| /* 8041 */ "BCCCTRL\0" | |
| /* 8049 */ "LXVRL\0" | |
| /* 8055 */ "STXVRL\0" | |
| /* 8062 */ "MFFSL\0" | |
| /* 8068 */ "LVSL\0" | |
| /* 8073 */ "G_ROTL\0" | |
| /* 8080 */ "EFDMUL\0" | |
| /* 8087 */ "G_VECREDUCE_FMUL\0" | |
| /* 8104 */ "G_FMUL\0" | |
| /* 8111 */ "G_VECREDUCE_SEQ_FMUL\0" | |
| /* 8132 */ "G_STRICT_FMUL\0" | |
| /* 8146 */ "EFSMUL\0" | |
| /* 8153 */ "EVFSMUL\0" | |
| /* 8161 */ "G_VECREDUCE_MUL\0" | |
| /* 8177 */ "G_MUL\0" | |
| /* 8183 */ "LXVL\0" | |
| /* 8188 */ "STXVL\0" | |
| /* 8194 */ "LBARXL\0" | |
| /* 8201 */ "LDARXL\0" | |
| /* 8208 */ "LHARXL\0" | |
| /* 8215 */ "LQARXL\0" | |
| /* 8222 */ "LWARXL\0" | |
| /* 8229 */ "LVXL\0" | |
| /* 8234 */ "STVXL\0" | |
| /* 8240 */ "DCBZL\0" | |
| /* 8246 */ "BDZL\0" | |
| /* 8251 */ "BDNZL\0" | |
| /* 8257 */ "LDtocL\0" | |
| /* 8264 */ "ADDItocL\0" | |
| /* 8273 */ "LWZtocL\0" | |
| /* 8281 */ "ADDItlsgdL\0" | |
| /* 8292 */ "ADDItlsldL\0" | |
| /* 8303 */ "LDgotTprelL\0" | |
| /* 8315 */ "ADDIdtprelL\0" | |
| /* 8327 */ "VEXPANDBM\0" | |
| /* 8337 */ "VMSUMMBM\0" | |
| /* 8346 */ "MTVSRBM\0" | |
| /* 8354 */ "VEXTRACTBM\0" | |
| /* 8365 */ "VSUBUBM\0" | |
| /* 8373 */ "VADDUBM\0" | |
| /* 8381 */ "VMSUMUBM\0" | |
| /* 8390 */ "XXGENPCVBM\0" | |
| /* 8401 */ "VEXPANDDM\0" | |
| /* 8411 */ "MTVSRDM\0" | |
| /* 8419 */ "VEXTRACTDM\0" | |
| /* 8430 */ "VSUBUDM\0" | |
| /* 8438 */ "VADDUDM\0" | |
| /* 8446 */ "VMSUMUDM\0" | |
| /* 8455 */ "XXGENPCVDM\0" | |
| /* 8466 */ "VCLZDM\0" | |
| /* 8473 */ "CNTLZDM\0" | |
| /* 8481 */ "VCTZDM\0" | |
| /* 8488 */ "CNTTZDM\0" | |
| /* 8496 */ "G_FREM\0" | |
| /* 8503 */ "G_STRICT_FREM\0" | |
| /* 8517 */ "G_SREM\0" | |
| /* 8524 */ "G_UREM\0" | |
| /* 8531 */ "G_SDIVREM\0" | |
| /* 8541 */ "G_UDIVREM\0" | |
| /* 8551 */ "VEXPANDHM\0" | |
| /* 8561 */ "MTVSRHM\0" | |
| /* 8569 */ "VMSUMSHM\0" | |
| /* 8578 */ "VEXTRACTHM\0" | |
| /* 8589 */ "VSUBUHM\0" | |
| /* 8597 */ "VMLADDUHM\0" | |
| /* 8607 */ "VADDUHM\0" | |
| /* 8615 */ "VMSUMUHM\0" | |
| /* 8624 */ "XXGENPCVHM\0" | |
| /* 8635 */ "TRECLAIM\0" | |
| /* 8644 */ "VRFIM\0" | |
| /* 8650 */ "XSRDPIM\0" | |
| /* 8658 */ "XVRDPIM\0" | |
| /* 8666 */ "XVRSPIM\0" | |
| /* 8674 */ "SETFLM\0" | |
| /* 8681 */ "VRLDNM\0" | |
| /* 8688 */ "RLWINM\0" | |
| /* 8695 */ "VRLQNM\0" | |
| /* 8702 */ "VRLWNM\0" | |
| /* 8709 */ "VEXPANDQM\0" | |
| /* 8719 */ "MTVSRQM\0" | |
| /* 8727 */ "VEXTRACTQM\0" | |
| /* 8738 */ "VSUBUQM\0" | |
| /* 8746 */ "VADDUQM\0" | |
| /* 8754 */ "VSUBEUQM\0" | |
| /* 8763 */ "VADDEUQM\0" | |
| /* 8772 */ "VPERM\0" | |
| /* 8778 */ "XXPERM\0" | |
| /* 8785 */ "BLA8_RM\0" | |
| /* 8793 */ "BL8_RM\0" | |
| /* 8800 */ "BCTRL8_RM\0" | |
| /* 8810 */ "BLA_RM\0" | |
| /* 8817 */ "BL8_NOTOC_RM\0" | |
| /* 8830 */ "BL_RM\0" | |
| /* 8836 */ "BCTRL_RM\0" | |
| /* 8845 */ "BLA8_NOP_RM\0" | |
| /* 8857 */ "BL8_NOP_RM\0" | |
| /* 8868 */ "BL_NOP_RM\0" | |
| /* 8878 */ "BCTRL8_LDinto_toc_RM\0" | |
| /* 8899 */ "BCTRL_LWZinto_toc_RM\0" | |
| /* 8920 */ "INLINEASM\0" | |
| /* 8930 */ "VPKUDUM\0" | |
| /* 8938 */ "VPKUHUM\0" | |
| /* 8946 */ "G_FMINIMUM\0" | |
| /* 8957 */ "G_FMAXIMUM\0" | |
| /* 8968 */ "G_FMINNUM\0" | |
| /* 8978 */ "G_FMAXNUM\0" | |
| /* 8988 */ "VPKUWUM\0" | |
| /* 8996 */ "VEXPANDWM\0" | |
| /* 9006 */ "MTVSRWM\0" | |
| /* 9014 */ "VEXTRACTWM\0" | |
| /* 9025 */ "VSUBUWM\0" | |
| /* 9033 */ "VADDUWM\0" | |
| /* 9041 */ "VMULUWM\0" | |
| /* 9049 */ "XXGENPCVWM\0" | |
| /* 9060 */ "EVMHEGSMFAN\0" | |
| /* 9072 */ "EVMHOGSMFAN\0" | |
| /* 9084 */ "EVMWSMFAN\0" | |
| /* 9094 */ "EVMWSSFAN\0" | |
| /* 9104 */ "EVMHEGSMIAN\0" | |
| /* 9116 */ "EVMHOGSMIAN\0" | |
| /* 9128 */ "EVMWSMIAN\0" | |
| /* 9138 */ "EVMHEGUMIAN\0" | |
| /* 9150 */ "EVMHOGUMIAN\0" | |
| /* 9162 */ "EVMWUMIAN\0" | |
| /* 9172 */ "G_INTRINSIC_ROUNDEVEN\0" | |
| /* 9194 */ "G_ASSERT_ALIGN\0" | |
| /* 9209 */ "G_FCOPYSIGN\0" | |
| /* 9221 */ "VRFIN\0" | |
| /* 9227 */ "TBEGIN\0" | |
| /* 9234 */ "G_VECREDUCE_FMIN\0" | |
| /* 9251 */ "G_ATOMICRMW_FMIN\0" | |
| /* 9268 */ "G_VECREDUCE_SMIN\0" | |
| /* 9285 */ "G_SMIN\0" | |
| /* 9292 */ "G_VECREDUCE_UMIN\0" | |
| /* 9309 */ "G_UMIN\0" | |
| /* 9316 */ "G_ATOMICRMW_UMIN\0" | |
| /* 9333 */ "G_ATOMICRMW_MIN\0" | |
| /* 9349 */ "MFSRIN\0" | |
| /* 9356 */ "MTSRIN\0" | |
| /* 9363 */ "G_FSIN\0" | |
| /* 9370 */ "PMXVBF16GER2NN\0" | |
| /* 9385 */ "PMXVF16GER2NN\0" | |
| /* 9399 */ "PMXVF32GERNN\0" | |
| /* 9412 */ "PMXVF64GERNN\0" | |
| /* 9425 */ "PMXVBF16GER2WNN\0" | |
| /* 9441 */ "PMXVF16GER2WNN\0" | |
| /* 9456 */ "PMXVF32GERWNN\0" | |
| /* 9470 */ "PMXVF64GERWNN\0" | |
| /* 9484 */ "CFI_INSTRUCTION\0" | |
| /* 9500 */ "PMXVBF16GER2PN\0" | |
| /* 9515 */ "PMXVF16GER2PN\0" | |
| /* 9529 */ "XSCVSPDPN\0" | |
| /* 9539 */ "PMXVF32GERPN\0" | |
| /* 9552 */ "PMXVF64GERPN\0" | |
| /* 9565 */ "XVCVBF16SPN\0" | |
| /* 9577 */ "XSCVDPSPN\0" | |
| /* 9587 */ "PMXVBF16GER2WPN\0" | |
| /* 9603 */ "PMXVF16GER2WPN\0" | |
| /* 9618 */ "PMXVF32GERWPN\0" | |
| /* 9632 */ "PMXVF64GERWPN\0" | |
| /* 9646 */ "DARN\0" | |
| /* 9651 */ "MFFSCRN\0" | |
| /* 9659 */ "MFFSCDRN\0" | |
| /* 9668 */ "ATTN\0" | |
| /* 9673 */ "ADJCALLSTACKDOWN\0" | |
| /* 9690 */ "ADD4O\0" | |
| /* 9696 */ "ADDC8O\0" | |
| /* 9703 */ "SUBFC8O\0" | |
| /* 9711 */ "ADD8O\0" | |
| /* 9717 */ "ADDE8O\0" | |
| /* 9724 */ "SUBFE8O\0" | |
| /* 9732 */ "ADDME8O\0" | |
| /* 9740 */ "SUBFME8O\0" | |
| /* 9749 */ "ADDZE8O\0" | |
| /* 9757 */ "SUBFZE8O\0" | |
| /* 9766 */ "SUBF8O\0" | |
| /* 9773 */ "NEG8O\0" | |
| /* 9779 */ "G_SSUBO\0" | |
| /* 9787 */ "G_USUBO\0" | |
| /* 9795 */ "ADDCO\0" | |
| /* 9801 */ "SUBFCO\0" | |
| /* 9808 */ "G_SADDO\0" | |
| /* 9816 */ "G_UADDO\0" | |
| /* 9824 */ "MULLDO\0" | |
| /* 9831 */ "LQX_PSEUDO\0" | |
| /* 9842 */ "STQX_PSEUDO\0" | |
| /* 9854 */ "DIVDO\0" | |
| /* 9860 */ "ADDEO\0" | |
| /* 9866 */ "DIVDEO\0" | |
| /* 9873 */ "SUBFEO\0" | |
| /* 9880 */ "ADDMEO\0" | |
| /* 9887 */ "SUBFMEO\0" | |
| /* 9895 */ "DIVWEO\0" | |
| /* 9902 */ "ADDZEO\0" | |
| /* 9909 */ "SUBFZEO\0" | |
| /* 9917 */ "SUBFO\0" | |
| /* 9923 */ "NEGO\0" | |
| /* 9928 */ "EVSTWHO\0" | |
| /* 9936 */ "PseudoEIEIO\0" | |
| /* 9948 */ "EnforceIEIO\0" | |
| /* 9960 */ "EVMERGELO\0" | |
| /* 9970 */ "EVMERGEHILO\0" | |
| /* 9982 */ "VSLO\0" | |
| /* 9987 */ "G_SMULO\0" | |
| /* 9995 */ "G_UMULO\0" | |
| /* 10003 */ "XSCVQPDPO\0" | |
| /* 10013 */ "XSNMSUBQPO\0" | |
| /* 10024 */ "XSMSUBQPO\0" | |
| /* 10034 */ "XSSUBQPO\0" | |
| /* 10043 */ "XSNMADDQPO\0" | |
| /* 10054 */ "XSMADDQPO\0" | |
| /* 10064 */ "XSADDQPO\0" | |
| /* 10073 */ "XSMULQPO\0" | |
| /* 10082 */ "XSSQRTQPO\0" | |
| /* 10092 */ "XSDIVQPO\0" | |
| /* 10101 */ "G_BZERO\0" | |
| /* 10109 */ "VSRO\0" | |
| /* 10114 */ "DIVDUO\0" | |
| /* 10121 */ "DIVDEUO\0" | |
| /* 10129 */ "DIVWEUO\0" | |
| /* 10137 */ "DIVWUO\0" | |
| /* 10144 */ "MULLWO\0" | |
| /* 10151 */ "DIVWO\0" | |
| /* 10157 */ "EVSTWWO\0" | |
| /* 10165 */ "STACKMAP\0" | |
| /* 10174 */ "NAP\0" | |
| /* 10178 */ "TRAP\0" | |
| /* 10183 */ "G_ATOMICRMW_UDEC_WRAP\0" | |
| /* 10205 */ "G_ATOMICRMW_UINC_WRAP\0" | |
| /* 10227 */ "G_BSWAP\0" | |
| /* 10235 */ "XSNMSUBADP\0" | |
| /* 10246 */ "XVNMSUBADP\0" | |
| /* 10257 */ "XSMSUBADP\0" | |
| /* 10267 */ "XVMSUBADP\0" | |
| /* 10277 */ "XSNMADDADP\0" | |
| /* 10288 */ "XVNMADDADP\0" | |
| /* 10299 */ "XSMADDADP\0" | |
| /* 10309 */ "XVMADDADP\0" | |
| /* 10319 */ "XSSUBDP\0" | |
| /* 10327 */ "XVSUBDP\0" | |
| /* 10335 */ "XSTSTDCDP\0" | |
| /* 10345 */ "XVTSTDCDP\0" | |
| /* 10355 */ "XSMINCDP\0" | |
| /* 10364 */ "XSMAXCDP\0" | |
| /* 10373 */ "XSADDDP\0" | |
| /* 10381 */ "XVADDDP\0" | |
| /* 10389 */ "XSCVSXDDP\0" | |
| /* 10399 */ "XVCVSXDDP\0" | |
| /* 10409 */ "XSCVUXDDP\0" | |
| /* 10419 */ "XVCVUXDDP\0" | |
| /* 10429 */ "XSCMPGEDP\0" | |
| /* 10439 */ "XVCMPGEDP\0" | |
| /* 10449 */ "XSREDP\0" | |
| /* 10456 */ "XVREDP\0" | |
| /* 10463 */ "XSRSQRTEDP\0" | |
| /* 10474 */ "XVRSQRTEDP\0" | |
| /* 10485 */ "XSNEGDP\0" | |
| /* 10493 */ "XVNEGDP\0" | |
| /* 10501 */ "XSXSIGDP\0" | |
| /* 10510 */ "XVXSIGDP\0" | |
| /* 10519 */ "XXSPLTIDP\0" | |
| /* 10529 */ "XSMINJDP\0" | |
| /* 10538 */ "XSMAXJDP\0" | |
| /* 10547 */ "XSMULDP\0" | |
| /* 10555 */ "XVMULDP\0" | |
| /* 10563 */ "XSNMSUBMDP\0" | |
| /* 10574 */ "XVNMSUBMDP\0" | |
| /* 10585 */ "XSMSUBMDP\0" | |
| /* 10595 */ "XVMSUBMDP\0" | |
| /* 10605 */ "XSNMADDMDP\0" | |
| /* 10616 */ "XVNMADDMDP\0" | |
| /* 10627 */ "XSMADDMDP\0" | |
| /* 10637 */ "XVMADDMDP\0" | |
| /* 10647 */ "XSCPSGNDP\0" | |
| /* 10657 */ "XVCPSGNDP\0" | |
| /* 10667 */ "XSMINDP\0" | |
| /* 10675 */ "XVMINDP\0" | |
| /* 10683 */ "XSCMPODP\0" | |
| /* 10692 */ "XSCVHPDP\0" | |
| /* 10701 */ "XSCVQPDP\0" | |
| /* 10710 */ "XSCVSPDP\0" | |
| /* 10719 */ "XVCVSPDP\0" | |
| /* 10728 */ "XSIEXPDP\0" | |
| /* 10737 */ "XVIEXPDP\0" | |
| /* 10746 */ "XSCMPEXPDP\0" | |
| /* 10757 */ "XSXEXPDP\0" | |
| /* 10766 */ "XVXEXPDP\0" | |
| /* 10775 */ "XSCMPEQDP\0" | |
| /* 10785 */ "XVCMPEQDP\0" | |
| /* 10795 */ "XSNABSDP\0" | |
| /* 10804 */ "XVNABSDP\0" | |
| /* 10813 */ "XSABSDP\0" | |
| /* 10821 */ "XVABSDP\0" | |
| /* 10829 */ "XSCMPGTDP\0" | |
| /* 10839 */ "XVCMPGTDP\0" | |
| /* 10849 */ "XSSQRTDP\0" | |
| /* 10858 */ "XSTSQRTDP\0" | |
| /* 10868 */ "XVTSQRTDP\0" | |
| /* 10878 */ "XVSQRTDP\0" | |
| /* 10887 */ "XSCMPUDP\0" | |
| /* 10896 */ "XSDIVDP\0" | |
| /* 10904 */ "XSTDIVDP\0" | |
| /* 10913 */ "XVTDIVDP\0" | |
| /* 10922 */ "XVDIVDP\0" | |
| /* 10930 */ "XVCVSXWDP\0" | |
| /* 10940 */ "XVCVUXWDP\0" | |
| /* 10950 */ "XSMAXDP\0" | |
| /* 10958 */ "XVMAXDP\0" | |
| /* 10966 */ "CTRL_DEP\0" | |
| /* 10975 */ "DCBFEP\0" | |
| /* 10982 */ "ICBIEP\0" | |
| /* 10989 */ "DCBZLEP\0" | |
| /* 10997 */ "DCBTEP\0" | |
| /* 11004 */ "DCBSTEP\0" | |
| /* 11012 */ "DCBTSTEP\0" | |
| /* 11021 */ "DCBZEP\0" | |
| /* 11028 */ "VCMPBFP\0" | |
| /* 11036 */ "VNMSUBFP\0" | |
| /* 11045 */ "VSUBFP\0" | |
| /* 11052 */ "VMADDFP\0" | |
| /* 11060 */ "VADDFP\0" | |
| /* 11067 */ "VLOGEFP\0" | |
| /* 11075 */ "VCMPGEFP\0" | |
| /* 11084 */ "VREFP\0" | |
| /* 11090 */ "VEXPTEFP\0" | |
| /* 11099 */ "VRSQRTEFP\0" | |
| /* 11109 */ "VMINFP\0" | |
| /* 11116 */ "G_SITOFP\0" | |
| /* 11125 */ "G_UITOFP\0" | |
| /* 11134 */ "VCMPEQFP\0" | |
| /* 11143 */ "VCMPGTFP\0" | |
| /* 11152 */ "VMAXFP\0" | |
| /* 11159 */ "XSCVDPHP\0" | |
| /* 11168 */ "XVCVSPHP\0" | |
| /* 11177 */ "VRFIP\0" | |
| /* 11183 */ "XSRDPIP\0" | |
| /* 11191 */ "XVRDPIP\0" | |
| /* 11199 */ "XVRSPIP\0" | |
| /* 11207 */ "HASHCHKP\0" | |
| /* 11216 */ "DCBFLP\0" | |
| /* 11223 */ "G_FCMP\0" | |
| /* 11230 */ "G_ICMP\0" | |
| /* 11237 */ "PMXVBF16GER2NP\0" | |
| /* 11252 */ "PMXVF16GER2NP\0" | |
| /* 11266 */ "PMXVF32GERNP\0" | |
| /* 11279 */ "PMXVF64GERNP\0" | |
| /* 11292 */ "PMXVBF16GER2WNP\0" | |
| /* 11308 */ "PMXVF16GER2WNP\0" | |
| /* 11323 */ "PMXVF32GERWNP\0" | |
| /* 11337 */ "PMXVF64GERWNP\0" | |
| /* 11351 */ "BLA8_NOP\0" | |
| /* 11360 */ "BL8_NOP\0" | |
| /* 11368 */ "UNENCODED_NOP\0" | |
| /* 11382 */ "BL_NOP\0" | |
| /* 11389 */ "G_CTPOP\0" | |
| /* 11397 */ "STOP\0" | |
| /* 11402 */ "PATCHABLE_OP\0" | |
| /* 11415 */ "FAULTING_OP\0" | |
| /* 11427 */ "PMXVBF16GER2PP\0" | |
| /* 11442 */ "PMXVF16GER2PP\0" | |
| /* 11456 */ "PMXVI16GER2PP\0" | |
| /* 11470 */ "PMXVI8GER4PP\0" | |
| /* 11483 */ "PMXVI4GER8PP\0" | |
| /* 11496 */ "PMXVF32GERPP\0" | |
| /* 11509 */ "PMXVF64GERPP\0" | |
| /* 11522 */ "PMXVI16GER2SPP\0" | |
| /* 11537 */ "PMXVI8GER4SPP\0" | |
| /* 11551 */ "PMXVI8GER4WSPP\0" | |
| /* 11566 */ "PMXVBF16GER2WPP\0" | |
| /* 11582 */ "PMXVF16GER2WPP\0" | |
| /* 11597 */ "PMXVI16GER2WPP\0" | |
| /* 11612 */ "PMXVI8GER4WPP\0" | |
| /* 11626 */ "PMXVI4GER8WPP\0" | |
| /* 11640 */ "PMXVF32GERWPP\0" | |
| /* 11654 */ "PMXVF64GERWPP\0" | |
| /* 11668 */ "PMXVI16GER2SWPP\0" | |
| /* 11684 */ "XSNMSUBQP\0" | |
| /* 11694 */ "XSMSUBQP\0" | |
| /* 11703 */ "XSSUBQP\0" | |
| /* 11711 */ "XSTSTDCQP\0" | |
| /* 11721 */ "XSMINCQP\0" | |
| /* 11730 */ "XSMAXCQP\0" | |
| /* 11739 */ "XSNMADDQP\0" | |
| /* 11749 */ "XSMADDQP\0" | |
| /* 11758 */ "XSADDQP\0" | |
| /* 11766 */ "XSCVSDQP\0" | |
| /* 11775 */ "XSCVUDQP\0" | |
| /* 11784 */ "XSCMPGEQP\0" | |
| /* 11794 */ "XSNEGQP\0" | |
| /* 11802 */ "XSXSIGQP\0" | |
| /* 11811 */ "XSMULQP\0" | |
| /* 11819 */ "XSCPSGNQP\0" | |
| /* 11829 */ "XSCMPOQP\0" | |
| /* 11838 */ "XSCVDPQP\0" | |
| /* 11847 */ "XSIEXPQP\0" | |
| /* 11856 */ "XSCMPEXPQP\0" | |
| /* 11867 */ "XSXEXPQP\0" | |
| /* 11876 */ "XSCMPEQQP\0" | |
| /* 11886 */ "XSCVSQQP\0" | |
| /* 11895 */ "XSCVUQQP\0" | |
| /* 11904 */ "XSNABSQP\0" | |
| /* 11913 */ "XSABSQP\0" | |
| /* 11921 */ "XSCMPGTQP\0" | |
| /* 11931 */ "XSSQRTQP\0" | |
| /* 11940 */ "XSCMPUQP\0" | |
| /* 11949 */ "XSDIVQP\0" | |
| /* 11957 */ "XSNMSUBASP\0" | |
| /* 11968 */ "XVNMSUBASP\0" | |
| /* 11979 */ "XSMSUBASP\0" | |
| /* 11989 */ "XVMSUBASP\0" | |
| /* 11999 */ "XSNMADDASP\0" | |
| /* 12010 */ "XVNMADDASP\0" | |
| /* 12021 */ "XSMADDASP\0" | |
| /* 12031 */ "XVMADDASP\0" | |
| /* 12041 */ "XSSUBSP\0" | |
| /* 12049 */ "XVSUBSP\0" | |
| /* 12057 */ "XSTSTDCSP\0" | |
| /* 12067 */ "XVTSTDCSP\0" | |
| /* 12077 */ "XSADDSP\0" | |
| /* 12085 */ "XVADDSP\0" | |
| /* 12093 */ "XSCVSXDSP\0" | |
| /* 12103 */ "XVCVSXDSP\0" | |
| /* 12113 */ "XSCVUXDSP\0" | |
| /* 12123 */ "XVCVUXDSP\0" | |
| /* 12133 */ "XVCMPGESP\0" | |
| /* 12143 */ "XSRESP\0" | |
| /* 12150 */ "XVRESP\0" | |
| /* 12157 */ "XSRSQRTESP\0" | |
| /* 12168 */ "XVRSQRTESP\0" | |
| /* 12179 */ "XVNEGSP\0" | |
| /* 12187 */ "XVXSIGSP\0" | |
| /* 12196 */ "XSMULSP\0" | |
| /* 12204 */ "XVMULSP\0" | |
| /* 12212 */ "XSNMSUBMSP\0" | |
| /* 12223 */ "XVNMSUBMSP\0" | |
| /* 12234 */ "XSMSUBMSP\0" | |
| /* 12244 */ "XVMSUBMSP\0" | |
| /* 12254 */ "XSNMADDMSP\0" | |
| /* 12265 */ "XVNMADDMSP\0" | |
| /* 12276 */ "XSMADDMSP\0" | |
| /* 12286 */ "XVMADDMSP\0" | |
| /* 12296 */ "XVCPSGNSP\0" | |
| /* 12306 */ "XVMINSP\0" | |
| /* 12314 */ "XSCVDPSP\0" | |
| /* 12323 */ "XVCVDPSP\0" | |
| /* 12332 */ "XVCVHPSP\0" | |
| /* 12341 */ "XVIEXPSP\0" | |
| /* 12350 */ "XVXEXPSP\0" | |
| /* 12359 */ "XVCMPEQSP\0" | |
| /* 12369 */ "FRSP\0" | |
| /* 12374 */ "XSRSP\0" | |
| /* 12380 */ "XVNABSSP\0" | |
| /* 12389 */ "XVABSSP\0" | |
| /* 12397 */ "PLXSSP\0" | |
| /* 12404 */ "PSTXSSP\0" | |
| /* 12412 */ "XVCMPGTSP\0" | |
| /* 12422 */ "XSSQRTSP\0" | |
| /* 12431 */ "XVTSQRTSP\0" | |
| /* 12441 */ "XVSQRTSP\0" | |
| /* 12450 */ "XSDIVSP\0" | |
| /* 12458 */ "XVTDIVSP\0" | |
| /* 12467 */ "XVDIVSP\0" | |
| /* 12475 */ "XVCVSXWSP\0" | |
| /* 12485 */ "XVCVUXWSP\0" | |
| /* 12495 */ "XVMAXSP\0" | |
| /* 12503 */ "HASHSTP\0" | |
| /* 12511 */ "ADJCALLSTACKUP\0" | |
| /* 12526 */ "PREALLOCATED_SETUP\0" | |
| /* 12545 */ "PLXVP\0" | |
| /* 12551 */ "PSTXVP\0" | |
| /* 12558 */ "G_FEXP\0" | |
| /* 12565 */ "XSRQPXP\0" | |
| /* 12573 */ "VEXTSD2Q\0" | |
| /* 12582 */ "VSRAQ\0" | |
| /* 12588 */ "VPRTYBQ\0" | |
| /* 12596 */ "EFDCMPEQ\0" | |
| /* 12605 */ "EFSCMPEQ\0" | |
| /* 12614 */ "EVFSCMPEQ\0" | |
| /* 12624 */ "EVCMPEQ\0" | |
| /* 12632 */ "EFDTSTEQ\0" | |
| /* 12641 */ "EFSTSTEQ\0" | |
| /* 12650 */ "EVFSTSTEQ\0" | |
| /* 12660 */ "LXVKQ\0" | |
| /* 12666 */ "ICBLQ\0" | |
| /* 12672 */ "VRLQ\0" | |
| /* 12677 */ "VSLQ\0" | |
| /* 12682 */ "VBPERMQ\0" | |
| /* 12690 */ "XXBRQ\0" | |
| /* 12696 */ "VSRQ\0" | |
| /* 12701 */ "VMODSQ\0" | |
| /* 12708 */ "VDIVESQ\0" | |
| /* 12716 */ "VCMPSQ\0" | |
| /* 12723 */ "VCMPGTSQ\0" | |
| /* 12732 */ "VDIVSQ\0" | |
| /* 12739 */ "STQ\0" | |
| /* 12743 */ "VMUL10UQ\0" | |
| /* 12752 */ "VMUL10CUQ\0" | |
| /* 12762 */ "VSUBCUQ\0" | |
| /* 12770 */ "VADDCUQ\0" | |
| /* 12778 */ "VMUL10ECUQ\0" | |
| /* 12789 */ "VSUBECUQ\0" | |
| /* 12798 */ "VADDECUQ\0" | |
| /* 12807 */ "VMODUQ\0" | |
| /* 12814 */ "VMUL10EUQ\0" | |
| /* 12824 */ "VDIVEUQ\0" | |
| /* 12832 */ "VCMPUQ\0" | |
| /* 12839 */ "VCMPEQUQ\0" | |
| /* 12848 */ "VCMPGTUQ\0" | |
| /* 12857 */ "VDIVUQ\0" | |
| /* 12864 */ "MBAR\0" | |
| /* 12869 */ "UpdateGBR\0" | |
| /* 12879 */ "VSTRIBR\0" | |
| /* 12887 */ "G_BR\0" | |
| /* 12892 */ "INLINEASM_BR\0" | |
| /* 12905 */ "SETNBCR\0" | |
| /* 12913 */ "SETBCR\0" | |
| /* 12920 */ "MFDCR\0" | |
| /* 12926 */ "RLDCR\0" | |
| /* 12932 */ "MTDCR\0" | |
| /* 12938 */ "MFCR\0" | |
| /* 12943 */ "RLDICR\0" | |
| /* 12950 */ "MFUDSCR\0" | |
| /* 12958 */ "MTUDSCR\0" | |
| /* 12966 */ "MFVSCR\0" | |
| /* 12973 */ "MTVSCR\0" | |
| /* 12980 */ "RESTORE_CR\0" | |
| /* 12991 */ "SPILL_CR\0" | |
| /* 13000 */ "ADDItlsgdLADDR\0" | |
| /* 13015 */ "ADDItlsldLADDR\0" | |
| /* 13030 */ "G_BLOCK_ADDR\0" | |
| /* 13043 */ "GETtlsldADDR\0" | |
| /* 13056 */ "GETtlsADDR\0" | |
| /* 13067 */ "PMXVF32GER\0" | |
| /* 13078 */ "PMXVF64GER\0" | |
| /* 13089 */ "VNCIPHER\0" | |
| /* 13098 */ "VCIPHER\0" | |
| /* 13106 */ "MEMBARRIER\0" | |
| /* 13117 */ "PATCHABLE_FUNCTION_ENTER\0" | |
| /* 13142 */ "G_READCYCLECOUNTER\0" | |
| /* 13161 */ "G_READ_REGISTER\0" | |
| /* 13177 */ "G_WRITE_REGISTER\0" | |
| /* 13194 */ "VSTRIHR\0" | |
| /* 13202 */ "G_ASHR\0" | |
| /* 13209 */ "G_FSHR\0" | |
| /* 13216 */ "G_LSHR\0" | |
| /* 13223 */ "KILL_PAIR\0" | |
| /* 13233 */ "BLR\0" | |
| /* 13237 */ "gBCLR\0" | |
| /* 13243 */ "BCCLR\0" | |
| /* 13249 */ "MFLR\0" | |
| /* 13254 */ "MTLR\0" | |
| /* 13259 */ "BDZLR\0" | |
| /* 13265 */ "BDNZLR\0" | |
| /* 13272 */ "MovePCtoLR\0" | |
| /* 13283 */ "MoveGOTtoLR\0" | |
| /* 13295 */ "FMR\0" | |
| /* 13299 */ "DMMR\0" | |
| /* 13304 */ "MFPMR\0" | |
| /* 13310 */ "MTPMR\0" | |
| /* 13316 */ "VPERMR\0" | |
| /* 13323 */ "XXPERMR\0" | |
| /* 13331 */ "XXLOR\0" | |
| /* 13337 */ "XXLNOR\0" | |
| /* 13344 */ "CRNOR\0" | |
| /* 13350 */ "EVNOR\0" | |
| /* 13356 */ "G_FFLOOR\0" | |
| /* 13365 */ "CROR\0" | |
| /* 13370 */ "G_BUILD_VECTOR\0" | |
| /* 13385 */ "G_SHUFFLE_VECTOR\0" | |
| /* 13402 */ "EVOR\0" | |
| /* 13407 */ "XXLXOR\0" | |
| /* 13414 */ "DMXOR\0" | |
| /* 13420 */ "VPERMXOR\0" | |
| /* 13429 */ "CRXOR\0" | |
| /* 13435 */ "EVXOR\0" | |
| /* 13441 */ "G_VECREDUCE_XOR\0" | |
| /* 13457 */ "G_XOR\0" | |
| /* 13463 */ "G_ATOMICRMW_XOR\0" | |
| /* 13479 */ "G_VECREDUCE_OR\0" | |
| /* 13494 */ "G_OR\0" | |
| /* 13499 */ "G_ATOMICRMW_OR\0" | |
| /* 13514 */ "MFSPR\0" | |
| /* 13520 */ "MTSPR\0" | |
| /* 13526 */ "MFSR\0" | |
| /* 13531 */ "MFMSR\0" | |
| /* 13537 */ "MTMSR\0" | |
| /* 13543 */ "MTSR\0" | |
| /* 13548 */ "LVSR\0" | |
| /* 13553 */ "TAILBCTR\0" | |
| /* 13562 */ "gBCCTR\0" | |
| /* 13569 */ "BCCCTR\0" | |
| /* 13576 */ "MFCTR\0" | |
| /* 13582 */ "MTCTR\0" | |
| /* 13588 */ "G_ROTR\0" | |
| /* 13595 */ "G_INTTOPTR\0" | |
| /* 13606 */ "PMXVI16GER2S\0" | |
| /* 13619 */ "EFDABS\0" | |
| /* 13626 */ "G_FABS\0" | |
| /* 13633 */ "EFDNABS\0" | |
| /* 13641 */ "EFSNABS\0" | |
| /* 13649 */ "EVFSNABS\0" | |
| /* 13658 */ "EFSABS\0" | |
| /* 13665 */ "EVFSABS\0" | |
| /* 13673 */ "EVABS\0" | |
| /* 13679 */ "G_ABS\0" | |
| /* 13685 */ "VSUM4SBS\0" | |
| /* 13694 */ "VSUBSBS\0" | |
| /* 13702 */ "VADDSBS\0" | |
| /* 13710 */ "VSUM4UBS\0" | |
| /* 13719 */ "VSUBUBS\0" | |
| /* 13727 */ "VADDUBS\0" | |
| /* 13735 */ "FSUBS\0" | |
| /* 13741 */ "FMSUBS\0" | |
| /* 13748 */ "FNMSUBS\0" | |
| /* 13756 */ "FADDS\0" | |
| /* 13762 */ "FMADDS\0" | |
| /* 13769 */ "FNMADDS\0" | |
| /* 13777 */ "FCFIDS\0" | |
| /* 13784 */ "DCBTDS\0" | |
| /* 13791 */ "DCBTSTDS\0" | |
| /* 13800 */ "XSCVDPSXDS\0" | |
| /* 13811 */ "XVCVDPSXDS\0" | |
| /* 13822 */ "XVCVSPSXDS\0" | |
| /* 13833 */ "XSCVDPUXDS\0" | |
| /* 13844 */ "XVCVDPUXDS\0" | |
| /* 13855 */ "XVCVSPUXDS\0" | |
| /* 13866 */ "V_SETALLONES\0" | |
| /* 13879 */ "FRES\0" | |
| /* 13884 */ "FRSQRTES\0" | |
| /* 13893 */ "G_UNMERGE_VALUES\0" | |
| /* 13910 */ "G_MERGE_VALUES\0" | |
| /* 13925 */ "EFDCFS\0" | |
| /* 13932 */ "MFFS\0" | |
| /* 13937 */ "PLFS\0" | |
| /* 13942 */ "MCRFS\0" | |
| /* 13948 */ "PSTFS\0" | |
| /* 13954 */ "FNEGS\0" | |
| /* 13960 */ "VSUM4SHS\0" | |
| /* 13969 */ "VSUBSHS\0" | |
| /* 13977 */ "VMHADDSHS\0" | |
| /* 13987 */ "VMHRADDSHS\0" | |
| /* 13998 */ "VADDSHS\0" | |
| /* 14006 */ "VMSUMSHS\0" | |
| /* 14015 */ "VSUBUHS\0" | |
| /* 14023 */ "VADDUHS\0" | |
| /* 14031 */ "VMSUMUHS\0" | |
| /* 14040 */ "SUBIS\0" | |
| /* 14046 */ "SUBPCIS\0" | |
| /* 14054 */ "ADDPCIS\0" | |
| /* 14062 */ "ADDIS\0" | |
| /* 14068 */ "LIS\0" | |
| /* 14072 */ "XORIS\0" | |
| /* 14078 */ "EVSRWIS\0" | |
| /* 14086 */ "FSELS\0" | |
| /* 14092 */ "ADD4TLS\0" | |
| /* 14100 */ "ADD8TLS\0" | |
| /* 14108 */ "ICBTLS\0" | |
| /* 14115 */ "STBXTLS\0" | |
| /* 14123 */ "LDXTLS\0" | |
| /* 14130 */ "STDXTLS\0" | |
| /* 14138 */ "STHXTLS\0" | |
| /* 14146 */ "STWXTLS\0" | |
| /* 14154 */ "LBZXTLS\0" | |
| /* 14162 */ "LHZXTLS\0" | |
| /* 14170 */ "LWZXTLS\0" | |
| /* 14178 */ "BL8_TLS\0" | |
| /* 14186 */ "BL8_NOTOC_TLS\0" | |
| /* 14200 */ "BL_TLS\0" | |
| /* 14207 */ "BL8_NOP_TLS\0" | |
| /* 14219 */ "FMULS\0" | |
| /* 14225 */ "FRIMS\0" | |
| /* 14231 */ "FCPSGNS\0" | |
| /* 14239 */ "FRINS\0" | |
| /* 14245 */ "G_FCOS\0" | |
| /* 14252 */ "EVLWHOS\0" | |
| /* 14260 */ "FCMPOS\0" | |
| /* 14267 */ "DCBFPS\0" | |
| /* 14274 */ "FRIPS\0" | |
| /* 14280 */ "DCBSTPS\0" | |
| /* 14288 */ "G_CONCAT_VECTORS\0" | |
| /* 14305 */ "COPY_TO_REGCLASS\0" | |
| /* 14322 */ "G_IS_FPCLASS\0" | |
| /* 14335 */ "FABSS\0" | |
| /* 14341 */ "FNABSS\0" | |
| /* 14348 */ "VPKSDSS\0" | |
| /* 14356 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0" | |
| /* 14386 */ "VPKSHSS\0" | |
| /* 14394 */ "VPKSWSS\0" | |
| /* 14402 */ "G_INTRINSIC_W_SIDE_EFFECTS\0" | |
| /* 14429 */ "EVCMPGTS\0" | |
| /* 14438 */ "EVCMPLTS\0" | |
| /* 14447 */ "FSQRTS\0" | |
| /* 14454 */ "FCFIDUS\0" | |
| /* 14462 */ "VPKSDUS\0" | |
| /* 14470 */ "VPKUDUS\0" | |
| /* 14478 */ "SUBFUS\0" | |
| /* 14485 */ "VPKSHUS\0" | |
| /* 14493 */ "VPKUHUS\0" | |
| /* 14501 */ "FCMPUS\0" | |
| /* 14508 */ "VPKSWUS\0" | |
| /* 14516 */ "VPKUWUS\0" | |
| /* 14524 */ "FDIVS\0" | |
| /* 14530 */ "EVSRWS\0" | |
| /* 14537 */ "MTVSRWS\0" | |
| /* 14545 */ "VSUM2SWS\0" | |
| /* 14554 */ "VSUBSWS\0" | |
| /* 14562 */ "VADDSWS\0" | |
| /* 14570 */ "VSUMSWS\0" | |
| /* 14578 */ "VSUBUWS\0" | |
| /* 14586 */ "VADDUWS\0" | |
| /* 14594 */ "EVDIVWS\0" | |
| /* 14602 */ "XSCVDPSXWS\0" | |
| /* 14613 */ "XVCVDPSXWS\0" | |
| /* 14624 */ "XVCVSPSXWS\0" | |
| /* 14635 */ "XSCVDPUXWS\0" | |
| /* 14646 */ "XVCVDPUXWS\0" | |
| /* 14657 */ "XVCVSPUXWS\0" | |
| /* 14668 */ "VCTSXS\0" | |
| /* 14675 */ "VCTUXS\0" | |
| /* 14682 */ "FRIZS\0" | |
| /* 14688 */ "LDAT\0" | |
| /* 14693 */ "STDAT\0" | |
| /* 14699 */ "EVLHHESPLAT\0" | |
| /* 14711 */ "EVLWHSPLAT\0" | |
| /* 14722 */ "EVLHHOSSPLAT\0" | |
| /* 14735 */ "EVLHHOUSPLAT\0" | |
| /* 14748 */ "EVLWWSPLAT\0" | |
| /* 14759 */ "G_SSUBSAT\0" | |
| /* 14769 */ "G_USUBSAT\0" | |
| /* 14779 */ "G_SADDSAT\0" | |
| /* 14789 */ "G_UADDSAT\0" | |
| /* 14799 */ "G_SSHLSAT\0" | |
| /* 14809 */ "G_USHLSAT\0" | |
| /* 14819 */ "G_SMULFIXSAT\0" | |
| /* 14832 */ "G_UMULFIXSAT\0" | |
| /* 14845 */ "G_SDIVFIXSAT\0" | |
| /* 14858 */ "G_UDIVFIXSAT\0" | |
| /* 14871 */ "LWAT\0" | |
| /* 14876 */ "STWAT\0" | |
| /* 14882 */ "DCBT\0" | |
| /* 14887 */ "ICBT\0" | |
| /* 14892 */ "G_EXTRACT\0" | |
| /* 14902 */ "G_SELECT\0" | |
| /* 14911 */ "G_BRINDIRECT\0" | |
| /* 14924 */ "DCBTCT\0" | |
| /* 14931 */ "DCBTSTCT\0" | |
| /* 14940 */ "PATCHABLE_RET\0" | |
| /* 14954 */ "TCHECK_RET\0" | |
| /* 14965 */ "TBEGIN_RET\0" | |
| /* 14976 */ "CR6SET\0" | |
| /* 14983 */ "DYNAREAOFFSET\0" | |
| /* 14997 */ "G_MEMSET\0" | |
| /* 15006 */ "CR6UNSET\0" | |
| /* 15015 */ "CRUNSET\0" | |
| /* 15023 */ "CRSET\0" | |
| /* 15029 */ "EFDCMPGT\0" | |
| /* 15038 */ "EFSCMPGT\0" | |
| /* 15047 */ "EVFSCMPGT\0" | |
| /* 15057 */ "EFDTSTGT\0" | |
| /* 15066 */ "EFSTSTGT\0" | |
| /* 15075 */ "EVFSTSTGT\0" | |
| /* 15085 */ "WAIT\0" | |
| /* 15090 */ "RESTORE_CRBIT\0" | |
| /* 15104 */ "SPILL_CRBIT\0" | |
| /* 15116 */ "ANDI_rec_1_EQ_BIT\0" | |
| /* 15134 */ "ANDI_rec_1_GT_BIT\0" | |
| /* 15152 */ "PATCHABLE_FUNCTION_EXIT\0" | |
| /* 15176 */ "G_BRJT\0" | |
| /* 15183 */ "G_EXTRACT_VECTOR_ELT\0" | |
| /* 15204 */ "G_INSERT_VECTOR_ELT\0" | |
| /* 15224 */ "EFDCMPLT\0" | |
| /* 15233 */ "EFSCMPLT\0" | |
| /* 15242 */ "EVFSCMPLT\0" | |
| /* 15252 */ "EFDTSTLT\0" | |
| /* 15261 */ "EFSTSTLT\0" | |
| /* 15270 */ "EVFSTSTLT\0" | |
| /* 15280 */ "G_FCONSTANT\0" | |
| /* 15292 */ "G_CONSTANT\0" | |
| /* 15303 */ "STATEPOINT\0" | |
| /* 15314 */ "PATCHPOINT\0" | |
| /* 15325 */ "G_PTRTOINT\0" | |
| /* 15336 */ "G_FRINT\0" | |
| /* 15344 */ "G_INTRINSIC_LRINT\0" | |
| /* 15362 */ "G_FNEARBYINT\0" | |
| /* 15375 */ "PPC32GOT\0" | |
| /* 15384 */ "PPC32PICGOT\0" | |
| /* 15396 */ "CRNOT\0" | |
| /* 15402 */ "LDtocCPT\0" | |
| /* 15411 */ "TRECHKPT\0" | |
| /* 15420 */ "G_VASTART\0" | |
| /* 15430 */ "LIFETIME_START\0" | |
| /* 15445 */ "G_INVOKE_REGION_START\0" | |
| /* 15467 */ "G_INSERT\0" | |
| /* 15476 */ "TABORT\0" | |
| /* 15483 */ "CP_ABORT\0" | |
| /* 15492 */ "G_FSQRT\0" | |
| /* 15500 */ "G_STRICT_FSQRT\0" | |
| /* 15515 */ "FTSQRT\0" | |
| /* 15522 */ "G_BITCAST\0" | |
| /* 15532 */ "G_ADDRSPACE_CAST\0" | |
| /* 15549 */ "VNCIPHERLAST\0" | |
| /* 15562 */ "VCIPHERLAST\0" | |
| /* 15574 */ "DCBST\0" | |
| /* 15580 */ "DST\0" | |
| /* 15584 */ "HASHST\0" | |
| /* 15591 */ "DBG_VALUE_LIST\0" | |
| /* 15606 */ "DCBTST\0" | |
| /* 15613 */ "DSTST\0" | |
| /* 15619 */ "SPILLTOVSR_ST\0" | |
| /* 15633 */ "DCBTT\0" | |
| /* 15639 */ "DSTT\0" | |
| /* 15644 */ "DCBTSTT\0" | |
| /* 15652 */ "DSTSTT\0" | |
| /* 15659 */ "G_FPEXT\0" | |
| /* 15667 */ "G_SEXT\0" | |
| /* 15674 */ "G_ASSERT_SEXT\0" | |
| /* 15688 */ "G_ANYEXT\0" | |
| /* 15697 */ "G_ZEXT\0" | |
| /* 15704 */ "G_ASSERT_ZEXT\0" | |
| /* 15718 */ "LHAU\0" | |
| /* 15723 */ "STBU\0" | |
| /* 15728 */ "LFDU\0" | |
| /* 15733 */ "STFDU\0" | |
| /* 15739 */ "MADDHDU\0" | |
| /* 15747 */ "MULHDU\0" | |
| /* 15754 */ "FCFIDU\0" | |
| /* 15761 */ "FCTIDU\0" | |
| /* 15768 */ "LDU\0" | |
| /* 15772 */ "STDU\0" | |
| /* 15777 */ "DIVDU\0" | |
| /* 15783 */ "DIVDEU\0" | |
| /* 15790 */ "DIVWEU\0" | |
| /* 15797 */ "STHU\0" | |
| /* 15802 */ "EVSRWIU\0" | |
| /* 15810 */ "EVLWHOU\0" | |
| /* 15818 */ "LFSU\0" | |
| /* 15823 */ "STFSU\0" | |
| /* 15829 */ "EVCMPGTU\0" | |
| /* 15838 */ "EVCMPLTU\0" | |
| /* 15847 */ "MULHWU\0" | |
| /* 15854 */ "FCTIWU\0" | |
| /* 15861 */ "EVSRWU\0" | |
| /* 15868 */ "STWU\0" | |
| /* 15873 */ "EVDIVWU\0" | |
| /* 15881 */ "LBZU\0" | |
| /* 15886 */ "LHZU\0" | |
| /* 15891 */ "LWZU\0" | |
| /* 15896 */ "SLBMFEV\0" | |
| /* 15904 */ "EFDDIV\0" | |
| /* 15911 */ "G_FDIV\0" | |
| /* 15918 */ "G_STRICT_FDIV\0" | |
| /* 15932 */ "EFSDIV\0" | |
| /* 15939 */ "EVFSDIV\0" | |
| /* 15947 */ "G_SDIV\0" | |
| /* 15954 */ "FTDIV\0" | |
| /* 15960 */ "G_UDIV\0" | |
| /* 15967 */ "VSLV\0" | |
| /* 15972 */ "XXLEQV\0" | |
| /* 15979 */ "CREQV\0" | |
| /* 15985 */ "EVEQV\0" | |
| /* 15991 */ "VSRV\0" | |
| /* 15996 */ "PLXV\0" | |
| /* 16001 */ "PSTXV\0" | |
| /* 16007 */ "VEXTSB2W\0" | |
| /* 16016 */ "VEXTSH2W\0" | |
| /* 16025 */ "PMXVBF16GER2W\0" | |
| /* 16039 */ "PMXVF16GER2W\0" | |
| /* 16052 */ "PMXVI16GER2W\0" | |
| /* 16065 */ "PMXVI8GER4W\0" | |
| /* 16077 */ "PMXVI4GER8W\0" | |
| /* 16089 */ "EVMHESMFAAW\0" | |
| /* 16101 */ "EVMHOSMFAAW\0" | |
| /* 16113 */ "EVMHESSFAAW\0" | |
| /* 16125 */ "EVMHOSSFAAW\0" | |
| /* 16137 */ "EVADDSMIAAW\0" | |
| /* 16149 */ "EVMHESMIAAW\0" | |
| /* 16161 */ "EVSUBFSMIAAW\0" | |
| /* 16174 */ "EVMWLSMIAAW\0" | |
| /* 16186 */ "EVMHOSMIAAW\0" | |
| /* 16198 */ "EVADDUMIAAW\0" | |
| /* 16210 */ "EVMHEUMIAAW\0" | |
| /* 16222 */ "EVSUBFUMIAAW\0" | |
| /* 16235 */ "EVMWLUMIAAW\0" | |
| /* 16247 */ "EVMHOUMIAAW\0" | |
| /* 16259 */ "EVADDSSIAAW\0" | |
| /* 16271 */ "EVMHESSIAAW\0" | |
| /* 16283 */ "EVSUBFSSIAAW\0" | |
| /* 16296 */ "EVMWLSSIAAW\0" | |
| /* 16308 */ "EVMHOSSIAAW\0" | |
| /* 16320 */ "EVADDUSIAAW\0" | |
| /* 16332 */ "EVMHEUSIAAW\0" | |
| /* 16344 */ "EVSUBFUSIAAW\0" | |
| /* 16357 */ "EVMWLUSIAAW\0" | |
| /* 16369 */ "EVMHOUSIAAW\0" | |
| /* 16381 */ "VSHASIGMAW\0" | |
| /* 16392 */ "VSRAW\0" | |
| /* 16398 */ "VCNTMBW\0" | |
| /* 16406 */ "VPRTYBW\0" | |
| /* 16414 */ "XXMFACCW\0" | |
| /* 16423 */ "XXMTACCW\0" | |
| /* 16432 */ "EVADDW\0" | |
| /* 16439 */ "EVLDW\0" | |
| /* 16445 */ "EVRNDW\0" | |
| /* 16452 */ "EVSTDW\0" | |
| /* 16459 */ "VMRGEW\0" | |
| /* 16466 */ "VCMPNEW\0" | |
| /* 16474 */ "EVSUBFW\0" | |
| /* 16482 */ "EVSUBIFW\0" | |
| /* 16491 */ "VNEGW\0" | |
| /* 16497 */ "VMRGHW\0" | |
| /* 16504 */ "XXMRGHW\0" | |
| /* 16512 */ "MULHW\0" | |
| /* 16518 */ "EVADDIW\0" | |
| /* 16526 */ "FCTIW\0" | |
| /* 16532 */ "XXSPLTIW\0" | |
| /* 16541 */ "VMRGLW\0" | |
| /* 16548 */ "XXMRGLW\0" | |
| /* 16556 */ "MULLW\0" | |
| /* 16562 */ "CMPLW\0" | |
| /* 16568 */ "EVRLW\0" | |
| /* 16574 */ "EVSLW\0" | |
| /* 16580 */ "LMW\0" | |
| /* 16584 */ "STMW\0" | |
| /* 16589 */ "VPMSUMW\0" | |
| /* 16597 */ "EVMHESMFANW\0" | |
| /* 16609 */ "EVMHOSMFANW\0" | |
| /* 16621 */ "EVMHESSFANW\0" | |
| /* 16633 */ "EVMHOSSFANW\0" | |
| /* 16645 */ "EVMHESMIANW\0" | |
| /* 16657 */ "EVMWLSMIANW\0" | |
| /* 16669 */ "EVMHOSMIANW\0" | |
| /* 16681 */ "EVMHEUMIANW\0" | |
| /* 16693 */ "EVMWLUMIANW\0" | |
| /* 16705 */ "EVMHOUMIANW\0" | |
| /* 16717 */ "EVMHESSIANW\0" | |
| /* 16729 */ "EVMWLSSIANW\0" | |
| /* 16741 */ "EVMHOSSIANW\0" | |
| /* 16753 */ "EVMHEUSIANW\0" | |
| /* 16765 */ "EVMWLUSIANW\0" | |
| /* 16777 */ "EVMHOUSIANW\0" | |
| /* 16789 */ "VMRGOW\0" | |
| /* 16796 */ "G_FPOW\0" | |
| /* 16803 */ "CMPW\0" | |
| /* 16808 */ "XXBRW\0" | |
| /* 16814 */ "PMXVF32GERW\0" | |
| /* 16826 */ "PMXVF64GERW\0" | |
| /* 16838 */ "VSRW\0" | |
| /* 16843 */ "PMXVI16GER2SW\0" | |
| /* 16857 */ "VMODSW\0" | |
| /* 16864 */ "VMULESW\0" | |
| /* 16872 */ "VDIVESW\0" | |
| /* 16880 */ "VAVGSW\0" | |
| /* 16887 */ "VUPKHSW\0" | |
| /* 16895 */ "VMULHSW\0" | |
| /* 16903 */ "VSPLTISW\0" | |
| /* 16912 */ "VUPKLSW\0" | |
| /* 16920 */ "EVCNTLSW\0" | |
| /* 16929 */ "VMINSW\0" | |
| /* 16936 */ "VINSW\0" | |
| /* 16942 */ "VMULOSW\0" | |
| /* 16950 */ "VCMPGTSW\0" | |
| /* 16959 */ "EXTSW\0" | |
| /* 16965 */ "VDIVSW\0" | |
| /* 16972 */ "VMAXSW\0" | |
| /* 16979 */ "VSPLTW\0" | |
| /* 16986 */ "XXSPLTW\0" | |
| /* 16994 */ "VPOPCNTW\0" | |
| /* 17003 */ "VINSERTW\0" | |
| /* 17012 */ "XXINSERTW\0" | |
| /* 17022 */ "SPESTW\0" | |
| /* 17029 */ "PSTW\0" | |
| /* 17034 */ "VSUBCUW\0" | |
| /* 17042 */ "VADDCUW\0" | |
| /* 17050 */ "VMODUW\0" | |
| /* 17057 */ "VABSDUW\0" | |
| /* 17065 */ "VMULEUW\0" | |
| /* 17073 */ "VDIVEUW\0" | |
| /* 17081 */ "VAVGUW\0" | |
| /* 17088 */ "VMULHUW\0" | |
| /* 17096 */ "VMINUW\0" | |
| /* 17103 */ "VMULOUW\0" | |
| /* 17111 */ "VCMPEQUW\0" | |
| /* 17120 */ "VEXTRACTUW\0" | |
| /* 17131 */ "XXEXTRACTUW\0" | |
| /* 17143 */ "VCMPGTUW\0" | |
| /* 17152 */ "VDIVUW\0" | |
| /* 17159 */ "VMAXUW\0" | |
| /* 17166 */ "XXBLENDVW\0" | |
| /* 17176 */ "DIVW\0" | |
| /* 17181 */ "XXSETACCZW\0" | |
| /* 17192 */ "VCMPNEZW\0" | |
| /* 17201 */ "VCLZW\0" | |
| /* 17207 */ "EVCNTLZW\0" | |
| /* 17216 */ "VCTZW\0" | |
| /* 17222 */ "CNTTZW\0" | |
| /* 17229 */ "LXVD2X\0" | |
| /* 17236 */ "STXVD2X\0" | |
| /* 17244 */ "LXVW4X\0" | |
| /* 17251 */ "STXVW4X\0" | |
| /* 17259 */ "LXVB16X\0" | |
| /* 17267 */ "STXVB16X\0" | |
| /* 17276 */ "LXVH8X\0" | |
| /* 17283 */ "STXVH8X\0" | |
| /* 17291 */ "LHAX\0" | |
| /* 17296 */ "G_VECREDUCE_FMAX\0" | |
| /* 17313 */ "G_ATOMICRMW_FMAX\0" | |
| /* 17330 */ "G_VECREDUCE_SMAX\0" | |
| /* 17347 */ "G_SMAX\0" | |
| /* 17354 */ "G_VECREDUCE_UMAX\0" | |
| /* 17371 */ "G_UMAX\0" | |
| /* 17378 */ "G_ATOMICRMW_UMAX\0" | |
| /* 17395 */ "G_ATOMICRMW_MAX\0" | |
| /* 17411 */ "TLBIVAX\0" | |
| /* 17419 */ "LFIWAX\0" | |
| /* 17426 */ "LIWAX\0" | |
| /* 17432 */ "LXSIWAX\0" | |
| /* 17440 */ "LWAX\0" | |
| /* 17445 */ "LVEBX\0" | |
| /* 17451 */ "STVEBX\0" | |
| /* 17458 */ "STXSIBX\0" | |
| /* 17466 */ "LXVRBX\0" | |
| /* 17473 */ "STXVRBX\0" | |
| /* 17481 */ "STBX\0" | |
| /* 17486 */ "STBCX\0" | |
| /* 17492 */ "STDCX\0" | |
| /* 17498 */ "STHCX\0" | |
| /* 17504 */ "STQCX\0" | |
| /* 17510 */ "STWCX\0" | |
| /* 17516 */ "XXSPLTI32DX\0" | |
| /* 17528 */ "EVLDDX\0" | |
| /* 17535 */ "EVSTDDX\0" | |
| /* 17543 */ "LFDX\0" | |
| /* 17548 */ "STFDX\0" | |
| /* 17554 */ "SPILLTOVSR_LDX\0" | |
| /* 17569 */ "LXVRDX\0" | |
| /* 17576 */ "STXVRDX\0" | |
| /* 17584 */ "LXSDX\0" | |
| /* 17590 */ "STXSDX\0" | |
| /* 17597 */ "STDX\0" | |
| /* 17602 */ "ADDEX\0" | |
| /* 17608 */ "G_FRAME_INDEX\0" | |
| /* 17622 */ "EVLWHEX\0" | |
| /* 17630 */ "EVSTWHEX\0" | |
| /* 17639 */ "EVSTWWEX\0" | |
| /* 17648 */ "G_SBFX\0" | |
| /* 17655 */ "G_UBFX\0" | |
| /* 17662 */ "EVLDHX\0" | |
| /* 17669 */ "EVSTDHX\0" | |
| /* 17677 */ "LVEHX\0" | |
| /* 17683 */ "STVEHX\0" | |
| /* 17690 */ "STXSIHX\0" | |
| /* 17698 */ "LXVRHX\0" | |
| /* 17705 */ "STXVRHX\0" | |
| /* 17713 */ "STHX\0" | |
| /* 17718 */ "GETtlsADDR32AIX\0" | |
| /* 17734 */ "GETtlsADDR64AIX\0" | |
| /* 17750 */ "TLSGDAIX\0" | |
| /* 17759 */ "STBCIX\0" | |
| /* 17766 */ "LDCIX\0" | |
| /* 17772 */ "STDCIX\0" | |
| /* 17779 */ "STHCIX\0" | |
| /* 17786 */ "STWCIX\0" | |
| /* 17793 */ "LBZCIX\0" | |
| /* 17800 */ "LHZCIX\0" | |
| /* 17807 */ "LWZCIX\0" | |
| /* 17814 */ "G_SMULFIX\0" | |
| /* 17824 */ "G_UMULFIX\0" | |
| /* 17834 */ "G_SDIVFIX\0" | |
| /* 17844 */ "G_UDIVFIX\0" | |
| /* 17854 */ "XSRQPIX\0" | |
| /* 17862 */ "VINSBLX\0" | |
| /* 17870 */ "VEXTUBLX\0" | |
| /* 17879 */ "VINSDLX\0" | |
| /* 17887 */ "VINSHLX\0" | |
| /* 17895 */ "VEXTUHLX\0" | |
| /* 17904 */ "VINSBVLX\0" | |
| /* 17913 */ "VEXTDUBVLX\0" | |
| /* 17924 */ "VEXTDDVLX\0" | |
| /* 17934 */ "VINSHVLX\0" | |
| /* 17943 */ "VEXTDUHVLX\0" | |
| /* 17954 */ "VINSWVLX\0" | |
| /* 17963 */ "VEXTDUWVLX\0" | |
| /* 17974 */ "VINSWLX\0" | |
| /* 17982 */ "VEXTUWLX\0" | |
| /* 17991 */ "XXPERMX\0" | |
| /* 17999 */ "VSBOX\0" | |
| /* 18005 */ "EVSTWHOX\0" | |
| /* 18014 */ "EVSTWWOX\0" | |
| /* 18023 */ "LBEPX\0" | |
| /* 18029 */ "STBEPX\0" | |
| /* 18036 */ "LFDEPX\0" | |
| /* 18043 */ "STFDEPX\0" | |
| /* 18051 */ "LHEPX\0" | |
| /* 18057 */ "STHEPX\0" | |
| /* 18064 */ "LWEPX\0" | |
| /* 18070 */ "STWEPX\0" | |
| /* 18077 */ "VUPKHPX\0" | |
| /* 18085 */ "VPKPX\0" | |
| /* 18091 */ "VUPKLPX\0" | |
| /* 18099 */ "LXSSPX\0" | |
| /* 18106 */ "STXSSPX\0" | |
| /* 18114 */ "LXVPX\0" | |
| /* 18120 */ "STXVPX\0" | |
| /* 18127 */ "LBARX\0" | |
| /* 18133 */ "LDARX\0" | |
| /* 18139 */ "LHARX\0" | |
| /* 18145 */ "LQARX\0" | |
| /* 18151 */ "LWARX\0" | |
| /* 18157 */ "LDBRX\0" | |
| /* 18163 */ "STDBRX\0" | |
| /* 18170 */ "LHBRX\0" | |
| /* 18176 */ "STHBRX\0" | |
| /* 18183 */ "VINSBRX\0" | |
| /* 18191 */ "VEXTUBRX\0" | |
| /* 18200 */ "LWBRX\0" | |
| /* 18206 */ "STWBRX\0" | |
| /* 18213 */ "VINSDRX\0" | |
| /* 18221 */ "VINSHRX\0" | |
| /* 18229 */ "VEXTUHRX\0" | |
| /* 18238 */ "VINSBVRX\0" | |
| /* 18247 */ "VEXTDUBVRX\0" | |
| /* 18258 */ "VEXTDDVRX\0" | |
| /* 18268 */ "VINSHVRX\0" | |
| /* 18277 */ "VEXTDUHVRX\0" | |
| /* 18288 */ "VINSWVRX\0" | |
| /* 18297 */ "VEXTDUWVRX\0" | |
| /* 18308 */ "VINSWRX\0" | |
| /* 18316 */ "VEXTUWRX\0" | |
| /* 18325 */ "MCRXRX\0" | |
| /* 18332 */ "TLBSX\0" | |
| /* 18338 */ "LXVDSX\0" | |
| /* 18345 */ "VCFSX\0" | |
| /* 18351 */ "LFSX\0" | |
| /* 18356 */ "STFSX\0" | |
| /* 18362 */ "EVLWHOSX\0" | |
| /* 18371 */ "LXVWSX\0" | |
| /* 18378 */ "EVLHHESPLATX\0" | |
| /* 18391 */ "EVLWHSPLATX\0" | |
| /* 18403 */ "EVLHHOSSPLATX\0" | |
| /* 18417 */ "EVLHHOUSPLATX\0" | |
| /* 18431 */ "EVLWWSPLATX\0" | |
| /* 18443 */ "SPILLTOVSR_STX\0" | |
| /* 18458 */ "LHAUX\0" | |
| /* 18464 */ "LWAUX\0" | |
| /* 18470 */ "STBUX\0" | |
| /* 18476 */ "LFDUX\0" | |
| /* 18482 */ "STFDUX\0" | |
| /* 18489 */ "LDUX\0" | |
| /* 18494 */ "STDUX\0" | |
| /* 18500 */ "VCFUX\0" | |
| /* 18506 */ "STHUX\0" | |
| /* 18512 */ "EVLWHOUX\0" | |
| /* 18521 */ "LFSUX\0" | |
| /* 18527 */ "STFSUX\0" | |
| /* 18534 */ "STWUX\0" | |
| /* 18540 */ "LBZUX\0" | |
| /* 18546 */ "LHZUX\0" | |
| /* 18552 */ "LWZUX\0" | |
| /* 18558 */ "LVX\0" | |
| /* 18562 */ "STVX\0" | |
| /* 18567 */ "LXVX\0" | |
| /* 18572 */ "STXVX\0" | |
| /* 18578 */ "EVLDWX\0" | |
| /* 18585 */ "EVSTDWX\0" | |
| /* 18593 */ "LVEWX\0" | |
| /* 18599 */ "STVEWX\0" | |
| /* 18606 */ "STFIWX\0" | |
| /* 18613 */ "STXSIWX\0" | |
| /* 18621 */ "STIWX\0" | |
| /* 18627 */ "LXVRWX\0" | |
| /* 18634 */ "STXVRWX\0" | |
| /* 18642 */ "SPESTWX\0" | |
| /* 18650 */ "LXSIBZX\0" | |
| /* 18658 */ "LBZX\0" | |
| /* 18663 */ "LXSIHZX\0" | |
| /* 18671 */ "LHZX\0" | |
| /* 18676 */ "LFIWZX\0" | |
| /* 18683 */ "LIWZX\0" | |
| /* 18689 */ "LXSIWZX\0" | |
| /* 18697 */ "SPELWZX\0" | |
| /* 18705 */ "G_MEMCPY\0" | |
| /* 18714 */ "CP_COPY\0" | |
| /* 18722 */ "DCBZ\0" | |
| /* 18727 */ "PLBZ\0" | |
| /* 18732 */ "XXSETACCZ\0" | |
| /* 18742 */ "BDZ\0" | |
| /* 18746 */ "EFDCTSIDZ\0" | |
| /* 18756 */ "FCTIDZ\0" | |
| /* 18763 */ "EFDCTUIDZ\0" | |
| /* 18773 */ "XSCVQPSDZ\0" | |
| /* 18783 */ "XSCVQPUDZ\0" | |
| /* 18793 */ "PLHZ\0" | |
| /* 18798 */ "VRFIZ\0" | |
| /* 18804 */ "XSRDPIZ\0" | |
| /* 18812 */ "XVRDPIZ\0" | |
| /* 18820 */ "XVRSPIZ\0" | |
| /* 18828 */ "EFDCTSIZ\0" | |
| /* 18837 */ "EFSCTSIZ\0" | |
| /* 18846 */ "EVFSCTSIZ\0" | |
| /* 18856 */ "EFDCTUIZ\0" | |
| /* 18865 */ "EFSCTUIZ\0" | |
| /* 18874 */ "EVFSCTUIZ\0" | |
| /* 18884 */ "G_CTLZ\0" | |
| /* 18891 */ "BDNZ\0" | |
| /* 18896 */ "XSCVQPSQZ\0" | |
| /* 18906 */ "XSCVQPUQZ\0" | |
| /* 18916 */ "DMSETDMRZ\0" | |
| /* 18926 */ "G_CTTZ\0" | |
| /* 18933 */ "FCTIDUZ\0" | |
| /* 18941 */ "FCTIWUZ\0" | |
| /* 18949 */ "FCTIWZ\0" | |
| /* 18956 */ "SPELWZ\0" | |
| /* 18963 */ "PLWZ\0" | |
| /* 18968 */ "MFVSRWZ\0" | |
| /* 18976 */ "MTVSRWZ\0" | |
| /* 18984 */ "MFVRWZ\0" | |
| /* 18991 */ "MTVRWZ\0" | |
| /* 18998 */ "XSCVQPSWZ\0" | |
| /* 19008 */ "XSCVQPUWZ\0" | |
| /* 19018 */ "ADD8TLS_\0" | |
| /* 19027 */ "STBXTLS_\0" | |
| /* 19036 */ "LDXTLS_\0" | |
| /* 19044 */ "STDXTLS_\0" | |
| /* 19053 */ "STHXTLS_\0" | |
| /* 19062 */ "STWXTLS_\0" | |
| /* 19071 */ "LBZXTLS_\0" | |
| /* 19080 */ "LHZXTLS_\0" | |
| /* 19089 */ "LWZXTLS_\0" | |
| /* 19098 */ "BL8_TLS_\0" | |
| /* 19107 */ "MTFSFb\0" | |
| /* 19114 */ "MTFSFIb\0" | |
| /* 19122 */ "RLDICL_32_rec\0" | |
| /* 19136 */ "EXTSWSLI_32_64_rec\0" | |
| /* 19155 */ "EXTSW_32_64_rec\0" | |
| /* 19171 */ "ADD4_rec\0" | |
| /* 19180 */ "EXTSB8_rec\0" | |
| /* 19191 */ "ADDC8_rec\0" | |
| /* 19201 */ "ANDC8_rec\0" | |
| /* 19211 */ "SUBFC8_rec\0" | |
| /* 19222 */ "ORC8_rec\0" | |
| /* 19231 */ "ADD8_rec\0" | |
| /* 19240 */ "NAND8_rec\0" | |
| /* 19250 */ "ADDE8_rec\0" | |
| /* 19260 */ "SUBFE8_rec\0" | |
| /* 19271 */ "ADDME8_rec\0" | |
| /* 19282 */ "SUBFME8_rec\0" | |
| /* 19294 */ "CP_PASTE8_rec\0" | |
| /* 19308 */ "ADDZE8_rec\0" | |
| /* 19319 */ "SUBFZE8_rec\0" | |
| /* 19331 */ "SUBF8_rec\0" | |
| /* 19341 */ "NEG8_rec\0" | |
| /* 19350 */ "EXTSH8_rec\0" | |
| /* 19361 */ "ANDI8_rec\0" | |
| /* 19371 */ "RLWIMI8_rec\0" | |
| /* 19383 */ "RLWINM8_rec\0" | |
| /* 19395 */ "RLWNM8_rec\0" | |
| /* 19406 */ "NOR8_rec\0" | |
| /* 19415 */ "XOR8_rec\0" | |
| /* 19424 */ "ANDIS8_rec\0" | |
| /* 19435 */ "EQV8_rec\0" | |
| /* 19444 */ "SLW8_rec\0" | |
| /* 19453 */ "SRW8_rec\0" | |
| /* 19462 */ "CNTLZW8_rec\0" | |
| /* 19474 */ "CNTTZW8_rec\0" | |
| /* 19486 */ "VCMPNEB_rec\0" | |
| /* 19498 */ "VCMPGTSB_rec\0" | |
| /* 19511 */ "EXTSB_rec\0" | |
| /* 19521 */ "VCMPEQUB_rec\0" | |
| /* 19534 */ "BCDSUB_rec\0" | |
| /* 19545 */ "FSUB_rec\0" | |
| /* 19554 */ "FMSUB_rec\0" | |
| /* 19564 */ "FNMSUB_rec\0" | |
| /* 19575 */ "VCMPGTUB_rec\0" | |
| /* 19588 */ "VCMPNEZB_rec\0" | |
| /* 19601 */ "ADDC_rec\0" | |
| /* 19610 */ "ANDC_rec\0" | |
| /* 19619 */ "SUBFC_rec\0" | |
| /* 19629 */ "SUBIC_rec\0" | |
| /* 19639 */ "ADDIC_rec\0" | |
| /* 19649 */ "RLDIC_rec\0" | |
| /* 19659 */ "BCDTRUNC_rec\0" | |
| /* 19672 */ "BCDUTRUNC_rec\0" | |
| /* 19686 */ "ORC_rec\0" | |
| /* 19694 */ "SRAD_rec\0" | |
| /* 19703 */ "BCDADD_rec\0" | |
| /* 19714 */ "FADD_rec\0" | |
| /* 19723 */ "FMADD_rec\0" | |
| /* 19733 */ "FNMADD_rec\0" | |
| /* 19744 */ "FNEGD_rec\0" | |
| /* 19754 */ "MULHD_rec\0" | |
| /* 19764 */ "FCFID_rec\0" | |
| /* 19774 */ "FCTID_rec\0" | |
| /* 19784 */ "FSELD_rec\0" | |
| /* 19794 */ "MULLD_rec\0" | |
| /* 19804 */ "SLD_rec\0" | |
| /* 19812 */ "FRIMD_rec\0" | |
| /* 19822 */ "NAND_rec\0" | |
| /* 19831 */ "FCPSGND_rec\0" | |
| /* 19843 */ "FRIND_rec\0" | |
| /* 19853 */ "FRIPD_rec\0" | |
| /* 19863 */ "SRD_rec\0" | |
| /* 19871 */ "FABSD_rec\0" | |
| /* 19881 */ "FNABSD_rec\0" | |
| /* 19892 */ "VCMPGTSD_rec\0" | |
| /* 19905 */ "VCMPEQUD_rec\0" | |
| /* 19918 */ "VCMPGTUD_rec\0" | |
| /* 19931 */ "DIVD_rec\0" | |
| /* 19940 */ "FRIZD_rec\0" | |
| /* 19950 */ "CNTLZD_rec\0" | |
| /* 19961 */ "CNTTZD_rec\0" | |
| /* 19972 */ "ADDE_rec\0" | |
| /* 19981 */ "DIVDE_rec\0" | |
| /* 19991 */ "SLBFEE_rec\0" | |
| /* 20002 */ "SUBFE_rec\0" | |
| /* 20012 */ "ADDME_rec\0" | |
| /* 20022 */ "SUBFME_rec\0" | |
| /* 20033 */ "FRE_rec\0" | |
| /* 20041 */ "FRSQRTE_rec\0" | |
| /* 20053 */ "CP_PASTE_rec\0" | |
| /* 20066 */ "DIVWE_rec\0" | |
| /* 20076 */ "ADDZE_rec\0" | |
| /* 20086 */ "SUBFZE_rec\0" | |
| /* 20097 */ "SUBF_rec\0" | |
| /* 20106 */ "MTFSF_rec\0" | |
| /* 20116 */ "NEG_rec\0" | |
| /* 20124 */ "VCMPNEH_rec\0" | |
| /* 20136 */ "VCMPGTSH_rec\0" | |
| /* 20149 */ "EXTSH_rec\0" | |
| /* 20159 */ "VCMPEQUH_rec\0" | |
| /* 20172 */ "VCMPGTUH_rec\0" | |
| /* 20185 */ "VCMPNEZH_rec\0" | |
| /* 20198 */ "SRADI_rec\0" | |
| /* 20208 */ "CLRLSLDI_rec\0" | |
| /* 20221 */ "EXTLDI_rec\0" | |
| /* 20232 */ "ANDI_rec\0" | |
| /* 20241 */ "CLRRDI_rec\0" | |
| /* 20252 */ "INSRDI_rec\0" | |
| /* 20263 */ "ROTRDI_rec\0" | |
| /* 20274 */ "EXTRDI_rec\0" | |
| /* 20285 */ "MTFSFI_rec\0" | |
| /* 20296 */ "EXTSWSLI_rec\0" | |
| /* 20309 */ "RLDIMI_rec\0" | |
| /* 20320 */ "RLWIMI_rec\0" | |
| /* 20331 */ "SRAWI_rec\0" | |
| /* 20341 */ "CLRLSLWI_rec\0" | |
| /* 20354 */ "INSLWI_rec\0" | |
| /* 20365 */ "EXTLWI_rec\0" | |
| /* 20376 */ "CLRRWI_rec\0" | |
| /* 20387 */ "INSRWI_rec\0" | |
| /* 20398 */ "ROTRWI_rec\0" | |
| /* 20409 */ "EXTRWI_rec\0" | |
| /* 20420 */ "VSTRIBL_rec\0" | |
| /* 20432 */ "RLDCL_rec\0" | |
| /* 20442 */ "RLDICL_rec\0" | |
| /* 20453 */ "VSTRIHL_rec\0" | |
| /* 20465 */ "FMUL_rec\0" | |
| /* 20474 */ "RLWINM_rec\0" | |
| /* 20485 */ "RLWNM_rec\0" | |
| /* 20495 */ "BCDCFN_rec\0" | |
| /* 20506 */ "BCDCPSGN_rec\0" | |
| /* 20519 */ "BCDSETSGN_rec\0" | |
| /* 20533 */ "BCDCTN_rec\0" | |
| /* 20544 */ "ADD4O_rec\0" | |
| /* 20554 */ "ADDC8O_rec\0" | |
| /* 20565 */ "SUBFC8O_rec\0" | |
| /* 20577 */ "ADD8O_rec\0" | |
| /* 20587 */ "ADDE8O_rec\0" | |
| /* 20598 */ "SUBFE8O_rec\0" | |
| /* 20610 */ "ADDME8O_rec\0" | |
| /* 20622 */ "SUBFME8O_rec\0" | |
| /* 20635 */ "ADDZE8O_rec\0" | |
| /* 20647 */ "SUBFZE8O_rec\0" | |
| /* 20660 */ "SUBF8O_rec\0" | |
| /* 20671 */ "NEG8O_rec\0" | |
| /* 20681 */ "ADDCO_rec\0" | |
| /* 20691 */ "SUBFCO_rec\0" | |
| /* 20702 */ "MULLDO_rec\0" | |
| /* 20713 */ "DIVDO_rec\0" | |
| /* 20723 */ "ADDEO_rec\0" | |
| /* 20733 */ "DIVDEO_rec\0" | |
| /* 20744 */ "SUBFEO_rec\0" | |
| /* 20755 */ "ADDMEO_rec\0" | |
| /* 20766 */ "SUBFMEO_rec\0" | |
| /* 20778 */ "DIVWEO_rec\0" | |
| /* 20789 */ "ADDZEO_rec\0" | |
| /* 20800 */ "SUBFZEO_rec\0" | |
| /* 20812 */ "SUBFO_rec\0" | |
| /* 20822 */ "NEGO_rec\0" | |
| /* 20831 */ "DIVDUO_rec\0" | |
| /* 20842 */ "DIVDEUO_rec\0" | |
| /* 20854 */ "DIVWEUO_rec\0" | |
| /* 20866 */ "DIVWUO_rec\0" | |
| /* 20877 */ "MULLWO_rec\0" | |
| /* 20888 */ "DIVWO_rec\0" | |
| /* 20898 */ "XVCMPGEDP_rec\0" | |
| /* 20912 */ "XVCMPEQDP_rec\0" | |
| /* 20926 */ "XVCMPGTDP_rec\0" | |
| /* 20940 */ "VCMPBFP_rec\0" | |
| /* 20952 */ "VCMPGEFP_rec\0" | |
| /* 20965 */ "VCMPEQFP_rec\0" | |
| /* 20978 */ "VCMPGTFP_rec\0" | |
| /* 20991 */ "XVCMPGESP_rec\0" | |
| /* 21005 */ "XVCMPEQSP_rec\0" | |
| /* 21019 */ "FRSP_rec\0" | |
| /* 21028 */ "XVCMPGTSP_rec\0" | |
| /* 21042 */ "BCDCFSQ_rec\0" | |
| /* 21054 */ "BCDCTSQ_rec\0" | |
| /* 21066 */ "VCMPGTSQ_rec\0" | |
| /* 21079 */ "VCMPEQUQ_rec\0" | |
| /* 21092 */ "VCMPGTUQ_rec\0" | |
| /* 21105 */ "VSTRIBR_rec\0" | |
| /* 21117 */ "RLDCR_rec\0" | |
| /* 21127 */ "RLDICR_rec\0" | |
| /* 21138 */ "VSTRIHR_rec\0" | |
| /* 21150 */ "FMR_rec\0" | |
| /* 21158 */ "NOR_rec\0" | |
| /* 21166 */ "XOR_rec\0" | |
| /* 21174 */ "BCDSR_rec\0" | |
| /* 21184 */ "FSUBS_rec\0" | |
| /* 21194 */ "FMSUBS_rec\0" | |
| /* 21205 */ "FNMSUBS_rec\0" | |
| /* 21217 */ "BCDS_rec\0" | |
| /* 21226 */ "FADDS_rec\0" | |
| /* 21236 */ "FMADDS_rec\0" | |
| /* 21247 */ "FNMADDS_rec\0" | |
| /* 21259 */ "FCFIDS_rec\0" | |
| /* 21270 */ "FRES_rec\0" | |
| /* 21279 */ "FRSQRTES_rec\0" | |
| /* 21292 */ "MFFS_rec\0" | |
| /* 21301 */ "FNEGS_rec\0" | |
| /* 21311 */ "ANDIS_rec\0" | |
| /* 21321 */ "FSELS_rec\0" | |
| /* 21331 */ "FMULS_rec\0" | |
| /* 21341 */ "FRIMS_rec\0" | |
| /* 21351 */ "FCPSGNS_rec\0" | |
| /* 21363 */ "FRINS_rec\0" | |
| /* 21373 */ "FRIPS_rec\0" | |
| /* 21383 */ "FABSS_rec\0" | |
| /* 21393 */ "FNABSS_rec\0" | |
| /* 21404 */ "FSQRTS_rec\0" | |
| /* 21415 */ "BCDUS_rec\0" | |
| /* 21425 */ "FCFIDUS_rec\0" | |
| /* 21437 */ "SUBFUS_rec\0" | |
| /* 21448 */ "FDIVS_rec\0" | |
| /* 21458 */ "FRIZS_rec\0" | |
| /* 21468 */ "FSQRT_rec\0" | |
| /* 21478 */ "MULHDU_rec\0" | |
| /* 21489 */ "FCFIDU_rec\0" | |
| /* 21500 */ "FCTIDU_rec\0" | |
| /* 21511 */ "DIVDU_rec\0" | |
| /* 21521 */ "DIVDEU_rec\0" | |
| /* 21532 */ "DIVWEU_rec\0" | |
| /* 21543 */ "MULHWU_rec\0" | |
| /* 21554 */ "FCTIWU_rec\0" | |
| /* 21565 */ "DIVWU_rec\0" | |
| /* 21575 */ "FDIV_rec\0" | |
| /* 21584 */ "EQV_rec\0" | |
| /* 21592 */ "SRAW_rec\0" | |
| /* 21601 */ "VCMPNEW_rec\0" | |
| /* 21613 */ "MULHW_rec\0" | |
| /* 21623 */ "FCTIW_rec\0" | |
| /* 21633 */ "MULLW_rec\0" | |
| /* 21643 */ "SLW_rec\0" | |
| /* 21651 */ "SRW_rec\0" | |
| /* 21659 */ "VCMPGTSW_rec\0" | |
| /* 21672 */ "EXTSW_rec\0" | |
| /* 21682 */ "VCMPEQUW_rec\0" | |
| /* 21695 */ "VCMPGTUW_rec\0" | |
| /* 21708 */ "DIVW_rec\0" | |
| /* 21717 */ "VCMPNEZW_rec\0" | |
| /* 21730 */ "CNTLZW_rec\0" | |
| /* 21741 */ "CNTTZW_rec\0" | |
| /* 21752 */ "FCTIDZ_rec\0" | |
| /* 21763 */ "BCDCFZ_rec\0" | |
| /* 21774 */ "BCDCTZ_rec\0" | |
| /* 21785 */ "FCTIDUZ_rec\0" | |
| /* 21797 */ "FCTIWUZ_rec\0" | |
| /* 21809 */ "FCTIWZ_rec\0" | |
| /* 21820 */ "RLWIMIbm_rec\0" | |
| /* 21833 */ "RLWINMbm_rec\0" | |
| /* 21846 */ "RLWNMbm_rec\0" | |
| /* 21858 */ "LDtoc\0" | |
| /* 21864 */ "ADDItoc\0" | |
| /* 21872 */ "LWZtoc\0" | |
| /* 21879 */ "BCTRL8_LDinto_toc\0" | |
| /* 21897 */ "BCTRL_LWZinto_toc\0" | |
| /* 21915 */ "PLHA8pc\0" | |
| /* 21923 */ "PLWA8pc\0" | |
| /* 21931 */ "PSTB8pc\0" | |
| /* 21939 */ "PSTH8pc\0" | |
| /* 21947 */ "PADDI8pc\0" | |
| /* 21956 */ "PSTW8pc\0" | |
| /* 21964 */ "PLBZ8pc\0" | |
| /* 21972 */ "PLHZ8pc\0" | |
| /* 21980 */ "PLWZ8pc\0" | |
| /* 21988 */ "PLHApc\0" | |
| /* 21995 */ "PLWApc\0" | |
| /* 22002 */ "PSTBpc\0" | |
| /* 22009 */ "PLFDpc\0" | |
| /* 22016 */ "PSTFDpc\0" | |
| /* 22024 */ "PLDpc\0" | |
| /* 22030 */ "PLXSDpc\0" | |
| /* 22038 */ "PSTXSDpc\0" | |
| /* 22047 */ "PSTDpc\0" | |
| /* 22054 */ "PSTHpc\0" | |
| /* 22061 */ "PADDIpc\0" | |
| /* 22069 */ "PLXSSPpc\0" | |
| /* 22078 */ "PSTXSSPpc\0" | |
| /* 22088 */ "PLXVPpc\0" | |
| /* 22096 */ "PSTXVPpc\0" | |
| /* 22105 */ "PLFSpc\0" | |
| /* 22112 */ "PSTFSpc\0" | |
| /* 22120 */ "PLXVpc\0" | |
| /* 22127 */ "PSTXVpc\0" | |
| /* 22135 */ "PSTWpc\0" | |
| /* 22142 */ "PLBZpc\0" | |
| /* 22149 */ "PLHZpc\0" | |
| /* 22156 */ "PLWZpc\0" | |
| /* 22163 */ "XXLORf\0" | |
| /* 22170 */ "SETRNDi\0" | |
| /* 22178 */ "TCRETURNai\0" | |
| /* 22189 */ "TCRETURNdi\0" | |
| /* 22200 */ "TCRETURNri\0" | |
| /* 22211 */ "PADDIdtprel\0" | |
| /* 22223 */ "BDZLAm\0" | |
| /* 22230 */ "BDNZLAm\0" | |
| /* 22238 */ "BDZAm\0" | |
| /* 22244 */ "BDNZAm\0" | |
| /* 22251 */ "BDZLRLm\0" | |
| /* 22259 */ "BDNZLRLm\0" | |
| /* 22268 */ "BDZLm\0" | |
| /* 22274 */ "BDNZLm\0" | |
| /* 22281 */ "BDZLRm\0" | |
| /* 22288 */ "BDNZLRm\0" | |
| /* 22296 */ "BDZm\0" | |
| /* 22301 */ "BDNZm\0" | |
| /* 22307 */ "RLWIMIbm\0" | |
| /* 22316 */ "RLWINMbm\0" | |
| /* 22325 */ "RLWNMbm\0" | |
| /* 22333 */ "BCCTRL8n\0" | |
| /* 22342 */ "BCCTR8n\0" | |
| /* 22350 */ "BCn\0" | |
| /* 22354 */ "BCLn\0" | |
| /* 22359 */ "BCLRLn\0" | |
| /* 22366 */ "BCCTRLn\0" | |
| /* 22374 */ "BCLRn\0" | |
| /* 22380 */ "BCCTRn\0" | |
| /* 22387 */ "BDZLAp\0" | |
| /* 22394 */ "BDNZLAp\0" | |
| /* 22402 */ "BDZAp\0" | |
| /* 22408 */ "BDNZAp\0" | |
| /* 22415 */ "BDZLRLp\0" | |
| /* 22423 */ "BDNZLRLp\0" | |
| /* 22432 */ "BDZLp\0" | |
| /* 22438 */ "BDNZLp\0" | |
| /* 22445 */ "BDZLRp\0" | |
| /* 22452 */ "BDNZLRp\0" | |
| /* 22460 */ "BDZp\0" | |
| /* 22465 */ "BDNZp\0" | |
| /* 22471 */ "MTCTR8loop\0" | |
| /* 22482 */ "DecreaseCTR8loop\0" | |
| /* 22499 */ "MTCTRloop\0" | |
| /* 22509 */ "DecreaseCTRloop\0" | |
| /* 22525 */ "EH_SjLj_Setup\0" | |
| /* 22539 */ "VSPLTBs\0" | |
| /* 22547 */ "VEXTSB2Ds\0" | |
| /* 22557 */ "VEXTSH2Ds\0" | |
| /* 22567 */ "VEXTSW2Ds\0" | |
| /* 22577 */ "VSPLTHs\0" | |
| /* 22585 */ "XXPERMDIs\0" | |
| /* 22595 */ "XXSLDWIs\0" | |
| /* 22604 */ "XSNABSDPs\0" | |
| /* 22614 */ "XSCVDPSXDSs\0" | |
| /* 22626 */ "XSCVDPUXDSs\0" | |
| /* 22638 */ "XSCVDPSXWSs\0" | |
| /* 22650 */ "XSCVDPUXWSs\0" | |
| /* 22662 */ "VEXTSB2Ws\0" | |
| /* 22672 */ "VEXTSH2Ws\0" | |
| /* 22682 */ "XXSPLTWs\0" | |
| /* 22691 */ "XXLEQVOnes\0" | |
| /* 22702 */ "BCLalways\0" | |
| /* 22712 */ "gBCAat\0" | |
| /* 22719 */ "gBCLAat\0" | |
| /* 22727 */ "gBCat\0" | |
| /* 22733 */ "gBCLat\0" | |
| /* 22740 */ "MFVRSAVEv\0" | |
| /* 22750 */ "MTVRSAVEv\0" | |
| /* 22760 */ "STXSIBXv\0" | |
| /* 22769 */ "STXSIHXv\0" | |
| /* 22778 */ "LAx\0" | |
| /* 22782 */ "DCBFx\0" | |
| /* 22788 */ "DCBTx\0" | |
| /* 22794 */ "DCBTSTx\0" | |
| /* 22802 */ "XXLXORz\0" | |
| /* 22810 */ "XXLXORdpz\0" | |
| /* 22820 */ "XXLXORspz\0" | |
| /* 22830 */ "FADDrtz\0" | |
| }; | |
| #ifdef __GNUC__ | |
| #pragma GCC diagnostic pop | |
| #endif | |
| extern const unsigned PPCInstrNameIndices[] = { | |
| 7121U, 8920U, 12892U, 9484U, 7702U, 7683U, 7711U, 7928U, | |
| 6456U, 6471U, 6186U, 6498U, 14305U, 6027U, 15591U, 6199U, | |
| 7117U, 7692U, 5759U, 18717U, 5891U, 15430U, 5171U, 5702U, | |
| 5747U, 10165U, 7909U, 15314U, 5302U, 12526U, 6561U, 15303U, | |
| 5927U, 11415U, 11402U, 13117U, 14940U, 15152U, 7841U, 7888U, | |
| 7861U, 7735U, 13106U, 15674U, 15704U, 9194U, 4844U, 3969U, | |
| 8177U, 15947U, 15960U, 8517U, 8524U, 8531U, 8541U, 5144U, | |
| 13494U, 13457U, 6184U, 7119U, 17608U, 6037U, 14892U, 13893U, | |
| 15467U, 13910U, 13370U, 4318U, 14288U, 15325U, 13595U, 15522U, | |
| 6106U, 5251U, 4292U, 5233U, 15344U, 9172U, 13142U, 4682U, | |
| 4626U, 4656U, 4667U, 4607U, 4637U, 5991U, 5975U, 14356U, | |
| 6512U, 6529U, 4860U, 3975U, 5150U, 5099U, 13499U, 13463U, | |
| 17395U, 9333U, 17378U, 9316U, 4783U, 3924U, 17313U, 9251U, | |
| 10205U, 10183U, 5739U, 5198U, 14911U, 15445U, 4258U, 14402U, | |
| 15688U, 4310U, 15292U, 15280U, 15420U, 6553U, 15667U, 6485U, | |
| 15697U, 7827U, 13216U, 13202U, 7820U, 13209U, 13588U, 8073U, | |
| 11230U, 11223U, 14902U, 9816U, 5787U, 9787U, 5731U, 9808U, | |
| 5779U, 9779U, 5723U, 9995U, 9987U, 6653U, 6645U, 14789U, | |
| 14779U, 14769U, 14759U, 14809U, 14799U, 17814U, 17824U, 14819U, | |
| 14832U, 17834U, 17844U, 14845U, 14858U, 4741U, 3903U, 8104U, | |
| 3494U, 4589U, 15911U, 8496U, 16796U, 7563U, 12558U, 771U, | |
| 6546U, 763U, 0U, 6428U, 15659U, 4282U, 7394U, 7471U, | |
| 11116U, 11125U, 13626U, 9209U, 14322U, 6122U, 8968U, 8978U, | |
| 5801U, 5816U, 8946U, 8957U, 4850U, 7635U, 9285U, 17347U, | |
| 9309U, 17371U, 13679U, 5224U, 5214U, 12887U, 15176U, 15204U, | |
| 15183U, 13385U, 18926U, 6166U, 18884U, 6148U, 11389U, 10227U, | |
| 5999U, 7833U, 14245U, 9363U, 15492U, 13356U, 15336U, 15362U, | |
| 15532U, 13030U, 5878U, 4375U, 4769U, 3910U, 8132U, 15918U, | |
| 8503U, 3500U, 15500U, 13161U, 13177U, 18705U, 5911U, 6070U, | |
| 14997U, 10101U, 4748U, 8111U, 4724U, 8087U, 17296U, 9234U, | |
| 4828U, 8161U, 5128U, 13479U, 13441U, 17330U, 9268U, 17354U, | |
| 9292U, 17648U, 17655U, 1842U, 1761U, 1804U, 1782U, 1884U, | |
| 1740U, 1863U, 1825U, 5325U, 4082U, 2078U, 7004U, 20208U, | |
| 7533U, 20341U, 7035U, 20241U, 7577U, 20376U, 7806U, 11216U, | |
| 14267U, 22782U, 14280U, 14924U, 13784U, 14931U, 13791U, 15644U, | |
| 22794U, 15633U, 22788U, 672U, 1245U, 692U, 1265U, 7013U, | |
| 20221U, 7556U, 20365U, 7056U, 20274U, 7598U, 20409U, 7542U, | |
| 20354U, 7042U, 20252U, 7584U, 20387U, 13223U, 22778U, 17426U, | |
| 18683U, 22307U, 21820U, 22316U, 21833U, 22325U, 21846U, 7049U, | |
| 20263U, 7591U, 20398U, 7008U, 20212U, 7537U, 20345U, 5034U, | |
| 17554U, 15619U, 18443U, 7044U, 20254U, 7586U, 20389U, 18621U, | |
| 6932U, 4209U, 19629U, 14040U, 14046U, 682U, 1255U, 703U, | |
| 1276U, 1322U, 9690U, 20544U, 14092U, 19171U, 2059U, 9711U, | |
| 20577U, 14100U, 19018U, 19231U, 4167U, 2010U, 9696U, 20554U, | |
| 19191U, 9795U, 20681U, 19601U, 5782U, 2086U, 9717U, 20587U, | |
| 19250U, 9860U, 20723U, 17602U, 2880U, 19972U, 6987U, 2205U, | |
| 4215U, 2029U, 19639U, 14062U, 2704U, 3351U, 95U, 3335U, | |
| 3309U, 3322U, 3298U, 1918U, 8315U, 389U, 8281U, 349U, | |
| 13000U, 403U, 8292U, 362U, 13015U, 420U, 21864U, 3028U, | |
| 8264U, 5898U, 2099U, 9732U, 20610U, 19271U, 9880U, 20755U, | |
| 20012U, 14054U, 6100U, 2114U, 9749U, 20635U, 19308U, 9902U, | |
| 20789U, 20076U, 9673U, 12511U, 5073U, 2073U, 19241U, 4175U, | |
| 2016U, 19201U, 19610U, 19361U, 19424U, 21311U, 20232U, 15116U, | |
| 2738U, 15134U, 2757U, 19823U, 1585U, 249U, 961U, 2381U, | |
| 1467U, 131U, 843U, 2269U, 1508U, 172U, 884U, 2308U, | |
| 1665U, 329U, 1041U, 2467U, 1549U, 213U, 925U, 2347U, | |
| 1487U, 151U, 863U, 2288U, 1625U, 289U, 1001U, 2419U, | |
| 1447U, 111U, 823U, 2237U, 1644U, 308U, 1020U, 2447U, | |
| 1528U, 192U, 904U, 2327U, 1605U, 269U, 981U, 2400U, | |
| 1569U, 233U, 945U, 2366U, 9668U, 3556U, 3187U, 4053U, | |
| 4163U, 3210U, 13569U, 2682U, 8041U, 2520U, 7665U, 3475U, | |
| 13243U, 7990U, 13563U, 2675U, 22342U, 8034U, 2512U, 22333U, | |
| 22366U, 22380U, 19703U, 20495U, 21042U, 21763U, 20506U, 20533U, | |
| 21054U, 21774U, 20519U, 21174U, 19534U, 21217U, 19659U, 21415U, | |
| 19672U, 7661U, 13238U, 7984U, 22359U, 22374U, 22702U, 22354U, | |
| 13557U, 2669U, 8027U, 2505U, 21879U, 8878U, 8800U, 21897U, | |
| 8899U, 8836U, 22350U, 18891U, 3016U, 3544U, 22244U, 22408U, | |
| 8251U, 3487U, 22230U, 22394U, 13265U, 2621U, 8004U, 22259U, | |
| 22423U, 22288U, 22452U, 22274U, 22438U, 22301U, 22465U, 18742U, | |
| 3005U, 3539U, 22238U, 22402U, 8246U, 3481U, 22223U, 22387U, | |
| 13259U, 2614U, 7997U, 22251U, 22415U, 22281U, 22445U, 22268U, | |
| 22432U, 22296U, 22460U, 7657U, 2495U, 11360U, 8857U, 14207U, | |
| 4401U, 8817U, 14186U, 8793U, 14178U, 19098U, 3465U, 1930U, | |
| 11351U, 8845U, 8785U, 8810U, 13233U, 2597U, 7978U, 11382U, | |
| 8868U, 8830U, 14200U, 5055U, 5321U, 6671U, 2186U, 4276U, | |
| 16810U, 2836U, 4898U, 3683U, 3671U, 1948U, 5297U, 7029U, | |
| 3676U, 5010U, 6997U, 16562U, 7519U, 3691U, 1954U, 16803U, | |
| 7571U, 5682U, 8473U, 19950U, 17209U, 2852U, 19462U, 21730U, | |
| 5695U, 8488U, 19961U, 17222U, 2860U, 19474U, 21741U, 15483U, | |
| 18714U, 2990U, 19294U, 20053U, 14976U, 15006U, 5116U, 4180U, | |
| 15979U, 5085U, 13344U, 15396U, 13365U, 4447U, 15023U, 15015U, | |
| 13429U, 10966U, 9646U, 3185U, 6138U, 10975U, 6908U, 15574U, | |
| 11004U, 14882U, 10997U, 15606U, 11012U, 18722U, 11021U, 8240U, | |
| 10989U, 6937U, 5665U, 5795U, 9866U, 20733U, 15783U, 10121U, | |
| 20842U, 21521U, 19981U, 9854U, 20713U, 15777U, 10114U, 20831U, | |
| 21511U, 19931U, 17176U, 6086U, 9895U, 20778U, 15790U, 10129U, | |
| 20854U, 21532U, 20066U, 10151U, 20888U, 15875U, 10137U, 20866U, | |
| 21565U, 21708U, 13299U, 18916U, 13414U, 1701U, 80U, 7144U, | |
| 1685U, 64U, 7125U, 14352U, 7921U, 15580U, 1061U, 15613U, | |
| 1067U, 15652U, 1082U, 15639U, 1075U, 4392U, 2044U, 14983U, | |
| 2723U, 22482U, 22509U, 13619U, 4717U, 13925U, 6273U, 7369U, | |
| 4960U, 6364U, 7446U, 4975U, 12596U, 15029U, 15224U, 6339U, | |
| 7403U, 18746U, 18828U, 6389U, 7480U, 18763U, 18856U, 15904U, | |
| 8080U, 13633U, 6421U, 3896U, 12632U, 15057U, 15252U, 13658U, | |
| 4813U, 4905U, 6281U, 7377U, 6372U, 7454U, 12605U, 15038U, | |
| 15233U, 6347U, 7411U, 18837U, 6397U, 7488U, 18865U, 15932U, | |
| 8146U, 13641U, 6435U, 3954U, 12641U, 15066U, 15261U, 714U, | |
| 1287U, 732U, 1305U, 22525U, 15975U, 2826U, 19435U, 21584U, | |
| 13673U, 16518U, 16137U, 16259U, 16198U, 16320U, 16432U, 5122U, | |
| 4187U, 12624U, 14429U, 15829U, 14438U, 15838U, 16920U, 17207U, | |
| 14594U, 15873U, 15985U, 3787U, 6758U, 13665U, 4820U, 6289U, | |
| 7385U, 6380U, 7462U, 12614U, 15047U, 15242U, 6355U, 7419U, | |
| 18846U, 6405U, 7496U, 18874U, 15939U, 8153U, 13649U, 6442U, | |
| 3961U, 12650U, 15075U, 15270U, 4876U, 17528U, 6600U, 17662U, | |
| 16439U, 18578U, 14699U, 18378U, 14722U, 18403U, 14735U, 18417U, | |
| 5851U, 17622U, 14252U, 18362U, 15810U, 18512U, 14711U, 18391U, | |
| 14748U, 18431U, 7095U, 9970U, 9960U, 7105U, 3073U, 9060U, | |
| 3117U, 9104U, 3151U, 9138U, 6213U, 3215U, 16089U, 16597U, | |
| 7224U, 3377U, 16149U, 16645U, 6304U, 3254U, 16113U, 16621U, | |
| 16271U, 16717U, 7259U, 3416U, 16210U, 16681U, 16332U, 16753U, | |
| 3085U, 9072U, 3129U, 9116U, 3163U, 9150U, 6231U, 3235U, | |
| 16101U, 16609U, 7242U, 3397U, 16186U, 16669U, 6322U, 3274U, | |
| 16125U, 16633U, 16308U, 16741U, 7286U, 3446U, 16247U, 16705U, | |
| 16369U, 16777U, 3513U, 6222U, 3225U, 7233U, 3387U, 6313U, | |
| 3264U, 7268U, 3426U, 16174U, 16657U, 16296U, 16729U, 7277U, | |
| 3436U, 16235U, 16693U, 16357U, 16765U, 6240U, 3245U, 3097U, | |
| 9084U, 7251U, 3407U, 3141U, 9128U, 6331U, 3284U, 3107U, | |
| 9094U, 7295U, 3456U, 3175U, 9162U, 5092U, 6450U, 13350U, | |
| 13402U, 4453U, 16568U, 7526U, 16445U, 7794U, 16574U, 7549U, | |
| 7085U, 7428U, 14078U, 15802U, 14530U, 15861U, 4890U, 17535U, | |
| 6606U, 17669U, 16452U, 18585U, 5858U, 17630U, 9928U, 18005U, | |
| 6092U, 17639U, 10157U, 18014U, 16161U, 16283U, 16222U, 16344U, | |
| 16474U, 16482U, 13435U, 3789U, 1961U, 1091U, 19180U, 19511U, | |
| 6760U, 2191U, 1104U, 19350U, 20149U, 16959U, 7178U, 1117U, | |
| 19136U, 20296U, 655U, 1145U, 19155U, 21672U, 9948U, 5420U, | |
| 19871U, 14335U, 21383U, 4736U, 13756U, 21226U, 19714U, 22830U, | |
| 4948U, 13777U, 21259U, 15754U, 14454U, 21425U, 21489U, 19764U, | |
| 5277U, 14260U, 5616U, 14501U, 5184U, 19831U, 14231U, 21351U, | |
| 4969U, 15761U, 18933U, 21785U, 21500U, 18756U, 21752U, 19774U, | |
| 16526U, 15854U, 18941U, 21797U, 21554U, 18949U, 21809U, 21623U, | |
| 15913U, 14524U, 21448U, 21575U, 4800U, 13762U, 21236U, 19723U, | |
| 13295U, 21150U, 3941U, 13741U, 21194U, 19554U, 8099U, 14219U, | |
| 21331U, 20465U, 5426U, 19881U, 14341U, 21393U, 4923U, 19744U, | |
| 13954U, 21301U, 4806U, 13769U, 21247U, 19733U, 3947U, 13748U, | |
| 21205U, 19564U, 5971U, 13879U, 21270U, 20033U, 5048U, 19812U, | |
| 14225U, 21341U, 5192U, 19843U, 14239U, 21363U, 5291U, 19853U, | |
| 14274U, 21373U, 5670U, 19940U, 14682U, 21458U, 12369U, 21019U, | |
| 6019U, 13884U, 21279U, 20041U, 4997U, 19784U, 14086U, 21321U, | |
| 15494U, 14447U, 21404U, 21468U, 3905U, 13735U, 21184U, 19545U, | |
| 15954U, 15515U, 13056U, 452U, 17718U, 17734U, 7773U, 13043U, | |
| 437U, 7755U, 7627U, 2486U, 11207U, 2544U, 15584U, 2776U, | |
| 12503U, 2554U, 4954U, 6913U, 10982U, 4270U, 12666U, 14887U, | |
| 14108U, 6943U, 7789U, 2499U, 4363U, 3466U, 1931U, 18127U, | |
| 8194U, 18023U, 18728U, 3000U, 17793U, 15881U, 2808U, 18540U, | |
| 2945U, 18658U, 2972U, 14154U, 19071U, 622U, 4987U, 18133U, | |
| 8201U, 14688U, 18157U, 17766U, 15768U, 18489U, 17565U, 14123U, | |
| 19036U, 8303U, 375U, 21858U, 3197U, 15402U, 7437U, 8257U, | |
| 4913U, 18036U, 15728U, 18476U, 17543U, 17419U, 18676U, 13938U, | |
| 15818U, 18521U, 18351U, 3294U, 1913U, 18139U, 8208U, 15718U, | |
| 2784U, 18458U, 2917U, 17291U, 2868U, 18170U, 2903U, 18051U, | |
| 18794U, 3011U, 17800U, 15886U, 2814U, 18546U, 2952U, 18671U, | |
| 2978U, 14162U, 19080U, 633U, 7165U, 2214U, 14068U, 2711U, | |
| 16580U, 12669U, 18145U, 8215U, 9831U, 7605U, 17445U, 17677U, | |
| 18593U, 8068U, 13548U, 18558U, 8229U, 3520U, 18151U, 8222U, | |
| 14871U, 18464U, 17440U, 664U, 490U, 18200U, 2910U, 18064U, | |
| 18959U, 3023U, 17807U, 15891U, 2820U, 18552U, 2959U, 18700U, | |
| 2984U, 14170U, 19089U, 644U, 21872U, 8273U, 5509U, 17584U, | |
| 18650U, 18663U, 17432U, 18689U, 12398U, 18099U, 15997U, 17259U, | |
| 17229U, 18338U, 17276U, 12660U, 8183U, 7965U, 12546U, 8012U, | |
| 7933U, 18114U, 17466U, 17569U, 17698U, 8049U, 7950U, 18627U, | |
| 17244U, 18371U, 18567U, 4935U, 15739U, 4990U, 2064U, 12864U, | |
| 6248U, 13942U, 18325U, 5715U, 12938U, 2580U, 13576U, 2690U, | |
| 12920U, 13932U, 9659U, 7319U, 5772U, 9651U, 7310U, 8062U, | |
| 21292U, 13249U, 2602U, 13531U, 6253U, 2135U, 13304U, 13514U, | |
| 2651U, 13526U, 9349U, 3807U, 1974U, 12950U, 5408U, 6052U, | |
| 22740U, 18984U, 12966U, 5394U, 5016U, 18968U, 5434U, 16858U, | |
| 5571U, 17051U, 4355U, 4369U, 6267U, 2151U, 13582U, 2697U, | |
| 22471U, 22499U, 12932U, 9U, 57U, 6298U, 7078U, 20285U, | |
| 19114U, 20106U, 19107U, 13254U, 2608U, 13537U, 5387U, 6260U, | |
| 2143U, 13310U, 13520U, 2658U, 13543U, 9356U, 12958U, 5414U, | |
| 6061U, 22750U, 3532U, 18991U, 12973U, 8346U, 7187U, 5401U, | |
| 4882U, 8411U, 8561U, 8719U, 3524U, 9006U, 14537U, 18976U, | |
| 4942U, 15747U, 21478U, 19754U, 16512U, 15847U, 21543U, 21613U, | |
| 5004U, 9824U, 20702U, 19794U, 7168U, 2211U, 16556U, 10144U, | |
| 20877U, 21633U, 13283U, 13272U, 2629U, 5080U, 2072U, 19240U, | |
| 19822U, 10174U, 6424U, 2181U, 9773U, 20671U, 19341U, 9923U, | |
| 20822U, 20116U, 11356U, 1716U, 1728U, 13340U, 2641U, 19406U, | |
| 21158U, 13334U, 2642U, 19407U, 4443U, 2054U, 19222U, 19686U, | |
| 7365U, 2232U, 14073U, 2717U, 21159U, 6986U, 2204U, 21947U, | |
| 22211U, 22061U, 5285U, 5555U, 18727U, 2999U, 21964U, 22142U, | |
| 5012U, 22024U, 4912U, 22009U, 13937U, 22105U, 3293U, 1912U, | |
| 21915U, 21988U, 18793U, 3010U, 21972U, 22149U, 7174U, 2218U, | |
| 3519U, 1935U, 21923U, 21995U, 18963U, 3022U, 21980U, 22156U, | |
| 5508U, 22030U, 12397U, 22069U, 15996U, 12545U, 22088U, 22120U, | |
| 779U, 9370U, 11237U, 9500U, 11427U, 16025U, 9425U, 11292U, | |
| 9587U, 11566U, 792U, 9385U, 11252U, 9515U, 11442U, 16039U, | |
| 9441U, 11308U, 9603U, 11582U, 13067U, 9399U, 11266U, 9539U, | |
| 11496U, 16814U, 9456U, 11323U, 9618U, 11640U, 13078U, 9412U, | |
| 11279U, 9552U, 11509U, 16826U, 9470U, 11337U, 9632U, 11654U, | |
| 804U, 11456U, 13606U, 11522U, 16843U, 11668U, 16052U, 11597U, | |
| 2586U, 11483U, 16077U, 11626U, 1400U, 11470U, 11537U, 16065U, | |
| 11612U, 11551U, 3820U, 1980U, 5532U, 16995U, 15375U, 15384U, | |
| 465U, 1157U, 518U, 1203U, 473U, 1165U, 497U, 1182U, | |
| 3837U, 1989U, 21931U, 22002U, 5549U, 22047U, 4917U, 22016U, | |
| 13948U, 22112U, 6798U, 2198U, 21939U, 22054U, 17029U, 2846U, | |
| 21956U, 22135U, 5514U, 22038U, 12404U, 22078U, 16001U, 12551U, | |
| 22096U, 22127U, 9936U, 4141U, 12980U, 15090U, 5340U, 4093U, | |
| 4117U, 6959U, 6992U, 3564U, 7074U, 4955U, 6964U, 7670U, | |
| 20432U, 12926U, 21117U, 4221U, 7676U, 569U, 1132U, 19122U, | |
| 20442U, 12943U, 579U, 21127U, 19649U, 7203U, 20309U, 7210U, | |
| 2223U, 19371U, 20320U, 8688U, 2529U, 19383U, 20474U, 8703U, | |
| 2537U, 19395U, 20485U, 3842U, 4542U, 1422U, 1354U, 2158U, | |
| 1377U, 2256U, 5940U, 1327U, 4459U, 4411U, 4515U, 4486U, | |
| 1436U, 1367U, 2171U, 1390U, 2437U, 5954U, 1342U, 4474U, | |
| 4427U, 4530U, 4502U, 3802U, 1968U, 4056U, 2003U, 12913U, | |
| 2572U, 8674U, 4049U, 1995U, 12905U, 2563U, 5207U, 22170U, | |
| 19991U, 3365U, 5866U, 6414U, 5831U, 15896U, 6012U, 4339U, | |
| 5030U, 19804U, 16576U, 2831U, 19444U, 21643U, 18956U, 18697U, | |
| 17022U, 18642U, 4153U, 12991U, 15104U, 5357U, 4106U, 4130U, | |
| 5372U, 4690U, 6980U, 560U, 20198U, 19694U, 16393U, 7505U, | |
| 20331U, 21592U, 5390U, 19863U, 16839U, 2841U, 19453U, 21651U, | |
| 3838U, 1990U, 17759U, 17486U, 18029U, 15723U, 2790U, 18470U, | |
| 2924U, 17481U, 2874U, 14115U, 19027U, 589U, 5550U, 14693U, | |
| 18163U, 17772U, 17492U, 15772U, 18494U, 17597U, 14130U, 19044U, | |
| 4918U, 18043U, 15733U, 18482U, 17548U, 18606U, 13949U, 15823U, | |
| 18527U, 18356U, 6799U, 2199U, 18176U, 17779U, 17498U, 18057U, | |
| 15797U, 2796U, 18506U, 2931U, 17713U, 2887U, 14138U, 19053U, | |
| 600U, 16584U, 11397U, 12739U, 17504U, 9842U, 7610U, 17451U, | |
| 17683U, 18599U, 18562U, 8234U, 17025U, 2847U, 14876U, 18206U, | |
| 17786U, 17510U, 18070U, 15868U, 2802U, 18534U, 2938U, 18645U, | |
| 2966U, 14146U, 19062U, 611U, 5515U, 17590U, 17458U, 22760U, | |
| 17690U, 22769U, 18613U, 12405U, 18106U, 16002U, 17267U, 17236U, | |
| 17283U, 8188U, 7971U, 12552U, 8019U, 7941U, 18120U, 17473U, | |
| 17576U, 17705U, 8055U, 7957U, 18634U, 17251U, 18572U, 6143U, | |
| 2129U, 9766U, 20660U, 19331U, 4203U, 2022U, 9703U, 20565U, | |
| 19211U, 9801U, 20691U, 19619U, 5845U, 2092U, 9724U, 20598U, | |
| 19260U, 9873U, 20744U, 20002U, 4227U, 2036U, 5904U, 2106U, | |
| 9740U, 20622U, 19282U, 9887U, 20766U, 20022U, 9917U, 20812U, | |
| 14478U, 21437U, 6115U, 2121U, 9757U, 20647U, 19319U, 9909U, | |
| 20800U, 20086U, 20097U, 4342U, 15476U, 4194U, 6949U, 4545U, | |
| 6970U, 3635U, 1941U, 3190U, 1904U, 13553U, 2665U, 9227U, | |
| 14965U, 7620U, 14954U, 22178U, 3037U, 22189U, 3049U, 22200U, | |
| 3061U, 5528U, 7063U, 5166U, 3371U, 5872U, 7728U, 17411U, | |
| 4984U, 7162U, 5965U, 749U, 18332U, 816U, 4581U, 4347U, | |
| 6080U, 756U, 17750U, 2893U, 10178U, 15411U, 8635U, 13544U, | |
| 16983U, 7616U, 11368U, 12869U, 3849U, 6803U, 17057U, 12770U, | |
| 17042U, 12798U, 8763U, 11060U, 13702U, 13998U, 14562U, 8373U, | |
| 13727U, 8438U, 8607U, 14023U, 8746U, 9033U, 14586U, 5123U, | |
| 4188U, 3731U, 6702U, 16880U, 3865U, 6819U, 17081U, 5054U, | |
| 12682U, 18345U, 41U, 4897U, 18500U, 49U, 13098U, 15562U, | |
| 3641U, 3697U, 4037U, 5676U, 8466U, 6896U, 3586U, 17201U, | |
| 11028U, 20940U, 11134U, 20965U, 3887U, 19521U, 5623U, 19905U, | |
| 6841U, 20159U, 12839U, 21079U, 17111U, 21682U, 11075U, 20952U, | |
| 11143U, 20978U, 3778U, 19498U, 5485U, 19892U, 6749U, 20136U, | |
| 12723U, 21066U, 16950U, 21659U, 4002U, 19575U, 5632U, 19918U, | |
| 6861U, 20172U, 12848U, 21092U, 17143U, 21695U, 3604U, 19486U, | |
| 6613U, 20124U, 16466U, 21601U, 4028U, 19588U, 6887U, 20185U, | |
| 17192U, 21717U, 12716U, 12832U, 3570U, 4701U, 6592U, 16398U, | |
| 14668U, 23U, 14675U, 32U, 4043U, 5689U, 8481U, 6902U, | |
| 3595U, 17216U, 5448U, 12708U, 16872U, 5585U, 12824U, 17073U, | |
| 5494U, 12732U, 16965U, 5641U, 12857U, 17152U, 15986U, 8327U, | |
| 8401U, 8551U, 8709U, 8996U, 11090U, 17924U, 18258U, 17913U, | |
| 18247U, 17943U, 18277U, 17963U, 18297U, 8354U, 5521U, 8419U, | |
| 8578U, 8727U, 3991U, 6850U, 17120U, 9014U, 4554U, 22547U, | |
| 16007U, 22662U, 12573U, 4563U, 22557U, 16016U, 22672U, 4572U, | |
| 22567U, 17870U, 18191U, 17895U, 18229U, 17982U, 18316U, 4695U, | |
| 3666U, 17862U, 18183U, 17904U, 18238U, 5471U, 17879U, 18213U, | |
| 3828U, 5540U, 6789U, 17003U, 17887U, 18221U, 17934U, 18268U, | |
| 16936U, 17974U, 18308U, 17954U, 18288U, 11067U, 11052U, 11152U, | |
| 3795U, 5501U, 6766U, 16972U, 4011U, 5648U, 6870U, 17159U, | |
| 13977U, 13987U, 11109U, 3763U, 5464U, 6734U, 16929U, 3872U, | |
| 5601U, 6826U, 17096U, 8597U, 5433U, 12701U, 16857U, 5570U, | |
| 12807U, 17050U, 16459U, 3612U, 6621U, 16497U, 3628U, 6628U, | |
| 16541U, 16789U, 5561U, 8337U, 8569U, 14006U, 8381U, 8446U, | |
| 8615U, 14031U, 12752U, 12778U, 12814U, 12743U, 3709U, 5440U, | |
| 6680U, 16864U, 3857U, 5577U, 6811U, 17065U, 5456U, 16895U, | |
| 5593U, 17088U, 5003U, 3770U, 5477U, 6741U, 16942U, 3879U, | |
| 5608U, 6833U, 17103U, 9041U, 5093U, 13089U, 15549U, 4929U, | |
| 16491U, 11036U, 13351U, 13403U, 4454U, 5284U, 8772U, 13316U, | |
| 13420U, 5554U, 18085U, 14348U, 14462U, 14386U, 14485U, 14394U, | |
| 14508U, 8930U, 14470U, 8938U, 14493U, 8988U, 14516U, 3658U, | |
| 5062U, 6661U, 16589U, 3819U, 5531U, 6780U, 16994U, 4709U, | |
| 12588U, 16406U, 11084U, 8644U, 9221U, 11177U, 18798U, 3648U, | |
| 5024U, 7196U, 8681U, 6635U, 12672U, 7217U, 8695U, 16569U, | |
| 7303U, 8702U, 11099U, 17999U, 7795U, 4596U, 16381U, 8069U, | |
| 3653U, 5029U, 6918U, 7329U, 6640U, 9982U, 12677U, 15967U, | |
| 16575U, 3812U, 22539U, 6773U, 22577U, 3746U, 6717U, 16903U, | |
| 16979U, 13549U, 3558U, 4689U, 6586U, 12582U, 16392U, 3704U, | |
| 5396U, 6925U, 6675U, 10109U, 12696U, 15991U, 16838U, 7652U, | |
| 20420U, 12879U, 21105U, 7812U, 20453U, 13194U, 21138U, 12762U, | |
| 17034U, 12789U, 8754U, 11045U, 13694U, 13969U, 14554U, 8365U, | |
| 13719U, 8430U, 8589U, 14015U, 8738U, 9025U, 14578U, 14545U, | |
| 13685U, 13960U, 13710U, 14570U, 18077U, 3738U, 6709U, 16887U, | |
| 18091U, 3755U, 6726U, 16912U, 13436U, 16U, 3550U, 6578U, | |
| 13866U, 3717U, 6688U, 15085U, 5839U, 7067U, 13410U, 2646U, | |
| 19415U, 7364U, 2231U, 14072U, 2716U, 21166U, 10813U, 11913U, | |
| 10373U, 11758U, 10064U, 12077U, 10775U, 11876U, 10746U, 11856U, | |
| 10429U, 11784U, 10829U, 11921U, 10683U, 11829U, 10887U, 11940U, | |
| 10647U, 11819U, 11159U, 11838U, 12314U, 9577U, 13800U, 22614U, | |
| 14602U, 22638U, 13833U, 22626U, 14635U, 22650U, 10692U, 10701U, | |
| 10003U, 18773U, 18896U, 18998U, 18783U, 18906U, 19008U, 11766U, | |
| 10710U, 9529U, 11886U, 10389U, 12093U, 11775U, 11895U, 10409U, | |
| 12113U, 10896U, 11949U, 10092U, 12450U, 10728U, 11847U, 10299U, | |
| 12021U, 10627U, 12276U, 11749U, 10054U, 10364U, 11730U, 10950U, | |
| 10538U, 10355U, 11721U, 10667U, 10529U, 10257U, 11979U, 10585U, | |
| 12234U, 11694U, 10024U, 10547U, 11811U, 10073U, 12196U, 10795U, | |
| 22604U, 11904U, 10485U, 11794U, 10277U, 11999U, 10605U, 12254U, | |
| 11739U, 10043U, 10235U, 11957U, 10563U, 12212U, 11684U, 10013U, | |
| 7336U, 4234U, 8650U, 11183U, 18804U, 10449U, 12143U, 7350U, | |
| 17854U, 12565U, 12374U, 10463U, 12157U, 10849U, 11931U, 10082U, | |
| 12422U, 10319U, 11703U, 10034U, 12041U, 10904U, 10858U, 10335U, | |
| 11711U, 12057U, 10757U, 11867U, 10501U, 11802U, 10821U, 12389U, | |
| 10381U, 12085U, 781U, 9372U, 11239U, 9502U, 11429U, 16027U, | |
| 9427U, 11294U, 9589U, 11568U, 10785U, 20912U, 12359U, 21005U, | |
| 10439U, 20898U, 12133U, 20991U, 10839U, 20926U, 12412U, 21028U, | |
| 10657U, 12296U, 9565U, 12323U, 13811U, 14613U, 13844U, 14646U, | |
| 12332U, 1411U, 10719U, 11168U, 13822U, 14624U, 13855U, 14657U, | |
| 10399U, 12103U, 10930U, 12475U, 10419U, 12123U, 10940U, 12485U, | |
| 10922U, 12467U, 794U, 9387U, 11254U, 9517U, 11444U, 16041U, | |
| 9443U, 11310U, 9605U, 11584U, 13069U, 9401U, 11268U, 9541U, | |
| 11498U, 16816U, 9458U, 11325U, 9620U, 11642U, 13080U, 9414U, | |
| 11281U, 9554U, 11511U, 16828U, 9472U, 11339U, 9634U, 11656U, | |
| 806U, 11458U, 13608U, 11524U, 16845U, 11670U, 16054U, 11599U, | |
| 2588U, 11485U, 16079U, 11628U, 1402U, 11472U, 11539U, 16067U, | |
| 11614U, 11553U, 10737U, 12341U, 10309U, 12031U, 10637U, 12286U, | |
| 10958U, 12495U, 10675U, 12306U, 10267U, 11989U, 10595U, 12244U, | |
| 10555U, 12204U, 10804U, 12380U, 10493U, 12179U, 10288U, 12010U, | |
| 10616U, 12265U, 10246U, 11968U, 10574U, 12223U, 7343U, 4242U, | |
| 8658U, 11191U, 18812U, 10456U, 12150U, 7357U, 4250U, 8666U, | |
| 11199U, 18820U, 10474U, 12168U, 10878U, 12441U, 10327U, 12049U, | |
| 10913U, 12458U, 3578U, 10868U, 12431U, 10345U, 12067U, 10766U, | |
| 12350U, 10510U, 12187U, 4018U, 5655U, 6877U, 17166U, 5319U, | |
| 6669U, 12690U, 16808U, 7645U, 17131U, 8390U, 8455U, 8624U, | |
| 9049U, 17012U, 5070U, 4172U, 15972U, 22691U, 5077U, 13337U, | |
| 13331U, 4440U, 22163U, 13407U, 22810U, 22820U, 22802U, 4066U, | |
| 16414U, 16504U, 16548U, 4074U, 16423U, 8778U, 7020U, 22585U, | |
| 13323U, 17991U, 7800U, 18732U, 17181U, 7511U, 22595U, 17516U, | |
| 3619U, 10519U, 16532U, 16986U, 22682U, 4062U, 3205U, 22712U, | |
| 13562U, 8033U, 7660U, 3469U, 22719U, 13237U, 7983U, 22733U, | |
| 22727U, | |
| }; | |
| extern const uint8_t PPCInstrDeprecationFeatures[] = { | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), PPC::DeprecatedDST, PPC::DeprecatedDST, PPC::DeprecatedDST, PPC::DeprecatedDST, PPC::DeprecatedDST, | |
| PPC::DeprecatedDST, PPC::DeprecatedDST, PPC::DeprecatedDST, PPC::DeprecatedDST, PPC::DeprecatedDST, uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), uint8_t(-1), | |
| uint8_t(-1), | |
| }; | |
| static inline void InitPPCMCInstrInfo(MCInstrInfo *II) { | |
| II->InitMCInstrInfo(PPCInsts, PPCInstrNameIndices, PPCInstrNameData, PPCInstrDeprecationFeatures, nullptr, 2633); | |
| } | |
| } // end namespace llvm | |
| #endif // GET_INSTRINFO_MC_DESC | |
| #ifdef GET_INSTRINFO_HEADER | |
| #undef GET_INSTRINFO_HEADER | |
| namespace llvm { | |
| struct PPCGenInstrInfo : public TargetInstrInfo { | |
| explicit PPCGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u); | |
| ~PPCGenInstrInfo() override = default; | |
| }; | |
| } // end namespace llvm | |
| #endif // GET_INSTRINFO_HEADER | |
| #ifdef GET_INSTRINFO_HELPER_DECLS | |
| #undef GET_INSTRINFO_HELPER_DECLS | |
| #endif // GET_INSTRINFO_HELPER_DECLS | |
| #ifdef GET_INSTRINFO_HELPERS | |
| #undef GET_INSTRINFO_HELPERS | |
| #endif // GET_INSTRINFO_HELPERS | |
| #ifdef GET_INSTRINFO_CTOR_DTOR | |
| #undef GET_INSTRINFO_CTOR_DTOR | |
| namespace llvm { | |
| extern const MCInstrDesc PPCInsts[]; | |
| extern const unsigned PPCInstrNameIndices[]; | |
| extern const char PPCInstrNameData[]; | |
| extern const uint8_t PPCInstrDeprecationFeatures[]; | |
| PPCGenInstrInfo::PPCGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode) | |
| : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) { | |
| InitMCInstrInfo(PPCInsts, PPCInstrNameIndices, PPCInstrNameData, PPCInstrDeprecationFeatures, nullptr, 2633); | |
| } | |
| } // end namespace llvm | |
| #endif // GET_INSTRINFO_CTOR_DTOR | |
| #ifdef GET_INSTRINFO_OPERAND_ENUM | |
| #undef GET_INSTRINFO_OPERAND_ENUM | |
| namespace llvm { | |
| namespace PPC { | |
| namespace OpName { | |
| enum { | |
| OPERAND_LAST | |
| }; | |
| } // end namespace OpName | |
| } // end namespace PPC | |
| } // end namespace llvm | |
| #endif //GET_INSTRINFO_OPERAND_ENUM | |
| #ifdef GET_INSTRINFO_NAMED_OPS | |
| #undef GET_INSTRINFO_NAMED_OPS | |
| namespace llvm { | |
| namespace PPC { | |
| LLVM_READONLY | |
| int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) { | |
| return -1; | |
| } | |
| } // end namespace PPC | |
| } // end namespace llvm | |
| #endif //GET_INSTRINFO_NAMED_OPS | |
| #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM | |
| #undef GET_INSTRINFO_OPERAND_TYPES_ENUM | |
| namespace llvm { | |
| namespace PPC { | |
| namespace OpTypes { | |
| enum OperandType { | |
| abscalltarget = 0, | |
| abscondbrtarget = 1, | |
| absdirectbrtarget = 2, | |
| atimm = 3, | |
| calltarget = 4, | |
| condbrtarget = 5, | |
| crbitm = 6, | |
| directbrtarget = 7, | |
| dispRI = 8, | |
| dispRI34 = 9, | |
| dispRIHash = 10, | |
| dispRIX = 11, | |
| dispRIX16 = 12, | |
| dispSPE2 = 13, | |
| dispSPE4 = 14, | |
| dispSPE8 = 15, | |
| f32imm = 16, | |
| f64imm = 17, | |
| i16imm = 18, | |
| i1imm = 19, | |
| i32imm = 20, | |
| i64imm = 21, | |
| i8imm = 22, | |
| imm32SExt16 = 23, | |
| imm64SExt16 = 24, | |
| imm64ZExt32 = 25, | |
| immZero = 26, | |
| memr = 27, | |
| memri = 28, | |
| memri34 = 29, | |
| memri34_pcrel = 30, | |
| memrihash = 31, | |
| memrix = 32, | |
| memrix16 = 33, | |
| memrr = 34, | |
| pred = 35, | |
| ptr_rc_idx = 36, | |
| ptr_rc_nor0 = 37, | |
| ptype0 = 38, | |
| ptype1 = 39, | |
| ptype2 = 40, | |
| ptype3 = 41, | |
| ptype4 = 42, | |
| ptype5 = 43, | |
| s16imm = 44, | |
| s16imm64 = 45, | |
| s17imm = 46, | |
| s17imm64 = 47, | |
| s34imm = 48, | |
| s34imm_pcrel = 49, | |
| s5imm = 50, | |
| spe2dis = 51, | |
| spe4dis = 52, | |
| spe8dis = 53, | |
| tlscall = 54, | |
| tlscall32 = 55, | |
| tlsgd = 56, | |
| tlsgd32 = 57, | |
| tlsreg = 58, | |
| tlsreg32 = 59, | |
| tocentry = 60, | |
| tocentry32 = 61, | |
| type0 = 62, | |
| type1 = 63, | |
| type2 = 64, | |
| type3 = 65, | |
| type4 = 66, | |
| type5 = 67, | |
| u10imm = 68, | |
| u12imm = 69, | |
| u16imm = 70, | |
| u16imm64 = 71, | |
| u1imm = 72, | |
| u2imm = 73, | |
| u3imm = 74, | |
| u4imm = 75, | |
| u5imm = 76, | |
| u6imm = 77, | |
| u7imm = 78, | |
| u8imm = 79, | |
| untyped_imm_0 = 80, | |
| acc = 81, | |
| crbitrc = 82, | |
| crrc = 83, | |
| dmr = 84, | |
| dmrp = 85, | |
| dmrrow = 86, | |
| dmrrowp = 87, | |
| f4rc = 88, | |
| f8rc = 89, | |
| g8prc = 90, | |
| g8rc = 91, | |
| g8rc_nox0 = 92, | |
| gprc = 93, | |
| gprc_nor0 = 94, | |
| spe4rc = 95, | |
| sperc = 96, | |
| spilltovsrrc = 97, | |
| uacc = 98, | |
| vfrc = 99, | |
| vrrc = 100, | |
| vsfrc = 101, | |
| vsrc = 102, | |
| vsrpevenrc = 103, | |
| vsrprc = 104, | |
| vssrc = 105, | |
| wacc = 106, | |
| wacc_hi = 107, | |
| ACCRC = 108, | |
| CARRYRC = 109, | |
| CRBITRC = 110, | |
| CRRC = 111, | |
| CTRRC = 112, | |
| CTRRC8 = 113, | |
| DMRRC = 114, | |
| DMRROWRC = 115, | |
| DMRROWpRC = 116, | |
| DMRpRC = 117, | |
| F4RC = 118, | |
| F8RC = 119, | |
| G8RC = 120, | |
| G8RC_NOX0 = 121, | |
| G8pRC = 122, | |
| GPRC = 123, | |
| GPRC_NOR0 = 124, | |
| LR8RC = 125, | |
| LRRC = 126, | |
| SPERC = 127, | |
| SPILLTOVSRRC = 128, | |
| UACCRC = 129, | |
| VFRC = 130, | |
| VRRC = 131, | |
| VRSAVERC = 132, | |
| VSFRC = 133, | |
| VSLRC = 134, | |
| VSRC = 135, | |
| VSRpRC = 136, | |
| VSSRC = 137, | |
| WACCRC = 138, | |
| WACC_HIRC = 139, | |
| OPERAND_TYPE_LIST_END | |
| }; | |
| } // end namespace OpTypes | |
| } // end namespace PPC | |
| } // end namespace llvm | |
| #endif // GET_INSTRINFO_OPERAND_TYPES_ENUM | |
| #ifdef GET_INSTRINFO_OPERAND_TYPE | |
| #undef GET_INSTRINFO_OPERAND_TYPE | |
| namespace llvm { | |
| namespace PPC { | |
| LLVM_READONLY | |
| static int getOperandType(uint16_t Opcode, uint16_t OpIdx) { | |
| const uint16_t Offsets[] = { | |
| /* PHI */ | |
| 0, | |
| /* INLINEASM */ | |
| 1, | |
| /* INLINEASM_BR */ | |
| 1, | |
| /* CFI_INSTRUCTION */ | |
| 1, | |
| /* EH_LABEL */ | |
| 2, | |
| /* GC_LABEL */ | |
| 3, | |
| /* ANNOTATION_LABEL */ | |
| 4, | |
| /* KILL */ | |
| 5, | |
| /* EXTRACT_SUBREG */ | |
| 5, | |
| /* INSERT_SUBREG */ | |
| 8, | |
| /* IMPLICIT_DEF */ | |
| 12, | |
| /* SUBREG_TO_REG */ | |
| 13, | |
| /* COPY_TO_REGCLASS */ | |
| 17, | |
| /* DBG_VALUE */ | |
| 20, | |
| /* DBG_VALUE_LIST */ | |
| 20, | |
| /* DBG_INSTR_REF */ | |
| 20, | |
| /* DBG_PHI */ | |
| 20, | |
| /* DBG_LABEL */ | |
| 20, | |
| /* REG_SEQUENCE */ | |
| 21, | |
| /* COPY */ | |
| 23, | |
| /* BUNDLE */ | |
| 25, | |
| /* LIFETIME_START */ | |
| 25, | |
| /* LIFETIME_END */ | |
| 26, | |
| /* PSEUDO_PROBE */ | |
| 27, | |
| /* ARITH_FENCE */ | |
| 31, | |
| /* STACKMAP */ | |
| 33, | |
| /* FENTRY_CALL */ | |
| 35, | |
| /* PATCHPOINT */ | |
| 35, | |
| /* LOAD_STACK_GUARD */ | |
| 41, | |
| /* PREALLOCATED_SETUP */ | |
| 42, | |
| /* PREALLOCATED_ARG */ | |
| 43, | |
| /* STATEPOINT */ | |
| 46, | |
| /* LOCAL_ESCAPE */ | |
| 46, | |
| /* FAULTING_OP */ | |
| 48, | |
| /* PATCHABLE_OP */ | |
| 49, | |
| /* PATCHABLE_FUNCTION_ENTER */ | |
| 49, | |
| /* PATCHABLE_RET */ | |
| 49, | |
| /* PATCHABLE_FUNCTION_EXIT */ | |
| 49, | |
| /* PATCHABLE_TAIL_CALL */ | |
| 49, | |
| /* PATCHABLE_EVENT_CALL */ | |
| 49, | |
| /* PATCHABLE_TYPED_EVENT_CALL */ | |
| 51, | |
| /* ICALL_BRANCH_FUNNEL */ | |
| 54, | |
| /* MEMBARRIER */ | |
| 54, | |
| /* G_ASSERT_SEXT */ | |
| 54, | |
| /* G_ASSERT_ZEXT */ | |
| 57, | |
| /* G_ASSERT_ALIGN */ | |
| 60, | |
| /* G_ADD */ | |
| 63, | |
| /* G_SUB */ | |
| 66, | |
| /* G_MUL */ | |
| 69, | |
| /* G_SDIV */ | |
| 72, | |
| /* G_UDIV */ | |
| 75, | |
| /* G_SREM */ | |
| 78, | |
| /* G_UREM */ | |
| 81, | |
| /* G_SDIVREM */ | |
| 84, | |
| /* G_UDIVREM */ | |
| 88, | |
| /* G_AND */ | |
| 92, | |
| /* G_OR */ | |
| 95, | |
| /* G_XOR */ | |
| 98, | |
| /* G_IMPLICIT_DEF */ | |
| 101, | |
| /* G_PHI */ | |
| 102, | |
| /* G_FRAME_INDEX */ | |
| 103, | |
| /* G_GLOBAL_VALUE */ | |
| 105, | |
| /* G_EXTRACT */ | |
| 107, | |
| /* G_UNMERGE_VALUES */ | |
| 110, | |
| /* G_INSERT */ | |
| 112, | |
| /* G_MERGE_VALUES */ | |
| 116, | |
| /* G_BUILD_VECTOR */ | |
| 118, | |
| /* G_BUILD_VECTOR_TRUNC */ | |
| 120, | |
| /* G_CONCAT_VECTORS */ | |
| 122, | |
| /* G_PTRTOINT */ | |
| 124, | |
| /* G_INTTOPTR */ | |
| 126, | |
| /* G_BITCAST */ | |
| 128, | |
| /* G_FREEZE */ | |
| 130, | |
| /* G_INTRINSIC_FPTRUNC_ROUND */ | |
| 132, | |
| /* G_INTRINSIC_TRUNC */ | |
| 135, | |
| /* G_INTRINSIC_ROUND */ | |
| 137, | |
| /* G_INTRINSIC_LRINT */ | |
| 139, | |
| /* G_INTRINSIC_ROUNDEVEN */ | |
| 141, | |
| /* G_READCYCLECOUNTER */ | |
| 143, | |
| /* G_LOAD */ | |
| 144, | |
| /* G_SEXTLOAD */ | |
| 146, | |
| /* G_ZEXTLOAD */ | |
| 148, | |
| /* G_INDEXED_LOAD */ | |
| 150, | |
| /* G_INDEXED_SEXTLOAD */ | |
| 155, | |
| /* G_INDEXED_ZEXTLOAD */ | |
| 160, | |
| /* G_STORE */ | |
| 165, | |
| /* G_INDEXED_STORE */ | |
| 167, | |
| /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ | |
| 172, | |
| /* G_ATOMIC_CMPXCHG */ | |
| 177, | |
| /* G_ATOMICRMW_XCHG */ | |
| 181, | |
| /* G_ATOMICRMW_ADD */ | |
| 184, | |
| /* G_ATOMICRMW_SUB */ | |
| 187, | |
| /* G_ATOMICRMW_AND */ | |
| 190, | |
| /* G_ATOMICRMW_NAND */ | |
| 193, | |
| /* G_ATOMICRMW_OR */ | |
| 196, | |
| /* G_ATOMICRMW_XOR */ | |
| 199, | |
| /* G_ATOMICRMW_MAX */ | |
| 202, | |
| /* G_ATOMICRMW_MIN */ | |
| 205, | |
| /* G_ATOMICRMW_UMAX */ | |
| 208, | |
| /* G_ATOMICRMW_UMIN */ | |
| 211, | |
| /* G_ATOMICRMW_FADD */ | |
| 214, | |
| /* G_ATOMICRMW_FSUB */ | |
| 217, | |
| /* G_ATOMICRMW_FMAX */ | |
| 220, | |
| /* G_ATOMICRMW_FMIN */ | |
| 223, | |
| /* G_ATOMICRMW_UINC_WRAP */ | |
| 226, | |
| /* G_ATOMICRMW_UDEC_WRAP */ | |
| 229, | |
| /* G_FENCE */ | |
| 232, | |
| /* G_BRCOND */ | |
| 234, | |
| /* G_BRINDIRECT */ | |
| 236, | |
| /* G_INVOKE_REGION_START */ | |
| 237, | |
| /* G_INTRINSIC */ | |
| 237, | |
| /* G_INTRINSIC_W_SIDE_EFFECTS */ | |
| 238, | |
| /* G_ANYEXT */ | |
| 239, | |
| /* G_TRUNC */ | |
| 241, | |
| /* G_CONSTANT */ | |
| 243, | |
| /* G_FCONSTANT */ | |
| 245, | |
| /* G_VASTART */ | |
| 247, | |
| /* G_VAARG */ | |
| 248, | |
| /* G_SEXT */ | |
| 251, | |
| /* G_SEXT_INREG */ | |
| 253, | |
| /* G_ZEXT */ | |
| 256, | |
| /* G_SHL */ | |
| 258, | |
| /* G_LSHR */ | |
| 261, | |
| /* G_ASHR */ | |
| 264, | |
| /* G_FSHL */ | |
| 267, | |
| /* G_FSHR */ | |
| 271, | |
| /* G_ROTR */ | |
| 275, | |
| /* G_ROTL */ | |
| 278, | |
| /* G_ICMP */ | |
| 281, | |
| /* G_FCMP */ | |
| 285, | |
| /* G_SELECT */ | |
| 289, | |
| /* G_UADDO */ | |
| 293, | |
| /* G_UADDE */ | |
| 297, | |
| /* G_USUBO */ | |
| 302, | |
| /* G_USUBE */ | |
| 306, | |
| /* G_SADDO */ | |
| 311, | |
| /* G_SADDE */ | |
| 315, | |
| /* G_SSUBO */ | |
| 320, | |
| /* G_SSUBE */ | |
| 324, | |
| /* G_UMULO */ | |
| 329, | |
| /* G_SMULO */ | |
| 333, | |
| /* G_UMULH */ | |
| 337, | |
| /* G_SMULH */ | |
| 340, | |
| /* G_UADDSAT */ | |
| 343, | |
| /* G_SADDSAT */ | |
| 346, | |
| /* G_USUBSAT */ | |
| 349, | |
| /* G_SSUBSAT */ | |
| 352, | |
| /* G_USHLSAT */ | |
| 355, | |
| /* G_SSHLSAT */ | |
| 358, | |
| /* G_SMULFIX */ | |
| 361, | |
| /* G_UMULFIX */ | |
| 365, | |
| /* G_SMULFIXSAT */ | |
| 369, | |
| /* G_UMULFIXSAT */ | |
| 373, | |
| /* G_SDIVFIX */ | |
| 377, | |
| /* G_UDIVFIX */ | |
| 381, | |
| /* G_SDIVFIXSAT */ | |
| 385, | |
| /* G_UDIVFIXSAT */ | |
| 389, | |
| /* G_FADD */ | |
| 393, | |
| /* G_FSUB */ | |
| 396, | |
| /* G_FMUL */ | |
| 399, | |
| /* G_FMA */ | |
| 402, | |
| /* G_FMAD */ | |
| 406, | |
| /* G_FDIV */ | |
| 410, | |
| /* G_FREM */ | |
| 413, | |
| /* G_FPOW */ | |
| 416, | |
| /* G_FPOWI */ | |
| 419, | |
| /* G_FEXP */ | |
| 422, | |
| /* G_FEXP2 */ | |
| 424, | |
| /* G_FLOG */ | |
| 426, | |
| /* G_FLOG2 */ | |
| 428, | |
| /* G_FLOG10 */ | |
| 430, | |
| /* G_FNEG */ | |
| 432, | |
| /* G_FPEXT */ | |
| 434, | |
| /* G_FPTRUNC */ | |
| 436, | |
| /* G_FPTOSI */ | |
| 438, | |
| /* G_FPTOUI */ | |
| 440, | |
| /* G_SITOFP */ | |
| 442, | |
| /* G_UITOFP */ | |
| 444, | |
| /* G_FABS */ | |
| 446, | |
| /* G_FCOPYSIGN */ | |
| 448, | |
| /* G_IS_FPCLASS */ | |
| 451, | |
| /* G_FCANONICALIZE */ | |
| 454, | |
| /* G_FMINNUM */ | |
| 456, | |
| /* G_FMAXNUM */ | |
| 459, | |
| /* G_FMINNUM_IEEE */ | |
| 462, | |
| /* G_FMAXNUM_IEEE */ | |
| 465, | |
| /* G_FMINIMUM */ | |
| 468, | |
| /* G_FMAXIMUM */ | |
| 471, | |
| /* G_PTR_ADD */ | |
| 474, | |
| /* G_PTRMASK */ | |
| 477, | |
| /* G_SMIN */ | |
| 480, | |
| /* G_SMAX */ | |
| 483, | |
| /* G_UMIN */ | |
| 486, | |
| /* G_UMAX */ | |
| 489, | |
| /* G_ABS */ | |
| 492, | |
| /* G_LROUND */ | |
| 494, | |
| /* G_LLROUND */ | |
| 496, | |
| /* G_BR */ | |
| 498, | |
| /* G_BRJT */ | |
| 499, | |
| /* G_INSERT_VECTOR_ELT */ | |
| 502, | |
| /* G_EXTRACT_VECTOR_ELT */ | |
| 506, | |
| /* G_SHUFFLE_VECTOR */ | |
| 509, | |
| /* G_CTTZ */ | |
| 513, | |
| /* G_CTTZ_ZERO_UNDEF */ | |
| 515, | |
| /* G_CTLZ */ | |
| 517, | |
| /* G_CTLZ_ZERO_UNDEF */ | |
| 519, | |
| /* G_CTPOP */ | |
| 521, | |
| /* G_BSWAP */ | |
| 523, | |
| /* G_BITREVERSE */ | |
| 525, | |
| /* G_FCEIL */ | |
| 527, | |
| /* G_FCOS */ | |
| 529, | |
| /* G_FSIN */ | |
| 531, | |
| /* G_FSQRT */ | |
| 533, | |
| /* G_FFLOOR */ | |
| 535, | |
| /* G_FRINT */ | |
| 537, | |
| /* G_FNEARBYINT */ | |
| 539, | |
| /* G_ADDRSPACE_CAST */ | |
| 541, | |
| /* G_BLOCK_ADDR */ | |
| 543, | |
| /* G_JUMP_TABLE */ | |
| 545, | |
| /* G_DYN_STACKALLOC */ | |
| 547, | |
| /* G_STRICT_FADD */ | |
| 550, | |
| /* G_STRICT_FSUB */ | |
| 553, | |
| /* G_STRICT_FMUL */ | |
| 556, | |
| /* G_STRICT_FDIV */ | |
| 559, | |
| /* G_STRICT_FREM */ | |
| 562, | |
| /* G_STRICT_FMA */ | |
| 565, | |
| /* G_STRICT_FSQRT */ | |
| 569, | |
| /* G_READ_REGISTER */ | |
| 571, | |
| /* G_WRITE_REGISTER */ | |
| 573, | |
| /* G_MEMCPY */ | |
| 575, | |
| /* G_MEMCPY_INLINE */ | |
| 579, | |
| /* G_MEMMOVE */ | |
| 582, | |
| /* G_MEMSET */ | |
| 586, | |
| /* G_BZERO */ | |
| 590, | |
| /* G_VECREDUCE_SEQ_FADD */ | |
| 593, | |
| /* G_VECREDUCE_SEQ_FMUL */ | |
| 596, | |
| /* G_VECREDUCE_FADD */ | |
| 599, | |
| /* G_VECREDUCE_FMUL */ | |
| 601, | |
| /* G_VECREDUCE_FMAX */ | |
| 603, | |
| /* G_VECREDUCE_FMIN */ | |
| 605, | |
| /* G_VECREDUCE_ADD */ | |
| 607, | |
| /* G_VECREDUCE_MUL */ | |
| 609, | |
| /* G_VECREDUCE_AND */ | |
| 611, | |
| /* G_VECREDUCE_OR */ | |
| 613, | |
| /* G_VECREDUCE_XOR */ | |
| 615, | |
| /* G_VECREDUCE_SMAX */ | |
| 617, | |
| /* G_VECREDUCE_SMIN */ | |
| 619, | |
| /* G_VECREDUCE_UMAX */ | |
| 621, | |
| /* G_VECREDUCE_UMIN */ | |
| 623, | |
| /* G_SBFX */ | |
| 625, | |
| /* G_UBFX */ | |
| 629, | |
| /* ATOMIC_CMP_SWAP_I128 */ | |
| 633, | |
| /* ATOMIC_LOAD_ADD_I128 */ | |
| 641, | |
| /* ATOMIC_LOAD_AND_I128 */ | |
| 647, | |
| /* ATOMIC_LOAD_NAND_I128 */ | |
| 653, | |
| /* ATOMIC_LOAD_OR_I128 */ | |
| 659, | |
| /* ATOMIC_LOAD_SUB_I128 */ | |
| 665, | |
| /* ATOMIC_LOAD_XOR_I128 */ | |
| 671, | |
| /* ATOMIC_SWAP_I128 */ | |
| 677, | |
| /* BUILD_QUADWORD */ | |
| 683, | |
| /* BUILD_UACC */ | |
| 686, | |
| /* CFENCE8 */ | |
| 688, | |
| /* CLRLSLDI */ | |
| 689, | |
| /* CLRLSLDI_rec */ | |
| 693, | |
| /* CLRLSLWI */ | |
| 697, | |
| /* CLRLSLWI_rec */ | |
| 701, | |
| /* CLRRDI */ | |
| 705, | |
| /* CLRRDI_rec */ | |
| 708, | |
| /* CLRRWI */ | |
| 711, | |
| /* CLRRWI_rec */ | |
| 714, | |
| /* DCBFL */ | |
| 717, | |
| /* DCBFLP */ | |
| 719, | |
| /* DCBFPS */ | |
| 721, | |
| /* DCBFx */ | |
| 723, | |
| /* DCBSTPS */ | |
| 725, | |
| /* DCBTCT */ | |
| 727, | |
| /* DCBTDS */ | |
| 730, | |
| /* DCBTSTCT */ | |
| 733, | |
| /* DCBTSTDS */ | |
| 736, | |
| /* DCBTSTT */ | |
| 739, | |
| /* DCBTSTx */ | |
| 741, | |
| /* DCBTT */ | |
| 743, | |
| /* DCBTx */ | |
| 745, | |
| /* DFLOADf32 */ | |
| 747, | |
| /* DFLOADf64 */ | |
| 750, | |
| /* DFSTOREf32 */ | |
| 753, | |
| /* DFSTOREf64 */ | |
| 756, | |
| /* EXTLDI */ | |
| 759, | |
| /* EXTLDI_rec */ | |
| 763, | |
| /* EXTLWI */ | |
| 767, | |
| /* EXTLWI_rec */ | |
| 771, | |
| /* EXTRDI */ | |
| 775, | |
| /* EXTRDI_rec */ | |
| 779, | |
| /* EXTRWI */ | |
| 783, | |
| /* EXTRWI_rec */ | |
| 787, | |
| /* INSLWI */ | |
| 791, | |
| /* INSLWI_rec */ | |
| 795, | |
| /* INSRDI */ | |
| 799, | |
| /* INSRDI_rec */ | |
| 803, | |
| /* INSRWI */ | |
| 807, | |
| /* INSRWI_rec */ | |
| 811, | |
| /* KILL_PAIR */ | |
| 815, | |
| /* LAx */ | |
| 817, | |
| /* LIWAX */ | |
| 820, | |
| /* LIWZX */ | |
| 823, | |
| /* RLWIMIbm */ | |
| 826, | |
| /* RLWIMIbm_rec */ | |
| 830, | |
| /* RLWINMbm */ | |
| 834, | |
| /* RLWINMbm_rec */ | |
| 838, | |
| /* RLWNMbm */ | |
| 842, | |
| /* RLWNMbm_rec */ | |
| 846, | |
| /* ROTRDI */ | |
| 850, | |
| /* ROTRDI_rec */ | |
| 853, | |
| /* ROTRWI */ | |
| 856, | |
| /* ROTRWI_rec */ | |
| 859, | |
| /* SLDI */ | |
| 862, | |
| /* SLDI_rec */ | |
| 865, | |
| /* SLWI */ | |
| 868, | |
| /* SLWI_rec */ | |
| 871, | |
| /* SPILLTOVSR_LD */ | |
| 874, | |
| /* SPILLTOVSR_LDX */ | |
| 877, | |
| /* SPILLTOVSR_ST */ | |
| 880, | |
| /* SPILLTOVSR_STX */ | |
| 883, | |
| /* SRDI */ | |
| 886, | |
| /* SRDI_rec */ | |
| 889, | |
| /* SRWI */ | |
| 892, | |
| /* SRWI_rec */ | |
| 895, | |
| /* STIWX */ | |
| 898, | |
| /* SUBI */ | |
| 901, | |
| /* SUBIC */ | |
| 904, | |
| /* SUBIC_rec */ | |
| 907, | |
| /* SUBIS */ | |
| 910, | |
| /* SUBPCIS */ | |
| 913, | |
| /* XFLOADf32 */ | |
| 915, | |
| /* XFLOADf64 */ | |
| 918, | |
| /* XFSTOREf32 */ | |
| 921, | |
| /* XFSTOREf64 */ | |
| 924, | |
| /* ADD4 */ | |
| 927, | |
| /* ADD4O */ | |
| 930, | |
| /* ADD4O_rec */ | |
| 933, | |
| /* ADD4TLS */ | |
| 936, | |
| /* ADD4_rec */ | |
| 939, | |
| /* ADD8 */ | |
| 942, | |
| /* ADD8O */ | |
| 945, | |
| /* ADD8O_rec */ | |
| 948, | |
| /* ADD8TLS */ | |
| 951, | |
| /* ADD8TLS_ */ | |
| 954, | |
| /* ADD8_rec */ | |
| 957, | |
| /* ADDC */ | |
| 960, | |
| /* ADDC8 */ | |
| 963, | |
| /* ADDC8O */ | |
| 966, | |
| /* ADDC8O_rec */ | |
| 969, | |
| /* ADDC8_rec */ | |
| 972, | |
| /* ADDCO */ | |
| 975, | |
| /* ADDCO_rec */ | |
| 978, | |
| /* ADDC_rec */ | |
| 981, | |
| /* ADDE */ | |
| 984, | |
| /* ADDE8 */ | |
| 987, | |
| /* ADDE8O */ | |
| 990, | |
| /* ADDE8O_rec */ | |
| 993, | |
| /* ADDE8_rec */ | |
| 996, | |
| /* ADDEO */ | |
| 999, | |
| /* ADDEO_rec */ | |
| 1002, | |
| /* ADDEX */ | |
| 1005, | |
| /* ADDEX8 */ | |
| 1009, | |
| /* ADDE_rec */ | |
| 1013, | |
| /* ADDI */ | |
| 1016, | |
| /* ADDI8 */ | |
| 1019, | |
| /* ADDIC */ | |
| 1022, | |
| /* ADDIC8 */ | |
| 1025, | |
| /* ADDIC_rec */ | |
| 1028, | |
| /* ADDIS */ | |
| 1031, | |
| /* ADDIS8 */ | |
| 1034, | |
| /* ADDISdtprelHA */ | |
| 1037, | |
| /* ADDISdtprelHA32 */ | |
| 1040, | |
| /* ADDISgotTprelHA */ | |
| 1043, | |
| /* ADDIStlsgdHA */ | |
| 1046, | |
| /* ADDIStlsldHA */ | |
| 1049, | |
| /* ADDIStocHA */ | |
| 1052, | |
| /* ADDIStocHA8 */ | |
| 1055, | |
| /* ADDIdtprelL */ | |
| 1058, | |
| /* ADDIdtprelL32 */ | |
| 1061, | |
| /* ADDItlsgdL */ | |
| 1064, | |
| /* ADDItlsgdL32 */ | |
| 1067, | |
| /* ADDItlsgdLADDR */ | |
| 1070, | |
| /* ADDItlsgdLADDR32 */ | |
| 1074, | |
| /* ADDItlsldL */ | |
| 1078, | |
| /* ADDItlsldL32 */ | |
| 1081, | |
| /* ADDItlsldLADDR */ | |
| 1084, | |
| /* ADDItlsldLADDR32 */ | |
| 1088, | |
| /* ADDItoc */ | |
| 1092, | |
| /* ADDItoc8 */ | |
| 1095, | |
| /* ADDItocL */ | |
| 1098, | |
| /* ADDME */ | |
| 1101, | |
| /* ADDME8 */ | |
| 1103, | |
| /* ADDME8O */ | |
| 1105, | |
| /* ADDME8O_rec */ | |
| 1107, | |
| /* ADDME8_rec */ | |
| 1109, | |
| /* ADDMEO */ | |
| 1111, | |
| /* ADDMEO_rec */ | |
| 1113, | |
| /* ADDME_rec */ | |
| 1115, | |
| /* ADDPCIS */ | |
| 1117, | |
| /* ADDZE */ | |
| 1119, | |
| /* ADDZE8 */ | |
| 1121, | |
| /* ADDZE8O */ | |
| 1123, | |
| /* ADDZE8O_rec */ | |
| 1125, | |
| /* ADDZE8_rec */ | |
| 1127, | |
| /* ADDZEO */ | |
| 1129, | |
| /* ADDZEO_rec */ | |
| 1131, | |
| /* ADDZE_rec */ | |
| 1133, | |
| /* ADJCALLSTACKDOWN */ | |
| 1135, | |
| /* ADJCALLSTACKUP */ | |
| 1137, | |
| /* AND */ | |
| 1139, | |
| /* AND8 */ | |
| 1142, | |
| /* AND8_rec */ | |
| 1145, | |
| /* ANDC */ | |
| 1148, | |
| /* ANDC8 */ | |
| 1151, | |
| /* ANDC8_rec */ | |
| 1154, | |
| /* ANDC_rec */ | |
| 1157, | |
| /* ANDI8_rec */ | |
| 1160, | |
| /* ANDIS8_rec */ | |
| 1163, | |
| /* ANDIS_rec */ | |
| 1166, | |
| /* ANDI_rec */ | |
| 1169, | |
| /* ANDI_rec_1_EQ_BIT */ | |
| 1172, | |
| /* ANDI_rec_1_EQ_BIT8 */ | |
| 1174, | |
| /* ANDI_rec_1_GT_BIT */ | |
| 1176, | |
| /* ANDI_rec_1_GT_BIT8 */ | |
| 1178, | |
| /* AND_rec */ | |
| 1180, | |
| /* ATOMIC_CMP_SWAP_I16 */ | |
| 1183, | |
| /* ATOMIC_CMP_SWAP_I32 */ | |
| 1188, | |
| /* ATOMIC_CMP_SWAP_I64 */ | |
| 1193, | |
| /* ATOMIC_CMP_SWAP_I8 */ | |
| 1198, | |
| /* ATOMIC_LOAD_ADD_I16 */ | |
| 1203, | |
| /* ATOMIC_LOAD_ADD_I32 */ | |
| 1207, | |
| /* ATOMIC_LOAD_ADD_I64 */ | |
| 1211, | |
| /* ATOMIC_LOAD_ADD_I8 */ | |
| 1215, | |
| /* ATOMIC_LOAD_AND_I16 */ | |
| 1219, | |
| /* ATOMIC_LOAD_AND_I32 */ | |
| 1223, | |
| /* ATOMIC_LOAD_AND_I64 */ | |
| 1227, | |
| /* ATOMIC_LOAD_AND_I8 */ | |
| 1231, | |
| /* ATOMIC_LOAD_MAX_I16 */ | |
| 1235, | |
| /* ATOMIC_LOAD_MAX_I32 */ | |
| 1239, | |
| /* ATOMIC_LOAD_MAX_I64 */ | |
| 1243, | |
| /* ATOMIC_LOAD_MAX_I8 */ | |
| 1247, | |
| /* ATOMIC_LOAD_MIN_I16 */ | |
| 1251, | |
| /* ATOMIC_LOAD_MIN_I32 */ | |
| 1255, | |
| /* ATOMIC_LOAD_MIN_I64 */ | |
| 1259, | |
| /* ATOMIC_LOAD_MIN_I8 */ | |
| 1263, | |
| /* ATOMIC_LOAD_NAND_I16 */ | |
| 1267, | |
| /* ATOMIC_LOAD_NAND_I32 */ | |
| 1271, | |
| /* ATOMIC_LOAD_NAND_I64 */ | |
| 1275, | |
| /* ATOMIC_LOAD_NAND_I8 */ | |
| 1279, | |
| /* ATOMIC_LOAD_OR_I16 */ | |
| 1283, | |
| /* ATOMIC_LOAD_OR_I32 */ | |
| 1287, | |
| /* ATOMIC_LOAD_OR_I64 */ | |
| 1291, | |
| /* ATOMIC_LOAD_OR_I8 */ | |
| 1295, | |
| /* ATOMIC_LOAD_SUB_I16 */ | |
| 1299, | |
| /* ATOMIC_LOAD_SUB_I32 */ | |
| 1303, | |
| /* ATOMIC_LOAD_SUB_I64 */ | |
| 1307, | |
| /* ATOMIC_LOAD_SUB_I8 */ | |
| 1311, | |
| /* ATOMIC_LOAD_UMAX_I16 */ | |
| 1315, | |
| /* ATOMIC_LOAD_UMAX_I32 */ | |
| 1319, | |
| /* ATOMIC_LOAD_UMAX_I64 */ | |
| 1323, | |
| /* ATOMIC_LOAD_UMAX_I8 */ | |
| 1327, | |
| /* ATOMIC_LOAD_UMIN_I16 */ | |
| 1331, | |
| /* ATOMIC_LOAD_UMIN_I32 */ | |
| 1335, | |
| /* ATOMIC_LOAD_UMIN_I64 */ | |
| 1339, | |
| /* ATOMIC_LOAD_UMIN_I8 */ | |
| 1343, | |
| /* ATOMIC_LOAD_XOR_I16 */ | |
| 1347, | |
| /* ATOMIC_LOAD_XOR_I32 */ | |
| 1351, | |
| /* ATOMIC_LOAD_XOR_I64 */ | |
| 1355, | |
| /* ATOMIC_LOAD_XOR_I8 */ | |
| 1359, | |
| /* ATOMIC_SWAP_I16 */ | |
| 1363, | |
| /* ATOMIC_SWAP_I32 */ | |
| 1367, | |
| /* ATOMIC_SWAP_I64 */ | |
| 1371, | |
| /* ATOMIC_SWAP_I8 */ | |
| 1375, | |
| /* ATTN */ | |
| 1379, | |
| /* B */ | |
| 1379, | |
| /* BA */ | |
| 1380, | |
| /* BC */ | |
| 1381, | |
| /* BCC */ | |
| 1383, | |
| /* BCCA */ | |
| 1386, | |
| /* BCCCTR */ | |
| 1389, | |
| /* BCCCTR8 */ | |
| 1391, | |
| /* BCCCTRL */ | |
| 1393, | |
| /* BCCCTRL8 */ | |
| 1395, | |
| /* BCCL */ | |
| 1397, | |
| /* BCCLA */ | |
| 1400, | |
| /* BCCLR */ | |
| 1403, | |
| /* BCCLRL */ | |
| 1405, | |
| /* BCCTR */ | |
| 1407, | |
| /* BCCTR8 */ | |
| 1408, | |
| /* BCCTR8n */ | |
| 1409, | |
| /* BCCTRL */ | |
| 1410, | |
| /* BCCTRL8 */ | |
| 1411, | |
| /* BCCTRL8n */ | |
| 1412, | |
| /* BCCTRLn */ | |
| 1413, | |
| /* BCCTRn */ | |
| 1414, | |
| /* BCDADD_rec */ | |
| 1415, | |
| /* BCDCFN_rec */ | |
| 1419, | |
| /* BCDCFSQ_rec */ | |
| 1422, | |
| /* BCDCFZ_rec */ | |
| 1425, | |
| /* BCDCPSGN_rec */ | |
| 1428, | |
| /* BCDCTN_rec */ | |
| 1431, | |
| /* BCDCTSQ_rec */ | |
| 1433, | |
| /* BCDCTZ_rec */ | |
| 1435, | |
| /* BCDSETSGN_rec */ | |
| 1438, | |
| /* BCDSR_rec */ | |
| 1441, | |
| /* BCDSUB_rec */ | |
| 1445, | |
| /* BCDS_rec */ | |
| 1449, | |
| /* BCDTRUNC_rec */ | |
| 1453, | |
| /* BCDUS_rec */ | |
| 1457, | |
| /* BCDUTRUNC_rec */ | |
| 1460, | |
| /* BCL */ | |
| 1463, | |
| /* BCLR */ | |
| 1465, | |
| /* BCLRL */ | |
| 1466, | |
| /* BCLRLn */ | |
| 1467, | |
| /* BCLRn */ | |
| 1468, | |
| /* BCLalways */ | |
| 1469, | |
| /* BCLn */ | |
| 1470, | |
| /* BCTR */ | |
| 1472, | |
| /* BCTR8 */ | |
| 1472, | |
| /* BCTRL */ | |
| 1472, | |
| /* BCTRL8 */ | |
| 1472, | |
| /* BCTRL8_LDinto_toc */ | |
| 1472, | |
| /* BCTRL8_LDinto_toc_RM */ | |
| 1474, | |
| /* BCTRL8_RM */ | |
| 1476, | |
| /* BCTRL_LWZinto_toc */ | |
| 1476, | |
| /* BCTRL_LWZinto_toc_RM */ | |
| 1478, | |
| /* BCTRL_RM */ | |
| 1480, | |
| /* BCn */ | |
| 1480, | |
| /* BDNZ */ | |
| 1482, | |
| /* BDNZ8 */ | |
| 1483, | |
| /* BDNZA */ | |
| 1484, | |
| /* BDNZAm */ | |
| 1485, | |
| /* BDNZAp */ | |
| 1486, | |
| /* BDNZL */ | |
| 1487, | |
| /* BDNZLA */ | |
| 1488, | |
| /* BDNZLAm */ | |
| 1489, | |
| /* BDNZLAp */ | |
| 1490, | |
| /* BDNZLR */ | |
| 1491, | |
| /* BDNZLR8 */ | |
| 1491, | |
| /* BDNZLRL */ | |
| 1491, | |
| /* BDNZLRLm */ | |
| 1491, | |
| /* BDNZLRLp */ | |
| 1491, | |
| /* BDNZLRm */ | |
| 1491, | |
| /* BDNZLRp */ | |
| 1491, | |
| /* BDNZLm */ | |
| 1491, | |
| /* BDNZLp */ | |
| 1492, | |
| /* BDNZm */ | |
| 1493, | |
| /* BDNZp */ | |
| 1494, | |
| /* BDZ */ | |
| 1495, | |
| /* BDZ8 */ | |
| 1496, | |
| /* BDZA */ | |
| 1497, | |
| /* BDZAm */ | |
| 1498, | |
| /* BDZAp */ | |
| 1499, | |
| /* BDZL */ | |
| 1500, | |
| /* BDZLA */ | |
| 1501, | |
| /* BDZLAm */ | |
| 1502, | |
| /* BDZLAp */ | |
| 1503, | |
| /* BDZLR */ | |
| 1504, | |
| /* BDZLR8 */ | |
| 1504, | |
| /* BDZLRL */ | |
| 1504, | |
| /* BDZLRLm */ | |
| 1504, | |
| /* BDZLRLp */ | |
| 1504, | |
| /* BDZLRm */ | |
| 1504, | |
| /* BDZLRp */ | |
| 1504, | |
| /* BDZLm */ | |
| 1504, | |
| /* BDZLp */ | |
| 1505, | |
| /* BDZm */ | |
| 1506, | |
| /* BDZp */ | |
| 1507, | |
| /* BL */ | |
| 1508, | |
| /* BL8 */ | |
| 1509, | |
| /* BL8_NOP */ | |
| 1510, | |
| /* BL8_NOP_RM */ | |
| 1511, | |
| /* BL8_NOP_TLS */ | |
| 1512, | |
| /* BL8_NOTOC */ | |
| 1514, | |
| /* BL8_NOTOC_RM */ | |
| 1515, | |
| /* BL8_NOTOC_TLS */ | |
| 1516, | |
| /* BL8_RM */ | |
| 1518, | |
| /* BL8_TLS */ | |
| 1519, | |
| /* BL8_TLS_ */ | |
| 1521, | |
| /* BLA */ | |
| 1523, | |
| /* BLA8 */ | |
| 1524, | |
| /* BLA8_NOP */ | |
| 1525, | |
| /* BLA8_NOP_RM */ | |
| 1526, | |
| /* BLA8_RM */ | |
| 1527, | |
| /* BLA_RM */ | |
| 1528, | |
| /* BLR */ | |
| 1529, | |
| /* BLR8 */ | |
| 1529, | |
| /* BLRL */ | |
| 1529, | |
| /* BL_NOP */ | |
| 1529, | |
| /* BL_NOP_RM */ | |
| 1530, | |
| /* BL_RM */ | |
| 1531, | |
| /* BL_TLS */ | |
| 1532, | |
| /* BPERMD */ | |
| 1534, | |
| /* BRD */ | |
| 1537, | |
| /* BRH */ | |
| 1539, | |
| /* BRH8 */ | |
| 1541, | |
| /* BRINC */ | |
| 1543, | |
| /* BRW */ | |
| 1546, | |
| /* BRW8 */ | |
| 1548, | |
| /* CFUGED */ | |
| 1550, | |
| /* CLRBHRB */ | |
| 1553, | |
| /* CMPB */ | |
| 1553, | |
| /* CMPB8 */ | |
| 1556, | |
| /* CMPD */ | |
| 1559, | |
| /* CMPDI */ | |
| 1562, | |
| /* CMPEQB */ | |
| 1565, | |
| /* CMPLD */ | |
| 1568, | |
| /* CMPLDI */ | |
| 1571, | |
| /* CMPLW */ | |
| 1574, | |
| /* CMPLWI */ | |
| 1577, | |
| /* CMPRB */ | |
| 1580, | |
| /* CMPRB8 */ | |
| 1584, | |
| /* CMPW */ | |
| 1588, | |
| /* CMPWI */ | |
| 1591, | |
| /* CNTLZD */ | |
| 1594, | |
| /* CNTLZDM */ | |
| 1596, | |
| /* CNTLZD_rec */ | |
| 1599, | |
| /* CNTLZW */ | |
| 1601, | |
| /* CNTLZW8 */ | |
| 1603, | |
| /* CNTLZW8_rec */ | |
| 1605, | |
| /* CNTLZW_rec */ | |
| 1607, | |
| /* CNTTZD */ | |
| 1609, | |
| /* CNTTZDM */ | |
| 1611, | |
| /* CNTTZD_rec */ | |
| 1614, | |
| /* CNTTZW */ | |
| 1616, | |
| /* CNTTZW8 */ | |
| 1618, | |
| /* CNTTZW8_rec */ | |
| 1620, | |
| /* CNTTZW_rec */ | |
| 1622, | |
| /* CP_ABORT */ | |
| 1624, | |
| /* CP_COPY */ | |
| 1624, | |
| /* CP_COPY8 */ | |
| 1627, | |
| /* CP_PASTE8_rec */ | |
| 1630, | |
| /* CP_PASTE_rec */ | |
| 1633, | |
| /* CR6SET */ | |
| 1636, | |
| /* CR6UNSET */ | |
| 1636, | |
| /* CRAND */ | |
| 1636, | |
| /* CRANDC */ | |
| 1639, | |
| /* CREQV */ | |
| 1642, | |
| /* CRNAND */ | |
| 1645, | |
| /* CRNOR */ | |
| 1648, | |
| /* CRNOT */ | |
| 1651, | |
| /* CROR */ | |
| 1653, | |
| /* CRORC */ | |
| 1656, | |
| /* CRSET */ | |
| 1659, | |
| /* CRUNSET */ | |
| 1660, | |
| /* CRXOR */ | |
| 1661, | |
| /* CTRL_DEP */ | |
| 1664, | |
| /* DARN */ | |
| 1667, | |
| /* DCBA */ | |
| 1669, | |
| /* DCBF */ | |
| 1671, | |
| /* DCBFEP */ | |
| 1674, | |
| /* DCBI */ | |
| 1676, | |
| /* DCBST */ | |
| 1678, | |
| /* DCBSTEP */ | |
| 1680, | |
| /* DCBT */ | |
| 1682, | |
| /* DCBTEP */ | |
| 1685, | |
| /* DCBTST */ | |
| 1688, | |
| /* DCBTSTEP */ | |
| 1691, | |
| /* DCBZ */ | |
| 1694, | |
| /* DCBZEP */ | |
| 1696, | |
| /* DCBZL */ | |
| 1698, | |
| /* DCBZLEP */ | |
| 1700, | |
| /* DCCCI */ | |
| 1702, | |
| /* DIVD */ | |
| 1704, | |
| /* DIVDE */ | |
| 1707, | |
| /* DIVDEO */ | |
| 1710, | |
| /* DIVDEO_rec */ | |
| 1713, | |
| /* DIVDEU */ | |
| 1716, | |
| /* DIVDEUO */ | |
| 1719, | |
| /* DIVDEUO_rec */ | |
| 1722, | |
| /* DIVDEU_rec */ | |
| 1725, | |
| /* DIVDE_rec */ | |
| 1728, | |
| /* DIVDO */ | |
| 1731, | |
| /* DIVDO_rec */ | |
| 1734, | |
| /* DIVDU */ | |
| 1737, | |
| /* DIVDUO */ | |
| 1740, | |
| /* DIVDUO_rec */ | |
| 1743, | |
| /* DIVDU_rec */ | |
| 1746, | |
| /* DIVD_rec */ | |
| 1749, | |
| /* DIVW */ | |
| 1752, | |
| /* DIVWE */ | |
| 1755, | |
| /* DIVWEO */ | |
| 1758, | |
| /* DIVWEO_rec */ | |
| 1761, | |
| /* DIVWEU */ | |
| 1764, | |
| /* DIVWEUO */ | |
| 1767, | |
| /* DIVWEUO_rec */ | |
| 1770, | |
| /* DIVWEU_rec */ | |
| 1773, | |
| /* DIVWE_rec */ | |
| 1776, | |
| /* DIVWO */ | |
| 1779, | |
| /* DIVWO_rec */ | |
| 1782, | |
| /* DIVWU */ | |
| 1785, | |
| /* DIVWUO */ | |
| 1788, | |
| /* DIVWUO_rec */ | |
| 1791, | |
| /* DIVWU_rec */ | |
| 1794, | |
| /* DIVW_rec */ | |
| 1797, | |
| /* DMMR */ | |
| 1800, | |
| /* DMSETDMRZ */ | |
| 1802, | |
| /* DMXOR */ | |
| 1803, | |
| /* DMXXEXTFDMR256 */ | |
| 1806, | |
| /* DMXXEXTFDMR512 */ | |
| 1809, | |
| /* DMXXEXTFDMR512_HI */ | |
| 1812, | |
| /* DMXXINSTFDMR256 */ | |
| 1815, | |
| /* DMXXINSTFDMR512 */ | |
| 1818, | |
| /* DMXXINSTFDMR512_HI */ | |
| 1821, | |
| /* DSS */ | |
| 1824, | |
| /* DSSALL */ | |
| 1825, | |
| /* DST */ | |
| 1825, | |
| /* DST64 */ | |
| 1828, | |
| /* DSTST */ | |
| 1831, | |
| /* DSTST64 */ | |
| 1834, | |
| /* DSTSTT */ | |
| 1837, | |
| /* DSTSTT64 */ | |
| 1840, | |
| /* DSTT */ | |
| 1843, | |
| /* DSTT64 */ | |
| 1846, | |
| /* DYNALLOC */ | |
| 1849, | |
| /* DYNALLOC8 */ | |
| 1853, | |
| /* DYNAREAOFFSET */ | |
| 1857, | |
| /* DYNAREAOFFSET8 */ | |
| 1860, | |
| /* DecreaseCTR8loop */ | |
| 1863, | |
| /* DecreaseCTRloop */ | |
| 1865, | |
| /* EFDABS */ | |
| 1867, | |
| /* EFDADD */ | |
| 1869, | |
| /* EFDCFS */ | |
| 1872, | |
| /* EFDCFSF */ | |
| 1874, | |
| /* EFDCFSI */ | |
| 1876, | |
| /* EFDCFSID */ | |
| 1878, | |
| /* EFDCFUF */ | |
| 1880, | |
| /* EFDCFUI */ | |
| 1882, | |
| /* EFDCFUID */ | |
| 1884, | |
| /* EFDCMPEQ */ | |
| 1886, | |
| /* EFDCMPGT */ | |
| 1889, | |
| /* EFDCMPLT */ | |
| 1892, | |
| /* EFDCTSF */ | |
| 1895, | |
| /* EFDCTSI */ | |
| 1897, | |
| /* EFDCTSIDZ */ | |
| 1899, | |
| /* EFDCTSIZ */ | |
| 1901, | |
| /* EFDCTUF */ | |
| 1903, | |
| /* EFDCTUI */ | |
| 1905, | |
| /* EFDCTUIDZ */ | |
| 1907, | |
| /* EFDCTUIZ */ | |
| 1909, | |
| /* EFDDIV */ | |
| 1911, | |
| /* EFDMUL */ | |
| 1914, | |
| /* EFDNABS */ | |
| 1917, | |
| /* EFDNEG */ | |
| 1919, | |
| /* EFDSUB */ | |
| 1921, | |
| /* EFDTSTEQ */ | |
| 1924, | |
| /* EFDTSTGT */ | |
| 1927, | |
| /* EFDTSTLT */ | |
| 1930, | |
| /* EFSABS */ | |
| 1933, | |
| /* EFSADD */ | |
| 1935, | |
| /* EFSCFD */ | |
| 1938, | |
| /* EFSCFSF */ | |
| 1940, | |
| /* EFSCFSI */ | |
| 1942, | |
| /* EFSCFUF */ | |
| 1944, | |
| /* EFSCFUI */ | |
| 1946, | |
| /* EFSCMPEQ */ | |
| 1948, | |
| /* EFSCMPGT */ | |
| 1951, | |
| /* EFSCMPLT */ | |
| 1954, | |
| /* EFSCTSF */ | |
| 1957, | |
| /* EFSCTSI */ | |
| 1959, | |
| /* EFSCTSIZ */ | |
| 1961, | |
| /* EFSCTUF */ | |
| 1963, | |
| /* EFSCTUI */ | |
| 1965, | |
| /* EFSCTUIZ */ | |
| 1967, | |
| /* EFSDIV */ | |
| 1969, | |
| /* EFSMUL */ | |
| 1972, | |
| /* EFSNABS */ | |
| 1975, | |
| /* EFSNEG */ | |
| 1977, | |
| /* EFSSUB */ | |
| 1979, | |
| /* EFSTSTEQ */ | |
| 1982, | |
| /* EFSTSTGT */ | |
| 1985, | |
| /* EFSTSTLT */ | |
| 1988, | |
| /* EH_SjLj_LongJmp32 */ | |
| 1991, | |
| /* EH_SjLj_LongJmp64 */ | |
| 1992, | |
| /* EH_SjLj_SetJmp32 */ | |
| 1993, | |
| /* EH_SjLj_SetJmp64 */ | |
| 1995, | |
| /* EH_SjLj_Setup */ | |
| 1997, | |
| /* EQV */ | |
| 1998, | |
| /* EQV8 */ | |
| 2001, | |
| /* EQV8_rec */ | |
| 2004, | |
| /* EQV_rec */ | |
| 2007, | |
| /* EVABS */ | |
| 2010, | |
| /* EVADDIW */ | |
| 2012, | |
| /* EVADDSMIAAW */ | |
| 2015, | |
| /* EVADDSSIAAW */ | |
| 2017, | |
| /* EVADDUMIAAW */ | |
| 2019, | |
| /* EVADDUSIAAW */ | |
| 2021, | |
| /* EVADDW */ | |
| 2023, | |
| /* EVAND */ | |
| 2026, | |
| /* EVANDC */ | |
| 2029, | |
| /* EVCMPEQ */ | |
| 2032, | |
| /* EVCMPGTS */ | |
| 2035, | |
| /* EVCMPGTU */ | |
| 2038, | |
| /* EVCMPLTS */ | |
| 2041, | |
| /* EVCMPLTU */ | |
| 2044, | |
| /* EVCNTLSW */ | |
| 2047, | |
| /* EVCNTLZW */ | |
| 2049, | |
| /* EVDIVWS */ | |
| 2051, | |
| /* EVDIVWU */ | |
| 2054, | |
| /* EVEQV */ | |
| 2057, | |
| /* EVEXTSB */ | |
| 2060, | |
| /* EVEXTSH */ | |
| 2062, | |
| /* EVFSABS */ | |
| 2064, | |
| /* EVFSADD */ | |
| 2066, | |
| /* EVFSCFSF */ | |
| 2069, | |
| /* EVFSCFSI */ | |
| 2071, | |
| /* EVFSCFUF */ | |
| 2073, | |
| /* EVFSCFUI */ | |
| 2075, | |
| /* EVFSCMPEQ */ | |
| 2077, | |
| /* EVFSCMPGT */ | |
| 2080, | |
| /* EVFSCMPLT */ | |
| 2083, | |
| /* EVFSCTSF */ | |
| 2086, | |
| /* EVFSCTSI */ | |
| 2088, | |
| /* EVFSCTSIZ */ | |
| 2090, | |
| /* EVFSCTUF */ | |
| 2092, | |
| /* EVFSCTUI */ | |
| 2094, | |
| /* EVFSCTUIZ */ | |
| 2096, | |
| /* EVFSDIV */ | |
| 2098, | |
| /* EVFSMUL */ | |
| 2101, | |
| /* EVFSNABS */ | |
| 2104, | |
| /* EVFSNEG */ | |
| 2106, | |
| /* EVFSSUB */ | |
| 2108, | |
| /* EVFSTSTEQ */ | |
| 2111, | |
| /* EVFSTSTGT */ | |
| 2114, | |
| /* EVFSTSTLT */ | |
| 2117, | |
| /* EVLDD */ | |
| 2120, | |
| /* EVLDDX */ | |
| 2123, | |
| /* EVLDH */ | |
| 2126, | |
| /* EVLDHX */ | |
| 2129, | |
| /* EVLDW */ | |
| 2132, | |
| /* EVLDWX */ | |
| 2135, | |
| /* EVLHHESPLAT */ | |
| 2138, | |
| /* EVLHHESPLATX */ | |
| 2141, | |
| /* EVLHHOSSPLAT */ | |
| 2144, | |
| /* EVLHHOSSPLATX */ | |
| 2147, | |
| /* EVLHHOUSPLAT */ | |
| 2150, | |
| /* EVLHHOUSPLATX */ | |
| 2153, | |
| /* EVLWHE */ | |
| 2156, | |
| /* EVLWHEX */ | |
| 2159, | |
| /* EVLWHOS */ | |
| 2162, | |
| /* EVLWHOSX */ | |
| 2165, | |
| /* EVLWHOU */ | |
| 2168, | |
| /* EVLWHOUX */ | |
| 2171, | |
| /* EVLWHSPLAT */ | |
| 2174, | |
| /* EVLWHSPLATX */ | |
| 2177, | |
| /* EVLWWSPLAT */ | |
| 2180, | |
| /* EVLWWSPLATX */ | |
| 2183, | |
| /* EVMERGEHI */ | |
| 2186, | |
| /* EVMERGEHILO */ | |
| 2189, | |
| /* EVMERGELO */ | |
| 2192, | |
| /* EVMERGELOHI */ | |
| 2195, | |
| /* EVMHEGSMFAA */ | |
| 2198, | |
| /* EVMHEGSMFAN */ | |
| 2201, | |
| /* EVMHEGSMIAA */ | |
| 2204, | |
| /* EVMHEGSMIAN */ | |
| 2207, | |
| /* EVMHEGUMIAA */ | |
| 2210, | |
| /* EVMHEGUMIAN */ | |
| 2213, | |
| /* EVMHESMF */ | |
| 2216, | |
| /* EVMHESMFA */ | |
| 2219, | |
| /* EVMHESMFAAW */ | |
| 2222, | |
| /* EVMHESMFANW */ | |
| 2225, | |
| /* EVMHESMI */ | |
| 2228, | |
| /* EVMHESMIA */ | |
| 2231, | |
| /* EVMHESMIAAW */ | |
| 2234, | |
| /* EVMHESMIANW */ | |
| 2237, | |
| /* EVMHESSF */ | |
| 2240, | |
| /* EVMHESSFA */ | |
| 2243, | |
| /* EVMHESSFAAW */ | |
| 2246, | |
| /* EVMHESSFANW */ | |
| 2249, | |
| /* EVMHESSIAAW */ | |
| 2252, | |
| /* EVMHESSIANW */ | |
| 2255, | |
| /* EVMHEUMI */ | |
| 2258, | |
| /* EVMHEUMIA */ | |
| 2261, | |
| /* EVMHEUMIAAW */ | |
| 2264, | |
| /* EVMHEUMIANW */ | |
| 2267, | |
| /* EVMHEUSIAAW */ | |
| 2270, | |
| /* EVMHEUSIANW */ | |
| 2273, | |
| /* EVMHOGSMFAA */ | |
| 2276, | |
| /* EVMHOGSMFAN */ | |
| 2279, | |
| /* EVMHOGSMIAA */ | |
| 2282, | |
| /* EVMHOGSMIAN */ | |
| 2285, | |
| /* EVMHOGUMIAA */ | |
| 2288, | |
| /* EVMHOGUMIAN */ | |
| 2291, | |
| /* EVMHOSMF */ | |
| 2294, | |
| /* EVMHOSMFA */ | |
| 2297, | |
| /* EVMHOSMFAAW */ | |
| 2300, | |
| /* EVMHOSMFANW */ | |
| 2303, | |
| /* EVMHOSMI */ | |
| 2306, | |
| /* EVMHOSMIA */ | |
| 2309, | |
| /* EVMHOSMIAAW */ | |
| 2312, | |
| /* EVMHOSMIANW */ | |
| 2315, | |
| /* EVMHOSSF */ | |
| 2318, | |
| /* EVMHOSSFA */ | |
| 2321, | |
| /* EVMHOSSFAAW */ | |
| 2324, | |
| /* EVMHOSSFANW */ | |
| 2327, | |
| /* EVMHOSSIAAW */ | |
| 2330, | |
| /* EVMHOSSIANW */ | |
| 2333, | |
| /* EVMHOUMI */ | |
| 2336, | |
| /* EVMHOUMIA */ | |
| 2339, | |
| /* EVMHOUMIAAW */ | |
| 2342, | |
| /* EVMHOUMIANW */ | |
| 2345, | |
| /* EVMHOUSIAAW */ | |
| 2348, | |
| /* EVMHOUSIANW */ | |
| 2351, | |
| /* EVMRA */ | |
| 2354, | |
| /* EVMWHSMF */ | |
| 2356, | |
| /* EVMWHSMFA */ | |
| 2359, | |
| /* EVMWHSMI */ | |
| 2362, | |
| /* EVMWHSMIA */ | |
| 2365, | |
| /* EVMWHSSF */ | |
| 2368, | |
| /* EVMWHSSFA */ | |
| 2371, | |
| /* EVMWHUMI */ | |
| 2374, | |
| /* EVMWHUMIA */ | |
| 2377, | |
| /* EVMWLSMIAAW */ | |
| 2380, | |
| /* EVMWLSMIANW */ | |
| 2383, | |
| /* EVMWLSSIAAW */ | |
| 2386, | |
| /* EVMWLSSIANW */ | |
| 2389, | |
| /* EVMWLUMI */ | |
| 2392, | |
| /* EVMWLUMIA */ | |
| 2395, | |
| /* EVMWLUMIAAW */ | |
| 2398, | |
| /* EVMWLUMIANW */ | |
| 2401, | |
| /* EVMWLUSIAAW */ | |
| 2404, | |
| /* EVMWLUSIANW */ | |
| 2407, | |
| /* EVMWSMF */ | |
| 2410, | |
| /* EVMWSMFA */ | |
| 2413, | |
| /* EVMWSMFAA */ | |
| 2416, | |
| /* EVMWSMFAN */ | |
| 2419, | |
| /* EVMWSMI */ | |
| 2422, | |
| /* EVMWSMIA */ | |
| 2425, | |
| /* EVMWSMIAA */ | |
| 2428, | |
| /* EVMWSMIAN */ | |
| 2431, | |
| /* EVMWSSF */ | |
| 2434, | |
| /* EVMWSSFA */ | |
| 2437, | |
| /* EVMWSSFAA */ | |
| 2440, | |
| /* EVMWSSFAN */ | |
| 2443, | |
| /* EVMWUMI */ | |
| 2446, | |
| /* EVMWUMIA */ | |
| 2449, | |
| /* EVMWUMIAA */ | |
| 2452, | |
| /* EVMWUMIAN */ | |
| 2455, | |
| /* EVNAND */ | |
| 2458, | |
| /* EVNEG */ | |
| 2461, | |
| /* EVNOR */ | |
| 2463, | |
| /* EVOR */ | |
| 2466, | |
| /* EVORC */ | |
| 2469, | |
| /* EVRLW */ | |
| 2472, | |
| /* EVRLWI */ | |
| 2475, | |
| /* EVRNDW */ | |
| 2478, | |
| /* EVSEL */ | |
| 2480, | |
| /* EVSLW */ | |
| 2484, | |
| /* EVSLWI */ | |
| 2487, | |
| /* EVSPLATFI */ | |
| 2490, | |
| /* EVSPLATI */ | |
| 2492, | |
| /* EVSRWIS */ | |
| 2494, | |
| /* EVSRWIU */ | |
| 2497, | |
| /* EVSRWS */ | |
| 2500, | |
| /* EVSRWU */ | |
| 2503, | |
| /* EVSTDD */ | |
| 2506, | |
| /* EVSTDDX */ | |
| 2509, | |
| /* EVSTDH */ | |
| 2512, | |
| /* EVSTDHX */ | |
| 2515, | |
| /* EVSTDW */ | |
| 2518, | |
| /* EVSTDWX */ | |
| 2521, | |
| /* EVSTWHE */ | |
| 2524, | |
| /* EVSTWHEX */ | |
| 2527, | |
| /* EVSTWHO */ | |
| 2530, | |
| /* EVSTWHOX */ | |
| 2533, | |
| /* EVSTWWE */ | |
| 2536, | |
| /* EVSTWWEX */ | |
| 2539, | |
| /* EVSTWWO */ | |
| 2542, | |
| /* EVSTWWOX */ | |
| 2545, | |
| /* EVSUBFSMIAAW */ | |
| 2548, | |
| /* EVSUBFSSIAAW */ | |
| 2550, | |
| /* EVSUBFUMIAAW */ | |
| 2552, | |
| /* EVSUBFUSIAAW */ | |
| 2554, | |
| /* EVSUBFW */ | |
| 2556, | |
| /* EVSUBIFW */ | |
| 2559, | |
| /* EVXOR */ | |
| 2562, | |
| /* EXTSB */ | |
| 2565, | |
| /* EXTSB8 */ | |
| 2567, | |
| /* EXTSB8_32_64 */ | |
| 2569, | |
| /* EXTSB8_rec */ | |
| 2571, | |
| /* EXTSB_rec */ | |
| 2573, | |
| /* EXTSH */ | |
| 2575, | |
| /* EXTSH8 */ | |
| 2577, | |
| /* EXTSH8_32_64 */ | |
| 2579, | |
| /* EXTSH8_rec */ | |
| 2581, | |
| /* EXTSH_rec */ | |
| 2583, | |
| /* EXTSW */ | |
| 2585, | |
| /* EXTSWSLI */ | |
| 2587, | |
| /* EXTSWSLI_32_64 */ | |
| 2590, | |
| /* EXTSWSLI_32_64_rec */ | |
| 2593, | |
| /* EXTSWSLI_rec */ | |
| 2596, | |
| /* EXTSW_32 */ | |
| 2599, | |
| /* EXTSW_32_64 */ | |
| 2601, | |
| /* EXTSW_32_64_rec */ | |
| 2603, | |
| /* EXTSW_rec */ | |
| 2605, | |
| /* EnforceIEIO */ | |
| 2607, | |
| /* FABSD */ | |
| 2607, | |
| /* FABSD_rec */ | |
| 2609, | |
| /* FABSS */ | |
| 2611, | |
| /* FABSS_rec */ | |
| 2613, | |
| /* FADD */ | |
| 2615, | |
| /* FADDS */ | |
| 2618, | |
| /* FADDS_rec */ | |
| 2621, | |
| /* FADD_rec */ | |
| 2624, | |
| /* FADDrtz */ | |
| 2627, | |
| /* FCFID */ | |
| 2630, | |
| /* FCFIDS */ | |
| 2632, | |
| /* FCFIDS_rec */ | |
| 2634, | |
| /* FCFIDU */ | |
| 2636, | |
| /* FCFIDUS */ | |
| 2638, | |
| /* FCFIDUS_rec */ | |
| 2640, | |
| /* FCFIDU_rec */ | |
| 2642, | |
| /* FCFID_rec */ | |
| 2644, | |
| /* FCMPOD */ | |
| 2646, | |
| /* FCMPOS */ | |
| 2649, | |
| /* FCMPUD */ | |
| 2652, | |
| /* FCMPUS */ | |
| 2655, | |
| /* FCPSGND */ | |
| 2658, | |
| /* FCPSGND_rec */ | |
| 2661, | |
| /* FCPSGNS */ | |
| 2664, | |
| /* FCPSGNS_rec */ | |
| 2667, | |
| /* FCTID */ | |
| 2670, | |
| /* FCTIDU */ | |
| 2672, | |
| /* FCTIDUZ */ | |
| 2674, | |
| /* FCTIDUZ_rec */ | |
| 2676, | |
| /* FCTIDU_rec */ | |
| 2678, | |
| /* FCTIDZ */ | |
| 2680, | |
| /* FCTIDZ_rec */ | |
| 2682, | |
| /* FCTID_rec */ | |
| 2684, | |
| /* FCTIW */ | |
| 2686, | |
| /* FCTIWU */ | |
| 2688, | |
| /* FCTIWUZ */ | |
| 2690, | |
| /* FCTIWUZ_rec */ | |
| 2692, | |
| /* FCTIWU_rec */ | |
| 2694, | |
| /* FCTIWZ */ | |
| 2696, | |
| /* FCTIWZ_rec */ | |
| 2698, | |
| /* FCTIW_rec */ | |
| 2700, | |
| /* FDIV */ | |
| 2702, | |
| /* FDIVS */ | |
| 2705, | |
| /* FDIVS_rec */ | |
| 2708, | |
| /* FDIV_rec */ | |
| 2711, | |
| /* FMADD */ | |
| 2714, | |
| /* FMADDS */ | |
| 2718, | |
| /* FMADDS_rec */ | |
| 2722, | |
| /* FMADD_rec */ | |
| 2726, | |
| /* FMR */ | |
| 2730, | |
| /* FMR_rec */ | |
| 2732, | |
| /* FMSUB */ | |
| 2734, | |
| /* FMSUBS */ | |
| 2738, | |
| /* FMSUBS_rec */ | |
| 2742, | |
| /* FMSUB_rec */ | |
| 2746, | |
| /* FMUL */ | |
| 2750, | |
| /* FMULS */ | |
| 2753, | |
| /* FMULS_rec */ | |
| 2756, | |
| /* FMUL_rec */ | |
| 2759, | |
| /* FNABSD */ | |
| 2762, | |
| /* FNABSD_rec */ | |
| 2764, | |
| /* FNABSS */ | |
| 2766, | |
| /* FNABSS_rec */ | |
| 2768, | |
| /* FNEGD */ | |
| 2770, | |
| /* FNEGD_rec */ | |
| 2772, | |
| /* FNEGS */ | |
| 2774, | |
| /* FNEGS_rec */ | |
| 2776, | |
| /* FNMADD */ | |
| 2778, | |
| /* FNMADDS */ | |
| 2782, | |
| /* FNMADDS_rec */ | |
| 2786, | |
| /* FNMADD_rec */ | |
| 2790, | |
| /* FNMSUB */ | |
| 2794, | |
| /* FNMSUBS */ | |
| 2798, | |
| /* FNMSUBS_rec */ | |
| 2802, | |
| /* FNMSUB_rec */ | |
| 2806, | |
| /* FRE */ | |
| 2810, | |
| /* FRES */ | |
| 2812, | |
| /* FRES_rec */ | |
| 2814, | |
| /* FRE_rec */ | |
| 2816, | |
| /* FRIMD */ | |
| 2818, | |
| /* FRIMD_rec */ | |
| 2820, | |
| /* FRIMS */ | |
| 2822, | |
| /* FRIMS_rec */ | |
| 2824, | |
| /* FRIND */ | |
| 2826, | |
| /* FRIND_rec */ | |
| 2828, | |
| /* FRINS */ | |
| 2830, | |
| /* FRINS_rec */ | |
| 2832, | |
| /* FRIPD */ | |
| 2834, | |
| /* FRIPD_rec */ | |
| 2836, | |
| /* FRIPS */ | |
| 2838, | |
| /* FRIPS_rec */ | |
| 2840, | |
| /* FRIZD */ | |
| 2842, | |
| /* FRIZD_rec */ | |
| 2844, | |
| /* FRIZS */ | |
| 2846, | |
| /* FRIZS_rec */ | |
| 2848, | |
| /* FRSP */ | |
| 2850, | |
| /* FRSP_rec */ | |
| 2852, | |
| /* FRSQRTE */ | |
| 2854, | |
| /* FRSQRTES */ | |
| 2856, | |
| /* FRSQRTES_rec */ | |
| 2858, | |
| /* FRSQRTE_rec */ | |
| 2860, | |
| /* FSELD */ | |
| 2862, | |
| /* FSELD_rec */ | |
| 2866, | |
| /* FSELS */ | |
| 2870, | |
| /* FSELS_rec */ | |
| 2874, | |
| /* FSQRT */ | |
| 2878, | |
| /* FSQRTS */ | |
| 2880, | |
| /* FSQRTS_rec */ | |
| 2882, | |
| /* FSQRT_rec */ | |
| 2884, | |
| /* FSUB */ | |
| 2886, | |
| /* FSUBS */ | |
| 2889, | |
| /* FSUBS_rec */ | |
| 2892, | |
| /* FSUB_rec */ | |
| 2895, | |
| /* FTDIV */ | |
| 2898, | |
| /* FTSQRT */ | |
| 2901, | |
| /* GETtlsADDR */ | |
| 2903, | |
| /* GETtlsADDR32 */ | |
| 2906, | |
| /* GETtlsADDR32AIX */ | |
| 2909, | |
| /* GETtlsADDR64AIX */ | |
| 2912, | |
| /* GETtlsADDRPCREL */ | |
| 2915, | |
| /* GETtlsldADDR */ | |
| 2918, | |
| /* GETtlsldADDR32 */ | |
| 2921, | |
| /* GETtlsldADDRPCREL */ | |
| 2924, | |
| /* HASHCHK */ | |
| 2927, | |
| /* HASHCHK8 */ | |
| 2930, | |
| /* HASHCHKP */ | |
| 2933, | |
| /* HASHCHKP8 */ | |
| 2936, | |
| /* HASHST */ | |
| 2939, | |
| /* HASHST8 */ | |
| 2942, | |
| /* HASHSTP */ | |
| 2945, | |
| /* HASHSTP8 */ | |
| 2948, | |
| /* HRFID */ | |
| 2951, | |
| /* ICBI */ | |
| 2951, | |
| /* ICBIEP */ | |
| 2953, | |
| /* ICBLC */ | |
| 2955, | |
| /* ICBLQ */ | |
| 2958, | |
| /* ICBT */ | |
| 2961, | |
| /* ICBTLS */ | |
| 2964, | |
| /* ICCCI */ | |
| 2967, | |
| /* ISEL */ | |
| 2969, | |
| /* ISEL8 */ | |
| 2973, | |
| /* ISYNC */ | |
| 2977, | |
| /* LA */ | |
| 2977, | |
| /* LA8 */ | |
| 2980, | |
| /* LBARX */ | |
| 2983, | |
| /* LBARXL */ | |
| 2986, | |
| /* LBEPX */ | |
| 2989, | |
| /* LBZ */ | |
| 2992, | |
| /* LBZ8 */ | |
| 2995, | |
| /* LBZCIX */ | |
| 2998, | |
| /* LBZU */ | |
| 3001, | |
| /* LBZU8 */ | |
| 3005, | |
| /* LBZUX */ | |
| 3009, | |
| /* LBZUX8 */ | |
| 3013, | |
| /* LBZX */ | |
| 3017, | |
| /* LBZX8 */ | |
| 3020, | |
| /* LBZXTLS */ | |
| 3023, | |
| /* LBZXTLS_ */ | |
| 3026, | |
| /* LBZXTLS_32 */ | |
| 3029, | |
| /* LD */ | |
| 3032, | |
| /* LDARX */ | |
| 3035, | |
| /* LDARXL */ | |
| 3038, | |
| /* LDAT */ | |
| 3041, | |
| /* LDBRX */ | |
| 3044, | |
| /* LDCIX */ | |
| 3047, | |
| /* LDU */ | |
| 3050, | |
| /* LDUX */ | |
| 3054, | |
| /* LDX */ | |
| 3058, | |
| /* LDXTLS */ | |
| 3061, | |
| /* LDXTLS_ */ | |
| 3064, | |
| /* LDgotTprelL */ | |
| 3067, | |
| /* LDgotTprelL32 */ | |
| 3070, | |
| /* LDtoc */ | |
| 3073, | |
| /* LDtocBA */ | |
| 3076, | |
| /* LDtocCPT */ | |
| 3079, | |
| /* LDtocJTI */ | |
| 3082, | |
| /* LDtocL */ | |
| 3085, | |
| /* LFD */ | |
| 3088, | |
| /* LFDEPX */ | |
| 3091, | |
| /* LFDU */ | |
| 3094, | |
| /* LFDUX */ | |
| 3098, | |
| /* LFDX */ | |
| 3102, | |
| /* LFIWAX */ | |
| 3105, | |
| /* LFIWZX */ | |
| 3108, | |
| /* LFS */ | |
| 3111, | |
| /* LFSU */ | |
| 3114, | |
| /* LFSUX */ | |
| 3118, | |
| /* LFSX */ | |
| 3122, | |
| /* LHA */ | |
| 3125, | |
| /* LHA8 */ | |
| 3128, | |
| /* LHARX */ | |
| 3131, | |
| /* LHARXL */ | |
| 3134, | |
| /* LHAU */ | |
| 3137, | |
| /* LHAU8 */ | |
| 3141, | |
| /* LHAUX */ | |
| 3145, | |
| /* LHAUX8 */ | |
| 3149, | |
| /* LHAX */ | |
| 3153, | |
| /* LHAX8 */ | |
| 3156, | |
| /* LHBRX */ | |
| 3159, | |
| /* LHBRX8 */ | |
| 3162, | |
| /* LHEPX */ | |
| 3165, | |
| /* LHZ */ | |
| 3168, | |
| /* LHZ8 */ | |
| 3171, | |
| /* LHZCIX */ | |
| 3174, | |
| /* LHZU */ | |
| 3177, | |
| /* LHZU8 */ | |
| 3181, | |
| /* LHZUX */ | |
| 3185, | |
| /* LHZUX8 */ | |
| 3189, | |
| /* LHZX */ | |
| 3193, | |
| /* LHZX8 */ | |
| 3196, | |
| /* LHZXTLS */ | |
| 3199, | |
| /* LHZXTLS_ */ | |
| 3202, | |
| /* LHZXTLS_32 */ | |
| 3205, | |
| /* LI */ | |
| 3208, | |
| /* LI8 */ | |
| 3210, | |
| /* LIS */ | |
| 3212, | |
| /* LIS8 */ | |
| 3214, | |
| /* LMW */ | |
| 3216, | |
| /* LQ */ | |
| 3219, | |
| /* LQARX */ | |
| 3222, | |
| /* LQARXL */ | |
| 3225, | |
| /* LQX_PSEUDO */ | |
| 3228, | |
| /* LSWI */ | |
| 3231, | |
| /* LVEBX */ | |
| 3234, | |
| /* LVEHX */ | |
| 3237, | |
| /* LVEWX */ | |
| 3240, | |
| /* LVSL */ | |
| 3243, | |
| /* LVSR */ | |
| 3246, | |
| /* LVX */ | |
| 3249, | |
| /* LVXL */ | |
| 3252, | |
| /* LWA */ | |
| 3255, | |
| /* LWARX */ | |
| 3258, | |
| /* LWARXL */ | |
| 3261, | |
| /* LWAT */ | |
| 3264, | |
| /* LWAUX */ | |
| 3267, | |
| /* LWAX */ | |
| 3271, | |
| /* LWAX_32 */ | |
| 3274, | |
| /* LWA_32 */ | |
| 3277, | |
| /* LWBRX */ | |
| 3280, | |
| /* LWBRX8 */ | |
| 3283, | |
| /* LWEPX */ | |
| 3286, | |
| /* LWZ */ | |
| 3289, | |
| /* LWZ8 */ | |
| 3292, | |
| /* LWZCIX */ | |
| 3295, | |
| /* LWZU */ | |
| 3298, | |
| /* LWZU8 */ | |
| 3302, | |
| /* LWZUX */ | |
| 3306, | |
| /* LWZUX8 */ | |
| 3310, | |
| /* LWZX */ | |
| 3314, | |
| /* LWZX8 */ | |
| 3317, | |
| /* LWZXTLS */ | |
| 3320, | |
| /* LWZXTLS_ */ | |
| 3323, | |
| /* LWZXTLS_32 */ | |
| 3326, | |
| /* LWZtoc */ | |
| 3329, | |
| /* LWZtocL */ | |
| 3332, | |
| /* LXSD */ | |
| 3335, | |
| /* LXSDX */ | |
| 3338, | |
| /* LXSIBZX */ | |
| 3341, | |
| /* LXSIHZX */ | |
| 3344, | |
| /* LXSIWAX */ | |
| 3347, | |
| /* LXSIWZX */ | |
| 3350, | |
| /* LXSSP */ | |
| 3353, | |
| /* LXSSPX */ | |
| 3356, | |
| /* LXV */ | |
| 3359, | |
| /* LXVB16X */ | |
| 3362, | |
| /* LXVD2X */ | |
| 3365, | |
| /* LXVDSX */ | |
| 3368, | |
| /* LXVH8X */ | |
| 3371, | |
| /* LXVKQ */ | |
| 3374, | |
| /* LXVL */ | |
| 3376, | |
| /* LXVLL */ | |
| 3379, | |
| /* LXVP */ | |
| 3382, | |
| /* LXVPRL */ | |
| 3385, | |
| /* LXVPRLL */ | |
| 3388, | |
| /* LXVPX */ | |
| 3391, | |
| /* LXVRBX */ | |
| 3394, | |
| /* LXVRDX */ | |
| 3397, | |
| /* LXVRHX */ | |
| 3400, | |
| /* LXVRL */ | |
| 3403, | |
| /* LXVRLL */ | |
| 3406, | |
| /* LXVRWX */ | |
| 3409, | |
| /* LXVW4X */ | |
| 3412, | |
| /* LXVWSX */ | |
| 3415, | |
| /* LXVX */ | |
| 3418, | |
| /* MADDHD */ | |
| 3421, | |
| /* MADDHDU */ | |
| 3425, | |
| /* MADDLD */ | |
| 3429, | |
| /* MADDLD8 */ | |
| 3433, | |
| /* MBAR */ | |
| 3437, | |
| /* MCRF */ | |
| 3438, | |
| /* MCRFS */ | |
| 3440, | |
| /* MCRXRX */ | |
| 3442, | |
| /* MFBHRBE */ | |
| 3443, | |
| /* MFCR */ | |
| 3446, | |
| /* MFCR8 */ | |
| 3447, | |
| /* MFCTR */ | |
| 3448, | |
| /* MFCTR8 */ | |
| 3449, | |
| /* MFDCR */ | |
| 3450, | |
| /* MFFS */ | |
| 3452, | |
| /* MFFSCDRN */ | |
| 3453, | |
| /* MFFSCDRNI */ | |
| 3455, | |
| /* MFFSCE */ | |
| 3457, | |
| /* MFFSCRN */ | |
| 3458, | |
| /* MFFSCRNI */ | |
| 3460, | |
| /* MFFSL */ | |
| 3462, | |
| /* MFFS_rec */ | |
| 3463, | |
| /* MFLR */ | |
| 3464, | |
| /* MFLR8 */ | |
| 3465, | |
| /* MFMSR */ | |
| 3466, | |
| /* MFOCRF */ | |
| 3467, | |
| /* MFOCRF8 */ | |
| 3469, | |
| /* MFPMR */ | |
| 3471, | |
| /* MFSPR */ | |
| 3473, | |
| /* MFSPR8 */ | |
| 3475, | |
| /* MFSR */ | |
| 3477, | |
| /* MFSRIN */ | |
| 3479, | |
| /* MFTB */ | |
| 3481, | |
| /* MFTB8 */ | |
| 3483, | |
| /* MFUDSCR */ | |
| 3484, | |
| /* MFVRD */ | |
| 3485, | |
| /* MFVRSAVE */ | |
| 3487, | |
| /* MFVRSAVEv */ | |
| 3488, | |
| /* MFVRWZ */ | |
| 3490, | |
| /* MFVSCR */ | |
| 3492, | |
| /* MFVSRD */ | |
| 3493, | |
| /* MFVSRLD */ | |
| 3495, | |
| /* MFVSRWZ */ | |
| 3497, | |
| /* MODSD */ | |
| 3499, | |
| /* MODSW */ | |
| 3502, | |
| /* MODUD */ | |
| 3505, | |
| /* MODUW */ | |
| 3508, | |
| /* MSGSYNC */ | |
| 3511, | |
| /* MSYNC */ | |
| 3511, | |
| /* MTCRF */ | |
| 3511, | |
| /* MTCRF8 */ | |
| 3513, | |
| /* MTCTR */ | |
| 3515, | |
| /* MTCTR8 */ | |
| 3516, | |
| /* MTCTR8loop */ | |
| 3517, | |
| /* MTCTRloop */ | |
| 3518, | |
| /* MTDCR */ | |
| 3519, | |
| /* MTFSB0 */ | |
| 3521, | |
| /* MTFSB1 */ | |
| 3522, | |
| /* MTFSF */ | |
| 3523, | |
| /* MTFSFI */ | |
| 3527, | |
| /* MTFSFI_rec */ | |
| 3530, | |
| /* MTFSFIb */ | |
| 3533, | |
| /* MTFSF_rec */ | |
| 3535, | |
| /* MTFSFb */ | |
| 3539, | |
| /* MTLR */ | |
| 3541, | |
| /* MTLR8 */ | |
| 3542, | |
| /* MTMSR */ | |
| 3543, | |
| /* MTMSRD */ | |
| 3545, | |
| /* MTOCRF */ | |
| 3547, | |
| /* MTOCRF8 */ | |
| 3549, | |
| /* MTPMR */ | |
| 3551, | |
| /* MTSPR */ | |
| 3553, | |
| /* MTSPR8 */ | |
| 3555, | |
| /* MTSR */ | |
| 3557, | |
| /* MTSRIN */ | |
| 3559, | |
| /* MTUDSCR */ | |
| 3561, | |
| /* MTVRD */ | |
| 3562, | |
| /* MTVRSAVE */ | |
| 3564, | |
| /* MTVRSAVEv */ | |
| 3565, | |
| /* MTVRWA */ | |
| 3567, | |
| /* MTVRWZ */ | |
| 3569, | |
| /* MTVSCR */ | |
| 3571, | |
| /* MTVSRBM */ | |
| 3572, | |
| /* MTVSRBMI */ | |
| 3574, | |
| /* MTVSRD */ | |
| 3576, | |
| /* MTVSRDD */ | |
| 3578, | |
| /* MTVSRDM */ | |
| 3581, | |
| /* MTVSRHM */ | |
| 3583, | |
| /* MTVSRQM */ | |
| 3585, | |
| /* MTVSRWA */ | |
| 3587, | |
| /* MTVSRWM */ | |
| 3589, | |
| /* MTVSRWS */ | |
| 3591, | |
| /* MTVSRWZ */ | |
| 3593, | |
| /* MULHD */ | |
| 3595, | |
| /* MULHDU */ | |
| 3598, | |
| /* MULHDU_rec */ | |
| 3601, | |
| /* MULHD_rec */ | |
| 3604, | |
| /* MULHW */ | |
| 3607, | |
| /* MULHWU */ | |
| 3610, | |
| /* MULHWU_rec */ | |
| 3613, | |
| /* MULHW_rec */ | |
| 3616, | |
| /* MULLD */ | |
| 3619, | |
| /* MULLDO */ | |
| 3622, | |
| /* MULLDO_rec */ | |
| 3625, | |
| /* MULLD_rec */ | |
| 3628, | |
| /* MULLI */ | |
| 3631, | |
| /* MULLI8 */ | |
| 3634, | |
| /* MULLW */ | |
| 3637, | |
| /* MULLWO */ | |
| 3640, | |
| /* MULLWO_rec */ | |
| 3643, | |
| /* MULLW_rec */ | |
| 3646, | |
| /* MoveGOTtoLR */ | |
| 3649, | |
| /* MovePCtoLR */ | |
| 3649, | |
| /* MovePCtoLR8 */ | |
| 3649, | |
| /* NAND */ | |
| 3649, | |
| /* NAND8 */ | |
| 3652, | |
| /* NAND8_rec */ | |
| 3655, | |
| /* NAND_rec */ | |
| 3658, | |
| /* NAP */ | |
| 3661, | |
| /* NEG */ | |
| 3661, | |
| /* NEG8 */ | |
| 3663, | |
| /* NEG8O */ | |
| 3665, | |
| /* NEG8O_rec */ | |
| 3667, | |
| /* NEG8_rec */ | |
| 3669, | |
| /* NEGO */ | |
| 3671, | |
| /* NEGO_rec */ | |
| 3673, | |
| /* NEG_rec */ | |
| 3675, | |
| /* NOP */ | |
| 3677, | |
| /* NOP_GT_PWR6 */ | |
| 3677, | |
| /* NOP_GT_PWR7 */ | |
| 3677, | |
| /* NOR */ | |
| 3677, | |
| /* NOR8 */ | |
| 3680, | |
| /* NOR8_rec */ | |
| 3683, | |
| /* NOR_rec */ | |
| 3686, | |
| /* OR */ | |
| 3689, | |
| /* OR8 */ | |
| 3692, | |
| /* OR8_rec */ | |
| 3695, | |
| /* ORC */ | |
| 3698, | |
| /* ORC8 */ | |
| 3701, | |
| /* ORC8_rec */ | |
| 3704, | |
| /* ORC_rec */ | |
| 3707, | |
| /* ORI */ | |
| 3710, | |
| /* ORI8 */ | |
| 3713, | |
| /* ORIS */ | |
| 3716, | |
| /* ORIS8 */ | |
| 3719, | |
| /* OR_rec */ | |
| 3722, | |
| /* PADDI */ | |
| 3725, | |
| /* PADDI8 */ | |
| 3728, | |
| /* PADDI8pc */ | |
| 3731, | |
| /* PADDIdtprel */ | |
| 3734, | |
| /* PADDIpc */ | |
| 3737, | |
| /* PDEPD */ | |
| 3740, | |
| /* PEXTD */ | |
| 3743, | |
| /* PLBZ */ | |
| 3746, | |
| /* PLBZ8 */ | |
| 3749, | |
| /* PLBZ8pc */ | |
| 3752, | |
| /* PLBZpc */ | |
| 3755, | |
| /* PLD */ | |
| 3758, | |
| /* PLDpc */ | |
| 3761, | |
| /* PLFD */ | |
| 3764, | |
| /* PLFDpc */ | |
| 3767, | |
| /* PLFS */ | |
| 3770, | |
| /* PLFSpc */ | |
| 3773, | |
| /* PLHA */ | |
| 3776, | |
| /* PLHA8 */ | |
| 3779, | |
| /* PLHA8pc */ | |
| 3782, | |
| /* PLHApc */ | |
| 3785, | |
| /* PLHZ */ | |
| 3788, | |
| /* PLHZ8 */ | |
| 3791, | |
| /* PLHZ8pc */ | |
| 3794, | |
| /* PLHZpc */ | |
| 3797, | |
| /* PLI */ | |
| 3800, | |
| /* PLI8 */ | |
| 3802, | |
| /* PLWA */ | |
| 3804, | |
| /* PLWA8 */ | |
| 3807, | |
| /* PLWA8pc */ | |
| 3810, | |
| /* PLWApc */ | |
| 3813, | |
| /* PLWZ */ | |
| 3816, | |
| /* PLWZ8 */ | |
| 3819, | |
| /* PLWZ8pc */ | |
| 3822, | |
| /* PLWZpc */ | |
| 3825, | |
| /* PLXSD */ | |
| 3828, | |
| /* PLXSDpc */ | |
| 3831, | |
| /* PLXSSP */ | |
| 3834, | |
| /* PLXSSPpc */ | |
| 3837, | |
| /* PLXV */ | |
| 3840, | |
| /* PLXVP */ | |
| 3843, | |
| /* PLXVPpc */ | |
| 3846, | |
| /* PLXVpc */ | |
| 3849, | |
| /* PMXVBF16GER2 */ | |
| 3852, | |
| /* PMXVBF16GER2NN */ | |
| 3858, | |
| /* PMXVBF16GER2NP */ | |
| 3865, | |
| /* PMXVBF16GER2PN */ | |
| 3872, | |
| /* PMXVBF16GER2PP */ | |
| 3879, | |
| /* PMXVBF16GER2W */ | |
| 3886, | |
| /* PMXVBF16GER2WNN */ | |
| 3892, | |
| /* PMXVBF16GER2WNP */ | |
| 3899, | |
| /* PMXVBF16GER2WPN */ | |
| 3906, | |
| /* PMXVBF16GER2WPP */ | |
| 3913, | |
| /* PMXVF16GER2 */ | |
| 3920, | |
| /* PMXVF16GER2NN */ | |
| 3926, | |
| /* PMXVF16GER2NP */ | |
| 3933, | |
| /* PMXVF16GER2PN */ | |
| 3940, | |
| /* PMXVF16GER2PP */ | |
| 3947, | |
| /* PMXVF16GER2W */ | |
| 3954, | |
| /* PMXVF16GER2WNN */ | |
| 3960, | |
| /* PMXVF16GER2WNP */ | |
| 3967, | |
| /* PMXVF16GER2WPN */ | |
| 3974, | |
| /* PMXVF16GER2WPP */ | |
| 3981, | |
| /* PMXVF32GER */ | |
| 3988, | |
| /* PMXVF32GERNN */ | |
| 3993, | |
| /* PMXVF32GERNP */ | |
| 3999, | |
| /* PMXVF32GERPN */ | |
| 4005, | |
| /* PMXVF32GERPP */ | |
| 4011, | |
| /* PMXVF32GERW */ | |
| 4017, | |
| /* PMXVF32GERWNN */ | |
| 4022, | |
| /* PMXVF32GERWNP */ | |
| 4028, | |
| /* PMXVF32GERWPN */ | |
| 4034, | |
| /* PMXVF32GERWPP */ | |
| 4040, | |
| /* PMXVF64GER */ | |
| 4046, | |
| /* PMXVF64GERNN */ | |
| 4051, | |
| /* PMXVF64GERNP */ | |
| 4057, | |
| /* PMXVF64GERPN */ | |
| 4063, | |
| /* PMXVF64GERPP */ | |
| 4069, | |
| /* PMXVF64GERW */ | |
| 4075, | |
| /* PMXVF64GERWNN */ | |
| 4080, | |
| /* PMXVF64GERWNP */ | |
| 4086, | |
| /* PMXVF64GERWPN */ | |
| 4092, | |
| /* PMXVF64GERWPP */ | |
| 4098, | |
| /* PMXVI16GER2 */ | |
| 4104, | |
| /* PMXVI16GER2PP */ | |
| 4110, | |
| /* PMXVI16GER2S */ | |
| 4117, | |
| /* PMXVI16GER2SPP */ | |
| 4123, | |
| /* PMXVI16GER2SW */ | |
| 4130, | |
| /* PMXVI16GER2SWPP */ | |
| 4136, | |
| /* PMXVI16GER2W */ | |
| 4143, | |
| /* PMXVI16GER2WPP */ | |
| 4149, | |
| /* PMXVI4GER8 */ | |
| 4156, | |
| /* PMXVI4GER8PP */ | |
| 4162, | |
| /* PMXVI4GER8W */ | |
| 4169, | |
| /* PMXVI4GER8WPP */ | |
| 4175, | |
| /* PMXVI8GER4 */ | |
| 4182, | |
| /* PMXVI8GER4PP */ | |
| 4188, | |
| /* PMXVI8GER4SPP */ | |
| 4195, | |
| /* PMXVI8GER4W */ | |
| 4202, | |
| /* PMXVI8GER4WPP */ | |
| 4208, | |
| /* PMXVI8GER4WSPP */ | |
| 4215, | |
| /* POPCNTB */ | |
| 4222, | |
| /* POPCNTB8 */ | |
| 4224, | |
| /* POPCNTD */ | |
| 4226, | |
| /* POPCNTW */ | |
| 4228, | |
| /* PPC32GOT */ | |
| 4230, | |
| /* PPC32PICGOT */ | |
| 4231, | |
| /* PREPARE_PROBED_ALLOCA_32 */ | |
| 4233, | |
| /* PREPARE_PROBED_ALLOCA_64 */ | |
| 4238, | |
| /* PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 */ | |
| 4243, | |
| /* PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 */ | |
| 4248, | |
| /* PROBED_ALLOCA_32 */ | |
| 4253, | |
| /* PROBED_ALLOCA_64 */ | |
| 4257, | |
| /* PROBED_STACKALLOC_32 */ | |
| 4261, | |
| /* PROBED_STACKALLOC_64 */ | |
| 4264, | |
| /* PSTB */ | |
| 4267, | |
| /* PSTB8 */ | |
| 4270, | |
| /* PSTB8pc */ | |
| 4273, | |
| /* PSTBpc */ | |
| 4276, | |
| /* PSTD */ | |
| 4279, | |
| /* PSTDpc */ | |
| 4282, | |
| /* PSTFD */ | |
| 4285, | |
| /* PSTFDpc */ | |
| 4288, | |
| /* PSTFS */ | |
| 4291, | |
| /* PSTFSpc */ | |
| 4294, | |
| /* PSTH */ | |
| 4297, | |
| /* PSTH8 */ | |
| 4300, | |
| /* PSTH8pc */ | |
| 4303, | |
| /* PSTHpc */ | |
| 4306, | |
| /* PSTW */ | |
| 4309, | |
| /* PSTW8 */ | |
| 4312, | |
| /* PSTW8pc */ | |
| 4315, | |
| /* PSTWpc */ | |
| 4318, | |
| /* PSTXSD */ | |
| 4321, | |
| /* PSTXSDpc */ | |
| 4324, | |
| /* PSTXSSP */ | |
| 4327, | |
| /* PSTXSSPpc */ | |
| 4330, | |
| /* PSTXV */ | |
| 4333, | |
| /* PSTXVP */ | |
| 4336, | |
| /* PSTXVPpc */ | |
| 4339, | |
| /* PSTXVpc */ | |
| 4342, | |
| /* PseudoEIEIO */ | |
| 4345, | |
| /* RESTORE_ACC */ | |
| 4345, | |
| /* RESTORE_CR */ | |
| 4348, | |
| /* RESTORE_CRBIT */ | |
| 4351, | |
| /* RESTORE_QUADWORD */ | |
| 4354, | |
| /* RESTORE_UACC */ | |
| 4357, | |
| /* RESTORE_WACC */ | |
| 4360, | |
| /* RFCI */ | |
| 4363, | |
| /* RFDI */ | |
| 4363, | |
| /* RFEBB */ | |
| 4363, | |
| /* RFI */ | |
| 4364, | |
| /* RFID */ | |
| 4364, | |
| /* RFMCI */ | |
| 4364, | |
| /* RLDCL */ | |
| 4364, | |
| /* RLDCL_rec */ | |
| 4368, | |
| /* RLDCR */ | |
| 4372, | |
| /* RLDCR_rec */ | |
| 4376, | |
| /* RLDIC */ | |
| 4380, | |
| /* RLDICL */ | |
| 4384, | |
| /* RLDICL_32 */ | |
| 4388, | |
| /* RLDICL_32_64 */ | |
| 4392, | |
| /* RLDICL_32_rec */ | |
| 4396, | |
| /* RLDICL_rec */ | |
| 4400, | |
| /* RLDICR */ | |
| 4404, | |
| /* RLDICR_32 */ | |
| 4408, | |
| /* RLDICR_rec */ | |
| 4412, | |
| /* RLDIC_rec */ | |
| 4416, | |
| /* RLDIMI */ | |
| 4420, | |
| /* RLDIMI_rec */ | |
| 4425, | |
| /* RLWIMI */ | |
| 4430, | |
| /* RLWIMI8 */ | |
| 4436, | |
| /* RLWIMI8_rec */ | |
| 4442, | |
| /* RLWIMI_rec */ | |
| 4448, | |
| /* RLWINM */ | |
| 4454, | |
| /* RLWINM8 */ | |
| 4459, | |
| /* RLWINM8_rec */ | |
| 4464, | |
| /* RLWINM_rec */ | |
| 4469, | |
| /* RLWNM */ | |
| 4474, | |
| /* RLWNM8 */ | |
| 4479, | |
| /* RLWNM8_rec */ | |
| 4484, | |
| /* RLWNM_rec */ | |
| 4489, | |
| /* ReadTB */ | |
| 4494, | |
| /* SC */ | |
| 4496, | |
| /* SELECT_CC_F16 */ | |
| 4497, | |
| /* SELECT_CC_F4 */ | |
| 4502, | |
| /* SELECT_CC_F8 */ | |
| 4507, | |
| /* SELECT_CC_I4 */ | |
| 4512, | |
| /* SELECT_CC_I8 */ | |
| 4517, | |
| /* SELECT_CC_SPE */ | |
| 4522, | |
| /* SELECT_CC_SPE4 */ | |
| 4527, | |
| /* SELECT_CC_VRRC */ | |
| 4532, | |
| /* SELECT_CC_VSFRC */ | |
| 4537, | |
| /* SELECT_CC_VSRC */ | |
| 4542, | |
| /* SELECT_CC_VSSRC */ | |
| 4547, | |
| /* SELECT_F16 */ | |
| 4552, | |
| /* SELECT_F4 */ | |
| 4556, | |
| /* SELECT_F8 */ | |
| 4560, | |
| /* SELECT_I4 */ | |
| 4564, | |
| /* SELECT_I8 */ | |
| 4568, | |
| /* SELECT_SPE */ | |
| 4572, | |
| /* SELECT_SPE4 */ | |
| 4576, | |
| /* SELECT_VRRC */ | |
| 4580, | |
| /* SELECT_VSFRC */ | |
| 4584, | |
| /* SELECT_VSRC */ | |
| 4588, | |
| /* SELECT_VSSRC */ | |
| 4592, | |
| /* SETB */ | |
| 4596, | |
| /* SETB8 */ | |
| 4598, | |
| /* SETBC */ | |
| 4600, | |
| /* SETBC8 */ | |
| 4602, | |
| /* SETBCR */ | |
| 4604, | |
| /* SETBCR8 */ | |
| 4606, | |
| /* SETFLM */ | |
| 4608, | |
| /* SETNBC */ | |
| 4610, | |
| /* SETNBC8 */ | |
| 4612, | |
| /* SETNBCR */ | |
| 4614, | |
| /* SETNBCR8 */ | |
| 4616, | |
| /* SETRND */ | |
| 4618, | |
| /* SETRNDi */ | |
| 4620, | |
| /* SLBFEE_rec */ | |
| 4622, | |
| /* SLBIA */ | |
| 4624, | |
| /* SLBIE */ | |
| 4624, | |
| /* SLBIEG */ | |
| 4625, | |
| /* SLBMFEE */ | |
| 4627, | |
| /* SLBMFEV */ | |
| 4629, | |
| /* SLBMTE */ | |
| 4631, | |
| /* SLBSYNC */ | |
| 4633, | |
| /* SLD */ | |
| 4633, | |
| /* SLD_rec */ | |
| 4636, | |
| /* SLW */ | |
| 4639, | |
| /* SLW8 */ | |
| 4642, | |
| /* SLW8_rec */ | |
| 4645, | |
| /* SLW_rec */ | |
| 4648, | |
| /* SPELWZ */ | |
| 4651, | |
| /* SPELWZX */ | |
| 4654, | |
| /* SPESTW */ | |
| 4657, | |
| /* SPESTWX */ | |
| 4660, | |
| /* SPILL_ACC */ | |
| 4663, | |
| /* SPILL_CR */ | |
| 4666, | |
| /* SPILL_CRBIT */ | |
| 4669, | |
| /* SPILL_QUADWORD */ | |
| 4672, | |
| /* SPILL_UACC */ | |
| 4675, | |
| /* SPILL_WACC */ | |
| 4678, | |
| /* SPLIT_QUADWORD */ | |
| 4681, | |
| /* SRAD */ | |
| 4684, | |
| /* SRADI */ | |
| 4687, | |
| /* SRADI_32 */ | |
| 4690, | |
| /* SRADI_rec */ | |
| 4693, | |
| /* SRAD_rec */ | |
| 4696, | |
| /* SRAW */ | |
| 4699, | |
| /* SRAWI */ | |
| 4702, | |
| /* SRAWI_rec */ | |
| 4705, | |
| /* SRAW_rec */ | |
| 4708, | |
| /* SRD */ | |
| 4711, | |
| /* SRD_rec */ | |
| 4714, | |
| /* SRW */ | |
| 4717, | |
| /* SRW8 */ | |
| 4720, | |
| /* SRW8_rec */ | |
| 4723, | |
| /* SRW_rec */ | |
| 4726, | |
| /* STB */ | |
| 4729, | |
| /* STB8 */ | |
| 4732, | |
| /* STBCIX */ | |
| 4735, | |
| /* STBCX */ | |
| 4738, | |
| /* STBEPX */ | |
| 4741, | |
| /* STBU */ | |
| 4744, | |
| /* STBU8 */ | |
| 4748, | |
| /* STBUX */ | |
| 4752, | |
| /* STBUX8 */ | |
| 4756, | |
| /* STBX */ | |
| 4760, | |
| /* STBX8 */ | |
| 4763, | |
| /* STBXTLS */ | |
| 4766, | |
| /* STBXTLS_ */ | |
| 4769, | |
| /* STBXTLS_32 */ | |
| 4772, | |
| /* STD */ | |
| 4775, | |
| /* STDAT */ | |
| 4778, | |
| /* STDBRX */ | |
| 4781, | |
| /* STDCIX */ | |
| 4784, | |
| /* STDCX */ | |
| 4787, | |
| /* STDU */ | |
| 4790, | |
| /* STDUX */ | |
| 4794, | |
| /* STDX */ | |
| 4798, | |
| /* STDXTLS */ | |
| 4801, | |
| /* STDXTLS_ */ | |
| 4804, | |
| /* STFD */ | |
| 4807, | |
| /* STFDEPX */ | |
| 4810, | |
| /* STFDU */ | |
| 4813, | |
| /* STFDUX */ | |
| 4817, | |
| /* STFDX */ | |
| 4821, | |
| /* STFIWX */ | |
| 4824, | |
| /* STFS */ | |
| 4827, | |
| /* STFSU */ | |
| 4830, | |
| /* STFSUX */ | |
| 4834, | |
| /* STFSX */ | |
| 4838, | |
| /* STH */ | |
| 4841, | |
| /* STH8 */ | |
| 4844, | |
| /* STHBRX */ | |
| 4847, | |
| /* STHCIX */ | |
| 4850, | |
| /* STHCX */ | |
| 4853, | |
| /* STHEPX */ | |
| 4856, | |
| /* STHU */ | |
| 4859, | |
| /* STHU8 */ | |
| 4863, | |
| /* STHUX */ | |
| 4867, | |
| /* STHUX8 */ | |
| 4871, | |
| /* STHX */ | |
| 4875, | |
| /* STHX8 */ | |
| 4878, | |
| /* STHXTLS */ | |
| 4881, | |
| /* STHXTLS_ */ | |
| 4884, | |
| /* STHXTLS_32 */ | |
| 4887, | |
| /* STMW */ | |
| 4890, | |
| /* STOP */ | |
| 4893, | |
| /* STQ */ | |
| 4893, | |
| /* STQCX */ | |
| 4896, | |
| /* STQX_PSEUDO */ | |
| 4899, | |
| /* STSWI */ | |
| 4902, | |
| /* STVEBX */ | |
| 4905, | |
| /* STVEHX */ | |
| 4908, | |
| /* STVEWX */ | |
| 4911, | |
| /* STVX */ | |
| 4914, | |
| /* STVXL */ | |
| 4917, | |
| /* STW */ | |
| 4920, | |
| /* STW8 */ | |
| 4923, | |
| /* STWAT */ | |
| 4926, | |
| /* STWBRX */ | |
| 4929, | |
| /* STWCIX */ | |
| 4932, | |
| /* STWCX */ | |
| 4935, | |
| /* STWEPX */ | |
| 4938, | |
| /* STWU */ | |
| 4941, | |
| /* STWU8 */ | |
| 4945, | |
| /* STWUX */ | |
| 4949, | |
| /* STWUX8 */ | |
| 4953, | |
| /* STWX */ | |
| 4957, | |
| /* STWX8 */ | |
| 4960, | |
| /* STWXTLS */ | |
| 4963, | |
| /* STWXTLS_ */ | |
| 4966, | |
| /* STWXTLS_32 */ | |
| 4969, | |
| /* STXSD */ | |
| 4972, | |
| /* STXSDX */ | |
| 4975, | |
| /* STXSIBX */ | |
| 4978, | |
| /* STXSIBXv */ | |
| 4981, | |
| /* STXSIHX */ | |
| 4984, | |
| /* STXSIHXv */ | |
| 4987, | |
| /* STXSIWX */ | |
| 4990, | |
| /* STXSSP */ | |
| 4993, | |
| /* STXSSPX */ | |
| 4996, | |
| /* STXV */ | |
| 4999, | |
| /* STXVB16X */ | |
| 5002, | |
| /* STXVD2X */ | |
| 5005, | |
| /* STXVH8X */ | |
| 5008, | |
| /* STXVL */ | |
| 5011, | |
| /* STXVLL */ | |
| 5014, | |
| /* STXVP */ | |
| 5017, | |
| /* STXVPRL */ | |
| 5020, | |
| /* STXVPRLL */ | |
| 5023, | |
| /* STXVPX */ | |
| 5026, | |
| /* STXVRBX */ | |
| 5029, | |
| /* STXVRDX */ | |
| 5032, | |
| /* STXVRHX */ | |
| 5035, | |
| /* STXVRL */ | |
| 5038, | |
| /* STXVRLL */ | |
| 5041, | |
| /* STXVRWX */ | |
| 5044, | |
| /* STXVW4X */ | |
| 5047, | |
| /* STXVX */ | |
| 5050, | |
| /* SUBF */ | |
| 5053, | |
| /* SUBF8 */ | |
| 5056, | |
| /* SUBF8O */ | |
| 5059, | |
| /* SUBF8O_rec */ | |
| 5062, | |
| /* SUBF8_rec */ | |
| 5065, | |
| /* SUBFC */ | |
| 5068, | |
| /* SUBFC8 */ | |
| 5071, | |
| /* SUBFC8O */ | |
| 5074, | |
| /* SUBFC8O_rec */ | |
| 5077, | |
| /* SUBFC8_rec */ | |
| 5080, | |
| /* SUBFCO */ | |
| 5083, | |
| /* SUBFCO_rec */ | |
| 5086, | |
| /* SUBFC_rec */ | |
| 5089, | |
| /* SUBFE */ | |
| 5092, | |
| /* SUBFE8 */ | |
| 5095, | |
| /* SUBFE8O */ | |
| 5098, | |
| /* SUBFE8O_rec */ | |
| 5101, | |
| /* SUBFE8_rec */ | |
| 5104, | |
| /* SUBFEO */ | |
| 5107, | |
| /* SUBFEO_rec */ | |
| 5110, | |
| /* SUBFE_rec */ | |
| 5113, | |
| /* SUBFIC */ | |
| 5116, | |
| /* SUBFIC8 */ | |
| 5119, | |
| /* SUBFME */ | |
| 5122, | |
| /* SUBFME8 */ | |
| 5124, | |
| /* SUBFME8O */ | |
| 5126, | |
| /* SUBFME8O_rec */ | |
| 5128, | |
| /* SUBFME8_rec */ | |
| 5130, | |
| /* SUBFMEO */ | |
| 5132, | |
| /* SUBFMEO_rec */ | |
| 5134, | |
| /* SUBFME_rec */ | |
| 5136, | |
| /* SUBFO */ | |
| 5138, | |
| /* SUBFO_rec */ | |
| 5141, | |
| /* SUBFUS */ | |
| 5144, | |
| /* SUBFUS_rec */ | |
| 5148, | |
| /* SUBFZE */ | |
| 5152, | |
| /* SUBFZE8 */ | |
| 5154, | |
| /* SUBFZE8O */ | |
| 5156, | |
| /* SUBFZE8O_rec */ | |
| 5158, | |
| /* SUBFZE8_rec */ | |
| 5160, | |
| /* SUBFZEO */ | |
| 5162, | |
| /* SUBFZEO_rec */ | |
| 5164, | |
| /* SUBFZE_rec */ | |
| 5166, | |
| /* SUBF_rec */ | |
| 5168, | |
| /* SYNC */ | |
| 5171, | |
| /* TABORT */ | |
| 5172, | |
| /* TABORTDC */ | |
| 5173, | |
| /* TABORTDCI */ | |
| 5176, | |
| /* TABORTWC */ | |
| 5179, | |
| /* TABORTWCI */ | |
| 5182, | |
| /* TAILB */ | |
| 5185, | |
| /* TAILB8 */ | |
| 5186, | |
| /* TAILBA */ | |
| 5187, | |
| /* TAILBA8 */ | |
| 5188, | |
| /* TAILBCTR */ | |
| 5189, | |
| /* TAILBCTR8 */ | |
| 5189, | |
| /* TBEGIN */ | |
| 5189, | |
| /* TBEGIN_RET */ | |
| 5190, | |
| /* TCHECK */ | |
| 5192, | |
| /* TCHECK_RET */ | |
| 5193, | |
| /* TCRETURNai */ | |
| 5194, | |
| /* TCRETURNai8 */ | |
| 5196, | |
| /* TCRETURNdi */ | |
| 5198, | |
| /* TCRETURNdi8 */ | |
| 5200, | |
| /* TCRETURNri */ | |
| 5202, | |
| /* TCRETURNri8 */ | |
| 5204, | |
| /* TD */ | |
| 5206, | |
| /* TDI */ | |
| 5209, | |
| /* TEND */ | |
| 5212, | |
| /* TLBIA */ | |
| 5213, | |
| /* TLBIE */ | |
| 5213, | |
| /* TLBIEL */ | |
| 5215, | |
| /* TLBIVAX */ | |
| 5216, | |
| /* TLBLD */ | |
| 5218, | |
| /* TLBLI */ | |
| 5219, | |
| /* TLBRE */ | |
| 5220, | |
| /* TLBRE2 */ | |
| 5220, | |
| /* TLBSX */ | |
| 5223, | |
| /* TLBSX2 */ | |
| 5225, | |
| /* TLBSX2D */ | |
| 5228, | |
| /* TLBSYNC */ | |
| 5231, | |
| /* TLBWE */ | |
| 5231, | |
| /* TLBWE2 */ | |
| 5231, | |
| /* TLSGDAIX */ | |
| 5234, | |
| /* TLSGDAIX8 */ | |
| 5237, | |
| /* TRAP */ | |
| 5240, | |
| /* TRECHKPT */ | |
| 5240, | |
| /* TRECLAIM */ | |
| 5240, | |
| /* TSR */ | |
| 5241, | |
| /* TW */ | |
| 5242, | |
| /* TWI */ | |
| 5245, | |
| /* UNENCODED_NOP */ | |
| 5248, | |
| /* UpdateGBR */ | |
| 5248, | |
| /* VABSDUB */ | |
| 5251, | |
| /* VABSDUH */ | |
| 5254, | |
| /* VABSDUW */ | |
| 5257, | |
| /* VADDCUQ */ | |
| 5260, | |
| /* VADDCUW */ | |
| 5263, | |
| /* VADDECUQ */ | |
| 5266, | |
| /* VADDEUQM */ | |
| 5270, | |
| /* VADDFP */ | |
| 5274, | |
| /* VADDSBS */ | |
| 5277, | |
| /* VADDSHS */ | |
| 5280, | |
| /* VADDSWS */ | |
| 5283, | |
| /* VADDUBM */ | |
| 5286, | |
| /* VADDUBS */ | |
| 5289, | |
| /* VADDUDM */ | |
| 5292, | |
| /* VADDUHM */ | |
| 5295, | |
| /* VADDUHS */ | |
| 5298, | |
| /* VADDUQM */ | |
| 5301, | |
| /* VADDUWM */ | |
| 5304, | |
| /* VADDUWS */ | |
| 5307, | |
| /* VAND */ | |
| 5310, | |
| /* VANDC */ | |
| 5313, | |
| /* VAVGSB */ | |
| 5316, | |
| /* VAVGSH */ | |
| 5319, | |
| /* VAVGSW */ | |
| 5322, | |
| /* VAVGUB */ | |
| 5325, | |
| /* VAVGUH */ | |
| 5328, | |
| /* VAVGUW */ | |
| 5331, | |
| /* VBPERMD */ | |
| 5334, | |
| /* VBPERMQ */ | |
| 5337, | |
| /* VCFSX */ | |
| 5340, | |
| /* VCFSX_0 */ | |
| 5343, | |
| /* VCFUGED */ | |
| 5345, | |
| /* VCFUX */ | |
| 5348, | |
| /* VCFUX_0 */ | |
| 5351, | |
| /* VCIPHER */ | |
| 5353, | |
| /* VCIPHERLAST */ | |
| 5356, | |
| /* VCLRLB */ | |
| 5359, | |
| /* VCLRRB */ | |
| 5362, | |
| /* VCLZB */ | |
| 5365, | |
| /* VCLZD */ | |
| 5367, | |
| /* VCLZDM */ | |
| 5369, | |
| /* VCLZH */ | |
| 5372, | |
| /* VCLZLSBB */ | |
| 5374, | |
| /* VCLZW */ | |
| 5376, | |
| /* VCMPBFP */ | |
| 5378, | |
| /* VCMPBFP_rec */ | |
| 5381, | |
| /* VCMPEQFP */ | |
| 5384, | |
| /* VCMPEQFP_rec */ | |
| 5387, | |
| /* VCMPEQUB */ | |
| 5390, | |
| /* VCMPEQUB_rec */ | |
| 5393, | |
| /* VCMPEQUD */ | |
| 5396, | |
| /* VCMPEQUD_rec */ | |
| 5399, | |
| /* VCMPEQUH */ | |
| 5402, | |
| /* VCMPEQUH_rec */ | |
| 5405, | |
| /* VCMPEQUQ */ | |
| 5408, | |
| /* VCMPEQUQ_rec */ | |
| 5411, | |
| /* VCMPEQUW */ | |
| 5414, | |
| /* VCMPEQUW_rec */ | |
| 5417, | |
| /* VCMPGEFP */ | |
| 5420, | |
| /* VCMPGEFP_rec */ | |
| 5423, | |
| /* VCMPGTFP */ | |
| 5426, | |
| /* VCMPGTFP_rec */ | |
| 5429, | |
| /* VCMPGTSB */ | |
| 5432, | |
| /* VCMPGTSB_rec */ | |
| 5435, | |
| /* VCMPGTSD */ | |
| 5438, | |
| /* VCMPGTSD_rec */ | |
| 5441, | |
| /* VCMPGTSH */ | |
| 5444, | |
| /* VCMPGTSH_rec */ | |
| 5447, | |
| /* VCMPGTSQ */ | |
| 5450, | |
| /* VCMPGTSQ_rec */ | |
| 5453, | |
| /* VCMPGTSW */ | |
| 5456, | |
| /* VCMPGTSW_rec */ | |
| 5459, | |
| /* VCMPGTUB */ | |
| 5462, | |
| /* VCMPGTUB_rec */ | |
| 5465, | |
| /* VCMPGTUD */ | |
| 5468, | |
| /* VCMPGTUD_rec */ | |
| 5471, | |
| /* VCMPGTUH */ | |
| 5474, | |
| /* VCMPGTUH_rec */ | |
| 5477, | |
| /* VCMPGTUQ */ | |
| 5480, | |
| /* VCMPGTUQ_rec */ | |
| 5483, | |
| /* VCMPGTUW */ | |
| 5486, | |
| /* VCMPGTUW_rec */ | |
| 5489, | |
| /* VCMPNEB */ | |
| 5492, | |
| /* VCMPNEB_rec */ | |
| 5495, | |
| /* VCMPNEH */ | |
| 5498, | |
| /* VCMPNEH_rec */ | |
| 5501, | |
| /* VCMPNEW */ | |
| 5504, | |
| /* VCMPNEW_rec */ | |
| 5507, | |
| /* VCMPNEZB */ | |
| 5510, | |
| /* VCMPNEZB_rec */ | |
| 5513, | |
| /* VCMPNEZH */ | |
| 5516, | |
| /* VCMPNEZH_rec */ | |
| 5519, | |
| /* VCMPNEZW */ | |
| 5522, | |
| /* VCMPNEZW_rec */ | |
| 5525, | |
| /* VCMPSQ */ | |
| 5528, | |
| /* VCMPUQ */ | |
| 5531, | |
| /* VCNTMBB */ | |
| 5534, | |
| /* VCNTMBD */ | |
| 5537, | |
| /* VCNTMBH */ | |
| 5540, | |
| /* VCNTMBW */ | |
| 5543, | |
| /* VCTSXS */ | |
| 5546, | |
| /* VCTSXS_0 */ | |
| 5549, | |
| /* VCTUXS */ | |
| 5551, | |
| /* VCTUXS_0 */ | |
| 5554, | |
| /* VCTZB */ | |
| 5556, | |
| /* VCTZD */ | |
| 5558, | |
| /* VCTZDM */ | |
| 5560, | |
| /* VCTZH */ | |
| 5563, | |
| /* VCTZLSBB */ | |
| 5565, | |
| /* VCTZW */ | |
| 5567, | |
| /* VDIVESD */ | |
| 5569, | |
| /* VDIVESQ */ | |
| 5572, | |
| /* VDIVESW */ | |
| 5575, | |
| /* VDIVEUD */ | |
| 5578, | |
| /* VDIVEUQ */ | |
| 5581, | |
| /* VDIVEUW */ | |
| 5584, | |
| /* VDIVSD */ | |
| 5587, | |
| /* VDIVSQ */ | |
| 5590, | |
| /* VDIVSW */ | |
| 5593, | |
| /* VDIVUD */ | |
| 5596, | |
| /* VDIVUQ */ | |
| 5599, | |
| /* VDIVUW */ | |
| 5602, | |
| /* VEQV */ | |
| 5605, | |
| /* VEXPANDBM */ | |
| 5608, | |
| /* VEXPANDDM */ | |
| 5610, | |
| /* VEXPANDHM */ | |
| 5612, | |
| /* VEXPANDQM */ | |
| 5614, | |
| /* VEXPANDWM */ | |
| 5616, | |
| /* VEXPTEFP */ | |
| 5618, | |
| /* VEXTDDVLX */ | |
| 5620, | |
| /* VEXTDDVRX */ | |
| 5624, | |
| /* VEXTDUBVLX */ | |
| 5628, | |
| /* VEXTDUBVRX */ | |
| 5632, | |
| /* VEXTDUHVLX */ | |
| 5636, | |
| /* VEXTDUHVRX */ | |
| 5640, | |
| /* VEXTDUWVLX */ | |
| 5644, | |
| /* VEXTDUWVRX */ | |
| 5648, | |
| /* VEXTRACTBM */ | |
| 5652, | |
| /* VEXTRACTD */ | |
| 5654, | |
| /* VEXTRACTDM */ | |
| 5657, | |
| /* VEXTRACTHM */ | |
| 5659, | |
| /* VEXTRACTQM */ | |
| 5661, | |
| /* VEXTRACTUB */ | |
| 5663, | |
| /* VEXTRACTUH */ | |
| 5666, | |
| /* VEXTRACTUW */ | |
| 5669, | |
| /* VEXTRACTWM */ | |
| 5672, | |
| /* VEXTSB2D */ | |
| 5674, | |
| /* VEXTSB2Ds */ | |
| 5676, | |
| /* VEXTSB2W */ | |
| 5678, | |
| /* VEXTSB2Ws */ | |
| 5680, | |
| /* VEXTSD2Q */ | |
| 5682, | |
| /* VEXTSH2D */ | |
| 5684, | |
| /* VEXTSH2Ds */ | |
| 5686, | |
| /* VEXTSH2W */ | |
| 5688, | |
| /* VEXTSH2Ws */ | |
| 5690, | |
| /* VEXTSW2D */ | |
| 5692, | |
| /* VEXTSW2Ds */ | |
| 5694, | |
| /* VEXTUBLX */ | |
| 5696, | |
| /* VEXTUBRX */ | |
| 5699, | |
| /* VEXTUHLX */ | |
| 5702, | |
| /* VEXTUHRX */ | |
| 5705, | |
| /* VEXTUWLX */ | |
| 5708, | |
| /* VEXTUWRX */ | |
| 5711, | |
| /* VGBBD */ | |
| 5714, | |
| /* VGNB */ | |
| 5716, | |
| /* VINSBLX */ | |
| 5719, | |
| /* VINSBRX */ | |
| 5723, | |
| /* VINSBVLX */ | |
| 5727, | |
| /* VINSBVRX */ | |
| 5731, | |
| /* VINSD */ | |
| 5735, | |
| /* VINSDLX */ | |
| 5739, | |
| /* VINSDRX */ | |
| 5743, | |
| /* VINSERTB */ | |
| 5747, | |
| /* VINSERTD */ | |
| 5751, | |
| /* VINSERTH */ | |
| 5754, | |
| /* VINSERTW */ | |
| 5758, | |
| /* VINSHLX */ | |
| 5761, | |
| /* VINSHRX */ | |
| 5765, | |
| /* VINSHVLX */ | |
| 5769, | |
| /* VINSHVRX */ | |
| 5773, | |
| /* VINSW */ | |
| 5777, | |
| /* VINSWLX */ | |
| 5781, | |
| /* VINSWRX */ | |
| 5785, | |
| /* VINSWVLX */ | |
| 5789, | |
| /* VINSWVRX */ | |
| 5793, | |
| /* VLOGEFP */ | |
| 5797, | |
| /* VMADDFP */ | |
| 5799, | |
| /* VMAXFP */ | |
| 5803, | |
| /* VMAXSB */ | |
| 5806, | |
| /* VMAXSD */ | |
| 5809, | |
| /* VMAXSH */ | |
| 5812, | |
| /* VMAXSW */ | |
| 5815, | |
| /* VMAXUB */ | |
| 5818, | |
| /* VMAXUD */ | |
| 5821, | |
| /* VMAXUH */ | |
| 5824, | |
| /* VMAXUW */ | |
| 5827, | |
| /* VMHADDSHS */ | |
| 5830, | |
| /* VMHRADDSHS */ | |
| 5834, | |
| /* VMINFP */ | |
| 5838, | |
| /* VMINSB */ | |
| 5841, | |
| /* VMINSD */ | |
| 5844, | |
| /* VMINSH */ | |
| 5847, | |
| /* VMINSW */ | |
| 5850, | |
| /* VMINUB */ | |
| 5853, | |
| /* VMINUD */ | |
| 5856, | |
| /* VMINUH */ | |
| 5859, | |
| /* VMINUW */ | |
| 5862, | |
| /* VMLADDUHM */ | |
| 5865, | |
| /* VMODSD */ | |
| 5869, | |
| /* VMODSQ */ | |
| 5872, | |
| /* VMODSW */ | |
| 5875, | |
| /* VMODUD */ | |
| 5878, | |
| /* VMODUQ */ | |
| 5881, | |
| /* VMODUW */ | |
| 5884, | |
| /* VMRGEW */ | |
| 5887, | |
| /* VMRGHB */ | |
| 5890, | |
| /* VMRGHH */ | |
| 5893, | |
| /* VMRGHW */ | |
| 5896, | |
| /* VMRGLB */ | |
| 5899, | |
| /* VMRGLH */ | |
| 5902, | |
| /* VMRGLW */ | |
| 5905, | |
| /* VMRGOW */ | |
| 5908, | |
| /* VMSUMCUD */ | |
| 5911, | |
| /* VMSUMMBM */ | |
| 5915, | |
| /* VMSUMSHM */ | |
| 5919, | |
| /* VMSUMSHS */ | |
| 5923, | |
| /* VMSUMUBM */ | |
| 5927, | |
| /* VMSUMUDM */ | |
| 5931, | |
| /* VMSUMUHM */ | |
| 5935, | |
| /* VMSUMUHS */ | |
| 5939, | |
| /* VMUL10CUQ */ | |
| 5943, | |
| /* VMUL10ECUQ */ | |
| 5945, | |
| /* VMUL10EUQ */ | |
| 5948, | |
| /* VMUL10UQ */ | |
| 5951, | |
| /* VMULESB */ | |
| 5953, | |
| /* VMULESD */ | |
| 5956, | |
| /* VMULESH */ | |
| 5959, | |
| /* VMULESW */ | |
| 5962, | |
| /* VMULEUB */ | |
| 5965, | |
| /* VMULEUD */ | |
| 5968, | |
| /* VMULEUH */ | |
| 5971, | |
| /* VMULEUW */ | |
| 5974, | |
| /* VMULHSD */ | |
| 5977, | |
| /* VMULHSW */ | |
| 5980, | |
| /* VMULHUD */ | |
| 5983, | |
| /* VMULHUW */ | |
| 5986, | |
| /* VMULLD */ | |
| 5989, | |
| /* VMULOSB */ | |
| 5992, | |
| /* VMULOSD */ | |
| 5995, | |
| /* VMULOSH */ | |
| 5998, | |
| /* VMULOSW */ | |
| 6001, | |
| /* VMULOUB */ | |
| 6004, | |
| /* VMULOUD */ | |
| 6007, | |
| /* VMULOUH */ | |
| 6010, | |
| /* VMULOUW */ | |
| 6013, | |
| /* VMULUWM */ | |
| 6016, | |
| /* VNAND */ | |
| 6019, | |
| /* VNCIPHER */ | |
| 6022, | |
| /* VNCIPHERLAST */ | |
| 6025, | |
| /* VNEGD */ | |
| 6028, | |
| /* VNEGW */ | |
| 6030, | |
| /* VNMSUBFP */ | |
| 6032, | |
| /* VNOR */ | |
| 6036, | |
| /* VOR */ | |
| 6039, | |
| /* VORC */ | |
| 6042, | |
| /* VPDEPD */ | |
| 6045, | |
| /* VPERM */ | |
| 6048, | |
| /* VPERMR */ | |
| 6052, | |
| /* VPERMXOR */ | |
| 6056, | |
| /* VPEXTD */ | |
| 6060, | |
| /* VPKPX */ | |
| 6063, | |
| /* VPKSDSS */ | |
| 6066, | |
| /* VPKSDUS */ | |
| 6069, | |
| /* VPKSHSS */ | |
| 6072, | |
| /* VPKSHUS */ | |
| 6075, | |
| /* VPKSWSS */ | |
| 6078, | |
| /* VPKSWUS */ | |
| 6081, | |
| /* VPKUDUM */ | |
| 6084, | |
| /* VPKUDUS */ | |
| 6087, | |
| /* VPKUHUM */ | |
| 6090, | |
| /* VPKUHUS */ | |
| 6093, | |
| /* VPKUWUM */ | |
| 6096, | |
| /* VPKUWUS */ | |
| 6099, | |
| /* VPMSUMB */ | |
| 6102, | |
| /* VPMSUMD */ | |
| 6105, | |
| /* VPMSUMH */ | |
| 6108, | |
| /* VPMSUMW */ | |
| 6111, | |
| /* VPOPCNTB */ | |
| 6114, | |
| /* VPOPCNTD */ | |
| 6116, | |
| /* VPOPCNTH */ | |
| 6118, | |
| /* VPOPCNTW */ | |
| 6120, | |
| /* VPRTYBD */ | |
| 6122, | |
| /* VPRTYBQ */ | |
| 6124, | |
| /* VPRTYBW */ | |
| 6126, | |
| /* VREFP */ | |
| 6128, | |
| /* VRFIM */ | |
| 6130, | |
| /* VRFIN */ | |
| 6132, | |
| /* VRFIP */ | |
| 6134, | |
| /* VRFIZ */ | |
| 6136, | |
| /* VRLB */ | |
| 6138, | |
| /* VRLD */ | |
| 6141, | |
| /* VRLDMI */ | |
| 6144, | |
| /* VRLDNM */ | |
| 6148, | |
| /* VRLH */ | |
| 6151, | |
| /* VRLQ */ | |
| 6154, | |
| /* VRLQMI */ | |
| 6157, | |
| /* VRLQNM */ | |
| 6161, | |
| /* VRLW */ | |
| 6164, | |
| /* VRLWMI */ | |
| 6167, | |
| /* VRLWNM */ | |
| 6171, | |
| /* VRSQRTEFP */ | |
| 6174, | |
| /* VSBOX */ | |
| 6176, | |
| /* VSEL */ | |
| 6178, | |
| /* VSHASIGMAD */ | |
| 6182, | |
| /* VSHASIGMAW */ | |
| 6186, | |
| /* VSL */ | |
| 6190, | |
| /* VSLB */ | |
| 6193, | |
| /* VSLD */ | |
| 6196, | |
| /* VSLDBI */ | |
| 6199, | |
| /* VSLDOI */ | |
| 6203, | |
| /* VSLH */ | |
| 6207, | |
| /* VSLO */ | |
| 6210, | |
| /* VSLQ */ | |
| 6213, | |
| /* VSLV */ | |
| 6216, | |
| /* VSLW */ | |
| 6219, | |
| /* VSPLTB */ | |
| 6222, | |
| /* VSPLTBs */ | |
| 6225, | |
| /* VSPLTH */ | |
| 6228, | |
| /* VSPLTHs */ | |
| 6231, | |
| /* VSPLTISB */ | |
| 6234, | |
| /* VSPLTISH */ | |
| 6236, | |
| /* VSPLTISW */ | |
| 6238, | |
| /* VSPLTW */ | |
| 6240, | |
| /* VSR */ | |
| 6243, | |
| /* VSRAB */ | |
| 6246, | |
| /* VSRAD */ | |
| 6249, | |
| /* VSRAH */ | |
| 6252, | |
| /* VSRAQ */ | |
| 6255, | |
| /* VSRAW */ | |
| 6258, | |
| /* VSRB */ | |
| 6261, | |
| /* VSRD */ | |
| 6264, | |
| /* VSRDBI */ | |
| 6267, | |
| /* VSRH */ | |
| 6271, | |
| /* VSRO */ | |
| 6274, | |
| /* VSRQ */ | |
| 6277, | |
| /* VSRV */ | |
| 6280, | |
| /* VSRW */ | |
| 6283, | |
| /* VSTRIBL */ | |
| 6286, | |
| /* VSTRIBL_rec */ | |
| 6288, | |
| /* VSTRIBR */ | |
| 6290, | |
| /* VSTRIBR_rec */ | |
| 6292, | |
| /* VSTRIHL */ | |
| 6294, | |
| /* VSTRIHL_rec */ | |
| 6296, | |
| /* VSTRIHR */ | |
| 6298, | |
| /* VSTRIHR_rec */ | |
| 6300, | |
| /* VSUBCUQ */ | |
| 6302, | |
| /* VSUBCUW */ | |
| 6305, | |
| /* VSUBECUQ */ | |
| 6308, | |
| /* VSUBEUQM */ | |
| 6312, | |
| /* VSUBFP */ | |
| 6316, | |
| /* VSUBSBS */ | |
| 6319, | |
| /* VSUBSHS */ | |
| 6322, | |
| /* VSUBSWS */ | |
| 6325, | |
| /* VSUBUBM */ | |
| 6328, | |
| /* VSUBUBS */ | |
| 6331, | |
| /* VSUBUDM */ | |
| 6334, | |
| /* VSUBUHM */ | |
| 6337, | |
| /* VSUBUHS */ | |
| 6340, | |
| /* VSUBUQM */ | |
| 6343, | |
| /* VSUBUWM */ | |
| 6346, | |
| /* VSUBUWS */ | |
| 6349, | |
| /* VSUM2SWS */ | |
| 6352, | |
| /* VSUM4SBS */ | |
| 6355, | |
| /* VSUM4SHS */ | |
| 6358, | |
| /* VSUM4UBS */ | |
| 6361, | |
| /* VSUMSWS */ | |
| 6364, | |
| /* VUPKHPX */ | |
| 6367, | |
| /* VUPKHSB */ | |
| 6369, | |
| /* VUPKHSH */ | |
| 6371, | |
| /* VUPKHSW */ | |
| 6373, | |
| /* VUPKLPX */ | |
| 6375, | |
| /* VUPKLSB */ | |
| 6377, | |
| /* VUPKLSH */ | |
| 6379, | |
| /* VUPKLSW */ | |
| 6381, | |
| /* VXOR */ | |
| 6383, | |
| /* V_SET0 */ | |
| 6386, | |
| /* V_SET0B */ | |
| 6387, | |
| /* V_SET0H */ | |
| 6388, | |
| /* V_SETALLONES */ | |
| 6389, | |
| /* V_SETALLONESB */ | |
| 6390, | |
| /* V_SETALLONESH */ | |
| 6391, | |
| /* WAIT */ | |
| 6392, | |
| /* WRTEE */ | |
| 6393, | |
| /* WRTEEI */ | |
| 6394, | |
| /* XOR */ | |
| 6395, | |
| /* XOR8 */ | |
| 6398, | |
| /* XOR8_rec */ | |
| 6401, | |
| /* XORI */ | |
| 6404, | |
| /* XORI8 */ | |
| 6407, | |
| /* XORIS */ | |
| 6410, | |
| /* XORIS8 */ | |
| 6413, | |
| /* XOR_rec */ | |
| 6416, | |
| /* XSABSDP */ | |
| 6419, | |
| /* XSABSQP */ | |
| 6421, | |
| /* XSADDDP */ | |
| 6423, | |
| /* XSADDQP */ | |
| 6426, | |
| /* XSADDQPO */ | |
| 6429, | |
| /* XSADDSP */ | |
| 6432, | |
| /* XSCMPEQDP */ | |
| 6435, | |
| /* XSCMPEQQP */ | |
| 6438, | |
| /* XSCMPEXPDP */ | |
| 6441, | |
| /* XSCMPEXPQP */ | |
| 6444, | |
| /* XSCMPGEDP */ | |
| 6447, | |
| /* XSCMPGEQP */ | |
| 6450, | |
| /* XSCMPGTDP */ | |
| 6453, | |
| /* XSCMPGTQP */ | |
| 6456, | |
| /* XSCMPODP */ | |
| 6459, | |
| /* XSCMPOQP */ | |
| 6462, | |
| /* XSCMPUDP */ | |
| 6465, | |
| /* XSCMPUQP */ | |
| 6468, | |
| /* XSCPSGNDP */ | |
| 6471, | |
| /* XSCPSGNQP */ | |
| 6474, | |
| /* XSCVDPHP */ | |
| 6477, | |
| /* XSCVDPQP */ | |
| 6479, | |
| /* XSCVDPSP */ | |
| 6481, | |
| /* XSCVDPSPN */ | |
| 6483, | |
| /* XSCVDPSXDS */ | |
| 6485, | |
| /* XSCVDPSXDSs */ | |
| 6487, | |
| /* XSCVDPSXWS */ | |
| 6489, | |
| /* XSCVDPSXWSs */ | |
| 6491, | |
| /* XSCVDPUXDS */ | |
| 6493, | |
| /* XSCVDPUXDSs */ | |
| 6495, | |
| /* XSCVDPUXWS */ | |
| 6497, | |
| /* XSCVDPUXWSs */ | |
| 6499, | |
| /* XSCVHPDP */ | |
| 6501, | |
| /* XSCVQPDP */ | |
| 6503, | |
| /* XSCVQPDPO */ | |
| 6505, | |
| /* XSCVQPSDZ */ | |
| 6507, | |
| /* XSCVQPSQZ */ | |
| 6509, | |
| /* XSCVQPSWZ */ | |
| 6511, | |
| /* XSCVQPUDZ */ | |
| 6513, | |
| /* XSCVQPUQZ */ | |
| 6515, | |
| /* XSCVQPUWZ */ | |
| 6517, | |
| /* XSCVSDQP */ | |
| 6519, | |
| /* XSCVSPDP */ | |
| 6521, | |
| /* XSCVSPDPN */ | |
| 6523, | |
| /* XSCVSQQP */ | |
| 6525, | |
| /* XSCVSXDDP */ | |
| 6527, | |
| /* XSCVSXDSP */ | |
| 6529, | |
| /* XSCVUDQP */ | |
| 6531, | |
| /* XSCVUQQP */ | |
| 6533, | |
| /* XSCVUXDDP */ | |
| 6535, | |
| /* XSCVUXDSP */ | |
| 6537, | |
| /* XSDIVDP */ | |
| 6539, | |
| /* XSDIVQP */ | |
| 6542, | |
| /* XSDIVQPO */ | |
| 6545, | |
| /* XSDIVSP */ | |
| 6548, | |
| /* XSIEXPDP */ | |
| 6551, | |
| /* XSIEXPQP */ | |
| 6554, | |
| /* XSMADDADP */ | |
| 6557, | |
| /* XSMADDASP */ | |
| 6561, | |
| /* XSMADDMDP */ | |
| 6565, | |
| /* XSMADDMSP */ | |
| 6569, | |
| /* XSMADDQP */ | |
| 6573, | |
| /* XSMADDQPO */ | |
| 6577, | |
| /* XSMAXCDP */ | |
| 6581, | |
| /* XSMAXCQP */ | |
| 6584, | |
| /* XSMAXDP */ | |
| 6587, | |
| /* XSMAXJDP */ | |
| 6590, | |
| /* XSMINCDP */ | |
| 6593, | |
| /* XSMINCQP */ | |
| 6596, | |
| /* XSMINDP */ | |
| 6599, | |
| /* XSMINJDP */ | |
| 6602, | |
| /* XSMSUBADP */ | |
| 6605, | |
| /* XSMSUBASP */ | |
| 6609, | |
| /* XSMSUBMDP */ | |
| 6613, | |
| /* XSMSUBMSP */ | |
| 6617, | |
| /* XSMSUBQP */ | |
| 6621, | |
| /* XSMSUBQPO */ | |
| 6625, | |
| /* XSMULDP */ | |
| 6629, | |
| /* XSMULQP */ | |
| 6632, | |
| /* XSMULQPO */ | |
| 6635, | |
| /* XSMULSP */ | |
| 6638, | |
| /* XSNABSDP */ | |
| 6641, | |
| /* XSNABSDPs */ | |
| 6643, | |
| /* XSNABSQP */ | |
| 6645, | |
| /* XSNEGDP */ | |
| 6647, | |
| /* XSNEGQP */ | |
| 6649, | |
| /* XSNMADDADP */ | |
| 6651, | |
| /* XSNMADDASP */ | |
| 6655, | |
| /* XSNMADDMDP */ | |
| 6659, | |
| /* XSNMADDMSP */ | |
| 6663, | |
| /* XSNMADDQP */ | |
| 6667, | |
| /* XSNMADDQPO */ | |
| 6671, | |
| /* XSNMSUBADP */ | |
| 6675, | |
| /* XSNMSUBASP */ | |
| 6679, | |
| /* XSNMSUBMDP */ | |
| 6683, | |
| /* XSNMSUBMSP */ | |
| 6687, | |
| /* XSNMSUBQP */ | |
| 6691, | |
| /* XSNMSUBQPO */ | |
| 6695, | |
| /* XSRDPI */ | |
| 6699, | |
| /* XSRDPIC */ | |
| 6701, | |
| /* XSRDPIM */ | |
| 6703, | |
| /* XSRDPIP */ | |
| 6705, | |
| /* XSRDPIZ */ | |
| 6707, | |
| /* XSREDP */ | |
| 6709, | |
| /* XSRESP */ | |
| 6711, | |
| /* XSRQPI */ | |
| 6713, | |
| /* XSRQPIX */ | |
| 6717, | |
| /* XSRQPXP */ | |
| 6721, | |
| /* XSRSP */ | |
| 6725, | |
| /* XSRSQRTEDP */ | |
| 6727, | |
| /* XSRSQRTESP */ | |
| 6729, | |
| /* XSSQRTDP */ | |
| 6731, | |
| /* XSSQRTQP */ | |
| 6733, | |
| /* XSSQRTQPO */ | |
| 6735, | |
| /* XSSQRTSP */ | |
| 6737, | |
| /* XSSUBDP */ | |
| 6739, | |
| /* XSSUBQP */ | |
| 6742, | |
| /* XSSUBQPO */ | |
| 6745, | |
| /* XSSUBSP */ | |
| 6748, | |
| /* XSTDIVDP */ | |
| 6751, | |
| /* XSTSQRTDP */ | |
| 6754, | |
| /* XSTSTDCDP */ | |
| 6756, | |
| /* XSTSTDCQP */ | |
| 6759, | |
| /* XSTSTDCSP */ | |
| 6762, | |
| /* XSXEXPDP */ | |
| 6765, | |
| /* XSXEXPQP */ | |
| 6767, | |
| /* XSXSIGDP */ | |
| 6769, | |
| /* XSXSIGQP */ | |
| 6771, | |
| /* XVABSDP */ | |
| 6773, | |
| /* XVABSSP */ | |
| 6775, | |
| /* XVADDDP */ | |
| 6777, | |
| /* XVADDSP */ | |
| 6780, | |
| /* XVBF16GER2 */ | |
| 6783, | |
| /* XVBF16GER2NN */ | |
| 6786, | |
| /* XVBF16GER2NP */ | |
| 6790, | |
| /* XVBF16GER2PN */ | |
| 6794, | |
| /* XVBF16GER2PP */ | |
| 6798, | |
| /* XVBF16GER2W */ | |
| 6802, | |
| /* XVBF16GER2WNN */ | |
| 6805, | |
| /* XVBF16GER2WNP */ | |
| 6809, | |
| /* XVBF16GER2WPN */ | |
| 6813, | |
| /* XVBF16GER2WPP */ | |
| 6817, | |
| /* XVCMPEQDP */ | |
| 6821, | |
| /* XVCMPEQDP_rec */ | |
| 6824, | |
| /* XVCMPEQSP */ | |
| 6827, | |
| /* XVCMPEQSP_rec */ | |
| 6830, | |
| /* XVCMPGEDP */ | |
| 6833, | |
| /* XVCMPGEDP_rec */ | |
| 6836, | |
| /* XVCMPGESP */ | |
| 6839, | |
| /* XVCMPGESP_rec */ | |
| 6842, | |
| /* XVCMPGTDP */ | |
| 6845, | |
| /* XVCMPGTDP_rec */ | |
| 6848, | |
| /* XVCMPGTSP */ | |
| 6851, | |
| /* XVCMPGTSP_rec */ | |
| 6854, | |
| /* XVCPSGNDP */ | |
| 6857, | |
| /* XVCPSGNSP */ | |
| 6860, | |
| /* XVCVBF16SPN */ | |
| 6863, | |
| /* XVCVDPSP */ | |
| 6865, | |
| /* XVCVDPSXDS */ | |
| 6867, | |
| /* XVCVDPSXWS */ | |
| 6869, | |
| /* XVCVDPUXDS */ | |
| 6871, | |
| /* XVCVDPUXWS */ | |
| 6873, | |
| /* XVCVHPSP */ | |
| 6875, | |
| /* XVCVSPBF16 */ | |
| 6877, | |
| /* XVCVSPDP */ | |
| 6879, | |
| /* XVCVSPHP */ | |
| 6881, | |
| /* XVCVSPSXDS */ | |
| 6883, | |
| /* XVCVSPSXWS */ | |
| 6885, | |
| /* XVCVSPUXDS */ | |
| 6887, | |
| /* XVCVSPUXWS */ | |
| 6889, | |
| /* XVCVSXDDP */ | |
| 6891, | |
| /* XVCVSXDSP */ | |
| 6893, | |
| /* XVCVSXWDP */ | |
| 6895, | |
| /* XVCVSXWSP */ | |
| 6897, | |
| /* XVCVUXDDP */ | |
| 6899, | |
| /* XVCVUXDSP */ | |
| 6901, | |
| /* XVCVUXWDP */ | |
| 6903, | |
| /* XVCVUXWSP */ | |
| 6905, | |
| /* XVDIVDP */ | |
| 6907, | |
| /* XVDIVSP */ | |
| 6910, | |
| /* XVF16GER2 */ | |
| 6913, | |
| /* XVF16GER2NN */ | |
| 6916, | |
| /* XVF16GER2NP */ | |
| 6920, | |
| /* XVF16GER2PN */ | |
| 6924, | |
| /* XVF16GER2PP */ | |
| 6928, | |
| /* XVF16GER2W */ | |
| 6932, | |
| /* XVF16GER2WNN */ | |
| 6935, | |
| /* XVF16GER2WNP */ | |
| 6939, | |
| /* XVF16GER2WPN */ | |
| 6943, | |
| /* XVF16GER2WPP */ | |
| 6947, | |
| /* XVF32GER */ | |
| 6951, | |
| /* XVF32GERNN */ | |
| 6954, | |
| /* XVF32GERNP */ | |
| 6958, | |
| /* XVF32GERPN */ | |
| 6962, | |
| /* XVF32GERPP */ | |
| 6966, | |
| /* XVF32GERW */ | |
| 6970, | |
| /* XVF32GERWNN */ | |
| 6973, | |
| /* XVF32GERWNP */ | |
| 6977, | |
| /* XVF32GERWPN */ | |
| 6981, | |
| /* XVF32GERWPP */ | |
| 6985, | |
| /* XVF64GER */ | |
| 6989, | |
| /* XVF64GERNN */ | |
| 6992, | |
| /* XVF64GERNP */ | |
| 6996, | |
| /* XVF64GERPN */ | |
| 7000, | |
| /* XVF64GERPP */ | |
| 7004, | |
| /* XVF64GERW */ | |
| 7008, | |
| /* XVF64GERWNN */ | |
| 7011, | |
| /* XVF64GERWNP */ | |
| 7015, | |
| /* XVF64GERWPN */ | |
| 7019, | |
| /* XVF64GERWPP */ | |
| 7023, | |
| /* XVI16GER2 */ | |
| 7027, | |
| /* XVI16GER2PP */ | |
| 7030, | |
| /* XVI16GER2S */ | |
| 7034, | |
| /* XVI16GER2SPP */ | |
| 7037, | |
| /* XVI16GER2SW */ | |
| 7041, | |
| /* XVI16GER2SWPP */ | |
| 7044, | |
| /* XVI16GER2W */ | |
| 7048, | |
| /* XVI16GER2WPP */ | |
| 7051, | |
| /* XVI4GER8 */ | |
| 7055, | |
| /* XVI4GER8PP */ | |
| 7058, | |
| /* XVI4GER8W */ | |
| 7062, | |
| /* XVI4GER8WPP */ | |
| 7065, | |
| /* XVI8GER4 */ | |
| 7069, | |
| /* XVI8GER4PP */ | |
| 7072, | |
| /* XVI8GER4SPP */ | |
| 7076, | |
| /* XVI8GER4W */ | |
| 7080, | |
| /* XVI8GER4WPP */ | |
| 7083, | |
| /* XVI8GER4WSPP */ | |
| 7087, | |
| /* XVIEXPDP */ | |
| 7091, | |
| /* XVIEXPSP */ | |
| 7094, | |
| /* XVMADDADP */ | |
| 7097, | |
| /* XVMADDASP */ | |
| 7101, | |
| /* XVMADDMDP */ | |
| 7105, | |
| /* XVMADDMSP */ | |
| 7109, | |
| /* XVMAXDP */ | |
| 7113, | |
| /* XVMAXSP */ | |
| 7116, | |
| /* XVMINDP */ | |
| 7119, | |
| /* XVMINSP */ | |
| 7122, | |
| /* XVMSUBADP */ | |
| 7125, | |
| /* XVMSUBASP */ | |
| 7129, | |
| /* XVMSUBMDP */ | |
| 7133, | |
| /* XVMSUBMSP */ | |
| 7137, | |
| /* XVMULDP */ | |
| 7141, | |
| /* XVMULSP */ | |
| 7144, | |
| /* XVNABSDP */ | |
| 7147, | |
| /* XVNABSSP */ | |
| 7149, | |
| /* XVNEGDP */ | |
| 7151, | |
| /* XVNEGSP */ | |
| 7153, | |
| /* XVNMADDADP */ | |
| 7155, | |
| /* XVNMADDASP */ | |
| 7159, | |
| /* XVNMADDMDP */ | |
| 7163, | |
| /* XVNMADDMSP */ | |
| 7167, | |
| /* XVNMSUBADP */ | |
| 7171, | |
| /* XVNMSUBASP */ | |
| 7175, | |
| /* XVNMSUBMDP */ | |
| 7179, | |
| /* XVNMSUBMSP */ | |
| 7183, | |
| /* XVRDPI */ | |
| 7187, | |
| /* XVRDPIC */ | |
| 7189, | |
| /* XVRDPIM */ | |
| 7191, | |
| /* XVRDPIP */ | |
| 7193, | |
| /* XVRDPIZ */ | |
| 7195, | |
| /* XVREDP */ | |
| 7197, | |
| /* XVRESP */ | |
| 7199, | |
| /* XVRSPI */ | |
| 7201, | |
| /* XVRSPIC */ | |
| 7203, | |
| /* XVRSPIM */ | |
| 7205, | |
| /* XVRSPIP */ | |
| 7207, | |
| /* XVRSPIZ */ | |
| 7209, | |
| /* XVRSQRTEDP */ | |
| 7211, | |
| /* XVRSQRTESP */ | |
| 7213, | |
| /* XVSQRTDP */ | |
| 7215, | |
| /* XVSQRTSP */ | |
| 7217, | |
| /* XVSUBDP */ | |
| 7219, | |
| /* XVSUBSP */ | |
| 7222, | |
| /* XVTDIVDP */ | |
| 7225, | |
| /* XVTDIVSP */ | |
| 7228, | |
| /* XVTLSBB */ | |
| 7231, | |
| /* XVTSQRTDP */ | |
| 7233, | |
| /* XVTSQRTSP */ | |
| 7235, | |
| /* XVTSTDCDP */ | |
| 7237, | |
| /* XVTSTDCSP */ | |
| 7240, | |
| /* XVXEXPDP */ | |
| 7243, | |
| /* XVXEXPSP */ | |
| 7245, | |
| /* XVXSIGDP */ | |
| 7247, | |
| /* XVXSIGSP */ | |
| 7249, | |
| /* XXBLENDVB */ | |
| 7251, | |
| /* XXBLENDVD */ | |
| 7255, | |
| /* XXBLENDVH */ | |
| 7259, | |
| /* XXBLENDVW */ | |
| 7263, | |
| /* XXBRD */ | |
| 7267, | |
| /* XXBRH */ | |
| 7269, | |
| /* XXBRQ */ | |
| 7271, | |
| /* XXBRW */ | |
| 7273, | |
| /* XXEVAL */ | |
| 7275, | |
| /* XXEXTRACTUW */ | |
| 7280, | |
| /* XXGENPCVBM */ | |
| 7283, | |
| /* XXGENPCVDM */ | |
| 7286, | |
| /* XXGENPCVHM */ | |
| 7289, | |
| /* XXGENPCVWM */ | |
| 7292, | |
| /* XXINSERTW */ | |
| 7295, | |
| /* XXLAND */ | |
| 7299, | |
| /* XXLANDC */ | |
| 7302, | |
| /* XXLEQV */ | |
| 7305, | |
| /* XXLEQVOnes */ | |
| 7308, | |
| /* XXLNAND */ | |
| 7309, | |
| /* XXLNOR */ | |
| 7312, | |
| /* XXLOR */ | |
| 7315, | |
| /* XXLORC */ | |
| 7318, | |
| /* XXLORf */ | |
| 7321, | |
| /* XXLXOR */ | |
| 7324, | |
| /* XXLXORdpz */ | |
| 7327, | |
| /* XXLXORspz */ | |
| 7328, | |
| /* XXLXORz */ | |
| 7329, | |
| /* XXMFACC */ | |
| 7330, | |
| /* XXMFACCW */ | |
| 7332, | |
| /* XXMRGHW */ | |
| 7334, | |
| /* XXMRGLW */ | |
| 7337, | |
| /* XXMTACC */ | |
| 7340, | |
| /* XXMTACCW */ | |
| 7342, | |
| /* XXPERM */ | |
| 7344, | |
| /* XXPERMDI */ | |
| 7348, | |
| /* XXPERMDIs */ | |
| 7352, | |
| /* XXPERMR */ | |
| 7355, | |
| /* XXPERMX */ | |
| 7359, | |
| /* XXSEL */ | |
| 7364, | |
| /* XXSETACCZ */ | |
| 7368, | |
| /* XXSETACCZW */ | |
| 7369, | |
| /* XXSLDWI */ | |
| 7370, | |
| /* XXSLDWIs */ | |
| 7374, | |
| /* XXSPLTI32DX */ | |
| 7377, | |
| /* XXSPLTIB */ | |
| 7381, | |
| /* XXSPLTIDP */ | |
| 7383, | |
| /* XXSPLTIW */ | |
| 7385, | |
| /* XXSPLTW */ | |
| 7387, | |
| /* XXSPLTWs */ | |
| 7390, | |
| /* gBC */ | |
| 7393, | |
| /* gBCA */ | |
| 7396, | |
| /* gBCAat */ | |
| 7399, | |
| /* gBCCTR */ | |
| 7403, | |
| /* gBCCTRL */ | |
| 7406, | |
| /* gBCL */ | |
| 7409, | |
| /* gBCLA */ | |
| 7412, | |
| /* gBCLAat */ | |
| 7415, | |
| /* gBCLR */ | |
| 7419, | |
| /* gBCLRL */ | |
| 7422, | |
| /* gBCLat */ | |
| 7425, | |
| /* gBCat */ | |
| 7429, | |
| }; | |
| using namespace OpTypes; | |
| const int16_t OpcodeOperandTypes[] = { | |
| /* PHI */ | |
| -1, | |
| /* INLINEASM */ | |
| /* INLINEASM_BR */ | |
| /* CFI_INSTRUCTION */ | |
| i32imm, | |
| /* EH_LABEL */ | |
| i32imm, | |
| /* GC_LABEL */ | |
| i32imm, | |
| /* ANNOTATION_LABEL */ | |
| i32imm, | |
| /* KILL */ | |
| /* EXTRACT_SUBREG */ | |
| -1, -1, i32imm, | |
| /* INSERT_SUBREG */ | |
| -1, -1, -1, i32imm, | |
| /* IMPLICIT_DEF */ | |
| -1, | |
| /* SUBREG_TO_REG */ | |
| -1, -1, -1, i32imm, | |
| /* COPY_TO_REGCLASS */ | |
| -1, -1, i32imm, | |
| /* DBG_VALUE */ | |
| /* DBG_VALUE_LIST */ | |
| /* DBG_INSTR_REF */ | |
| /* DBG_PHI */ | |
| /* DBG_LABEL */ | |
| -1, | |
| /* REG_SEQUENCE */ | |
| -1, -1, | |
| /* COPY */ | |
| -1, -1, | |
| /* BUNDLE */ | |
| /* LIFETIME_START */ | |
| i32imm, | |
| /* LIFETIME_END */ | |
| i32imm, | |
| /* PSEUDO_PROBE */ | |
| i64imm, i64imm, i8imm, i32imm, | |
| /* ARITH_FENCE */ | |
| -1, -1, | |
| /* STACKMAP */ | |
| i64imm, i32imm, | |
| /* FENTRY_CALL */ | |
| /* PATCHPOINT */ | |
| -1, i64imm, i32imm, -1, i32imm, i32imm, | |
| /* LOAD_STACK_GUARD */ | |
| -1, | |
| /* PREALLOCATED_SETUP */ | |
| i32imm, | |
| /* PREALLOCATED_ARG */ | |
| -1, i32imm, i32imm, | |
| /* STATEPOINT */ | |
| /* LOCAL_ESCAPE */ | |
| -1, i32imm, | |
| /* FAULTING_OP */ | |
| -1, | |
| /* PATCHABLE_OP */ | |
| /* PATCHABLE_FUNCTION_ENTER */ | |
| /* PATCHABLE_RET */ | |
| /* PATCHABLE_FUNCTION_EXIT */ | |
| /* PATCHABLE_TAIL_CALL */ | |
| /* PATCHABLE_EVENT_CALL */ | |
| -1, -1, | |
| /* PATCHABLE_TYPED_EVENT_CALL */ | |
| -1, -1, -1, | |
| /* ICALL_BRANCH_FUNNEL */ | |
| /* MEMBARRIER */ | |
| /* G_ASSERT_SEXT */ | |
| type0, type0, untyped_imm_0, | |
| /* G_ASSERT_ZEXT */ | |
| type0, type0, untyped_imm_0, | |
| /* G_ASSERT_ALIGN */ | |
| type0, type0, untyped_imm_0, | |
| /* G_ADD */ | |
| type0, type0, type0, | |
| /* G_SUB */ | |
| type0, type0, type0, | |
| /* G_MUL */ | |
| type0, type0, type0, | |
| /* G_SDIV */ | |
| type0, type0, type0, | |
| /* G_UDIV */ | |
| type0, type0, type0, | |
| /* G_SREM */ | |
| type0, type0, type0, | |
| /* G_UREM */ | |
| type0, type0, type0, | |
| /* G_SDIVREM */ | |
| type0, type0, type0, type0, | |
| /* G_UDIVREM */ | |
| type0, type0, type0, type0, | |
| /* G_AND */ | |
| type0, type0, type0, | |
| /* G_OR */ | |
| type0, type0, type0, | |
| /* G_XOR */ | |
| type0, type0, type0, | |
| /* G_IMPLICIT_DEF */ | |
| type0, | |
| /* G_PHI */ | |
| type0, | |
| /* G_FRAME_INDEX */ | |
| type0, -1, | |
| /* G_GLOBAL_VALUE */ | |
| type0, -1, | |
| /* G_EXTRACT */ | |
| type0, type1, untyped_imm_0, | |
| /* G_UNMERGE_VALUES */ | |
| type0, type1, | |
| /* G_INSERT */ | |
| type0, type0, type1, untyped_imm_0, | |
| /* G_MERGE_VALUES */ | |
| type0, type1, | |
| /* G_BUILD_VECTOR */ | |
| type0, type1, | |
| /* G_BUILD_VECTOR_TRUNC */ | |
| type0, type1, | |
| /* G_CONCAT_VECTORS */ | |
| type0, type1, | |
| /* G_PTRTOINT */ | |
| type0, type1, | |
| /* G_INTTOPTR */ | |
| type0, type1, | |
| /* G_BITCAST */ | |
| type0, type1, | |
| /* G_FREEZE */ | |
| type0, type0, | |
| /* G_INTRINSIC_FPTRUNC_ROUND */ | |
| type0, type1, i32imm, | |
| /* G_INTRINSIC_TRUNC */ | |
| type0, type0, | |
| /* G_INTRINSIC_ROUND */ | |
| type0, type0, | |
| /* G_INTRINSIC_LRINT */ | |
| type0, type1, | |
| /* G_INTRINSIC_ROUNDEVEN */ | |
| type0, type0, | |
| /* G_READCYCLECOUNTER */ | |
| type0, | |
| /* G_LOAD */ | |
| type0, ptype1, | |
| /* G_SEXTLOAD */ | |
| type0, ptype1, | |
| /* G_ZEXTLOAD */ | |
| type0, ptype1, | |
| /* G_INDEXED_LOAD */ | |
| type0, ptype1, ptype1, type2, -1, | |
| /* G_INDEXED_SEXTLOAD */ | |
| type0, ptype1, ptype1, type2, -1, | |
| /* G_INDEXED_ZEXTLOAD */ | |
| type0, ptype1, ptype1, type2, -1, | |
| /* G_STORE */ | |
| type0, ptype1, | |
| /* G_INDEXED_STORE */ | |
| ptype0, type1, ptype0, ptype2, -1, | |
| /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ | |
| type0, type1, type2, type0, type0, | |
| /* G_ATOMIC_CMPXCHG */ | |
| type0, ptype1, type0, type0, | |
| /* G_ATOMICRMW_XCHG */ | |
| type0, ptype1, type0, | |
| /* G_ATOMICRMW_ADD */ | |
| type0, ptype1, type0, | |
| /* G_ATOMICRMW_SUB */ | |
| type0, ptype1, type0, | |
| /* G_ATOMICRMW_AND */ | |
| type0, ptype1, type0, | |
| /* G_ATOMICRMW_NAND */ | |
| type0, ptype1, type0, | |
| /* G_ATOMICRMW_OR */ | |
| type0, ptype1, type0, | |
| /* G_ATOMICRMW_XOR */ | |
| type0, ptype1, type0, | |
| /* G_ATOMICRMW_MAX */ | |
| type0, ptype1, type0, | |
| /* G_ATOMICRMW_MIN */ | |
| type0, ptype1, type0, | |
| /* G_ATOMICRMW_UMAX */ | |
| type0, ptype1, type0, | |
| /* G_ATOMICRMW_UMIN */ | |
| type0, ptype1, type0, | |
| /* G_ATOMICRMW_FADD */ | |
| type0, ptype1, type0, | |
| /* G_ATOMICRMW_FSUB */ | |
| type0, ptype1, type0, | |
| /* G_ATOMICRMW_FMAX */ | |
| type0, ptype1, type0, | |
| /* G_ATOMICRMW_FMIN */ | |
| type0, ptype1, type0, | |
| /* G_ATOMICRMW_UINC_WRAP */ | |
| type0, ptype1, type0, | |
| /* G_ATOMICRMW_UDEC_WRAP */ | |
| type0, ptype1, type0, | |
| /* G_FENCE */ | |
| i32imm, i32imm, | |
| /* G_BRCOND */ | |
| type0, -1, | |
| /* G_BRINDIRECT */ | |
| type0, | |
| /* G_INVOKE_REGION_START */ | |
| /* G_INTRINSIC */ | |
| -1, | |
| /* G_INTRINSIC_W_SIDE_EFFECTS */ | |
| -1, | |
| /* G_ANYEXT */ | |
| type0, type1, | |
| /* G_TRUNC */ | |
| type0, type1, | |
| /* G_CONSTANT */ | |
| type0, -1, | |
| /* G_FCONSTANT */ | |
| type0, -1, | |
| /* G_VASTART */ | |
| type0, | |
| /* G_VAARG */ | |
| type0, type1, -1, | |
| /* G_SEXT */ | |
| type0, type1, | |
| /* G_SEXT_INREG */ | |
| type0, type0, untyped_imm_0, | |
| /* G_ZEXT */ | |
| type0, type1, | |
| /* G_SHL */ | |
| type0, type0, type1, | |
| /* G_LSHR */ | |
| type0, type0, type1, | |
| /* G_ASHR */ | |
| type0, type0, type1, | |
| /* G_FSHL */ | |
| type0, type0, type0, type1, | |
| /* G_FSHR */ | |
| type0, type0, type0, type1, | |
| /* G_ROTR */ | |
| type0, type0, type1, | |
| /* G_ROTL */ | |
| type0, type0, type1, | |
| /* G_ICMP */ | |
| type0, -1, type1, type1, | |
| /* G_FCMP */ | |
| type0, -1, type1, type1, | |
| /* G_SELECT */ | |
| type0, type1, type0, type0, | |
| /* G_UADDO */ | |
| type0, type1, type0, type0, | |
| /* G_UADDE */ | |
| type0, type1, type0, type0, type1, | |
| /* G_USUBO */ | |
| type0, type1, type0, type0, | |
| /* G_USUBE */ | |
| type0, type1, type0, type0, type1, | |
| /* G_SADDO */ | |
| type0, type1, type0, type0, | |
| /* G_SADDE */ | |
| type0, type1, type0, type0, type1, | |
| /* G_SSUBO */ | |
| type0, type1, type0, type0, | |
| /* G_SSUBE */ | |
| type0, type1, type0, type0, type1, | |
| /* G_UMULO */ | |
| type0, type1, type0, type0, | |
| /* G_SMULO */ | |
| type0, type1, type0, type0, | |
| /* G_UMULH */ | |
| type0, type0, type0, | |
| /* G_SMULH */ | |
| type0, type0, type0, | |
| /* G_UADDSAT */ | |
| type0, type0, type0, | |
| /* G_SADDSAT */ | |
| type0, type0, type0, | |
| /* G_USUBSAT */ | |
| type0, type0, type0, | |
| /* G_SSUBSAT */ | |
| type0, type0, type0, | |
| /* G_USHLSAT */ | |
| type0, type0, type1, | |
| /* G_SSHLSAT */ | |
| type0, type0, type1, | |
| /* G_SMULFIX */ | |
| type0, type0, type0, untyped_imm_0, | |
| /* G_UMULFIX */ | |
| type0, type0, type0, untyped_imm_0, | |
| /* G_SMULFIXSAT */ | |
| type0, type0, type0, untyped_imm_0, | |
| /* G_UMULFIXSAT */ | |
| type0, type0, type0, untyped_imm_0, | |
| /* G_SDIVFIX */ | |
| type0, type0, type0, untyped_imm_0, | |
| /* G_UDIVFIX */ | |
| type0, type0, type0, untyped_imm_0, | |
| /* G_SDIVFIXSAT */ | |
| type0, type0, type0, untyped_imm_0, | |
| /* G_UDIVFIXSAT */ | |
| type0, type0, type0, untyped_imm_0, | |
| /* G_FADD */ | |
| type0, type0, type0, | |
| /* G_FSUB */ | |
| type0, type0, type0, | |
| /* G_FMUL */ | |
| type0, type0, type0, | |
| /* G_FMA */ | |
| type0, type0, type0, type0, | |
| /* G_FMAD */ | |
| type0, type0, type0, type0, | |
| /* G_FDIV */ | |
| type0, type0, type0, | |
| /* G_FREM */ | |
| type0, type0, type0, | |
| /* G_FPOW */ | |
| type0, type0, type0, | |
| /* G_FPOWI */ | |
| type0, type0, type1, | |
| /* G_FEXP */ | |
| type0, type0, | |
| /* G_FEXP2 */ | |
| type0, type0, | |
| /* G_FLOG */ | |
| type0, type0, | |
| /* G_FLOG2 */ | |
| type0, type0, | |
| /* G_FLOG10 */ | |
| type0, type0, | |
| /* G_FNEG */ | |
| type0, type0, | |
| /* G_FPEXT */ | |
| type0, type1, | |
| /* G_FPTRUNC */ | |
| type0, type1, | |
| /* G_FPTOSI */ | |
| type0, type1, | |
| /* G_FPTOUI */ | |
| type0, type1, | |
| /* G_SITOFP */ | |
| type0, type1, | |
| /* G_UITOFP */ | |
| type0, type1, | |
| /* G_FABS */ | |
| type0, type0, | |
| /* G_FCOPYSIGN */ | |
| type0, type0, type1, | |
| /* G_IS_FPCLASS */ | |
| type0, type1, -1, | |
| /* G_FCANONICALIZE */ | |
| type0, type0, | |
| /* G_FMINNUM */ | |
| type0, type0, type0, | |
| /* G_FMAXNUM */ | |
| type0, type0, type0, | |
| /* G_FMINNUM_IEEE */ | |
| type0, type0, type0, | |
| /* G_FMAXNUM_IEEE */ | |
| type0, type0, type0, | |
| /* G_FMINIMUM */ | |
| type0, type0, type0, | |
| /* G_FMAXIMUM */ | |
| type0, type0, type0, | |
| /* G_PTR_ADD */ | |
| ptype0, ptype0, type1, | |
| /* G_PTRMASK */ | |
| ptype0, ptype0, type1, | |
| /* G_SMIN */ | |
| type0, type0, type0, | |
| /* G_SMAX */ | |
| type0, type0, type0, | |
| /* G_UMIN */ | |
| type0, type0, type0, | |
| /* G_UMAX */ | |
| type0, type0, type0, | |
| /* G_ABS */ | |
| type0, type0, | |
| /* G_LROUND */ | |
| type0, type1, | |
| /* G_LLROUND */ | |
| type0, type1, | |
| /* G_BR */ | |
| -1, | |
| /* G_BRJT */ | |
| ptype0, -1, type1, | |
| /* G_INSERT_VECTOR_ELT */ | |
| type0, type0, type1, type2, | |
| /* G_EXTRACT_VECTOR_ELT */ | |
| type0, type1, type2, | |
| /* G_SHUFFLE_VECTOR */ | |
| type0, type1, type1, -1, | |
| /* G_CTTZ */ | |
| type0, type1, | |
| /* G_CTTZ_ZERO_UNDEF */ | |
| type0, type1, | |
| /* G_CTLZ */ | |
| type0, type1, | |
| /* G_CTLZ_ZERO_UNDEF */ | |
| type0, type1, | |
| /* G_CTPOP */ | |
| type0, type1, | |
| /* G_BSWAP */ | |
| type0, type0, | |
| /* G_BITREVERSE */ | |
| type0, type0, | |
| /* G_FCEIL */ | |
| type0, type0, | |
| /* G_FCOS */ | |
| type0, type0, | |
| /* G_FSIN */ | |
| type0, type0, | |
| /* G_FSQRT */ | |
| type0, type0, | |
| /* G_FFLOOR */ | |
| type0, type0, | |
| /* G_FRINT */ | |
| type0, type0, | |
| /* G_FNEARBYINT */ | |
| type0, type0, | |
| /* G_ADDRSPACE_CAST */ | |
| type0, type1, | |
| /* G_BLOCK_ADDR */ | |
| type0, -1, | |
| /* G_JUMP_TABLE */ | |
| type0, -1, | |
| /* G_DYN_STACKALLOC */ | |
| ptype0, type1, i32imm, | |
| /* G_STRICT_FADD */ | |
| type0, type0, type0, | |
| /* G_STRICT_FSUB */ | |
| type0, type0, type0, | |
| /* G_STRICT_FMUL */ | |
| type0, type0, type0, | |
| /* G_STRICT_FDIV */ | |
| type0, type0, type0, | |
| /* G_STRICT_FREM */ | |
| type0, type0, type0, | |
| /* G_STRICT_FMA */ | |
| type0, type0, type0, type0, | |
| /* G_STRICT_FSQRT */ | |
| type0, type0, | |
| /* G_READ_REGISTER */ | |
| type0, -1, | |
| /* G_WRITE_REGISTER */ | |
| -1, type0, | |
| /* G_MEMCPY */ | |
| ptype0, ptype1, type2, untyped_imm_0, | |
| /* G_MEMCPY_INLINE */ | |
| ptype0, ptype1, type2, | |
| /* G_MEMMOVE */ | |
| ptype0, ptype1, type2, untyped_imm_0, | |
| /* G_MEMSET */ | |
| ptype0, type1, type2, untyped_imm_0, | |
| /* G_BZERO */ | |
| ptype0, type1, untyped_imm_0, | |
| /* G_VECREDUCE_SEQ_FADD */ | |
| type0, type1, type2, | |
| /* G_VECREDUCE_SEQ_FMUL */ | |
| type0, type1, type2, | |
| /* G_VECREDUCE_FADD */ | |
| type0, type1, | |
| /* G_VECREDUCE_FMUL */ | |
| type0, type1, | |
| /* G_VECREDUCE_FMAX */ | |
| type0, type1, | |
| /* G_VECREDUCE_FMIN */ | |
| type0, type1, | |
| /* G_VECREDUCE_ADD */ | |
| type0, type1, | |
| /* G_VECREDUCE_MUL */ | |
| type0, type1, | |
| /* G_VECREDUCE_AND */ | |
| type0, type1, | |
| /* G_VECREDUCE_OR */ | |
| type0, type1, | |
| /* G_VECREDUCE_XOR */ | |
| type0, type1, | |
| /* G_VECREDUCE_SMAX */ | |
| type0, type1, | |
| /* G_VECREDUCE_SMIN */ | |
| type0, type1, | |
| /* G_VECREDUCE_UMAX */ | |
| type0, type1, | |
| /* G_VECREDUCE_UMIN */ | |
| type0, type1, | |
| /* G_SBFX */ | |
| type0, type0, type1, type1, | |
| /* G_UBFX */ | |
| type0, type0, type1, type1, | |
| /* ATOMIC_CMP_SWAP_I128 */ | |
| g8prc, g8prc, ptr_rc_nor0, ptr_rc_idx, g8rc, g8rc, g8rc, g8rc, | |
| /* ATOMIC_LOAD_ADD_I128 */ | |
| g8prc, g8prc, ptr_rc_nor0, ptr_rc_idx, g8rc, g8rc, | |
| /* ATOMIC_LOAD_AND_I128 */ | |
| g8prc, g8prc, ptr_rc_nor0, ptr_rc_idx, g8rc, g8rc, | |
| /* ATOMIC_LOAD_NAND_I128 */ | |
| g8prc, g8prc, ptr_rc_nor0, ptr_rc_idx, g8rc, g8rc, | |
| /* ATOMIC_LOAD_OR_I128 */ | |
| g8prc, g8prc, ptr_rc_nor0, ptr_rc_idx, g8rc, g8rc, | |
| /* ATOMIC_LOAD_SUB_I128 */ | |
| g8prc, g8prc, ptr_rc_nor0, ptr_rc_idx, g8rc, g8rc, | |
| /* ATOMIC_LOAD_XOR_I128 */ | |
| g8prc, g8prc, ptr_rc_nor0, ptr_rc_idx, g8rc, g8rc, | |
| /* ATOMIC_SWAP_I128 */ | |
| g8prc, g8prc, ptr_rc_nor0, ptr_rc_idx, g8rc, g8rc, | |
| /* BUILD_QUADWORD */ | |
| g8prc, g8rc, g8rc, | |
| /* BUILD_UACC */ | |
| acc, uacc, | |
| /* CFENCE8 */ | |
| g8rc, | |
| /* CLRLSLDI */ | |
| g8rc, g8rc, u6imm, u6imm, | |
| /* CLRLSLDI_rec */ | |
| g8rc, g8rc, u6imm, u6imm, | |
| /* CLRLSLWI */ | |
| gprc, gprc, u5imm, u5imm, | |
| /* CLRLSLWI_rec */ | |
| gprc, gprc, u5imm, u5imm, | |
| /* CLRRDI */ | |
| g8rc, g8rc, u6imm, | |
| /* CLRRDI_rec */ | |
| g8rc, g8rc, u6imm, | |
| /* CLRRWI */ | |
| gprc, gprc, u5imm, | |
| /* CLRRWI_rec */ | |
| gprc, gprc, u5imm, | |
| /* DCBFL */ | |
| ptr_rc_nor0, ptr_rc_idx, | |
| /* DCBFLP */ | |
| ptr_rc_nor0, ptr_rc_idx, | |
| /* DCBFPS */ | |
| ptr_rc_nor0, ptr_rc_idx, | |
| /* DCBFx */ | |
| ptr_rc_nor0, ptr_rc_idx, | |
| /* DCBSTPS */ | |
| ptr_rc_nor0, ptr_rc_idx, | |
| /* DCBTCT */ | |
| ptr_rc_nor0, ptr_rc_idx, u5imm, | |
| /* DCBTDS */ | |
| ptr_rc_nor0, ptr_rc_idx, u5imm, | |
| /* DCBTSTCT */ | |
| ptr_rc_nor0, ptr_rc_idx, u5imm, | |
| /* DCBTSTDS */ | |
| ptr_rc_nor0, ptr_rc_idx, u5imm, | |
| /* DCBTSTT */ | |
| ptr_rc_nor0, ptr_rc_idx, | |
| /* DCBTSTx */ | |
| ptr_rc_nor0, ptr_rc_idx, | |
| /* DCBTT */ | |
| ptr_rc_nor0, ptr_rc_idx, | |
| /* DCBTx */ | |
| ptr_rc_nor0, ptr_rc_idx, | |
| /* DFLOADf32 */ | |
| vssrc, dispRIX, ptr_rc_nor0, | |
| /* DFLOADf64 */ | |
| vsfrc, dispRIX, ptr_rc_nor0, | |
| /* DFSTOREf32 */ | |
| vssrc, dispRIX, ptr_rc_nor0, | |
| /* DFSTOREf64 */ | |
| vsfrc, dispRIX, ptr_rc_nor0, | |
| /* EXTLDI */ | |
| g8rc, g8rc, u6imm, u6imm, | |
| /* EXTLDI_rec */ | |
| g8rc, g8rc, u6imm, u6imm, | |
| /* EXTLWI */ | |
| gprc, gprc, u5imm, u5imm, | |
| /* EXTLWI_rec */ | |
| gprc, gprc, u5imm, u5imm, | |
| /* EXTRDI */ | |
| g8rc, g8rc, u6imm, u6imm, | |
| /* EXTRDI_rec */ | |
| g8rc, g8rc, u6imm, u6imm, | |
| /* EXTRWI */ | |
| gprc, gprc, u5imm, u5imm, | |
| /* EXTRWI_rec */ | |
| gprc, gprc, u5imm, u5imm, | |
| /* INSLWI */ | |
| gprc, gprc, u5imm, u5imm, | |
| /* INSLWI_rec */ | |
| gprc, gprc, u5imm, u5imm, | |
| /* INSRDI */ | |
| g8rc, g8rc, u6imm, u6imm, | |
| /* INSRDI_rec */ | |
| g8rc, g8rc, u6imm, u6imm, | |
| /* INSRWI */ | |
| gprc, gprc, u5imm, u5imm, | |
| /* INSRWI_rec */ | |
| gprc, gprc, u5imm, u5imm, | |
| /* KILL_PAIR */ | |
| vsrprc, vsrprc, | |
| /* LAx */ | |
| gprc, dispRI, ptr_rc_nor0, | |
| /* LIWAX */ | |
| vsfrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LIWZX */ | |
| vsfrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* RLWIMIbm */ | |
| g8rc, g8rc, u5imm, i32imm, | |
| /* RLWIMIbm_rec */ | |
| g8rc, g8rc, u5imm, i32imm, | |
| /* RLWINMbm */ | |
| g8rc, g8rc, u5imm, i32imm, | |
| /* RLWINMbm_rec */ | |
| g8rc, g8rc, u5imm, i32imm, | |
| /* RLWNMbm */ | |
| g8rc, g8rc, u5imm, i32imm, | |
| /* RLWNMbm_rec */ | |
| g8rc, g8rc, u5imm, i32imm, | |
| /* ROTRDI */ | |
| g8rc, g8rc, u6imm, | |
| /* ROTRDI_rec */ | |
| g8rc, g8rc, u6imm, | |
| /* ROTRWI */ | |
| gprc, gprc, u5imm, | |
| /* ROTRWI_rec */ | |
| gprc, gprc, u5imm, | |
| /* SLDI */ | |
| g8rc, g8rc, u6imm, | |
| /* SLDI_rec */ | |
| g8rc, g8rc, u6imm, | |
| /* SLWI */ | |
| gprc, gprc, u5imm, | |
| /* SLWI_rec */ | |
| gprc, gprc, u5imm, | |
| /* SPILLTOVSR_LD */ | |
| spilltovsrrc, dispRIX, ptr_rc_nor0, | |
| /* SPILLTOVSR_LDX */ | |
| spilltovsrrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* SPILLTOVSR_ST */ | |
| spilltovsrrc, dispRIX, ptr_rc_nor0, | |
| /* SPILLTOVSR_STX */ | |
| spilltovsrrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* SRDI */ | |
| g8rc, g8rc, u6imm, | |
| /* SRDI_rec */ | |
| g8rc, g8rc, u6imm, | |
| /* SRWI */ | |
| gprc, gprc, u5imm, | |
| /* SRWI_rec */ | |
| gprc, gprc, u5imm, | |
| /* STIWX */ | |
| vsfrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* SUBI */ | |
| gprc, gprc, s16imm, | |
| /* SUBIC */ | |
| gprc, gprc, s16imm, | |
| /* SUBIC_rec */ | |
| gprc, gprc, s16imm, | |
| /* SUBIS */ | |
| gprc, gprc, s16imm, | |
| /* SUBPCIS */ | |
| g8rc, s16imm, | |
| /* XFLOADf32 */ | |
| vssrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* XFLOADf64 */ | |
| vsfrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* XFSTOREf32 */ | |
| vssrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* XFSTOREf64 */ | |
| vsfrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* ADD4 */ | |
| gprc, gprc, gprc, | |
| /* ADD4O */ | |
| gprc, gprc, gprc, | |
| /* ADD4O_rec */ | |
| gprc, gprc, gprc, | |
| /* ADD4TLS */ | |
| gprc, gprc, tlsreg32, | |
| /* ADD4_rec */ | |
| gprc, gprc, gprc, | |
| /* ADD8 */ | |
| g8rc, g8rc, g8rc, | |
| /* ADD8O */ | |
| g8rc, g8rc, g8rc, | |
| /* ADD8O_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* ADD8TLS */ | |
| g8rc, g8rc_nox0, tlsreg, | |
| /* ADD8TLS_ */ | |
| g8rc, g8rc, tlsreg, | |
| /* ADD8_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* ADDC */ | |
| gprc, gprc, gprc, | |
| /* ADDC8 */ | |
| g8rc, g8rc, g8rc, | |
| /* ADDC8O */ | |
| g8rc, g8rc, g8rc, | |
| /* ADDC8O_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* ADDC8_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* ADDCO */ | |
| gprc, gprc, gprc, | |
| /* ADDCO_rec */ | |
| gprc, gprc, gprc, | |
| /* ADDC_rec */ | |
| gprc, gprc, gprc, | |
| /* ADDE */ | |
| gprc, gprc, gprc, | |
| /* ADDE8 */ | |
| g8rc, g8rc, g8rc, | |
| /* ADDE8O */ | |
| g8rc, g8rc, g8rc, | |
| /* ADDE8O_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* ADDE8_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* ADDEO */ | |
| gprc, gprc, gprc, | |
| /* ADDEO_rec */ | |
| gprc, gprc, gprc, | |
| /* ADDEX */ | |
| gprc, gprc, gprc, u2imm, | |
| /* ADDEX8 */ | |
| g8rc, g8rc, g8rc, u2imm, | |
| /* ADDE_rec */ | |
| gprc, gprc, gprc, | |
| /* ADDI */ | |
| gprc, gprc_nor0, s16imm, | |
| /* ADDI8 */ | |
| g8rc, g8rc_nox0, s16imm64, | |
| /* ADDIC */ | |
| gprc, gprc, s16imm, | |
| /* ADDIC8 */ | |
| g8rc, g8rc, s16imm64, | |
| /* ADDIC_rec */ | |
| gprc, gprc, s16imm, | |
| /* ADDIS */ | |
| gprc, gprc_nor0, s17imm, | |
| /* ADDIS8 */ | |
| g8rc, g8rc_nox0, s17imm64, | |
| /* ADDISdtprelHA */ | |
| g8rc, g8rc_nox0, s16imm64, | |
| /* ADDISdtprelHA32 */ | |
| gprc, gprc_nor0, s16imm, | |
| /* ADDISgotTprelHA */ | |
| g8rc, g8rc_nox0, s16imm64, | |
| /* ADDIStlsgdHA */ | |
| g8rc, g8rc_nox0, s16imm64, | |
| /* ADDIStlsldHA */ | |
| g8rc, g8rc_nox0, s16imm64, | |
| /* ADDIStocHA */ | |
| gprc, gprc_nor0, i32imm, | |
| /* ADDIStocHA8 */ | |
| g8rc, g8rc_nox0, i64imm, | |
| /* ADDIdtprelL */ | |
| g8rc, g8rc_nox0, s16imm64, | |
| /* ADDIdtprelL32 */ | |
| gprc, gprc_nor0, s16imm, | |
| /* ADDItlsgdL */ | |
| g8rc, g8rc_nox0, s16imm64, | |
| /* ADDItlsgdL32 */ | |
| gprc, gprc_nor0, s16imm, | |
| /* ADDItlsgdLADDR */ | |
| g8rc, g8rc_nox0, s16imm64, tlsgd, | |
| /* ADDItlsgdLADDR32 */ | |
| gprc, gprc_nor0, s16imm, tlsgd32, | |
| /* ADDItlsldL */ | |
| g8rc, g8rc_nox0, s16imm64, | |
| /* ADDItlsldL32 */ | |
| gprc, gprc_nor0, s16imm, | |
| /* ADDItlsldLADDR */ | |
| g8rc, g8rc_nox0, s16imm64, tlsgd, | |
| /* ADDItlsldLADDR32 */ | |
| gprc, gprc_nor0, s16imm, tlsgd32, | |
| /* ADDItoc */ | |
| gprc, i32imm, gprc, | |
| /* ADDItoc8 */ | |
| g8rc, i64imm, g8rc_nox0, | |
| /* ADDItocL */ | |
| g8rc, g8rc_nox0, i64imm, | |
| /* ADDME */ | |
| gprc, gprc, | |
| /* ADDME8 */ | |
| g8rc, g8rc, | |
| /* ADDME8O */ | |
| g8rc, g8rc, | |
| /* ADDME8O_rec */ | |
| g8rc, g8rc, | |
| /* ADDME8_rec */ | |
| g8rc, g8rc, | |
| /* ADDMEO */ | |
| gprc, gprc, | |
| /* ADDMEO_rec */ | |
| gprc, gprc, | |
| /* ADDME_rec */ | |
| gprc, gprc, | |
| /* ADDPCIS */ | |
| g8rc, i32imm, | |
| /* ADDZE */ | |
| gprc, gprc, | |
| /* ADDZE8 */ | |
| g8rc, g8rc, | |
| /* ADDZE8O */ | |
| g8rc, g8rc, | |
| /* ADDZE8O_rec */ | |
| g8rc, g8rc, | |
| /* ADDZE8_rec */ | |
| g8rc, g8rc, | |
| /* ADDZEO */ | |
| gprc, gprc, | |
| /* ADDZEO_rec */ | |
| gprc, gprc, | |
| /* ADDZE_rec */ | |
| gprc, gprc, | |
| /* ADJCALLSTACKDOWN */ | |
| u16imm, u16imm, | |
| /* ADJCALLSTACKUP */ | |
| u16imm, u16imm, | |
| /* AND */ | |
| gprc, gprc, gprc, | |
| /* AND8 */ | |
| g8rc, g8rc, g8rc, | |
| /* AND8_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* ANDC */ | |
| gprc, gprc, gprc, | |
| /* ANDC8 */ | |
| g8rc, g8rc, g8rc, | |
| /* ANDC8_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* ANDC_rec */ | |
| gprc, gprc, gprc, | |
| /* ANDI8_rec */ | |
| g8rc, g8rc, u16imm64, | |
| /* ANDIS8_rec */ | |
| g8rc, g8rc, u16imm64, | |
| /* ANDIS_rec */ | |
| gprc, gprc, u16imm, | |
| /* ANDI_rec */ | |
| gprc, gprc, u16imm, | |
| /* ANDI_rec_1_EQ_BIT */ | |
| crbitrc, gprc, | |
| /* ANDI_rec_1_EQ_BIT8 */ | |
| crbitrc, g8rc, | |
| /* ANDI_rec_1_GT_BIT */ | |
| crbitrc, gprc, | |
| /* ANDI_rec_1_GT_BIT8 */ | |
| crbitrc, g8rc, | |
| /* AND_rec */ | |
| gprc, gprc, gprc, | |
| /* ATOMIC_CMP_SWAP_I16 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, gprc, | |
| /* ATOMIC_CMP_SWAP_I32 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, gprc, | |
| /* ATOMIC_CMP_SWAP_I64 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, g8rc, g8rc, | |
| /* ATOMIC_CMP_SWAP_I8 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, gprc, | |
| /* ATOMIC_LOAD_ADD_I16 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_ADD_I32 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_ADD_I64 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, g8rc, | |
| /* ATOMIC_LOAD_ADD_I8 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_AND_I16 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_AND_I32 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_AND_I64 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, g8rc, | |
| /* ATOMIC_LOAD_AND_I8 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_MAX_I16 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_MAX_I32 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_MAX_I64 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, g8rc, | |
| /* ATOMIC_LOAD_MAX_I8 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_MIN_I16 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_MIN_I32 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_MIN_I64 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, g8rc, | |
| /* ATOMIC_LOAD_MIN_I8 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_NAND_I16 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_NAND_I32 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_NAND_I64 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, g8rc, | |
| /* ATOMIC_LOAD_NAND_I8 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_OR_I16 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_OR_I32 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_OR_I64 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, g8rc, | |
| /* ATOMIC_LOAD_OR_I8 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_SUB_I16 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_SUB_I32 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_SUB_I64 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, g8rc, | |
| /* ATOMIC_LOAD_SUB_I8 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_UMAX_I16 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_UMAX_I32 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_UMAX_I64 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, g8rc, | |
| /* ATOMIC_LOAD_UMAX_I8 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_UMIN_I16 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_UMIN_I32 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_UMIN_I64 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, g8rc, | |
| /* ATOMIC_LOAD_UMIN_I8 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_XOR_I16 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_XOR_I32 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_LOAD_XOR_I64 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, g8rc, | |
| /* ATOMIC_LOAD_XOR_I8 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_SWAP_I16 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_SWAP_I32 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATOMIC_SWAP_I64 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, g8rc, | |
| /* ATOMIC_SWAP_I8 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, gprc, | |
| /* ATTN */ | |
| /* B */ | |
| directbrtarget, | |
| /* BA */ | |
| absdirectbrtarget, | |
| /* BC */ | |
| crbitrc, condbrtarget, | |
| /* BCC */ | |
| i32imm, crrc, condbrtarget, | |
| /* BCCA */ | |
| i32imm, crrc, abscondbrtarget, | |
| /* BCCCTR */ | |
| i32imm, crrc, | |
| /* BCCCTR8 */ | |
| i32imm, crrc, | |
| /* BCCCTRL */ | |
| i32imm, crrc, | |
| /* BCCCTRL8 */ | |
| i32imm, crrc, | |
| /* BCCL */ | |
| i32imm, crrc, condbrtarget, | |
| /* BCCLA */ | |
| i32imm, crrc, abscondbrtarget, | |
| /* BCCLR */ | |
| i32imm, crrc, | |
| /* BCCLRL */ | |
| i32imm, crrc, | |
| /* BCCTR */ | |
| crbitrc, | |
| /* BCCTR8 */ | |
| crbitrc, | |
| /* BCCTR8n */ | |
| crbitrc, | |
| /* BCCTRL */ | |
| crbitrc, | |
| /* BCCTRL8 */ | |
| crbitrc, | |
| /* BCCTRL8n */ | |
| crbitrc, | |
| /* BCCTRLn */ | |
| crbitrc, | |
| /* BCCTRn */ | |
| crbitrc, | |
| /* BCDADD_rec */ | |
| vrrc, vrrc, vrrc, u1imm, | |
| /* BCDCFN_rec */ | |
| vrrc, vrrc, u1imm, | |
| /* BCDCFSQ_rec */ | |
| vrrc, vrrc, u1imm, | |
| /* BCDCFZ_rec */ | |
| vrrc, vrrc, u1imm, | |
| /* BCDCPSGN_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* BCDCTN_rec */ | |
| vrrc, vrrc, | |
| /* BCDCTSQ_rec */ | |
| vrrc, vrrc, | |
| /* BCDCTZ_rec */ | |
| vrrc, vrrc, u1imm, | |
| /* BCDSETSGN_rec */ | |
| vrrc, vrrc, u1imm, | |
| /* BCDSR_rec */ | |
| vrrc, vrrc, vrrc, u1imm, | |
| /* BCDSUB_rec */ | |
| vrrc, vrrc, vrrc, u1imm, | |
| /* BCDS_rec */ | |
| vrrc, vrrc, vrrc, u1imm, | |
| /* BCDTRUNC_rec */ | |
| vrrc, vrrc, vrrc, u1imm, | |
| /* BCDUS_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* BCDUTRUNC_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* BCL */ | |
| crbitrc, condbrtarget, | |
| /* BCLR */ | |
| crbitrc, | |
| /* BCLRL */ | |
| crbitrc, | |
| /* BCLRLn */ | |
| crbitrc, | |
| /* BCLRn */ | |
| crbitrc, | |
| /* BCLalways */ | |
| condbrtarget, | |
| /* BCLn */ | |
| crbitrc, condbrtarget, | |
| /* BCTR */ | |
| /* BCTR8 */ | |
| /* BCTRL */ | |
| /* BCTRL8 */ | |
| /* BCTRL8_LDinto_toc */ | |
| dispRIX, ptr_rc_nor0, | |
| /* BCTRL8_LDinto_toc_RM */ | |
| dispRIX, ptr_rc_nor0, | |
| /* BCTRL8_RM */ | |
| /* BCTRL_LWZinto_toc */ | |
| dispRI, ptr_rc_nor0, | |
| /* BCTRL_LWZinto_toc_RM */ | |
| dispRI, ptr_rc_nor0, | |
| /* BCTRL_RM */ | |
| /* BCn */ | |
| crbitrc, condbrtarget, | |
| /* BDNZ */ | |
| condbrtarget, | |
| /* BDNZ8 */ | |
| condbrtarget, | |
| /* BDNZA */ | |
| abscondbrtarget, | |
| /* BDNZAm */ | |
| abscondbrtarget, | |
| /* BDNZAp */ | |
| abscondbrtarget, | |
| /* BDNZL */ | |
| condbrtarget, | |
| /* BDNZLA */ | |
| abscondbrtarget, | |
| /* BDNZLAm */ | |
| abscondbrtarget, | |
| /* BDNZLAp */ | |
| abscondbrtarget, | |
| /* BDNZLR */ | |
| /* BDNZLR8 */ | |
| /* BDNZLRL */ | |
| /* BDNZLRLm */ | |
| /* BDNZLRLp */ | |
| /* BDNZLRm */ | |
| /* BDNZLRp */ | |
| /* BDNZLm */ | |
| condbrtarget, | |
| /* BDNZLp */ | |
| condbrtarget, | |
| /* BDNZm */ | |
| condbrtarget, | |
| /* BDNZp */ | |
| condbrtarget, | |
| /* BDZ */ | |
| condbrtarget, | |
| /* BDZ8 */ | |
| condbrtarget, | |
| /* BDZA */ | |
| abscondbrtarget, | |
| /* BDZAm */ | |
| abscondbrtarget, | |
| /* BDZAp */ | |
| abscondbrtarget, | |
| /* BDZL */ | |
| condbrtarget, | |
| /* BDZLA */ | |
| abscondbrtarget, | |
| /* BDZLAm */ | |
| abscondbrtarget, | |
| /* BDZLAp */ | |
| abscondbrtarget, | |
| /* BDZLR */ | |
| /* BDZLR8 */ | |
| /* BDZLRL */ | |
| /* BDZLRLm */ | |
| /* BDZLRLp */ | |
| /* BDZLRm */ | |
| /* BDZLRp */ | |
| /* BDZLm */ | |
| condbrtarget, | |
| /* BDZLp */ | |
| condbrtarget, | |
| /* BDZm */ | |
| condbrtarget, | |
| /* BDZp */ | |
| condbrtarget, | |
| /* BL */ | |
| calltarget, | |
| /* BL8 */ | |
| calltarget, | |
| /* BL8_NOP */ | |
| calltarget, | |
| /* BL8_NOP_RM */ | |
| calltarget, | |
| /* BL8_NOP_TLS */ | |
| calltarget, tlsgd, | |
| /* BL8_NOTOC */ | |
| calltarget, | |
| /* BL8_NOTOC_RM */ | |
| calltarget, | |
| /* BL8_NOTOC_TLS */ | |
| calltarget, tlsgd, | |
| /* BL8_RM */ | |
| calltarget, | |
| /* BL8_TLS */ | |
| calltarget, tlsgd, | |
| /* BL8_TLS_ */ | |
| calltarget, tlsgd, | |
| /* BLA */ | |
| abscalltarget, | |
| /* BLA8 */ | |
| abscalltarget, | |
| /* BLA8_NOP */ | |
| abscalltarget, | |
| /* BLA8_NOP_RM */ | |
| abscalltarget, | |
| /* BLA8_RM */ | |
| abscalltarget, | |
| /* BLA_RM */ | |
| abscalltarget, | |
| /* BLR */ | |
| /* BLR8 */ | |
| /* BLRL */ | |
| /* BL_NOP */ | |
| calltarget, | |
| /* BL_NOP_RM */ | |
| calltarget, | |
| /* BL_RM */ | |
| calltarget, | |
| /* BL_TLS */ | |
| calltarget, tlsgd32, | |
| /* BPERMD */ | |
| g8rc, g8rc, g8rc, | |
| /* BRD */ | |
| g8rc, g8rc, | |
| /* BRH */ | |
| gprc, gprc, | |
| /* BRH8 */ | |
| g8rc, g8rc, | |
| /* BRINC */ | |
| gprc, gprc, gprc, | |
| /* BRW */ | |
| gprc, gprc, | |
| /* BRW8 */ | |
| g8rc, g8rc, | |
| /* CFUGED */ | |
| g8rc, g8rc, g8rc, | |
| /* CLRBHRB */ | |
| /* CMPB */ | |
| gprc, gprc, gprc, | |
| /* CMPB8 */ | |
| g8rc, g8rc, g8rc, | |
| /* CMPD */ | |
| crrc, g8rc, g8rc, | |
| /* CMPDI */ | |
| crrc, g8rc, s16imm64, | |
| /* CMPEQB */ | |
| crrc, g8rc, g8rc, | |
| /* CMPLD */ | |
| crrc, g8rc, g8rc, | |
| /* CMPLDI */ | |
| crrc, g8rc, u16imm64, | |
| /* CMPLW */ | |
| crrc, gprc, gprc, | |
| /* CMPLWI */ | |
| crrc, gprc, u16imm, | |
| /* CMPRB */ | |
| crrc, u1imm, gprc, gprc, | |
| /* CMPRB8 */ | |
| crrc, u1imm, g8rc, g8rc, | |
| /* CMPW */ | |
| crrc, gprc, gprc, | |
| /* CMPWI */ | |
| crrc, gprc, s16imm, | |
| /* CNTLZD */ | |
| g8rc, g8rc, | |
| /* CNTLZDM */ | |
| g8rc, g8rc, g8rc, | |
| /* CNTLZD_rec */ | |
| g8rc, g8rc, | |
| /* CNTLZW */ | |
| gprc, gprc, | |
| /* CNTLZW8 */ | |
| g8rc, g8rc, | |
| /* CNTLZW8_rec */ | |
| g8rc, g8rc, | |
| /* CNTLZW_rec */ | |
| gprc, gprc, | |
| /* CNTTZD */ | |
| g8rc, g8rc, | |
| /* CNTTZDM */ | |
| g8rc, g8rc, g8rc, | |
| /* CNTTZD_rec */ | |
| g8rc, g8rc, | |
| /* CNTTZW */ | |
| gprc, gprc, | |
| /* CNTTZW8 */ | |
| g8rc, g8rc, | |
| /* CNTTZW8_rec */ | |
| g8rc, g8rc, | |
| /* CNTTZW_rec */ | |
| gprc, gprc, | |
| /* CP_ABORT */ | |
| /* CP_COPY */ | |
| gprc, gprc, u1imm, | |
| /* CP_COPY8 */ | |
| g8rc, g8rc, u1imm, | |
| /* CP_PASTE8_rec */ | |
| g8rc, g8rc, u1imm, | |
| /* CP_PASTE_rec */ | |
| gprc, gprc, u1imm, | |
| /* CR6SET */ | |
| /* CR6UNSET */ | |
| /* CRAND */ | |
| crbitrc, crbitrc, crbitrc, | |
| /* CRANDC */ | |
| crbitrc, crbitrc, crbitrc, | |
| /* CREQV */ | |
| crbitrc, crbitrc, crbitrc, | |
| /* CRNAND */ | |
| crbitrc, crbitrc, crbitrc, | |
| /* CRNOR */ | |
| crbitrc, crbitrc, crbitrc, | |
| /* CRNOT */ | |
| crbitrc, crbitrc, | |
| /* CROR */ | |
| crbitrc, crbitrc, crbitrc, | |
| /* CRORC */ | |
| crbitrc, crbitrc, crbitrc, | |
| /* CRSET */ | |
| crbitrc, | |
| /* CRUNSET */ | |
| crbitrc, | |
| /* CRXOR */ | |
| crbitrc, crbitrc, crbitrc, | |
| /* CTRL_DEP */ | |
| i32imm, crrc, condbrtarget, | |
| /* DARN */ | |
| g8rc, u2imm, | |
| /* DCBA */ | |
| ptr_rc_nor0, ptr_rc_idx, | |
| /* DCBF */ | |
| u3imm, ptr_rc_nor0, ptr_rc_idx, | |
| /* DCBFEP */ | |
| ptr_rc_nor0, ptr_rc_idx, | |
| /* DCBI */ | |
| ptr_rc_nor0, ptr_rc_idx, | |
| /* DCBST */ | |
| ptr_rc_nor0, ptr_rc_idx, | |
| /* DCBSTEP */ | |
| ptr_rc_nor0, ptr_rc_idx, | |
| /* DCBT */ | |
| u5imm, ptr_rc_nor0, ptr_rc_idx, | |
| /* DCBTEP */ | |
| ptr_rc_nor0, ptr_rc_idx, u5imm, | |
| /* DCBTST */ | |
| u5imm, ptr_rc_nor0, ptr_rc_idx, | |
| /* DCBTSTEP */ | |
| ptr_rc_nor0, ptr_rc_idx, u5imm, | |
| /* DCBZ */ | |
| ptr_rc_nor0, ptr_rc_idx, | |
| /* DCBZEP */ | |
| ptr_rc_nor0, ptr_rc_idx, | |
| /* DCBZL */ | |
| ptr_rc_nor0, ptr_rc_idx, | |
| /* DCBZLEP */ | |
| ptr_rc_nor0, ptr_rc_idx, | |
| /* DCCCI */ | |
| gprc, gprc, | |
| /* DIVD */ | |
| g8rc, g8rc, g8rc, | |
| /* DIVDE */ | |
| g8rc, g8rc, g8rc, | |
| /* DIVDEO */ | |
| g8rc, g8rc, g8rc, | |
| /* DIVDEO_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* DIVDEU */ | |
| g8rc, g8rc, g8rc, | |
| /* DIVDEUO */ | |
| g8rc, g8rc, g8rc, | |
| /* DIVDEUO_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* DIVDEU_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* DIVDE_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* DIVDO */ | |
| g8rc, g8rc, g8rc, | |
| /* DIVDO_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* DIVDU */ | |
| g8rc, g8rc, g8rc, | |
| /* DIVDUO */ | |
| g8rc, g8rc, g8rc, | |
| /* DIVDUO_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* DIVDU_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* DIVD_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* DIVW */ | |
| gprc, gprc, gprc, | |
| /* DIVWE */ | |
| gprc, gprc, gprc, | |
| /* DIVWEO */ | |
| gprc, gprc, gprc, | |
| /* DIVWEO_rec */ | |
| gprc, gprc, gprc, | |
| /* DIVWEU */ | |
| gprc, gprc, gprc, | |
| /* DIVWEUO */ | |
| gprc, gprc, gprc, | |
| /* DIVWEUO_rec */ | |
| gprc, gprc, gprc, | |
| /* DIVWEU_rec */ | |
| gprc, gprc, gprc, | |
| /* DIVWE_rec */ | |
| gprc, gprc, gprc, | |
| /* DIVWO */ | |
| gprc, gprc, gprc, | |
| /* DIVWO_rec */ | |
| gprc, gprc, gprc, | |
| /* DIVWU */ | |
| gprc, gprc, gprc, | |
| /* DIVWUO */ | |
| gprc, gprc, gprc, | |
| /* DIVWUO_rec */ | |
| gprc, gprc, gprc, | |
| /* DIVWU_rec */ | |
| gprc, gprc, gprc, | |
| /* DIVW_rec */ | |
| gprc, gprc, gprc, | |
| /* DMMR */ | |
| dmr, dmr, | |
| /* DMSETDMRZ */ | |
| dmr, | |
| /* DMXOR */ | |
| dmr, dmr, dmr, | |
| /* DMXXEXTFDMR256 */ | |
| vsrprc, dmrrowp, u2imm, | |
| /* DMXXEXTFDMR512 */ | |
| vsrprc, vsrprc, wacc, | |
| /* DMXXEXTFDMR512_HI */ | |
| vsrprc, vsrprc, wacc_hi, | |
| /* DMXXINSTFDMR256 */ | |
| dmrrowp, vsrprc, u2imm, | |
| /* DMXXINSTFDMR512 */ | |
| wacc, vsrprc, vsrprc, | |
| /* DMXXINSTFDMR512_HI */ | |
| wacc_hi, vsrprc, vsrprc, | |
| /* DSS */ | |
| u5imm, | |
| /* DSSALL */ | |
| /* DST */ | |
| u5imm, gprc, gprc, | |
| /* DST64 */ | |
| u5imm, g8rc, gprc, | |
| /* DSTST */ | |
| u5imm, gprc, gprc, | |
| /* DSTST64 */ | |
| u5imm, g8rc, gprc, | |
| /* DSTSTT */ | |
| u5imm, gprc, gprc, | |
| /* DSTSTT64 */ | |
| u5imm, g8rc, gprc, | |
| /* DSTT */ | |
| u5imm, gprc, gprc, | |
| /* DSTT64 */ | |
| u5imm, g8rc, gprc, | |
| /* DYNALLOC */ | |
| gprc, gprc, dispRI, ptr_rc_nor0, | |
| /* DYNALLOC8 */ | |
| g8rc, g8rc, dispRI, ptr_rc_nor0, | |
| /* DYNAREAOFFSET */ | |
| i32imm, dispRI, ptr_rc_nor0, | |
| /* DYNAREAOFFSET8 */ | |
| i64imm, dispRI, ptr_rc_nor0, | |
| /* DecreaseCTR8loop */ | |
| crbitrc, i64imm, | |
| /* DecreaseCTRloop */ | |
| crbitrc, i32imm, | |
| /* EFDABS */ | |
| sperc, sperc, | |
| /* EFDADD */ | |
| sperc, sperc, sperc, | |
| /* EFDCFS */ | |
| sperc, spe4rc, | |
| /* EFDCFSF */ | |
| sperc, spe4rc, | |
| /* EFDCFSI */ | |
| sperc, gprc, | |
| /* EFDCFSID */ | |
| sperc, gprc, | |
| /* EFDCFUF */ | |
| sperc, spe4rc, | |
| /* EFDCFUI */ | |
| sperc, gprc, | |
| /* EFDCFUID */ | |
| sperc, gprc, | |
| /* EFDCMPEQ */ | |
| crrc, sperc, sperc, | |
| /* EFDCMPGT */ | |
| crrc, sperc, sperc, | |
| /* EFDCMPLT */ | |
| crrc, sperc, sperc, | |
| /* EFDCTSF */ | |
| sperc, spe4rc, | |
| /* EFDCTSI */ | |
| gprc, sperc, | |
| /* EFDCTSIDZ */ | |
| gprc, sperc, | |
| /* EFDCTSIZ */ | |
| gprc, sperc, | |
| /* EFDCTUF */ | |
| sperc, spe4rc, | |
| /* EFDCTUI */ | |
| gprc, sperc, | |
| /* EFDCTUIDZ */ | |
| gprc, sperc, | |
| /* EFDCTUIZ */ | |
| gprc, sperc, | |
| /* EFDDIV */ | |
| sperc, sperc, sperc, | |
| /* EFDMUL */ | |
| sperc, sperc, sperc, | |
| /* EFDNABS */ | |
| sperc, sperc, | |
| /* EFDNEG */ | |
| sperc, sperc, | |
| /* EFDSUB */ | |
| sperc, sperc, sperc, | |
| /* EFDTSTEQ */ | |
| crrc, sperc, sperc, | |
| /* EFDTSTGT */ | |
| crrc, sperc, sperc, | |
| /* EFDTSTLT */ | |
| crrc, sperc, sperc, | |
| /* EFSABS */ | |
| spe4rc, spe4rc, | |
| /* EFSADD */ | |
| spe4rc, spe4rc, spe4rc, | |
| /* EFSCFD */ | |
| spe4rc, sperc, | |
| /* EFSCFSF */ | |
| spe4rc, spe4rc, | |
| /* EFSCFSI */ | |
| spe4rc, gprc, | |
| /* EFSCFUF */ | |
| spe4rc, spe4rc, | |
| /* EFSCFUI */ | |
| spe4rc, gprc, | |
| /* EFSCMPEQ */ | |
| crrc, spe4rc, spe4rc, | |
| /* EFSCMPGT */ | |
| crrc, spe4rc, spe4rc, | |
| /* EFSCMPLT */ | |
| crrc, spe4rc, spe4rc, | |
| /* EFSCTSF */ | |
| spe4rc, spe4rc, | |
| /* EFSCTSI */ | |
| gprc, spe4rc, | |
| /* EFSCTSIZ */ | |
| gprc, spe4rc, | |
| /* EFSCTUF */ | |
| sperc, spe4rc, | |
| /* EFSCTUI */ | |
| gprc, spe4rc, | |
| /* EFSCTUIZ */ | |
| gprc, spe4rc, | |
| /* EFSDIV */ | |
| spe4rc, spe4rc, spe4rc, | |
| /* EFSMUL */ | |
| spe4rc, spe4rc, spe4rc, | |
| /* EFSNABS */ | |
| spe4rc, spe4rc, | |
| /* EFSNEG */ | |
| spe4rc, spe4rc, | |
| /* EFSSUB */ | |
| spe4rc, spe4rc, spe4rc, | |
| /* EFSTSTEQ */ | |
| crrc, sperc, sperc, | |
| /* EFSTSTGT */ | |
| crrc, sperc, sperc, | |
| /* EFSTSTLT */ | |
| crrc, sperc, sperc, | |
| /* EH_SjLj_LongJmp32 */ | |
| ptr_rc_nor0, | |
| /* EH_SjLj_LongJmp64 */ | |
| ptr_rc_nor0, | |
| /* EH_SjLj_SetJmp32 */ | |
| gprc, ptr_rc_nor0, | |
| /* EH_SjLj_SetJmp64 */ | |
| gprc, ptr_rc_nor0, | |
| /* EH_SjLj_Setup */ | |
| directbrtarget, | |
| /* EQV */ | |
| gprc, gprc, gprc, | |
| /* EQV8 */ | |
| g8rc, g8rc, g8rc, | |
| /* EQV8_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* EQV_rec */ | |
| gprc, gprc, gprc, | |
| /* EVABS */ | |
| sperc, sperc, | |
| /* EVADDIW */ | |
| sperc, sperc, u5imm, | |
| /* EVADDSMIAAW */ | |
| sperc, sperc, | |
| /* EVADDSSIAAW */ | |
| sperc, sperc, | |
| /* EVADDUMIAAW */ | |
| sperc, sperc, | |
| /* EVADDUSIAAW */ | |
| sperc, sperc, | |
| /* EVADDW */ | |
| sperc, sperc, sperc, | |
| /* EVAND */ | |
| sperc, sperc, sperc, | |
| /* EVANDC */ | |
| sperc, sperc, sperc, | |
| /* EVCMPEQ */ | |
| crrc, sperc, sperc, | |
| /* EVCMPGTS */ | |
| crrc, sperc, sperc, | |
| /* EVCMPGTU */ | |
| crrc, sperc, sperc, | |
| /* EVCMPLTS */ | |
| crrc, sperc, sperc, | |
| /* EVCMPLTU */ | |
| crrc, sperc, sperc, | |
| /* EVCNTLSW */ | |
| sperc, sperc, | |
| /* EVCNTLZW */ | |
| sperc, sperc, | |
| /* EVDIVWS */ | |
| sperc, sperc, sperc, | |
| /* EVDIVWU */ | |
| sperc, sperc, sperc, | |
| /* EVEQV */ | |
| sperc, sperc, sperc, | |
| /* EVEXTSB */ | |
| sperc, sperc, | |
| /* EVEXTSH */ | |
| sperc, sperc, | |
| /* EVFSABS */ | |
| sperc, sperc, | |
| /* EVFSADD */ | |
| sperc, sperc, sperc, | |
| /* EVFSCFSF */ | |
| sperc, sperc, | |
| /* EVFSCFSI */ | |
| sperc, sperc, | |
| /* EVFSCFUF */ | |
| sperc, sperc, | |
| /* EVFSCFUI */ | |
| sperc, sperc, | |
| /* EVFSCMPEQ */ | |
| crrc, sperc, sperc, | |
| /* EVFSCMPGT */ | |
| crrc, sperc, sperc, | |
| /* EVFSCMPLT */ | |
| crrc, sperc, sperc, | |
| /* EVFSCTSF */ | |
| sperc, sperc, | |
| /* EVFSCTSI */ | |
| sperc, sperc, | |
| /* EVFSCTSIZ */ | |
| sperc, sperc, | |
| /* EVFSCTUF */ | |
| sperc, sperc, | |
| /* EVFSCTUI */ | |
| sperc, sperc, | |
| /* EVFSCTUIZ */ | |
| sperc, sperc, | |
| /* EVFSDIV */ | |
| sperc, sperc, sperc, | |
| /* EVFSMUL */ | |
| sperc, sperc, sperc, | |
| /* EVFSNABS */ | |
| sperc, sperc, | |
| /* EVFSNEG */ | |
| sperc, sperc, | |
| /* EVFSSUB */ | |
| sperc, sperc, sperc, | |
| /* EVFSTSTEQ */ | |
| crrc, sperc, sperc, | |
| /* EVFSTSTGT */ | |
| crrc, sperc, sperc, | |
| /* EVFSTSTLT */ | |
| crrc, sperc, sperc, | |
| /* EVLDD */ | |
| sperc, dispSPE8, ptr_rc_nor0, | |
| /* EVLDDX */ | |
| sperc, ptr_rc_nor0, ptr_rc_idx, | |
| /* EVLDH */ | |
| sperc, dispSPE8, ptr_rc_nor0, | |
| /* EVLDHX */ | |
| sperc, ptr_rc_nor0, ptr_rc_idx, | |
| /* EVLDW */ | |
| sperc, dispSPE8, ptr_rc_nor0, | |
| /* EVLDWX */ | |
| sperc, ptr_rc_nor0, ptr_rc_idx, | |
| /* EVLHHESPLAT */ | |
| sperc, dispSPE2, ptr_rc_nor0, | |
| /* EVLHHESPLATX */ | |
| sperc, ptr_rc_nor0, ptr_rc_idx, | |
| /* EVLHHOSSPLAT */ | |
| sperc, dispSPE2, ptr_rc_nor0, | |
| /* EVLHHOSSPLATX */ | |
| sperc, ptr_rc_nor0, ptr_rc_idx, | |
| /* EVLHHOUSPLAT */ | |
| sperc, dispSPE2, ptr_rc_nor0, | |
| /* EVLHHOUSPLATX */ | |
| sperc, ptr_rc_nor0, ptr_rc_idx, | |
| /* EVLWHE */ | |
| sperc, dispSPE4, ptr_rc_nor0, | |
| /* EVLWHEX */ | |
| sperc, ptr_rc_nor0, ptr_rc_idx, | |
| /* EVLWHOS */ | |
| sperc, dispSPE4, ptr_rc_nor0, | |
| /* EVLWHOSX */ | |
| sperc, ptr_rc_nor0, ptr_rc_idx, | |
| /* EVLWHOU */ | |
| sperc, dispSPE4, ptr_rc_nor0, | |
| /* EVLWHOUX */ | |
| sperc, ptr_rc_nor0, ptr_rc_idx, | |
| /* EVLWHSPLAT */ | |
| sperc, dispSPE4, ptr_rc_nor0, | |
| /* EVLWHSPLATX */ | |
| sperc, ptr_rc_nor0, ptr_rc_idx, | |
| /* EVLWWSPLAT */ | |
| sperc, dispSPE4, ptr_rc_nor0, | |
| /* EVLWWSPLATX */ | |
| sperc, ptr_rc_nor0, ptr_rc_idx, | |
| /* EVMERGEHI */ | |
| sperc, sperc, sperc, | |
| /* EVMERGEHILO */ | |
| sperc, sperc, sperc, | |
| /* EVMERGELO */ | |
| sperc, gprc, gprc, | |
| /* EVMERGELOHI */ | |
| sperc, sperc, sperc, | |
| /* EVMHEGSMFAA */ | |
| sperc, sperc, sperc, | |
| /* EVMHEGSMFAN */ | |
| sperc, sperc, sperc, | |
| /* EVMHEGSMIAA */ | |
| sperc, sperc, sperc, | |
| /* EVMHEGSMIAN */ | |
| sperc, sperc, sperc, | |
| /* EVMHEGUMIAA */ | |
| sperc, sperc, sperc, | |
| /* EVMHEGUMIAN */ | |
| sperc, sperc, sperc, | |
| /* EVMHESMF */ | |
| sperc, sperc, sperc, | |
| /* EVMHESMFA */ | |
| sperc, sperc, sperc, | |
| /* EVMHESMFAAW */ | |
| sperc, sperc, sperc, | |
| /* EVMHESMFANW */ | |
| sperc, sperc, sperc, | |
| /* EVMHESMI */ | |
| sperc, sperc, sperc, | |
| /* EVMHESMIA */ | |
| sperc, sperc, sperc, | |
| /* EVMHESMIAAW */ | |
| sperc, sperc, sperc, | |
| /* EVMHESMIANW */ | |
| sperc, sperc, sperc, | |
| /* EVMHESSF */ | |
| sperc, sperc, sperc, | |
| /* EVMHESSFA */ | |
| sperc, sperc, sperc, | |
| /* EVMHESSFAAW */ | |
| sperc, sperc, sperc, | |
| /* EVMHESSFANW */ | |
| sperc, sperc, sperc, | |
| /* EVMHESSIAAW */ | |
| sperc, sperc, sperc, | |
| /* EVMHESSIANW */ | |
| sperc, sperc, sperc, | |
| /* EVMHEUMI */ | |
| sperc, sperc, sperc, | |
| /* EVMHEUMIA */ | |
| sperc, sperc, sperc, | |
| /* EVMHEUMIAAW */ | |
| sperc, sperc, sperc, | |
| /* EVMHEUMIANW */ | |
| sperc, sperc, sperc, | |
| /* EVMHEUSIAAW */ | |
| sperc, sperc, sperc, | |
| /* EVMHEUSIANW */ | |
| sperc, sperc, sperc, | |
| /* EVMHOGSMFAA */ | |
| sperc, sperc, sperc, | |
| /* EVMHOGSMFAN */ | |
| sperc, sperc, sperc, | |
| /* EVMHOGSMIAA */ | |
| sperc, sperc, sperc, | |
| /* EVMHOGSMIAN */ | |
| sperc, sperc, sperc, | |
| /* EVMHOGUMIAA */ | |
| sperc, sperc, sperc, | |
| /* EVMHOGUMIAN */ | |
| sperc, sperc, sperc, | |
| /* EVMHOSMF */ | |
| sperc, sperc, sperc, | |
| /* EVMHOSMFA */ | |
| sperc, sperc, sperc, | |
| /* EVMHOSMFAAW */ | |
| sperc, sperc, sperc, | |
| /* EVMHOSMFANW */ | |
| sperc, sperc, sperc, | |
| /* EVMHOSMI */ | |
| sperc, sperc, sperc, | |
| /* EVMHOSMIA */ | |
| sperc, sperc, sperc, | |
| /* EVMHOSMIAAW */ | |
| sperc, sperc, sperc, | |
| /* EVMHOSMIANW */ | |
| sperc, sperc, sperc, | |
| /* EVMHOSSF */ | |
| sperc, sperc, sperc, | |
| /* EVMHOSSFA */ | |
| sperc, sperc, sperc, | |
| /* EVMHOSSFAAW */ | |
| sperc, sperc, sperc, | |
| /* EVMHOSSFANW */ | |
| sperc, sperc, sperc, | |
| /* EVMHOSSIAAW */ | |
| sperc, sperc, sperc, | |
| /* EVMHOSSIANW */ | |
| sperc, sperc, sperc, | |
| /* EVMHOUMI */ | |
| sperc, sperc, sperc, | |
| /* EVMHOUMIA */ | |
| sperc, sperc, sperc, | |
| /* EVMHOUMIAAW */ | |
| sperc, sperc, sperc, | |
| /* EVMHOUMIANW */ | |
| sperc, sperc, sperc, | |
| /* EVMHOUSIAAW */ | |
| sperc, sperc, sperc, | |
| /* EVMHOUSIANW */ | |
| sperc, sperc, sperc, | |
| /* EVMRA */ | |
| sperc, sperc, | |
| /* EVMWHSMF */ | |
| sperc, sperc, sperc, | |
| /* EVMWHSMFA */ | |
| sperc, sperc, sperc, | |
| /* EVMWHSMI */ | |
| sperc, sperc, sperc, | |
| /* EVMWHSMIA */ | |
| sperc, sperc, sperc, | |
| /* EVMWHSSF */ | |
| sperc, sperc, sperc, | |
| /* EVMWHSSFA */ | |
| sperc, sperc, sperc, | |
| /* EVMWHUMI */ | |
| sperc, sperc, sperc, | |
| /* EVMWHUMIA */ | |
| sperc, sperc, sperc, | |
| /* EVMWLSMIAAW */ | |
| sperc, sperc, sperc, | |
| /* EVMWLSMIANW */ | |
| sperc, sperc, sperc, | |
| /* EVMWLSSIAAW */ | |
| sperc, sperc, sperc, | |
| /* EVMWLSSIANW */ | |
| sperc, sperc, sperc, | |
| /* EVMWLUMI */ | |
| sperc, sperc, sperc, | |
| /* EVMWLUMIA */ | |
| sperc, sperc, sperc, | |
| /* EVMWLUMIAAW */ | |
| sperc, sperc, sperc, | |
| /* EVMWLUMIANW */ | |
| sperc, sperc, sperc, | |
| /* EVMWLUSIAAW */ | |
| sperc, sperc, sperc, | |
| /* EVMWLUSIANW */ | |
| sperc, sperc, sperc, | |
| /* EVMWSMF */ | |
| sperc, sperc, sperc, | |
| /* EVMWSMFA */ | |
| sperc, sperc, sperc, | |
| /* EVMWSMFAA */ | |
| sperc, sperc, sperc, | |
| /* EVMWSMFAN */ | |
| sperc, sperc, sperc, | |
| /* EVMWSMI */ | |
| sperc, sperc, sperc, | |
| /* EVMWSMIA */ | |
| sperc, sperc, sperc, | |
| /* EVMWSMIAA */ | |
| sperc, sperc, sperc, | |
| /* EVMWSMIAN */ | |
| sperc, sperc, sperc, | |
| /* EVMWSSF */ | |
| sperc, sperc, sperc, | |
| /* EVMWSSFA */ | |
| sperc, sperc, sperc, | |
| /* EVMWSSFAA */ | |
| sperc, sperc, sperc, | |
| /* EVMWSSFAN */ | |
| sperc, sperc, sperc, | |
| /* EVMWUMI */ | |
| sperc, sperc, sperc, | |
| /* EVMWUMIA */ | |
| sperc, sperc, sperc, | |
| /* EVMWUMIAA */ | |
| sperc, sperc, sperc, | |
| /* EVMWUMIAN */ | |
| sperc, sperc, sperc, | |
| /* EVNAND */ | |
| sperc, sperc, sperc, | |
| /* EVNEG */ | |
| sperc, sperc, | |
| /* EVNOR */ | |
| sperc, sperc, sperc, | |
| /* EVOR */ | |
| sperc, sperc, sperc, | |
| /* EVORC */ | |
| sperc, sperc, sperc, | |
| /* EVRLW */ | |
| sperc, sperc, sperc, | |
| /* EVRLWI */ | |
| sperc, sperc, u5imm, | |
| /* EVRNDW */ | |
| sperc, sperc, | |
| /* EVSEL */ | |
| sperc, sperc, sperc, crrc, | |
| /* EVSLW */ | |
| sperc, sperc, sperc, | |
| /* EVSLWI */ | |
| sperc, sperc, u5imm, | |
| /* EVSPLATFI */ | |
| sperc, s5imm, | |
| /* EVSPLATI */ | |
| sperc, s5imm, | |
| /* EVSRWIS */ | |
| sperc, sperc, u5imm, | |
| /* EVSRWIU */ | |
| sperc, sperc, u5imm, | |
| /* EVSRWS */ | |
| sperc, sperc, sperc, | |
| /* EVSRWU */ | |
| sperc, sperc, sperc, | |
| /* EVSTDD */ | |
| sperc, dispSPE8, ptr_rc_nor0, | |
| /* EVSTDDX */ | |
| sperc, ptr_rc_nor0, ptr_rc_idx, | |
| /* EVSTDH */ | |
| sperc, dispSPE8, ptr_rc_nor0, | |
| /* EVSTDHX */ | |
| sperc, ptr_rc_nor0, ptr_rc_idx, | |
| /* EVSTDW */ | |
| sperc, dispSPE8, ptr_rc_nor0, | |
| /* EVSTDWX */ | |
| sperc, ptr_rc_nor0, ptr_rc_idx, | |
| /* EVSTWHE */ | |
| sperc, dispSPE4, ptr_rc_nor0, | |
| /* EVSTWHEX */ | |
| sperc, ptr_rc_nor0, ptr_rc_idx, | |
| /* EVSTWHO */ | |
| sperc, dispSPE4, ptr_rc_nor0, | |
| /* EVSTWHOX */ | |
| sperc, ptr_rc_nor0, ptr_rc_idx, | |
| /* EVSTWWE */ | |
| sperc, dispSPE4, ptr_rc_nor0, | |
| /* EVSTWWEX */ | |
| sperc, ptr_rc_nor0, ptr_rc_idx, | |
| /* EVSTWWO */ | |
| sperc, dispSPE4, ptr_rc_nor0, | |
| /* EVSTWWOX */ | |
| sperc, ptr_rc_nor0, ptr_rc_idx, | |
| /* EVSUBFSMIAAW */ | |
| sperc, sperc, | |
| /* EVSUBFSSIAAW */ | |
| sperc, sperc, | |
| /* EVSUBFUMIAAW */ | |
| sperc, sperc, | |
| /* EVSUBFUSIAAW */ | |
| sperc, sperc, | |
| /* EVSUBFW */ | |
| sperc, sperc, sperc, | |
| /* EVSUBIFW */ | |
| sperc, u5imm, sperc, | |
| /* EVXOR */ | |
| sperc, sperc, sperc, | |
| /* EXTSB */ | |
| gprc, gprc, | |
| /* EXTSB8 */ | |
| g8rc, g8rc, | |
| /* EXTSB8_32_64 */ | |
| g8rc, gprc, | |
| /* EXTSB8_rec */ | |
| g8rc, g8rc, | |
| /* EXTSB_rec */ | |
| gprc, gprc, | |
| /* EXTSH */ | |
| gprc, gprc, | |
| /* EXTSH8 */ | |
| g8rc, g8rc, | |
| /* EXTSH8_32_64 */ | |
| g8rc, gprc, | |
| /* EXTSH8_rec */ | |
| g8rc, g8rc, | |
| /* EXTSH_rec */ | |
| gprc, gprc, | |
| /* EXTSW */ | |
| g8rc, g8rc, | |
| /* EXTSWSLI */ | |
| g8rc, g8rc, u6imm, | |
| /* EXTSWSLI_32_64 */ | |
| g8rc, gprc, u6imm, | |
| /* EXTSWSLI_32_64_rec */ | |
| g8rc, gprc, u6imm, | |
| /* EXTSWSLI_rec */ | |
| g8rc, g8rc, u6imm, | |
| /* EXTSW_32 */ | |
| gprc, gprc, | |
| /* EXTSW_32_64 */ | |
| g8rc, gprc, | |
| /* EXTSW_32_64_rec */ | |
| g8rc, gprc, | |
| /* EXTSW_rec */ | |
| g8rc, g8rc, | |
| /* EnforceIEIO */ | |
| /* FABSD */ | |
| f8rc, f8rc, | |
| /* FABSD_rec */ | |
| f8rc, f8rc, | |
| /* FABSS */ | |
| f4rc, f4rc, | |
| /* FABSS_rec */ | |
| f4rc, f4rc, | |
| /* FADD */ | |
| f8rc, f8rc, f8rc, | |
| /* FADDS */ | |
| f4rc, f4rc, f4rc, | |
| /* FADDS_rec */ | |
| f4rc, f4rc, f4rc, | |
| /* FADD_rec */ | |
| f8rc, f8rc, f8rc, | |
| /* FADDrtz */ | |
| f8rc, f8rc, f8rc, | |
| /* FCFID */ | |
| f8rc, f8rc, | |
| /* FCFIDS */ | |
| f4rc, f8rc, | |
| /* FCFIDS_rec */ | |
| f4rc, f8rc, | |
| /* FCFIDU */ | |
| f8rc, f8rc, | |
| /* FCFIDUS */ | |
| f4rc, f8rc, | |
| /* FCFIDUS_rec */ | |
| f4rc, f8rc, | |
| /* FCFIDU_rec */ | |
| f8rc, f8rc, | |
| /* FCFID_rec */ | |
| f8rc, f8rc, | |
| /* FCMPOD */ | |
| crrc, f8rc, f8rc, | |
| /* FCMPOS */ | |
| crrc, f4rc, f4rc, | |
| /* FCMPUD */ | |
| crrc, f8rc, f8rc, | |
| /* FCMPUS */ | |
| crrc, f4rc, f4rc, | |
| /* FCPSGND */ | |
| f8rc, f8rc, f8rc, | |
| /* FCPSGND_rec */ | |
| f8rc, f8rc, f8rc, | |
| /* FCPSGNS */ | |
| f4rc, f4rc, f4rc, | |
| /* FCPSGNS_rec */ | |
| f4rc, f4rc, f4rc, | |
| /* FCTID */ | |
| f8rc, f8rc, | |
| /* FCTIDU */ | |
| f8rc, f8rc, | |
| /* FCTIDUZ */ | |
| f8rc, f8rc, | |
| /* FCTIDUZ_rec */ | |
| f8rc, f8rc, | |
| /* FCTIDU_rec */ | |
| f8rc, f8rc, | |
| /* FCTIDZ */ | |
| f8rc, f8rc, | |
| /* FCTIDZ_rec */ | |
| f8rc, f8rc, | |
| /* FCTID_rec */ | |
| f8rc, f8rc, | |
| /* FCTIW */ | |
| f8rc, f8rc, | |
| /* FCTIWU */ | |
| f8rc, f8rc, | |
| /* FCTIWUZ */ | |
| f8rc, f8rc, | |
| /* FCTIWUZ_rec */ | |
| f8rc, f8rc, | |
| /* FCTIWU_rec */ | |
| f8rc, f8rc, | |
| /* FCTIWZ */ | |
| f8rc, f8rc, | |
| /* FCTIWZ_rec */ | |
| f8rc, f8rc, | |
| /* FCTIW_rec */ | |
| f8rc, f8rc, | |
| /* FDIV */ | |
| f8rc, f8rc, f8rc, | |
| /* FDIVS */ | |
| f4rc, f4rc, f4rc, | |
| /* FDIVS_rec */ | |
| f4rc, f4rc, f4rc, | |
| /* FDIV_rec */ | |
| f8rc, f8rc, f8rc, | |
| /* FMADD */ | |
| f8rc, f8rc, f8rc, f8rc, | |
| /* FMADDS */ | |
| f4rc, f4rc, f4rc, f4rc, | |
| /* FMADDS_rec */ | |
| f4rc, f4rc, f4rc, f4rc, | |
| /* FMADD_rec */ | |
| f8rc, f8rc, f8rc, f8rc, | |
| /* FMR */ | |
| f4rc, f4rc, | |
| /* FMR_rec */ | |
| f4rc, f4rc, | |
| /* FMSUB */ | |
| f8rc, f8rc, f8rc, f8rc, | |
| /* FMSUBS */ | |
| f4rc, f4rc, f4rc, f4rc, | |
| /* FMSUBS_rec */ | |
| f4rc, f4rc, f4rc, f4rc, | |
| /* FMSUB_rec */ | |
| f8rc, f8rc, f8rc, f8rc, | |
| /* FMUL */ | |
| f8rc, f8rc, f8rc, | |
| /* FMULS */ | |
| f4rc, f4rc, f4rc, | |
| /* FMULS_rec */ | |
| f4rc, f4rc, f4rc, | |
| /* FMUL_rec */ | |
| f8rc, f8rc, f8rc, | |
| /* FNABSD */ | |
| f8rc, f8rc, | |
| /* FNABSD_rec */ | |
| f8rc, f8rc, | |
| /* FNABSS */ | |
| f4rc, f4rc, | |
| /* FNABSS_rec */ | |
| f4rc, f4rc, | |
| /* FNEGD */ | |
| f8rc, f8rc, | |
| /* FNEGD_rec */ | |
| f8rc, f8rc, | |
| /* FNEGS */ | |
| f4rc, f4rc, | |
| /* FNEGS_rec */ | |
| f4rc, f4rc, | |
| /* FNMADD */ | |
| f8rc, f8rc, f8rc, f8rc, | |
| /* FNMADDS */ | |
| f4rc, f4rc, f4rc, f4rc, | |
| /* FNMADDS_rec */ | |
| f4rc, f4rc, f4rc, f4rc, | |
| /* FNMADD_rec */ | |
| f8rc, f8rc, f8rc, f8rc, | |
| /* FNMSUB */ | |
| f8rc, f8rc, f8rc, f8rc, | |
| /* FNMSUBS */ | |
| f4rc, f4rc, f4rc, f4rc, | |
| /* FNMSUBS_rec */ | |
| f4rc, f4rc, f4rc, f4rc, | |
| /* FNMSUB_rec */ | |
| f8rc, f8rc, f8rc, f8rc, | |
| /* FRE */ | |
| f8rc, f8rc, | |
| /* FRES */ | |
| f4rc, f4rc, | |
| /* FRES_rec */ | |
| f4rc, f4rc, | |
| /* FRE_rec */ | |
| f8rc, f8rc, | |
| /* FRIMD */ | |
| f8rc, f8rc, | |
| /* FRIMD_rec */ | |
| f8rc, f8rc, | |
| /* FRIMS */ | |
| f4rc, f4rc, | |
| /* FRIMS_rec */ | |
| f4rc, f4rc, | |
| /* FRIND */ | |
| f8rc, f8rc, | |
| /* FRIND_rec */ | |
| f8rc, f8rc, | |
| /* FRINS */ | |
| f4rc, f4rc, | |
| /* FRINS_rec */ | |
| f4rc, f4rc, | |
| /* FRIPD */ | |
| f8rc, f8rc, | |
| /* FRIPD_rec */ | |
| f8rc, f8rc, | |
| /* FRIPS */ | |
| f4rc, f4rc, | |
| /* FRIPS_rec */ | |
| f4rc, f4rc, | |
| /* FRIZD */ | |
| f8rc, f8rc, | |
| /* FRIZD_rec */ | |
| f8rc, f8rc, | |
| /* FRIZS */ | |
| f4rc, f4rc, | |
| /* FRIZS_rec */ | |
| f4rc, f4rc, | |
| /* FRSP */ | |
| f4rc, f8rc, | |
| /* FRSP_rec */ | |
| f4rc, f8rc, | |
| /* FRSQRTE */ | |
| f8rc, f8rc, | |
| /* FRSQRTES */ | |
| f4rc, f4rc, | |
| /* FRSQRTES_rec */ | |
| f4rc, f4rc, | |
| /* FRSQRTE_rec */ | |
| f8rc, f8rc, | |
| /* FSELD */ | |
| f8rc, f8rc, f8rc, f8rc, | |
| /* FSELD_rec */ | |
| f8rc, f8rc, f8rc, f8rc, | |
| /* FSELS */ | |
| f4rc, f8rc, f4rc, f4rc, | |
| /* FSELS_rec */ | |
| f4rc, f8rc, f4rc, f4rc, | |
| /* FSQRT */ | |
| f8rc, f8rc, | |
| /* FSQRTS */ | |
| f4rc, f4rc, | |
| /* FSQRTS_rec */ | |
| f4rc, f4rc, | |
| /* FSQRT_rec */ | |
| f8rc, f8rc, | |
| /* FSUB */ | |
| f8rc, f8rc, f8rc, | |
| /* FSUBS */ | |
| f4rc, f4rc, f4rc, | |
| /* FSUBS_rec */ | |
| f4rc, f4rc, f4rc, | |
| /* FSUB_rec */ | |
| f8rc, f8rc, f8rc, | |
| /* FTDIV */ | |
| crrc, f8rc, f8rc, | |
| /* FTSQRT */ | |
| crrc, f8rc, | |
| /* GETtlsADDR */ | |
| g8rc, g8rc, tlsgd, | |
| /* GETtlsADDR32 */ | |
| gprc, gprc, tlsgd32, | |
| /* GETtlsADDR32AIX */ | |
| gprc, gprc, gprc, | |
| /* GETtlsADDR64AIX */ | |
| g8rc, g8rc, g8rc, | |
| /* GETtlsADDRPCREL */ | |
| g8rc, g8rc, tlsgd, | |
| /* GETtlsldADDR */ | |
| g8rc, g8rc, tlsgd, | |
| /* GETtlsldADDR32 */ | |
| gprc, gprc, tlsgd32, | |
| /* GETtlsldADDRPCREL */ | |
| g8rc, g8rc, tlsgd, | |
| /* HASHCHK */ | |
| gprc, dispRIHash, ptr_rc_nor0, | |
| /* HASHCHK8 */ | |
| g8rc, dispRIHash, ptr_rc_nor0, | |
| /* HASHCHKP */ | |
| gprc, dispRIHash, ptr_rc_nor0, | |
| /* HASHCHKP8 */ | |
| g8rc, dispRIHash, ptr_rc_nor0, | |
| /* HASHST */ | |
| gprc, dispRIHash, ptr_rc_nor0, | |
| /* HASHST8 */ | |
| g8rc, dispRIHash, ptr_rc_nor0, | |
| /* HASHSTP */ | |
| gprc, dispRIHash, ptr_rc_nor0, | |
| /* HASHSTP8 */ | |
| g8rc, dispRIHash, ptr_rc_nor0, | |
| /* HRFID */ | |
| /* ICBI */ | |
| ptr_rc_nor0, ptr_rc_idx, | |
| /* ICBIEP */ | |
| ptr_rc_nor0, ptr_rc_idx, | |
| /* ICBLC */ | |
| u4imm, ptr_rc_nor0, ptr_rc_idx, | |
| /* ICBLQ */ | |
| u4imm, ptr_rc_nor0, ptr_rc_idx, | |
| /* ICBT */ | |
| u4imm, ptr_rc_nor0, ptr_rc_idx, | |
| /* ICBTLS */ | |
| u4imm, ptr_rc_nor0, ptr_rc_idx, | |
| /* ICCCI */ | |
| gprc, gprc, | |
| /* ISEL */ | |
| gprc, gprc_nor0, gprc, crbitrc, | |
| /* ISEL8 */ | |
| g8rc, g8rc_nox0, g8rc, crbitrc, | |
| /* ISYNC */ | |
| /* LA */ | |
| gprc, gprc_nor0, s16imm, | |
| /* LA8 */ | |
| g8rc, g8rc_nox0, s16imm64, | |
| /* LBARX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LBARXL */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LBEPX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LBZ */ | |
| gprc, dispRI, ptr_rc_nor0, | |
| /* LBZ8 */ | |
| g8rc, dispRI, ptr_rc_nor0, | |
| /* LBZCIX */ | |
| gprc, gprc, gprc, | |
| /* LBZU */ | |
| gprc, ptr_rc_nor0, dispRI, ptr_rc_nor0, | |
| /* LBZU8 */ | |
| g8rc, ptr_rc_nor0, dispRI, ptr_rc_nor0, | |
| /* LBZUX */ | |
| gprc, ptr_rc_nor0, ptr_rc_nor0, ptr_rc_idx, | |
| /* LBZUX8 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_nor0, ptr_rc_idx, | |
| /* LBZX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LBZX8 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LBZXTLS */ | |
| g8rc, ptr_rc_nor0, tlsreg, | |
| /* LBZXTLS_ */ | |
| g8rc, ptr_rc_nor0, tlsreg, | |
| /* LBZXTLS_32 */ | |
| gprc, ptr_rc_nor0, tlsreg, | |
| /* LD */ | |
| g8rc, dispRIX, ptr_rc_nor0, | |
| /* LDARX */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LDARXL */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LDAT */ | |
| g8rc, g8rc, u5imm, | |
| /* LDBRX */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LDCIX */ | |
| gprc, gprc, gprc, | |
| /* LDU */ | |
| g8rc, ptr_rc_nor0, dispRIX, ptr_rc_nor0, | |
| /* LDUX */ | |
| g8rc, ptr_rc_nor0, ptr_rc_nor0, ptr_rc_idx, | |
| /* LDX */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LDXTLS */ | |
| g8rc, ptr_rc_nor0, tlsreg, | |
| /* LDXTLS_ */ | |
| g8rc, ptr_rc_nor0, tlsreg, | |
| /* LDgotTprelL */ | |
| g8rc_nox0, s16imm64, g8rc_nox0, | |
| /* LDgotTprelL32 */ | |
| gprc_nor0, s16imm, gprc_nor0, | |
| /* LDtoc */ | |
| g8rc, i64imm, g8rc, | |
| /* LDtocBA */ | |
| g8rc, i64imm, g8rc, | |
| /* LDtocCPT */ | |
| g8rc, i64imm, g8rc, | |
| /* LDtocJTI */ | |
| g8rc, i64imm, g8rc, | |
| /* LDtocL */ | |
| g8rc, i64imm, g8rc_nox0, | |
| /* LFD */ | |
| f8rc, dispRI, ptr_rc_nor0, | |
| /* LFDEPX */ | |
| f8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LFDU */ | |
| f8rc, ptr_rc_nor0, dispRI, ptr_rc_nor0, | |
| /* LFDUX */ | |
| f8rc, ptr_rc_nor0, ptr_rc_nor0, ptr_rc_idx, | |
| /* LFDX */ | |
| f8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LFIWAX */ | |
| f8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LFIWZX */ | |
| f8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LFS */ | |
| f4rc, dispRI, ptr_rc_nor0, | |
| /* LFSU */ | |
| f4rc, ptr_rc_nor0, dispRI, ptr_rc_nor0, | |
| /* LFSUX */ | |
| f4rc, ptr_rc_nor0, ptr_rc_nor0, ptr_rc_idx, | |
| /* LFSX */ | |
| f4rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LHA */ | |
| gprc, dispRI, ptr_rc_nor0, | |
| /* LHA8 */ | |
| g8rc, dispRI, ptr_rc_nor0, | |
| /* LHARX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LHARXL */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LHAU */ | |
| gprc, ptr_rc_nor0, dispRI, ptr_rc_nor0, | |
| /* LHAU8 */ | |
| g8rc, ptr_rc_nor0, dispRI, ptr_rc_nor0, | |
| /* LHAUX */ | |
| gprc, ptr_rc_nor0, ptr_rc_nor0, ptr_rc_idx, | |
| /* LHAUX8 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_nor0, ptr_rc_idx, | |
| /* LHAX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LHAX8 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LHBRX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LHBRX8 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LHEPX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LHZ */ | |
| gprc, dispRI, ptr_rc_nor0, | |
| /* LHZ8 */ | |
| g8rc, dispRI, ptr_rc_nor0, | |
| /* LHZCIX */ | |
| gprc, gprc, gprc, | |
| /* LHZU */ | |
| gprc, ptr_rc_nor0, dispRI, ptr_rc_nor0, | |
| /* LHZU8 */ | |
| g8rc, ptr_rc_nor0, dispRI, ptr_rc_nor0, | |
| /* LHZUX */ | |
| gprc, ptr_rc_nor0, ptr_rc_nor0, ptr_rc_idx, | |
| /* LHZUX8 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_nor0, ptr_rc_idx, | |
| /* LHZX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LHZX8 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LHZXTLS */ | |
| g8rc, ptr_rc_nor0, tlsreg, | |
| /* LHZXTLS_ */ | |
| g8rc, ptr_rc_nor0, tlsreg, | |
| /* LHZXTLS_32 */ | |
| gprc, ptr_rc_nor0, tlsreg, | |
| /* LI */ | |
| gprc, s16imm, | |
| /* LI8 */ | |
| g8rc, s16imm64, | |
| /* LIS */ | |
| gprc, s17imm, | |
| /* LIS8 */ | |
| g8rc, s17imm64, | |
| /* LMW */ | |
| gprc, dispRI, ptr_rc_nor0, | |
| /* LQ */ | |
| g8prc, dispRIX16, ptr_rc_nor0, | |
| /* LQARX */ | |
| g8prc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LQARXL */ | |
| g8prc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LQX_PSEUDO */ | |
| g8prc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LSWI */ | |
| gprc, gprc, u5imm, | |
| /* LVEBX */ | |
| vrrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LVEHX */ | |
| vrrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LVEWX */ | |
| vrrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LVSL */ | |
| vrrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LVSR */ | |
| vrrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LVX */ | |
| vrrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LVXL */ | |
| vrrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LWA */ | |
| g8rc, dispRIX, ptr_rc_nor0, | |
| /* LWARX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LWARXL */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LWAT */ | |
| gprc, gprc, u5imm, | |
| /* LWAUX */ | |
| g8rc, ptr_rc_nor0, ptr_rc_nor0, ptr_rc_idx, | |
| /* LWAX */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LWAX_32 */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LWA_32 */ | |
| gprc, dispRIX, ptr_rc_nor0, | |
| /* LWBRX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LWBRX8 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LWEPX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LWZ */ | |
| gprc, dispRI, ptr_rc_nor0, | |
| /* LWZ8 */ | |
| g8rc, dispRI, ptr_rc_nor0, | |
| /* LWZCIX */ | |
| gprc, gprc, gprc, | |
| /* LWZU */ | |
| gprc, ptr_rc_nor0, dispRI, ptr_rc_nor0, | |
| /* LWZU8 */ | |
| g8rc, ptr_rc_nor0, dispRI, ptr_rc_nor0, | |
| /* LWZUX */ | |
| gprc, ptr_rc_nor0, ptr_rc_nor0, ptr_rc_idx, | |
| /* LWZUX8 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_nor0, ptr_rc_idx, | |
| /* LWZX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LWZX8 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LWZXTLS */ | |
| g8rc, ptr_rc_nor0, tlsreg, | |
| /* LWZXTLS_ */ | |
| g8rc, ptr_rc_nor0, tlsreg, | |
| /* LWZXTLS_32 */ | |
| gprc, ptr_rc_nor0, tlsreg, | |
| /* LWZtoc */ | |
| gprc, i32imm, gprc, | |
| /* LWZtocL */ | |
| gprc, i32imm, gprc_nor0, | |
| /* LXSD */ | |
| vfrc, dispRIX, ptr_rc_nor0, | |
| /* LXSDX */ | |
| vsfrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LXSIBZX */ | |
| vsfrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LXSIHZX */ | |
| vsfrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LXSIWAX */ | |
| vsfrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LXSIWZX */ | |
| vsfrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LXSSP */ | |
| vfrc, dispRIX, ptr_rc_nor0, | |
| /* LXSSPX */ | |
| vssrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LXV */ | |
| vsrc, dispRIX16, ptr_rc_nor0, | |
| /* LXVB16X */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LXVD2X */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LXVDSX */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LXVH8X */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LXVKQ */ | |
| vsrc, u5imm, | |
| /* LXVL */ | |
| vsrc, ptr_rc_nor0, g8rc, | |
| /* LXVLL */ | |
| vsrc, ptr_rc_nor0, g8rc, | |
| /* LXVP */ | |
| vsrprc, dispRIX16, ptr_rc_nor0, | |
| /* LXVPRL */ | |
| vsrprc, ptr_rc_nor0, g8rc, | |
| /* LXVPRLL */ | |
| vsrprc, ptr_rc_nor0, g8rc, | |
| /* LXVPX */ | |
| vsrprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LXVRBX */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LXVRDX */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LXVRHX */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LXVRL */ | |
| vsrc, ptr_rc_nor0, g8rc, | |
| /* LXVRLL */ | |
| vsrc, ptr_rc_nor0, g8rc, | |
| /* LXVRWX */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LXVW4X */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LXVWSX */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* LXVX */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* MADDHD */ | |
| g8rc, g8rc, g8rc, g8rc, | |
| /* MADDHDU */ | |
| g8rc, g8rc, g8rc, g8rc, | |
| /* MADDLD */ | |
| gprc, gprc, gprc, gprc, | |
| /* MADDLD8 */ | |
| g8rc, g8rc, g8rc, g8rc, | |
| /* MBAR */ | |
| u5imm, | |
| /* MCRF */ | |
| crrc, crrc, | |
| /* MCRFS */ | |
| crrc, crrc, | |
| /* MCRXRX */ | |
| crrc, | |
| /* MFBHRBE */ | |
| gprc, u10imm, u10imm, | |
| /* MFCR */ | |
| gprc, | |
| /* MFCR8 */ | |
| g8rc, | |
| /* MFCTR */ | |
| gprc, | |
| /* MFCTR8 */ | |
| g8rc, | |
| /* MFDCR */ | |
| gprc, i32imm, | |
| /* MFFS */ | |
| f8rc, | |
| /* MFFSCDRN */ | |
| f8rc, f8rc, | |
| /* MFFSCDRNI */ | |
| f8rc, u3imm, | |
| /* MFFSCE */ | |
| f8rc, | |
| /* MFFSCRN */ | |
| f8rc, f8rc, | |
| /* MFFSCRNI */ | |
| f8rc, u2imm, | |
| /* MFFSL */ | |
| f8rc, | |
| /* MFFS_rec */ | |
| f8rc, | |
| /* MFLR */ | |
| gprc, | |
| /* MFLR8 */ | |
| g8rc, | |
| /* MFMSR */ | |
| gprc, | |
| /* MFOCRF */ | |
| gprc, crbitm, | |
| /* MFOCRF8 */ | |
| g8rc, crbitm, | |
| /* MFPMR */ | |
| gprc, i32imm, | |
| /* MFSPR */ | |
| gprc, i32imm, | |
| /* MFSPR8 */ | |
| g8rc, i32imm, | |
| /* MFSR */ | |
| gprc, u4imm, | |
| /* MFSRIN */ | |
| gprc, gprc, | |
| /* MFTB */ | |
| gprc, i32imm, | |
| /* MFTB8 */ | |
| g8rc, | |
| /* MFUDSCR */ | |
| gprc, | |
| /* MFVRD */ | |
| g8rc, vsrc, | |
| /* MFVRSAVE */ | |
| gprc, | |
| /* MFVRSAVEv */ | |
| gprc, VRSAVERC, | |
| /* MFVRWZ */ | |
| gprc, vsrc, | |
| /* MFVSCR */ | |
| vrrc, | |
| /* MFVSRD */ | |
| g8rc, vsfrc, | |
| /* MFVSRLD */ | |
| g8rc, vsrc, | |
| /* MFVSRWZ */ | |
| gprc, vsfrc, | |
| /* MODSD */ | |
| g8rc, g8rc, g8rc, | |
| /* MODSW */ | |
| gprc, gprc, gprc, | |
| /* MODUD */ | |
| g8rc, g8rc, g8rc, | |
| /* MODUW */ | |
| gprc, gprc, gprc, | |
| /* MSGSYNC */ | |
| /* MSYNC */ | |
| /* MTCRF */ | |
| i32imm, gprc, | |
| /* MTCRF8 */ | |
| i32imm, g8rc, | |
| /* MTCTR */ | |
| gprc, | |
| /* MTCTR8 */ | |
| g8rc, | |
| /* MTCTR8loop */ | |
| g8rc, | |
| /* MTCTRloop */ | |
| gprc, | |
| /* MTDCR */ | |
| gprc, i32imm, | |
| /* MTFSB0 */ | |
| u5imm, | |
| /* MTFSB1 */ | |
| u5imm, | |
| /* MTFSF */ | |
| i32imm, f8rc, u1imm, i32imm, | |
| /* MTFSFI */ | |
| u3imm, u4imm, i32imm, | |
| /* MTFSFI_rec */ | |
| u3imm, u4imm, u1imm, | |
| /* MTFSFIb */ | |
| u3imm, u4imm, | |
| /* MTFSF_rec */ | |
| i32imm, f8rc, u1imm, i32imm, | |
| /* MTFSFb */ | |
| i32imm, f8rc, | |
| /* MTLR */ | |
| gprc, | |
| /* MTLR8 */ | |
| g8rc, | |
| /* MTMSR */ | |
| gprc, u1imm, | |
| /* MTMSRD */ | |
| gprc, u1imm, | |
| /* MTOCRF */ | |
| crbitm, gprc, | |
| /* MTOCRF8 */ | |
| crbitm, g8rc, | |
| /* MTPMR */ | |
| i32imm, gprc, | |
| /* MTSPR */ | |
| i32imm, gprc, | |
| /* MTSPR8 */ | |
| i32imm, g8rc, | |
| /* MTSR */ | |
| gprc, u4imm, | |
| /* MTSRIN */ | |
| gprc, gprc, | |
| /* MTUDSCR */ | |
| gprc, | |
| /* MTVRD */ | |
| vsrc, g8rc, | |
| /* MTVRSAVE */ | |
| gprc, | |
| /* MTVRSAVEv */ | |
| VRSAVERC, gprc, | |
| /* MTVRWA */ | |
| vsrc, gprc, | |
| /* MTVRWZ */ | |
| vsrc, gprc, | |
| /* MTVSCR */ | |
| vrrc, | |
| /* MTVSRBM */ | |
| vrrc, g8rc, | |
| /* MTVSRBMI */ | |
| vrrc, u16imm64, | |
| /* MTVSRD */ | |
| vsfrc, g8rc, | |
| /* MTVSRDD */ | |
| vsrc, g8rc_nox0, g8rc, | |
| /* MTVSRDM */ | |
| vrrc, g8rc, | |
| /* MTVSRHM */ | |
| vrrc, g8rc, | |
| /* MTVSRQM */ | |
| vrrc, g8rc, | |
| /* MTVSRWA */ | |
| vsfrc, gprc, | |
| /* MTVSRWM */ | |
| vrrc, g8rc, | |
| /* MTVSRWS */ | |
| vsrc, gprc, | |
| /* MTVSRWZ */ | |
| vsfrc, gprc, | |
| /* MULHD */ | |
| g8rc, g8rc, g8rc, | |
| /* MULHDU */ | |
| g8rc, g8rc, g8rc, | |
| /* MULHDU_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* MULHD_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* MULHW */ | |
| gprc, gprc, gprc, | |
| /* MULHWU */ | |
| gprc, gprc, gprc, | |
| /* MULHWU_rec */ | |
| gprc, gprc, gprc, | |
| /* MULHW_rec */ | |
| gprc, gprc, gprc, | |
| /* MULLD */ | |
| g8rc, g8rc, g8rc, | |
| /* MULLDO */ | |
| g8rc, g8rc, g8rc, | |
| /* MULLDO_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* MULLD_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* MULLI */ | |
| gprc, gprc, s16imm, | |
| /* MULLI8 */ | |
| g8rc, g8rc, s16imm64, | |
| /* MULLW */ | |
| gprc, gprc, gprc, | |
| /* MULLWO */ | |
| gprc, gprc, gprc, | |
| /* MULLWO_rec */ | |
| gprc, gprc, gprc, | |
| /* MULLW_rec */ | |
| gprc, gprc, gprc, | |
| /* MoveGOTtoLR */ | |
| /* MovePCtoLR */ | |
| /* MovePCtoLR8 */ | |
| /* NAND */ | |
| gprc, gprc, gprc, | |
| /* NAND8 */ | |
| g8rc, g8rc, g8rc, | |
| /* NAND8_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* NAND_rec */ | |
| gprc, gprc, gprc, | |
| /* NAP */ | |
| /* NEG */ | |
| gprc, gprc, | |
| /* NEG8 */ | |
| g8rc, g8rc, | |
| /* NEG8O */ | |
| g8rc, g8rc, | |
| /* NEG8O_rec */ | |
| g8rc, g8rc, | |
| /* NEG8_rec */ | |
| g8rc, g8rc, | |
| /* NEGO */ | |
| gprc, gprc, | |
| /* NEGO_rec */ | |
| gprc, gprc, | |
| /* NEG_rec */ | |
| gprc, gprc, | |
| /* NOP */ | |
| /* NOP_GT_PWR6 */ | |
| /* NOP_GT_PWR7 */ | |
| /* NOR */ | |
| gprc, gprc, gprc, | |
| /* NOR8 */ | |
| g8rc, g8rc, g8rc, | |
| /* NOR8_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* NOR_rec */ | |
| gprc, gprc, gprc, | |
| /* OR */ | |
| gprc, gprc, gprc, | |
| /* OR8 */ | |
| g8rc, g8rc, g8rc, | |
| /* OR8_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* ORC */ | |
| gprc, gprc, gprc, | |
| /* ORC8 */ | |
| g8rc, g8rc, g8rc, | |
| /* ORC8_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* ORC_rec */ | |
| gprc, gprc, gprc, | |
| /* ORI */ | |
| gprc, gprc, u16imm, | |
| /* ORI8 */ | |
| g8rc, g8rc, u16imm64, | |
| /* ORIS */ | |
| gprc, gprc, u16imm, | |
| /* ORIS8 */ | |
| g8rc, g8rc, u16imm64, | |
| /* OR_rec */ | |
| gprc, gprc, gprc, | |
| /* PADDI */ | |
| gprc, gprc, s34imm, | |
| /* PADDI8 */ | |
| g8rc, g8rc, s34imm, | |
| /* PADDI8pc */ | |
| g8rc, immZero, s34imm_pcrel, | |
| /* PADDIdtprel */ | |
| g8rc, g8rc_nox0, s16imm64, | |
| /* PADDIpc */ | |
| gprc, immZero, s34imm_pcrel, | |
| /* PDEPD */ | |
| g8rc, g8rc, g8rc, | |
| /* PEXTD */ | |
| g8rc, g8rc, g8rc, | |
| /* PLBZ */ | |
| gprc, dispRI34, ptr_rc_nor0, | |
| /* PLBZ8 */ | |
| g8rc, dispRI34, ptr_rc_nor0, | |
| /* PLBZ8pc */ | |
| g8rc, dispRI34, immZero, | |
| /* PLBZpc */ | |
| gprc, dispRI34, immZero, | |
| /* PLD */ | |
| g8rc, dispRI34, ptr_rc_nor0, | |
| /* PLDpc */ | |
| g8rc, dispRI34, immZero, | |
| /* PLFD */ | |
| f8rc, dispRI34, ptr_rc_nor0, | |
| /* PLFDpc */ | |
| f8rc, dispRI34, immZero, | |
| /* PLFS */ | |
| f4rc, dispRI34, ptr_rc_nor0, | |
| /* PLFSpc */ | |
| f4rc, dispRI34, immZero, | |
| /* PLHA */ | |
| gprc, dispRI34, ptr_rc_nor0, | |
| /* PLHA8 */ | |
| g8rc, dispRI34, ptr_rc_nor0, | |
| /* PLHA8pc */ | |
| g8rc, dispRI34, immZero, | |
| /* PLHApc */ | |
| gprc, dispRI34, immZero, | |
| /* PLHZ */ | |
| gprc, dispRI34, ptr_rc_nor0, | |
| /* PLHZ8 */ | |
| g8rc, dispRI34, ptr_rc_nor0, | |
| /* PLHZ8pc */ | |
| g8rc, dispRI34, immZero, | |
| /* PLHZpc */ | |
| gprc, dispRI34, immZero, | |
| /* PLI */ | |
| gprc, s34imm, | |
| /* PLI8 */ | |
| g8rc, s34imm, | |
| /* PLWA */ | |
| gprc, dispRI34, ptr_rc_nor0, | |
| /* PLWA8 */ | |
| g8rc, dispRI34, ptr_rc_nor0, | |
| /* PLWA8pc */ | |
| g8rc, dispRI34, immZero, | |
| /* PLWApc */ | |
| gprc, dispRI34, immZero, | |
| /* PLWZ */ | |
| gprc, dispRI34, ptr_rc_nor0, | |
| /* PLWZ8 */ | |
| g8rc, dispRI34, ptr_rc_nor0, | |
| /* PLWZ8pc */ | |
| g8rc, dispRI34, immZero, | |
| /* PLWZpc */ | |
| gprc, dispRI34, immZero, | |
| /* PLXSD */ | |
| vfrc, dispRI34, ptr_rc_nor0, | |
| /* PLXSDpc */ | |
| vfrc, dispRI34, immZero, | |
| /* PLXSSP */ | |
| vfrc, dispRI34, ptr_rc_nor0, | |
| /* PLXSSPpc */ | |
| vfrc, dispRI34, immZero, | |
| /* PLXV */ | |
| vsrc, dispRI34, ptr_rc_nor0, | |
| /* PLXVP */ | |
| vsrprc, dispRI34, ptr_rc_nor0, | |
| /* PLXVPpc */ | |
| vsrprc, dispRI34, immZero, | |
| /* PLXVpc */ | |
| vsrc, dispRI34, immZero, | |
| /* PMXVBF16GER2 */ | |
| acc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVBF16GER2NN */ | |
| acc, acc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVBF16GER2NP */ | |
| acc, acc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVBF16GER2PN */ | |
| acc, acc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVBF16GER2PP */ | |
| acc, acc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVBF16GER2W */ | |
| wacc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVBF16GER2WNN */ | |
| wacc, wacc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVBF16GER2WNP */ | |
| wacc, wacc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVBF16GER2WPN */ | |
| wacc, wacc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVBF16GER2WPP */ | |
| wacc, wacc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVF16GER2 */ | |
| acc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVF16GER2NN */ | |
| acc, acc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVF16GER2NP */ | |
| acc, acc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVF16GER2PN */ | |
| acc, acc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVF16GER2PP */ | |
| acc, acc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVF16GER2W */ | |
| wacc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVF16GER2WNN */ | |
| wacc, wacc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVF16GER2WNP */ | |
| wacc, wacc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVF16GER2WPN */ | |
| wacc, wacc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVF16GER2WPP */ | |
| wacc, wacc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVF32GER */ | |
| acc, vsrc, vsrc, u4imm, u4imm, | |
| /* PMXVF32GERNN */ | |
| acc, acc, vsrc, vsrc, u4imm, u4imm, | |
| /* PMXVF32GERNP */ | |
| acc, acc, vsrc, vsrc, u4imm, u4imm, | |
| /* PMXVF32GERPN */ | |
| acc, acc, vsrc, vsrc, u4imm, u4imm, | |
| /* PMXVF32GERPP */ | |
| acc, acc, vsrc, vsrc, u4imm, u4imm, | |
| /* PMXVF32GERW */ | |
| wacc, vsrc, vsrc, u4imm, u4imm, | |
| /* PMXVF32GERWNN */ | |
| wacc, wacc, vsrc, vsrc, u4imm, u4imm, | |
| /* PMXVF32GERWNP */ | |
| wacc, wacc, vsrc, vsrc, u4imm, u4imm, | |
| /* PMXVF32GERWPN */ | |
| wacc, wacc, vsrc, vsrc, u4imm, u4imm, | |
| /* PMXVF32GERWPP */ | |
| wacc, wacc, vsrc, vsrc, u4imm, u4imm, | |
| /* PMXVF64GER */ | |
| acc, vsrpevenrc, vsrc, u4imm, u2imm, | |
| /* PMXVF64GERNN */ | |
| acc, acc, vsrpevenrc, vsrc, u4imm, u2imm, | |
| /* PMXVF64GERNP */ | |
| acc, acc, vsrpevenrc, vsrc, u4imm, u2imm, | |
| /* PMXVF64GERPN */ | |
| acc, acc, vsrpevenrc, vsrc, u4imm, u2imm, | |
| /* PMXVF64GERPP */ | |
| acc, acc, vsrpevenrc, vsrc, u4imm, u2imm, | |
| /* PMXVF64GERW */ | |
| wacc, vsrpevenrc, vsrc, u4imm, u2imm, | |
| /* PMXVF64GERWNN */ | |
| wacc, wacc, vsrpevenrc, vsrc, u4imm, u2imm, | |
| /* PMXVF64GERWNP */ | |
| wacc, wacc, vsrpevenrc, vsrc, u4imm, u2imm, | |
| /* PMXVF64GERWPN */ | |
| wacc, wacc, vsrpevenrc, vsrc, u4imm, u2imm, | |
| /* PMXVF64GERWPP */ | |
| wacc, wacc, vsrpevenrc, vsrc, u4imm, u2imm, | |
| /* PMXVI16GER2 */ | |
| acc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVI16GER2PP */ | |
| acc, acc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVI16GER2S */ | |
| acc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVI16GER2SPP */ | |
| acc, acc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVI16GER2SW */ | |
| wacc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVI16GER2SWPP */ | |
| wacc, wacc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVI16GER2W */ | |
| wacc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVI16GER2WPP */ | |
| acc, wacc, vsrc, vsrc, u4imm, u4imm, u2imm, | |
| /* PMXVI4GER8 */ | |
| acc, vsrc, vsrc, u4imm, u4imm, u8imm, | |
| /* PMXVI4GER8PP */ | |
| acc, acc, vsrc, vsrc, u4imm, u4imm, u8imm, | |
| /* PMXVI4GER8W */ | |
| wacc, vsrc, vsrc, u4imm, u4imm, u8imm, | |
| /* PMXVI4GER8WPP */ | |
| wacc, wacc, vsrc, vsrc, u4imm, u4imm, u8imm, | |
| /* PMXVI8GER4 */ | |
| acc, vsrc, vsrc, u4imm, u4imm, u4imm, | |
| /* PMXVI8GER4PP */ | |
| acc, acc, vsrc, vsrc, u4imm, u4imm, u4imm, | |
| /* PMXVI8GER4SPP */ | |
| acc, acc, vsrc, vsrc, u4imm, u4imm, u4imm, | |
| /* PMXVI8GER4W */ | |
| wacc, vsrc, vsrc, u4imm, u4imm, u4imm, | |
| /* PMXVI8GER4WPP */ | |
| wacc, wacc, vsrc, vsrc, u4imm, u4imm, u4imm, | |
| /* PMXVI8GER4WSPP */ | |
| wacc, wacc, vsrc, vsrc, u4imm, u4imm, u4imm, | |
| /* POPCNTB */ | |
| gprc, gprc, | |
| /* POPCNTB8 */ | |
| g8rc, g8rc, | |
| /* POPCNTD */ | |
| g8rc, g8rc, | |
| /* POPCNTW */ | |
| gprc, gprc, | |
| /* PPC32GOT */ | |
| gprc, | |
| /* PPC32PICGOT */ | |
| gprc, gprc, | |
| /* PREPARE_PROBED_ALLOCA_32 */ | |
| gprc, gprc, gprc, dispRI, ptr_rc_nor0, | |
| /* PREPARE_PROBED_ALLOCA_64 */ | |
| g8rc, g8rc, g8rc, dispRI, ptr_rc_nor0, | |
| /* PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 */ | |
| gprc, gprc, gprc, dispRI, ptr_rc_nor0, | |
| /* PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 */ | |
| g8rc, g8rc, g8rc, dispRI, ptr_rc_nor0, | |
| /* PROBED_ALLOCA_32 */ | |
| gprc, gprc, dispRI, ptr_rc_nor0, | |
| /* PROBED_ALLOCA_64 */ | |
| g8rc, g8rc, dispRI, ptr_rc_nor0, | |
| /* PROBED_STACKALLOC_32 */ | |
| gprc, gprc, i64imm, | |
| /* PROBED_STACKALLOC_64 */ | |
| g8rc, g8rc, i64imm, | |
| /* PSTB */ | |
| gprc, dispRI34, ptr_rc_nor0, | |
| /* PSTB8 */ | |
| g8rc, dispRI34, ptr_rc_nor0, | |
| /* PSTB8pc */ | |
| g8rc, dispRI34, immZero, | |
| /* PSTBpc */ | |
| gprc, dispRI34, immZero, | |
| /* PSTD */ | |
| g8rc, dispRI34, ptr_rc_nor0, | |
| /* PSTDpc */ | |
| g8rc, dispRI34, immZero, | |
| /* PSTFD */ | |
| f8rc, dispRI34, ptr_rc_nor0, | |
| /* PSTFDpc */ | |
| f8rc, dispRI34, immZero, | |
| /* PSTFS */ | |
| f4rc, dispRI34, ptr_rc_nor0, | |
| /* PSTFSpc */ | |
| f4rc, dispRI34, immZero, | |
| /* PSTH */ | |
| gprc, dispRI34, ptr_rc_nor0, | |
| /* PSTH8 */ | |
| g8rc, dispRI34, ptr_rc_nor0, | |
| /* PSTH8pc */ | |
| g8rc, dispRI34, immZero, | |
| /* PSTHpc */ | |
| gprc, dispRI34, immZero, | |
| /* PSTW */ | |
| gprc, dispRI34, ptr_rc_nor0, | |
| /* PSTW8 */ | |
| g8rc, dispRI34, ptr_rc_nor0, | |
| /* PSTW8pc */ | |
| g8rc, dispRI34, immZero, | |
| /* PSTWpc */ | |
| gprc, dispRI34, immZero, | |
| /* PSTXSD */ | |
| vfrc, dispRI34, ptr_rc_nor0, | |
| /* PSTXSDpc */ | |
| vfrc, dispRI34, immZero, | |
| /* PSTXSSP */ | |
| vfrc, dispRI34, ptr_rc_nor0, | |
| /* PSTXSSPpc */ | |
| vfrc, dispRI34, immZero, | |
| /* PSTXV */ | |
| vsrc, dispRI34, ptr_rc_nor0, | |
| /* PSTXVP */ | |
| vsrprc, dispRI34, ptr_rc_nor0, | |
| /* PSTXVPpc */ | |
| vsrprc, dispRI34, immZero, | |
| /* PSTXVpc */ | |
| vsrc, dispRI34, immZero, | |
| /* PseudoEIEIO */ | |
| /* RESTORE_ACC */ | |
| acc, dispRIX16, ptr_rc_nor0, | |
| /* RESTORE_CR */ | |
| crrc, dispRI, ptr_rc_nor0, | |
| /* RESTORE_CRBIT */ | |
| crbitrc, dispRI, ptr_rc_nor0, | |
| /* RESTORE_QUADWORD */ | |
| g8prc, dispRIX, ptr_rc_nor0, | |
| /* RESTORE_UACC */ | |
| uacc, dispRIX16, ptr_rc_nor0, | |
| /* RESTORE_WACC */ | |
| wacc, dispRIX16, ptr_rc_nor0, | |
| /* RFCI */ | |
| /* RFDI */ | |
| /* RFEBB */ | |
| u1imm, | |
| /* RFI */ | |
| /* RFID */ | |
| /* RFMCI */ | |
| /* RLDCL */ | |
| g8rc, g8rc, gprc, u6imm, | |
| /* RLDCL_rec */ | |
| g8rc, g8rc, gprc, u6imm, | |
| /* RLDCR */ | |
| g8rc, g8rc, gprc, u6imm, | |
| /* RLDCR_rec */ | |
| g8rc, g8rc, gprc, u6imm, | |
| /* RLDIC */ | |
| g8rc, g8rc, u6imm, u6imm, | |
| /* RLDICL */ | |
| g8rc, g8rc, u6imm, u6imm, | |
| /* RLDICL_32 */ | |
| gprc, gprc, u6imm, u6imm, | |
| /* RLDICL_32_64 */ | |
| g8rc, gprc, u6imm, u6imm, | |
| /* RLDICL_32_rec */ | |
| gprc, gprc, u6imm, u6imm, | |
| /* RLDICL_rec */ | |
| g8rc, g8rc, u6imm, u6imm, | |
| /* RLDICR */ | |
| g8rc, g8rc, u6imm, u6imm, | |
| /* RLDICR_32 */ | |
| gprc, gprc, u6imm, u6imm, | |
| /* RLDICR_rec */ | |
| g8rc, g8rc, u6imm, u6imm, | |
| /* RLDIC_rec */ | |
| g8rc, g8rc, u6imm, u6imm, | |
| /* RLDIMI */ | |
| g8rc, g8rc, g8rc, u6imm, u6imm, | |
| /* RLDIMI_rec */ | |
| g8rc, g8rc, g8rc, u6imm, u6imm, | |
| /* RLWIMI */ | |
| gprc, gprc, gprc, u5imm, u5imm, u5imm, | |
| /* RLWIMI8 */ | |
| g8rc, g8rc, g8rc, u5imm, u5imm, u5imm, | |
| /* RLWIMI8_rec */ | |
| g8rc, g8rc, g8rc, u5imm, u5imm, u5imm, | |
| /* RLWIMI_rec */ | |
| gprc, gprc, gprc, u5imm, u5imm, u5imm, | |
| /* RLWINM */ | |
| gprc, gprc, u5imm, u5imm, u5imm, | |
| /* RLWINM8 */ | |
| g8rc, g8rc, u5imm, u5imm, u5imm, | |
| /* RLWINM8_rec */ | |
| g8rc, g8rc, u5imm, u5imm, u5imm, | |
| /* RLWINM_rec */ | |
| gprc, gprc, u5imm, u5imm, u5imm, | |
| /* RLWNM */ | |
| gprc, gprc, gprc, u5imm, u5imm, | |
| /* RLWNM8 */ | |
| g8rc, g8rc, g8rc, u5imm, u5imm, | |
| /* RLWNM8_rec */ | |
| g8rc, g8rc, g8rc, u5imm, u5imm, | |
| /* RLWNM_rec */ | |
| gprc, gprc, gprc, u5imm, u5imm, | |
| /* ReadTB */ | |
| gprc, gprc, | |
| /* SC */ | |
| i32imm, | |
| /* SELECT_CC_F16 */ | |
| vrrc, crrc, vrrc, vrrc, i32imm, | |
| /* SELECT_CC_F4 */ | |
| f4rc, crrc, f4rc, f4rc, i32imm, | |
| /* SELECT_CC_F8 */ | |
| f8rc, crrc, f8rc, f8rc, i32imm, | |
| /* SELECT_CC_I4 */ | |
| gprc, crrc, gprc_nor0, gprc_nor0, i32imm, | |
| /* SELECT_CC_I8 */ | |
| g8rc, crrc, g8rc_nox0, g8rc_nox0, i32imm, | |
| /* SELECT_CC_SPE */ | |
| sperc, crrc, sperc, sperc, i32imm, | |
| /* SELECT_CC_SPE4 */ | |
| spe4rc, crrc, spe4rc, spe4rc, i32imm, | |
| /* SELECT_CC_VRRC */ | |
| vrrc, crrc, vrrc, vrrc, i32imm, | |
| /* SELECT_CC_VSFRC */ | |
| f8rc, crrc, f8rc, f8rc, i32imm, | |
| /* SELECT_CC_VSRC */ | |
| vsrc, crrc, vsrc, vsrc, i32imm, | |
| /* SELECT_CC_VSSRC */ | |
| f4rc, crrc, f4rc, f4rc, i32imm, | |
| /* SELECT_F16 */ | |
| vrrc, crbitrc, vrrc, vrrc, | |
| /* SELECT_F4 */ | |
| f4rc, crbitrc, f4rc, f4rc, | |
| /* SELECT_F8 */ | |
| f8rc, crbitrc, f8rc, f8rc, | |
| /* SELECT_I4 */ | |
| gprc, crbitrc, gprc_nor0, gprc_nor0, | |
| /* SELECT_I8 */ | |
| g8rc, crbitrc, g8rc_nox0, g8rc_nox0, | |
| /* SELECT_SPE */ | |
| sperc, crbitrc, sperc, sperc, | |
| /* SELECT_SPE4 */ | |
| spe4rc, crbitrc, spe4rc, spe4rc, | |
| /* SELECT_VRRC */ | |
| vrrc, crbitrc, vrrc, vrrc, | |
| /* SELECT_VSFRC */ | |
| f8rc, crbitrc, f8rc, f8rc, | |
| /* SELECT_VSRC */ | |
| vsrc, crbitrc, vsrc, vsrc, | |
| /* SELECT_VSSRC */ | |
| f4rc, crbitrc, f4rc, f4rc, | |
| /* SETB */ | |
| gprc, crrc, | |
| /* SETB8 */ | |
| g8rc, crrc, | |
| /* SETBC */ | |
| gprc, crbitrc, | |
| /* SETBC8 */ | |
| g8rc, crbitrc, | |
| /* SETBCR */ | |
| gprc, crbitrc, | |
| /* SETBCR8 */ | |
| g8rc, crbitrc, | |
| /* SETFLM */ | |
| f8rc, f8rc, | |
| /* SETNBC */ | |
| gprc, crbitrc, | |
| /* SETNBC8 */ | |
| g8rc, crbitrc, | |
| /* SETNBCR */ | |
| gprc, crbitrc, | |
| /* SETNBCR8 */ | |
| g8rc, crbitrc, | |
| /* SETRND */ | |
| f8rc, gprc, | |
| /* SETRNDi */ | |
| f8rc, u2imm, | |
| /* SLBFEE_rec */ | |
| gprc, gprc, | |
| /* SLBIA */ | |
| /* SLBIE */ | |
| gprc, | |
| /* SLBIEG */ | |
| gprc, gprc, | |
| /* SLBMFEE */ | |
| gprc, gprc, | |
| /* SLBMFEV */ | |
| gprc, gprc, | |
| /* SLBMTE */ | |
| gprc, gprc, | |
| /* SLBSYNC */ | |
| /* SLD */ | |
| g8rc, g8rc, gprc, | |
| /* SLD_rec */ | |
| g8rc, g8rc, gprc, | |
| /* SLW */ | |
| gprc, gprc, gprc, | |
| /* SLW8 */ | |
| g8rc, g8rc, g8rc, | |
| /* SLW8_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* SLW_rec */ | |
| gprc, gprc, gprc, | |
| /* SPELWZ */ | |
| spe4rc, dispRI, ptr_rc_nor0, | |
| /* SPELWZX */ | |
| spe4rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* SPESTW */ | |
| spe4rc, dispRI, ptr_rc_nor0, | |
| /* SPESTWX */ | |
| spe4rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* SPILL_ACC */ | |
| acc, dispRIX16, ptr_rc_nor0, | |
| /* SPILL_CR */ | |
| crrc, dispRI, ptr_rc_nor0, | |
| /* SPILL_CRBIT */ | |
| crbitrc, dispRI, ptr_rc_nor0, | |
| /* SPILL_QUADWORD */ | |
| g8prc, dispRIX, ptr_rc_nor0, | |
| /* SPILL_UACC */ | |
| uacc, dispRIX16, ptr_rc_nor0, | |
| /* SPILL_WACC */ | |
| wacc, dispRIX16, ptr_rc_nor0, | |
| /* SPLIT_QUADWORD */ | |
| g8rc, g8rc, g8prc, | |
| /* SRAD */ | |
| g8rc, g8rc, gprc, | |
| /* SRADI */ | |
| g8rc, g8rc, u6imm, | |
| /* SRADI_32 */ | |
| gprc, gprc, u6imm, | |
| /* SRADI_rec */ | |
| g8rc, g8rc, u6imm, | |
| /* SRAD_rec */ | |
| g8rc, g8rc, gprc, | |
| /* SRAW */ | |
| gprc, gprc, gprc, | |
| /* SRAWI */ | |
| gprc, gprc, u5imm, | |
| /* SRAWI_rec */ | |
| gprc, gprc, u5imm, | |
| /* SRAW_rec */ | |
| gprc, gprc, gprc, | |
| /* SRD */ | |
| g8rc, g8rc, gprc, | |
| /* SRD_rec */ | |
| g8rc, g8rc, gprc, | |
| /* SRW */ | |
| gprc, gprc, gprc, | |
| /* SRW8 */ | |
| g8rc, g8rc, g8rc, | |
| /* SRW8_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* SRW_rec */ | |
| gprc, gprc, gprc, | |
| /* STB */ | |
| gprc, dispRI, ptr_rc_nor0, | |
| /* STB8 */ | |
| g8rc, dispRI, ptr_rc_nor0, | |
| /* STBCIX */ | |
| gprc, gprc, gprc, | |
| /* STBCX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STBEPX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STBU */ | |
| ptr_rc_nor0, gprc, dispRI, ptr_rc_nor0, | |
| /* STBU8 */ | |
| ptr_rc_nor0, g8rc, dispRI, ptr_rc_nor0, | |
| /* STBUX */ | |
| ptr_rc_nor0, gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STBUX8 */ | |
| ptr_rc_nor0, g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STBX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STBX8 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STBXTLS */ | |
| g8rc, ptr_rc_nor0, tlsreg, | |
| /* STBXTLS_ */ | |
| g8rc, ptr_rc_nor0, tlsreg, | |
| /* STBXTLS_32 */ | |
| gprc, ptr_rc_nor0, tlsreg, | |
| /* STD */ | |
| g8rc, dispRIX, ptr_rc_nor0, | |
| /* STDAT */ | |
| g8rc, g8rc, u5imm, | |
| /* STDBRX */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STDCIX */ | |
| gprc, gprc, gprc, | |
| /* STDCX */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STDU */ | |
| ptr_rc_nor0, g8rc, dispRIX, ptr_rc_nor0, | |
| /* STDUX */ | |
| ptr_rc_nor0, g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STDX */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STDXTLS */ | |
| g8rc, ptr_rc_nor0, tlsreg, | |
| /* STDXTLS_ */ | |
| g8rc, ptr_rc_nor0, tlsreg, | |
| /* STFD */ | |
| f8rc, dispRI, ptr_rc_nor0, | |
| /* STFDEPX */ | |
| f8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STFDU */ | |
| ptr_rc_nor0, f8rc, dispRI, ptr_rc_nor0, | |
| /* STFDUX */ | |
| ptr_rc_nor0, f8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STFDX */ | |
| f8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STFIWX */ | |
| f8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STFS */ | |
| f4rc, dispRI, ptr_rc_nor0, | |
| /* STFSU */ | |
| ptr_rc_nor0, f4rc, dispRI, ptr_rc_nor0, | |
| /* STFSUX */ | |
| ptr_rc_nor0, f4rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STFSX */ | |
| f4rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STH */ | |
| gprc, dispRI, ptr_rc_nor0, | |
| /* STH8 */ | |
| g8rc, dispRI, ptr_rc_nor0, | |
| /* STHBRX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STHCIX */ | |
| gprc, gprc, gprc, | |
| /* STHCX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STHEPX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STHU */ | |
| ptr_rc_nor0, gprc, dispRI, ptr_rc_nor0, | |
| /* STHU8 */ | |
| ptr_rc_nor0, g8rc, dispRI, ptr_rc_nor0, | |
| /* STHUX */ | |
| ptr_rc_nor0, gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STHUX8 */ | |
| ptr_rc_nor0, g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STHX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STHX8 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STHXTLS */ | |
| g8rc, ptr_rc_nor0, tlsreg, | |
| /* STHXTLS_ */ | |
| g8rc, ptr_rc_nor0, tlsreg, | |
| /* STHXTLS_32 */ | |
| gprc, ptr_rc_nor0, tlsreg, | |
| /* STMW */ | |
| gprc, dispRI, ptr_rc_nor0, | |
| /* STOP */ | |
| /* STQ */ | |
| g8prc, dispRIX, ptr_rc_nor0, | |
| /* STQCX */ | |
| g8prc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STQX_PSEUDO */ | |
| g8prc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STSWI */ | |
| gprc, gprc, u5imm, | |
| /* STVEBX */ | |
| vrrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STVEHX */ | |
| vrrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STVEWX */ | |
| vrrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STVX */ | |
| vrrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STVXL */ | |
| vrrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STW */ | |
| gprc, dispRI, ptr_rc_nor0, | |
| /* STW8 */ | |
| g8rc, dispRI, ptr_rc_nor0, | |
| /* STWAT */ | |
| gprc, gprc, u5imm, | |
| /* STWBRX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STWCIX */ | |
| gprc, gprc, gprc, | |
| /* STWCX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STWEPX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STWU */ | |
| ptr_rc_nor0, gprc, dispRI, ptr_rc_nor0, | |
| /* STWU8 */ | |
| ptr_rc_nor0, g8rc, dispRI, ptr_rc_nor0, | |
| /* STWUX */ | |
| ptr_rc_nor0, gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STWUX8 */ | |
| ptr_rc_nor0, g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STWX */ | |
| gprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STWX8 */ | |
| g8rc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STWXTLS */ | |
| g8rc, ptr_rc_nor0, tlsreg, | |
| /* STWXTLS_ */ | |
| g8rc, ptr_rc_nor0, tlsreg, | |
| /* STWXTLS_32 */ | |
| gprc, ptr_rc_nor0, tlsreg, | |
| /* STXSD */ | |
| vfrc, dispRIX, ptr_rc_nor0, | |
| /* STXSDX */ | |
| vsfrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STXSIBX */ | |
| vsfrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STXSIBXv */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STXSIHX */ | |
| vsfrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STXSIHXv */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STXSIWX */ | |
| vsfrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STXSSP */ | |
| vfrc, dispRIX, ptr_rc_nor0, | |
| /* STXSSPX */ | |
| vssrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STXV */ | |
| vsrc, dispRIX16, ptr_rc_nor0, | |
| /* STXVB16X */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STXVD2X */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STXVH8X */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STXVL */ | |
| vsrc, ptr_rc_nor0, g8rc, | |
| /* STXVLL */ | |
| vsrc, ptr_rc_nor0, g8rc, | |
| /* STXVP */ | |
| vsrprc, dispRIX16, ptr_rc_nor0, | |
| /* STXVPRL */ | |
| vsrprc, ptr_rc_nor0, g8rc, | |
| /* STXVPRLL */ | |
| vsrprc, ptr_rc_nor0, g8rc, | |
| /* STXVPX */ | |
| vsrprc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STXVRBX */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STXVRDX */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STXVRHX */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STXVRL */ | |
| vsrc, ptr_rc_nor0, g8rc, | |
| /* STXVRLL */ | |
| vsrc, ptr_rc_nor0, g8rc, | |
| /* STXVRWX */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STXVW4X */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* STXVX */ | |
| vsrc, ptr_rc_nor0, ptr_rc_idx, | |
| /* SUBF */ | |
| gprc, gprc, gprc, | |
| /* SUBF8 */ | |
| g8rc, g8rc, g8rc, | |
| /* SUBF8O */ | |
| g8rc, g8rc, g8rc, | |
| /* SUBF8O_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* SUBF8_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* SUBFC */ | |
| gprc, gprc, gprc, | |
| /* SUBFC8 */ | |
| g8rc, g8rc, g8rc, | |
| /* SUBFC8O */ | |
| g8rc, g8rc, g8rc, | |
| /* SUBFC8O_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* SUBFC8_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* SUBFCO */ | |
| gprc, gprc, gprc, | |
| /* SUBFCO_rec */ | |
| gprc, gprc, gprc, | |
| /* SUBFC_rec */ | |
| gprc, gprc, gprc, | |
| /* SUBFE */ | |
| gprc, gprc, gprc, | |
| /* SUBFE8 */ | |
| g8rc, g8rc, g8rc, | |
| /* SUBFE8O */ | |
| g8rc, g8rc, g8rc, | |
| /* SUBFE8O_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* SUBFE8_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* SUBFEO */ | |
| gprc, gprc, gprc, | |
| /* SUBFEO_rec */ | |
| gprc, gprc, gprc, | |
| /* SUBFE_rec */ | |
| gprc, gprc, gprc, | |
| /* SUBFIC */ | |
| gprc, gprc, s16imm, | |
| /* SUBFIC8 */ | |
| g8rc, g8rc, s16imm64, | |
| /* SUBFME */ | |
| gprc, gprc, | |
| /* SUBFME8 */ | |
| g8rc, g8rc, | |
| /* SUBFME8O */ | |
| g8rc, g8rc, | |
| /* SUBFME8O_rec */ | |
| g8rc, g8rc, | |
| /* SUBFME8_rec */ | |
| g8rc, g8rc, | |
| /* SUBFMEO */ | |
| gprc, gprc, | |
| /* SUBFMEO_rec */ | |
| gprc, gprc, | |
| /* SUBFME_rec */ | |
| gprc, gprc, | |
| /* SUBFO */ | |
| gprc, gprc, gprc, | |
| /* SUBFO_rec */ | |
| gprc, gprc, gprc, | |
| /* SUBFUS */ | |
| g8rc, g8rc, g8rc, u1imm, | |
| /* SUBFUS_rec */ | |
| g8rc, g8rc, g8rc, u1imm, | |
| /* SUBFZE */ | |
| gprc, gprc, | |
| /* SUBFZE8 */ | |
| g8rc, g8rc, | |
| /* SUBFZE8O */ | |
| g8rc, g8rc, | |
| /* SUBFZE8O_rec */ | |
| g8rc, g8rc, | |
| /* SUBFZE8_rec */ | |
| g8rc, g8rc, | |
| /* SUBFZEO */ | |
| gprc, gprc, | |
| /* SUBFZEO_rec */ | |
| gprc, gprc, | |
| /* SUBFZE_rec */ | |
| gprc, gprc, | |
| /* SUBF_rec */ | |
| gprc, gprc, gprc, | |
| /* SYNC */ | |
| u2imm, | |
| /* TABORT */ | |
| gprc, | |
| /* TABORTDC */ | |
| u5imm, gprc, gprc, | |
| /* TABORTDCI */ | |
| u5imm, gprc, u5imm, | |
| /* TABORTWC */ | |
| u5imm, gprc, gprc, | |
| /* TABORTWCI */ | |
| u5imm, gprc, u5imm, | |
| /* TAILB */ | |
| calltarget, | |
| /* TAILB8 */ | |
| calltarget, | |
| /* TAILBA */ | |
| abscalltarget, | |
| /* TAILBA8 */ | |
| abscalltarget, | |
| /* TAILBCTR */ | |
| /* TAILBCTR8 */ | |
| /* TBEGIN */ | |
| u1imm, | |
| /* TBEGIN_RET */ | |
| gprc, u1imm, | |
| /* TCHECK */ | |
| crrc, | |
| /* TCHECK_RET */ | |
| gprc, | |
| /* TCRETURNai */ | |
| abscalltarget, i32imm, | |
| /* TCRETURNai8 */ | |
| abscalltarget, i32imm, | |
| /* TCRETURNdi */ | |
| calltarget, i32imm, | |
| /* TCRETURNdi8 */ | |
| calltarget, i32imm, | |
| /* TCRETURNri */ | |
| CTRRC, i32imm, | |
| /* TCRETURNri8 */ | |
| CTRRC8, i32imm, | |
| /* TD */ | |
| u5imm, g8rc, g8rc, | |
| /* TDI */ | |
| u5imm, g8rc, s16imm, | |
| /* TEND */ | |
| u1imm, | |
| /* TLBIA */ | |
| /* TLBIE */ | |
| gprc, gprc, | |
| /* TLBIEL */ | |
| gprc, | |
| /* TLBIVAX */ | |
| gprc, gprc, | |
| /* TLBLD */ | |
| gprc, | |
| /* TLBLI */ | |
| gprc, | |
| /* TLBRE */ | |
| /* TLBRE2 */ | |
| gprc, gprc, i1imm, | |
| /* TLBSX */ | |
| gprc, gprc, | |
| /* TLBSX2 */ | |
| gprc, gprc, gprc, | |
| /* TLBSX2D */ | |
| gprc, gprc, gprc, | |
| /* TLBSYNC */ | |
| /* TLBWE */ | |
| /* TLBWE2 */ | |
| gprc, gprc, i1imm, | |
| /* TLSGDAIX */ | |
| gprc, gprc, gprc, | |
| /* TLSGDAIX8 */ | |
| g8rc, g8rc, g8rc, | |
| /* TRAP */ | |
| /* TRECHKPT */ | |
| /* TRECLAIM */ | |
| gprc, | |
| /* TSR */ | |
| u1imm, | |
| /* TW */ | |
| u5imm, gprc, gprc, | |
| /* TWI */ | |
| u5imm, gprc, s16imm, | |
| /* UNENCODED_NOP */ | |
| /* UpdateGBR */ | |
| gprc, gprc, gprc, | |
| /* VABSDUB */ | |
| vrrc, vrrc, vrrc, | |
| /* VABSDUH */ | |
| vrrc, vrrc, vrrc, | |
| /* VABSDUW */ | |
| vrrc, vrrc, vrrc, | |
| /* VADDCUQ */ | |
| vrrc, vrrc, vrrc, | |
| /* VADDCUW */ | |
| vrrc, vrrc, vrrc, | |
| /* VADDECUQ */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VADDEUQM */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VADDFP */ | |
| vrrc, vrrc, vrrc, | |
| /* VADDSBS */ | |
| vrrc, vrrc, vrrc, | |
| /* VADDSHS */ | |
| vrrc, vrrc, vrrc, | |
| /* VADDSWS */ | |
| vrrc, vrrc, vrrc, | |
| /* VADDUBM */ | |
| vrrc, vrrc, vrrc, | |
| /* VADDUBS */ | |
| vrrc, vrrc, vrrc, | |
| /* VADDUDM */ | |
| vrrc, vrrc, vrrc, | |
| /* VADDUHM */ | |
| vrrc, vrrc, vrrc, | |
| /* VADDUHS */ | |
| vrrc, vrrc, vrrc, | |
| /* VADDUQM */ | |
| vrrc, vrrc, vrrc, | |
| /* VADDUWM */ | |
| vrrc, vrrc, vrrc, | |
| /* VADDUWS */ | |
| vrrc, vrrc, vrrc, | |
| /* VAND */ | |
| vrrc, vrrc, vrrc, | |
| /* VANDC */ | |
| vrrc, vrrc, vrrc, | |
| /* VAVGSB */ | |
| vrrc, vrrc, vrrc, | |
| /* VAVGSH */ | |
| vrrc, vrrc, vrrc, | |
| /* VAVGSW */ | |
| vrrc, vrrc, vrrc, | |
| /* VAVGUB */ | |
| vrrc, vrrc, vrrc, | |
| /* VAVGUH */ | |
| vrrc, vrrc, vrrc, | |
| /* VAVGUW */ | |
| vrrc, vrrc, vrrc, | |
| /* VBPERMD */ | |
| vrrc, vrrc, vrrc, | |
| /* VBPERMQ */ | |
| vrrc, vrrc, vrrc, | |
| /* VCFSX */ | |
| vrrc, u5imm, vrrc, | |
| /* VCFSX_0 */ | |
| vrrc, vrrc, | |
| /* VCFUGED */ | |
| vrrc, vrrc, vrrc, | |
| /* VCFUX */ | |
| vrrc, u5imm, vrrc, | |
| /* VCFUX_0 */ | |
| vrrc, vrrc, | |
| /* VCIPHER */ | |
| vrrc, vrrc, vrrc, | |
| /* VCIPHERLAST */ | |
| vrrc, vrrc, vrrc, | |
| /* VCLRLB */ | |
| vrrc, vrrc, gprc, | |
| /* VCLRRB */ | |
| vrrc, vrrc, gprc, | |
| /* VCLZB */ | |
| vrrc, vrrc, | |
| /* VCLZD */ | |
| vrrc, vrrc, | |
| /* VCLZDM */ | |
| vrrc, vrrc, vrrc, | |
| /* VCLZH */ | |
| vrrc, vrrc, | |
| /* VCLZLSBB */ | |
| gprc, vrrc, | |
| /* VCLZW */ | |
| vrrc, vrrc, | |
| /* VCMPBFP */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPBFP_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPEQFP */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPEQFP_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPEQUB */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPEQUB_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPEQUD */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPEQUD_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPEQUH */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPEQUH_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPEQUQ */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPEQUQ_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPEQUW */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPEQUW_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGEFP */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGEFP_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTFP */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTFP_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTSB */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTSB_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTSD */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTSD_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTSH */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTSH_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTSQ */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTSQ_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTSW */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTSW_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTUB */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTUB_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTUD */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTUD_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTUH */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTUH_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTUQ */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTUQ_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTUW */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPGTUW_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPNEB */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPNEB_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPNEH */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPNEH_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPNEW */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPNEW_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPNEZB */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPNEZB_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPNEZH */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPNEZH_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPNEZW */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPNEZW_rec */ | |
| vrrc, vrrc, vrrc, | |
| /* VCMPSQ */ | |
| crrc, vrrc, vrrc, | |
| /* VCMPUQ */ | |
| crrc, vrrc, vrrc, | |
| /* VCNTMBB */ | |
| g8rc, vrrc, u1imm, | |
| /* VCNTMBD */ | |
| g8rc, vrrc, u1imm, | |
| /* VCNTMBH */ | |
| g8rc, vrrc, u1imm, | |
| /* VCNTMBW */ | |
| g8rc, vrrc, u1imm, | |
| /* VCTSXS */ | |
| vrrc, u5imm, vrrc, | |
| /* VCTSXS_0 */ | |
| vrrc, vrrc, | |
| /* VCTUXS */ | |
| vrrc, u5imm, vrrc, | |
| /* VCTUXS_0 */ | |
| vrrc, vrrc, | |
| /* VCTZB */ | |
| vrrc, vrrc, | |
| /* VCTZD */ | |
| vrrc, vrrc, | |
| /* VCTZDM */ | |
| vrrc, vrrc, vrrc, | |
| /* VCTZH */ | |
| vrrc, vrrc, | |
| /* VCTZLSBB */ | |
| gprc, vrrc, | |
| /* VCTZW */ | |
| vrrc, vrrc, | |
| /* VDIVESD */ | |
| vrrc, vrrc, vrrc, | |
| /* VDIVESQ */ | |
| vrrc, vrrc, vrrc, | |
| /* VDIVESW */ | |
| vrrc, vrrc, vrrc, | |
| /* VDIVEUD */ | |
| vrrc, vrrc, vrrc, | |
| /* VDIVEUQ */ | |
| vrrc, vrrc, vrrc, | |
| /* VDIVEUW */ | |
| vrrc, vrrc, vrrc, | |
| /* VDIVSD */ | |
| vrrc, vrrc, vrrc, | |
| /* VDIVSQ */ | |
| vrrc, vrrc, vrrc, | |
| /* VDIVSW */ | |
| vrrc, vrrc, vrrc, | |
| /* VDIVUD */ | |
| vrrc, vrrc, vrrc, | |
| /* VDIVUQ */ | |
| vrrc, vrrc, vrrc, | |
| /* VDIVUW */ | |
| vrrc, vrrc, vrrc, | |
| /* VEQV */ | |
| vrrc, vrrc, vrrc, | |
| /* VEXPANDBM */ | |
| vrrc, vrrc, | |
| /* VEXPANDDM */ | |
| vrrc, vrrc, | |
| /* VEXPANDHM */ | |
| vrrc, vrrc, | |
| /* VEXPANDQM */ | |
| vrrc, vrrc, | |
| /* VEXPANDWM */ | |
| vrrc, vrrc, | |
| /* VEXPTEFP */ | |
| vrrc, vrrc, | |
| /* VEXTDDVLX */ | |
| vrrc, vrrc, vrrc, gprc, | |
| /* VEXTDDVRX */ | |
| vrrc, vrrc, vrrc, gprc, | |
| /* VEXTDUBVLX */ | |
| vrrc, vrrc, vrrc, gprc, | |
| /* VEXTDUBVRX */ | |
| vrrc, vrrc, vrrc, gprc, | |
| /* VEXTDUHVLX */ | |
| vrrc, vrrc, vrrc, gprc, | |
| /* VEXTDUHVRX */ | |
| vrrc, vrrc, vrrc, gprc, | |
| /* VEXTDUWVLX */ | |
| vrrc, vrrc, vrrc, gprc, | |
| /* VEXTDUWVRX */ | |
| vrrc, vrrc, vrrc, gprc, | |
| /* VEXTRACTBM */ | |
| gprc, vrrc, | |
| /* VEXTRACTD */ | |
| vrrc, u4imm, vrrc, | |
| /* VEXTRACTDM */ | |
| gprc, vrrc, | |
| /* VEXTRACTHM */ | |
| gprc, vrrc, | |
| /* VEXTRACTQM */ | |
| gprc, vrrc, | |
| /* VEXTRACTUB */ | |
| vrrc, u4imm, vrrc, | |
| /* VEXTRACTUH */ | |
| vrrc, u4imm, vrrc, | |
| /* VEXTRACTUW */ | |
| vrrc, u4imm, vrrc, | |
| /* VEXTRACTWM */ | |
| gprc, vrrc, | |
| /* VEXTSB2D */ | |
| vrrc, vrrc, | |
| /* VEXTSB2Ds */ | |
| vfrc, vfrc, | |
| /* VEXTSB2W */ | |
| vrrc, vrrc, | |
| /* VEXTSB2Ws */ | |
| vfrc, vfrc, | |
| /* VEXTSD2Q */ | |
| vrrc, vrrc, | |
| /* VEXTSH2D */ | |
| vrrc, vrrc, | |
| /* VEXTSH2Ds */ | |
| vfrc, vfrc, | |
| /* VEXTSH2W */ | |
| vrrc, vrrc, | |
| /* VEXTSH2Ws */ | |
| vfrc, vfrc, | |
| /* VEXTSW2D */ | |
| vrrc, vrrc, | |
| /* VEXTSW2Ds */ | |
| vfrc, vfrc, | |
| /* VEXTUBLX */ | |
| g8rc, g8rc, vrrc, | |
| /* VEXTUBRX */ | |
| g8rc, g8rc, vrrc, | |
| /* VEXTUHLX */ | |
| g8rc, g8rc, vrrc, | |
| /* VEXTUHRX */ | |
| g8rc, g8rc, vrrc, | |
| /* VEXTUWLX */ | |
| g8rc, g8rc, vrrc, | |
| /* VEXTUWRX */ | |
| g8rc, g8rc, vrrc, | |
| /* VGBBD */ | |
| vrrc, vrrc, | |
| /* VGNB */ | |
| g8rc, vrrc, u3imm, | |
| /* VINSBLX */ | |
| vrrc, vrrc, gprc, gprc, | |
| /* VINSBRX */ | |
| vrrc, vrrc, gprc, gprc, | |
| /* VINSBVLX */ | |
| vrrc, vrrc, gprc, vrrc, | |
| /* VINSBVRX */ | |
| vrrc, vrrc, gprc, vrrc, | |
| /* VINSD */ | |
| vrrc, vrrc, u4imm, g8rc, | |
| /* VINSDLX */ | |
| vrrc, vrrc, g8rc, g8rc, | |
| /* VINSDRX */ | |
| vrrc, vrrc, g8rc, g8rc, | |
| /* VINSERTB */ | |
| vrrc, vrrc, u4imm, vrrc, | |
| /* VINSERTD */ | |
| vrrc, u4imm, vrrc, | |
| /* VINSERTH */ | |
| vrrc, vrrc, u4imm, vrrc, | |
| /* VINSERTW */ | |
| vrrc, u4imm, vrrc, | |
| /* VINSHLX */ | |
| vrrc, vrrc, gprc, gprc, | |
| /* VINSHRX */ | |
| vrrc, vrrc, gprc, gprc, | |
| /* VINSHVLX */ | |
| vrrc, vrrc, gprc, vrrc, | |
| /* VINSHVRX */ | |
| vrrc, vrrc, gprc, vrrc, | |
| /* VINSW */ | |
| vrrc, vrrc, u4imm, gprc, | |
| /* VINSWLX */ | |
| vrrc, vrrc, gprc, gprc, | |
| /* VINSWRX */ | |
| vrrc, vrrc, gprc, gprc, | |
| /* VINSWVLX */ | |
| vrrc, vrrc, gprc, vrrc, | |
| /* VINSWVRX */ | |
| vrrc, vrrc, gprc, vrrc, | |
| /* VLOGEFP */ | |
| vrrc, vrrc, | |
| /* VMADDFP */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VMAXFP */ | |
| vrrc, vrrc, vrrc, | |
| /* VMAXSB */ | |
| vrrc, vrrc, vrrc, | |
| /* VMAXSD */ | |
| vrrc, vrrc, vrrc, | |
| /* VMAXSH */ | |
| vrrc, vrrc, vrrc, | |
| /* VMAXSW */ | |
| vrrc, vrrc, vrrc, | |
| /* VMAXUB */ | |
| vrrc, vrrc, vrrc, | |
| /* VMAXUD */ | |
| vrrc, vrrc, vrrc, | |
| /* VMAXUH */ | |
| vrrc, vrrc, vrrc, | |
| /* VMAXUW */ | |
| vrrc, vrrc, vrrc, | |
| /* VMHADDSHS */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VMHRADDSHS */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VMINFP */ | |
| vrrc, vrrc, vrrc, | |
| /* VMINSB */ | |
| vrrc, vrrc, vrrc, | |
| /* VMINSD */ | |
| vrrc, vrrc, vrrc, | |
| /* VMINSH */ | |
| vrrc, vrrc, vrrc, | |
| /* VMINSW */ | |
| vrrc, vrrc, vrrc, | |
| /* VMINUB */ | |
| vrrc, vrrc, vrrc, | |
| /* VMINUD */ | |
| vrrc, vrrc, vrrc, | |
| /* VMINUH */ | |
| vrrc, vrrc, vrrc, | |
| /* VMINUW */ | |
| vrrc, vrrc, vrrc, | |
| /* VMLADDUHM */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VMODSD */ | |
| vrrc, vrrc, vrrc, | |
| /* VMODSQ */ | |
| vrrc, vrrc, vrrc, | |
| /* VMODSW */ | |
| vrrc, vrrc, vrrc, | |
| /* VMODUD */ | |
| vrrc, vrrc, vrrc, | |
| /* VMODUQ */ | |
| vrrc, vrrc, vrrc, | |
| /* VMODUW */ | |
| vrrc, vrrc, vrrc, | |
| /* VMRGEW */ | |
| vrrc, vrrc, vrrc, | |
| /* VMRGHB */ | |
| vrrc, vrrc, vrrc, | |
| /* VMRGHH */ | |
| vrrc, vrrc, vrrc, | |
| /* VMRGHW */ | |
| vrrc, vrrc, vrrc, | |
| /* VMRGLB */ | |
| vrrc, vrrc, vrrc, | |
| /* VMRGLH */ | |
| vrrc, vrrc, vrrc, | |
| /* VMRGLW */ | |
| vrrc, vrrc, vrrc, | |
| /* VMRGOW */ | |
| vrrc, vrrc, vrrc, | |
| /* VMSUMCUD */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VMSUMMBM */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VMSUMSHM */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VMSUMSHS */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VMSUMUBM */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VMSUMUDM */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VMSUMUHM */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VMSUMUHS */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VMUL10CUQ */ | |
| vrrc, vrrc, | |
| /* VMUL10ECUQ */ | |
| vrrc, vrrc, vrrc, | |
| /* VMUL10EUQ */ | |
| vrrc, vrrc, vrrc, | |
| /* VMUL10UQ */ | |
| vrrc, vrrc, | |
| /* VMULESB */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULESD */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULESH */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULESW */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULEUB */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULEUD */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULEUH */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULEUW */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULHSD */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULHSW */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULHUD */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULHUW */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULLD */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULOSB */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULOSD */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULOSH */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULOSW */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULOUB */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULOUD */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULOUH */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULOUW */ | |
| vrrc, vrrc, vrrc, | |
| /* VMULUWM */ | |
| vrrc, vrrc, vrrc, | |
| /* VNAND */ | |
| vrrc, vrrc, vrrc, | |
| /* VNCIPHER */ | |
| vrrc, vrrc, vrrc, | |
| /* VNCIPHERLAST */ | |
| vrrc, vrrc, vrrc, | |
| /* VNEGD */ | |
| vrrc, vrrc, | |
| /* VNEGW */ | |
| vrrc, vrrc, | |
| /* VNMSUBFP */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VNOR */ | |
| vrrc, vrrc, vrrc, | |
| /* VOR */ | |
| vrrc, vrrc, vrrc, | |
| /* VORC */ | |
| vrrc, vrrc, vrrc, | |
| /* VPDEPD */ | |
| vrrc, vrrc, vrrc, | |
| /* VPERM */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VPERMR */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VPERMXOR */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VPEXTD */ | |
| vrrc, vrrc, vrrc, | |
| /* VPKPX */ | |
| vrrc, vrrc, vrrc, | |
| /* VPKSDSS */ | |
| vrrc, vrrc, vrrc, | |
| /* VPKSDUS */ | |
| vrrc, vrrc, vrrc, | |
| /* VPKSHSS */ | |
| vrrc, vrrc, vrrc, | |
| /* VPKSHUS */ | |
| vrrc, vrrc, vrrc, | |
| /* VPKSWSS */ | |
| vrrc, vrrc, vrrc, | |
| /* VPKSWUS */ | |
| vrrc, vrrc, vrrc, | |
| /* VPKUDUM */ | |
| vrrc, vrrc, vrrc, | |
| /* VPKUDUS */ | |
| vrrc, vrrc, vrrc, | |
| /* VPKUHUM */ | |
| vrrc, vrrc, vrrc, | |
| /* VPKUHUS */ | |
| vrrc, vrrc, vrrc, | |
| /* VPKUWUM */ | |
| vrrc, vrrc, vrrc, | |
| /* VPKUWUS */ | |
| vrrc, vrrc, vrrc, | |
| /* VPMSUMB */ | |
| vrrc, vrrc, vrrc, | |
| /* VPMSUMD */ | |
| vrrc, vrrc, vrrc, | |
| /* VPMSUMH */ | |
| vrrc, vrrc, vrrc, | |
| /* VPMSUMW */ | |
| vrrc, vrrc, vrrc, | |
| /* VPOPCNTB */ | |
| vrrc, vrrc, | |
| /* VPOPCNTD */ | |
| vrrc, vrrc, | |
| /* VPOPCNTH */ | |
| vrrc, vrrc, | |
| /* VPOPCNTW */ | |
| vrrc, vrrc, | |
| /* VPRTYBD */ | |
| vrrc, vrrc, | |
| /* VPRTYBQ */ | |
| vrrc, vrrc, | |
| /* VPRTYBW */ | |
| vrrc, vrrc, | |
| /* VREFP */ | |
| vrrc, vrrc, | |
| /* VRFIM */ | |
| vrrc, vrrc, | |
| /* VRFIN */ | |
| vrrc, vrrc, | |
| /* VRFIP */ | |
| vrrc, vrrc, | |
| /* VRFIZ */ | |
| vrrc, vrrc, | |
| /* VRLB */ | |
| vrrc, vrrc, vrrc, | |
| /* VRLD */ | |
| vrrc, vrrc, vrrc, | |
| /* VRLDMI */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VRLDNM */ | |
| vrrc, vrrc, vrrc, | |
| /* VRLH */ | |
| vrrc, vrrc, vrrc, | |
| /* VRLQ */ | |
| vrrc, vrrc, vrrc, | |
| /* VRLQMI */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VRLQNM */ | |
| vrrc, vrrc, vrrc, | |
| /* VRLW */ | |
| vrrc, vrrc, vrrc, | |
| /* VRLWMI */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VRLWNM */ | |
| vrrc, vrrc, vrrc, | |
| /* VRSQRTEFP */ | |
| vrrc, vrrc, | |
| /* VSBOX */ | |
| vrrc, vrrc, | |
| /* VSEL */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VSHASIGMAD */ | |
| vrrc, vrrc, u1imm, u4imm, | |
| /* VSHASIGMAW */ | |
| vrrc, vrrc, u1imm, u4imm, | |
| /* VSL */ | |
| vrrc, vrrc, vrrc, | |
| /* VSLB */ | |
| vrrc, vrrc, vrrc, | |
| /* VSLD */ | |
| vrrc, vrrc, vrrc, | |
| /* VSLDBI */ | |
| vrrc, vrrc, vrrc, u3imm, | |
| /* VSLDOI */ | |
| vrrc, vrrc, vrrc, u4imm, | |
| /* VSLH */ | |
| vrrc, vrrc, vrrc, | |
| /* VSLO */ | |
| vrrc, vrrc, vrrc, | |
| /* VSLQ */ | |
| vrrc, vrrc, vrrc, | |
| /* VSLV */ | |
| vrrc, vrrc, vrrc, | |
| /* VSLW */ | |
| vrrc, vrrc, vrrc, | |
| /* VSPLTB */ | |
| vrrc, u5imm, vrrc, | |
| /* VSPLTBs */ | |
| vrrc, u5imm, vfrc, | |
| /* VSPLTH */ | |
| vrrc, u5imm, vrrc, | |
| /* VSPLTHs */ | |
| vrrc, u5imm, vfrc, | |
| /* VSPLTISB */ | |
| vrrc, s5imm, | |
| /* VSPLTISH */ | |
| vrrc, s5imm, | |
| /* VSPLTISW */ | |
| vrrc, s5imm, | |
| /* VSPLTW */ | |
| vrrc, u5imm, vrrc, | |
| /* VSR */ | |
| vrrc, vrrc, vrrc, | |
| /* VSRAB */ | |
| vrrc, vrrc, vrrc, | |
| /* VSRAD */ | |
| vrrc, vrrc, vrrc, | |
| /* VSRAH */ | |
| vrrc, vrrc, vrrc, | |
| /* VSRAQ */ | |
| vrrc, vrrc, vrrc, | |
| /* VSRAW */ | |
| vrrc, vrrc, vrrc, | |
| /* VSRB */ | |
| vrrc, vrrc, vrrc, | |
| /* VSRD */ | |
| vrrc, vrrc, vrrc, | |
| /* VSRDBI */ | |
| vrrc, vrrc, vrrc, u3imm, | |
| /* VSRH */ | |
| vrrc, vrrc, vrrc, | |
| /* VSRO */ | |
| vrrc, vrrc, vrrc, | |
| /* VSRQ */ | |
| vrrc, vrrc, vrrc, | |
| /* VSRV */ | |
| vrrc, vrrc, vrrc, | |
| /* VSRW */ | |
| vrrc, vrrc, vrrc, | |
| /* VSTRIBL */ | |
| vrrc, vrrc, | |
| /* VSTRIBL_rec */ | |
| vrrc, vrrc, | |
| /* VSTRIBR */ | |
| vrrc, vrrc, | |
| /* VSTRIBR_rec */ | |
| vrrc, vrrc, | |
| /* VSTRIHL */ | |
| vrrc, vrrc, | |
| /* VSTRIHL_rec */ | |
| vrrc, vrrc, | |
| /* VSTRIHR */ | |
| vrrc, vrrc, | |
| /* VSTRIHR_rec */ | |
| vrrc, vrrc, | |
| /* VSUBCUQ */ | |
| vrrc, vrrc, vrrc, | |
| /* VSUBCUW */ | |
| vrrc, vrrc, vrrc, | |
| /* VSUBECUQ */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VSUBEUQM */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* VSUBFP */ | |
| vrrc, vrrc, vrrc, | |
| /* VSUBSBS */ | |
| vrrc, vrrc, vrrc, | |
| /* VSUBSHS */ | |
| vrrc, vrrc, vrrc, | |
| /* VSUBSWS */ | |
| vrrc, vrrc, vrrc, | |
| /* VSUBUBM */ | |
| vrrc, vrrc, vrrc, | |
| /* VSUBUBS */ | |
| vrrc, vrrc, vrrc, | |
| /* VSUBUDM */ | |
| vrrc, vrrc, vrrc, | |
| /* VSUBUHM */ | |
| vrrc, vrrc, vrrc, | |
| /* VSUBUHS */ | |
| vrrc, vrrc, vrrc, | |
| /* VSUBUQM */ | |
| vrrc, vrrc, vrrc, | |
| /* VSUBUWM */ | |
| vrrc, vrrc, vrrc, | |
| /* VSUBUWS */ | |
| vrrc, vrrc, vrrc, | |
| /* VSUM2SWS */ | |
| vrrc, vrrc, vrrc, | |
| /* VSUM4SBS */ | |
| vrrc, vrrc, vrrc, | |
| /* VSUM4SHS */ | |
| vrrc, vrrc, vrrc, | |
| /* VSUM4UBS */ | |
| vrrc, vrrc, vrrc, | |
| /* VSUMSWS */ | |
| vrrc, vrrc, vrrc, | |
| /* VUPKHPX */ | |
| vrrc, vrrc, | |
| /* VUPKHSB */ | |
| vrrc, vrrc, | |
| /* VUPKHSH */ | |
| vrrc, vrrc, | |
| /* VUPKHSW */ | |
| vrrc, vrrc, | |
| /* VUPKLPX */ | |
| vrrc, vrrc, | |
| /* VUPKLSB */ | |
| vrrc, vrrc, | |
| /* VUPKLSH */ | |
| vrrc, vrrc, | |
| /* VUPKLSW */ | |
| vrrc, vrrc, | |
| /* VXOR */ | |
| vrrc, vrrc, vrrc, | |
| /* V_SET0 */ | |
| vrrc, | |
| /* V_SET0B */ | |
| vrrc, | |
| /* V_SET0H */ | |
| vrrc, | |
| /* V_SETALLONES */ | |
| vrrc, | |
| /* V_SETALLONESB */ | |
| vrrc, | |
| /* V_SETALLONESH */ | |
| vrrc, | |
| /* WAIT */ | |
| u2imm, | |
| /* WRTEE */ | |
| gprc, | |
| /* WRTEEI */ | |
| i1imm, | |
| /* XOR */ | |
| gprc, gprc, gprc, | |
| /* XOR8 */ | |
| g8rc, g8rc, g8rc, | |
| /* XOR8_rec */ | |
| g8rc, g8rc, g8rc, | |
| /* XORI */ | |
| gprc, gprc, u16imm, | |
| /* XORI8 */ | |
| g8rc, g8rc, u16imm64, | |
| /* XORIS */ | |
| gprc, gprc, u16imm, | |
| /* XORIS8 */ | |
| g8rc, g8rc, u16imm64, | |
| /* XOR_rec */ | |
| gprc, gprc, gprc, | |
| /* XSABSDP */ | |
| vsfrc, vsfrc, | |
| /* XSABSQP */ | |
| vrrc, vrrc, | |
| /* XSADDDP */ | |
| vsfrc, vsfrc, vsfrc, | |
| /* XSADDQP */ | |
| vrrc, vrrc, vrrc, | |
| /* XSADDQPO */ | |
| vrrc, vrrc, vrrc, | |
| /* XSADDSP */ | |
| vssrc, vssrc, vssrc, | |
| /* XSCMPEQDP */ | |
| vsrc, vsfrc, vsfrc, | |
| /* XSCMPEQQP */ | |
| vrrc, vrrc, vrrc, | |
| /* XSCMPEXPDP */ | |
| crrc, vsfrc, vsfrc, | |
| /* XSCMPEXPQP */ | |
| crrc, vrrc, vrrc, | |
| /* XSCMPGEDP */ | |
| vsrc, vsfrc, vsfrc, | |
| /* XSCMPGEQP */ | |
| vrrc, vrrc, vrrc, | |
| /* XSCMPGTDP */ | |
| vsrc, vsfrc, vsfrc, | |
| /* XSCMPGTQP */ | |
| vrrc, vrrc, vrrc, | |
| /* XSCMPODP */ | |
| crrc, vsfrc, vsfrc, | |
| /* XSCMPOQP */ | |
| crrc, vrrc, vrrc, | |
| /* XSCMPUDP */ | |
| crrc, vsfrc, vsfrc, | |
| /* XSCMPUQP */ | |
| crrc, vrrc, vrrc, | |
| /* XSCPSGNDP */ | |
| vsfrc, vsfrc, vsfrc, | |
| /* XSCPSGNQP */ | |
| vrrc, vrrc, vrrc, | |
| /* XSCVDPHP */ | |
| vsfrc, vsfrc, | |
| /* XSCVDPQP */ | |
| vrrc, vfrc, | |
| /* XSCVDPSP */ | |
| vsfrc, vsfrc, | |
| /* XSCVDPSPN */ | |
| vsrc, vssrc, | |
| /* XSCVDPSXDS */ | |
| vsfrc, vsfrc, | |
| /* XSCVDPSXDSs */ | |
| vssrc, vssrc, | |
| /* XSCVDPSXWS */ | |
| vsfrc, vsfrc, | |
| /* XSCVDPSXWSs */ | |
| vssrc, vssrc, | |
| /* XSCVDPUXDS */ | |
| vsfrc, vsfrc, | |
| /* XSCVDPUXDSs */ | |
| vssrc, vssrc, | |
| /* XSCVDPUXWS */ | |
| vsfrc, vsfrc, | |
| /* XSCVDPUXWSs */ | |
| vssrc, vssrc, | |
| /* XSCVHPDP */ | |
| vsfrc, vsfrc, | |
| /* XSCVQPDP */ | |
| vfrc, vrrc, | |
| /* XSCVQPDPO */ | |
| vfrc, vrrc, | |
| /* XSCVQPSDZ */ | |
| vrrc, vrrc, | |
| /* XSCVQPSQZ */ | |
| vrrc, vrrc, | |
| /* XSCVQPSWZ */ | |
| vrrc, vrrc, | |
| /* XSCVQPUDZ */ | |
| vrrc, vrrc, | |
| /* XSCVQPUQZ */ | |
| vrrc, vrrc, | |
| /* XSCVQPUWZ */ | |
| vrrc, vrrc, | |
| /* XSCVSDQP */ | |
| vrrc, vfrc, | |
| /* XSCVSPDP */ | |
| vsfrc, vsfrc, | |
| /* XSCVSPDPN */ | |
| vssrc, vsrc, | |
| /* XSCVSQQP */ | |
| vrrc, vrrc, | |
| /* XSCVSXDDP */ | |
| vsfrc, vsfrc, | |
| /* XSCVSXDSP */ | |
| vssrc, vsfrc, | |
| /* XSCVUDQP */ | |
| vrrc, vfrc, | |
| /* XSCVUQQP */ | |
| vrrc, vrrc, | |
| /* XSCVUXDDP */ | |
| vsfrc, vsfrc, | |
| /* XSCVUXDSP */ | |
| vssrc, vsfrc, | |
| /* XSDIVDP */ | |
| vsfrc, vsfrc, vsfrc, | |
| /* XSDIVQP */ | |
| vrrc, vrrc, vrrc, | |
| /* XSDIVQPO */ | |
| vrrc, vrrc, vrrc, | |
| /* XSDIVSP */ | |
| vssrc, vssrc, vssrc, | |
| /* XSIEXPDP */ | |
| vsrc, g8rc, g8rc, | |
| /* XSIEXPQP */ | |
| vrrc, vrrc, vsfrc, | |
| /* XSMADDADP */ | |
| vsfrc, vsfrc, vsfrc, vsfrc, | |
| /* XSMADDASP */ | |
| vssrc, vssrc, vssrc, vssrc, | |
| /* XSMADDMDP */ | |
| vsfrc, vsfrc, vsfrc, vsfrc, | |
| /* XSMADDMSP */ | |
| vssrc, vssrc, vssrc, vssrc, | |
| /* XSMADDQP */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* XSMADDQPO */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* XSMAXCDP */ | |
| vsfrc, vsfrc, vsfrc, | |
| /* XSMAXCQP */ | |
| vrrc, vrrc, vrrc, | |
| /* XSMAXDP */ | |
| vsfrc, vsfrc, vsfrc, | |
| /* XSMAXJDP */ | |
| vsrc, vsfrc, vsfrc, | |
| /* XSMINCDP */ | |
| vsfrc, vsfrc, vsfrc, | |
| /* XSMINCQP */ | |
| vrrc, vrrc, vrrc, | |
| /* XSMINDP */ | |
| vsfrc, vsfrc, vsfrc, | |
| /* XSMINJDP */ | |
| vsrc, vsfrc, vsfrc, | |
| /* XSMSUBADP */ | |
| vsfrc, vsfrc, vsfrc, vsfrc, | |
| /* XSMSUBASP */ | |
| vssrc, vssrc, vssrc, vssrc, | |
| /* XSMSUBMDP */ | |
| vsfrc, vsfrc, vsfrc, vsfrc, | |
| /* XSMSUBMSP */ | |
| vssrc, vssrc, vssrc, vssrc, | |
| /* XSMSUBQP */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* XSMSUBQPO */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* XSMULDP */ | |
| vsfrc, vsfrc, vsfrc, | |
| /* XSMULQP */ | |
| vrrc, vrrc, vrrc, | |
| /* XSMULQPO */ | |
| vrrc, vrrc, vrrc, | |
| /* XSMULSP */ | |
| vssrc, vssrc, vssrc, | |
| /* XSNABSDP */ | |
| vsfrc, vsfrc, | |
| /* XSNABSDPs */ | |
| vssrc, vssrc, | |
| /* XSNABSQP */ | |
| vrrc, vrrc, | |
| /* XSNEGDP */ | |
| vsfrc, vsfrc, | |
| /* XSNEGQP */ | |
| vrrc, vrrc, | |
| /* XSNMADDADP */ | |
| vsfrc, vsfrc, vsfrc, vsfrc, | |
| /* XSNMADDASP */ | |
| vssrc, vssrc, vssrc, vssrc, | |
| /* XSNMADDMDP */ | |
| vsfrc, vsfrc, vsfrc, vsfrc, | |
| /* XSNMADDMSP */ | |
| vssrc, vssrc, vssrc, vssrc, | |
| /* XSNMADDQP */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* XSNMADDQPO */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* XSNMSUBADP */ | |
| vsfrc, vsfrc, vsfrc, vsfrc, | |
| /* XSNMSUBASP */ | |
| vssrc, vssrc, vssrc, vssrc, | |
| /* XSNMSUBMDP */ | |
| vsfrc, vsfrc, vsfrc, vsfrc, | |
| /* XSNMSUBMSP */ | |
| vssrc, vssrc, vssrc, vssrc, | |
| /* XSNMSUBQP */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* XSNMSUBQPO */ | |
| vrrc, vrrc, vrrc, vrrc, | |
| /* XSRDPI */ | |
| vsfrc, vsfrc, | |
| /* XSRDPIC */ | |
| vsfrc, vsfrc, | |
| /* XSRDPIM */ | |
| vsfrc, vsfrc, | |
| /* XSRDPIP */ | |
| vsfrc, vsfrc, | |
| /* XSRDPIZ */ | |
| vsfrc, vsfrc, | |
| /* XSREDP */ | |
| vsfrc, vsfrc, | |
| /* XSRESP */ | |
| vssrc, vssrc, | |
| /* XSRQPI */ | |
| vrrc, u1imm, vrrc, u2imm, | |
| /* XSRQPIX */ | |
| vrrc, u1imm, vrrc, u2imm, | |
| /* XSRQPXP */ | |
| vrrc, u1imm, vrrc, u2imm, | |
| /* XSRSP */ | |
| vssrc, vsfrc, | |
| /* XSRSQRTEDP */ | |
| vsfrc, vsfrc, | |
| /* XSRSQRTESP */ | |
| vssrc, vssrc, | |
| /* XSSQRTDP */ | |
| vsfrc, vsfrc, | |
| /* XSSQRTQP */ | |
| vrrc, vrrc, | |
| /* XSSQRTQPO */ | |
| vrrc, vrrc, | |
| /* XSSQRTSP */ | |
| vssrc, vssrc, | |
| /* XSSUBDP */ | |
| vsfrc, vsfrc, vsfrc, | |
| /* XSSUBQP */ | |
| vrrc, vrrc, vrrc, | |
| /* XSSUBQPO */ | |
| vrrc, vrrc, vrrc, | |
| /* XSSUBSP */ | |
| vssrc, vssrc, vssrc, | |
| /* XSTDIVDP */ | |
| crrc, vsfrc, vsfrc, | |
| /* XSTSQRTDP */ | |
| crrc, vsfrc, | |
| /* XSTSTDCDP */ | |
| crrc, u7imm, vsfrc, | |
| /* XSTSTDCQP */ | |
| crrc, u7imm, vrrc, | |
| /* XSTSTDCSP */ | |
| crrc, u7imm, vsfrc, | |
| /* XSXEXPDP */ | |
| g8rc, vsfrc, | |
| /* XSXEXPQP */ | |
| vrrc, vrrc, | |
| /* XSXSIGDP */ | |
| g8rc, vsfrc, | |
| /* XSXSIGQP */ | |
| vrrc, vrrc, | |
| /* XVABSDP */ | |
| vsrc, vsrc, | |
| /* XVABSSP */ | |
| vsrc, vsrc, | |
| /* XVADDDP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVADDSP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVBF16GER2 */ | |
| acc, vsrc, vsrc, | |
| /* XVBF16GER2NN */ | |
| acc, acc, vsrc, vsrc, | |
| /* XVBF16GER2NP */ | |
| acc, acc, vsrc, vsrc, | |
| /* XVBF16GER2PN */ | |
| acc, acc, vsrc, vsrc, | |
| /* XVBF16GER2PP */ | |
| acc, acc, vsrc, vsrc, | |
| /* XVBF16GER2W */ | |
| wacc, vsrc, vsrc, | |
| /* XVBF16GER2WNN */ | |
| wacc, wacc, vsrc, vsrc, | |
| /* XVBF16GER2WNP */ | |
| wacc, wacc, vsrc, vsrc, | |
| /* XVBF16GER2WPN */ | |
| wacc, wacc, vsrc, vsrc, | |
| /* XVBF16GER2WPP */ | |
| wacc, wacc, vsrc, vsrc, | |
| /* XVCMPEQDP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVCMPEQDP_rec */ | |
| vsrc, vsrc, vsrc, | |
| /* XVCMPEQSP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVCMPEQSP_rec */ | |
| vsrc, vsrc, vsrc, | |
| /* XVCMPGEDP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVCMPGEDP_rec */ | |
| vsrc, vsrc, vsrc, | |
| /* XVCMPGESP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVCMPGESP_rec */ | |
| vsrc, vsrc, vsrc, | |
| /* XVCMPGTDP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVCMPGTDP_rec */ | |
| vsrc, vsrc, vsrc, | |
| /* XVCMPGTSP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVCMPGTSP_rec */ | |
| vsrc, vsrc, vsrc, | |
| /* XVCPSGNDP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVCPSGNSP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVCVBF16SPN */ | |
| vsrc, vsrc, | |
| /* XVCVDPSP */ | |
| vsrc, vsrc, | |
| /* XVCVDPSXDS */ | |
| vsrc, vsrc, | |
| /* XVCVDPSXWS */ | |
| vsrc, vsrc, | |
| /* XVCVDPUXDS */ | |
| vsrc, vsrc, | |
| /* XVCVDPUXWS */ | |
| vsrc, vsrc, | |
| /* XVCVHPSP */ | |
| vsrc, vsrc, | |
| /* XVCVSPBF16 */ | |
| vsrc, vsrc, | |
| /* XVCVSPDP */ | |
| vsrc, vsrc, | |
| /* XVCVSPHP */ | |
| vsrc, vsrc, | |
| /* XVCVSPSXDS */ | |
| vsrc, vsrc, | |
| /* XVCVSPSXWS */ | |
| vsrc, vsrc, | |
| /* XVCVSPUXDS */ | |
| vsrc, vsrc, | |
| /* XVCVSPUXWS */ | |
| vsrc, vsrc, | |
| /* XVCVSXDDP */ | |
| vsrc, vsrc, | |
| /* XVCVSXDSP */ | |
| vsrc, vsrc, | |
| /* XVCVSXWDP */ | |
| vsrc, vsrc, | |
| /* XVCVSXWSP */ | |
| vsrc, vsrc, | |
| /* XVCVUXDDP */ | |
| vsrc, vsrc, | |
| /* XVCVUXDSP */ | |
| vsrc, vsrc, | |
| /* XVCVUXWDP */ | |
| vsrc, vsrc, | |
| /* XVCVUXWSP */ | |
| vsrc, vsrc, | |
| /* XVDIVDP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVDIVSP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVF16GER2 */ | |
| acc, vsrc, vsrc, | |
| /* XVF16GER2NN */ | |
| acc, acc, vsrc, vsrc, | |
| /* XVF16GER2NP */ | |
| acc, acc, vsrc, vsrc, | |
| /* XVF16GER2PN */ | |
| acc, acc, vsrc, vsrc, | |
| /* XVF16GER2PP */ | |
| acc, acc, vsrc, vsrc, | |
| /* XVF16GER2W */ | |
| wacc, vsrc, vsrc, | |
| /* XVF16GER2WNN */ | |
| wacc, wacc, vsrc, vsrc, | |
| /* XVF16GER2WNP */ | |
| wacc, wacc, vsrc, vsrc, | |
| /* XVF16GER2WPN */ | |
| wacc, wacc, vsrc, vsrc, | |
| /* XVF16GER2WPP */ | |
| wacc, wacc, vsrc, vsrc, | |
| /* XVF32GER */ | |
| acc, vsrc, vsrc, | |
| /* XVF32GERNN */ | |
| acc, acc, vsrc, vsrc, | |
| /* XVF32GERNP */ | |
| acc, acc, vsrc, vsrc, | |
| /* XVF32GERPN */ | |
| acc, acc, vsrc, vsrc, | |
| /* XVF32GERPP */ | |
| acc, acc, vsrc, vsrc, | |
| /* XVF32GERW */ | |
| wacc, vsrc, vsrc, | |
| /* XVF32GERWNN */ | |
| wacc, wacc, vsrc, vsrc, | |
| /* XVF32GERWNP */ | |
| wacc, wacc, vsrc, vsrc, | |
| /* XVF32GERWPN */ | |
| wacc, wacc, vsrc, vsrc, | |
| /* XVF32GERWPP */ | |
| wacc, wacc, vsrc, vsrc, | |
| /* XVF64GER */ | |
| acc, vsrpevenrc, vsrc, | |
| /* XVF64GERNN */ | |
| acc, acc, vsrpevenrc, vsrc, | |
| /* XVF64GERNP */ | |
| acc, acc, vsrpevenrc, vsrc, | |
| /* XVF64GERPN */ | |
| acc, acc, vsrpevenrc, vsrc, | |
| /* XVF64GERPP */ | |
| acc, acc, vsrpevenrc, vsrc, | |
| /* XVF64GERW */ | |
| wacc, vsrpevenrc, vsrc, | |
| /* XVF64GERWNN */ | |
| wacc, wacc, vsrpevenrc, vsrc, | |
| /* XVF64GERWNP */ | |
| wacc, wacc, vsrpevenrc, vsrc, | |
| /* XVF64GERWPN */ | |
| wacc, wacc, vsrpevenrc, vsrc, | |
| /* XVF64GERWPP */ | |
| wacc, wacc, vsrpevenrc, vsrc, | |
| /* XVI16GER2 */ | |
| acc, vsrc, vsrc, | |
| /* XVI16GER2PP */ | |
| acc, acc, vsrc, vsrc, | |
| /* XVI16GER2S */ | |
| acc, vsrc, vsrc, | |
| /* XVI16GER2SPP */ | |
| acc, acc, vsrc, vsrc, | |
| /* XVI16GER2SW */ | |
| wacc, vsrc, vsrc, | |
| /* XVI16GER2SWPP */ | |
| wacc, wacc, vsrc, vsrc, | |
| /* XVI16GER2W */ | |
| wacc, vsrc, vsrc, | |
| /* XVI16GER2WPP */ | |
| wacc, wacc, vsrc, vsrc, | |
| /* XVI4GER8 */ | |
| acc, vsrc, vsrc, | |
| /* XVI4GER8PP */ | |
| acc, acc, vsrc, vsrc, | |
| /* XVI4GER8W */ | |
| wacc, vsrc, vsrc, | |
| /* XVI4GER8WPP */ | |
| wacc, wacc, vsrc, vsrc, | |
| /* XVI8GER4 */ | |
| acc, vsrc, vsrc, | |
| /* XVI8GER4PP */ | |
| acc, acc, vsrc, vsrc, | |
| /* XVI8GER4SPP */ | |
| acc, acc, vsrc, vsrc, | |
| /* XVI8GER4W */ | |
| wacc, vsrc, vsrc, | |
| /* XVI8GER4WPP */ | |
| wacc, wacc, vsrc, vsrc, | |
| /* XVI8GER4WSPP */ | |
| wacc, wacc, vsrc, vsrc, | |
| /* XVIEXPDP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVIEXPSP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVMADDADP */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XVMADDASP */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XVMADDMDP */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XVMADDMSP */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XVMAXDP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVMAXSP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVMINDP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVMINSP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVMSUBADP */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XVMSUBASP */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XVMSUBMDP */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XVMSUBMSP */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XVMULDP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVMULSP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVNABSDP */ | |
| vsrc, vsrc, | |
| /* XVNABSSP */ | |
| vsrc, vsrc, | |
| /* XVNEGDP */ | |
| vsrc, vsrc, | |
| /* XVNEGSP */ | |
| vsrc, vsrc, | |
| /* XVNMADDADP */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XVNMADDASP */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XVNMADDMDP */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XVNMADDMSP */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XVNMSUBADP */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XVNMSUBASP */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XVNMSUBMDP */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XVNMSUBMSP */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XVRDPI */ | |
| vsrc, vsrc, | |
| /* XVRDPIC */ | |
| vsrc, vsrc, | |
| /* XVRDPIM */ | |
| vsrc, vsrc, | |
| /* XVRDPIP */ | |
| vsrc, vsrc, | |
| /* XVRDPIZ */ | |
| vsrc, vsrc, | |
| /* XVREDP */ | |
| vsrc, vsrc, | |
| /* XVRESP */ | |
| vsrc, vsrc, | |
| /* XVRSPI */ | |
| vsrc, vsrc, | |
| /* XVRSPIC */ | |
| vsrc, vsrc, | |
| /* XVRSPIM */ | |
| vsrc, vsrc, | |
| /* XVRSPIP */ | |
| vsrc, vsrc, | |
| /* XVRSPIZ */ | |
| vsrc, vsrc, | |
| /* XVRSQRTEDP */ | |
| vsrc, vsrc, | |
| /* XVRSQRTESP */ | |
| vsrc, vsrc, | |
| /* XVSQRTDP */ | |
| vsrc, vsrc, | |
| /* XVSQRTSP */ | |
| vsrc, vsrc, | |
| /* XVSUBDP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVSUBSP */ | |
| vsrc, vsrc, vsrc, | |
| /* XVTDIVDP */ | |
| crrc, vsrc, vsrc, | |
| /* XVTDIVSP */ | |
| crrc, vsrc, vsrc, | |
| /* XVTLSBB */ | |
| crrc, vsrc, | |
| /* XVTSQRTDP */ | |
| crrc, vsrc, | |
| /* XVTSQRTSP */ | |
| crrc, vsrc, | |
| /* XVTSTDCDP */ | |
| vsrc, u7imm, vsrc, | |
| /* XVTSTDCSP */ | |
| vsrc, u7imm, vsrc, | |
| /* XVXEXPDP */ | |
| vsrc, vsrc, | |
| /* XVXEXPSP */ | |
| vsrc, vsrc, | |
| /* XVXSIGDP */ | |
| vsrc, vsrc, | |
| /* XVXSIGSP */ | |
| vsrc, vsrc, | |
| /* XXBLENDVB */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XXBLENDVD */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XXBLENDVH */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XXBLENDVW */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XXBRD */ | |
| vsrc, vsrc, | |
| /* XXBRH */ | |
| vsrc, vsrc, | |
| /* XXBRQ */ | |
| vsrc, vsrc, | |
| /* XXBRW */ | |
| vsrc, vsrc, | |
| /* XXEVAL */ | |
| vsrc, vsrc, vsrc, vsrc, u8imm, | |
| /* XXEXTRACTUW */ | |
| vsfrc, vsrc, u4imm, | |
| /* XXGENPCVBM */ | |
| vsrc, vrrc, s5imm, | |
| /* XXGENPCVDM */ | |
| vsrc, vrrc, s5imm, | |
| /* XXGENPCVHM */ | |
| vsrc, vrrc, s5imm, | |
| /* XXGENPCVWM */ | |
| vsrc, vrrc, s5imm, | |
| /* XXINSERTW */ | |
| vsrc, vsrc, vsrc, u4imm, | |
| /* XXLAND */ | |
| vsrc, vsrc, vsrc, | |
| /* XXLANDC */ | |
| vsrc, vsrc, vsrc, | |
| /* XXLEQV */ | |
| vsrc, vsrc, vsrc, | |
| /* XXLEQVOnes */ | |
| vsrc, | |
| /* XXLNAND */ | |
| vsrc, vsrc, vsrc, | |
| /* XXLNOR */ | |
| vsrc, vsrc, vsrc, | |
| /* XXLOR */ | |
| vsrc, vsrc, vsrc, | |
| /* XXLORC */ | |
| vsrc, vsrc, vsrc, | |
| /* XXLORf */ | |
| vsfrc, vsfrc, vsfrc, | |
| /* XXLXOR */ | |
| vsrc, vsrc, vsrc, | |
| /* XXLXORdpz */ | |
| vsfrc, | |
| /* XXLXORspz */ | |
| vssrc, | |
| /* XXLXORz */ | |
| vsrc, | |
| /* XXMFACC */ | |
| acc, acc, | |
| /* XXMFACCW */ | |
| wacc, wacc, | |
| /* XXMRGHW */ | |
| vsrc, vsrc, vsrc, | |
| /* XXMRGLW */ | |
| vsrc, vsrc, vsrc, | |
| /* XXMTACC */ | |
| acc, acc, | |
| /* XXMTACCW */ | |
| wacc, wacc, | |
| /* XXPERM */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XXPERMDI */ | |
| vsrc, vsrc, vsrc, u2imm, | |
| /* XXPERMDIs */ | |
| vsrc, vsfrc, u2imm, | |
| /* XXPERMR */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XXPERMX */ | |
| vsrc, vsrc, vsrc, vsrc, u3imm, | |
| /* XXSEL */ | |
| vsrc, vsrc, vsrc, vsrc, | |
| /* XXSETACCZ */ | |
| acc, | |
| /* XXSETACCZW */ | |
| wacc, | |
| /* XXSLDWI */ | |
| vsrc, vsrc, vsrc, u2imm, | |
| /* XXSLDWIs */ | |
| vsrc, vsfrc, u2imm, | |
| /* XXSPLTI32DX */ | |
| vsrc, vsrc, u1imm, i32imm, | |
| /* XXSPLTIB */ | |
| vsrc, u8imm, | |
| /* XXSPLTIDP */ | |
| vsrc, i32imm, | |
| /* XXSPLTIW */ | |
| vsrc, i32imm, | |
| /* XXSPLTW */ | |
| vsrc, vsrc, u2imm, | |
| /* XXSPLTWs */ | |
| vsrc, vsfrc, u2imm, | |
| /* gBC */ | |
| u5imm, crbitrc, condbrtarget, | |
| /* gBCA */ | |
| u5imm, crbitrc, abscondbrtarget, | |
| /* gBCAat */ | |
| u5imm, atimm, crbitrc, abscondbrtarget, | |
| /* gBCCTR */ | |
| u5imm, crbitrc, i32imm, | |
| /* gBCCTRL */ | |
| u5imm, crbitrc, i32imm, | |
| /* gBCL */ | |
| u5imm, crbitrc, condbrtarget, | |
| /* gBCLA */ | |
| u5imm, crbitrc, abscondbrtarget, | |
| /* gBCLAat */ | |
| u5imm, atimm, crbitrc, abscondbrtarget, | |
| /* gBCLR */ | |
| u5imm, crbitrc, i32imm, | |
| /* gBCLRL */ | |
| u5imm, crbitrc, i32imm, | |
| /* gBCLat */ | |
| u5imm, atimm, crbitrc, condbrtarget, | |
| /* gBCat */ | |
| u5imm, atimm, crbitrc, condbrtarget, | |
| }; | |
| return OpcodeOperandTypes[Offsets[Opcode] + OpIdx]; | |
| } | |
| } // end namespace PPC | |
| } // end namespace llvm | |
| #endif // GET_INSTRINFO_OPERAND_TYPE | |
| #ifdef GET_INSTRINFO_MEM_OPERAND_SIZE | |
| #undef GET_INSTRINFO_MEM_OPERAND_SIZE | |
| namespace llvm { | |
| namespace PPC { | |
| LLVM_READONLY | |
| static int getMemOperandSize(int OpType) { | |
| switch (OpType) { | |
| default: return 0; | |
| } | |
| } | |
| } // end namespace PPC | |
| } // end namespace llvm | |
| #endif // GET_INSTRINFO_MEM_OPERAND_SIZE | |
| #ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP | |
| #undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP | |
| namespace llvm { | |
| namespace PPC { | |
| LLVM_READONLY static unsigned | |
| getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) { | |
| return LogicalOpIdx; | |
| } | |
| LLVM_READONLY static inline unsigned | |
| getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) { | |
| auto S = 0U; | |
| for (auto i = 0U; i < LogicalOpIdx; ++i) | |
| S += getLogicalOperandSize(Opcode, i); | |
| return S; | |
| } | |
| } // end namespace PPC | |
| } // end namespace llvm | |
| #endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP | |
| #ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP | |
| #undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP | |
| namespace llvm { | |
| namespace PPC { | |
| LLVM_READONLY static int | |
| getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) { | |
| return -1; | |
| } | |
| } // end namespace PPC | |
| } // end namespace llvm | |
| #endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP | |
| #ifdef GET_INSTRINFO_MC_HELPER_DECLS | |
| #undef GET_INSTRINFO_MC_HELPER_DECLS | |
| namespace llvm { | |
| class MCInst; | |
| class FeatureBitset; | |
| namespace PPC_MC { | |
| void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features); | |
| } // end namespace PPC_MC | |
| } // end namespace llvm | |
| #endif // GET_INSTRINFO_MC_HELPER_DECLS | |
| #ifdef GET_INSTRINFO_MC_HELPERS | |
| #undef GET_INSTRINFO_MC_HELPERS | |
| namespace llvm { | |
| namespace PPC_MC { | |
| } // end namespace PPC_MC | |
| } // end namespace llvm | |
| #endif // GET_GENISTRINFO_MC_HELPERS | |
| #ifdef ENABLE_INSTR_PREDICATE_VERIFIER | |
| #undef ENABLE_INSTR_PREDICATE_VERIFIER | |
| #include <sstream> | |
| namespace llvm { | |
| namespace PPC_MC { | |
| // Bits for subtarget features that participate in instruction matching. | |
| enum SubtargetFeatureBits : uint8_t { | |
| Feature_ModernAsBit = 0, | |
| }; | |
| #ifndef NDEBUG | |
| static const char *SubtargetFeatureNames[] = { | |
| "Feature_ModernAs", | |
| nullptr | |
| }; | |
| #endif // NDEBUG | |
| FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) { | |
| FeatureBitset Features; | |
| if (!FB[PPC::AIXOS] || FB[PPC::FeatureModernAIXAs]) | |
| Features.set(Feature_ModernAsBit); | |
| return Features; | |
| } | |
| #ifndef NDEBUG | |
| // Feature bitsets. | |
| enum : uint8_t { | |
| CEFBS_None, | |
| }; | |
| static constexpr FeatureBitset FeatureBitsets[] = { | |
| {}, // CEFBS_None | |
| }; | |
| #endif // NDEBUG | |
| void verifyInstructionPredicates( | |
| unsigned Opcode, const FeatureBitset &Features) { | |
| #ifndef NDEBUG | |
| static uint8_t RequiredFeaturesRefs[] = { | |
| CEFBS_None, // PHI = 0 | |
| CEFBS_None, // INLINEASM = 1 | |
| CEFBS_None, // INLINEASM_BR = 2 | |
| CEFBS_None, // CFI_INSTRUCTION = 3 | |
| CEFBS_None, // EH_LABEL = 4 | |
| CEFBS_None, // GC_LABEL = 5 | |
| CEFBS_None, // ANNOTATION_LABEL = 6 | |
| CEFBS_None, // KILL = 7 | |
| CEFBS_None, // EXTRACT_SUBREG = 8 | |
| CEFBS_None, // INSERT_SUBREG = 9 | |
| CEFBS_None, // IMPLICIT_DEF = 10 | |
| CEFBS_None, // SUBREG_TO_REG = 11 | |
| CEFBS_None, // COPY_TO_REGCLASS = 12 | |
| CEFBS_None, // DBG_VALUE = 13 | |
| CEFBS_None, // DBG_VALUE_LIST = 14 | |
| CEFBS_None, // DBG_INSTR_REF = 15 | |
| CEFBS_None, // DBG_PHI = 16 | |
| CEFBS_None, // DBG_LABEL = 17 | |
| CEFBS_None, // REG_SEQUENCE = 18 | |
| CEFBS_None, // COPY = 19 | |
| CEFBS_None, // BUNDLE = 20 | |
| CEFBS_None, // LIFETIME_START = 21 | |
| CEFBS_None, // LIFETIME_END = 22 | |
| CEFBS_None, // PSEUDO_PROBE = 23 | |
| CEFBS_None, // ARITH_FENCE = 24 | |
| CEFBS_None, // STACKMAP = 25 | |
| CEFBS_None, // FENTRY_CALL = 26 | |
| CEFBS_None, // PATCHPOINT = 27 | |
| CEFBS_None, // LOAD_STACK_GUARD = 28 | |
| CEFBS_None, // PREALLOCATED_SETUP = 29 | |
| CEFBS_None, // PREALLOCATED_ARG = 30 | |
| CEFBS_None, // STATEPOINT = 31 | |
| CEFBS_None, // LOCAL_ESCAPE = 32 | |
| CEFBS_None, // FAULTING_OP = 33 | |
| CEFBS_None, // PATCHABLE_OP = 34 | |
| CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35 | |
| CEFBS_None, // PATCHABLE_RET = 36 | |
| CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37 | |
| CEFBS_None, // PATCHABLE_TAIL_CALL = 38 | |
| CEFBS_None, // PATCHABLE_EVENT_CALL = 39 | |
| CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40 | |
| CEFBS_None, // ICALL_BRANCH_FUNNEL = 41 | |
| CEFBS_None, // MEMBARRIER = 42 | |
| CEFBS_None, // G_ASSERT_SEXT = 43 | |
| CEFBS_None, // G_ASSERT_ZEXT = 44 | |
| CEFBS_None, // G_ASSERT_ALIGN = 45 | |
| CEFBS_None, // G_ADD = 46 | |
| CEFBS_None, // G_SUB = 47 | |
| CEFBS_None, // G_MUL = 48 | |
| CEFBS_None, // G_SDIV = 49 | |
| CEFBS_None, // G_UDIV = 50 | |
| CEFBS_None, // G_SREM = 51 | |
| CEFBS_None, // G_UREM = 52 | |
| CEFBS_None, // G_SDIVREM = 53 | |
| CEFBS_None, // G_UDIVREM = 54 | |
| CEFBS_None, // G_AND = 55 | |
| CEFBS_None, // G_OR = 56 | |
| CEFBS_None, // G_XOR = 57 | |
| CEFBS_None, // G_IMPLICIT_DEF = 58 | |
| CEFBS_None, // G_PHI = 59 | |
| CEFBS_None, // G_FRAME_INDEX = 60 | |
| CEFBS_None, // G_GLOBAL_VALUE = 61 | |
| CEFBS_None, // G_EXTRACT = 62 | |
| CEFBS_None, // G_UNMERGE_VALUES = 63 | |
| CEFBS_None, // G_INSERT = 64 | |
| CEFBS_None, // G_MERGE_VALUES = 65 | |
| CEFBS_None, // G_BUILD_VECTOR = 66 | |
| CEFBS_None, // G_BUILD_VECTOR_TRUNC = 67 | |
| CEFBS_None, // G_CONCAT_VECTORS = 68 | |
| CEFBS_None, // G_PTRTOINT = 69 | |
| CEFBS_None, // G_INTTOPTR = 70 | |
| CEFBS_None, // G_BITCAST = 71 | |
| CEFBS_None, // G_FREEZE = 72 | |
| CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 73 | |
| CEFBS_None, // G_INTRINSIC_TRUNC = 74 | |
| CEFBS_None, // G_INTRINSIC_ROUND = 75 | |
| CEFBS_None, // G_INTRINSIC_LRINT = 76 | |
| CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 77 | |
| CEFBS_None, // G_READCYCLECOUNTER = 78 | |
| CEFBS_None, // G_LOAD = 79 | |
| CEFBS_None, // G_SEXTLOAD = 80 | |
| CEFBS_None, // G_ZEXTLOAD = 81 | |
| CEFBS_None, // G_INDEXED_LOAD = 82 | |
| CEFBS_None, // G_INDEXED_SEXTLOAD = 83 | |
| CEFBS_None, // G_INDEXED_ZEXTLOAD = 84 | |
| CEFBS_None, // G_STORE = 85 | |
| CEFBS_None, // G_INDEXED_STORE = 86 | |
| CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 87 | |
| CEFBS_None, // G_ATOMIC_CMPXCHG = 88 | |
| CEFBS_None, // G_ATOMICRMW_XCHG = 89 | |
| CEFBS_None, // G_ATOMICRMW_ADD = 90 | |
| CEFBS_None, // G_ATOMICRMW_SUB = 91 | |
| CEFBS_None, // G_ATOMICRMW_AND = 92 | |
| CEFBS_None, // G_ATOMICRMW_NAND = 93 | |
| CEFBS_None, // G_ATOMICRMW_OR = 94 | |
| CEFBS_None, // G_ATOMICRMW_XOR = 95 | |
| CEFBS_None, // G_ATOMICRMW_MAX = 96 | |
| CEFBS_None, // G_ATOMICRMW_MIN = 97 | |
| CEFBS_None, // G_ATOMICRMW_UMAX = 98 | |
| CEFBS_None, // G_ATOMICRMW_UMIN = 99 | |
| CEFBS_None, // G_ATOMICRMW_FADD = 100 | |
| CEFBS_None, // G_ATOMICRMW_FSUB = 101 | |
| CEFBS_None, // G_ATOMICRMW_FMAX = 102 | |
| CEFBS_None, // G_ATOMICRMW_FMIN = 103 | |
| CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 104 | |
| CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 105 | |
| CEFBS_None, // G_FENCE = 106 | |
| CEFBS_None, // G_BRCOND = 107 | |
| CEFBS_None, // G_BRINDIRECT = 108 | |
| CEFBS_None, // G_INVOKE_REGION_START = 109 | |
| CEFBS_None, // G_INTRINSIC = 110 | |
| CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 111 | |
| CEFBS_None, // G_ANYEXT = 112 | |
| CEFBS_None, // G_TRUNC = 113 | |
| CEFBS_None, // G_CONSTANT = 114 | |
| CEFBS_None, // G_FCONSTANT = 115 | |
| CEFBS_None, // G_VASTART = 116 | |
| CEFBS_None, // G_VAARG = 117 | |
| CEFBS_None, // G_SEXT = 118 | |
| CEFBS_None, // G_SEXT_INREG = 119 | |
| CEFBS_None, // G_ZEXT = 120 | |
| CEFBS_None, // G_SHL = 121 | |
| CEFBS_None, // G_LSHR = 122 | |
| CEFBS_None, // G_ASHR = 123 | |
| CEFBS_None, // G_FSHL = 124 | |
| CEFBS_None, // G_FSHR = 125 | |
| CEFBS_None, // G_ROTR = 126 | |
| CEFBS_None, // G_ROTL = 127 | |
| CEFBS_None, // G_ICMP = 128 | |
| CEFBS_None, // G_FCMP = 129 | |
| CEFBS_None, // G_SELECT = 130 | |
| CEFBS_None, // G_UADDO = 131 | |
| CEFBS_None, // G_UADDE = 132 | |
| CEFBS_None, // G_USUBO = 133 | |
| CEFBS_None, // G_USUBE = 134 | |
| CEFBS_None, // G_SADDO = 135 | |
| CEFBS_None, // G_SADDE = 136 | |
| CEFBS_None, // G_SSUBO = 137 | |
| CEFBS_None, // G_SSUBE = 138 | |
| CEFBS_None, // G_UMULO = 139 | |
| CEFBS_None, // G_SMULO = 140 | |
| CEFBS_None, // G_UMULH = 141 | |
| CEFBS_None, // G_SMULH = 142 | |
| CEFBS_None, // G_UADDSAT = 143 | |
| CEFBS_None, // G_SADDSAT = 144 | |
| CEFBS_None, // G_USUBSAT = 145 | |
| CEFBS_None, // G_SSUBSAT = 146 | |
| CEFBS_None, // G_USHLSAT = 147 | |
| CEFBS_None, // G_SSHLSAT = 148 | |
| CEFBS_None, // G_SMULFIX = 149 | |
| CEFBS_None, // G_UMULFIX = 150 | |
| CEFBS_None, // G_SMULFIXSAT = 151 | |
| CEFBS_None, // G_UMULFIXSAT = 152 | |
| CEFBS_None, // G_SDIVFIX = 153 | |
| CEFBS_None, // G_UDIVFIX = 154 | |
| CEFBS_None, // G_SDIVFIXSAT = 155 | |
| CEFBS_None, // G_UDIVFIXSAT = 156 | |
| CEFBS_None, // G_FADD = 157 | |
| CEFBS_None, // G_FSUB = 158 | |
| CEFBS_None, // G_FMUL = 159 | |
| CEFBS_None, // G_FMA = 160 | |
| CEFBS_None, // G_FMAD = 161 | |
| CEFBS_None, // G_FDIV = 162 | |
| CEFBS_None, // G_FREM = 163 | |
| CEFBS_None, // G_FPOW = 164 | |
| CEFBS_None, // G_FPOWI = 165 | |
| CEFBS_None, // G_FEXP = 166 | |
| CEFBS_None, // G_FEXP2 = 167 | |
| CEFBS_None, // G_FLOG = 168 | |
| CEFBS_None, // G_FLOG2 = 169 | |
| CEFBS_None, // G_FLOG10 = 170 | |
| CEFBS_None, // G_FNEG = 171 | |
| CEFBS_None, // G_FPEXT = 172 | |
| CEFBS_None, // G_FPTRUNC = 173 | |
| CEFBS_None, // G_FPTOSI = 174 | |
| CEFBS_None, // G_FPTOUI = 175 | |
| CEFBS_None, // G_SITOFP = 176 | |
| CEFBS_None, // G_UITOFP = 177 | |
| CEFBS_None, // G_FABS = 178 | |
| CEFBS_None, // G_FCOPYSIGN = 179 | |
| CEFBS_None, // G_IS_FPCLASS = 180 | |
| CEFBS_None, // G_FCANONICALIZE = 181 | |
| CEFBS_None, // G_FMINNUM = 182 | |
| CEFBS_None, // G_FMAXNUM = 183 | |
| CEFBS_None, // G_FMINNUM_IEEE = 184 | |
| CEFBS_None, // G_FMAXNUM_IEEE = 185 | |
| CEFBS_None, // G_FMINIMUM = 186 | |
| CEFBS_None, // G_FMAXIMUM = 187 | |
| CEFBS_None, // G_PTR_ADD = 188 | |
| CEFBS_None, // G_PTRMASK = 189 | |
| CEFBS_None, // G_SMIN = 190 | |
| CEFBS_None, // G_SMAX = 191 | |
| CEFBS_None, // G_UMIN = 192 | |
| CEFBS_None, // G_UMAX = 193 | |
| CEFBS_None, // G_ABS = 194 | |
| CEFBS_None, // G_LROUND = 195 | |
| CEFBS_None, // G_LLROUND = 196 | |
| CEFBS_None, // G_BR = 197 | |
| CEFBS_None, // G_BRJT = 198 | |
| CEFBS_None, // G_INSERT_VECTOR_ELT = 199 | |
| CEFBS_None, // G_EXTRACT_VECTOR_ELT = 200 | |
| CEFBS_None, // G_SHUFFLE_VECTOR = 201 | |
| CEFBS_None, // G_CTTZ = 202 | |
| CEFBS_None, // G_CTTZ_ZERO_UNDEF = 203 | |
| CEFBS_None, // G_CTLZ = 204 | |
| CEFBS_None, // G_CTLZ_ZERO_UNDEF = 205 | |
| CEFBS_None, // G_CTPOP = 206 | |
| CEFBS_None, // G_BSWAP = 207 | |
| CEFBS_None, // G_BITREVERSE = 208 | |
| CEFBS_None, // G_FCEIL = 209 | |
| CEFBS_None, // G_FCOS = 210 | |
| CEFBS_None, // G_FSIN = 211 | |
| CEFBS_None, // G_FSQRT = 212 | |
| CEFBS_None, // G_FFLOOR = 213 | |
| CEFBS_None, // G_FRINT = 214 | |
| CEFBS_None, // G_FNEARBYINT = 215 | |
| CEFBS_None, // G_ADDRSPACE_CAST = 216 | |
| CEFBS_None, // G_BLOCK_ADDR = 217 | |
| CEFBS_None, // G_JUMP_TABLE = 218 | |
| CEFBS_None, // G_DYN_STACKALLOC = 219 | |
| CEFBS_None, // G_STRICT_FADD = 220 | |
| CEFBS_None, // G_STRICT_FSUB = 221 | |
| CEFBS_None, // G_STRICT_FMUL = 222 | |
| CEFBS_None, // G_STRICT_FDIV = 223 | |
| CEFBS_None, // G_STRICT_FREM = 224 | |
| CEFBS_None, // G_STRICT_FMA = 225 | |
| CEFBS_None, // G_STRICT_FSQRT = 226 | |
| CEFBS_None, // G_READ_REGISTER = 227 | |
| CEFBS_None, // G_WRITE_REGISTER = 228 | |
| CEFBS_None, // G_MEMCPY = 229 | |
| CEFBS_None, // G_MEMCPY_INLINE = 230 | |
| CEFBS_None, // G_MEMMOVE = 231 | |
| CEFBS_None, // G_MEMSET = 232 | |
| CEFBS_None, // G_BZERO = 233 | |
| CEFBS_None, // G_VECREDUCE_SEQ_FADD = 234 | |
| CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 235 | |
| CEFBS_None, // G_VECREDUCE_FADD = 236 | |
| CEFBS_None, // G_VECREDUCE_FMUL = 237 | |
| CEFBS_None, // G_VECREDUCE_FMAX = 238 | |
| CEFBS_None, // G_VECREDUCE_FMIN = 239 | |
| CEFBS_None, // G_VECREDUCE_ADD = 240 | |
| CEFBS_None, // G_VECREDUCE_MUL = 241 | |
| CEFBS_None, // G_VECREDUCE_AND = 242 | |
| CEFBS_None, // G_VECREDUCE_OR = 243 | |
| CEFBS_None, // G_VECREDUCE_XOR = 244 | |
| CEFBS_None, // G_VECREDUCE_SMAX = 245 | |
| CEFBS_None, // G_VECREDUCE_SMIN = 246 | |
| CEFBS_None, // G_VECREDUCE_UMAX = 247 | |
| CEFBS_None, // G_VECREDUCE_UMIN = 248 | |
| CEFBS_None, // G_SBFX = 249 | |
| CEFBS_None, // G_UBFX = 250 | |
| CEFBS_None, // ATOMIC_CMP_SWAP_I128 = 251 | |
| CEFBS_None, // ATOMIC_LOAD_ADD_I128 = 252 | |
| CEFBS_None, // ATOMIC_LOAD_AND_I128 = 253 | |
| CEFBS_None, // ATOMIC_LOAD_NAND_I128 = 254 | |
| CEFBS_None, // ATOMIC_LOAD_OR_I128 = 255 | |
| CEFBS_None, // ATOMIC_LOAD_SUB_I128 = 256 | |
| CEFBS_None, // ATOMIC_LOAD_XOR_I128 = 257 | |
| CEFBS_None, // ATOMIC_SWAP_I128 = 258 | |
| CEFBS_None, // BUILD_QUADWORD = 259 | |
| CEFBS_None, // BUILD_UACC = 260 | |
| CEFBS_None, // CFENCE8 = 261 | |
| CEFBS_None, // CLRLSLDI = 262 | |
| CEFBS_None, // CLRLSLDI_rec = 263 | |
| CEFBS_None, // CLRLSLWI = 264 | |
| CEFBS_None, // CLRLSLWI_rec = 265 | |
| CEFBS_None, // CLRRDI = 266 | |
| CEFBS_None, // CLRRDI_rec = 267 | |
| CEFBS_None, // CLRRWI = 268 | |
| CEFBS_None, // CLRRWI_rec = 269 | |
| CEFBS_None, // DCBFL = 270 | |
| CEFBS_None, // DCBFLP = 271 | |
| CEFBS_None, // DCBFPS = 272 | |
| CEFBS_None, // DCBFx = 273 | |
| CEFBS_None, // DCBSTPS = 274 | |
| CEFBS_None, // DCBTCT = 275 | |
| CEFBS_None, // DCBTDS = 276 | |
| CEFBS_None, // DCBTSTCT = 277 | |
| CEFBS_None, // DCBTSTDS = 278 | |
| CEFBS_None, // DCBTSTT = 279 | |
| CEFBS_None, // DCBTSTx = 280 | |
| CEFBS_None, // DCBTT = 281 | |
| CEFBS_None, // DCBTx = 282 | |
| CEFBS_None, // DFLOADf32 = 283 | |
| CEFBS_None, // DFLOADf64 = 284 | |
| CEFBS_None, // DFSTOREf32 = 285 | |
| CEFBS_None, // DFSTOREf64 = 286 | |
| CEFBS_None, // EXTLDI = 287 | |
| CEFBS_None, // EXTLDI_rec = 288 | |
| CEFBS_None, // EXTLWI = 289 | |
| CEFBS_None, // EXTLWI_rec = 290 | |
| CEFBS_None, // EXTRDI = 291 | |
| CEFBS_None, // EXTRDI_rec = 292 | |
| CEFBS_None, // EXTRWI = 293 | |
| CEFBS_None, // EXTRWI_rec = 294 | |
| CEFBS_None, // INSLWI = 295 | |
| CEFBS_None, // INSLWI_rec = 296 | |
| CEFBS_None, // INSRDI = 297 | |
| CEFBS_None, // INSRDI_rec = 298 | |
| CEFBS_None, // INSRWI = 299 | |
| CEFBS_None, // INSRWI_rec = 300 | |
| CEFBS_None, // KILL_PAIR = 301 | |
| CEFBS_None, // LAx = 302 | |
| CEFBS_None, // LIWAX = 303 | |
| CEFBS_None, // LIWZX = 304 | |
| CEFBS_None, // RLWIMIbm = 305 | |
| CEFBS_None, // RLWIMIbm_rec = 306 | |
| CEFBS_None, // RLWINMbm = 307 | |
| CEFBS_None, // RLWINMbm_rec = 308 | |
| CEFBS_None, // RLWNMbm = 309 | |
| CEFBS_None, // RLWNMbm_rec = 310 | |
| CEFBS_None, // ROTRDI = 311 | |
| CEFBS_None, // ROTRDI_rec = 312 | |
| CEFBS_None, // ROTRWI = 313 | |
| CEFBS_None, // ROTRWI_rec = 314 | |
| CEFBS_None, // SLDI = 315 | |
| CEFBS_None, // SLDI_rec = 316 | |
| CEFBS_None, // SLWI = 317 | |
| CEFBS_None, // SLWI_rec = 318 | |
| CEFBS_None, // SPILLTOVSR_LD = 319 | |
| CEFBS_None, // SPILLTOVSR_LDX = 320 | |
| CEFBS_None, // SPILLTOVSR_ST = 321 | |
| CEFBS_None, // SPILLTOVSR_STX = 322 | |
| CEFBS_None, // SRDI = 323 | |
| CEFBS_None, // SRDI_rec = 324 | |
| CEFBS_None, // SRWI = 325 | |
| CEFBS_None, // SRWI_rec = 326 | |
| CEFBS_None, // STIWX = 327 | |
| CEFBS_None, // SUBI = 328 | |
| CEFBS_None, // SUBIC = 329 | |
| CEFBS_None, // SUBIC_rec = 330 | |
| CEFBS_None, // SUBIS = 331 | |
| CEFBS_None, // SUBPCIS = 332 | |
| CEFBS_None, // XFLOADf32 = 333 | |
| CEFBS_None, // XFLOADf64 = 334 | |
| CEFBS_None, // XFSTOREf32 = 335 | |
| CEFBS_None, // XFSTOREf64 = 336 | |
| CEFBS_None, // ADD4 = 337 | |
| CEFBS_None, // ADD4O = 338 | |
| CEFBS_None, // ADD4O_rec = 339 | |
| CEFBS_None, // ADD4TLS = 340 | |
| CEFBS_None, // ADD4_rec = 341 | |
| CEFBS_None, // ADD8 = 342 | |
| CEFBS_None, // ADD8O = 343 | |
| CEFBS_None, // ADD8O_rec = 344 | |
| CEFBS_None, // ADD8TLS = 345 | |
| CEFBS_None, // ADD8TLS_ = 346 | |
| CEFBS_None, // ADD8_rec = 347 | |
| CEFBS_None, // ADDC = 348 | |
| CEFBS_None, // ADDC8 = 349 | |
| CEFBS_None, // ADDC8O = 350 | |
| CEFBS_None, // ADDC8O_rec = 351 | |
| CEFBS_None, // ADDC8_rec = 352 | |
| CEFBS_None, // ADDCO = 353 | |
| CEFBS_None, // ADDCO_rec = 354 | |
| CEFBS_None, // ADDC_rec = 355 | |
| CEFBS_None, // ADDE = 356 | |
| CEFBS_None, // ADDE8 = 357 | |
| CEFBS_None, // ADDE8O = 358 | |
| CEFBS_None, // ADDE8O_rec = 359 | |
| CEFBS_None, // ADDE8_rec = 360 | |
| CEFBS_None, // ADDEO = 361 | |
| CEFBS_None, // ADDEO_rec = 362 | |
| CEFBS_None, // ADDEX = 363 | |
| CEFBS_None, // ADDEX8 = 364 | |
| CEFBS_None, // ADDE_rec = 365 | |
| CEFBS_None, // ADDI = 366 | |
| CEFBS_None, // ADDI8 = 367 | |
| CEFBS_None, // ADDIC = 368 | |
| CEFBS_None, // ADDIC8 = 369 | |
| CEFBS_None, // ADDIC_rec = 370 | |
| CEFBS_None, // ADDIS = 371 | |
| CEFBS_None, // ADDIS8 = 372 | |
| CEFBS_None, // ADDISdtprelHA = 373 | |
| CEFBS_None, // ADDISdtprelHA32 = 374 | |
| CEFBS_None, // ADDISgotTprelHA = 375 | |
| CEFBS_None, // ADDIStlsgdHA = 376 | |
| CEFBS_None, // ADDIStlsldHA = 377 | |
| CEFBS_None, // ADDIStocHA = 378 | |
| CEFBS_None, // ADDIStocHA8 = 379 | |
| CEFBS_None, // ADDIdtprelL = 380 | |
| CEFBS_None, // ADDIdtprelL32 = 381 | |
| CEFBS_None, // ADDItlsgdL = 382 | |
| CEFBS_None, // ADDItlsgdL32 = 383 | |
| CEFBS_None, // ADDItlsgdLADDR = 384 | |
| CEFBS_None, // ADDItlsgdLADDR32 = 385 | |
| CEFBS_None, // ADDItlsldL = 386 | |
| CEFBS_None, // ADDItlsldL32 = 387 | |
| CEFBS_None, // ADDItlsldLADDR = 388 | |
| CEFBS_None, // ADDItlsldLADDR32 = 389 | |
| CEFBS_None, // ADDItoc = 390 | |
| CEFBS_None, // ADDItoc8 = 391 | |
| CEFBS_None, // ADDItocL = 392 | |
| CEFBS_None, // ADDME = 393 | |
| CEFBS_None, // ADDME8 = 394 | |
| CEFBS_None, // ADDME8O = 395 | |
| CEFBS_None, // ADDME8O_rec = 396 | |
| CEFBS_None, // ADDME8_rec = 397 | |
| CEFBS_None, // ADDMEO = 398 | |
| CEFBS_None, // ADDMEO_rec = 399 | |
| CEFBS_None, // ADDME_rec = 400 | |
| CEFBS_None, // ADDPCIS = 401 | |
| CEFBS_None, // ADDZE = 402 | |
| CEFBS_None, // ADDZE8 = 403 | |
| CEFBS_None, // ADDZE8O = 404 | |
| CEFBS_None, // ADDZE8O_rec = 405 | |
| CEFBS_None, // ADDZE8_rec = 406 | |
| CEFBS_None, // ADDZEO = 407 | |
| CEFBS_None, // ADDZEO_rec = 408 | |
| CEFBS_None, // ADDZE_rec = 409 | |
| CEFBS_None, // ADJCALLSTACKDOWN = 410 | |
| CEFBS_None, // ADJCALLSTACKUP = 411 | |
| CEFBS_None, // AND = 412 | |
| CEFBS_None, // AND8 = 413 | |
| CEFBS_None, // AND8_rec = 414 | |
| CEFBS_None, // ANDC = 415 | |
| CEFBS_None, // ANDC8 = 416 | |
| CEFBS_None, // ANDC8_rec = 417 | |
| CEFBS_None, // ANDC_rec = 418 | |
| CEFBS_None, // ANDI8_rec = 419 | |
| CEFBS_None, // ANDIS8_rec = 420 | |
| CEFBS_None, // ANDIS_rec = 421 | |
| CEFBS_None, // ANDI_rec = 422 | |
| CEFBS_None, // ANDI_rec_1_EQ_BIT = 423 | |
| CEFBS_None, // ANDI_rec_1_EQ_BIT8 = 424 | |
| CEFBS_None, // ANDI_rec_1_GT_BIT = 425 | |
| CEFBS_None, // ANDI_rec_1_GT_BIT8 = 426 | |
| CEFBS_None, // AND_rec = 427 | |
| CEFBS_None, // ATOMIC_CMP_SWAP_I16 = 428 | |
| CEFBS_None, // ATOMIC_CMP_SWAP_I32 = 429 | |
| CEFBS_None, // ATOMIC_CMP_SWAP_I64 = 430 | |
| CEFBS_None, // ATOMIC_CMP_SWAP_I8 = 431 | |
| CEFBS_None, // ATOMIC_LOAD_ADD_I16 = 432 | |
| CEFBS_None, // ATOMIC_LOAD_ADD_I32 = 433 | |
| CEFBS_None, // ATOMIC_LOAD_ADD_I64 = 434 | |
| CEFBS_None, // ATOMIC_LOAD_ADD_I8 = 435 | |
| CEFBS_None, // ATOMIC_LOAD_AND_I16 = 436 | |
| CEFBS_None, // ATOMIC_LOAD_AND_I32 = 437 | |
| CEFBS_None, // ATOMIC_LOAD_AND_I64 = 438 | |
| CEFBS_None, // ATOMIC_LOAD_AND_I8 = 439 | |
| CEFBS_None, // ATOMIC_LOAD_MAX_I16 = 440 | |
| CEFBS_None, // ATOMIC_LOAD_MAX_I32 = 441 | |
| CEFBS_None, // ATOMIC_LOAD_MAX_I64 = 442 | |
| CEFBS_None, // ATOMIC_LOAD_MAX_I8 = 443 | |
| CEFBS_None, // ATOMIC_LOAD_MIN_I16 = 444 | |
| CEFBS_None, // ATOMIC_LOAD_MIN_I32 = 445 | |
| CEFBS_None, // ATOMIC_LOAD_MIN_I64 = 446 | |
| CEFBS_None, // ATOMIC_LOAD_MIN_I8 = 447 | |
| CEFBS_None, // ATOMIC_LOAD_NAND_I16 = 448 | |
| CEFBS_None, // ATOMIC_LOAD_NAND_I32 = 449 | |
| CEFBS_None, // ATOMIC_LOAD_NAND_I64 = 450 | |
| CEFBS_None, // ATOMIC_LOAD_NAND_I8 = 451 | |
| CEFBS_None, // ATOMIC_LOAD_OR_I16 = 452 | |
| CEFBS_None, // ATOMIC_LOAD_OR_I32 = 453 | |
| CEFBS_None, // ATOMIC_LOAD_OR_I64 = 454 | |
| CEFBS_None, // ATOMIC_LOAD_OR_I8 = 455 | |
| CEFBS_None, // ATOMIC_LOAD_SUB_I16 = 456 | |
| CEFBS_None, // ATOMIC_LOAD_SUB_I32 = 457 | |
| CEFBS_None, // ATOMIC_LOAD_SUB_I64 = 458 | |
| CEFBS_None, // ATOMIC_LOAD_SUB_I8 = 459 | |
| CEFBS_None, // ATOMIC_LOAD_UMAX_I16 = 460 | |
| CEFBS_None, // ATOMIC_LOAD_UMAX_I32 = 461 | |
| CEFBS_None, // ATOMIC_LOAD_UMAX_I64 = 462 | |
| CEFBS_None, // ATOMIC_LOAD_UMAX_I8 = 463 | |
| CEFBS_None, // ATOMIC_LOAD_UMIN_I16 = 464 | |
| CEFBS_None, // ATOMIC_LOAD_UMIN_I32 = 465 | |
| CEFBS_None, // ATOMIC_LOAD_UMIN_I64 = 466 | |
| CEFBS_None, // ATOMIC_LOAD_UMIN_I8 = 467 | |
| CEFBS_None, // ATOMIC_LOAD_XOR_I16 = 468 | |
| CEFBS_None, // ATOMIC_LOAD_XOR_I32 = 469 | |
| CEFBS_None, // ATOMIC_LOAD_XOR_I64 = 470 | |
| CEFBS_None, // ATOMIC_LOAD_XOR_I8 = 471 | |
| CEFBS_None, // ATOMIC_SWAP_I16 = 472 | |
| CEFBS_None, // ATOMIC_SWAP_I32 = 473 | |
| CEFBS_None, // ATOMIC_SWAP_I64 = 474 | |
| CEFBS_None, // ATOMIC_SWAP_I8 = 475 | |
| CEFBS_None, // ATTN = 476 | |
| CEFBS_None, // B = 477 | |
| CEFBS_None, // BA = 478 | |
| CEFBS_None, // BC = 479 | |
| CEFBS_None, // BCC = 480 | |
| CEFBS_None, // BCCA = 481 | |
| CEFBS_None, // BCCCTR = 482 | |
| CEFBS_None, // BCCCTR8 = 483 | |
| CEFBS_None, // BCCCTRL = 484 | |
| CEFBS_None, // BCCCTRL8 = 485 | |
| CEFBS_None, // BCCL = 486 | |
| CEFBS_None, // BCCLA = 487 | |
| CEFBS_None, // BCCLR = 488 | |
| CEFBS_None, // BCCLRL = 489 | |
| CEFBS_None, // BCCTR = 490 | |
| CEFBS_None, // BCCTR8 = 491 | |
| CEFBS_None, // BCCTR8n = 492 | |
| CEFBS_None, // BCCTRL = 493 | |
| CEFBS_None, // BCCTRL8 = 494 | |
| CEFBS_None, // BCCTRL8n = 495 | |
| CEFBS_None, // BCCTRLn = 496 | |
| CEFBS_None, // BCCTRn = 497 | |
| CEFBS_None, // BCDADD_rec = 498 | |
| CEFBS_None, // BCDCFN_rec = 499 | |
| CEFBS_None, // BCDCFSQ_rec = 500 | |
| CEFBS_None, // BCDCFZ_rec = 501 | |
| CEFBS_None, // BCDCPSGN_rec = 502 | |
| CEFBS_None, // BCDCTN_rec = 503 | |
| CEFBS_None, // BCDCTSQ_rec = 504 | |
| CEFBS_None, // BCDCTZ_rec = 505 | |
| CEFBS_None, // BCDSETSGN_rec = 506 | |
| CEFBS_None, // BCDSR_rec = 507 | |
| CEFBS_None, // BCDSUB_rec = 508 | |
| CEFBS_None, // BCDS_rec = 509 | |
| CEFBS_None, // BCDTRUNC_rec = 510 | |
| CEFBS_None, // BCDUS_rec = 511 | |
| CEFBS_None, // BCDUTRUNC_rec = 512 | |
| CEFBS_None, // BCL = 513 | |
| CEFBS_None, // BCLR = 514 | |
| CEFBS_None, // BCLRL = 515 | |
| CEFBS_None, // BCLRLn = 516 | |
| CEFBS_None, // BCLRn = 517 | |
| CEFBS_None, // BCLalways = 518 | |
| CEFBS_None, // BCLn = 519 | |
| CEFBS_None, // BCTR = 520 | |
| CEFBS_None, // BCTR8 = 521 | |
| CEFBS_None, // BCTRL = 522 | |
| CEFBS_None, // BCTRL8 = 523 | |
| CEFBS_None, // BCTRL8_LDinto_toc = 524 | |
| CEFBS_None, // BCTRL8_LDinto_toc_RM = 525 | |
| CEFBS_None, // BCTRL8_RM = 526 | |
| CEFBS_None, // BCTRL_LWZinto_toc = 527 | |
| CEFBS_None, // BCTRL_LWZinto_toc_RM = 528 | |
| CEFBS_None, // BCTRL_RM = 529 | |
| CEFBS_None, // BCn = 530 | |
| CEFBS_None, // BDNZ = 531 | |
| CEFBS_None, // BDNZ8 = 532 | |
| CEFBS_None, // BDNZA = 533 | |
| CEFBS_None, // BDNZAm = 534 | |
| CEFBS_None, // BDNZAp = 535 | |
| CEFBS_None, // BDNZL = 536 | |
| CEFBS_None, // BDNZLA = 537 | |
| CEFBS_None, // BDNZLAm = 538 | |
| CEFBS_None, // BDNZLAp = 539 | |
| CEFBS_None, // BDNZLR = 540 | |
| CEFBS_None, // BDNZLR8 = 541 | |
| CEFBS_None, // BDNZLRL = 542 | |
| CEFBS_None, // BDNZLRLm = 543 | |
| CEFBS_None, // BDNZLRLp = 544 | |
| CEFBS_None, // BDNZLRm = 545 | |
| CEFBS_None, // BDNZLRp = 546 | |
| CEFBS_None, // BDNZLm = 547 | |
| CEFBS_None, // BDNZLp = 548 | |
| CEFBS_None, // BDNZm = 549 | |
| CEFBS_None, // BDNZp = 550 | |
| CEFBS_None, // BDZ = 551 | |
| CEFBS_None, // BDZ8 = 552 | |
| CEFBS_None, // BDZA = 553 | |
| CEFBS_None, // BDZAm = 554 | |
| CEFBS_None, // BDZAp = 555 | |
| CEFBS_None, // BDZL = 556 | |
| CEFBS_None, // BDZLA = 557 | |
| CEFBS_None, // BDZLAm = 558 | |
| CEFBS_None, // BDZLAp = 559 | |
| CEFBS_None, // BDZLR = 560 | |
| CEFBS_None, // BDZLR8 = 561 | |
| CEFBS_None, // BDZLRL = 562 | |
| CEFBS_None, // BDZLRLm = 563 | |
| CEFBS_None, // BDZLRLp = 564 | |
| CEFBS_None, // BDZLRm = 565 | |
| CEFBS_None, // BDZLRp = 566 | |
| CEFBS_None, // BDZLm = 567 | |
| CEFBS_None, // BDZLp = 568 | |
| CEFBS_None, // BDZm = 569 | |
| CEFBS_None, // BDZp = 570 | |
| CEFBS_None, // BL = 571 | |
| CEFBS_None, // BL8 = 572 | |
| CEFBS_None, // BL8_NOP = 573 | |
| CEFBS_None, // BL8_NOP_RM = 574 | |
| CEFBS_None, // BL8_NOP_TLS = 575 | |
| CEFBS_None, // BL8_NOTOC = 576 | |
| CEFBS_None, // BL8_NOTOC_RM = 577 | |
| CEFBS_None, // BL8_NOTOC_TLS = 578 | |
| CEFBS_None, // BL8_RM = 579 | |
| CEFBS_None, // BL8_TLS = 580 | |
| CEFBS_None, // BL8_TLS_ = 581 | |
| CEFBS_None, // BLA = 582 | |
| CEFBS_None, // BLA8 = 583 | |
| CEFBS_None, // BLA8_NOP = 584 | |
| CEFBS_None, // BLA8_NOP_RM = 585 | |
| CEFBS_None, // BLA8_RM = 586 | |
| CEFBS_None, // BLA_RM = 587 | |
| CEFBS_None, // BLR = 588 | |
| CEFBS_None, // BLR8 = 589 | |
| CEFBS_None, // BLRL = 590 | |
| CEFBS_None, // BL_NOP = 591 | |
| CEFBS_None, // BL_NOP_RM = 592 | |
| CEFBS_None, // BL_RM = 593 | |
| CEFBS_None, // BL_TLS = 594 | |
| CEFBS_None, // BPERMD = 595 | |
| CEFBS_None, // BRD = 596 | |
| CEFBS_None, // BRH = 597 | |
| CEFBS_None, // BRH8 = 598 | |
| CEFBS_None, // BRINC = 599 | |
| CEFBS_None, // BRW = 600 | |
| CEFBS_None, // BRW8 = 601 | |
| CEFBS_None, // CFUGED = 602 | |
| CEFBS_None, // CLRBHRB = 603 | |
| CEFBS_None, // CMPB = 604 | |
| CEFBS_None, // CMPB8 = 605 | |
| CEFBS_None, // CMPD = 606 | |
| CEFBS_None, // CMPDI = 607 | |
| CEFBS_None, // CMPEQB = 608 | |
| CEFBS_None, // CMPLD = 609 | |
| CEFBS_None, // CMPLDI = 610 | |
| CEFBS_None, // CMPLW = 611 | |
| CEFBS_None, // CMPLWI = 612 | |
| CEFBS_None, // CMPRB = 613 | |
| CEFBS_None, // CMPRB8 = 614 | |
| CEFBS_None, // CMPW = 615 | |
| CEFBS_None, // CMPWI = 616 | |
| CEFBS_None, // CNTLZD = 617 | |
| CEFBS_None, // CNTLZDM = 618 | |
| CEFBS_None, // CNTLZD_rec = 619 | |
| CEFBS_None, // CNTLZW = 620 | |
| CEFBS_None, // CNTLZW8 = 621 | |
| CEFBS_None, // CNTLZW8_rec = 622 | |
| CEFBS_None, // CNTLZW_rec = 623 | |
| CEFBS_None, // CNTTZD = 624 | |
| CEFBS_None, // CNTTZDM = 625 | |
| CEFBS_None, // CNTTZD_rec = 626 | |
| CEFBS_None, // CNTTZW = 627 | |
| CEFBS_None, // CNTTZW8 = 628 | |
| CEFBS_None, // CNTTZW8_rec = 629 | |
| CEFBS_None, // CNTTZW_rec = 630 | |
| CEFBS_None, // CP_ABORT = 631 | |
| CEFBS_None, // CP_COPY = 632 | |
| CEFBS_None, // CP_COPY8 = 633 | |
| CEFBS_None, // CP_PASTE8_rec = 634 | |
| CEFBS_None, // CP_PASTE_rec = 635 | |
| CEFBS_None, // CR6SET = 636 | |
| CEFBS_None, // CR6UNSET = 637 | |
| CEFBS_None, // CRAND = 638 | |
| CEFBS_None, // CRANDC = 639 | |
| CEFBS_None, // CREQV = 640 | |
| CEFBS_None, // CRNAND = 641 | |
| CEFBS_None, // CRNOR = 642 | |
| CEFBS_None, // CRNOT = 643 | |
| CEFBS_None, // CROR = 644 | |
| CEFBS_None, // CRORC = 645 | |
| CEFBS_None, // CRSET = 646 | |
| CEFBS_None, // CRUNSET = 647 | |
| CEFBS_None, // CRXOR = 648 | |
| CEFBS_None, // CTRL_DEP = 649 | |
| CEFBS_None, // DARN = 650 | |
| CEFBS_None, // DCBA = 651 | |
| CEFBS_None, // DCBF = 652 | |
| CEFBS_None, // DCBFEP = 653 | |
| CEFBS_None, // DCBI = 654 | |
| CEFBS_None, // DCBST = 655 | |
| CEFBS_None, // DCBSTEP = 656 | |
| CEFBS_None, // DCBT = 657 | |
| CEFBS_None, // DCBTEP = 658 | |
| CEFBS_None, // DCBTST = 659 | |
| CEFBS_None, // DCBTSTEP = 660 | |
| CEFBS_None, // DCBZ = 661 | |
| CEFBS_None, // DCBZEP = 662 | |
| CEFBS_None, // DCBZL = 663 | |
| CEFBS_None, // DCBZLEP = 664 | |
| CEFBS_None, // DCCCI = 665 | |
| CEFBS_None, // DIVD = 666 | |
| CEFBS_None, // DIVDE = 667 | |
| CEFBS_None, // DIVDEO = 668 | |
| CEFBS_None, // DIVDEO_rec = 669 | |
| CEFBS_None, // DIVDEU = 670 | |
| CEFBS_None, // DIVDEUO = 671 | |
| CEFBS_None, // DIVDEUO_rec = 672 | |
| CEFBS_None, // DIVDEU_rec = 673 | |
| CEFBS_None, // DIVDE_rec = 674 | |
| CEFBS_None, // DIVDO = 675 | |
| CEFBS_None, // DIVDO_rec = 676 | |
| CEFBS_None, // DIVDU = 677 | |
| CEFBS_None, // DIVDUO = 678 | |
| CEFBS_None, // DIVDUO_rec = 679 | |
| CEFBS_None, // DIVDU_rec = 680 | |
| CEFBS_None, // DIVD_rec = 681 | |
| CEFBS_None, // DIVW = 682 | |
| CEFBS_None, // DIVWE = 683 | |
| CEFBS_None, // DIVWEO = 684 | |
| CEFBS_None, // DIVWEO_rec = 685 | |
| CEFBS_None, // DIVWEU = 686 | |
| CEFBS_None, // DIVWEUO = 687 | |
| CEFBS_None, // DIVWEUO_rec = 688 | |
| CEFBS_None, // DIVWEU_rec = 689 | |
| CEFBS_None, // DIVWE_rec = 690 | |
| CEFBS_None, // DIVWO = 691 | |
| CEFBS_None, // DIVWO_rec = 692 | |
| CEFBS_None, // DIVWU = 693 | |
| CEFBS_None, // DIVWUO = 694 | |
| CEFBS_None, // DIVWUO_rec = 695 | |
| CEFBS_None, // DIVWU_rec = 696 | |
| CEFBS_None, // DIVW_rec = 697 | |
| CEFBS_None, // DMMR = 698 | |
| CEFBS_None, // DMSETDMRZ = 699 | |
| CEFBS_None, // DMXOR = 700 | |
| CEFBS_None, // DMXXEXTFDMR256 = 701 | |
| CEFBS_None, // DMXXEXTFDMR512 = 702 | |
| CEFBS_None, // DMXXEXTFDMR512_HI = 703 | |
| CEFBS_None, // DMXXINSTFDMR256 = 704 | |
| CEFBS_None, // DMXXINSTFDMR512 = 705 | |
| CEFBS_None, // DMXXINSTFDMR512_HI = 706 | |
| CEFBS_None, // DSS = 707 | |
| CEFBS_None, // DSSALL = 708 | |
| CEFBS_None, // DST = 709 | |
| CEFBS_None, // DST64 = 710 | |
| CEFBS_None, // DSTST = 711 | |
| CEFBS_None, // DSTST64 = 712 | |
| CEFBS_None, // DSTSTT = 713 | |
| CEFBS_None, // DSTSTT64 = 714 | |
| CEFBS_None, // DSTT = 715 | |
| CEFBS_None, // DSTT64 = 716 | |
| CEFBS_None, // DYNALLOC = 717 | |
| CEFBS_None, // DYNALLOC8 = 718 | |
| CEFBS_None, // DYNAREAOFFSET = 719 | |
| CEFBS_None, // DYNAREAOFFSET8 = 720 | |
| CEFBS_None, // DecreaseCTR8loop = 721 | |
| CEFBS_None, // DecreaseCTRloop = 722 | |
| CEFBS_None, // EFDABS = 723 | |
| CEFBS_None, // EFDADD = 724 | |
| CEFBS_None, // EFDCFS = 725 | |
| CEFBS_None, // EFDCFSF = 726 | |
| CEFBS_None, // EFDCFSI = 727 | |
| CEFBS_None, // EFDCFSID = 728 | |
| CEFBS_None, // EFDCFUF = 729 | |
| CEFBS_None, // EFDCFUI = 730 | |
| CEFBS_None, // EFDCFUID = 731 | |
| CEFBS_None, // EFDCMPEQ = 732 | |
| CEFBS_None, // EFDCMPGT = 733 | |
| CEFBS_None, // EFDCMPLT = 734 | |
| CEFBS_None, // EFDCTSF = 735 | |
| CEFBS_None, // EFDCTSI = 736 | |
| CEFBS_None, // EFDCTSIDZ = 737 | |
| CEFBS_None, // EFDCTSIZ = 738 | |
| CEFBS_None, // EFDCTUF = 739 | |
| CEFBS_None, // EFDCTUI = 740 | |
| CEFBS_None, // EFDCTUIDZ = 741 | |
| CEFBS_None, // EFDCTUIZ = 742 | |
| CEFBS_None, // EFDDIV = 743 | |
| CEFBS_None, // EFDMUL = 744 | |
| CEFBS_None, // EFDNABS = 745 | |
| CEFBS_None, // EFDNEG = 746 | |
| CEFBS_None, // EFDSUB = 747 | |
| CEFBS_None, // EFDTSTEQ = 748 | |
| CEFBS_None, // EFDTSTGT = 749 | |
| CEFBS_None, // EFDTSTLT = 750 | |
| CEFBS_None, // EFSABS = 751 | |
| CEFBS_None, // EFSADD = 752 | |
| CEFBS_None, // EFSCFD = 753 | |
| CEFBS_None, // EFSCFSF = 754 | |
| CEFBS_None, // EFSCFSI = 755 | |
| CEFBS_None, // EFSCFUF = 756 | |
| CEFBS_None, // EFSCFUI = 757 | |
| CEFBS_None, // EFSCMPEQ = 758 | |
| CEFBS_None, // EFSCMPGT = 759 | |
| CEFBS_None, // EFSCMPLT = 760 | |
| CEFBS_None, // EFSCTSF = 761 | |
| CEFBS_None, // EFSCTSI = 762 | |
| CEFBS_None, // EFSCTSIZ = 763 | |
| CEFBS_None, // EFSCTUF = 764 | |
| CEFBS_None, // EFSCTUI = 765 | |
| CEFBS_None, // EFSCTUIZ = 766 | |
| CEFBS_None, // EFSDIV = 767 | |
| CEFBS_None, // EFSMUL = 768 | |
| CEFBS_None, // EFSNABS = 769 | |
| CEFBS_None, // EFSNEG = 770 | |
| CEFBS_None, // EFSSUB = 771 | |
| CEFBS_None, // EFSTSTEQ = 772 | |
| CEFBS_None, // EFSTSTGT = 773 | |
| CEFBS_None, // EFSTSTLT = 774 | |
| CEFBS_None, // EH_SjLj_LongJmp32 = 775 | |
| CEFBS_None, // EH_SjLj_LongJmp64 = 776 | |
| CEFBS_None, // EH_SjLj_SetJmp32 = 777 | |
| CEFBS_None, // EH_SjLj_SetJmp64 = 778 | |
| CEFBS_None, // EH_SjLj_Setup = 779 | |
| CEFBS_None, // EQV = 780 | |
| CEFBS_None, // EQV8 = 781 | |
| CEFBS_None, // EQV8_rec = 782 | |
| CEFBS_None, // EQV_rec = 783 | |
| CEFBS_None, // EVABS = 784 | |
| CEFBS_None, // EVADDIW = 785 | |
| CEFBS_None, // EVADDSMIAAW = 786 | |
| CEFBS_None, // EVADDSSIAAW = 787 | |
| CEFBS_None, // EVADDUMIAAW = 788 | |
| CEFBS_None, // EVADDUSIAAW = 789 | |
| CEFBS_None, // EVADDW = 790 | |
| CEFBS_None, // EVAND = 791 | |
| CEFBS_None, // EVANDC = 792 | |
| CEFBS_None, // EVCMPEQ = 793 | |
| CEFBS_None, // EVCMPGTS = 794 | |
| CEFBS_None, // EVCMPGTU = 795 | |
| CEFBS_None, // EVCMPLTS = 796 | |
| CEFBS_None, // EVCMPLTU = 797 | |
| CEFBS_None, // EVCNTLSW = 798 | |
| CEFBS_None, // EVCNTLZW = 799 | |
| CEFBS_None, // EVDIVWS = 800 | |
| CEFBS_None, // EVDIVWU = 801 | |
| CEFBS_None, // EVEQV = 802 | |
| CEFBS_None, // EVEXTSB = 803 | |
| CEFBS_None, // EVEXTSH = 804 | |
| CEFBS_None, // EVFSABS = 805 | |
| CEFBS_None, // EVFSADD = 806 | |
| CEFBS_None, // EVFSCFSF = 807 | |
| CEFBS_None, // EVFSCFSI = 808 | |
| CEFBS_None, // EVFSCFUF = 809 | |
| CEFBS_None, // EVFSCFUI = 810 | |
| CEFBS_None, // EVFSCMPEQ = 811 | |
| CEFBS_None, // EVFSCMPGT = 812 | |
| CEFBS_None, // EVFSCMPLT = 813 | |
| CEFBS_None, // EVFSCTSF = 814 | |
| CEFBS_None, // EVFSCTSI = 815 | |
| CEFBS_None, // EVFSCTSIZ = 816 | |
| CEFBS_None, // EVFSCTUF = 817 | |
| CEFBS_None, // EVFSCTUI = 818 | |
| CEFBS_None, // EVFSCTUIZ = 819 | |
| CEFBS_None, // EVFSDIV = 820 | |
| CEFBS_None, // EVFSMUL = 821 | |
| CEFBS_None, // EVFSNABS = 822 | |
| CEFBS_None, // EVFSNEG = 823 | |
| CEFBS_None, // EVFSSUB = 824 | |
| CEFBS_None, // EVFSTSTEQ = 825 | |
| CEFBS_None, // EVFSTSTGT = 826 | |
| CEFBS_None, // EVFSTSTLT = 827 | |
| CEFBS_None, // EVLDD = 828 | |
| CEFBS_None, // EVLDDX = 829 | |
| CEFBS_None, // EVLDH = 830 | |
| CEFBS_None, // EVLDHX = 831 | |
| CEFBS_None, // EVLDW = 832 | |
| CEFBS_None, // EVLDWX = 833 | |
| CEFBS_None, // EVLHHESPLAT = 834 | |
| CEFBS_None, // EVLHHESPLATX = 835 | |
| CEFBS_None, // EVLHHOSSPLAT = 836 | |
| CEFBS_None, // EVLHHOSSPLATX = 837 | |
| CEFBS_None, // EVLHHOUSPLAT = 838 | |
| CEFBS_None, // EVLHHOUSPLATX = 839 | |
| CEFBS_None, // EVLWHE = 840 | |
| CEFBS_None, // EVLWHEX = 841 | |
| CEFBS_None, // EVLWHOS = 842 | |
| CEFBS_None, // EVLWHOSX = 843 | |
| CEFBS_None, // EVLWHOU = 844 | |
| CEFBS_None, // EVLWHOUX = 845 | |
| CEFBS_None, // EVLWHSPLAT = 846 | |
| CEFBS_None, // EVLWHSPLATX = 847 | |
| CEFBS_None, // EVLWWSPLAT = 848 | |
| CEFBS_None, // EVLWWSPLATX = 849 | |
| CEFBS_None, // EVMERGEHI = 850 | |
| CEFBS_None, // EVMERGEHILO = 851 | |
| CEFBS_None, // EVMERGELO = 852 | |
| CEFBS_None, // EVMERGELOHI = 853 | |
| CEFBS_None, // EVMHEGSMFAA = 854 | |
| CEFBS_None, // EVMHEGSMFAN = 855 | |
| CEFBS_None, // EVMHEGSMIAA = 856 | |
| CEFBS_None, // EVMHEGSMIAN = 857 | |
| CEFBS_None, // EVMHEGUMIAA = 858 | |
| CEFBS_None, // EVMHEGUMIAN = 859 | |
| CEFBS_None, // EVMHESMF = 860 | |
| CEFBS_None, // EVMHESMFA = 861 | |
| CEFBS_None, // EVMHESMFAAW = 862 | |
| CEFBS_None, // EVMHESMFANW = 863 | |
| CEFBS_None, // EVMHESMI = 864 | |
| CEFBS_None, // EVMHESMIA = 865 | |
| CEFBS_None, // EVMHESMIAAW = 866 | |
| CEFBS_None, // EVMHESMIANW = 867 | |
| CEFBS_None, // EVMHESSF = 868 | |
| CEFBS_None, // EVMHESSFA = 869 | |
| CEFBS_None, // EVMHESSFAAW = 870 | |
| CEFBS_None, // EVMHESSFANW = 871 | |
| CEFBS_None, // EVMHESSIAAW = 872 | |
| CEFBS_None, // EVMHESSIANW = 873 | |
| CEFBS_None, // EVMHEUMI = 874 | |
| CEFBS_None, // EVMHEUMIA = 875 | |
| CEFBS_None, // EVMHEUMIAAW = 876 | |
| CEFBS_None, // EVMHEUMIANW = 877 | |
| CEFBS_None, // EVMHEUSIAAW = 878 | |
| CEFBS_None, // EVMHEUSIANW = 879 | |
| CEFBS_None, // EVMHOGSMFAA = 880 | |
| CEFBS_None, // EVMHOGSMFAN = 881 | |
| CEFBS_None, // EVMHOGSMIAA = 882 | |
| CEFBS_None, // EVMHOGSMIAN = 883 | |
| CEFBS_None, // EVMHOGUMIAA = 884 | |
| CEFBS_None, // EVMHOGUMIAN = 885 | |
| CEFBS_None, // EVMHOSMF = 886 | |
| CEFBS_None, // EVMHOSMFA = 887 | |
| CEFBS_None, // EVMHOSMFAAW = 888 | |
| CEFBS_None, // EVMHOSMFANW = 889 | |
| CEFBS_None, // EVMHOSMI = 890 | |
| CEFBS_None, // EVMHOSMIA = 891 | |
| CEFBS_None, // EVMHOSMIAAW = 892 | |
| CEFBS_None, // EVMHOSMIANW = 893 | |
| CEFBS_None, // EVMHOSSF = 894 | |
| CEFBS_None, // EVMHOSSFA = 895 | |
| CEFBS_None, // EVMHOSSFAAW = 896 | |
| CEFBS_None, // EVMHOSSFANW = 897 | |
| CEFBS_None, // EVMHOSSIAAW = 898 | |
| CEFBS_None, // EVMHOSSIANW = 899 | |
| CEFBS_None, // EVMHOUMI = 900 | |
| CEFBS_None, // EVMHOUMIA = 901 | |
| CEFBS_None, // EVMHOUMIAAW = 902 | |
| CEFBS_None, // EVMHOUMIANW = 903 | |
| CEFBS_None, // EVMHOUSIAAW = 904 | |
| CEFBS_None, // EVMHOUSIANW = 905 | |
| CEFBS_None, // EVMRA = 906 | |
| CEFBS_None, // EVMWHSMF = 907 | |
| CEFBS_None, // EVMWHSMFA = 908 | |
| CEFBS_None, // EVMWHSMI = 909 | |
| CEFBS_None, // EVMWHSMIA = 910 | |
| CEFBS_None, // EVMWHSSF = 911 | |
| CEFBS_None, // EVMWHSSFA = 912 | |
| CEFBS_None, // EVMWHUMI = 913 | |
| CEFBS_None, // EVMWHUMIA = 914 | |
| CEFBS_None, // EVMWLSMIAAW = 915 | |
| CEFBS_None, // EVMWLSMIANW = 916 | |
| CEFBS_None, // EVMWLSSIAAW = 917 | |
| CEFBS_None, // EVMWLSSIANW = 918 | |
| CEFBS_None, // EVMWLUMI = 919 | |
| CEFBS_None, // EVMWLUMIA = 920 | |
| CEFBS_None, // EVMWLUMIAAW = 921 | |
| CEFBS_None, // EVMWLUMIANW = 922 | |
| CEFBS_None, // EVMWLUSIAAW = 923 | |
| CEFBS_None, // EVMWLUSIANW = 924 | |
| CEFBS_None, // EVMWSMF = 925 | |
| CEFBS_None, // EVMWSMFA = 926 | |
| CEFBS_None, // EVMWSMFAA = 927 | |
| CEFBS_None, // EVMWSMFAN = 928 | |
| CEFBS_None, // EVMWSMI = 929 | |
| CEFBS_None, // EVMWSMIA = 930 | |
| CEFBS_None, // EVMWSMIAA = 931 | |
| CEFBS_None, // EVMWSMIAN = 932 | |
| CEFBS_None, // EVMWSSF = 933 | |
| CEFBS_None, // EVMWSSFA = 934 | |
| CEFBS_None, // EVMWSSFAA = 935 | |
| CEFBS_None, // EVMWSSFAN = 936 | |
| CEFBS_None, // EVMWUMI = 937 | |
| CEFBS_None, // EVMWUMIA = 938 | |
| CEFBS_None, // EVMWUMIAA = 939 | |
| CEFBS_None, // EVMWUMIAN = 940 | |
| CEFBS_None, // EVNAND = 941 | |
| CEFBS_None, // EVNEG = 942 | |
| CEFBS_None, // EVNOR = 943 | |
| CEFBS_None, // EVOR = 944 | |
| CEFBS_None, // EVORC = 945 | |
| CEFBS_None, // EVRLW = 946 | |
| CEFBS_None, // EVRLWI = 947 | |
| CEFBS_None, // EVRNDW = 948 | |
| CEFBS_None, // EVSEL = 949 | |
| CEFBS_None, // EVSLW = 950 | |
| CEFBS_None, // EVSLWI = 951 | |
| CEFBS_None, // EVSPLATFI = 952 | |
| CEFBS_None, // EVSPLATI = 953 | |
| CEFBS_None, // EVSRWIS = 954 | |
| CEFBS_None, // EVSRWIU = 955 | |
| CEFBS_None, // EVSRWS = 956 | |
| CEFBS_None, // EVSRWU = 957 | |
| CEFBS_None, // EVSTDD = 958 | |
| CEFBS_None, // EVSTDDX = 959 | |
| CEFBS_None, // EVSTDH = 960 | |
| CEFBS_None, // EVSTDHX = 961 | |
| CEFBS_None, // EVSTDW = 962 | |
| CEFBS_None, // EVSTDWX = 963 | |
| CEFBS_None, // EVSTWHE = 964 | |
| CEFBS_None, // EVSTWHEX = 965 | |
| CEFBS_None, // EVSTWHO = 966 | |
| CEFBS_None, // EVSTWHOX = 967 | |
| CEFBS_None, // EVSTWWE = 968 | |
| CEFBS_None, // EVSTWWEX = 969 | |
| CEFBS_None, // EVSTWWO = 970 | |
| CEFBS_None, // EVSTWWOX = 971 | |
| CEFBS_None, // EVSUBFSMIAAW = 972 | |
| CEFBS_None, // EVSUBFSSIAAW = 973 | |
| CEFBS_None, // EVSUBFUMIAAW = 974 | |
| CEFBS_None, // EVSUBFUSIAAW = 975 | |
| CEFBS_None, // EVSUBFW = 976 | |
| CEFBS_None, // EVSUBIFW = 977 | |
| CEFBS_None, // EVXOR = 978 | |
| CEFBS_None, // EXTSB = 979 | |
| CEFBS_None, // EXTSB8 = 980 | |
| CEFBS_None, // EXTSB8_32_64 = 981 | |
| CEFBS_None, // EXTSB8_rec = 982 | |
| CEFBS_None, // EXTSB_rec = 983 | |
| CEFBS_None, // EXTSH = 984 | |
| CEFBS_None, // EXTSH8 = 985 | |
| CEFBS_None, // EXTSH8_32_64 = 986 | |
| CEFBS_None, // EXTSH8_rec = 987 | |
| CEFBS_None, // EXTSH_rec = 988 | |
| CEFBS_None, // EXTSW = 989 | |
| CEFBS_None, // EXTSWSLI = 990 | |
| CEFBS_None, // EXTSWSLI_32_64 = 991 | |
| CEFBS_None, // EXTSWSLI_32_64_rec = 992 | |
| CEFBS_None, // EXTSWSLI_rec = 993 | |
| CEFBS_None, // EXTSW_32 = 994 | |
| CEFBS_None, // EXTSW_32_64 = 995 | |
| CEFBS_None, // EXTSW_32_64_rec = 996 | |
| CEFBS_None, // EXTSW_rec = 997 | |
| CEFBS_None, // EnforceIEIO = 998 | |
| CEFBS_None, // FABSD = 999 | |
| CEFBS_None, // FABSD_rec = 1000 | |
| CEFBS_None, // FABSS = 1001 | |
| CEFBS_None, // FABSS_rec = 1002 | |
| CEFBS_None, // FADD = 1003 | |
| CEFBS_None, // FADDS = 1004 | |
| CEFBS_None, // FADDS_rec = 1005 | |
| CEFBS_None, // FADD_rec = 1006 | |
| CEFBS_None, // FADDrtz = 1007 | |
| CEFBS_None, // FCFID = 1008 | |
| CEFBS_None, // FCFIDS = 1009 | |
| CEFBS_None, // FCFIDS_rec = 1010 | |
| CEFBS_None, // FCFIDU = 1011 | |
| CEFBS_None, // FCFIDUS = 1012 | |
| CEFBS_None, // FCFIDUS_rec = 1013 | |
| CEFBS_None, // FCFIDU_rec = 1014 | |
| CEFBS_None, // FCFID_rec = 1015 | |
| CEFBS_None, // FCMPOD = 1016 | |
| CEFBS_None, // FCMPOS = 1017 | |
| CEFBS_None, // FCMPUD = 1018 | |
| CEFBS_None, // FCMPUS = 1019 | |
| CEFBS_None, // FCPSGND = 1020 | |
| CEFBS_None, // FCPSGND_rec = 1021 | |
| CEFBS_None, // FCPSGNS = 1022 | |
| CEFBS_None, // FCPSGNS_rec = 1023 | |
| CEFBS_None, // FCTID = 1024 | |
| CEFBS_None, // FCTIDU = 1025 | |
| CEFBS_None, // FCTIDUZ = 1026 | |
| CEFBS_None, // FCTIDUZ_rec = 1027 | |
| CEFBS_None, // FCTIDU_rec = 1028 | |
| CEFBS_None, // FCTIDZ = 1029 | |
| CEFBS_None, // FCTIDZ_rec = 1030 | |
| CEFBS_None, // FCTID_rec = 1031 | |
| CEFBS_None, // FCTIW = 1032 | |
| CEFBS_None, // FCTIWU = 1033 | |
| CEFBS_None, // FCTIWUZ = 1034 | |
| CEFBS_None, // FCTIWUZ_rec = 1035 | |
| CEFBS_None, // FCTIWU_rec = 1036 | |
| CEFBS_None, // FCTIWZ = 1037 | |
| CEFBS_None, // FCTIWZ_rec = 1038 | |
| CEFBS_None, // FCTIW_rec = 1039 | |
| CEFBS_None, // FDIV = 1040 | |
| CEFBS_None, // FDIVS = 1041 | |
| CEFBS_None, // FDIVS_rec = 1042 | |
| CEFBS_None, // FDIV_rec = 1043 | |
| CEFBS_None, // FMADD = 1044 | |
| CEFBS_None, // FMADDS = 1045 | |
| CEFBS_None, // FMADDS_rec = 1046 | |
| CEFBS_None, // FMADD_rec = 1047 | |
| CEFBS_None, // FMR = 1048 | |
| CEFBS_None, // FMR_rec = 1049 | |
| CEFBS_None, // FMSUB = 1050 | |
| CEFBS_None, // FMSUBS = 1051 | |
| CEFBS_None, // FMSUBS_rec = 1052 | |
| CEFBS_None, // FMSUB_rec = 1053 | |
| CEFBS_None, // FMUL = 1054 | |
| CEFBS_None, // FMULS = 1055 | |
| CEFBS_None, // FMULS_rec = 1056 | |
| CEFBS_None, // FMUL_rec = 1057 | |
| CEFBS_None, // FNABSD = 1058 | |
| CEFBS_None, // FNABSD_rec = 1059 | |
| CEFBS_None, // FNABSS = 1060 | |
| CEFBS_None, // FNABSS_rec = 1061 | |
| CEFBS_None, // FNEGD = 1062 | |
| CEFBS_None, // FNEGD_rec = 1063 | |
| CEFBS_None, // FNEGS = 1064 | |
| CEFBS_None, // FNEGS_rec = 1065 | |
| CEFBS_None, // FNMADD = 1066 | |
| CEFBS_None, // FNMADDS = 1067 | |
| CEFBS_None, // FNMADDS_rec = 1068 | |
| CEFBS_None, // FNMADD_rec = 1069 | |
| CEFBS_None, // FNMSUB = 1070 | |
| CEFBS_None, // FNMSUBS = 1071 | |
| CEFBS_None, // FNMSUBS_rec = 1072 | |
| CEFBS_None, // FNMSUB_rec = 1073 | |
| CEFBS_None, // FRE = 1074 | |
| CEFBS_None, // FRES = 1075 | |
| CEFBS_None, // FRES_rec = 1076 | |
| CEFBS_None, // FRE_rec = 1077 | |
| CEFBS_None, // FRIMD = 1078 | |
| CEFBS_None, // FRIMD_rec = 1079 | |
| CEFBS_None, // FRIMS = 1080 | |
| CEFBS_None, // FRIMS_rec = 1081 | |
| CEFBS_None, // FRIND = 1082 | |
| CEFBS_None, // FRIND_rec = 1083 | |
| CEFBS_None, // FRINS = 1084 | |
| CEFBS_None, // FRINS_rec = 1085 | |
| CEFBS_None, // FRIPD = 1086 | |
| CEFBS_None, // FRIPD_rec = 1087 | |
| CEFBS_None, // FRIPS = 1088 | |
| CEFBS_None, // FRIPS_rec = 1089 | |
| CEFBS_None, // FRIZD = 1090 | |
| CEFBS_None, // FRIZD_rec = 1091 | |
| CEFBS_None, // FRIZS = 1092 | |
| CEFBS_None, // FRIZS_rec = 1093 | |
| CEFBS_None, // FRSP = 1094 | |
| CEFBS_None, // FRSP_rec = 1095 | |
| CEFBS_None, // FRSQRTE = 1096 | |
| CEFBS_None, // FRSQRTES = 1097 | |
| CEFBS_None, // FRSQRTES_rec = 1098 | |
| CEFBS_None, // FRSQRTE_rec = 1099 | |
| CEFBS_None, // FSELD = 1100 | |
| CEFBS_None, // FSELD_rec = 1101 | |
| CEFBS_None, // FSELS = 1102 | |
| CEFBS_None, // FSELS_rec = 1103 | |
| CEFBS_None, // FSQRT = 1104 | |
| CEFBS_None, // FSQRTS = 1105 | |
| CEFBS_None, // FSQRTS_rec = 1106 | |
| CEFBS_None, // FSQRT_rec = 1107 | |
| CEFBS_None, // FSUB = 1108 | |
| CEFBS_None, // FSUBS = 1109 | |
| CEFBS_None, // FSUBS_rec = 1110 | |
| CEFBS_None, // FSUB_rec = 1111 | |
| CEFBS_None, // FTDIV = 1112 | |
| CEFBS_None, // FTSQRT = 1113 | |
| CEFBS_None, // GETtlsADDR = 1114 | |
| CEFBS_None, // GETtlsADDR32 = 1115 | |
| CEFBS_None, // GETtlsADDR32AIX = 1116 | |
| CEFBS_None, // GETtlsADDR64AIX = 1117 | |
| CEFBS_None, // GETtlsADDRPCREL = 1118 | |
| CEFBS_None, // GETtlsldADDR = 1119 | |
| CEFBS_None, // GETtlsldADDR32 = 1120 | |
| CEFBS_None, // GETtlsldADDRPCREL = 1121 | |
| CEFBS_None, // HASHCHK = 1122 | |
| CEFBS_None, // HASHCHK8 = 1123 | |
| CEFBS_None, // HASHCHKP = 1124 | |
| CEFBS_None, // HASHCHKP8 = 1125 | |
| CEFBS_None, // HASHST = 1126 | |
| CEFBS_None, // HASHST8 = 1127 | |
| CEFBS_None, // HASHSTP = 1128 | |
| CEFBS_None, // HASHSTP8 = 1129 | |
| CEFBS_None, // HRFID = 1130 | |
| CEFBS_None, // ICBI = 1131 | |
| CEFBS_None, // ICBIEP = 1132 | |
| CEFBS_None, // ICBLC = 1133 | |
| CEFBS_None, // ICBLQ = 1134 | |
| CEFBS_None, // ICBT = 1135 | |
| CEFBS_None, // ICBTLS = 1136 | |
| CEFBS_None, // ICCCI = 1137 | |
| CEFBS_None, // ISEL = 1138 | |
| CEFBS_None, // ISEL8 = 1139 | |
| CEFBS_None, // ISYNC = 1140 | |
| CEFBS_None, // LA = 1141 | |
| CEFBS_None, // LA8 = 1142 | |
| CEFBS_None, // LBARX = 1143 | |
| CEFBS_None, // LBARXL = 1144 | |
| CEFBS_None, // LBEPX = 1145 | |
| CEFBS_None, // LBZ = 1146 | |
| CEFBS_None, // LBZ8 = 1147 | |
| CEFBS_None, // LBZCIX = 1148 | |
| CEFBS_None, // LBZU = 1149 | |
| CEFBS_None, // LBZU8 = 1150 | |
| CEFBS_None, // LBZUX = 1151 | |
| CEFBS_None, // LBZUX8 = 1152 | |
| CEFBS_None, // LBZX = 1153 | |
| CEFBS_None, // LBZX8 = 1154 | |
| CEFBS_None, // LBZXTLS = 1155 | |
| CEFBS_None, // LBZXTLS_ = 1156 | |
| CEFBS_None, // LBZXTLS_32 = 1157 | |
| CEFBS_None, // LD = 1158 | |
| CEFBS_None, // LDARX = 1159 | |
| CEFBS_None, // LDARXL = 1160 | |
| CEFBS_None, // LDAT = 1161 | |
| CEFBS_None, // LDBRX = 1162 | |
| CEFBS_None, // LDCIX = 1163 | |
| CEFBS_None, // LDU = 1164 | |
| CEFBS_None, // LDUX = 1165 | |
| CEFBS_None, // LDX = 1166 | |
| CEFBS_None, // LDXTLS = 1167 | |
| CEFBS_None, // LDXTLS_ = 1168 | |
| CEFBS_None, // LDgotTprelL = 1169 | |
| CEFBS_None, // LDgotTprelL32 = 1170 | |
| CEFBS_None, // LDtoc = 1171 | |
| CEFBS_None, // LDtocBA = 1172 | |
| CEFBS_None, // LDtocCPT = 1173 | |
| CEFBS_None, // LDtocJTI = 1174 | |
| CEFBS_None, // LDtocL = 1175 | |
| CEFBS_None, // LFD = 1176 | |
| CEFBS_None, // LFDEPX = 1177 | |
| CEFBS_None, // LFDU = 1178 | |
| CEFBS_None, // LFDUX = 1179 | |
| CEFBS_None, // LFDX = 1180 | |
| CEFBS_None, // LFIWAX = 1181 | |
| CEFBS_None, // LFIWZX = 1182 | |
| CEFBS_None, // LFS = 1183 | |
| CEFBS_None, // LFSU = 1184 | |
| CEFBS_None, // LFSUX = 1185 | |
| CEFBS_None, // LFSX = 1186 | |
| CEFBS_None, // LHA = 1187 | |
| CEFBS_None, // LHA8 = 1188 | |
| CEFBS_None, // LHARX = 1189 | |
| CEFBS_None, // LHARXL = 1190 | |
| CEFBS_None, // LHAU = 1191 | |
| CEFBS_None, // LHAU8 = 1192 | |
| CEFBS_None, // LHAUX = 1193 | |
| CEFBS_None, // LHAUX8 = 1194 | |
| CEFBS_None, // LHAX = 1195 | |
| CEFBS_None, // LHAX8 = 1196 | |
| CEFBS_None, // LHBRX = 1197 | |
| CEFBS_None, // LHBRX8 = 1198 | |
| CEFBS_None, // LHEPX = 1199 | |
| CEFBS_None, // LHZ = 1200 | |
| CEFBS_None, // LHZ8 = 1201 | |
| CEFBS_None, // LHZCIX = 1202 | |
| CEFBS_None, // LHZU = 1203 | |
| CEFBS_None, // LHZU8 = 1204 | |
| CEFBS_None, // LHZUX = 1205 | |
| CEFBS_None, // LHZUX8 = 1206 | |
| CEFBS_None, // LHZX = 1207 | |
| CEFBS_None, // LHZX8 = 1208 | |
| CEFBS_None, // LHZXTLS = 1209 | |
| CEFBS_None, // LHZXTLS_ = 1210 | |
| CEFBS_None, // LHZXTLS_32 = 1211 | |
| CEFBS_None, // LI = 1212 | |
| CEFBS_None, // LI8 = 1213 | |
| CEFBS_None, // LIS = 1214 | |
| CEFBS_None, // LIS8 = 1215 | |
| CEFBS_None, // LMW = 1216 | |
| CEFBS_None, // LQ = 1217 | |
| CEFBS_None, // LQARX = 1218 | |
| CEFBS_None, // LQARXL = 1219 | |
| CEFBS_None, // LQX_PSEUDO = 1220 | |
| CEFBS_None, // LSWI = 1221 | |
| CEFBS_None, // LVEBX = 1222 | |
| CEFBS_None, // LVEHX = 1223 | |
| CEFBS_None, // LVEWX = 1224 | |
| CEFBS_None, // LVSL = 1225 | |
| CEFBS_None, // LVSR = 1226 | |
| CEFBS_None, // LVX = 1227 | |
| CEFBS_None, // LVXL = 1228 | |
| CEFBS_None, // LWA = 1229 | |
| CEFBS_None, // LWARX = 1230 | |
| CEFBS_None, // LWARXL = 1231 | |
| CEFBS_None, // LWAT = 1232 | |
| CEFBS_None, // LWAUX = 1233 | |
| CEFBS_None, // LWAX = 1234 | |
| CEFBS_None, // LWAX_32 = 1235 | |
| CEFBS_None, // LWA_32 = 1236 | |
| CEFBS_None, // LWBRX = 1237 | |
| CEFBS_None, // LWBRX8 = 1238 | |
| CEFBS_None, // LWEPX = 1239 | |
| CEFBS_None, // LWZ = 1240 | |
| CEFBS_None, // LWZ8 = 1241 | |
| CEFBS_None, // LWZCIX = 1242 | |
| CEFBS_None, // LWZU = 1243 | |
| CEFBS_None, // LWZU8 = 1244 | |
| CEFBS_None, // LWZUX = 1245 | |
| CEFBS_None, // LWZUX8 = 1246 | |
| CEFBS_None, // LWZX = 1247 | |
| CEFBS_None, // LWZX8 = 1248 | |
| CEFBS_None, // LWZXTLS = 1249 | |
| CEFBS_None, // LWZXTLS_ = 1250 | |
| CEFBS_None, // LWZXTLS_32 = 1251 | |
| CEFBS_None, // LWZtoc = 1252 | |
| CEFBS_None, // LWZtocL = 1253 | |
| CEFBS_None, // LXSD = 1254 | |
| CEFBS_None, // LXSDX = 1255 | |
| CEFBS_None, // LXSIBZX = 1256 | |
| CEFBS_None, // LXSIHZX = 1257 | |
| CEFBS_None, // LXSIWAX = 1258 | |
| CEFBS_None, // LXSIWZX = 1259 | |
| CEFBS_None, // LXSSP = 1260 | |
| CEFBS_None, // LXSSPX = 1261 | |
| CEFBS_None, // LXV = 1262 | |
| CEFBS_None, // LXVB16X = 1263 | |
| CEFBS_None, // LXVD2X = 1264 | |
| CEFBS_None, // LXVDSX = 1265 | |
| CEFBS_None, // LXVH8X = 1266 | |
| CEFBS_None, // LXVKQ = 1267 | |
| CEFBS_None, // LXVL = 1268 | |
| CEFBS_None, // LXVLL = 1269 | |
| CEFBS_None, // LXVP = 1270 | |
| CEFBS_None, // LXVPRL = 1271 | |
| CEFBS_None, // LXVPRLL = 1272 | |
| CEFBS_None, // LXVPX = 1273 | |
| CEFBS_None, // LXVRBX = 1274 | |
| CEFBS_None, // LXVRDX = 1275 | |
| CEFBS_None, // LXVRHX = 1276 | |
| CEFBS_None, // LXVRL = 1277 | |
| CEFBS_None, // LXVRLL = 1278 | |
| CEFBS_None, // LXVRWX = 1279 | |
| CEFBS_None, // LXVW4X = 1280 | |
| CEFBS_None, // LXVWSX = 1281 | |
| CEFBS_None, // LXVX = 1282 | |
| CEFBS_None, // MADDHD = 1283 | |
| CEFBS_None, // MADDHDU = 1284 | |
| CEFBS_None, // MADDLD = 1285 | |
| CEFBS_None, // MADDLD8 = 1286 | |
| CEFBS_None, // MBAR = 1287 | |
| CEFBS_None, // MCRF = 1288 | |
| CEFBS_None, // MCRFS = 1289 | |
| CEFBS_None, // MCRXRX = 1290 | |
| CEFBS_None, // MFBHRBE = 1291 | |
| CEFBS_None, // MFCR = 1292 | |
| CEFBS_None, // MFCR8 = 1293 | |
| CEFBS_None, // MFCTR = 1294 | |
| CEFBS_None, // MFCTR8 = 1295 | |
| CEFBS_None, // MFDCR = 1296 | |
| CEFBS_None, // MFFS = 1297 | |
| CEFBS_None, // MFFSCDRN = 1298 | |
| CEFBS_None, // MFFSCDRNI = 1299 | |
| CEFBS_None, // MFFSCE = 1300 | |
| CEFBS_None, // MFFSCRN = 1301 | |
| CEFBS_None, // MFFSCRNI = 1302 | |
| CEFBS_None, // MFFSL = 1303 | |
| CEFBS_None, // MFFS_rec = 1304 | |
| CEFBS_None, // MFLR = 1305 | |
| CEFBS_None, // MFLR8 = 1306 | |
| CEFBS_None, // MFMSR = 1307 | |
| CEFBS_None, // MFOCRF = 1308 | |
| CEFBS_None, // MFOCRF8 = 1309 | |
| CEFBS_None, // MFPMR = 1310 | |
| CEFBS_None, // MFSPR = 1311 | |
| CEFBS_None, // MFSPR8 = 1312 | |
| CEFBS_None, // MFSR = 1313 | |
| CEFBS_None, // MFSRIN = 1314 | |
| CEFBS_None, // MFTB = 1315 | |
| CEFBS_None, // MFTB8 = 1316 | |
| CEFBS_None, // MFUDSCR = 1317 | |
| CEFBS_None, // MFVRD = 1318 | |
| CEFBS_None, // MFVRSAVE = 1319 | |
| CEFBS_None, // MFVRSAVEv = 1320 | |
| CEFBS_None, // MFVRWZ = 1321 | |
| CEFBS_None, // MFVSCR = 1322 | |
| CEFBS_None, // MFVSRD = 1323 | |
| CEFBS_None, // MFVSRLD = 1324 | |
| CEFBS_None, // MFVSRWZ = 1325 | |
| CEFBS_None, // MODSD = 1326 | |
| CEFBS_None, // MODSW = 1327 | |
| CEFBS_None, // MODUD = 1328 | |
| CEFBS_None, // MODUW = 1329 | |
| CEFBS_None, // MSGSYNC = 1330 | |
| CEFBS_None, // MSYNC = 1331 | |
| CEFBS_None, // MTCRF = 1332 | |
| CEFBS_None, // MTCRF8 = 1333 | |
| CEFBS_None, // MTCTR = 1334 | |
| CEFBS_None, // MTCTR8 = 1335 | |
| CEFBS_None, // MTCTR8loop = 1336 | |
| CEFBS_None, // MTCTRloop = 1337 | |
| CEFBS_None, // MTDCR = 1338 | |
| CEFBS_None, // MTFSB0 = 1339 | |
| CEFBS_None, // MTFSB1 = 1340 | |
| CEFBS_None, // MTFSF = 1341 | |
| CEFBS_None, // MTFSFI = 1342 | |
| CEFBS_None, // MTFSFI_rec = 1343 | |
| CEFBS_None, // MTFSFIb = 1344 | |
| CEFBS_None, // MTFSF_rec = 1345 | |
| CEFBS_None, // MTFSFb = 1346 | |
| CEFBS_None, // MTLR = 1347 | |
| CEFBS_None, // MTLR8 = 1348 | |
| CEFBS_None, // MTMSR = 1349 | |
| CEFBS_None, // MTMSRD = 1350 | |
| CEFBS_None, // MTOCRF = 1351 | |
| CEFBS_None, // MTOCRF8 = 1352 | |
| CEFBS_None, // MTPMR = 1353 | |
| CEFBS_None, // MTSPR = 1354 | |
| CEFBS_None, // MTSPR8 = 1355 | |
| CEFBS_None, // MTSR = 1356 | |
| CEFBS_None, // MTSRIN = 1357 | |
| CEFBS_None, // MTUDSCR = 1358 | |
| CEFBS_None, // MTVRD = 1359 | |
| CEFBS_None, // MTVRSAVE = 1360 | |
| CEFBS_None, // MTVRSAVEv = 1361 | |
| CEFBS_None, // MTVRWA = 1362 | |
| CEFBS_None, // MTVRWZ = 1363 | |
| CEFBS_None, // MTVSCR = 1364 | |
| CEFBS_None, // MTVSRBM = 1365 | |
| CEFBS_None, // MTVSRBMI = 1366 | |
| CEFBS_None, // MTVSRD = 1367 | |
| CEFBS_None, // MTVSRDD = 1368 | |
| CEFBS_None, // MTVSRDM = 1369 | |
| CEFBS_None, // MTVSRHM = 1370 | |
| CEFBS_None, // MTVSRQM = 1371 | |
| CEFBS_None, // MTVSRWA = 1372 | |
| CEFBS_None, // MTVSRWM = 1373 | |
| CEFBS_None, // MTVSRWS = 1374 | |
| CEFBS_None, // MTVSRWZ = 1375 | |
| CEFBS_None, // MULHD = 1376 | |
| CEFBS_None, // MULHDU = 1377 | |
| CEFBS_None, // MULHDU_rec = 1378 | |
| CEFBS_None, // MULHD_rec = 1379 | |
| CEFBS_None, // MULHW = 1380 | |
| CEFBS_None, // MULHWU = 1381 | |
| CEFBS_None, // MULHWU_rec = 1382 | |
| CEFBS_None, // MULHW_rec = 1383 | |
| CEFBS_None, // MULLD = 1384 | |
| CEFBS_None, // MULLDO = 1385 | |
| CEFBS_None, // MULLDO_rec = 1386 | |
| CEFBS_None, // MULLD_rec = 1387 | |
| CEFBS_None, // MULLI = 1388 | |
| CEFBS_None, // MULLI8 = 1389 | |
| CEFBS_None, // MULLW = 1390 | |
| CEFBS_None, // MULLWO = 1391 | |
| CEFBS_None, // MULLWO_rec = 1392 | |
| CEFBS_None, // MULLW_rec = 1393 | |
| CEFBS_None, // MoveGOTtoLR = 1394 | |
| CEFBS_None, // MovePCtoLR = 1395 | |
| CEFBS_None, // MovePCtoLR8 = 1396 | |
| CEFBS_None, // NAND = 1397 | |
| CEFBS_None, // NAND8 = 1398 | |
| CEFBS_None, // NAND8_rec = 1399 | |
| CEFBS_None, // NAND_rec = 1400 | |
| CEFBS_None, // NAP = 1401 | |
| CEFBS_None, // NEG = 1402 | |
| CEFBS_None, // NEG8 = 1403 | |
| CEFBS_None, // NEG8O = 1404 | |
| CEFBS_None, // NEG8O_rec = 1405 | |
| CEFBS_None, // NEG8_rec = 1406 | |
| CEFBS_None, // NEGO = 1407 | |
| CEFBS_None, // NEGO_rec = 1408 | |
| CEFBS_None, // NEG_rec = 1409 | |
| CEFBS_None, // NOP = 1410 | |
| CEFBS_None, // NOP_GT_PWR6 = 1411 | |
| CEFBS_None, // NOP_GT_PWR7 = 1412 | |
| CEFBS_None, // NOR = 1413 | |
| CEFBS_None, // NOR8 = 1414 | |
| CEFBS_None, // NOR8_rec = 1415 | |
| CEFBS_None, // NOR_rec = 1416 | |
| CEFBS_None, // OR = 1417 | |
| CEFBS_None, // OR8 = 1418 | |
| CEFBS_None, // OR8_rec = 1419 | |
| CEFBS_None, // ORC = 1420 | |
| CEFBS_None, // ORC8 = 1421 | |
| CEFBS_None, // ORC8_rec = 1422 | |
| CEFBS_None, // ORC_rec = 1423 | |
| CEFBS_None, // ORI = 1424 | |
| CEFBS_None, // ORI8 = 1425 | |
| CEFBS_None, // ORIS = 1426 | |
| CEFBS_None, // ORIS8 = 1427 | |
| CEFBS_None, // OR_rec = 1428 | |
| CEFBS_None, // PADDI = 1429 | |
| CEFBS_None, // PADDI8 = 1430 | |
| CEFBS_None, // PADDI8pc = 1431 | |
| CEFBS_None, // PADDIdtprel = 1432 | |
| CEFBS_None, // PADDIpc = 1433 | |
| CEFBS_None, // PDEPD = 1434 | |
| CEFBS_None, // PEXTD = 1435 | |
| CEFBS_None, // PLBZ = 1436 | |
| CEFBS_None, // PLBZ8 = 1437 | |
| CEFBS_None, // PLBZ8pc = 1438 | |
| CEFBS_None, // PLBZpc = 1439 | |
| CEFBS_None, // PLD = 1440 | |
| CEFBS_None, // PLDpc = 1441 | |
| CEFBS_None, // PLFD = 1442 | |
| CEFBS_None, // PLFDpc = 1443 | |
| CEFBS_None, // PLFS = 1444 | |
| CEFBS_None, // PLFSpc = 1445 | |
| CEFBS_None, // PLHA = 1446 | |
| CEFBS_None, // PLHA8 = 1447 | |
| CEFBS_None, // PLHA8pc = 1448 | |
| CEFBS_None, // PLHApc = 1449 | |
| CEFBS_None, // PLHZ = 1450 | |
| CEFBS_None, // PLHZ8 = 1451 | |
| CEFBS_None, // PLHZ8pc = 1452 | |
| CEFBS_None, // PLHZpc = 1453 | |
| CEFBS_None, // PLI = 1454 | |
| CEFBS_None, // PLI8 = 1455 | |
| CEFBS_None, // PLWA = 1456 | |
| CEFBS_None, // PLWA8 = 1457 | |
| CEFBS_None, // PLWA8pc = 1458 | |
| CEFBS_None, // PLWApc = 1459 | |
| CEFBS_None, // PLWZ = 1460 | |
| CEFBS_None, // PLWZ8 = 1461 | |
| CEFBS_None, // PLWZ8pc = 1462 | |
| CEFBS_None, // PLWZpc = 1463 | |
| CEFBS_None, // PLXSD = 1464 | |
| CEFBS_None, // PLXSDpc = 1465 | |
| CEFBS_None, // PLXSSP = 1466 | |
| CEFBS_None, // PLXSSPpc = 1467 | |
| CEFBS_None, // PLXV = 1468 | |
| CEFBS_None, // PLXVP = 1469 | |
| CEFBS_None, // PLXVPpc = 1470 | |
| CEFBS_None, // PLXVpc = 1471 | |
| CEFBS_None, // PMXVBF16GER2 = 1472 | |
| CEFBS_None, // PMXVBF16GER2NN = 1473 | |
| CEFBS_None, // PMXVBF16GER2NP = 1474 | |
| CEFBS_None, // PMXVBF16GER2PN = 1475 | |
| CEFBS_None, // PMXVBF16GER2PP = 1476 | |
| CEFBS_None, // PMXVBF16GER2W = 1477 | |
| CEFBS_None, // PMXVBF16GER2WNN = 1478 | |
| CEFBS_None, // PMXVBF16GER2WNP = 1479 | |
| CEFBS_None, // PMXVBF16GER2WPN = 1480 | |
| CEFBS_None, // PMXVBF16GER2WPP = 1481 | |
| CEFBS_None, // PMXVF16GER2 = 1482 | |
| CEFBS_None, // PMXVF16GER2NN = 1483 | |
| CEFBS_None, // PMXVF16GER2NP = 1484 | |
| CEFBS_None, // PMXVF16GER2PN = 1485 | |
| CEFBS_None, // PMXVF16GER2PP = 1486 | |
| CEFBS_None, // PMXVF16GER2W = 1487 | |
| CEFBS_None, // PMXVF16GER2WNN = 1488 | |
| CEFBS_None, // PMXVF16GER2WNP = 1489 | |
| CEFBS_None, // PMXVF16GER2WPN = 1490 | |
| CEFBS_None, // PMXVF16GER2WPP = 1491 | |
| CEFBS_None, // PMXVF32GER = 1492 | |
| CEFBS_None, // PMXVF32GERNN = 1493 | |
| CEFBS_None, // PMXVF32GERNP = 1494 | |
| CEFBS_None, // PMXVF32GERPN = 1495 | |
| CEFBS_None, // PMXVF32GERPP = 1496 | |
| CEFBS_None, // PMXVF32GERW = 1497 | |
| CEFBS_None, // PMXVF32GERWNN = 1498 | |
| CEFBS_None, // PMXVF32GERWNP = 1499 | |
| CEFBS_None, // PMXVF32GERWPN = 1500 | |
| CEFBS_None, // PMXVF32GERWPP = 1501 | |
| CEFBS_None, // PMXVF64GER = 1502 | |
| CEFBS_None, // PMXVF64GERNN = 1503 | |
| CEFBS_None, // PMXVF64GERNP = 1504 | |
| CEFBS_None, // PMXVF64GERPN = 1505 | |
| CEFBS_None, // PMXVF64GERPP = 1506 | |
| CEFBS_None, // PMXVF64GERW = 1507 | |
| CEFBS_None, // PMXVF64GERWNN = 1508 | |
| CEFBS_None, // PMXVF64GERWNP = 1509 | |
| CEFBS_None, // PMXVF64GERWPN = 1510 | |
| CEFBS_None, // PMXVF64GERWPP = 1511 | |
| CEFBS_None, // PMXVI16GER2 = 1512 | |
| CEFBS_None, // PMXVI16GER2PP = 1513 | |
| CEFBS_None, // PMXVI16GER2S = 1514 | |
| CEFBS_None, // PMXVI16GER2SPP = 1515 | |
| CEFBS_None, // PMXVI16GER2SW = 1516 | |
| CEFBS_None, // PMXVI16GER2SWPP = 1517 | |
| CEFBS_None, // PMXVI16GER2W = 1518 | |
| CEFBS_None, // PMXVI16GER2WPP = 1519 | |
| CEFBS_None, // PMXVI4GER8 = 1520 | |
| CEFBS_None, // PMXVI4GER8PP = 1521 | |
| CEFBS_None, // PMXVI4GER8W = 1522 | |
| CEFBS_None, // PMXVI4GER8WPP = 1523 | |
| CEFBS_None, // PMXVI8GER4 = 1524 | |
| CEFBS_None, // PMXVI8GER4PP = 1525 | |
| CEFBS_None, // PMXVI8GER4SPP = 1526 | |
| CEFBS_None, // PMXVI8GER4W = 1527 | |
| CEFBS_None, // PMXVI8GER4WPP = 1528 | |
| CEFBS_None, // PMXVI8GER4WSPP = 1529 | |
| CEFBS_None, // POPCNTB = 1530 | |
| CEFBS_None, // POPCNTB8 = 1531 | |
| CEFBS_None, // POPCNTD = 1532 | |
| CEFBS_None, // POPCNTW = 1533 | |
| CEFBS_None, // PPC32GOT = 1534 | |
| CEFBS_None, // PPC32PICGOT = 1535 | |
| CEFBS_None, // PREPARE_PROBED_ALLOCA_32 = 1536 | |
| CEFBS_None, // PREPARE_PROBED_ALLOCA_64 = 1537 | |
| CEFBS_None, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 = 1538 | |
| CEFBS_None, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 = 1539 | |
| CEFBS_None, // PROBED_ALLOCA_32 = 1540 | |
| CEFBS_None, // PROBED_ALLOCA_64 = 1541 | |
| CEFBS_None, // PROBED_STACKALLOC_32 = 1542 | |
| CEFBS_None, // PROBED_STACKALLOC_64 = 1543 | |
| CEFBS_None, // PSTB = 1544 | |
| CEFBS_None, // PSTB8 = 1545 | |
| CEFBS_None, // PSTB8pc = 1546 | |
| CEFBS_None, // PSTBpc = 1547 | |
| CEFBS_None, // PSTD = 1548 | |
| CEFBS_None, // PSTDpc = 1549 | |
| CEFBS_None, // PSTFD = 1550 | |
| CEFBS_None, // PSTFDpc = 1551 | |
| CEFBS_None, // PSTFS = 1552 | |
| CEFBS_None, // PSTFSpc = 1553 | |
| CEFBS_None, // PSTH = 1554 | |
| CEFBS_None, // PSTH8 = 1555 | |
| CEFBS_None, // PSTH8pc = 1556 | |
| CEFBS_None, // PSTHpc = 1557 | |
| CEFBS_None, // PSTW = 1558 | |
| CEFBS_None, // PSTW8 = 1559 | |
| CEFBS_None, // PSTW8pc = 1560 | |
| CEFBS_None, // PSTWpc = 1561 | |
| CEFBS_None, // PSTXSD = 1562 | |
| CEFBS_None, // PSTXSDpc = 1563 | |
| CEFBS_None, // PSTXSSP = 1564 | |
| CEFBS_None, // PSTXSSPpc = 1565 | |
| CEFBS_None, // PSTXV = 1566 | |
| CEFBS_None, // PSTXVP = 1567 | |
| CEFBS_None, // PSTXVPpc = 1568 | |
| CEFBS_None, // PSTXVpc = 1569 | |
| CEFBS_None, // PseudoEIEIO = 1570 | |
| CEFBS_None, // RESTORE_ACC = 1571 | |
| CEFBS_None, // RESTORE_CR = 1572 | |
| CEFBS_None, // RESTORE_CRBIT = 1573 | |
| CEFBS_None, // RESTORE_QUADWORD = 1574 | |
| CEFBS_None, // RESTORE_UACC = 1575 | |
| CEFBS_None, // RESTORE_WACC = 1576 | |
| CEFBS_None, // RFCI = 1577 | |
| CEFBS_None, // RFDI = 1578 | |
| CEFBS_None, // RFEBB = 1579 | |
| CEFBS_None, // RFI = 1580 | |
| CEFBS_None, // RFID = 1581 | |
| CEFBS_None, // RFMCI = 1582 | |
| CEFBS_None, // RLDCL = 1583 | |
| CEFBS_None, // RLDCL_rec = 1584 | |
| CEFBS_None, // RLDCR = 1585 | |
| CEFBS_None, // RLDCR_rec = 1586 | |
| CEFBS_None, // RLDIC = 1587 | |
| CEFBS_None, // RLDICL = 1588 | |
| CEFBS_None, // RLDICL_32 = 1589 | |
| CEFBS_None, // RLDICL_32_64 = 1590 | |
| CEFBS_None, // RLDICL_32_rec = 1591 | |
| CEFBS_None, // RLDICL_rec = 1592 | |
| CEFBS_None, // RLDICR = 1593 | |
| CEFBS_None, // RLDICR_32 = 1594 | |
| CEFBS_None, // RLDICR_rec = 1595 | |
| CEFBS_None, // RLDIC_rec = 1596 | |
| CEFBS_None, // RLDIMI = 1597 | |
| CEFBS_None, // RLDIMI_rec = 1598 | |
| CEFBS_None, // RLWIMI = 1599 | |
| CEFBS_None, // RLWIMI8 = 1600 | |
| CEFBS_None, // RLWIMI8_rec = 1601 | |
| CEFBS_None, // RLWIMI_rec = 1602 | |
| CEFBS_None, // RLWINM = 1603 | |
| CEFBS_None, // RLWINM8 = 1604 | |
| CEFBS_None, // RLWINM8_rec = 1605 | |
| CEFBS_None, // RLWINM_rec = 1606 | |
| CEFBS_None, // RLWNM = 1607 | |
| CEFBS_None, // RLWNM8 = 1608 | |
| CEFBS_None, // RLWNM8_rec = 1609 | |
| CEFBS_None, // RLWNM_rec = 1610 | |
| CEFBS_None, // ReadTB = 1611 | |
| CEFBS_None, // SC = 1612 | |
| CEFBS_None, // SELECT_CC_F16 = 1613 | |
| CEFBS_None, // SELECT_CC_F4 = 1614 | |
| CEFBS_None, // SELECT_CC_F8 = 1615 | |
| CEFBS_None, // SELECT_CC_I4 = 1616 | |
| CEFBS_None, // SELECT_CC_I8 = 1617 | |
| CEFBS_None, // SELECT_CC_SPE = 1618 | |
| CEFBS_None, // SELECT_CC_SPE4 = 1619 | |
| CEFBS_None, // SELECT_CC_VRRC = 1620 | |
| CEFBS_None, // SELECT_CC_VSFRC = 1621 | |
| CEFBS_None, // SELECT_CC_VSRC = 1622 | |
| CEFBS_None, // SELECT_CC_VSSRC = 1623 | |
| CEFBS_None, // SELECT_F16 = 1624 | |
| CEFBS_None, // SELECT_F4 = 1625 | |
| CEFBS_None, // SELECT_F8 = 1626 | |
| CEFBS_None, // SELECT_I4 = 1627 | |
| CEFBS_None, // SELECT_I8 = 1628 | |
| CEFBS_None, // SELECT_SPE = 1629 | |
| CEFBS_None, // SELECT_SPE4 = 1630 | |
| CEFBS_None, // SELECT_VRRC = 1631 | |
| CEFBS_None, // SELECT_VSFRC = 1632 | |
| CEFBS_None, // SELECT_VSRC = 1633 | |
| CEFBS_None, // SELECT_VSSRC = 1634 | |
| CEFBS_None, // SETB = 1635 | |
| CEFBS_None, // SETB8 = 1636 | |
| CEFBS_None, // SETBC = 1637 | |
| CEFBS_None, // SETBC8 = 1638 | |
| CEFBS_None, // SETBCR = 1639 | |
| CEFBS_None, // SETBCR8 = 1640 | |
| CEFBS_None, // SETFLM = 1641 | |
| CEFBS_None, // SETNBC = 1642 | |
| CEFBS_None, // SETNBC8 = 1643 | |
| CEFBS_None, // SETNBCR = 1644 | |
| CEFBS_None, // SETNBCR8 = 1645 | |
| CEFBS_None, // SETRND = 1646 | |
| CEFBS_None, // SETRNDi = 1647 | |
| CEFBS_None, // SLBFEE_rec = 1648 | |
| CEFBS_None, // SLBIA = 1649 | |
| CEFBS_None, // SLBIE = 1650 | |
| CEFBS_None, // SLBIEG = 1651 | |
| CEFBS_None, // SLBMFEE = 1652 | |
| CEFBS_None, // SLBMFEV = 1653 | |
| CEFBS_None, // SLBMTE = 1654 | |
| CEFBS_None, // SLBSYNC = 1655 | |
| CEFBS_None, // SLD = 1656 | |
| CEFBS_None, // SLD_rec = 1657 | |
| CEFBS_None, // SLW = 1658 | |
| CEFBS_None, // SLW8 = 1659 | |
| CEFBS_None, // SLW8_rec = 1660 | |
| CEFBS_None, // SLW_rec = 1661 | |
| CEFBS_None, // SPELWZ = 1662 | |
| CEFBS_None, // SPELWZX = 1663 | |
| CEFBS_None, // SPESTW = 1664 | |
| CEFBS_None, // SPESTWX = 1665 | |
| CEFBS_None, // SPILL_ACC = 1666 | |
| CEFBS_None, // SPILL_CR = 1667 | |
| CEFBS_None, // SPILL_CRBIT = 1668 | |
| CEFBS_None, // SPILL_QUADWORD = 1669 | |
| CEFBS_None, // SPILL_UACC = 1670 | |
| CEFBS_None, // SPILL_WACC = 1671 | |
| CEFBS_None, // SPLIT_QUADWORD = 1672 | |
| CEFBS_None, // SRAD = 1673 | |
| CEFBS_None, // SRADI = 1674 | |
| CEFBS_None, // SRADI_32 = 1675 | |
| CEFBS_None, // SRADI_rec = 1676 | |
| CEFBS_None, // SRAD_rec = 1677 | |
| CEFBS_None, // SRAW = 1678 | |
| CEFBS_None, // SRAWI = 1679 | |
| CEFBS_None, // SRAWI_rec = 1680 | |
| CEFBS_None, // SRAW_rec = 1681 | |
| CEFBS_None, // SRD = 1682 | |
| CEFBS_None, // SRD_rec = 1683 | |
| CEFBS_None, // SRW = 1684 | |
| CEFBS_None, // SRW8 = 1685 | |
| CEFBS_None, // SRW8_rec = 1686 | |
| CEFBS_None, // SRW_rec = 1687 | |
| CEFBS_None, // STB = 1688 | |
| CEFBS_None, // STB8 = 1689 | |
| CEFBS_None, // STBCIX = 1690 | |
| CEFBS_None, // STBCX = 1691 | |
| CEFBS_None, // STBEPX = 1692 | |
| CEFBS_None, // STBU = 1693 | |
| CEFBS_None, // STBU8 = 1694 | |
| CEFBS_None, // STBUX = 1695 | |
| CEFBS_None, // STBUX8 = 1696 | |
| CEFBS_None, // STBX = 1697 | |
| CEFBS_None, // STBX8 = 1698 | |
| CEFBS_None, // STBXTLS = 1699 | |
| CEFBS_None, // STBXTLS_ = 1700 | |
| CEFBS_None, // STBXTLS_32 = 1701 | |
| CEFBS_None, // STD = 1702 | |
| CEFBS_None, // STDAT = 1703 | |
| CEFBS_None, // STDBRX = 1704 | |
| CEFBS_None, // STDCIX = 1705 | |
| CEFBS_None, // STDCX = 1706 | |
| CEFBS_None, // STDU = 1707 | |
| CEFBS_None, // STDUX = 1708 | |
| CEFBS_None, // STDX = 1709 | |
| CEFBS_None, // STDXTLS = 1710 | |
| CEFBS_None, // STDXTLS_ = 1711 | |
| CEFBS_None, // STFD = 1712 | |
| CEFBS_None, // STFDEPX = 1713 | |
| CEFBS_None, // STFDU = 1714 | |
| CEFBS_None, // STFDUX = 1715 | |
| CEFBS_None, // STFDX = 1716 | |
| CEFBS_None, // STFIWX = 1717 | |
| CEFBS_None, // STFS = 1718 | |
| CEFBS_None, // STFSU = 1719 | |
| CEFBS_None, // STFSUX = 1720 | |
| CEFBS_None, // STFSX = 1721 | |
| CEFBS_None, // STH = 1722 | |
| CEFBS_None, // STH8 = 1723 | |
| CEFBS_None, // STHBRX = 1724 | |
| CEFBS_None, // STHCIX = 1725 | |
| CEFBS_None, // STHCX = 1726 | |
| CEFBS_None, // STHEPX = 1727 | |
| CEFBS_None, // STHU = 1728 | |
| CEFBS_None, // STHU8 = 1729 | |
| CEFBS_None, // STHUX = 1730 | |
| CEFBS_None, // STHUX8 = 1731 | |
| CEFBS_None, // STHX = 1732 | |
| CEFBS_None, // STHX8 = 1733 | |
| CEFBS_None, // STHXTLS = 1734 | |
| CEFBS_None, // STHXTLS_ = 1735 | |
| CEFBS_None, // STHXTLS_32 = 1736 | |
| CEFBS_None, // STMW = 1737 | |
| CEFBS_None, // STOP = 1738 | |
| CEFBS_None, // STQ = 1739 | |
| CEFBS_None, // STQCX = 1740 | |
| CEFBS_None, // STQX_PSEUDO = 1741 | |
| CEFBS_None, // STSWI = 1742 | |
| CEFBS_None, // STVEBX = 1743 | |
| CEFBS_None, // STVEHX = 1744 | |
| CEFBS_None, // STVEWX = 1745 | |
| CEFBS_None, // STVX = 1746 | |
| CEFBS_None, // STVXL = 1747 | |
| CEFBS_None, // STW = 1748 | |
| CEFBS_None, // STW8 = 1749 | |
| CEFBS_None, // STWAT = 1750 | |
| CEFBS_None, // STWBRX = 1751 | |
| CEFBS_None, // STWCIX = 1752 | |
| CEFBS_None, // STWCX = 1753 | |
| CEFBS_None, // STWEPX = 1754 | |
| CEFBS_None, // STWU = 1755 | |
| CEFBS_None, // STWU8 = 1756 | |
| CEFBS_None, // STWUX = 1757 | |
| CEFBS_None, // STWUX8 = 1758 | |
| CEFBS_None, // STWX = 1759 | |
| CEFBS_None, // STWX8 = 1760 | |
| CEFBS_None, // STWXTLS = 1761 | |
| CEFBS_None, // STWXTLS_ = 1762 | |
| CEFBS_None, // STWXTLS_32 = 1763 | |
| CEFBS_None, // STXSD = 1764 | |
| CEFBS_None, // STXSDX = 1765 | |
| CEFBS_None, // STXSIBX = 1766 | |
| CEFBS_None, // STXSIBXv = 1767 | |
| CEFBS_None, // STXSIHX = 1768 | |
| CEFBS_None, // STXSIHXv = 1769 | |
| CEFBS_None, // STXSIWX = 1770 | |
| CEFBS_None, // STXSSP = 1771 | |
| CEFBS_None, // STXSSPX = 1772 | |
| CEFBS_None, // STXV = 1773 | |
| CEFBS_None, // STXVB16X = 1774 | |
| CEFBS_None, // STXVD2X = 1775 | |
| CEFBS_None, // STXVH8X = 1776 | |
| CEFBS_None, // STXVL = 1777 | |
| CEFBS_None, // STXVLL = 1778 | |
| CEFBS_None, // STXVP = 1779 | |
| CEFBS_None, // STXVPRL = 1780 | |
| CEFBS_None, // STXVPRLL = 1781 | |
| CEFBS_None, // STXVPX = 1782 | |
| CEFBS_None, // STXVRBX = 1783 | |
| CEFBS_None, // STXVRDX = 1784 | |
| CEFBS_None, // STXVRHX = 1785 | |
| CEFBS_None, // STXVRL = 1786 | |
| CEFBS_None, // STXVRLL = 1787 | |
| CEFBS_None, // STXVRWX = 1788 | |
| CEFBS_None, // STXVW4X = 1789 | |
| CEFBS_None, // STXVX = 1790 | |
| CEFBS_None, // SUBF = 1791 | |
| CEFBS_None, // SUBF8 = 1792 | |
| CEFBS_None, // SUBF8O = 1793 | |
| CEFBS_None, // SUBF8O_rec = 1794 | |
| CEFBS_None, // SUBF8_rec = 1795 | |
| CEFBS_None, // SUBFC = 1796 | |
| CEFBS_None, // SUBFC8 = 1797 | |
| CEFBS_None, // SUBFC8O = 1798 | |
| CEFBS_None, // SUBFC8O_rec = 1799 | |
| CEFBS_None, // SUBFC8_rec = 1800 | |
| CEFBS_None, // SUBFCO = 1801 | |
| CEFBS_None, // SUBFCO_rec = 1802 | |
| CEFBS_None, // SUBFC_rec = 1803 | |
| CEFBS_None, // SUBFE = 1804 | |
| CEFBS_None, // SUBFE8 = 1805 | |
| CEFBS_None, // SUBFE8O = 1806 | |
| CEFBS_None, // SUBFE8O_rec = 1807 | |
| CEFBS_None, // SUBFE8_rec = 1808 | |
| CEFBS_None, // SUBFEO = 1809 | |
| CEFBS_None, // SUBFEO_rec = 1810 | |
| CEFBS_None, // SUBFE_rec = 1811 | |
| CEFBS_None, // SUBFIC = 1812 | |
| CEFBS_None, // SUBFIC8 = 1813 | |
| CEFBS_None, // SUBFME = 1814 | |
| CEFBS_None, // SUBFME8 = 1815 | |
| CEFBS_None, // SUBFME8O = 1816 | |
| CEFBS_None, // SUBFME8O_rec = 1817 | |
| CEFBS_None, // SUBFME8_rec = 1818 | |
| CEFBS_None, // SUBFMEO = 1819 | |
| CEFBS_None, // SUBFMEO_rec = 1820 | |
| CEFBS_None, // SUBFME_rec = 1821 | |
| CEFBS_None, // SUBFO = 1822 | |
| CEFBS_None, // SUBFO_rec = 1823 | |
| CEFBS_None, // SUBFUS = 1824 | |
| CEFBS_None, // SUBFUS_rec = 1825 | |
| CEFBS_None, // SUBFZE = 1826 | |
| CEFBS_None, // SUBFZE8 = 1827 | |
| CEFBS_None, // SUBFZE8O = 1828 | |
| CEFBS_None, // SUBFZE8O_rec = 1829 | |
| CEFBS_None, // SUBFZE8_rec = 1830 | |
| CEFBS_None, // SUBFZEO = 1831 | |
| CEFBS_None, // SUBFZEO_rec = 1832 | |
| CEFBS_None, // SUBFZE_rec = 1833 | |
| CEFBS_None, // SUBF_rec = 1834 | |
| CEFBS_None, // SYNC = 1835 | |
| CEFBS_None, // TABORT = 1836 | |
| CEFBS_None, // TABORTDC = 1837 | |
| CEFBS_None, // TABORTDCI = 1838 | |
| CEFBS_None, // TABORTWC = 1839 | |
| CEFBS_None, // TABORTWCI = 1840 | |
| CEFBS_None, // TAILB = 1841 | |
| CEFBS_None, // TAILB8 = 1842 | |
| CEFBS_None, // TAILBA = 1843 | |
| CEFBS_None, // TAILBA8 = 1844 | |
| CEFBS_None, // TAILBCTR = 1845 | |
| CEFBS_None, // TAILBCTR8 = 1846 | |
| CEFBS_None, // TBEGIN = 1847 | |
| CEFBS_None, // TBEGIN_RET = 1848 | |
| CEFBS_None, // TCHECK = 1849 | |
| CEFBS_None, // TCHECK_RET = 1850 | |
| CEFBS_None, // TCRETURNai = 1851 | |
| CEFBS_None, // TCRETURNai8 = 1852 | |
| CEFBS_None, // TCRETURNdi = 1853 | |
| CEFBS_None, // TCRETURNdi8 = 1854 | |
| CEFBS_None, // TCRETURNri = 1855 | |
| CEFBS_None, // TCRETURNri8 = 1856 | |
| CEFBS_None, // TD = 1857 | |
| CEFBS_None, // TDI = 1858 | |
| CEFBS_None, // TEND = 1859 | |
| CEFBS_None, // TLBIA = 1860 | |
| CEFBS_None, // TLBIE = 1861 | |
| CEFBS_None, // TLBIEL = 1862 | |
| CEFBS_None, // TLBIVAX = 1863 | |
| CEFBS_None, // TLBLD = 1864 | |
| CEFBS_None, // TLBLI = 1865 | |
| CEFBS_None, // TLBRE = 1866 | |
| CEFBS_None, // TLBRE2 = 1867 | |
| CEFBS_None, // TLBSX = 1868 | |
| CEFBS_None, // TLBSX2 = 1869 | |
| CEFBS_None, // TLBSX2D = 1870 | |
| CEFBS_None, // TLBSYNC = 1871 | |
| CEFBS_None, // TLBWE = 1872 | |
| CEFBS_None, // TLBWE2 = 1873 | |
| CEFBS_None, // TLSGDAIX = 1874 | |
| CEFBS_None, // TLSGDAIX8 = 1875 | |
| CEFBS_None, // TRAP = 1876 | |
| CEFBS_None, // TRECHKPT = 1877 | |
| CEFBS_None, // TRECLAIM = 1878 | |
| CEFBS_None, // TSR = 1879 | |
| CEFBS_None, // TW = 1880 | |
| CEFBS_None, // TWI = 1881 | |
| CEFBS_None, // UNENCODED_NOP = 1882 | |
| CEFBS_None, // UpdateGBR = 1883 | |
| CEFBS_None, // VABSDUB = 1884 | |
| CEFBS_None, // VABSDUH = 1885 | |
| CEFBS_None, // VABSDUW = 1886 | |
| CEFBS_None, // VADDCUQ = 1887 | |
| CEFBS_None, // VADDCUW = 1888 | |
| CEFBS_None, // VADDECUQ = 1889 | |
| CEFBS_None, // VADDEUQM = 1890 | |
| CEFBS_None, // VADDFP = 1891 | |
| CEFBS_None, // VADDSBS = 1892 | |
| CEFBS_None, // VADDSHS = 1893 | |
| CEFBS_None, // VADDSWS = 1894 | |
| CEFBS_None, // VADDUBM = 1895 | |
| CEFBS_None, // VADDUBS = 1896 | |
| CEFBS_None, // VADDUDM = 1897 | |
| CEFBS_None, // VADDUHM = 1898 | |
| CEFBS_None, // VADDUHS = 1899 | |
| CEFBS_None, // VADDUQM = 1900 | |
| CEFBS_None, // VADDUWM = 1901 | |
| CEFBS_None, // VADDUWS = 1902 | |
| CEFBS_None, // VAND = 1903 | |
| CEFBS_None, // VANDC = 1904 | |
| CEFBS_None, // VAVGSB = 1905 | |
| CEFBS_None, // VAVGSH = 1906 | |
| CEFBS_None, // VAVGSW = 1907 | |
| CEFBS_None, // VAVGUB = 1908 | |
| CEFBS_None, // VAVGUH = 1909 | |
| CEFBS_None, // VAVGUW = 1910 | |
| CEFBS_None, // VBPERMD = 1911 | |
| CEFBS_None, // VBPERMQ = 1912 | |
| CEFBS_None, // VCFSX = 1913 | |
| CEFBS_None, // VCFSX_0 = 1914 | |
| CEFBS_None, // VCFUGED = 1915 | |
| CEFBS_None, // VCFUX = 1916 | |
| CEFBS_None, // VCFUX_0 = 1917 | |
| CEFBS_None, // VCIPHER = 1918 | |
| CEFBS_None, // VCIPHERLAST = 1919 | |
| CEFBS_None, // VCLRLB = 1920 | |
| CEFBS_None, // VCLRRB = 1921 | |
| CEFBS_None, // VCLZB = 1922 | |
| CEFBS_None, // VCLZD = 1923 | |
| CEFBS_None, // VCLZDM = 1924 | |
| CEFBS_None, // VCLZH = 1925 | |
| CEFBS_None, // VCLZLSBB = 1926 | |
| CEFBS_None, // VCLZW = 1927 | |
| CEFBS_None, // VCMPBFP = 1928 | |
| CEFBS_None, // VCMPBFP_rec = 1929 | |
| CEFBS_None, // VCMPEQFP = 1930 | |
| CEFBS_None, // VCMPEQFP_rec = 1931 | |
| CEFBS_None, // VCMPEQUB = 1932 | |
| CEFBS_None, // VCMPEQUB_rec = 1933 | |
| CEFBS_None, // VCMPEQUD = 1934 | |
| CEFBS_None, // VCMPEQUD_rec = 1935 | |
| CEFBS_None, // VCMPEQUH = 1936 | |
| CEFBS_None, // VCMPEQUH_rec = 1937 | |
| CEFBS_None, // VCMPEQUQ = 1938 | |
| CEFBS_None, // VCMPEQUQ_rec = 1939 | |
| CEFBS_None, // VCMPEQUW = 1940 | |
| CEFBS_None, // VCMPEQUW_rec = 1941 | |
| CEFBS_None, // VCMPGEFP = 1942 | |
| CEFBS_None, // VCMPGEFP_rec = 1943 | |
| CEFBS_None, // VCMPGTFP = 1944 | |
| CEFBS_None, // VCMPGTFP_rec = 1945 | |
| CEFBS_None, // VCMPGTSB = 1946 | |
| CEFBS_None, // VCMPGTSB_rec = 1947 | |
| CEFBS_None, // VCMPGTSD = 1948 | |
| CEFBS_None, // VCMPGTSD_rec = 1949 | |
| CEFBS_None, // VCMPGTSH = 1950 | |
| CEFBS_None, // VCMPGTSH_rec = 1951 | |
| CEFBS_None, // VCMPGTSQ = 1952 | |
| CEFBS_None, // VCMPGTSQ_rec = 1953 | |
| CEFBS_None, // VCMPGTSW = 1954 | |
| CEFBS_None, // VCMPGTSW_rec = 1955 | |
| CEFBS_None, // VCMPGTUB = 1956 | |
| CEFBS_None, // VCMPGTUB_rec = 1957 | |
| CEFBS_None, // VCMPGTUD = 1958 | |
| CEFBS_None, // VCMPGTUD_rec = 1959 | |
| CEFBS_None, // VCMPGTUH = 1960 | |
| CEFBS_None, // VCMPGTUH_rec = 1961 | |
| CEFBS_None, // VCMPGTUQ = 1962 | |
| CEFBS_None, // VCMPGTUQ_rec = 1963 | |
| CEFBS_None, // VCMPGTUW = 1964 | |
| CEFBS_None, // VCMPGTUW_rec = 1965 | |
| CEFBS_None, // VCMPNEB = 1966 | |
| CEFBS_None, // VCMPNEB_rec = 1967 | |
| CEFBS_None, // VCMPNEH = 1968 | |
| CEFBS_None, // VCMPNEH_rec = 1969 | |
| CEFBS_None, // VCMPNEW = 1970 | |
| CEFBS_None, // VCMPNEW_rec = 1971 | |
| CEFBS_None, // VCMPNEZB = 1972 | |
| CEFBS_None, // VCMPNEZB_rec = 1973 | |
| CEFBS_None, // VCMPNEZH = 1974 | |
| CEFBS_None, // VCMPNEZH_rec = 1975 | |
| CEFBS_None, // VCMPNEZW = 1976 | |
| CEFBS_None, // VCMPNEZW_rec = 1977 | |
| CEFBS_None, // VCMPSQ = 1978 | |
| CEFBS_None, // VCMPUQ = 1979 | |
| CEFBS_None, // VCNTMBB = 1980 | |
| CEFBS_None, // VCNTMBD = 1981 | |
| CEFBS_None, // VCNTMBH = 1982 | |
| CEFBS_None, // VCNTMBW = 1983 | |
| CEFBS_None, // VCTSXS = 1984 | |
| CEFBS_None, // VCTSXS_0 = 1985 | |
| CEFBS_None, // VCTUXS = 1986 | |
| CEFBS_None, // VCTUXS_0 = 1987 | |
| CEFBS_None, // VCTZB = 1988 | |
| CEFBS_None, // VCTZD = 1989 | |
| CEFBS_None, // VCTZDM = 1990 | |
| CEFBS_None, // VCTZH = 1991 | |
| CEFBS_None, // VCTZLSBB = 1992 | |
| CEFBS_None, // VCTZW = 1993 | |
| CEFBS_None, // VDIVESD = 1994 | |
| CEFBS_None, // VDIVESQ = 1995 | |
| CEFBS_None, // VDIVESW = 1996 | |
| CEFBS_None, // VDIVEUD = 1997 | |
| CEFBS_None, // VDIVEUQ = 1998 | |
| CEFBS_None, // VDIVEUW = 1999 | |
| CEFBS_None, // VDIVSD = 2000 | |
| CEFBS_None, // VDIVSQ = 2001 | |
| CEFBS_None, // VDIVSW = 2002 | |
| CEFBS_None, // VDIVUD = 2003 | |
| CEFBS_None, // VDIVUQ = 2004 | |
| CEFBS_None, // VDIVUW = 2005 | |
| CEFBS_None, // VEQV = 2006 | |
| CEFBS_None, // VEXPANDBM = 2007 | |
| CEFBS_None, // VEXPANDDM = 2008 | |
| CEFBS_None, // VEXPANDHM = 2009 | |
| CEFBS_None, // VEXPANDQM = 2010 | |
| CEFBS_None, // VEXPANDWM = 2011 | |
| CEFBS_None, // VEXPTEFP = 2012 | |
| CEFBS_None, // VEXTDDVLX = 2013 | |
| CEFBS_None, // VEXTDDVRX = 2014 | |
| CEFBS_None, // VEXTDUBVLX = 2015 | |
| CEFBS_None, // VEXTDUBVRX = 2016 | |
| CEFBS_None, // VEXTDUHVLX = 2017 | |
| CEFBS_None, // VEXTDUHVRX = 2018 | |
| CEFBS_None, // VEXTDUWVLX = 2019 | |
| CEFBS_None, // VEXTDUWVRX = 2020 | |
| CEFBS_None, // VEXTRACTBM = 2021 | |
| CEFBS_None, // VEXTRACTD = 2022 | |
| CEFBS_None, // VEXTRACTDM = 2023 | |
| CEFBS_None, // VEXTRACTHM = 2024 | |
| CEFBS_None, // VEXTRACTQM = 2025 | |
| CEFBS_None, // VEXTRACTUB = 2026 | |
| CEFBS_None, // VEXTRACTUH = 2027 | |
| CEFBS_None, // VEXTRACTUW = 2028 | |
| CEFBS_None, // VEXTRACTWM = 2029 | |
| CEFBS_None, // VEXTSB2D = 2030 | |
| CEFBS_None, // VEXTSB2Ds = 2031 | |
| CEFBS_None, // VEXTSB2W = 2032 | |
| CEFBS_None, // VEXTSB2Ws = 2033 | |
| CEFBS_None, // VEXTSD2Q = 2034 | |
| CEFBS_None, // VEXTSH2D = 2035 | |
| CEFBS_None, // VEXTSH2Ds = 2036 | |
| CEFBS_None, // VEXTSH2W = 2037 | |
| CEFBS_None, // VEXTSH2Ws = 2038 | |
| CEFBS_None, // VEXTSW2D = 2039 | |
| CEFBS_None, // VEXTSW2Ds = 2040 | |
| CEFBS_None, // VEXTUBLX = 2041 | |
| CEFBS_None, // VEXTUBRX = 2042 | |
| CEFBS_None, // VEXTUHLX = 2043 | |
| CEFBS_None, // VEXTUHRX = 2044 | |
| CEFBS_None, // VEXTUWLX = 2045 | |
| CEFBS_None, // VEXTUWRX = 2046 | |
| CEFBS_None, // VGBBD = 2047 | |
| CEFBS_None, // VGNB = 2048 | |
| CEFBS_None, // VINSBLX = 2049 | |
| CEFBS_None, // VINSBRX = 2050 | |
| CEFBS_None, // VINSBVLX = 2051 | |
| CEFBS_None, // VINSBVRX = 2052 | |
| CEFBS_None, // VINSD = 2053 | |
| CEFBS_None, // VINSDLX = 2054 | |
| CEFBS_None, // VINSDRX = 2055 | |
| CEFBS_None, // VINSERTB = 2056 | |
| CEFBS_None, // VINSERTD = 2057 | |
| CEFBS_None, // VINSERTH = 2058 | |
| CEFBS_None, // VINSERTW = 2059 | |
| CEFBS_None, // VINSHLX = 2060 | |
| CEFBS_None, // VINSHRX = 2061 | |
| CEFBS_None, // VINSHVLX = 2062 | |
| CEFBS_None, // VINSHVRX = 2063 | |
| CEFBS_None, // VINSW = 2064 | |
| CEFBS_None, // VINSWLX = 2065 | |
| CEFBS_None, // VINSWRX = 2066 | |
| CEFBS_None, // VINSWVLX = 2067 | |
| CEFBS_None, // VINSWVRX = 2068 | |
| CEFBS_None, // VLOGEFP = 2069 | |
| CEFBS_None, // VMADDFP = 2070 | |
| CEFBS_None, // VMAXFP = 2071 | |
| CEFBS_None, // VMAXSB = 2072 | |
| CEFBS_None, // VMAXSD = 2073 | |
| CEFBS_None, // VMAXSH = 2074 | |
| CEFBS_None, // VMAXSW = 2075 | |
| CEFBS_None, // VMAXUB = 2076 | |
| CEFBS_None, // VMAXUD = 2077 | |
| CEFBS_None, // VMAXUH = 2078 | |
| CEFBS_None, // VMAXUW = 2079 | |
| CEFBS_None, // VMHADDSHS = 2080 | |
| CEFBS_None, // VMHRADDSHS = 2081 | |
| CEFBS_None, // VMINFP = 2082 | |
| CEFBS_None, // VMINSB = 2083 | |
| CEFBS_None, // VMINSD = 2084 | |
| CEFBS_None, // VMINSH = 2085 | |
| CEFBS_None, // VMINSW = 2086 | |
| CEFBS_None, // VMINUB = 2087 | |
| CEFBS_None, // VMINUD = 2088 | |
| CEFBS_None, // VMINUH = 2089 | |
| CEFBS_None, // VMINUW = 2090 | |
| CEFBS_None, // VMLADDUHM = 2091 | |
| CEFBS_None, // VMODSD = 2092 | |
| CEFBS_None, // VMODSQ = 2093 | |
| CEFBS_None, // VMODSW = 2094 | |
| CEFBS_None, // VMODUD = 2095 | |
| CEFBS_None, // VMODUQ = 2096 | |
| CEFBS_None, // VMODUW = 2097 | |
| CEFBS_None, // VMRGEW = 2098 | |
| CEFBS_None, // VMRGHB = 2099 | |
| CEFBS_None, // VMRGHH = 2100 | |
| CEFBS_None, // VMRGHW = 2101 | |
| CEFBS_None, // VMRGLB = 2102 | |
| CEFBS_None, // VMRGLH = 2103 | |
| CEFBS_None, // VMRGLW = 2104 | |
| CEFBS_None, // VMRGOW = 2105 | |
| CEFBS_None, // VMSUMCUD = 2106 | |
| CEFBS_None, // VMSUMMBM = 2107 | |
| CEFBS_None, // VMSUMSHM = 2108 | |
| CEFBS_None, // VMSUMSHS = 2109 | |
| CEFBS_None, // VMSUMUBM = 2110 | |
| CEFBS_None, // VMSUMUDM = 2111 | |
| CEFBS_None, // VMSUMUHM = 2112 | |
| CEFBS_None, // VMSUMUHS = 2113 | |
| CEFBS_None, // VMUL10CUQ = 2114 | |
| CEFBS_None, // VMUL10ECUQ = 2115 | |
| CEFBS_None, // VMUL10EUQ = 2116 | |
| CEFBS_None, // VMUL10UQ = 2117 | |
| CEFBS_None, // VMULESB = 2118 | |
| CEFBS_None, // VMULESD = 2119 | |
| CEFBS_None, // VMULESH = 2120 | |
| CEFBS_None, // VMULESW = 2121 | |
| CEFBS_None, // VMULEUB = 2122 | |
| CEFBS_None, // VMULEUD = 2123 | |
| CEFBS_None, // VMULEUH = 2124 | |
| CEFBS_None, // VMULEUW = 2125 | |
| CEFBS_None, // VMULHSD = 2126 | |
| CEFBS_None, // VMULHSW = 2127 | |
| CEFBS_None, // VMULHUD = 2128 | |
| CEFBS_None, // VMULHUW = 2129 | |
| CEFBS_None, // VMULLD = 2130 | |
| CEFBS_None, // VMULOSB = 2131 | |
| CEFBS_None, // VMULOSD = 2132 | |
| CEFBS_None, // VMULOSH = 2133 | |
| CEFBS_None, // VMULOSW = 2134 | |
| CEFBS_None, // VMULOUB = 2135 | |
| CEFBS_None, // VMULOUD = 2136 | |
| CEFBS_None, // VMULOUH = 2137 | |
| CEFBS_None, // VMULOUW = 2138 | |
| CEFBS_None, // VMULUWM = 2139 | |
| CEFBS_None, // VNAND = 2140 | |
| CEFBS_None, // VNCIPHER = 2141 | |
| CEFBS_None, // VNCIPHERLAST = 2142 | |
| CEFBS_None, // VNEGD = 2143 | |
| CEFBS_None, // VNEGW = 2144 | |
| CEFBS_None, // VNMSUBFP = 2145 | |
| CEFBS_None, // VNOR = 2146 | |
| CEFBS_None, // VOR = 2147 | |
| CEFBS_None, // VORC = 2148 | |
| CEFBS_None, // VPDEPD = 2149 | |
| CEFBS_None, // VPERM = 2150 | |
| CEFBS_None, // VPERMR = 2151 | |
| CEFBS_None, // VPERMXOR = 2152 | |
| CEFBS_None, // VPEXTD = 2153 | |
| CEFBS_None, // VPKPX = 2154 | |
| CEFBS_None, // VPKSDSS = 2155 | |
| CEFBS_None, // VPKSDUS = 2156 | |
| CEFBS_None, // VPKSHSS = 2157 | |
| CEFBS_None, // VPKSHUS = 2158 | |
| CEFBS_None, // VPKSWSS = 2159 | |
| CEFBS_None, // VPKSWUS = 2160 | |
| CEFBS_None, // VPKUDUM = 2161 | |
| CEFBS_None, // VPKUDUS = 2162 | |
| CEFBS_None, // VPKUHUM = 2163 | |
| CEFBS_None, // VPKUHUS = 2164 | |
| CEFBS_None, // VPKUWUM = 2165 | |
| CEFBS_None, // VPKUWUS = 2166 | |
| CEFBS_None, // VPMSUMB = 2167 | |
| CEFBS_None, // VPMSUMD = 2168 | |
| CEFBS_None, // VPMSUMH = 2169 | |
| CEFBS_None, // VPMSUMW = 2170 | |
| CEFBS_None, // VPOPCNTB = 2171 | |
| CEFBS_None, // VPOPCNTD = 2172 | |
| CEFBS_None, // VPOPCNTH = 2173 | |
| CEFBS_None, // VPOPCNTW = 2174 | |
| CEFBS_None, // VPRTYBD = 2175 | |
| CEFBS_None, // VPRTYBQ = 2176 | |
| CEFBS_None, // VPRTYBW = 2177 | |
| CEFBS_None, // VREFP = 2178 | |
| CEFBS_None, // VRFIM = 2179 | |
| CEFBS_None, // VRFIN = 2180 | |
| CEFBS_None, // VRFIP = 2181 | |
| CEFBS_None, // VRFIZ = 2182 | |
| CEFBS_None, // VRLB = 2183 | |
| CEFBS_None, // VRLD = 2184 | |
| CEFBS_None, // VRLDMI = 2185 | |
| CEFBS_None, // VRLDNM = 2186 | |
| CEFBS_None, // VRLH = 2187 | |
| CEFBS_None, // VRLQ = 2188 | |
| CEFBS_None, // VRLQMI = 2189 | |
| CEFBS_None, // VRLQNM = 2190 | |
| CEFBS_None, // VRLW = 2191 | |
| CEFBS_None, // VRLWMI = 2192 | |
| CEFBS_None, // VRLWNM = 2193 | |
| CEFBS_None, // VRSQRTEFP = 2194 | |
| CEFBS_None, // VSBOX = 2195 | |
| CEFBS_None, // VSEL = 2196 | |
| CEFBS_None, // VSHASIGMAD = 2197 | |
| CEFBS_None, // VSHASIGMAW = 2198 | |
| CEFBS_None, // VSL = 2199 | |
| CEFBS_None, // VSLB = 2200 | |
| CEFBS_None, // VSLD = 2201 | |
| CEFBS_None, // VSLDBI = 2202 | |
| CEFBS_None, // VSLDOI = 2203 | |
| CEFBS_None, // VSLH = 2204 | |
| CEFBS_None, // VSLO = 2205 | |
| CEFBS_None, // VSLQ = 2206 | |
| CEFBS_None, // VSLV = 2207 | |
| CEFBS_None, // VSLW = 2208 | |
| CEFBS_None, // VSPLTB = 2209 | |
| CEFBS_None, // VSPLTBs = 2210 | |
| CEFBS_None, // VSPLTH = 2211 | |
| CEFBS_None, // VSPLTHs = 2212 | |
| CEFBS_None, // VSPLTISB = 2213 | |
| CEFBS_None, // VSPLTISH = 2214 | |
| CEFBS_None, // VSPLTISW = 2215 | |
| CEFBS_None, // VSPLTW = 2216 | |
| CEFBS_None, // VSR = 2217 | |
| CEFBS_None, // VSRAB = 2218 | |
| CEFBS_None, // VSRAD = 2219 | |
| CEFBS_None, // VSRAH = 2220 | |
| CEFBS_None, // VSRAQ = 2221 | |
| CEFBS_None, // VSRAW = 2222 | |
| CEFBS_None, // VSRB = 2223 | |
| CEFBS_None, // VSRD = 2224 | |
| CEFBS_None, // VSRDBI = 2225 | |
| CEFBS_None, // VSRH = 2226 | |
| CEFBS_None, // VSRO = 2227 | |
| CEFBS_None, // VSRQ = 2228 | |
| CEFBS_None, // VSRV = 2229 | |
| CEFBS_None, // VSRW = 2230 | |
| CEFBS_None, // VSTRIBL = 2231 | |
| CEFBS_None, // VSTRIBL_rec = 2232 | |
| CEFBS_None, // VSTRIBR = 2233 | |
| CEFBS_None, // VSTRIBR_rec = 2234 | |
| CEFBS_None, // VSTRIHL = 2235 | |
| CEFBS_None, // VSTRIHL_rec = 2236 | |
| CEFBS_None, // VSTRIHR = 2237 | |
| CEFBS_None, // VSTRIHR_rec = 2238 | |
| CEFBS_None, // VSUBCUQ = 2239 | |
| CEFBS_None, // VSUBCUW = 2240 | |
| CEFBS_None, // VSUBECUQ = 2241 | |
| CEFBS_None, // VSUBEUQM = 2242 | |
| CEFBS_None, // VSUBFP = 2243 | |
| CEFBS_None, // VSUBSBS = 2244 | |
| CEFBS_None, // VSUBSHS = 2245 | |
| CEFBS_None, // VSUBSWS = 2246 | |
| CEFBS_None, // VSUBUBM = 2247 | |
| CEFBS_None, // VSUBUBS = 2248 | |
| CEFBS_None, // VSUBUDM = 2249 | |
| CEFBS_None, // VSUBUHM = 2250 | |
| CEFBS_None, // VSUBUHS = 2251 | |
| CEFBS_None, // VSUBUQM = 2252 | |
| CEFBS_None, // VSUBUWM = 2253 | |
| CEFBS_None, // VSUBUWS = 2254 | |
| CEFBS_None, // VSUM2SWS = 2255 | |
| CEFBS_None, // VSUM4SBS = 2256 | |
| CEFBS_None, // VSUM4SHS = 2257 | |
| CEFBS_None, // VSUM4UBS = 2258 | |
| CEFBS_None, // VSUMSWS = 2259 | |
| CEFBS_None, // VUPKHPX = 2260 | |
| CEFBS_None, // VUPKHSB = 2261 | |
| CEFBS_None, // VUPKHSH = 2262 | |
| CEFBS_None, // VUPKHSW = 2263 | |
| CEFBS_None, // VUPKLPX = 2264 | |
| CEFBS_None, // VUPKLSB = 2265 | |
| CEFBS_None, // VUPKLSH = 2266 | |
| CEFBS_None, // VUPKLSW = 2267 | |
| CEFBS_None, // VXOR = 2268 | |
| CEFBS_None, // V_SET0 = 2269 | |
| CEFBS_None, // V_SET0B = 2270 | |
| CEFBS_None, // V_SET0H = 2271 | |
| CEFBS_None, // V_SETALLONES = 2272 | |
| CEFBS_None, // V_SETALLONESB = 2273 | |
| CEFBS_None, // V_SETALLONESH = 2274 | |
| CEFBS_None, // WAIT = 2275 | |
| CEFBS_None, // WRTEE = 2276 | |
| CEFBS_None, // WRTEEI = 2277 | |
| CEFBS_None, // XOR = 2278 | |
| CEFBS_None, // XOR8 = 2279 | |
| CEFBS_None, // XOR8_rec = 2280 | |
| CEFBS_None, // XORI = 2281 | |
| CEFBS_None, // XORI8 = 2282 | |
| CEFBS_None, // XORIS = 2283 | |
| CEFBS_None, // XORIS8 = 2284 | |
| CEFBS_None, // XOR_rec = 2285 | |
| CEFBS_None, // XSABSDP = 2286 | |
| CEFBS_None, // XSABSQP = 2287 | |
| CEFBS_None, // XSADDDP = 2288 | |
| CEFBS_None, // XSADDQP = 2289 | |
| CEFBS_None, // XSADDQPO = 2290 | |
| CEFBS_None, // XSADDSP = 2291 | |
| CEFBS_None, // XSCMPEQDP = 2292 | |
| CEFBS_None, // XSCMPEQQP = 2293 | |
| CEFBS_None, // XSCMPEXPDP = 2294 | |
| CEFBS_None, // XSCMPEXPQP = 2295 | |
| CEFBS_None, // XSCMPGEDP = 2296 | |
| CEFBS_None, // XSCMPGEQP = 2297 | |
| CEFBS_None, // XSCMPGTDP = 2298 | |
| CEFBS_None, // XSCMPGTQP = 2299 | |
| CEFBS_None, // XSCMPODP = 2300 | |
| CEFBS_None, // XSCMPOQP = 2301 | |
| CEFBS_None, // XSCMPUDP = 2302 | |
| CEFBS_None, // XSCMPUQP = 2303 | |
| CEFBS_None, // XSCPSGNDP = 2304 | |
| CEFBS_None, // XSCPSGNQP = 2305 | |
| CEFBS_None, // XSCVDPHP = 2306 | |
| CEFBS_None, // XSCVDPQP = 2307 | |
| CEFBS_None, // XSCVDPSP = 2308 | |
| CEFBS_None, // XSCVDPSPN = 2309 | |
| CEFBS_None, // XSCVDPSXDS = 2310 | |
| CEFBS_None, // XSCVDPSXDSs = 2311 | |
| CEFBS_None, // XSCVDPSXWS = 2312 | |
| CEFBS_None, // XSCVDPSXWSs = 2313 | |
| CEFBS_None, // XSCVDPUXDS = 2314 | |
| CEFBS_None, // XSCVDPUXDSs = 2315 | |
| CEFBS_None, // XSCVDPUXWS = 2316 | |
| CEFBS_None, // XSCVDPUXWSs = 2317 | |
| CEFBS_None, // XSCVHPDP = 2318 | |
| CEFBS_None, // XSCVQPDP = 2319 | |
| CEFBS_None, // XSCVQPDPO = 2320 | |
| CEFBS_None, // XSCVQPSDZ = 2321 | |
| CEFBS_None, // XSCVQPSQZ = 2322 | |
| CEFBS_None, // XSCVQPSWZ = 2323 | |
| CEFBS_None, // XSCVQPUDZ = 2324 | |
| CEFBS_None, // XSCVQPUQZ = 2325 | |
| CEFBS_None, // XSCVQPUWZ = 2326 | |
| CEFBS_None, // XSCVSDQP = 2327 | |
| CEFBS_None, // XSCVSPDP = 2328 | |
| CEFBS_None, // XSCVSPDPN = 2329 | |
| CEFBS_None, // XSCVSQQP = 2330 | |
| CEFBS_None, // XSCVSXDDP = 2331 | |
| CEFBS_None, // XSCVSXDSP = 2332 | |
| CEFBS_None, // XSCVUDQP = 2333 | |
| CEFBS_None, // XSCVUQQP = 2334 | |
| CEFBS_None, // XSCVUXDDP = 2335 | |
| CEFBS_None, // XSCVUXDSP = 2336 | |
| CEFBS_None, // XSDIVDP = 2337 | |
| CEFBS_None, // XSDIVQP = 2338 | |
| CEFBS_None, // XSDIVQPO = 2339 | |
| CEFBS_None, // XSDIVSP = 2340 | |
| CEFBS_None, // XSIEXPDP = 2341 | |
| CEFBS_None, // XSIEXPQP = 2342 | |
| CEFBS_None, // XSMADDADP = 2343 | |
| CEFBS_None, // XSMADDASP = 2344 | |
| CEFBS_None, // XSMADDMDP = 2345 | |
| CEFBS_None, // XSMADDMSP = 2346 | |
| CEFBS_None, // XSMADDQP = 2347 | |
| CEFBS_None, // XSMADDQPO = 2348 | |
| CEFBS_None, // XSMAXCDP = 2349 | |
| CEFBS_None, // XSMAXCQP = 2350 | |
| CEFBS_None, // XSMAXDP = 2351 | |
| CEFBS_None, // XSMAXJDP = 2352 | |
| CEFBS_None, // XSMINCDP = 2353 | |
| CEFBS_None, // XSMINCQP = 2354 | |
| CEFBS_None, // XSMINDP = 2355 | |
| CEFBS_None, // XSMINJDP = 2356 | |
| CEFBS_None, // XSMSUBADP = 2357 | |
| CEFBS_None, // XSMSUBASP = 2358 | |
| CEFBS_None, // XSMSUBMDP = 2359 | |
| CEFBS_None, // XSMSUBMSP = 2360 | |
| CEFBS_None, // XSMSUBQP = 2361 | |
| CEFBS_None, // XSMSUBQPO = 2362 | |
| CEFBS_None, // XSMULDP = 2363 | |
| CEFBS_None, // XSMULQP = 2364 | |
| CEFBS_None, // XSMULQPO = 2365 | |
| CEFBS_None, // XSMULSP = 2366 | |
| CEFBS_None, // XSNABSDP = 2367 | |
| CEFBS_None, // XSNABSDPs = 2368 | |
| CEFBS_None, // XSNABSQP = 2369 | |
| CEFBS_None, // XSNEGDP = 2370 | |
| CEFBS_None, // XSNEGQP = 2371 | |
| CEFBS_None, // XSNMADDADP = 2372 | |
| CEFBS_None, // XSNMADDASP = 2373 | |
| CEFBS_None, // XSNMADDMDP = 2374 | |
| CEFBS_None, // XSNMADDMSP = 2375 | |
| CEFBS_None, // XSNMADDQP = 2376 | |
| CEFBS_None, // XSNMADDQPO = 2377 | |
| CEFBS_None, // XSNMSUBADP = 2378 | |
| CEFBS_None, // XSNMSUBASP = 2379 | |
| CEFBS_None, // XSNMSUBMDP = 2380 | |
| CEFBS_None, // XSNMSUBMSP = 2381 | |
| CEFBS_None, // XSNMSUBQP = 2382 | |
| CEFBS_None, // XSNMSUBQPO = 2383 | |
| CEFBS_None, // XSRDPI = 2384 | |
| CEFBS_None, // XSRDPIC = 2385 | |
| CEFBS_None, // XSRDPIM = 2386 | |
| CEFBS_None, // XSRDPIP = 2387 | |
| CEFBS_None, // XSRDPIZ = 2388 | |
| CEFBS_None, // XSREDP = 2389 | |
| CEFBS_None, // XSRESP = 2390 | |
| CEFBS_None, // XSRQPI = 2391 | |
| CEFBS_None, // XSRQPIX = 2392 | |
| CEFBS_None, // XSRQPXP = 2393 | |
| CEFBS_None, // XSRSP = 2394 | |
| CEFBS_None, // XSRSQRTEDP = 2395 | |
| CEFBS_None, // XSRSQRTESP = 2396 | |
| CEFBS_None, // XSSQRTDP = 2397 | |
| CEFBS_None, // XSSQRTQP = 2398 | |
| CEFBS_None, // XSSQRTQPO = 2399 | |
| CEFBS_None, // XSSQRTSP = 2400 | |
| CEFBS_None, // XSSUBDP = 2401 | |
| CEFBS_None, // XSSUBQP = 2402 | |
| CEFBS_None, // XSSUBQPO = 2403 | |
| CEFBS_None, // XSSUBSP = 2404 | |
| CEFBS_None, // XSTDIVDP = 2405 | |
| CEFBS_None, // XSTSQRTDP = 2406 | |
| CEFBS_None, // XSTSTDCDP = 2407 | |
| CEFBS_None, // XSTSTDCQP = 2408 | |
| CEFBS_None, // XSTSTDCSP = 2409 | |
| CEFBS_None, // XSXEXPDP = 2410 | |
| CEFBS_None, // XSXEXPQP = 2411 | |
| CEFBS_None, // XSXSIGDP = 2412 | |
| CEFBS_None, // XSXSIGQP = 2413 | |
| CEFBS_None, // XVABSDP = 2414 | |
| CEFBS_None, // XVABSSP = 2415 | |
| CEFBS_None, // XVADDDP = 2416 | |
| CEFBS_None, // XVADDSP = 2417 | |
| CEFBS_None, // XVBF16GER2 = 2418 | |
| CEFBS_None, // XVBF16GER2NN = 2419 | |
| CEFBS_None, // XVBF16GER2NP = 2420 | |
| CEFBS_None, // XVBF16GER2PN = 2421 | |
| CEFBS_None, // XVBF16GER2PP = 2422 | |
| CEFBS_None, // XVBF16GER2W = 2423 | |
| CEFBS_None, // XVBF16GER2WNN = 2424 | |
| CEFBS_None, // XVBF16GER2WNP = 2425 | |
| CEFBS_None, // XVBF16GER2WPN = 2426 | |
| CEFBS_None, // XVBF16GER2WPP = 2427 | |
| CEFBS_None, // XVCMPEQDP = 2428 | |
| CEFBS_None, // XVCMPEQDP_rec = 2429 | |
| CEFBS_None, // XVCMPEQSP = 2430 | |
| CEFBS_None, // XVCMPEQSP_rec = 2431 | |
| CEFBS_None, // XVCMPGEDP = 2432 | |
| CEFBS_None, // XVCMPGEDP_rec = 2433 | |
| CEFBS_None, // XVCMPGESP = 2434 | |
| CEFBS_None, // XVCMPGESP_rec = 2435 | |
| CEFBS_None, // XVCMPGTDP = 2436 | |
| CEFBS_None, // XVCMPGTDP_rec = 2437 | |
| CEFBS_None, // XVCMPGTSP = 2438 | |
| CEFBS_None, // XVCMPGTSP_rec = 2439 | |
| CEFBS_None, // XVCPSGNDP = 2440 | |
| CEFBS_None, // XVCPSGNSP = 2441 | |
| CEFBS_None, // XVCVBF16SPN = 2442 | |
| CEFBS_None, // XVCVDPSP = 2443 | |
| CEFBS_None, // XVCVDPSXDS = 2444 | |
| CEFBS_None, // XVCVDPSXWS = 2445 | |
| CEFBS_None, // XVCVDPUXDS = 2446 | |
| CEFBS_None, // XVCVDPUXWS = 2447 | |
| CEFBS_None, // XVCVHPSP = 2448 | |
| CEFBS_None, // XVCVSPBF16 = 2449 | |
| CEFBS_None, // XVCVSPDP = 2450 | |
| CEFBS_None, // XVCVSPHP = 2451 | |
| CEFBS_None, // XVCVSPSXDS = 2452 | |
| CEFBS_None, // XVCVSPSXWS = 2453 | |
| CEFBS_None, // XVCVSPUXDS = 2454 | |
| CEFBS_None, // XVCVSPUXWS = 2455 | |
| CEFBS_None, // XVCVSXDDP = 2456 | |
| CEFBS_None, // XVCVSXDSP = 2457 | |
| CEFBS_None, // XVCVSXWDP = 2458 | |
| CEFBS_None, // XVCVSXWSP = 2459 | |
| CEFBS_None, // XVCVUXDDP = 2460 | |
| CEFBS_None, // XVCVUXDSP = 2461 | |
| CEFBS_None, // XVCVUXWDP = 2462 | |
| CEFBS_None, // XVCVUXWSP = 2463 | |
| CEFBS_None, // XVDIVDP = 2464 | |
| CEFBS_None, // XVDIVSP = 2465 | |
| CEFBS_None, // XVF16GER2 = 2466 | |
| CEFBS_None, // XVF16GER2NN = 2467 | |
| CEFBS_None, // XVF16GER2NP = 2468 | |
| CEFBS_None, // XVF16GER2PN = 2469 | |
| CEFBS_None, // XVF16GER2PP = 2470 | |
| CEFBS_None, // XVF16GER2W = 2471 | |
| CEFBS_None, // XVF16GER2WNN = 2472 | |
| CEFBS_None, // XVF16GER2WNP = 2473 | |
| CEFBS_None, // XVF16GER2WPN = 2474 | |
| CEFBS_None, // XVF16GER2WPP = 2475 | |
| CEFBS_None, // XVF32GER = 2476 | |
| CEFBS_None, // XVF32GERNN = 2477 | |
| CEFBS_None, // XVF32GERNP = 2478 | |
| CEFBS_None, // XVF32GERPN = 2479 | |
| CEFBS_None, // XVF32GERPP = 2480 | |
| CEFBS_None, // XVF32GERW = 2481 | |
| CEFBS_None, // XVF32GERWNN = 2482 | |
| CEFBS_None, // XVF32GERWNP = 2483 | |
| CEFBS_None, // XVF32GERWPN = 2484 | |
| CEFBS_None, // XVF32GERWPP = 2485 | |
| CEFBS_None, // XVF64GER = 2486 | |
| CEFBS_None, // XVF64GERNN = 2487 | |
| CEFBS_None, // XVF64GERNP = 2488 | |
| CEFBS_None, // XVF64GERPN = 2489 | |
| CEFBS_None, // XVF64GERPP = 2490 | |
| CEFBS_None, // XVF64GERW = 2491 | |
| CEFBS_None, // XVF64GERWNN = 2492 | |
| CEFBS_None, // XVF64GERWNP = 2493 | |
| CEFBS_None, // XVF64GERWPN = 2494 | |
| CEFBS_None, // XVF64GERWPP = 2495 | |
| CEFBS_None, // XVI16GER2 = 2496 | |
| CEFBS_None, // XVI16GER2PP = 2497 | |
| CEFBS_None, // XVI16GER2S = 2498 | |
| CEFBS_None, // XVI16GER2SPP = 2499 | |
| CEFBS_None, // XVI16GER2SW = 2500 | |
| CEFBS_None, // XVI16GER2SWPP = 2501 | |
| CEFBS_None, // XVI16GER2W = 2502 | |
| CEFBS_None, // XVI16GER2WPP = 2503 | |
| CEFBS_None, // XVI4GER8 = 2504 | |
| CEFBS_None, // XVI4GER8PP = 2505 | |
| CEFBS_None, // XVI4GER8W = 2506 | |
| CEFBS_None, // XVI4GER8WPP = 2507 | |
| CEFBS_None, // XVI8GER4 = 2508 | |
| CEFBS_None, // XVI8GER4PP = 2509 | |
| CEFBS_None, // XVI8GER4SPP = 2510 | |
| CEFBS_None, // XVI8GER4W = 2511 | |
| CEFBS_None, // XVI8GER4WPP = 2512 | |
| CEFBS_None, // XVI8GER4WSPP = 2513 | |
| CEFBS_None, // XVIEXPDP = 2514 | |
| CEFBS_None, // XVIEXPSP = 2515 | |
| CEFBS_None, // XVMADDADP = 2516 | |
| CEFBS_None, // XVMADDASP = 2517 | |
| CEFBS_None, // XVMADDMDP = 2518 | |
| CEFBS_None, // XVMADDMSP = 2519 | |
| CEFBS_None, // XVMAXDP = 2520 | |
| CEFBS_None, // XVMAXSP = 2521 | |
| CEFBS_None, // XVMINDP = 2522 | |
| CEFBS_None, // XVMINSP = 2523 | |
| CEFBS_None, // XVMSUBADP = 2524 | |
| CEFBS_None, // XVMSUBASP = 2525 | |
| CEFBS_None, // XVMSUBMDP = 2526 | |
| CEFBS_None, // XVMSUBMSP = 2527 | |
| CEFBS_None, // XVMULDP = 2528 | |
| CEFBS_None, // XVMULSP = 2529 | |
| CEFBS_None, // XVNABSDP = 2530 | |
| CEFBS_None, // XVNABSSP = 2531 | |
| CEFBS_None, // XVNEGDP = 2532 | |
| CEFBS_None, // XVNEGSP = 2533 | |
| CEFBS_None, // XVNMADDADP = 2534 | |
| CEFBS_None, // XVNMADDASP = 2535 | |
| CEFBS_None, // XVNMADDMDP = 2536 | |
| CEFBS_None, // XVNMADDMSP = 2537 | |
| CEFBS_None, // XVNMSUBADP = 2538 | |
| CEFBS_None, // XVNMSUBASP = 2539 | |
| CEFBS_None, // XVNMSUBMDP = 2540 | |
| CEFBS_None, // XVNMSUBMSP = 2541 | |
| CEFBS_None, // XVRDPI = 2542 | |
| CEFBS_None, // XVRDPIC = 2543 | |
| CEFBS_None, // XVRDPIM = 2544 | |
| CEFBS_None, // XVRDPIP = 2545 | |
| CEFBS_None, // XVRDPIZ = 2546 | |
| CEFBS_None, // XVREDP = 2547 | |
| CEFBS_None, // XVRESP = 2548 | |
| CEFBS_None, // XVRSPI = 2549 | |
| CEFBS_None, // XVRSPIC = 2550 | |
| CEFBS_None, // XVRSPIM = 2551 | |
| CEFBS_None, // XVRSPIP = 2552 | |
| CEFBS_None, // XVRSPIZ = 2553 | |
| CEFBS_None, // XVRSQRTEDP = 2554 | |
| CEFBS_None, // XVRSQRTESP = 2555 | |
| CEFBS_None, // XVSQRTDP = 2556 | |
| CEFBS_None, // XVSQRTSP = 2557 | |
| CEFBS_None, // XVSUBDP = 2558 | |
| CEFBS_None, // XVSUBSP = 2559 | |
| CEFBS_None, // XVTDIVDP = 2560 | |
| CEFBS_None, // XVTDIVSP = 2561 | |
| CEFBS_None, // XVTLSBB = 2562 | |
| CEFBS_None, // XVTSQRTDP = 2563 | |
| CEFBS_None, // XVTSQRTSP = 2564 | |
| CEFBS_None, // XVTSTDCDP = 2565 | |
| CEFBS_None, // XVTSTDCSP = 2566 | |
| CEFBS_None, // XVXEXPDP = 2567 | |
| CEFBS_None, // XVXEXPSP = 2568 | |
| CEFBS_None, // XVXSIGDP = 2569 | |
| CEFBS_None, // XVXSIGSP = 2570 | |
| CEFBS_None, // XXBLENDVB = 2571 | |
| CEFBS_None, // XXBLENDVD = 2572 | |
| CEFBS_None, // XXBLENDVH = 2573 | |
| CEFBS_None, // XXBLENDVW = 2574 | |
| CEFBS_None, // XXBRD = 2575 | |
| CEFBS_None, // XXBRH = 2576 | |
| CEFBS_None, // XXBRQ = 2577 | |
| CEFBS_None, // XXBRW = 2578 | |
| CEFBS_None, // XXEVAL = 2579 | |
| CEFBS_None, // XXEXTRACTUW = 2580 | |
| CEFBS_None, // XXGENPCVBM = 2581 | |
| CEFBS_None, // XXGENPCVDM = 2582 | |
| CEFBS_None, // XXGENPCVHM = 2583 | |
| CEFBS_None, // XXGENPCVWM = 2584 | |
| CEFBS_None, // XXINSERTW = 2585 | |
| CEFBS_None, // XXLAND = 2586 | |
| CEFBS_None, // XXLANDC = 2587 | |
| CEFBS_None, // XXLEQV = 2588 | |
| CEFBS_None, // XXLEQVOnes = 2589 | |
| CEFBS_None, // XXLNAND = 2590 | |
| CEFBS_None, // XXLNOR = 2591 | |
| CEFBS_None, // XXLOR = 2592 | |
| CEFBS_None, // XXLORC = 2593 | |
| CEFBS_None, // XXLORf = 2594 | |
| CEFBS_None, // XXLXOR = 2595 | |
| CEFBS_None, // XXLXORdpz = 2596 | |
| CEFBS_None, // XXLXORspz = 2597 | |
| CEFBS_None, // XXLXORz = 2598 | |
| CEFBS_None, // XXMFACC = 2599 | |
| CEFBS_None, // XXMFACCW = 2600 | |
| CEFBS_None, // XXMRGHW = 2601 | |
| CEFBS_None, // XXMRGLW = 2602 | |
| CEFBS_None, // XXMTACC = 2603 | |
| CEFBS_None, // XXMTACCW = 2604 | |
| CEFBS_None, // XXPERM = 2605 | |
| CEFBS_None, // XXPERMDI = 2606 | |
| CEFBS_None, // XXPERMDIs = 2607 | |
| CEFBS_None, // XXPERMR = 2608 | |
| CEFBS_None, // XXPERMX = 2609 | |
| CEFBS_None, // XXSEL = 2610 | |
| CEFBS_None, // XXSETACCZ = 2611 | |
| CEFBS_None, // XXSETACCZW = 2612 | |
| CEFBS_None, // XXSLDWI = 2613 | |
| CEFBS_None, // XXSLDWIs = 2614 | |
| CEFBS_None, // XXSPLTI32DX = 2615 | |
| CEFBS_None, // XXSPLTIB = 2616 | |
| CEFBS_None, // XXSPLTIDP = 2617 | |
| CEFBS_None, // XXSPLTIW = 2618 | |
| CEFBS_None, // XXSPLTW = 2619 | |
| CEFBS_None, // XXSPLTWs = 2620 | |
| CEFBS_None, // gBC = 2621 | |
| CEFBS_None, // gBCA = 2622 | |
| CEFBS_None, // gBCAat = 2623 | |
| CEFBS_None, // gBCCTR = 2624 | |
| CEFBS_None, // gBCCTRL = 2625 | |
| CEFBS_None, // gBCL = 2626 | |
| CEFBS_None, // gBCLA = 2627 | |
| CEFBS_None, // gBCLAat = 2628 | |
| CEFBS_None, // gBCLR = 2629 | |
| CEFBS_None, // gBCLRL = 2630 | |
| CEFBS_None, // gBCLat = 2631 | |
| CEFBS_None, // gBCat = 2632 | |
| }; | |
| assert(Opcode < 2633); | |
| FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); | |
| const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Opcode]]; | |
| FeatureBitset MissingFeatures = | |
| (AvailableFeatures & RequiredFeatures) ^ | |
| RequiredFeatures; | |
| if (MissingFeatures.any()) { | |
| std::ostringstream Msg; | |
| Msg << "Attempting to emit " << &PPCInstrNameData[PPCInstrNameIndices[Opcode]] | |
| << " instruction but the "; | |
| for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) | |
| if (MissingFeatures.test(i)) | |
| Msg << SubtargetFeatureNames[i] << " "; | |
| Msg << "predicate(s) are not met"; | |
| report_fatal_error(Msg.str().c_str()); | |
| } | |
| #endif // NDEBUG | |
| } | |
| } // end namespace PPC_MC | |
| } // end namespace llvm | |
| #endif // ENABLE_INSTR_PREDICATE_VERIFIER | |
| #ifdef GET_INSTRMAP_INFO | |
| #undef GET_INSTRMAP_INFO | |
| namespace llvm { | |
| namespace PPC { | |
| enum IsVSXFMAAlt { | |
| IsVSXFMAAlt_1 | |
| }; | |
| enum RC { | |
| RC_0, | |
| RC_1 | |
| }; | |
| // getAltVSXFMAOpcode | |
| LLVM_READONLY | |
| int getAltVSXFMAOpcode(uint16_t Opcode) { | |
| static const uint16_t getAltVSXFMAOpcodeTable[][2] = { | |
| { PPC::XSMADDADP, PPC::XSMADDMDP }, | |
| { PPC::XSMADDASP, PPC::XSMADDMSP }, | |
| { PPC::XSMSUBADP, PPC::XSMSUBMDP }, | |
| { PPC::XSMSUBASP, PPC::XSMSUBMSP }, | |
| { PPC::XSNMADDADP, PPC::XSNMADDMDP }, | |
| { PPC::XSNMADDASP, PPC::XSNMADDMSP }, | |
| { PPC::XSNMSUBADP, PPC::XSNMSUBMDP }, | |
| { PPC::XSNMSUBASP, PPC::XSNMSUBMSP }, | |
| { PPC::XVMADDADP, PPC::XVMADDMDP }, | |
| { PPC::XVMADDASP, PPC::XVMADDMSP }, | |
| { PPC::XVMSUBADP, PPC::XVMSUBMDP }, | |
| { PPC::XVMSUBASP, PPC::XVMSUBMSP }, | |
| { PPC::XVNMADDADP, PPC::XVNMADDMDP }, | |
| { PPC::XVNMADDASP, PPC::XVNMADDMSP }, | |
| { PPC::XVNMSUBADP, PPC::XVNMSUBMDP }, | |
| { PPC::XVNMSUBASP, PPC::XVNMSUBMSP }, | |
| }; // End of getAltVSXFMAOpcodeTable | |
| unsigned mid; | |
| unsigned start = 0; | |
| unsigned end = 16; | |
| while (start < end) { | |
| mid = start + (end - start) / 2; | |
| if (Opcode == getAltVSXFMAOpcodeTable[mid][0]) { | |
| break; | |
| } | |
| if (Opcode < getAltVSXFMAOpcodeTable[mid][0]) | |
| end = mid; | |
| else | |
| start = mid + 1; | |
| } | |
| if (start == end) | |
| return -1; // Instruction doesn't exist in this table. | |
| return getAltVSXFMAOpcodeTable[mid][1]; | |
| } | |
| // getNonRecordFormOpcode | |
| LLVM_READONLY | |
| int getNonRecordFormOpcode(uint16_t Opcode) { | |
| static const uint16_t getNonRecordFormOpcodeTable[][2] = { | |
| { PPC::ADD4O_rec, PPC::ADD4O }, | |
| { PPC::ADD4_rec, PPC::ADD4 }, | |
| { PPC::ADD8O_rec, PPC::ADD8O }, | |
| { PPC::ADD8_rec, PPC::ADD8 }, | |
| { PPC::ADDC8O_rec, PPC::ADDC8O }, | |
| { PPC::ADDC8_rec, PPC::ADDC8 }, | |
| { PPC::ADDCO_rec, PPC::ADDCO }, | |
| { PPC::ADDC_rec, PPC::ADDC }, | |
| { PPC::ADDE8O_rec, PPC::ADDE8O }, | |
| { PPC::ADDE8_rec, PPC::ADDE8 }, | |
| { PPC::ADDEO_rec, PPC::ADDEO }, | |
| { PPC::ADDE_rec, PPC::ADDE }, | |
| { PPC::ADDIC_rec, PPC::ADDIC }, | |
| { PPC::ADDME8O_rec, PPC::ADDME8O }, | |
| { PPC::ADDME8_rec, PPC::ADDME8 }, | |
| { PPC::ADDMEO_rec, PPC::ADDMEO }, | |
| { PPC::ADDME_rec, PPC::ADDME }, | |
| { PPC::ADDZE8O_rec, PPC::ADDZE8O }, | |
| { PPC::ADDZE8_rec, PPC::ADDZE8 }, | |
| { PPC::ADDZEO_rec, PPC::ADDZEO }, | |
| { PPC::ADDZE_rec, PPC::ADDZE }, | |
| { PPC::AND8_rec, PPC::AND8 }, | |
| { PPC::ANDC8_rec, PPC::ANDC8 }, | |
| { PPC::ANDC_rec, PPC::ANDC }, | |
| { PPC::AND_rec, PPC::AND }, | |
| { PPC::CNTLZD_rec, PPC::CNTLZD }, | |
| { PPC::CNTLZW8_rec, PPC::CNTLZW8 }, | |
| { PPC::CNTLZW_rec, PPC::CNTLZW }, | |
| { PPC::CNTTZD_rec, PPC::CNTTZD }, | |
| { PPC::CNTTZW8_rec, PPC::CNTTZW8 }, | |
| { PPC::CNTTZW_rec, PPC::CNTTZW }, | |
| { PPC::DIVDEO_rec, PPC::DIVDEO }, | |
| { PPC::DIVDEUO_rec, PPC::DIVDEUO }, | |
| { PPC::DIVDEU_rec, PPC::DIVDEU }, | |
| { PPC::DIVDE_rec, PPC::DIVDE }, | |
| { PPC::DIVDO_rec, PPC::DIVDO }, | |
| { PPC::DIVDUO_rec, PPC::DIVDUO }, | |
| { PPC::DIVDU_rec, PPC::DIVDU }, | |
| { PPC::DIVD_rec, PPC::DIVD }, | |
| { PPC::DIVWEO_rec, PPC::DIVWEO }, | |
| { PPC::DIVWEUO_rec, PPC::DIVWEUO }, | |
| { PPC::DIVWEU_rec, PPC::DIVWEU }, | |
| { PPC::DIVWE_rec, PPC::DIVWE }, | |
| { PPC::DIVWO_rec, PPC::DIVWO }, | |
| { PPC::DIVWUO_rec, PPC::DIVWUO }, | |
| { PPC::DIVWU_rec, PPC::DIVWU }, | |
| { PPC::DIVW_rec, PPC::DIVW }, | |
| { PPC::EQV8_rec, PPC::EQV8 }, | |
| { PPC::EQV_rec, PPC::EQV }, | |
| { PPC::EXTSB8_rec, PPC::EXTSB8 }, | |
| { PPC::EXTSB_rec, PPC::EXTSB }, | |
| { PPC::EXTSH8_rec, PPC::EXTSH8 }, | |
| { PPC::EXTSH_rec, PPC::EXTSH }, | |
| { PPC::EXTSWSLI_32_64_rec, PPC::EXTSWSLI_32_64 }, | |
| { PPC::EXTSWSLI_rec, PPC::EXTSWSLI }, | |
| { PPC::EXTSW_32_64_rec, PPC::EXTSW_32_64 }, | |
| { PPC::EXTSW_rec, PPC::EXTSW }, | |
| { PPC::FABSD_rec, PPC::FABSD }, | |
| { PPC::FABSS_rec, PPC::FABSS }, | |
| { PPC::FADDS_rec, PPC::FADDS }, | |
| { PPC::FADD_rec, PPC::FADD }, | |
| { PPC::FCFIDS_rec, PPC::FCFIDS }, | |
| { PPC::FCFIDUS_rec, PPC::FCFIDUS }, | |
| { PPC::FCFIDU_rec, PPC::FCFIDU }, | |
| { PPC::FCFID_rec, PPC::FCFID }, | |
| { PPC::FCPSGND_rec, PPC::FCPSGND }, | |
| { PPC::FCPSGNS_rec, PPC::FCPSGNS }, | |
| { PPC::FCTIDUZ_rec, PPC::FCTIDUZ }, | |
| { PPC::FCTIDU_rec, PPC::FCTIDU }, | |
| { PPC::FCTIDZ_rec, PPC::FCTIDZ }, | |
| { PPC::FCTID_rec, PPC::FCTID }, | |
| { PPC::FCTIWUZ_rec, PPC::FCTIWUZ }, | |
| { PPC::FCTIWU_rec, PPC::FCTIWU }, | |
| { PPC::FCTIWZ_rec, PPC::FCTIWZ }, | |
| { PPC::FCTIW_rec, PPC::FCTIW }, | |
| { PPC::FDIVS_rec, PPC::FDIVS }, | |
| { PPC::FDIV_rec, PPC::FDIV }, | |
| { PPC::FMADDS_rec, PPC::FMADDS }, | |
| { PPC::FMADD_rec, PPC::FMADD }, | |
| { PPC::FMR_rec, PPC::FMR }, | |
| { PPC::FMSUBS_rec, PPC::FMSUBS }, | |
| { PPC::FMSUB_rec, PPC::FMSUB }, | |
| { PPC::FMULS_rec, PPC::FMULS }, | |
| { PPC::FMUL_rec, PPC::FMUL }, | |
| { PPC::FNABSD_rec, PPC::FNABSD }, | |
| { PPC::FNABSS_rec, PPC::FNABSS }, | |
| { PPC::FNEGD_rec, PPC::FNEGD }, | |
| { PPC::FNEGS_rec, PPC::FNEGS }, | |
| { PPC::FNMADDS_rec, PPC::FNMADDS }, | |
| { PPC::FNMADD_rec, PPC::FNMADD }, | |
| { PPC::FNMSUBS_rec, PPC::FNMSUBS }, | |
| { PPC::FNMSUB_rec, PPC::FNMSUB }, | |
| { PPC::FRES_rec, PPC::FRES }, | |
| { PPC::FRE_rec, PPC::FRE }, | |
| { PPC::FRIMD_rec, PPC::FRIMD }, | |
| { PPC::FRIMS_rec, PPC::FRIMS }, | |
| { PPC::FRIND_rec, PPC::FRIND }, | |
| { PPC::FRINS_rec, PPC::FRINS }, | |
| { PPC::FRIPD_rec, PPC::FRIPD }, | |
| { PPC::FRIPS_rec, PPC::FRIPS }, | |
| { PPC::FRIZD_rec, PPC::FRIZD }, | |
| { PPC::FRIZS_rec, PPC::FRIZS }, | |
| { PPC::FRSP_rec, PPC::FRSP }, | |
| { PPC::FRSQRTES_rec, PPC::FRSQRTES }, | |
| { PPC::FRSQRTE_rec, PPC::FRSQRTE }, | |
| { PPC::FSELD_rec, PPC::FSELD }, | |
| { PPC::FSELS_rec, PPC::FSELS }, | |
| { PPC::FSQRTS_rec, PPC::FSQRTS }, | |
| { PPC::FSQRT_rec, PPC::FSQRT }, | |
| { PPC::FSUBS_rec, PPC::FSUBS }, | |
| { PPC::FSUB_rec, PPC::FSUB }, | |
| { PPC::MULHDU_rec, PPC::MULHDU }, | |
| { PPC::MULHD_rec, PPC::MULHD }, | |
| { PPC::MULHWU_rec, PPC::MULHWU }, | |
| { PPC::MULHW_rec, PPC::MULHW }, | |
| { PPC::MULLDO_rec, PPC::MULLDO }, | |
| { PPC::MULLD_rec, PPC::MULLD }, | |
| { PPC::MULLWO_rec, PPC::MULLWO }, | |
| { PPC::MULLW_rec, PPC::MULLW }, | |
| { PPC::NAND8_rec, PPC::NAND8 }, | |
| { PPC::NAND_rec, PPC::NAND }, | |
| { PPC::NEG8O_rec, PPC::NEG8O }, | |
| { PPC::NEG8_rec, PPC::NEG8 }, | |
| { PPC::NEGO_rec, PPC::NEGO }, | |
| { PPC::NEG_rec, PPC::NEG }, | |
| { PPC::NOR8_rec, PPC::NOR8 }, | |
| { PPC::NOR_rec, PPC::NOR }, | |
| { PPC::OR8_rec, PPC::OR8 }, | |
| { PPC::ORC8_rec, PPC::ORC8 }, | |
| { PPC::ORC_rec, PPC::ORC }, | |
| { PPC::OR_rec, PPC::OR }, | |
| { PPC::RLDCL_rec, PPC::RLDCL }, | |
| { PPC::RLDCR_rec, PPC::RLDCR }, | |
| { PPC::RLDICL_32_rec, PPC::RLDICL_32 }, | |
| { PPC::RLDICL_rec, PPC::RLDICL }, | |
| { PPC::RLDICR_rec, PPC::RLDICR }, | |
| { PPC::RLDIC_rec, PPC::RLDIC }, | |
| { PPC::RLDIMI_rec, PPC::RLDIMI }, | |
| { PPC::RLWIMI8_rec, PPC::RLWIMI8 }, | |
| { PPC::RLWIMI_rec, PPC::RLWIMI }, | |
| { PPC::RLWINM8_rec, PPC::RLWINM8 }, | |
| { PPC::RLWINM_rec, PPC::RLWINM }, | |
| { PPC::RLWNM8_rec, PPC::RLWNM8 }, | |
| { PPC::RLWNM_rec, PPC::RLWNM }, | |
| { PPC::SLD_rec, PPC::SLD }, | |
| { PPC::SLW8_rec, PPC::SLW8 }, | |
| { PPC::SLW_rec, PPC::SLW }, | |
| { PPC::SRADI_rec, PPC::SRADI }, | |
| { PPC::SRAD_rec, PPC::SRAD }, | |
| { PPC::SRAWI_rec, PPC::SRAWI }, | |
| { PPC::SRAW_rec, PPC::SRAW }, | |
| { PPC::SRD_rec, PPC::SRD }, | |
| { PPC::SRW8_rec, PPC::SRW8 }, | |
| { PPC::SRW_rec, PPC::SRW }, | |
| { PPC::SUBF8O_rec, PPC::SUBF8O }, | |
| { PPC::SUBF8_rec, PPC::SUBF8 }, | |
| { PPC::SUBFC8O_rec, PPC::SUBFC8O }, | |
| { PPC::SUBFC8_rec, PPC::SUBFC8 }, | |
| { PPC::SUBFCO_rec, PPC::SUBFCO }, | |
| { PPC::SUBFC_rec, PPC::SUBFC }, | |
| { PPC::SUBFE8O_rec, PPC::SUBFE8O }, | |
| { PPC::SUBFE8_rec, PPC::SUBFE8 }, | |
| { PPC::SUBFEO_rec, PPC::SUBFEO }, | |
| { PPC::SUBFE_rec, PPC::SUBFE }, | |
| { PPC::SUBFME8O_rec, PPC::SUBFME8O }, | |
| { PPC::SUBFME8_rec, PPC::SUBFME8 }, | |
| { PPC::SUBFMEO_rec, PPC::SUBFMEO }, | |
| { PPC::SUBFME_rec, PPC::SUBFME }, | |
| { PPC::SUBFO_rec, PPC::SUBFO }, | |
| { PPC::SUBFUS_rec, PPC::SUBFUS }, | |
| { PPC::SUBFZE8O_rec, PPC::SUBFZE8O }, | |
| { PPC::SUBFZE8_rec, PPC::SUBFZE8 }, | |
| { PPC::SUBFZEO_rec, PPC::SUBFZEO }, | |
| { PPC::SUBFZE_rec, PPC::SUBFZE }, | |
| { PPC::SUBF_rec, PPC::SUBF }, | |
| { PPC::VSTRIBL_rec, PPC::VSTRIBL }, | |
| { PPC::VSTRIBR_rec, PPC::VSTRIBR }, | |
| { PPC::VSTRIHL_rec, PPC::VSTRIHL }, | |
| { PPC::VSTRIHR_rec, PPC::VSTRIHR }, | |
| { PPC::XOR8_rec, PPC::XOR8 }, | |
| { PPC::XOR_rec, PPC::XOR }, | |
| }; // End of getNonRecordFormOpcodeTable | |
| unsigned mid; | |
| unsigned start = 0; | |
| unsigned end = 181; | |
| while (start < end) { | |
| mid = start + (end - start) / 2; | |
| if (Opcode == getNonRecordFormOpcodeTable[mid][0]) { | |
| break; | |
| } | |
| if (Opcode < getNonRecordFormOpcodeTable[mid][0]) | |
| end = mid; | |
| else | |
| start = mid + 1; | |
| } | |
| if (start == end) | |
| return -1; // Instruction doesn't exist in this table. | |
| return getNonRecordFormOpcodeTable[mid][1]; | |
| } | |
| // getRecordFormOpcode | |
| LLVM_READONLY | |
| int getRecordFormOpcode(uint16_t Opcode) { | |
| static const uint16_t getRecordFormOpcodeTable[][2] = { | |
| { PPC::ADD4, PPC::ADD4_rec }, | |
| { PPC::ADD4O, PPC::ADD4O_rec }, | |
| { PPC::ADD8, PPC::ADD8_rec }, | |
| { PPC::ADD8O, PPC::ADD8O_rec }, | |
| { PPC::ADDC, PPC::ADDC_rec }, | |
| { PPC::ADDC8, PPC::ADDC8_rec }, | |
| { PPC::ADDC8O, PPC::ADDC8O_rec }, | |
| { PPC::ADDCO, PPC::ADDCO_rec }, | |
| { PPC::ADDE, PPC::ADDE_rec }, | |
| { PPC::ADDE8, PPC::ADDE8_rec }, | |
| { PPC::ADDE8O, PPC::ADDE8O_rec }, | |
| { PPC::ADDEO, PPC::ADDEO_rec }, | |
| { PPC::ADDIC, PPC::ADDIC_rec }, | |
| { PPC::ADDME, PPC::ADDME_rec }, | |
| { PPC::ADDME8, PPC::ADDME8_rec }, | |
| { PPC::ADDME8O, PPC::ADDME8O_rec }, | |
| { PPC::ADDMEO, PPC::ADDMEO_rec }, | |
| { PPC::ADDZE, PPC::ADDZE_rec }, | |
| { PPC::ADDZE8, PPC::ADDZE8_rec }, | |
| { PPC::ADDZE8O, PPC::ADDZE8O_rec }, | |
| { PPC::ADDZEO, PPC::ADDZEO_rec }, | |
| { PPC::AND, PPC::AND_rec }, | |
| { PPC::AND8, PPC::AND8_rec }, | |
| { PPC::ANDC, PPC::ANDC_rec }, | |
| { PPC::ANDC8, PPC::ANDC8_rec }, | |
| { PPC::CNTLZD, PPC::CNTLZD_rec }, | |
| { PPC::CNTLZW, PPC::CNTLZW_rec }, | |
| { PPC::CNTLZW8, PPC::CNTLZW8_rec }, | |
| { PPC::CNTTZD, PPC::CNTTZD_rec }, | |
| { PPC::CNTTZW, PPC::CNTTZW_rec }, | |
| { PPC::CNTTZW8, PPC::CNTTZW8_rec }, | |
| { PPC::DIVD, PPC::DIVD_rec }, | |
| { PPC::DIVDE, PPC::DIVDE_rec }, | |
| { PPC::DIVDEO, PPC::DIVDEO_rec }, | |
| { PPC::DIVDEU, PPC::DIVDEU_rec }, | |
| { PPC::DIVDEUO, PPC::DIVDEUO_rec }, | |
| { PPC::DIVDO, PPC::DIVDO_rec }, | |
| { PPC::DIVDU, PPC::DIVDU_rec }, | |
| { PPC::DIVDUO, PPC::DIVDUO_rec }, | |
| { PPC::DIVW, PPC::DIVW_rec }, | |
| { PPC::DIVWE, PPC::DIVWE_rec }, | |
| { PPC::DIVWEO, PPC::DIVWEO_rec }, | |
| { PPC::DIVWEU, PPC::DIVWEU_rec }, | |
| { PPC::DIVWEUO, PPC::DIVWEUO_rec }, | |
| { PPC::DIVWO, PPC::DIVWO_rec }, | |
| { PPC::DIVWU, PPC::DIVWU_rec }, | |
| { PPC::DIVWUO, PPC::DIVWUO_rec }, | |
| { PPC::EQV, PPC::EQV_rec }, | |
| { PPC::EQV8, PPC::EQV8_rec }, | |
| { PPC::EXTSB, PPC::EXTSB_rec }, | |
| { PPC::EXTSB8, PPC::EXTSB8_rec }, | |
| { PPC::EXTSH, PPC::EXTSH_rec }, | |
| { PPC::EXTSH8, PPC::EXTSH8_rec }, | |
| { PPC::EXTSW, PPC::EXTSW_rec }, | |
| { PPC::EXTSWSLI, PPC::EXTSWSLI_rec }, | |
| { PPC::EXTSWSLI_32_64, PPC::EXTSWSLI_32_64_rec }, | |
| { PPC::EXTSW_32_64, PPC::EXTSW_32_64_rec }, | |
| { PPC::FABSD, PPC::FABSD_rec }, | |
| { PPC::FABSS, PPC::FABSS_rec }, | |
| { PPC::FADD, PPC::FADD_rec }, | |
| { PPC::FADDS, PPC::FADDS_rec }, | |
| { PPC::FCFID, PPC::FCFID_rec }, | |
| { PPC::FCFIDS, PPC::FCFIDS_rec }, | |
| { PPC::FCFIDU, PPC::FCFIDU_rec }, | |
| { PPC::FCFIDUS, PPC::FCFIDUS_rec }, | |
| { PPC::FCPSGND, PPC::FCPSGND_rec }, | |
| { PPC::FCPSGNS, PPC::FCPSGNS_rec }, | |
| { PPC::FCTID, PPC::FCTID_rec }, | |
| { PPC::FCTIDU, PPC::FCTIDU_rec }, | |
| { PPC::FCTIDUZ, PPC::FCTIDUZ_rec }, | |
| { PPC::FCTIDZ, PPC::FCTIDZ_rec }, | |
| { PPC::FCTIW, PPC::FCTIW_rec }, | |
| { PPC::FCTIWU, PPC::FCTIWU_rec }, | |
| { PPC::FCTIWUZ, PPC::FCTIWUZ_rec }, | |
| { PPC::FCTIWZ, PPC::FCTIWZ_rec }, | |
| { PPC::FDIV, PPC::FDIV_rec }, | |
| { PPC::FDIVS, PPC::FDIVS_rec }, | |
| { PPC::FMADD, PPC::FMADD_rec }, | |
| { PPC::FMADDS, PPC::FMADDS_rec }, | |
| { PPC::FMR, PPC::FMR_rec }, | |
| { PPC::FMSUB, PPC::FMSUB_rec }, | |
| { PPC::FMSUBS, PPC::FMSUBS_rec }, | |
| { PPC::FMUL, PPC::FMUL_rec }, | |
| { PPC::FMULS, PPC::FMULS_rec }, | |
| { PPC::FNABSD, PPC::FNABSD_rec }, | |
| { PPC::FNABSS, PPC::FNABSS_rec }, | |
| { PPC::FNEGD, PPC::FNEGD_rec }, | |
| { PPC::FNEGS, PPC::FNEGS_rec }, | |
| { PPC::FNMADD, PPC::FNMADD_rec }, | |
| { PPC::FNMADDS, PPC::FNMADDS_rec }, | |
| { PPC::FNMSUB, PPC::FNMSUB_rec }, | |
| { PPC::FNMSUBS, PPC::FNMSUBS_rec }, | |
| { PPC::FRE, PPC::FRE_rec }, | |
| { PPC::FRES, PPC::FRES_rec }, | |
| { PPC::FRIMD, PPC::FRIMD_rec }, | |
| { PPC::FRIMS, PPC::FRIMS_rec }, | |
| { PPC::FRIND, PPC::FRIND_rec }, | |
| { PPC::FRINS, PPC::FRINS_rec }, | |
| { PPC::FRIPD, PPC::FRIPD_rec }, | |
| { PPC::FRIPS, PPC::FRIPS_rec }, | |
| { PPC::FRIZD, PPC::FRIZD_rec }, | |
| { PPC::FRIZS, PPC::FRIZS_rec }, | |
| { PPC::FRSP, PPC::FRSP_rec }, | |
| { PPC::FRSQRTE, PPC::FRSQRTE_rec }, | |
| { PPC::FRSQRTES, PPC::FRSQRTES_rec }, | |
| { PPC::FSELD, PPC::FSELD_rec }, | |
| { PPC::FSELS, PPC::FSELS_rec }, | |
| { PPC::FSQRT, PPC::FSQRT_rec }, | |
| { PPC::FSQRTS, PPC::FSQRTS_rec }, | |
| { PPC::FSUB, PPC::FSUB_rec }, | |
| { PPC::FSUBS, PPC::FSUBS_rec }, | |
| { PPC::MULHD, PPC::MULHD_rec }, | |
| { PPC::MULHDU, PPC::MULHDU_rec }, | |
| { PPC::MULHW, PPC::MULHW_rec }, | |
| { PPC::MULHWU, PPC::MULHWU_rec }, | |
| { PPC::MULLD, PPC::MULLD_rec }, | |
| { PPC::MULLDO, PPC::MULLDO_rec }, | |
| { PPC::MULLW, PPC::MULLW_rec }, | |
| { PPC::MULLWO, PPC::MULLWO_rec }, | |
| { PPC::NAND, PPC::NAND_rec }, | |
| { PPC::NAND8, PPC::NAND8_rec }, | |
| { PPC::NEG, PPC::NEG_rec }, | |
| { PPC::NEG8, PPC::NEG8_rec }, | |
| { PPC::NEG8O, PPC::NEG8O_rec }, | |
| { PPC::NEGO, PPC::NEGO_rec }, | |
| { PPC::NOR, PPC::NOR_rec }, | |
| { PPC::NOR8, PPC::NOR8_rec }, | |
| { PPC::OR, PPC::OR_rec }, | |
| { PPC::OR8, PPC::OR8_rec }, | |
| { PPC::ORC, PPC::ORC_rec }, | |
| { PPC::ORC8, PPC::ORC8_rec }, | |
| { PPC::RLDCL, PPC::RLDCL_rec }, | |
| { PPC::RLDCR, PPC::RLDCR_rec }, | |
| { PPC::RLDIC, PPC::RLDIC_rec }, | |
| { PPC::RLDICL, PPC::RLDICL_rec }, | |
| { PPC::RLDICL_32, PPC::RLDICL_32_rec }, | |
| { PPC::RLDICR, PPC::RLDICR_rec }, | |
| { PPC::RLDIMI, PPC::RLDIMI_rec }, | |
| { PPC::RLWIMI, PPC::RLWIMI_rec }, | |
| { PPC::RLWIMI8, PPC::RLWIMI8_rec }, | |
| { PPC::RLWINM, PPC::RLWINM_rec }, | |
| { PPC::RLWINM8, PPC::RLWINM8_rec }, | |
| { PPC::RLWNM, PPC::RLWNM_rec }, | |
| { PPC::RLWNM8, PPC::RLWNM8_rec }, | |
| { PPC::SLD, PPC::SLD_rec }, | |
| { PPC::SLW, PPC::SLW_rec }, | |
| { PPC::SLW8, PPC::SLW8_rec }, | |
| { PPC::SRAD, PPC::SRAD_rec }, | |
| { PPC::SRADI, PPC::SRADI_rec }, | |
| { PPC::SRAW, PPC::SRAW_rec }, | |
| { PPC::SRAWI, PPC::SRAWI_rec }, | |
| { PPC::SRD, PPC::SRD_rec }, | |
| { PPC::SRW, PPC::SRW_rec }, | |
| { PPC::SRW8, PPC::SRW8_rec }, | |
| { PPC::SUBF, PPC::SUBF_rec }, | |
| { PPC::SUBF8, PPC::SUBF8_rec }, | |
| { PPC::SUBF8O, PPC::SUBF8O_rec }, | |
| { PPC::SUBFC, PPC::SUBFC_rec }, | |
| { PPC::SUBFC8, PPC::SUBFC8_rec }, | |
| { PPC::SUBFC8O, PPC::SUBFC8O_rec }, | |
| { PPC::SUBFCO, PPC::SUBFCO_rec }, | |
| { PPC::SUBFE, PPC::SUBFE_rec }, | |
| { PPC::SUBFE8, PPC::SUBFE8_rec }, | |
| { PPC::SUBFE8O, PPC::SUBFE8O_rec }, | |
| { PPC::SUBFEO, PPC::SUBFEO_rec }, | |
| { PPC::SUBFME, PPC::SUBFME_rec }, | |
| { PPC::SUBFME8, PPC::SUBFME8_rec }, | |
| { PPC::SUBFME8O, PPC::SUBFME8O_rec }, | |
| { PPC::SUBFMEO, PPC::SUBFMEO_rec }, | |
| { PPC::SUBFO, PPC::SUBFO_rec }, | |
| { PPC::SUBFUS, PPC::SUBFUS_rec }, | |
| { PPC::SUBFZE, PPC::SUBFZE_rec }, | |
| { PPC::SUBFZE8, PPC::SUBFZE8_rec }, | |
| { PPC::SUBFZE8O, PPC::SUBFZE8O_rec }, | |
| { PPC::SUBFZEO, PPC::SUBFZEO_rec }, | |
| { PPC::VSTRIBL, PPC::VSTRIBL_rec }, | |
| { PPC::VSTRIBR, PPC::VSTRIBR_rec }, | |
| { PPC::VSTRIHL, PPC::VSTRIHL_rec }, | |
| { PPC::VSTRIHR, PPC::VSTRIHR_rec }, | |
| { PPC::XOR, PPC::XOR_rec }, | |
| { PPC::XOR8, PPC::XOR8_rec }, | |
| }; // End of getRecordFormOpcodeTable | |
| unsigned mid; | |
| unsigned start = 0; | |
| unsigned end = 181; | |
| while (start < end) { | |
| mid = start + (end - start) / 2; | |
| if (Opcode == getRecordFormOpcodeTable[mid][0]) { | |
| break; | |
| } | |
| if (Opcode < getRecordFormOpcodeTable[mid][0]) | |
| end = mid; | |
| else | |
| start = mid + 1; | |
| } | |
| if (start == end) | |
| return -1; // Instruction doesn't exist in this table. | |
| return getRecordFormOpcodeTable[mid][1]; | |
| } | |
| } // end namespace PPC | |
| } // end namespace llvm | |
| #endif // GET_INSTRMAP_INFO | |