| //===-- VEISelLowering.h - VE DAG Lowering Interface ------------*- C++ -*-===// | |
| // | |
| // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | |
| // See https://llvm.org/LICENSE.txt for license information. | |
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | |
| // | |
| //===----------------------------------------------------------------------===// | |
| // | |
| // This file defines the interfaces that VE uses to lower LLVM code into a | |
| // selection DAG. | |
| // | |
| //===----------------------------------------------------------------------===// | |
| #ifndef LLVM_LIB_TARGET_VE_VEISELLOWERING_H | |
| #define LLVM_LIB_TARGET_VE_VEISELLOWERING_H | |
| #include "VE.h" | |
| #include "llvm/CodeGen/TargetLowering.h" | |
| namespace llvm { | |
| class VESubtarget; | |
| namespace VEISD { | |
| enum NodeType : unsigned { | |
| FIRST_NUMBER = ISD::BUILTIN_OP_END, | |
| RET_FLAG, // Return with a flag operand. | |
| }; | |
| } | |
| class VETargetLowering : public TargetLowering { | |
| const VESubtarget *Subtarget; | |
| public: | |
| VETargetLowering(const TargetMachine &TM, const VESubtarget &STI); | |
| const char *getTargetNodeName(unsigned Opcode) const override; | |
| Register getRegisterByName(const char *RegName, LLT VT, | |
| const MachineFunction &MF) const override; | |
| /// getSetCCResultType - Return the ISD::SETCC ValueType | |
| EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, | |
| EVT VT) const override; | |
| SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, | |
| bool isVarArg, | |
| const SmallVectorImpl<ISD::InputArg> &Ins, | |
| const SDLoc &dl, SelectionDAG &DAG, | |
| SmallVectorImpl<SDValue> &InVals) const override; | |
| bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, | |
| bool isVarArg, | |
| const SmallVectorImpl<ISD::OutputArg> &ArgsFlags, | |
| LLVMContext &Context) const override; | |
| SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, | |
| const SmallVectorImpl<ISD::OutputArg> &Outs, | |
| const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl, | |
| SelectionDAG &DAG) const override; | |
| }; | |
| } // namespace llvm | |
| #endif // VE_ISELLOWERING_H |