| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ | |
| |* *| | |
| |* Machine Code Emitter *| | |
| |* *| | |
| |* Automatically generated file, do not edit! *| | |
| |* *| | |
| \*===----------------------------------------------------------------------===*/ | |
| uint64_t PPCMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, | |
| SmallVectorImpl<MCFixup> &Fixups, | |
| const MCSubtargetInfo &STI) const { | |
| static const uint64_t InstBits[] = { | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(0), | |
| UINT64_C(2080375316), // ADD4 | |
| UINT64_C(2080376340), // ADD4O | |
| UINT64_C(2080376341), // ADD4O_rec | |
| UINT64_C(2080375316), // ADD4TLS | |
| UINT64_C(2080375317), // ADD4_rec | |
| UINT64_C(2080375316), // ADD8 | |
| UINT64_C(2080376340), // ADD8O | |
| UINT64_C(2080376341), // ADD8O_rec | |
| UINT64_C(2080375316), // ADD8TLS | |
| UINT64_C(2080375316), // ADD8TLS_ | |
| UINT64_C(2080375317), // ADD8_rec | |
| UINT64_C(2080374804), // ADDC | |
| UINT64_C(2080374804), // ADDC8 | |
| UINT64_C(2080375828), // ADDC8O | |
| UINT64_C(2080375829), // ADDC8O_rec | |
| UINT64_C(2080374805), // ADDC8_rec | |
| UINT64_C(2080375828), // ADDCO | |
| UINT64_C(2080375829), // ADDCO_rec | |
| UINT64_C(2080374805), // ADDC_rec | |
| UINT64_C(2080375060), // ADDE | |
| UINT64_C(2080375060), // ADDE8 | |
| UINT64_C(2080376084), // ADDE8O | |
| UINT64_C(2080376085), // ADDE8O_rec | |
| UINT64_C(2080375061), // ADDE8_rec | |
| UINT64_C(2080376084), // ADDEO | |
| UINT64_C(2080376085), // ADDEO_rec | |
| UINT64_C(2080375061), // ADDE_rec | |
| UINT64_C(939524096), // ADDI | |
| UINT64_C(939524096), // ADDI8 | |
| UINT64_C(805306368), // ADDIC | |
| UINT64_C(805306368), // ADDIC8 | |
| UINT64_C(872415232), // ADDIC_rec | |
| UINT64_C(1006632960), // ADDIS | |
| UINT64_C(1006632960), // ADDIS8 | |
| UINT64_C(0), // ADDISdtprelHA | |
| UINT64_C(0), // ADDISdtprelHA32 | |
| UINT64_C(0), // ADDISgotTprelHA | |
| UINT64_C(0), // ADDIStlsgdHA | |
| UINT64_C(0), // ADDIStlsldHA | |
| UINT64_C(0), // ADDIStocHA | |
| UINT64_C(0), // ADDIStocHA8 | |
| UINT64_C(0), // ADDIdtprelL | |
| UINT64_C(0), // ADDIdtprelL32 | |
| UINT64_C(0), // ADDItlsgdL | |
| UINT64_C(0), // ADDItlsgdL32 | |
| UINT64_C(0), // ADDItlsgdLADDR | |
| UINT64_C(0), // ADDItlsgdLADDR32 | |
| UINT64_C(0), // ADDItlsldL | |
| UINT64_C(0), // ADDItlsldL32 | |
| UINT64_C(0), // ADDItlsldLADDR | |
| UINT64_C(0), // ADDItlsldLADDR32 | |
| UINT64_C(0), // ADDItocL | |
| UINT64_C(2080375252), // ADDME | |
| UINT64_C(2080375252), // ADDME8 | |
| UINT64_C(2080376276), // ADDME8O | |
| UINT64_C(2080376277), // ADDME8O_rec | |
| UINT64_C(2080375253), // ADDME8_rec | |
| UINT64_C(2080376276), // ADDMEO | |
| UINT64_C(2080376277), // ADDMEO_rec | |
| UINT64_C(2080375253), // ADDME_rec | |
| UINT64_C(1275068420), // ADDPCIS | |
| UINT64_C(2080375188), // ADDZE | |
| UINT64_C(2080375188), // ADDZE8 | |
| UINT64_C(2080376212), // ADDZE8O | |
| UINT64_C(2080376213), // ADDZE8O_rec | |
| UINT64_C(2080375189), // ADDZE8_rec | |
| UINT64_C(2080376212), // ADDZEO | |
| UINT64_C(2080376213), // ADDZEO_rec | |
| UINT64_C(2080375189), // ADDZE_rec | |
| UINT64_C(0), // ADJCALLSTACKDOWN | |
| UINT64_C(0), // ADJCALLSTACKUP | |
| UINT64_C(2080374840), // AND | |
| UINT64_C(2080374840), // AND8 | |
| UINT64_C(2080374841), // AND8_rec | |
| UINT64_C(2080374904), // ANDC | |
| UINT64_C(2080374904), // ANDC8 | |
| UINT64_C(2080374905), // ANDC8_rec | |
| UINT64_C(2080374905), // ANDC_rec | |
| UINT64_C(1879048192), // ANDI8_rec | |
| UINT64_C(1946157056), // ANDIS8_rec | |
| UINT64_C(1946157056), // ANDIS_rec | |
| UINT64_C(1879048192), // ANDI_rec | |
| UINT64_C(0), // ANDI_rec_1_EQ_BIT | |
| UINT64_C(0), // ANDI_rec_1_EQ_BIT8 | |
| UINT64_C(0), // ANDI_rec_1_GT_BIT | |
| UINT64_C(0), // ANDI_rec_1_GT_BIT8 | |
| UINT64_C(2080374841), // AND_rec | |
| UINT64_C(0), // ATOMIC_CMP_SWAP_I16 | |
| UINT64_C(0), // ATOMIC_CMP_SWAP_I32 | |
| UINT64_C(0), // ATOMIC_CMP_SWAP_I64 | |
| UINT64_C(0), // ATOMIC_CMP_SWAP_I8 | |
| UINT64_C(0), // ATOMIC_LOAD_ADD_I16 | |
| UINT64_C(0), // ATOMIC_LOAD_ADD_I32 | |
| UINT64_C(0), // ATOMIC_LOAD_ADD_I64 | |
| UINT64_C(0), // ATOMIC_LOAD_ADD_I8 | |
| UINT64_C(0), // ATOMIC_LOAD_AND_I16 | |
| UINT64_C(0), // ATOMIC_LOAD_AND_I32 | |
| UINT64_C(0), // ATOMIC_LOAD_AND_I64 | |
| UINT64_C(0), // ATOMIC_LOAD_AND_I8 | |
| UINT64_C(0), // ATOMIC_LOAD_MAX_I16 | |
| UINT64_C(0), // ATOMIC_LOAD_MAX_I32 | |
| UINT64_C(0), // ATOMIC_LOAD_MAX_I64 | |
| UINT64_C(0), // ATOMIC_LOAD_MAX_I8 | |
| UINT64_C(0), // ATOMIC_LOAD_MIN_I16 | |
| UINT64_C(0), // ATOMIC_LOAD_MIN_I32 | |
| UINT64_C(0), // ATOMIC_LOAD_MIN_I64 | |
| UINT64_C(0), // ATOMIC_LOAD_MIN_I8 | |
| UINT64_C(0), // ATOMIC_LOAD_NAND_I16 | |
| UINT64_C(0), // ATOMIC_LOAD_NAND_I32 | |
| UINT64_C(0), // ATOMIC_LOAD_NAND_I64 | |
| UINT64_C(0), // ATOMIC_LOAD_NAND_I8 | |
| UINT64_C(0), // ATOMIC_LOAD_OR_I16 | |
| UINT64_C(0), // ATOMIC_LOAD_OR_I32 | |
| UINT64_C(0), // ATOMIC_LOAD_OR_I64 | |
| UINT64_C(0), // ATOMIC_LOAD_OR_I8 | |
| UINT64_C(0), // ATOMIC_LOAD_SUB_I16 | |
| UINT64_C(0), // ATOMIC_LOAD_SUB_I32 | |
| UINT64_C(0), // ATOMIC_LOAD_SUB_I64 | |
| UINT64_C(0), // ATOMIC_LOAD_SUB_I8 | |
| UINT64_C(0), // ATOMIC_LOAD_UMAX_I16 | |
| UINT64_C(0), // ATOMIC_LOAD_UMAX_I32 | |
| UINT64_C(0), // ATOMIC_LOAD_UMAX_I64 | |
| UINT64_C(0), // ATOMIC_LOAD_UMAX_I8 | |
| UINT64_C(0), // ATOMIC_LOAD_UMIN_I16 | |
| UINT64_C(0), // ATOMIC_LOAD_UMIN_I32 | |
| UINT64_C(0), // ATOMIC_LOAD_UMIN_I64 | |
| UINT64_C(0), // ATOMIC_LOAD_UMIN_I8 | |
| UINT64_C(0), // ATOMIC_LOAD_XOR_I16 | |
| UINT64_C(0), // ATOMIC_LOAD_XOR_I32 | |
| UINT64_C(0), // ATOMIC_LOAD_XOR_I64 | |
| UINT64_C(0), // ATOMIC_LOAD_XOR_I8 | |
| UINT64_C(0), // ATOMIC_SWAP_I16 | |
| UINT64_C(0), // ATOMIC_SWAP_I32 | |
| UINT64_C(0), // ATOMIC_SWAP_I64 | |
| UINT64_C(0), // ATOMIC_SWAP_I8 | |
| UINT64_C(512), // ATTN | |
| UINT64_C(1207959552), // B | |
| UINT64_C(1207959554), // BA | |
| UINT64_C(1098907648), // BC | |
| UINT64_C(1073741824), // BCC | |
| UINT64_C(1073741826), // BCCA | |
| UINT64_C(1275069472), // BCCCTR | |
| UINT64_C(1275069472), // BCCCTR8 | |
| UINT64_C(1275069473), // BCCCTRL | |
| UINT64_C(1275069473), // BCCCTRL8 | |
| UINT64_C(1073741825), // BCCL | |
| UINT64_C(1073741827), // BCCLA | |
| UINT64_C(1275068448), // BCCLR | |
| UINT64_C(1275068449), // BCCLRL | |
| UINT64_C(1300235296), // BCCTR | |
| UINT64_C(1300235296), // BCCTR8 | |
| UINT64_C(1283458080), // BCCTR8n | |
| UINT64_C(1300235297), // BCCTRL | |
| UINT64_C(1300235297), // BCCTRL8 | |
| UINT64_C(1283458081), // BCCTRL8n | |
| UINT64_C(1283458081), // BCCTRLn | |
| UINT64_C(1283458080), // BCCTRn | |
| UINT64_C(268895617), // BCDCFN_rec | |
| UINT64_C(268567937), // BCDCFSQ_rec | |
| UINT64_C(268830081), // BCDCFZ_rec | |
| UINT64_C(268436289), // BCDCPSGN_rec | |
| UINT64_C(268764545), // BCDCTN_rec | |
| UINT64_C(268436865), // BCDCTSQ_rec | |
| UINT64_C(268699009), // BCDCTZ_rec | |
| UINT64_C(270468481), // BCDSETSGN_rec | |
| UINT64_C(268436929), // BCDSR_rec | |
| UINT64_C(268436673), // BCDS_rec | |
| UINT64_C(268436737), // BCDTRUNC_rec | |
| UINT64_C(268436609), // BCDUS_rec | |
| UINT64_C(268436801), // BCDUTRUNC_rec | |
| UINT64_C(1098907649), // BCL | |
| UINT64_C(1300234272), // BCLR | |
| UINT64_C(1300234273), // BCLRL | |
| UINT64_C(1283457057), // BCLRLn | |
| UINT64_C(1283457056), // BCLRn | |
| UINT64_C(1117716481), // BCLalways | |
| UINT64_C(1082130433), // BCLn | |
| UINT64_C(1317012512), // BCTR | |
| UINT64_C(1317012512), // BCTR8 | |
| UINT64_C(1317012513), // BCTRL | |
| UINT64_C(1317012513), // BCTRL8 | |
| UINT64_C(5656525675654283264), // BCTRL8_LDinto_toc | |
| UINT64_C(5656525673909452800), // BCTRL_LWZinto_toc | |
| UINT64_C(1082130432), // BCn | |
| UINT64_C(1107296256), // BDNZ | |
| UINT64_C(1107296256), // BDNZ8 | |
| UINT64_C(1107296258), // BDNZA | |
| UINT64_C(1124073474), // BDNZAm | |
| UINT64_C(1126170626), // BDNZAp | |
| UINT64_C(1107296257), // BDNZL | |
| UINT64_C(1107296259), // BDNZLA | |
| UINT64_C(1124073475), // BDNZLAm | |
| UINT64_C(1126170627), // BDNZLAp | |
| UINT64_C(1308622880), // BDNZLR | |
| UINT64_C(1308622880), // BDNZLR8 | |
| UINT64_C(1308622881), // BDNZLRL | |
| UINT64_C(1325400097), // BDNZLRLm | |
| UINT64_C(1327497249), // BDNZLRLp | |
| UINT64_C(1325400096), // BDNZLRm | |
| UINT64_C(1327497248), // BDNZLRp | |
| UINT64_C(1124073473), // BDNZLm | |
| UINT64_C(1126170625), // BDNZLp | |
| UINT64_C(1124073472), // BDNZm | |
| UINT64_C(1126170624), // BDNZp | |
| UINT64_C(1111490560), // BDZ | |
| UINT64_C(1111490560), // BDZ8 | |
| UINT64_C(1111490562), // BDZA | |
| UINT64_C(1128267778), // BDZAm | |
| UINT64_C(1130364930), // BDZAp | |
| UINT64_C(1111490561), // BDZL | |
| UINT64_C(1111490563), // BDZLA | |
| UINT64_C(1128267779), // BDZLAm | |
| UINT64_C(1130364931), // BDZLAp | |
| UINT64_C(1312817184), // BDZLR | |
| UINT64_C(1312817184), // BDZLR8 | |
| UINT64_C(1312817185), // BDZLRL | |
| UINT64_C(1329594401), // BDZLRLm | |
| UINT64_C(1331691553), // BDZLRLp | |
| UINT64_C(1329594400), // BDZLRm | |
| UINT64_C(1331691552), // BDZLRp | |
| UINT64_C(1128267777), // BDZLm | |
| UINT64_C(1130364929), // BDZLp | |
| UINT64_C(1128267776), // BDZm | |
| UINT64_C(1130364928), // BDZp | |
| UINT64_C(1207959553), // BL | |
| UINT64_C(1207959553), // BL8 | |
| UINT64_C(5188146776636391424), // BL8_NOP | |
| UINT64_C(5188146776636391424), // BL8_NOP_TLS | |
| UINT64_C(1207959553), // BL8_TLS | |
| UINT64_C(1207959553), // BL8_TLS_ | |
| UINT64_C(1207959555), // BLA | |
| UINT64_C(1207959555), // BLA8 | |
| UINT64_C(5188146785226326016), // BLA8_NOP | |
| UINT64_C(1317011488), // BLR | |
| UINT64_C(1317011488), // BLR8 | |
| UINT64_C(1317011489), // BLRL | |
| UINT64_C(5188146776636391424), // BL_NOP | |
| UINT64_C(1207959553), // BL_TLS | |
| UINT64_C(2080375288), // BPERMD | |
| UINT64_C(268435983), // BRINC | |
| UINT64_C(2080375644), // CLRBHRB | |
| UINT64_C(2080375800), // CMPB | |
| UINT64_C(2080375800), // CMPB8 | |
| UINT64_C(2082471936), // CMPD | |
| UINT64_C(740294656), // CMPDI | |
| UINT64_C(2080375232), // CMPEQB | |
| UINT64_C(2082472000), // CMPLD | |
| UINT64_C(673185792), // CMPLDI | |
| UINT64_C(2080374848), // CMPLW | |
| UINT64_C(671088640), // CMPLWI | |
| UINT64_C(2080375168), // CMPRB | |
| UINT64_C(2080375168), // CMPRB8 | |
| UINT64_C(2080374784), // CMPW | |
| UINT64_C(738197504), // CMPWI | |
| UINT64_C(2080374900), // CNTLZD | |
| UINT64_C(2080374901), // CNTLZD_rec | |
| UINT64_C(2080374836), // CNTLZW | |
| UINT64_C(2080374836), // CNTLZW8 | |
| UINT64_C(2080374837), // CNTLZW8_rec | |
| UINT64_C(2080374837), // CNTLZW_rec | |
| UINT64_C(2080375924), // CNTTZD | |
| UINT64_C(2080375925), // CNTTZD_rec | |
| UINT64_C(2080375860), // CNTTZW | |
| UINT64_C(2080375860), // CNTTZW8 | |
| UINT64_C(2080375861), // CNTTZW8_rec | |
| UINT64_C(2080375861), // CNTTZW_rec | |
| UINT64_C(2080376460), // CP_ABORT | |
| UINT64_C(2080376332), // CP_COPY | |
| UINT64_C(2080376332), // CP_COPY8 | |
| UINT64_C(2080376588), // CP_PASTE | |
| UINT64_C(2080376588), // CP_PASTE8 | |
| UINT64_C(2080376589), // CP_PASTE8_rec | |
| UINT64_C(2080376589), // CP_PASTE_rec | |
| UINT64_C(1288057410), // CR6SET | |
| UINT64_C(1288057218), // CR6UNSET | |
| UINT64_C(1275068930), // CRAND | |
| UINT64_C(1275068674), // CRANDC | |
| UINT64_C(1275068994), // CREQV | |
| UINT64_C(1275068866), // CRNAND | |
| UINT64_C(1275068482), // CRNOR | |
| UINT64_C(1275069314), // CROR | |
| UINT64_C(1275069250), // CRORC | |
| UINT64_C(1275068994), // CRSET | |
| UINT64_C(1275068802), // CRUNSET | |
| UINT64_C(1275068802), // CRXOR | |
| UINT64_C(1073741824), // CTRL_DEP | |
| UINT64_C(2080376294), // DARN | |
| UINT64_C(2080376300), // DCBA | |
| UINT64_C(2080374956), // DCBF | |
| UINT64_C(2080375038), // DCBFEP | |
| UINT64_C(2080375724), // DCBI | |
| UINT64_C(2080374892), // DCBST | |
| UINT64_C(2080374910), // DCBSTEP | |
| UINT64_C(2080375340), // DCBT | |
| UINT64_C(2080375422), // DCBTEP | |
| UINT64_C(2080375276), // DCBTST | |
| UINT64_C(2080375294), // DCBTSTEP | |
| UINT64_C(2080376812), // DCBZ | |
| UINT64_C(2080376830), // DCBZEP | |
| UINT64_C(2082473964), // DCBZL | |
| UINT64_C(2082473982), // DCBZLEP | |
| UINT64_C(2080375692), // DCCCI | |
| UINT64_C(2080375762), // DIVD | |
| UINT64_C(2080375634), // DIVDE | |
| UINT64_C(2080376658), // DIVDEO | |
| UINT64_C(2080376659), // DIVDEO_rec | |
| UINT64_C(2080375570), // DIVDEU | |
| UINT64_C(2080376594), // DIVDEUO | |
| UINT64_C(2080376595), // DIVDEUO_rec | |
| UINT64_C(2080375571), // DIVDEU_rec | |
| UINT64_C(2080375635), // DIVDE_rec | |
| UINT64_C(2080376786), // DIVDO | |
| UINT64_C(2080376787), // DIVDO_rec | |
| UINT64_C(2080375698), // DIVDU | |
| UINT64_C(2080376722), // DIVDUO | |
| UINT64_C(2080376723), // DIVDUO_rec | |
| UINT64_C(2080375699), // DIVDU_rec | |
| UINT64_C(2080375763), // DIVD_rec | |
| UINT64_C(2080375766), // DIVW | |
| UINT64_C(2080375638), // DIVWE | |
| UINT64_C(2080376662), // DIVWEO | |
| UINT64_C(2080376663), // DIVWEO_rec | |
| UINT64_C(2080375574), // DIVWEU | |
| UINT64_C(2080376598), // DIVWEUO | |
| UINT64_C(2080376599), // DIVWEUO_rec | |
| UINT64_C(2080375575), // DIVWEU_rec | |
| UINT64_C(2080375639), // DIVWE_rec | |
| UINT64_C(2080376790), // DIVWO | |
| UINT64_C(2080376791), // DIVWO_rec | |
| UINT64_C(2080375702), // DIVWU | |
| UINT64_C(2080376726), // DIVWUO | |
| UINT64_C(2080376727), // DIVWUO_rec | |
| UINT64_C(2080375703), // DIVWU_rec | |
| UINT64_C(2080375767), // DIVW_rec | |
| UINT64_C(2080376428), // DSS | |
| UINT64_C(2113930860), // DSSALL | |
| UINT64_C(2080375468), // DST | |
| UINT64_C(2080375468), // DST64 | |
| UINT64_C(2080375532), // DSTST | |
| UINT64_C(2080375532), // DSTST64 | |
| UINT64_C(2113929964), // DSTSTT | |
| UINT64_C(2113929964), // DSTSTT64 | |
| UINT64_C(2113929900), // DSTT | |
| UINT64_C(2113929900), // DSTT64 | |
| UINT64_C(0), // DYNALLOC | |
| UINT64_C(0), // DYNALLOC8 | |
| UINT64_C(0), // DYNAREAOFFSET | |
| UINT64_C(0), // DYNAREAOFFSET8 | |
| UINT64_C(268436196), // EFDABS | |
| UINT64_C(268436192), // EFDADD | |
| UINT64_C(268436207), // EFDCFS | |
| UINT64_C(268436211), // EFDCFSF | |
| UINT64_C(268436209), // EFDCFSI | |
| UINT64_C(268436195), // EFDCFSID | |
| UINT64_C(268436210), // EFDCFUF | |
| UINT64_C(268436208), // EFDCFUI | |
| UINT64_C(268436194), // EFDCFUID | |
| UINT64_C(268436206), // EFDCMPEQ | |
| UINT64_C(268436204), // EFDCMPGT | |
| UINT64_C(268436205), // EFDCMPLT | |
| UINT64_C(268436215), // EFDCTSF | |
| UINT64_C(268436213), // EFDCTSI | |
| UINT64_C(268436203), // EFDCTSIDZ | |
| UINT64_C(268436218), // EFDCTSIZ | |
| UINT64_C(268436214), // EFDCTUF | |
| UINT64_C(268436212), // EFDCTUI | |
| UINT64_C(268436202), // EFDCTUIDZ | |
| UINT64_C(268436216), // EFDCTUIZ | |
| UINT64_C(268436201), // EFDDIV | |
| UINT64_C(268436200), // EFDMUL | |
| UINT64_C(268436197), // EFDNABS | |
| UINT64_C(268436198), // EFDNEG | |
| UINT64_C(268436193), // EFDSUB | |
| UINT64_C(268436222), // EFDTSTEQ | |
| UINT64_C(268436220), // EFDTSTGT | |
| UINT64_C(268436221), // EFDTSTLT | |
| UINT64_C(268436164), // EFSABS | |
| UINT64_C(268436160), // EFSADD | |
| UINT64_C(268436175), // EFSCFD | |
| UINT64_C(268436179), // EFSCFSF | |
| UINT64_C(268436177), // EFSCFSI | |
| UINT64_C(268436178), // EFSCFUF | |
| UINT64_C(268436176), // EFSCFUI | |
| UINT64_C(268436174), // EFSCMPEQ | |
| UINT64_C(268436172), // EFSCMPGT | |
| UINT64_C(268436173), // EFSCMPLT | |
| UINT64_C(268436183), // EFSCTSF | |
| UINT64_C(268436181), // EFSCTSI | |
| UINT64_C(268436186), // EFSCTSIZ | |
| UINT64_C(268436182), // EFSCTUF | |
| UINT64_C(268436180), // EFSCTUI | |
| UINT64_C(268436184), // EFSCTUIZ | |
| UINT64_C(268436169), // EFSDIV | |
| UINT64_C(268436168), // EFSMUL | |
| UINT64_C(268436165), // EFSNABS | |
| UINT64_C(268436166), // EFSNEG | |
| UINT64_C(268436161), // EFSSUB | |
| UINT64_C(268436190), // EFSTSTEQ | |
| UINT64_C(268436188), // EFSTSTGT | |
| UINT64_C(268436189), // EFSTSTLT | |
| UINT64_C(0), // EH_SjLj_LongJmp32 | |
| UINT64_C(0), // EH_SjLj_LongJmp64 | |
| UINT64_C(0), // EH_SjLj_SetJmp32 | |
| UINT64_C(0), // EH_SjLj_SetJmp64 | |
| UINT64_C(0), // EH_SjLj_Setup | |
| UINT64_C(2080375352), // EQV | |
| UINT64_C(2080375352), // EQV8 | |
| UINT64_C(2080375353), // EQV8_rec | |
| UINT64_C(2080375353), // EQV_rec | |
| UINT64_C(268435976), // EVABS | |
| UINT64_C(268435970), // EVADDIW | |
| UINT64_C(268436681), // EVADDSMIAAW | |
| UINT64_C(268436673), // EVADDSSIAAW | |
| UINT64_C(268436680), // EVADDUMIAAW | |
| UINT64_C(268436672), // EVADDUSIAAW | |
| UINT64_C(268435968), // EVADDW | |
| UINT64_C(268435985), // EVAND | |
| UINT64_C(268435986), // EVANDC | |
| UINT64_C(268436020), // EVCMPEQ | |
| UINT64_C(268436017), // EVCMPGTS | |
| UINT64_C(268436016), // EVCMPGTU | |
| UINT64_C(268436019), // EVCMPLTS | |
| UINT64_C(268436018), // EVCMPLTU | |
| UINT64_C(268435982), // EVCNTLSW | |
| UINT64_C(268435981), // EVCNTLZW | |
| UINT64_C(268436678), // EVDIVWS | |
| UINT64_C(268436679), // EVDIVWU | |
| UINT64_C(268435993), // EVEQV | |
| UINT64_C(268435978), // EVEXTSB | |
| UINT64_C(268435979), // EVEXTSH | |
| UINT64_C(268436100), // EVFSABS | |
| UINT64_C(268436096), // EVFSADD | |
| UINT64_C(268436115), // EVFSCFSF | |
| UINT64_C(268436113), // EVFSCFSI | |
| UINT64_C(268436114), // EVFSCFUF | |
| UINT64_C(268436106), // EVFSCFUI | |
| UINT64_C(268436110), // EVFSCMPEQ | |
| UINT64_C(268436108), // EVFSCMPGT | |
| UINT64_C(268436109), // EVFSCMPLT | |
| UINT64_C(268436119), // EVFSCTSF | |
| UINT64_C(268436117), // EVFSCTSI | |
| UINT64_C(268436122), // EVFSCTSIZ | |
| UINT64_C(268436118), // EVFSCTUF | |
| UINT64_C(268436116), // EVFSCTUI | |
| UINT64_C(268436120), // EVFSCTUIZ | |
| UINT64_C(268436105), // EVFSDIV | |
| UINT64_C(268436104), // EVFSMUL | |
| UINT64_C(268436101), // EVFSNABS | |
| UINT64_C(268436102), // EVFSNEG | |
| UINT64_C(268436097), // EVFSSUB | |
| UINT64_C(268436126), // EVFSTSTEQ | |
| UINT64_C(268436124), // EVFSTSTGT | |
| UINT64_C(268436125), // EVFSTSTLT | |
| UINT64_C(268436225), // EVLDD | |
| UINT64_C(268436224), // EVLDDX | |
| UINT64_C(268436229), // EVLDH | |
| UINT64_C(268436228), // EVLDHX | |
| UINT64_C(268436227), // EVLDW | |
| UINT64_C(268436226), // EVLDWX | |
| UINT64_C(268436233), // EVLHHESPLAT | |
| UINT64_C(268436232), // EVLHHESPLATX | |
| UINT64_C(268436239), // EVLHHOSSPLAT | |
| UINT64_C(268436238), // EVLHHOSSPLATX | |
| UINT64_C(268436237), // EVLHHOUSPLAT | |
| UINT64_C(268436236), // EVLHHOUSPLATX | |
| UINT64_C(268436241), // EVLWHE | |
| UINT64_C(268436240), // EVLWHEX | |
| UINT64_C(268436247), // EVLWHOS | |
| UINT64_C(268436246), // EVLWHOSX | |
| UINT64_C(268436245), // EVLWHOU | |
| UINT64_C(268436244), // EVLWHOUX | |
| UINT64_C(268436253), // EVLWHSPLAT | |
| UINT64_C(268436252), // EVLWHSPLATX | |
| UINT64_C(268436249), // EVLWWSPLAT | |
| UINT64_C(268436248), // EVLWWSPLATX | |
| UINT64_C(268436012), // EVMERGEHI | |
| UINT64_C(268436014), // EVMERGEHILO | |
| UINT64_C(268436013), // EVMERGELO | |
| UINT64_C(268436015), // EVMERGELOHI | |
| UINT64_C(268436779), // EVMHEGSMFAA | |
| UINT64_C(268436907), // EVMHEGSMFAN | |
| UINT64_C(268436777), // EVMHEGSMIAA | |
| UINT64_C(268436905), // EVMHEGSMIAN | |
| UINT64_C(268436776), // EVMHEGUMIAA | |
| UINT64_C(268436904), // EVMHEGUMIAN | |
| UINT64_C(268436491), // EVMHESMF | |
| UINT64_C(268436523), // EVMHESMFA | |
| UINT64_C(268436747), // EVMHESMFAAW | |
| UINT64_C(268436875), // EVMHESMFANW | |
| UINT64_C(268436489), // EVMHESMI | |
| UINT64_C(268436521), // EVMHESMIA | |
| UINT64_C(268436745), // EVMHESMIAAW | |
| UINT64_C(268436873), // EVMHESMIANW | |
| UINT64_C(268436483), // EVMHESSF | |
| UINT64_C(268436515), // EVMHESSFA | |
| UINT64_C(268436739), // EVMHESSFAAW | |
| UINT64_C(268436867), // EVMHESSFANW | |
| UINT64_C(268436737), // EVMHESSIAAW | |
| UINT64_C(268436865), // EVMHESSIANW | |
| UINT64_C(268436488), // EVMHEUMI | |
| UINT64_C(268436520), // EVMHEUMIA | |
| UINT64_C(268436744), // EVMHEUMIAAW | |
| UINT64_C(268436872), // EVMHEUMIANW | |
| UINT64_C(268436736), // EVMHEUSIAAW | |
| UINT64_C(268436864), // EVMHEUSIANW | |
| UINT64_C(268436783), // EVMHOGSMFAA | |
| UINT64_C(268436911), // EVMHOGSMFAN | |
| UINT64_C(268436781), // EVMHOGSMIAA | |
| UINT64_C(268436909), // EVMHOGSMIAN | |
| UINT64_C(268436780), // EVMHOGUMIAA | |
| UINT64_C(268436908), // EVMHOGUMIAN | |
| UINT64_C(268436495), // EVMHOSMF | |
| UINT64_C(268436527), // EVMHOSMFA | |
| UINT64_C(268436751), // EVMHOSMFAAW | |
| UINT64_C(268436879), // EVMHOSMFANW | |
| UINT64_C(268436493), // EVMHOSMI | |
| UINT64_C(268436525), // EVMHOSMIA | |
| UINT64_C(268436749), // EVMHOSMIAAW | |
| UINT64_C(268436877), // EVMHOSMIANW | |
| UINT64_C(268436487), // EVMHOSSF | |
| UINT64_C(268436519), // EVMHOSSFA | |
| UINT64_C(268436743), // EVMHOSSFAAW | |
| UINT64_C(268436871), // EVMHOSSFANW | |
| UINT64_C(268436741), // EVMHOSSIAAW | |
| UINT64_C(268436869), // EVMHOSSIANW | |
| UINT64_C(268436492), // EVMHOUMI | |
| UINT64_C(268436524), // EVMHOUMIA | |
| UINT64_C(268436748), // EVMHOUMIAAW | |
| UINT64_C(268436876), // EVMHOUMIANW | |
| UINT64_C(268436740), // EVMHOUSIAAW | |
| UINT64_C(268436868), // EVMHOUSIANW | |
| UINT64_C(268436676), // EVMRA | |
| UINT64_C(268436559), // EVMWHSMF | |
| UINT64_C(268436591), // EVMWHSMFA | |
| UINT64_C(268436557), // EVMWHSMI | |
| UINT64_C(268436589), // EVMWHSMIA | |
| UINT64_C(268436551), // EVMWHSSF | |
| UINT64_C(268436583), // EVMWHSSFA | |
| UINT64_C(268436556), // EVMWHUMI | |
| UINT64_C(268436588), // EVMWHUMIA | |
| UINT64_C(268436809), // EVMWLSMIAAW | |
| UINT64_C(268436937), // EVMWLSMIANW | |
| UINT64_C(268436801), // EVMWLSSIAAW | |
| UINT64_C(268436929), // EVMWLSSIANW | |
| UINT64_C(268436552), // EVMWLUMI | |
| UINT64_C(268436584), // EVMWLUMIA | |
| UINT64_C(268436808), // EVMWLUMIAAW | |
| UINT64_C(268436936), // EVMWLUMIANW | |
| UINT64_C(268436800), // EVMWLUSIAAW | |
| UINT64_C(268436928), // EVMWLUSIANW | |
| UINT64_C(268436571), // EVMWSMF | |
| UINT64_C(268436603), // EVMWSMFA | |
| UINT64_C(268436827), // EVMWSMFAA | |
| UINT64_C(268436955), // EVMWSMFAN | |
| UINT64_C(268436569), // EVMWSMI | |
| UINT64_C(268436601), // EVMWSMIA | |
| UINT64_C(268436825), // EVMWSMIAA | |
| UINT64_C(268436953), // EVMWSMIAN | |
| UINT64_C(268436563), // EVMWSSF | |
| UINT64_C(268436595), // EVMWSSFA | |
| UINT64_C(268436819), // EVMWSSFAA | |
| UINT64_C(268436947), // EVMWSSFAN | |
| UINT64_C(268436568), // EVMWUMI | |
| UINT64_C(268436600), // EVMWUMIA | |
| UINT64_C(268436824), // EVMWUMIAA | |
| UINT64_C(268436952), // EVMWUMIAN | |
| UINT64_C(268435998), // EVNAND | |
| UINT64_C(268435977), // EVNEG | |
| UINT64_C(268435992), // EVNOR | |
| UINT64_C(268435991), // EVOR | |
| UINT64_C(268435995), // EVORC | |
| UINT64_C(268436008), // EVRLW | |
| UINT64_C(268436010), // EVRLWI | |
| UINT64_C(268435980), // EVRNDW | |
| UINT64_C(268436088), // EVSEL | |
| UINT64_C(268436004), // EVSLW | |
| UINT64_C(268436006), // EVSLWI | |
| UINT64_C(268436011), // EVSPLATFI | |
| UINT64_C(268436009), // EVSPLATI | |
| UINT64_C(268436003), // EVSRWIS | |
| UINT64_C(268436002), // EVSRWIU | |
| UINT64_C(268436001), // EVSRWS | |
| UINT64_C(268436000), // EVSRWU | |
| UINT64_C(268436257), // EVSTDD | |
| UINT64_C(268436256), // EVSTDDX | |
| UINT64_C(268436261), // EVSTDH | |
| UINT64_C(268436260), // EVSTDHX | |
| UINT64_C(268436259), // EVSTDW | |
| UINT64_C(268436258), // EVSTDWX | |
| UINT64_C(268436273), // EVSTWHE | |
| UINT64_C(268436272), // EVSTWHEX | |
| UINT64_C(268436277), // EVSTWHO | |
| UINT64_C(268436276), // EVSTWHOX | |
| UINT64_C(268436281), // EVSTWWE | |
| UINT64_C(268436280), // EVSTWWEX | |
| UINT64_C(268436285), // EVSTWWO | |
| UINT64_C(268436284), // EVSTWWOX | |
| UINT64_C(268436683), // EVSUBFSMIAAW | |
| UINT64_C(268436675), // EVSUBFSSIAAW | |
| UINT64_C(268436682), // EVSUBFUMIAAW | |
| UINT64_C(268436674), // EVSUBFUSIAAW | |
| UINT64_C(268435972), // EVSUBFW | |
| UINT64_C(268435974), // EVSUBIFW | |
| UINT64_C(268435990), // EVXOR | |
| UINT64_C(2080376692), // EXTSB | |
| UINT64_C(2080376692), // EXTSB8 | |
| UINT64_C(2080376692), // EXTSB8_32_64 | |
| UINT64_C(2080376693), // EXTSB8_rec | |
| UINT64_C(2080376693), // EXTSB_rec | |
| UINT64_C(2080376628), // EXTSH | |
| UINT64_C(2080376628), // EXTSH8 | |
| UINT64_C(2080376628), // EXTSH8_32_64 | |
| UINT64_C(2080376629), // EXTSH8_rec | |
| UINT64_C(2080376629), // EXTSH_rec | |
| UINT64_C(2080376756), // EXTSW | |
| UINT64_C(2080376564), // EXTSWSLI | |
| UINT64_C(2080376564), // EXTSWSLI_32_64 | |
| UINT64_C(2080376565), // EXTSWSLI_32_64_rec | |
| UINT64_C(2080376565), // EXTSWSLI_rec | |
| UINT64_C(2080376756), // EXTSW_32 | |
| UINT64_C(2080376756), // EXTSW_32_64 | |
| UINT64_C(2080376757), // EXTSW_32_64_rec | |
| UINT64_C(2080376757), // EXTSW_rec | |
| UINT64_C(2080376492), // EnforceIEIO | |
| UINT64_C(4227858960), // FABSD | |
| UINT64_C(4227858961), // FABSD_rec | |
| UINT64_C(4227858960), // FABSS | |
| UINT64_C(4227858961), // FABSS_rec | |
| UINT64_C(4227858474), // FADD | |
| UINT64_C(3959423018), // FADDS | |
| UINT64_C(3959423019), // FADDS_rec | |
| UINT64_C(4227858475), // FADD_rec | |
| UINT64_C(0), // FADDrtz | |
| UINT64_C(4227860124), // FCFID | |
| UINT64_C(3959424668), // FCFIDS | |
| UINT64_C(3959424669), // FCFIDS_rec | |
| UINT64_C(4227860380), // FCFIDU | |
| UINT64_C(3959424924), // FCFIDUS | |
| UINT64_C(3959424925), // FCFIDUS_rec | |
| UINT64_C(4227860381), // FCFIDU_rec | |
| UINT64_C(4227860125), // FCFID_rec | |
| UINT64_C(4227858432), // FCMPUD | |
| UINT64_C(4227858432), // FCMPUS | |
| UINT64_C(4227858448), // FCPSGND | |
| UINT64_C(4227858449), // FCPSGND_rec | |
| UINT64_C(4227858448), // FCPSGNS | |
| UINT64_C(4227858449), // FCPSGNS_rec | |
| UINT64_C(4227860060), // FCTID | |
| UINT64_C(4227860316), // FCTIDU | |
| UINT64_C(4227860318), // FCTIDUZ | |
| UINT64_C(4227860319), // FCTIDUZ_rec | |
| UINT64_C(4227860317), // FCTIDU_rec | |
| UINT64_C(4227860062), // FCTIDZ | |
| UINT64_C(4227860063), // FCTIDZ_rec | |
| UINT64_C(4227860061), // FCTID_rec | |
| UINT64_C(4227858460), // FCTIW | |
| UINT64_C(4227858716), // FCTIWU | |
| UINT64_C(4227858718), // FCTIWUZ | |
| UINT64_C(4227858719), // FCTIWUZ_rec | |
| UINT64_C(4227858717), // FCTIWU_rec | |
| UINT64_C(4227858462), // FCTIWZ | |
| UINT64_C(4227858463), // FCTIWZ_rec | |
| UINT64_C(4227858461), // FCTIW_rec | |
| UINT64_C(4227858468), // FDIV | |
| UINT64_C(3959423012), // FDIVS | |
| UINT64_C(3959423013), // FDIVS_rec | |
| UINT64_C(4227858469), // FDIV_rec | |
| UINT64_C(4227858490), // FMADD | |
| UINT64_C(3959423034), // FMADDS | |
| UINT64_C(3959423035), // FMADDS_rec | |
| UINT64_C(4227858491), // FMADD_rec | |
| UINT64_C(4227858576), // FMR | |
| UINT64_C(4227858577), // FMR_rec | |
| UINT64_C(4227858488), // FMSUB | |
| UINT64_C(3959423032), // FMSUBS | |
| UINT64_C(3959423033), // FMSUBS_rec | |
| UINT64_C(4227858489), // FMSUB_rec | |
| UINT64_C(4227858482), // FMUL | |
| UINT64_C(3959423026), // FMULS | |
| UINT64_C(3959423027), // FMULS_rec | |
| UINT64_C(4227858483), // FMUL_rec | |
| UINT64_C(4227858704), // FNABSD | |
| UINT64_C(4227858705), // FNABSD_rec | |
| UINT64_C(4227858704), // FNABSS | |
| UINT64_C(4227858705), // FNABSS_rec | |
| UINT64_C(4227858512), // FNEGD | |
| UINT64_C(4227858513), // FNEGD_rec | |
| UINT64_C(4227858512), // FNEGS | |
| UINT64_C(4227858513), // FNEGS_rec | |
| UINT64_C(4227858494), // FNMADD | |
| UINT64_C(3959423038), // FNMADDS | |
| UINT64_C(3959423039), // FNMADDS_rec | |
| UINT64_C(4227858495), // FNMADD_rec | |
| UINT64_C(4227858492), // FNMSUB | |
| UINT64_C(3959423036), // FNMSUBS | |
| UINT64_C(3959423037), // FNMSUBS_rec | |
| UINT64_C(4227858493), // FNMSUB_rec | |
| UINT64_C(4227858480), // FRE | |
| UINT64_C(3959423024), // FRES | |
| UINT64_C(3959423025), // FRES_rec | |
| UINT64_C(4227858481), // FRE_rec | |
| UINT64_C(4227859408), // FRIMD | |
| UINT64_C(4227859409), // FRIMD_rec | |
| UINT64_C(4227859408), // FRIMS | |
| UINT64_C(4227859409), // FRIMS_rec | |
| UINT64_C(4227859216), // FRIND | |
| UINT64_C(4227859217), // FRIND_rec | |
| UINT64_C(4227859216), // FRINS | |
| UINT64_C(4227859217), // FRINS_rec | |
| UINT64_C(4227859344), // FRIPD | |
| UINT64_C(4227859345), // FRIPD_rec | |
| UINT64_C(4227859344), // FRIPS | |
| UINT64_C(4227859345), // FRIPS_rec | |
| UINT64_C(4227859280), // FRIZD | |
| UINT64_C(4227859281), // FRIZD_rec | |
| UINT64_C(4227859280), // FRIZS | |
| UINT64_C(4227859281), // FRIZS_rec | |
| UINT64_C(4227858456), // FRSP | |
| UINT64_C(4227858457), // FRSP_rec | |
| UINT64_C(4227858484), // FRSQRTE | |
| UINT64_C(3959423028), // FRSQRTES | |
| UINT64_C(3959423029), // FRSQRTES_rec | |
| UINT64_C(4227858485), // FRSQRTE_rec | |
| UINT64_C(4227858478), // FSELD | |
| UINT64_C(4227858479), // FSELD_rec | |
| UINT64_C(4227858478), // FSELS | |
| UINT64_C(4227858479), // FSELS_rec | |
| UINT64_C(4227858476), // FSQRT | |
| UINT64_C(3959423020), // FSQRTS | |
| UINT64_C(3959423021), // FSQRTS_rec | |
| UINT64_C(4227858477), // FSQRT_rec | |
| UINT64_C(4227858472), // FSUB | |
| UINT64_C(3959423016), // FSUBS | |
| UINT64_C(3959423017), // FSUBS_rec | |
| UINT64_C(4227858473), // FSUB_rec | |
| UINT64_C(4227858688), // FTDIV | |
| UINT64_C(4227858752), // FTSQRT | |
| UINT64_C(0), // GETtlsADDR | |
| UINT64_C(0), // GETtlsADDR32 | |
| UINT64_C(0), // GETtlsldADDR | |
| UINT64_C(0), // GETtlsldADDR32 | |
| UINT64_C(1275068964), // HRFID | |
| UINT64_C(2080376748), // ICBI | |
| UINT64_C(2080376766), // ICBIEP | |
| UINT64_C(2080375244), // ICBLC | |
| UINT64_C(2080375180), // ICBLQ | |
| UINT64_C(2080374828), // ICBT | |
| UINT64_C(2080375756), // ICBTLS | |
| UINT64_C(2080376716), // ICCCI | |
| UINT64_C(2080374814), // ISEL | |
| UINT64_C(2080374814), // ISEL8 | |
| UINT64_C(1275068716), // ISYNC | |
| UINT64_C(939524096), // LA | |
| UINT64_C(2080374888), // LBARX | |
| UINT64_C(2080374889), // LBARXL | |
| UINT64_C(2080374974), // LBEPX | |
| UINT64_C(2281701376), // LBZ | |
| UINT64_C(2281701376), // LBZ8 | |
| UINT64_C(2080376490), // LBZCIX | |
| UINT64_C(2348810240), // LBZU | |
| UINT64_C(2348810240), // LBZU8 | |
| UINT64_C(2080375022), // LBZUX | |
| UINT64_C(2080375022), // LBZUX8 | |
| UINT64_C(2080374958), // LBZX | |
| UINT64_C(2080374958), // LBZX8 | |
| UINT64_C(2080374958), // LBZXTLS | |
| UINT64_C(2080374958), // LBZXTLS_ | |
| UINT64_C(2080374958), // LBZXTLS_32 | |
| UINT64_C(3892314112), // LD | |
| UINT64_C(2080374952), // LDARX | |
| UINT64_C(2080374953), // LDARXL | |
| UINT64_C(2080376012), // LDAT | |
| UINT64_C(2080375848), // LDBRX | |
| UINT64_C(2080376554), // LDCIX | |
| UINT64_C(2080375402), // LDMX | |
| UINT64_C(3892314113), // LDU | |
| UINT64_C(2080374890), // LDUX | |
| UINT64_C(2080374826), // LDX | |
| UINT64_C(2080374826), // LDXTLS | |
| UINT64_C(2080374826), // LDXTLS_ | |
| UINT64_C(0), // LDgotTprelL | |
| UINT64_C(0), // LDgotTprelL32 | |
| UINT64_C(0), // LDtoc | |
| UINT64_C(0), // LDtocBA | |
| UINT64_C(0), // LDtocCPT | |
| UINT64_C(0), // LDtocJTI | |
| UINT64_C(0), // LDtocL | |
| UINT64_C(3355443200), // LFD | |
| UINT64_C(2080375998), // LFDEPX | |
| UINT64_C(3422552064), // LFDU | |
| UINT64_C(2080376046), // LFDUX | |
| UINT64_C(2080375982), // LFDX | |
| UINT64_C(2080376494), // LFIWAX | |
| UINT64_C(2080376558), // LFIWZX | |
| UINT64_C(3221225472), // LFS | |
| UINT64_C(3288334336), // LFSU | |
| UINT64_C(2080375918), // LFSUX | |
| UINT64_C(2080375854), // LFSX | |
| UINT64_C(2818572288), // LHA | |
| UINT64_C(2818572288), // LHA8 | |
| UINT64_C(2080375016), // LHARX | |
| UINT64_C(2080375017), // LHARXL | |
| UINT64_C(2885681152), // LHAU | |
| UINT64_C(2885681152), // LHAU8 | |
| UINT64_C(2080375534), // LHAUX | |
| UINT64_C(2080375534), // LHAUX8 | |
| UINT64_C(2080375470), // LHAX | |
| UINT64_C(2080375470), // LHAX8 | |
| UINT64_C(2080376364), // LHBRX | |
| UINT64_C(2080376364), // LHBRX8 | |
| UINT64_C(2080375358), // LHEPX | |
| UINT64_C(2684354560), // LHZ | |
| UINT64_C(2684354560), // LHZ8 | |
| UINT64_C(2080376426), // LHZCIX | |
| UINT64_C(2751463424), // LHZU | |
| UINT64_C(2751463424), // LHZU8 | |
| UINT64_C(2080375406), // LHZUX | |
| UINT64_C(2080375406), // LHZUX8 | |
| UINT64_C(2080375342), // LHZX | |
| UINT64_C(2080375342), // LHZX8 | |
| UINT64_C(2080375342), // LHZXTLS | |
| UINT64_C(2080375342), // LHZXTLS_ | |
| UINT64_C(2080375342), // LHZXTLS_32 | |
| UINT64_C(939524096), // LI | |
| UINT64_C(939524096), // LI8 | |
| UINT64_C(1006632960), // LIS | |
| UINT64_C(1006632960), // LIS8 | |
| UINT64_C(3087007744), // LMW | |
| UINT64_C(2080375978), // LSWI | |
| UINT64_C(2080374798), // LVEBX | |
| UINT64_C(2080374862), // LVEHX | |
| UINT64_C(2080374926), // LVEWX | |
| UINT64_C(2080374796), // LVSL | |
| UINT64_C(2080374860), // LVSR | |
| UINT64_C(2080374990), // LVX | |
| UINT64_C(2080375502), // LVXL | |
| UINT64_C(3892314114), // LWA | |
| UINT64_C(2080374824), // LWARX | |
| UINT64_C(2080374825), // LWARXL | |
| UINT64_C(2080375948), // LWAT | |
| UINT64_C(2080375530), // LWAUX | |
| UINT64_C(2080375466), // LWAX | |
| UINT64_C(2080375466), // LWAX_32 | |
| UINT64_C(3892314114), // LWA_32 | |
| UINT64_C(2080375852), // LWBRX | |
| UINT64_C(2080375852), // LWBRX8 | |
| UINT64_C(2080374846), // LWEPX | |
| UINT64_C(2147483648), // LWZ | |
| UINT64_C(2147483648), // LWZ8 | |
| UINT64_C(2080376362), // LWZCIX | |
| UINT64_C(2214592512), // LWZU | |
| UINT64_C(2214592512), // LWZU8 | |
| UINT64_C(2080374894), // LWZUX | |
| UINT64_C(2080374894), // LWZUX8 | |
| UINT64_C(2080374830), // LWZX | |
| UINT64_C(2080374830), // LWZX8 | |
| UINT64_C(2080374830), // LWZXTLS | |
| UINT64_C(2080374830), // LWZXTLS_ | |
| UINT64_C(2080374830), // LWZXTLS_32 | |
| UINT64_C(0), // LWZtoc | |
| UINT64_C(0), // LWZtocL | |
| UINT64_C(3825205250), // LXSD | |
| UINT64_C(2080375960), // LXSDX | |
| UINT64_C(2080376346), // LXSIBZX | |
| UINT64_C(2080376410), // LXSIHZX | |
| UINT64_C(2080374936), // LXSIWAX | |
| UINT64_C(2080374808), // LXSIWZX | |
| UINT64_C(3825205251), // LXSSP | |
| UINT64_C(2080375832), // LXSSPX | |
| UINT64_C(4093640705), // LXV | |
| UINT64_C(2080376536), // LXVB16X | |
| UINT64_C(2080376472), // LXVD2X | |
| UINT64_C(2080375448), // LXVDSX | |
| UINT64_C(2080376408), // LXVH8X | |
| UINT64_C(2080375322), // LXVL | |
| UINT64_C(2080375386), // LXVLL | |
| UINT64_C(2080376344), // LXVW4X | |
| UINT64_C(2080375512), // LXVWSX | |
| UINT64_C(2080375320), // LXVX | |
| UINT64_C(268435504), // MADDHD | |
| UINT64_C(268435505), // MADDHDU | |
| UINT64_C(268435507), // MADDLD | |
| UINT64_C(268435507), // MADDLD8 | |
| UINT64_C(2080376492), // MBAR | |
| UINT64_C(1275068416), // MCRF | |
| UINT64_C(4227858560), // MCRFS | |
| UINT64_C(2080375936), // MCRXRX | |
| UINT64_C(2080375388), // MFBHRBE | |
| UINT64_C(2080374822), // MFCR | |
| UINT64_C(2080374822), // MFCR8 | |
| UINT64_C(2080965286), // MFCTR | |
| UINT64_C(2080965286), // MFCTR8 | |
| UINT64_C(2080375430), // MFDCR | |
| UINT64_C(4227859598), // MFFS | |
| UINT64_C(4229170318), // MFFSCDRN | |
| UINT64_C(4229235854), // MFFSCDRNI | |
| UINT64_C(4227925134), // MFFSCE | |
| UINT64_C(4229301390), // MFFSCRN | |
| UINT64_C(4229366926), // MFFSCRNI | |
| UINT64_C(4229432462), // MFFSL | |
| UINT64_C(4227859599), // MFFS_rec | |
| UINT64_C(2080899750), // MFLR | |
| UINT64_C(2080899750), // MFLR8 | |
| UINT64_C(2080374950), // MFMSR | |
| UINT64_C(2081423398), // MFOCRF | |
| UINT64_C(2081423398), // MFOCRF8 | |
| UINT64_C(2080375452), // MFPMR | |
| UINT64_C(2080375462), // MFSPR | |
| UINT64_C(2080375462), // MFSPR8 | |
| UINT64_C(2080375974), // MFSR | |
| UINT64_C(2080376102), // MFSRIN | |
| UINT64_C(2080375526), // MFTB | |
| UINT64_C(2081178278), // MFTB8 | |
| UINT64_C(2080374886), // MFVRD | |
| UINT64_C(2080391846), // MFVRSAVE | |
| UINT64_C(2080391846), // MFVRSAVEv | |
| UINT64_C(2080375014), // MFVRWZ | |
| UINT64_C(268436996), // MFVSCR | |
| UINT64_C(2080374886), // MFVSRD | |
| UINT64_C(2080375398), // MFVSRLD | |
| UINT64_C(2080375014), // MFVSRWZ | |
| UINT64_C(2080376338), // MODSD | |
| UINT64_C(2080376342), // MODSW | |
| UINT64_C(2080375314), // MODUD | |
| UINT64_C(2080375318), // MODUW | |
| UINT64_C(2080376556), // MSGSYNC | |
| UINT64_C(2080375980), // MSYNC | |
| UINT64_C(2080375072), // MTCRF | |
| UINT64_C(2080375072), // MTCRF8 | |
| UINT64_C(2080965542), // MTCTR | |
| UINT64_C(2080965542), // MTCTR8 | |
| UINT64_C(2080965542), // MTCTR8loop | |
| UINT64_C(2080965542), // MTCTRloop | |
| UINT64_C(2080375686), // MTDCR | |
| UINT64_C(4227858572), // MTFSB0 | |
| UINT64_C(4227858508), // MTFSB1 | |
| UINT64_C(4227859854), // MTFSF | |
| UINT64_C(4227858700), // MTFSFI | |
| UINT64_C(4227858701), // MTFSFI_rec | |
| UINT64_C(4227859855), // MTFSF_rec | |
| UINT64_C(4227859854), // MTFSFb | |
| UINT64_C(2080900006), // MTLR | |
| UINT64_C(2080900006), // MTLR8 | |
| UINT64_C(2080375076), // MTMSR | |
| UINT64_C(2080375140), // MTMSRD | |
| UINT64_C(2081423648), // MTOCRF | |
| UINT64_C(2081423648), // MTOCRF8 | |
| UINT64_C(2080375708), // MTPMR | |
| UINT64_C(2080375718), // MTSPR | |
| UINT64_C(2080375718), // MTSPR8 | |
| UINT64_C(2080375204), // MTSR | |
| UINT64_C(2080375268), // MTSRIN | |
| UINT64_C(2080375142), // MTVRD | |
| UINT64_C(2080392102), // MTVRSAVE | |
| UINT64_C(2080392102), // MTVRSAVEv | |
| UINT64_C(2080375206), // MTVRWA | |
| UINT64_C(2080375270), // MTVRWZ | |
| UINT64_C(268437060), // MTVSCR | |
| UINT64_C(2080375142), // MTVSRD | |
| UINT64_C(2080375654), // MTVSRDD | |
| UINT64_C(2080375206), // MTVSRWA | |
| UINT64_C(2080375590), // MTVSRWS | |
| UINT64_C(2080375270), // MTVSRWZ | |
| UINT64_C(2080374930), // MULHD | |
| UINT64_C(2080374802), // MULHDU | |
| UINT64_C(2080374803), // MULHDU_rec | |
| UINT64_C(2080374931), // MULHD_rec | |
| UINT64_C(2080374934), // MULHW | |
| UINT64_C(2080374806), // MULHWU | |
| UINT64_C(2080374807), // MULHWU_rec | |
| UINT64_C(2080374935), // MULHW_rec | |
| UINT64_C(2080375250), // MULLD | |
| UINT64_C(2080376274), // MULLDO | |
| UINT64_C(2080376275), // MULLDO_rec | |
| UINT64_C(2080375251), // MULLD_rec | |
| UINT64_C(469762048), // MULLI | |
| UINT64_C(469762048), // MULLI8 | |
| UINT64_C(2080375254), // MULLW | |
| UINT64_C(2080376278), // MULLWO | |
| UINT64_C(2080376279), // MULLWO_rec | |
| UINT64_C(2080375255), // MULLW_rec | |
| UINT64_C(0), // MoveGOTtoLR | |
| UINT64_C(0), // MovePCtoLR | |
| UINT64_C(0), // MovePCtoLR8 | |
| UINT64_C(2080375736), // NAND | |
| UINT64_C(2080375736), // NAND8 | |
| UINT64_C(2080375737), // NAND8_rec | |
| UINT64_C(2080375737), // NAND_rec | |
| UINT64_C(1275069284), // NAP | |
| UINT64_C(2080374992), // NEG | |
| UINT64_C(2080374992), // NEG8 | |
| UINT64_C(2080376016), // NEG8O | |
| UINT64_C(2080376017), // NEG8O_rec | |
| UINT64_C(2080374993), // NEG8_rec | |
| UINT64_C(2080376016), // NEGO | |
| UINT64_C(2080376017), // NEGO_rec | |
| UINT64_C(2080374993), // NEG_rec | |
| UINT64_C(1610612736), // NOP | |
| UINT64_C(1612775424), // NOP_GT_PWR6 | |
| UINT64_C(1614938112), // NOP_GT_PWR7 | |
| UINT64_C(2080375032), // NOR | |
| UINT64_C(2080375032), // NOR8 | |
| UINT64_C(2080375033), // NOR8_rec | |
| UINT64_C(2080375033), // NOR_rec | |
| UINT64_C(2080375672), // OR | |
| UINT64_C(2080375672), // OR8 | |
| UINT64_C(2080375673), // OR8_rec | |
| UINT64_C(2080375608), // ORC | |
| UINT64_C(2080375608), // ORC8 | |
| UINT64_C(2080375609), // ORC8_rec | |
| UINT64_C(2080375609), // ORC_rec | |
| UINT64_C(1610612736), // ORI | |
| UINT64_C(1610612736), // ORI8 | |
| UINT64_C(1677721600), // ORIS | |
| UINT64_C(1677721600), // ORIS8 | |
| UINT64_C(2080375673), // OR_rec | |
| UINT64_C(2080375028), // POPCNTB | |
| UINT64_C(2080375796), // POPCNTD | |
| UINT64_C(2080375540), // POPCNTW | |
| UINT64_C(0), // PPC32GOT | |
| UINT64_C(0), // PPC32PICGOT | |
| UINT64_C(268435466), // QVALIGNI | |
| UINT64_C(268435466), // QVALIGNIb | |
| UINT64_C(268435466), // QVALIGNIs | |
| UINT64_C(268435530), // QVESPLATI | |
| UINT64_C(268435530), // QVESPLATIb | |
| UINT64_C(268435530), // QVESPLATIs | |
| UINT64_C(268435984), // QVFABS | |
| UINT64_C(268435984), // QVFABSs | |
| UINT64_C(268435498), // QVFADD | |
| UINT64_C(42), // QVFADDS | |
| UINT64_C(42), // QVFADDSs | |
| UINT64_C(268437148), // QVFCFID | |
| UINT64_C(1692), // QVFCFIDS | |
| UINT64_C(268437404), // QVFCFIDU | |
| UINT64_C(1948), // QVFCFIDUS | |
| UINT64_C(268437148), // QVFCFIDb | |
| UINT64_C(268435456), // QVFCMPEQ | |
| UINT64_C(268435456), // QVFCMPEQb | |
| UINT64_C(268435456), // QVFCMPEQbs | |
| UINT64_C(268435520), // QVFCMPGT | |
| UINT64_C(268435520), // QVFCMPGTb | |
| UINT64_C(268435520), // QVFCMPGTbs | |
| UINT64_C(268435648), // QVFCMPLT | |
| UINT64_C(268435648), // QVFCMPLTb | |
| UINT64_C(268435648), // QVFCMPLTbs | |
| UINT64_C(268435472), // QVFCPSGN | |
| UINT64_C(268435472), // QVFCPSGNs | |
| UINT64_C(268437084), // QVFCTID | |
| UINT64_C(268437340), // QVFCTIDU | |
| UINT64_C(268437342), // QVFCTIDUZ | |
| UINT64_C(268437086), // QVFCTIDZ | |
| UINT64_C(268437084), // QVFCTIDb | |
| UINT64_C(268435484), // QVFCTIW | |
| UINT64_C(268435740), // QVFCTIWU | |
| UINT64_C(268435742), // QVFCTIWUZ | |
| UINT64_C(268435486), // QVFCTIWZ | |
| UINT64_C(268435464), // QVFLOGICAL | |
| UINT64_C(268435464), // QVFLOGICALb | |
| UINT64_C(268435464), // QVFLOGICALs | |
| UINT64_C(268435514), // QVFMADD | |
| UINT64_C(58), // QVFMADDS | |
| UINT64_C(58), // QVFMADDSs | |
| UINT64_C(268435600), // QVFMR | |
| UINT64_C(268435600), // QVFMRb | |
| UINT64_C(268435600), // QVFMRs | |
| UINT64_C(268435512), // QVFMSUB | |
| UINT64_C(56), // QVFMSUBS | |
| UINT64_C(56), // QVFMSUBSs | |
| UINT64_C(268435506), // QVFMUL | |
| UINT64_C(50), // QVFMULS | |
| UINT64_C(50), // QVFMULSs | |
| UINT64_C(268435728), // QVFNABS | |
| UINT64_C(268435728), // QVFNABSs | |
| UINT64_C(268435536), // QVFNEG | |
| UINT64_C(268435536), // QVFNEGs | |
| UINT64_C(268435518), // QVFNMADD | |
| UINT64_C(62), // QVFNMADDS | |
| UINT64_C(62), // QVFNMADDSs | |
| UINT64_C(268435516), // QVFNMSUB | |
| UINT64_C(60), // QVFNMSUBS | |
| UINT64_C(60), // QVFNMSUBSs | |
| UINT64_C(268435468), // QVFPERM | |
| UINT64_C(268435468), // QVFPERMs | |
| UINT64_C(268435504), // QVFRE | |
| UINT64_C(48), // QVFRES | |
| UINT64_C(48), // QVFRESs | |
| UINT64_C(268436432), // QVFRIM | |
| UINT64_C(268436432), // QVFRIMs | |
| UINT64_C(268436240), // QVFRIN | |
| UINT64_C(268436240), // QVFRINs | |
| UINT64_C(268436368), // QVFRIP | |
| UINT64_C(268436368), // QVFRIPs | |
| UINT64_C(268436304), // QVFRIZ | |
| UINT64_C(268436304), // QVFRIZs | |
| UINT64_C(268435480), // QVFRSP | |
| UINT64_C(268435480), // QVFRSPs | |
| UINT64_C(268435508), // QVFRSQRTE | |
| UINT64_C(52), // QVFRSQRTES | |
| UINT64_C(52), // QVFRSQRTESs | |
| UINT64_C(268435502), // QVFSEL | |
| UINT64_C(268435502), // QVFSELb | |
| UINT64_C(268435502), // QVFSELbb | |
| UINT64_C(268435502), // QVFSELbs | |
| UINT64_C(268435496), // QVFSUB | |
| UINT64_C(40), // QVFSUBS | |
| UINT64_C(40), // QVFSUBSs | |
| UINT64_C(268435584), // QVFTSTNAN | |
| UINT64_C(268435584), // QVFTSTNANb | |
| UINT64_C(268435584), // QVFTSTNANbs | |
| UINT64_C(268435474), // QVFXMADD | |
| UINT64_C(18), // QVFXMADDS | |
| UINT64_C(268435490), // QVFXMUL | |
| UINT64_C(34), // QVFXMULS | |
| UINT64_C(268435462), // QVFXXCPNMADD | |
| UINT64_C(6), // QVFXXCPNMADDS | |
| UINT64_C(268435458), // QVFXXMADD | |
| UINT64_C(2), // QVFXXMADDS | |
| UINT64_C(268435478), // QVFXXNPMADD | |
| UINT64_C(22), // QVFXXNPMADDS | |
| UINT64_C(268435722), // QVGPCI | |
| UINT64_C(2080374990), // QVLFCDUX | |
| UINT64_C(2080374991), // QVLFCDUXA | |
| UINT64_C(2080374926), // QVLFCDX | |
| UINT64_C(2080374927), // QVLFCDXA | |
| UINT64_C(2080374862), // QVLFCSUX | |
| UINT64_C(2080374863), // QVLFCSUXA | |
| UINT64_C(2080374798), // QVLFCSX | |
| UINT64_C(2080374799), // QVLFCSXA | |
| UINT64_C(2080374798), // QVLFCSXs | |
| UINT64_C(2080376014), // QVLFDUX | |
| UINT64_C(2080376015), // QVLFDUXA | |
| UINT64_C(2080375950), // QVLFDX | |
| UINT64_C(2080375951), // QVLFDXA | |
| UINT64_C(2080375950), // QVLFDXb | |
| UINT64_C(2080376526), // QVLFIWAX | |
| UINT64_C(2080376527), // QVLFIWAXA | |
| UINT64_C(2080376462), // QVLFIWZX | |
| UINT64_C(2080376463), // QVLFIWZXA | |
| UINT64_C(2080375886), // QVLFSUX | |
| UINT64_C(2080375887), // QVLFSUXA | |
| UINT64_C(2080375822), // QVLFSX | |
| UINT64_C(2080375823), // QVLFSXA | |
| UINT64_C(2080375822), // QVLFSXb | |
| UINT64_C(2080375822), // QVLFSXs | |
| UINT64_C(2080375948), // QVLPCLDX | |
| UINT64_C(2080375820), // QVLPCLSX | |
| UINT64_C(2080375820), // QVLPCLSXint | |
| UINT64_C(2080374924), // QVLPCRDX | |
| UINT64_C(2080374796), // QVLPCRSX | |
| UINT64_C(2080375246), // QVSTFCDUX | |
| UINT64_C(2080375247), // QVSTFCDUXA | |
| UINT64_C(2080375242), // QVSTFCDUXI | |
| UINT64_C(2080375243), // QVSTFCDUXIA | |
| UINT64_C(2080375182), // QVSTFCDX | |
| UINT64_C(2080375183), // QVSTFCDXA | |
| UINT64_C(2080375178), // QVSTFCDXI | |
| UINT64_C(2080375179), // QVSTFCDXIA | |
| UINT64_C(2080375118), // QVSTFCSUX | |
| UINT64_C(2080375119), // QVSTFCSUXA | |
| UINT64_C(2080375114), // QVSTFCSUXI | |
| UINT64_C(2080375115), // QVSTFCSUXIA | |
| UINT64_C(2080375054), // QVSTFCSX | |
| UINT64_C(2080375055), // QVSTFCSXA | |
| UINT64_C(2080375050), // QVSTFCSXI | |
| UINT64_C(2080375051), // QVSTFCSXIA | |
| UINT64_C(2080375054), // QVSTFCSXs | |
| UINT64_C(2080376270), // QVSTFDUX | |
| UINT64_C(2080376271), // QVSTFDUXA | |
| UINT64_C(2080376266), // QVSTFDUXI | |
| UINT64_C(2080376267), // QVSTFDUXIA | |
| UINT64_C(2080376206), // QVSTFDX | |
| UINT64_C(2080376207), // QVSTFDXA | |
| UINT64_C(2080376202), // QVSTFDXI | |
| UINT64_C(2080376203), // QVSTFDXIA | |
| UINT64_C(2080376206), // QVSTFDXb | |
| UINT64_C(2080376718), // QVSTFIWX | |
| UINT64_C(2080376719), // QVSTFIWXA | |
| UINT64_C(2080376142), // QVSTFSUX | |
| UINT64_C(2080376143), // QVSTFSUXA | |
| UINT64_C(2080376138), // QVSTFSUXI | |
| UINT64_C(2080376139), // QVSTFSUXIA | |
| UINT64_C(2080376142), // QVSTFSUXs | |
| UINT64_C(2080376078), // QVSTFSX | |
| UINT64_C(2080376079), // QVSTFSXA | |
| UINT64_C(2080376074), // QVSTFSXI | |
| UINT64_C(2080376075), // QVSTFSXIA | |
| UINT64_C(2080376078), // QVSTFSXs | |
| UINT64_C(0), // RESTORE_CR | |
| UINT64_C(0), // RESTORE_CRBIT | |
| UINT64_C(0), // RESTORE_VRSAVE | |
| UINT64_C(1275068518), // RFCI | |
| UINT64_C(1275068494), // RFDI | |
| UINT64_C(1275068708), // RFEBB | |
| UINT64_C(1275068516), // RFI | |
| UINT64_C(1275068452), // RFID | |
| UINT64_C(1275068492), // RFMCI | |
| UINT64_C(2013265936), // RLDCL | |
| UINT64_C(2013265937), // RLDCL_rec | |
| UINT64_C(2013265938), // RLDCR | |
| UINT64_C(2013265939), // RLDCR_rec | |
| UINT64_C(2013265928), // RLDIC | |
| UINT64_C(2013265920), // RLDICL | |
| UINT64_C(2013265920), // RLDICL_32 | |
| UINT64_C(2013265920), // RLDICL_32_64 | |
| UINT64_C(2013265921), // RLDICL_32_rec | |
| UINT64_C(2013265921), // RLDICL_rec | |
| UINT64_C(2013265924), // RLDICR | |
| UINT64_C(2013265924), // RLDICR_32 | |
| UINT64_C(2013265925), // RLDICR_rec | |
| UINT64_C(2013265929), // RLDIC_rec | |
| UINT64_C(2013265932), // RLDIMI | |
| UINT64_C(2013265933), // RLDIMI_rec | |
| UINT64_C(1342177280), // RLWIMI | |
| UINT64_C(1342177280), // RLWIMI8 | |
| UINT64_C(1342177281), // RLWIMI8_rec | |
| UINT64_C(1342177281), // RLWIMI_rec | |
| UINT64_C(1409286144), // RLWINM | |
| UINT64_C(1409286144), // RLWINM8 | |
| UINT64_C(1409286145), // RLWINM8_rec | |
| UINT64_C(1409286145), // RLWINM_rec | |
| UINT64_C(1543503872), // RLWNM | |
| UINT64_C(1543503872), // RLWNM8 | |
| UINT64_C(1543503873), // RLWNM8_rec | |
| UINT64_C(1543503873), // RLWNM_rec | |
| UINT64_C(0), // ReadTB | |
| UINT64_C(1140850690), // SC | |
| UINT64_C(0), // SELECT_CC_F16 | |
| UINT64_C(0), // SELECT_CC_F4 | |
| UINT64_C(0), // SELECT_CC_F8 | |
| UINT64_C(0), // SELECT_CC_I4 | |
| UINT64_C(0), // SELECT_CC_I8 | |
| UINT64_C(0), // SELECT_CC_QBRC | |
| UINT64_C(0), // SELECT_CC_QFRC | |
| UINT64_C(0), // SELECT_CC_QSRC | |
| UINT64_C(0), // SELECT_CC_SPE | |
| UINT64_C(0), // SELECT_CC_SPE4 | |
| UINT64_C(0), // SELECT_CC_VRRC | |
| UINT64_C(0), // SELECT_CC_VSFRC | |
| UINT64_C(0), // SELECT_CC_VSRC | |
| UINT64_C(0), // SELECT_CC_VSSRC | |
| UINT64_C(0), // SELECT_F16 | |
| UINT64_C(0), // SELECT_F4 | |
| UINT64_C(0), // SELECT_F8 | |
| UINT64_C(0), // SELECT_I4 | |
| UINT64_C(0), // SELECT_I8 | |
| UINT64_C(0), // SELECT_QBRC | |
| UINT64_C(0), // SELECT_QFRC | |
| UINT64_C(0), // SELECT_QSRC | |
| UINT64_C(0), // SELECT_SPE | |
| UINT64_C(0), // SELECT_SPE4 | |
| UINT64_C(0), // SELECT_VRRC | |
| UINT64_C(0), // SELECT_VSFRC | |
| UINT64_C(0), // SELECT_VSRC | |
| UINT64_C(0), // SELECT_VSSRC | |
| UINT64_C(2080375040), // SETB | |
| UINT64_C(2080375040), // SETB8 | |
| UINT64_C(0), // SETRND | |
| UINT64_C(0), // SETRNDi | |
| UINT64_C(2080376743), // SLBFEE_rec | |
| UINT64_C(2080375780), // SLBIA | |
| UINT64_C(2080375652), // SLBIE | |
| UINT64_C(2080375716), // SLBIEG | |
| UINT64_C(2080376614), // SLBMFEE | |
| UINT64_C(2080376486), // SLBMFEV | |
| UINT64_C(2080375588), // SLBMTE | |
| UINT64_C(2080375460), // SLBSYNC | |
| UINT64_C(2080374838), // SLD | |
| UINT64_C(2080374839), // SLD_rec | |
| UINT64_C(2080374832), // SLW | |
| UINT64_C(2080374832), // SLW8 | |
| UINT64_C(2080374833), // SLW8_rec | |
| UINT64_C(2080374833), // SLW_rec | |
| UINT64_C(2147483648), // SPELWZ | |
| UINT64_C(2080374830), // SPELWZX | |
| UINT64_C(2415919104), // SPESTW | |
| UINT64_C(2080375086), // SPESTWX | |
| UINT64_C(0), // SPILL_CR | |
| UINT64_C(0), // SPILL_CRBIT | |
| UINT64_C(0), // SPILL_VRSAVE | |
| UINT64_C(2080376372), // SRAD | |
| UINT64_C(2080376436), // SRADI | |
| UINT64_C(2080376436), // SRADI_32 | |
| UINT64_C(2080376437), // SRADI_rec | |
| UINT64_C(2080376373), // SRAD_rec | |
| UINT64_C(2080376368), // SRAW | |
| UINT64_C(2080376432), // SRAWI | |
| UINT64_C(2080376433), // SRAWI_rec | |
| UINT64_C(2080376369), // SRAW_rec | |
| UINT64_C(2080375862), // SRD | |
| UINT64_C(2080375863), // SRD_rec | |
| UINT64_C(2080375856), // SRW | |
| UINT64_C(2080375856), // SRW8 | |
| UINT64_C(2080375857), // SRW8_rec | |
| UINT64_C(2080375857), // SRW_rec | |
| UINT64_C(2550136832), // STB | |
| UINT64_C(2550136832), // STB8 | |
| UINT64_C(2080376746), // STBCIX | |
| UINT64_C(2080376173), // STBCX | |
| UINT64_C(2080375230), // STBEPX | |
| UINT64_C(2617245696), // STBU | |
| UINT64_C(2617245696), // STBU8 | |
| UINT64_C(2080375278), // STBUX | |
| UINT64_C(2080375278), // STBUX8 | |
| UINT64_C(2080375214), // STBX | |
| UINT64_C(2080375214), // STBX8 | |
| UINT64_C(2080375214), // STBXTLS | |
| UINT64_C(2080375214), // STBXTLS_ | |
| UINT64_C(2080375214), // STBXTLS_32 | |
| UINT64_C(4160749568), // STD | |
| UINT64_C(2080376268), // STDAT | |
| UINT64_C(2080376104), // STDBRX | |
| UINT64_C(2080376810), // STDCIX | |
| UINT64_C(2080375213), // STDCX | |
| UINT64_C(4160749569), // STDU | |
| UINT64_C(2080375146), // STDUX | |
| UINT64_C(2080375082), // STDX | |
| UINT64_C(2080375082), // STDXTLS | |
| UINT64_C(2080375082), // STDXTLS_ | |
| UINT64_C(3623878656), // STFD | |
| UINT64_C(2080376254), // STFDEPX | |
| UINT64_C(3690987520), // STFDU | |
| UINT64_C(2080376302), // STFDUX | |
| UINT64_C(2080376238), // STFDX | |
| UINT64_C(2080376750), // STFIWX | |
| UINT64_C(3489660928), // STFS | |
| UINT64_C(3556769792), // STFSU | |
| UINT64_C(2080376174), // STFSUX | |
| UINT64_C(2080376110), // STFSX | |
| UINT64_C(2952790016), // STH | |
| UINT64_C(2952790016), // STH8 | |
| UINT64_C(2080376620), // STHBRX | |
| UINT64_C(2080376682), // STHCIX | |
| UINT64_C(2080376237), // STHCX | |
| UINT64_C(2080375614), // STHEPX | |
| UINT64_C(3019898880), // STHU | |
| UINT64_C(3019898880), // STHU8 | |
| UINT64_C(2080375662), // STHUX | |
| UINT64_C(2080375662), // STHUX8 | |
| UINT64_C(2080375598), // STHX | |
| UINT64_C(2080375598), // STHX8 | |
| UINT64_C(2080375598), // STHXTLS | |
| UINT64_C(2080375598), // STHXTLS_ | |
| UINT64_C(2080375598), // STHXTLS_32 | |
| UINT64_C(3154116608), // STMW | |
| UINT64_C(1275069156), // STOP | |
| UINT64_C(2080376234), // STSWI | |
| UINT64_C(2080375054), // STVEBX | |
| UINT64_C(2080375118), // STVEHX | |
| UINT64_C(2080375182), // STVEWX | |
| UINT64_C(2080375246), // STVX | |
| UINT64_C(2080375758), // STVXL | |
| UINT64_C(2415919104), // STW | |
| UINT64_C(2415919104), // STW8 | |
| UINT64_C(2080376204), // STWAT | |
| UINT64_C(2080376108), // STWBRX | |
| UINT64_C(2080376618), // STWCIX | |
| UINT64_C(2080375085), // STWCX | |
| UINT64_C(2080375102), // STWEPX | |
| UINT64_C(2483027968), // STWU | |
| UINT64_C(2483027968), // STWU8 | |
| UINT64_C(2080375150), // STWUX | |
| UINT64_C(2080375150), // STWUX8 | |
| UINT64_C(2080375086), // STWX | |
| UINT64_C(2080375086), // STWX8 | |
| UINT64_C(2080375086), // STWXTLS | |
| UINT64_C(2080375086), // STWXTLS_ | |
| UINT64_C(2080375086), // STWXTLS_32 | |
| UINT64_C(4093640706), // STXSD | |
| UINT64_C(2080376216), // STXSDX | |
| UINT64_C(2080376602), // STXSIBX | |
| UINT64_C(2080376602), // STXSIBXv | |
| UINT64_C(2080376666), // STXSIHX | |
| UINT64_C(2080376666), // STXSIHXv | |
| UINT64_C(2080375064), // STXSIWX | |
| UINT64_C(4093640707), // STXSSP | |
| UINT64_C(2080376088), // STXSSPX | |
| UINT64_C(4093640709), // STXV | |
| UINT64_C(2080376792), // STXVB16X | |
| UINT64_C(2080376728), // STXVD2X | |
| UINT64_C(2080376664), // STXVH8X | |
| UINT64_C(2080375578), // STXVL | |
| UINT64_C(2080375642), // STXVLL | |
| UINT64_C(2080376600), // STXVW4X | |
| UINT64_C(2080375576), // STXVX | |
| UINT64_C(2080374864), // SUBF | |
| UINT64_C(2080374864), // SUBF8 | |
| UINT64_C(2080375888), // SUBF8O | |
| UINT64_C(2080375889), // SUBF8O_rec | |
| UINT64_C(2080374865), // SUBF8_rec | |
| UINT64_C(2080374800), // SUBFC | |
| UINT64_C(2080374800), // SUBFC8 | |
| UINT64_C(2080375824), // SUBFC8O | |
| UINT64_C(2080375825), // SUBFC8O_rec | |
| UINT64_C(2080374801), // SUBFC8_rec | |
| UINT64_C(2080375824), // SUBFCO | |
| UINT64_C(2080375825), // SUBFCO_rec | |
| UINT64_C(2080374801), // SUBFC_rec | |
| UINT64_C(2080375056), // SUBFE | |
| UINT64_C(2080375056), // SUBFE8 | |
| UINT64_C(2080376080), // SUBFE8O | |
| UINT64_C(2080376081), // SUBFE8O_rec | |
| UINT64_C(2080375057), // SUBFE8_rec | |
| UINT64_C(2080376080), // SUBFEO | |
| UINT64_C(2080376081), // SUBFEO_rec | |
| UINT64_C(2080375057), // SUBFE_rec | |
| UINT64_C(536870912), // SUBFIC | |
| UINT64_C(536870912), // SUBFIC8 | |
| UINT64_C(2080375248), // SUBFME | |
| UINT64_C(2080375248), // SUBFME8 | |
| UINT64_C(2080376272), // SUBFME8O | |
| UINT64_C(2080376273), // SUBFME8O_rec | |
| UINT64_C(2080375249), // SUBFME8_rec | |
| UINT64_C(2080376272), // SUBFMEO | |
| UINT64_C(2080376273), // SUBFMEO_rec | |
| UINT64_C(2080375249), // SUBFME_rec | |
| UINT64_C(2080375888), // SUBFO | |
| UINT64_C(2080375889), // SUBFO_rec | |
| UINT64_C(2080375184), // SUBFZE | |
| UINT64_C(2080375184), // SUBFZE8 | |
| UINT64_C(2080376208), // SUBFZE8O | |
| UINT64_C(2080376209), // SUBFZE8O_rec | |
| UINT64_C(2080375185), // SUBFZE8_rec | |
| UINT64_C(2080376208), // SUBFZEO | |
| UINT64_C(2080376209), // SUBFZEO_rec | |
| UINT64_C(2080375185), // SUBFZE_rec | |
| UINT64_C(2080374865), // SUBF_rec | |
| UINT64_C(2080375980), // SYNC | |
| UINT64_C(2080376605), // TABORT | |
| UINT64_C(2080376413), // TABORTDC | |
| UINT64_C(2080376541), // TABORTDCI | |
| UINT64_C(2080376349), // TABORTWC | |
| UINT64_C(2080376477), // TABORTWCI | |
| UINT64_C(1207959552), // TAILB | |
| UINT64_C(1207959552), // TAILB8 | |
| UINT64_C(1207959552), // TAILBA | |
| UINT64_C(1207959552), // TAILBA8 | |
| UINT64_C(1317012512), // TAILBCTR | |
| UINT64_C(1317012512), // TAILBCTR8 | |
| UINT64_C(2080376093), // TBEGIN | |
| UINT64_C(0), // TBEGIN_RET | |
| UINT64_C(2080376220), // TCHECK | |
| UINT64_C(0), // TCHECK_RET | |
| UINT64_C(0), // TCRETURNai | |
| UINT64_C(0), // TCRETURNai8 | |
| UINT64_C(0), // TCRETURNdi | |
| UINT64_C(0), // TCRETURNdi8 | |
| UINT64_C(0), // TCRETURNri | |
| UINT64_C(0), // TCRETURNri8 | |
| UINT64_C(2080374920), // TD | |
| UINT64_C(134217728), // TDI | |
| UINT64_C(2080376157), // TEND | |
| UINT64_C(2080375524), // TLBIA | |
| UINT64_C(2080375396), // TLBIE | |
| UINT64_C(2080375332), // TLBIEL | |
| UINT64_C(2080376356), // TLBIVAX | |
| UINT64_C(2080376740), // TLBLD | |
| UINT64_C(2080376804), // TLBLI | |
| UINT64_C(2080376676), // TLBRE | |
| UINT64_C(2080376676), // TLBRE2 | |
| UINT64_C(2080376612), // TLBSX | |
| UINT64_C(2080376612), // TLBSX2 | |
| UINT64_C(2080376613), // TLBSX2D | |
| UINT64_C(2080375916), // TLBSYNC | |
| UINT64_C(2080376740), // TLBWE | |
| UINT64_C(2080376740), // TLBWE2 | |
| UINT64_C(2145386504), // TRAP | |
| UINT64_C(2080376797), // TRECHKPT | |
| UINT64_C(2080376669), // TRECLAIM | |
| UINT64_C(2080376285), // TSR | |
| UINT64_C(2080374792), // TW | |
| UINT64_C(201326592), // TWI | |
| UINT64_C(0), // UNENCODED_NOP | |
| UINT64_C(0), // UPDATE_VRSAVE | |
| UINT64_C(0), // UpdateGBR | |
| UINT64_C(268436483), // VABSDUB | |
| UINT64_C(268436547), // VABSDUH | |
| UINT64_C(268436611), // VABSDUW | |
| UINT64_C(268435776), // VADDCUQ | |
| UINT64_C(268435840), // VADDCUW | |
| UINT64_C(268435517), // VADDECUQ | |
| UINT64_C(268435516), // VADDEUQM | |
| UINT64_C(268435466), // VADDFP | |
| UINT64_C(268436224), // VADDSBS | |
| UINT64_C(268436288), // VADDSHS | |
| UINT64_C(268436352), // VADDSWS | |
| UINT64_C(268435456), // VADDUBM | |
| UINT64_C(268435968), // VADDUBS | |
| UINT64_C(268435648), // VADDUDM | |
| UINT64_C(268435520), // VADDUHM | |
| UINT64_C(268436032), // VADDUHS | |
| UINT64_C(268435712), // VADDUQM | |
| UINT64_C(268435584), // VADDUWM | |
| UINT64_C(268436096), // VADDUWS | |
| UINT64_C(268436484), // VAND | |
| UINT64_C(268436548), // VANDC | |
| UINT64_C(268436738), // VAVGSB | |
| UINT64_C(268436802), // VAVGSH | |
| UINT64_C(268436866), // VAVGSW | |
| UINT64_C(268436482), // VAVGUB | |
| UINT64_C(268436546), // VAVGUH | |
| UINT64_C(268436610), // VAVGUW | |
| UINT64_C(268436940), // VBPERMD | |
| UINT64_C(268436812), // VBPERMQ | |
| UINT64_C(268436298), // VCFSX | |
| UINT64_C(268436298), // VCFSX_0 | |
| UINT64_C(268436234), // VCFUX | |
| UINT64_C(268436234), // VCFUX_0 | |
| UINT64_C(268436744), // VCIPHER | |
| UINT64_C(268436745), // VCIPHERLAST | |
| UINT64_C(268437250), // VCLZB | |
| UINT64_C(268437442), // VCLZD | |
| UINT64_C(268437314), // VCLZH | |
| UINT64_C(268436994), // VCLZLSBB | |
| UINT64_C(268437378), // VCLZW | |
| UINT64_C(268436422), // VCMPBFP | |
| UINT64_C(268437446), // VCMPBFP_rec | |
| UINT64_C(268435654), // VCMPEQFP | |
| UINT64_C(268436678), // VCMPEQFP_rec | |
| UINT64_C(268435462), // VCMPEQUB | |
| UINT64_C(268436486), // VCMPEQUB_rec | |
| UINT64_C(268435655), // VCMPEQUD | |
| UINT64_C(268436679), // VCMPEQUD_rec | |
| UINT64_C(268435526), // VCMPEQUH | |
| UINT64_C(268436550), // VCMPEQUH_rec | |
| UINT64_C(268435590), // VCMPEQUW | |
| UINT64_C(268436614), // VCMPEQUW_rec | |
| UINT64_C(268435910), // VCMPGEFP | |
| UINT64_C(268436934), // VCMPGEFP_rec | |
| UINT64_C(268436166), // VCMPGTFP | |
| UINT64_C(268437190), // VCMPGTFP_rec | |
| UINT64_C(268436230), // VCMPGTSB | |
| UINT64_C(268437254), // VCMPGTSB_rec | |
| UINT64_C(268436423), // VCMPGTSD | |
| UINT64_C(268437447), // VCMPGTSD_rec | |
| UINT64_C(268436294), // VCMPGTSH | |
| UINT64_C(268437318), // VCMPGTSH_rec | |
| UINT64_C(268436358), // VCMPGTSW | |
| UINT64_C(268437382), // VCMPGTSW_rec | |
| UINT64_C(268435974), // VCMPGTUB | |
| UINT64_C(268436998), // VCMPGTUB_rec | |
| UINT64_C(268436167), // VCMPGTUD | |
| UINT64_C(268437191), // VCMPGTUD_rec | |
| UINT64_C(268436038), // VCMPGTUH | |
| UINT64_C(268437062), // VCMPGTUH_rec | |
| UINT64_C(268436102), // VCMPGTUW | |
| UINT64_C(268437126), // VCMPGTUW_rec | |
| UINT64_C(268435463), // VCMPNEB | |
| UINT64_C(268436487), // VCMPNEB_rec | |
| UINT64_C(268435527), // VCMPNEH | |
| UINT64_C(268436551), // VCMPNEH_rec | |
| UINT64_C(268435591), // VCMPNEW | |
| UINT64_C(268436615), // VCMPNEW_rec | |
| UINT64_C(268435719), // VCMPNEZB | |
| UINT64_C(268436743), // VCMPNEZB_rec | |
| UINT64_C(268435783), // VCMPNEZH | |
| UINT64_C(268436807), // VCMPNEZH_rec | |
| UINT64_C(268435847), // VCMPNEZW | |
| UINT64_C(268436871), // VCMPNEZW_rec | |
| UINT64_C(268436426), // VCTSXS | |
| UINT64_C(268436426), // VCTSXS_0 | |
| UINT64_C(268436362), // VCTUXS | |
| UINT64_C(268436362), // VCTUXS_0 | |
| UINT64_C(270272002), // VCTZB | |
| UINT64_C(270468610), // VCTZD | |
| UINT64_C(270337538), // VCTZH | |
| UINT64_C(268502530), // VCTZLSBB | |
| UINT64_C(270403074), // VCTZW | |
| UINT64_C(268437124), // VEQV | |
| UINT64_C(268435850), // VEXPTEFP | |
| UINT64_C(268436173), // VEXTRACTD | |
| UINT64_C(268435981), // VEXTRACTUB | |
| UINT64_C(268436045), // VEXTRACTUH | |
| UINT64_C(268436109), // VEXTRACTUW | |
| UINT64_C(270009858), // VEXTSB2D | |
| UINT64_C(270009858), // VEXTSB2Ds | |
| UINT64_C(269485570), // VEXTSB2W | |
| UINT64_C(269485570), // VEXTSB2Ws | |
| UINT64_C(270075394), // VEXTSH2D | |
| UINT64_C(270075394), // VEXTSH2Ds | |
| UINT64_C(269551106), // VEXTSH2W | |
| UINT64_C(269551106), // VEXTSH2Ws | |
| UINT64_C(270140930), // VEXTSW2D | |
| UINT64_C(270140930), // VEXTSW2Ds | |
| UINT64_C(268437005), // VEXTUBLX | |
| UINT64_C(268437261), // VEXTUBRX | |
| UINT64_C(268437069), // VEXTUHLX | |
| UINT64_C(268437325), // VEXTUHRX | |
| UINT64_C(268437133), // VEXTUWLX | |
| UINT64_C(268437389), // VEXTUWRX | |
| UINT64_C(268436748), // VGBBD | |
| UINT64_C(268436237), // VINSERTB | |
| UINT64_C(268436429), // VINSERTD | |
| UINT64_C(268436301), // VINSERTH | |
| UINT64_C(268436365), // VINSERTW | |
| UINT64_C(268435914), // VLOGEFP | |
| UINT64_C(268435502), // VMADDFP | |
| UINT64_C(268436490), // VMAXFP | |
| UINT64_C(268435714), // VMAXSB | |
| UINT64_C(268435906), // VMAXSD | |
| UINT64_C(268435778), // VMAXSH | |
| UINT64_C(268435842), // VMAXSW | |
| UINT64_C(268435458), // VMAXUB | |
| UINT64_C(268435650), // VMAXUD | |
| UINT64_C(268435522), // VMAXUH | |
| UINT64_C(268435586), // VMAXUW | |
| UINT64_C(268435488), // VMHADDSHS | |
| UINT64_C(268435489), // VMHRADDSHS | |
| UINT64_C(268436554), // VMINFP | |
| UINT64_C(268436226), // VMINSB | |
| UINT64_C(268436418), // VMINSD | |
| UINT64_C(268436290), // VMINSH | |
| UINT64_C(268436354), // VMINSW | |
| UINT64_C(268435970), // VMINUB | |
| UINT64_C(268436162), // VMINUD | |
| UINT64_C(268436034), // VMINUH | |
| UINT64_C(268436098), // VMINUW | |
| UINT64_C(268435490), // VMLADDUHM | |
| UINT64_C(268437388), // VMRGEW | |
| UINT64_C(268435468), // VMRGHB | |
| UINT64_C(268435532), // VMRGHH | |
| UINT64_C(268435596), // VMRGHW | |
| UINT64_C(268435724), // VMRGLB | |
| UINT64_C(268435788), // VMRGLH | |
| UINT64_C(268435852), // VMRGLW | |
| UINT64_C(268437132), // VMRGOW | |
| UINT64_C(268435493), // VMSUMMBM | |
| UINT64_C(268435496), // VMSUMSHM | |
| UINT64_C(268435497), // VMSUMSHS | |
| UINT64_C(268435492), // VMSUMUBM | |
| UINT64_C(268435494), // VMSUMUHM | |
| UINT64_C(268435495), // VMSUMUHS | |
| UINT64_C(268435457), // VMUL10CUQ | |
| UINT64_C(268435521), // VMUL10ECUQ | |
| UINT64_C(268436033), // VMUL10EUQ | |
| UINT64_C(268435969), // VMUL10UQ | |
| UINT64_C(268436232), // VMULESB | |
| UINT64_C(268436296), // VMULESH | |
| UINT64_C(268436360), // VMULESW | |
| UINT64_C(268435976), // VMULEUB | |
| UINT64_C(268436040), // VMULEUH | |
| UINT64_C(268436104), // VMULEUW | |
| UINT64_C(268435720), // VMULOSB | |
| UINT64_C(268435784), // VMULOSH | |
| UINT64_C(268435848), // VMULOSW | |
| UINT64_C(268435464), // VMULOUB | |
| UINT64_C(268435528), // VMULOUH | |
| UINT64_C(268435592), // VMULOUW | |
| UINT64_C(268435593), // VMULUWM | |
| UINT64_C(268436868), // VNAND | |
| UINT64_C(268436808), // VNCIPHER | |
| UINT64_C(268436809), // VNCIPHERLAST | |
| UINT64_C(268895746), // VNEGD | |
| UINT64_C(268830210), // VNEGW | |
| UINT64_C(268435503), // VNMSUBFP | |
| UINT64_C(268436740), // VNOR | |
| UINT64_C(268436612), // VOR | |
| UINT64_C(268436804), // VORC | |
| UINT64_C(268435499), // VPERM | |
| UINT64_C(268435515), // VPERMR | |
| UINT64_C(268435501), // VPERMXOR | |
| UINT64_C(268436238), // VPKPX | |
| UINT64_C(268436942), // VPKSDSS | |
| UINT64_C(268436814), // VPKSDUS | |
| UINT64_C(268435854), // VPKSHSS | |
| UINT64_C(268435726), // VPKSHUS | |
| UINT64_C(268435918), // VPKSWSS | |
| UINT64_C(268435790), // VPKSWUS | |
| UINT64_C(268436558), // VPKUDUM | |
| UINT64_C(268436686), // VPKUDUS | |
| UINT64_C(268435470), // VPKUHUM | |
| UINT64_C(268435598), // VPKUHUS | |
| UINT64_C(268435534), // VPKUWUM | |
| UINT64_C(268435662), // VPKUWUS | |
| UINT64_C(268436488), // VPMSUMB | |
| UINT64_C(268436680), // VPMSUMD | |
| UINT64_C(268436552), // VPMSUMH | |
| UINT64_C(268436616), // VPMSUMW | |
| UINT64_C(268437251), // VPOPCNTB | |
| UINT64_C(268437443), // VPOPCNTD | |
| UINT64_C(268437315), // VPOPCNTH | |
| UINT64_C(268437379), // VPOPCNTW | |
| UINT64_C(269026818), // VPRTYBD | |
| UINT64_C(269092354), // VPRTYBQ | |
| UINT64_C(268961282), // VPRTYBW | |
| UINT64_C(268435722), // VREFP | |
| UINT64_C(268436170), // VRFIM | |
| UINT64_C(268435978), // VRFIN | |
| UINT64_C(268436106), // VRFIP | |
| UINT64_C(268436042), // VRFIZ | |
| UINT64_C(268435460), // VRLB | |
| UINT64_C(268435652), // VRLD | |
| UINT64_C(268435653), // VRLDMI | |
| UINT64_C(268435909), // VRLDNM | |
| UINT64_C(268435524), // VRLH | |
| UINT64_C(268435588), // VRLW | |
| UINT64_C(268435589), // VRLWMI | |
| UINT64_C(268435845), // VRLWNM | |
| UINT64_C(268435786), // VRSQRTEFP | |
| UINT64_C(268436936), // VSBOX | |
| UINT64_C(268435498), // VSEL | |
| UINT64_C(268437186), // VSHASIGMAD | |
| UINT64_C(268437122), // VSHASIGMAW | |
| UINT64_C(268435908), // VSL | |
| UINT64_C(268435716), // VSLB | |
| UINT64_C(268436932), // VSLD | |
| UINT64_C(268435500), // VSLDOI | |
| UINT64_C(268435780), // VSLH | |
| UINT64_C(268436492), // VSLO | |
| UINT64_C(268437316), // VSLV | |
| UINT64_C(268435844), // VSLW | |
| UINT64_C(268435980), // VSPLTB | |
| UINT64_C(268435980), // VSPLTBs | |
| UINT64_C(268436044), // VSPLTH | |
| UINT64_C(268436044), // VSPLTHs | |
| UINT64_C(268436236), // VSPLTISB | |
| UINT64_C(268436300), // VSPLTISH | |
| UINT64_C(268436364), // VSPLTISW | |
| UINT64_C(268436108), // VSPLTW | |
| UINT64_C(268436164), // VSR | |
| UINT64_C(268436228), // VSRAB | |
| UINT64_C(268436420), // VSRAD | |
| UINT64_C(268436292), // VSRAH | |
| UINT64_C(268436356), // VSRAW | |
| UINT64_C(268435972), // VSRB | |
| UINT64_C(268437188), // VSRD | |
| UINT64_C(268436036), // VSRH | |
| UINT64_C(268436556), // VSRO | |
| UINT64_C(268437252), // VSRV | |
| UINT64_C(268436100), // VSRW | |
| UINT64_C(268436800), // VSUBCUQ | |
| UINT64_C(268436864), // VSUBCUW | |
| UINT64_C(268435519), // VSUBECUQ | |
| UINT64_C(268435518), // VSUBEUQM | |
| UINT64_C(268435530), // VSUBFP | |
| UINT64_C(268437248), // VSUBSBS | |
| UINT64_C(268437312), // VSUBSHS | |
| UINT64_C(268437376), // VSUBSWS | |
| UINT64_C(268436480), // VSUBUBM | |
| UINT64_C(268436992), // VSUBUBS | |
| UINT64_C(268436672), // VSUBUDM | |
| UINT64_C(268436544), // VSUBUHM | |
| UINT64_C(268437056), // VSUBUHS | |
| UINT64_C(268436736), // VSUBUQM | |
| UINT64_C(268436608), // VSUBUWM | |
| UINT64_C(268437120), // VSUBUWS | |
| UINT64_C(268437128), // VSUM2SWS | |
| UINT64_C(268437256), // VSUM4SBS | |
| UINT64_C(268437064), // VSUM4SHS | |
| UINT64_C(268437000), // VSUM4UBS | |
| UINT64_C(268437384), // VSUMSWS | |
| UINT64_C(268436302), // VUPKHPX | |
| UINT64_C(268435982), // VUPKHSB | |
| UINT64_C(268436046), // VUPKHSH | |
| UINT64_C(268437070), // VUPKHSW | |
| UINT64_C(268436430), // VUPKLPX | |
| UINT64_C(268436110), // VUPKLSB | |
| UINT64_C(268436174), // VUPKLSH | |
| UINT64_C(268437198), // VUPKLSW | |
| UINT64_C(268436676), // VXOR | |
| UINT64_C(268436676), // V_SET0 | |
| UINT64_C(268436676), // V_SET0B | |
| UINT64_C(268436676), // V_SET0H | |
| UINT64_C(270467980), // V_SETALLONES | |
| UINT64_C(270467980), // V_SETALLONESB | |
| UINT64_C(270467980), // V_SETALLONESH | |
| UINT64_C(2080374844), // WAIT | |
| UINT64_C(2080375046), // WRTEE | |
| UINT64_C(2080375110), // WRTEEI | |
| UINT64_C(2080375416), // XOR | |
| UINT64_C(2080375416), // XOR8 | |
| UINT64_C(2080375417), // XOR8_rec | |
| UINT64_C(1744830464), // XORI | |
| UINT64_C(1744830464), // XORI8 | |
| UINT64_C(1811939328), // XORIS | |
| UINT64_C(1811939328), // XORIS8 | |
| UINT64_C(2080375417), // XOR_rec | |
| UINT64_C(4026533220), // XSABSDP | |
| UINT64_C(4227860040), // XSABSQP | |
| UINT64_C(4026532096), // XSADDDP | |
| UINT64_C(4227858440), // XSADDQP | |
| UINT64_C(4227858441), // XSADDQPO | |
| UINT64_C(4026531840), // XSADDSP | |
| UINT64_C(4026531864), // XSCMPEQDP | |
| UINT64_C(4026532312), // XSCMPEXPDP | |
| UINT64_C(4227858760), // XSCMPEXPQP | |
| UINT64_C(4026531992), // XSCMPGEDP | |
| UINT64_C(4026531928), // XSCMPGTDP | |
| UINT64_C(4026532184), // XSCMPODP | |
| UINT64_C(4227858696), // XSCMPOQP | |
| UINT64_C(4026532120), // XSCMPUDP | |
| UINT64_C(4227859720), // XSCMPUQP | |
| UINT64_C(4026533248), // XSCPSGNDP | |
| UINT64_C(4227858632), // XSCPSGNQP | |
| UINT64_C(4027647340), // XSCVDPHP | |
| UINT64_C(4229301896), // XSCVDPQP | |
| UINT64_C(4026532900), // XSCVDPSP | |
| UINT64_C(4026532908), // XSCVDPSPN | |
| UINT64_C(4026533216), // XSCVDPSXDS | |
| UINT64_C(4026533216), // XSCVDPSXDSs | |
| UINT64_C(4026532192), // XSCVDPSXWS | |
| UINT64_C(4026532192), // XSCVDPSXWSs | |
| UINT64_C(4026533152), // XSCVDPUXDS | |
| UINT64_C(4026533152), // XSCVDPUXDSs | |
| UINT64_C(4026532128), // XSCVDPUXWS | |
| UINT64_C(4026532128), // XSCVDPUXWSs | |
| UINT64_C(4027581804), // XSCVHPDP | |
| UINT64_C(4229170824), // XSCVQPDP | |
| UINT64_C(4229170825), // XSCVQPDPO | |
| UINT64_C(4229498504), // XSCVQPSDZ | |
| UINT64_C(4228449928), // XSCVQPSWZ | |
| UINT64_C(4228974216), // XSCVQPUDZ | |
| UINT64_C(4227925640), // XSCVQPUWZ | |
| UINT64_C(4228515464), // XSCVSDQP | |
| UINT64_C(4026533156), // XSCVSPDP | |
| UINT64_C(4026533164), // XSCVSPDPN | |
| UINT64_C(4026533344), // XSCVSXDDP | |
| UINT64_C(4026533088), // XSCVSXDSP | |
| UINT64_C(4227991176), // XSCVUDQP | |
| UINT64_C(4026533280), // XSCVUXDDP | |
| UINT64_C(4026533024), // XSCVUXDSP | |
| UINT64_C(4026532288), // XSDIVDP | |
| UINT64_C(4227859528), // XSDIVQP | |
| UINT64_C(4227859529), // XSDIVQPO | |
| UINT64_C(4026532032), // XSDIVSP | |
| UINT64_C(4026533676), // XSIEXPDP | |
| UINT64_C(4227860168), // XSIEXPQP | |
| UINT64_C(4026532104), // XSMADDADP | |
| UINT64_C(4026531848), // XSMADDASP | |
| UINT64_C(4026532168), // XSMADDMDP | |
| UINT64_C(4026531912), // XSMADDMSP | |
| UINT64_C(4227859208), // XSMADDQP | |
| UINT64_C(4227859209), // XSMADDQPO | |
| UINT64_C(4026532864), // XSMAXCDP | |
| UINT64_C(4026533120), // XSMAXDP | |
| UINT64_C(4026532992), // XSMAXJDP | |
| UINT64_C(4026532928), // XSMINCDP | |
| UINT64_C(4026533184), // XSMINDP | |
| UINT64_C(4026533056), // XSMINJDP | |
| UINT64_C(4026532232), // XSMSUBADP | |
| UINT64_C(4026531976), // XSMSUBASP | |
| UINT64_C(4026532296), // XSMSUBMDP | |
| UINT64_C(4026532040), // XSMSUBMSP | |
| UINT64_C(4227859272), // XSMSUBQP | |
| UINT64_C(4227859273), // XSMSUBQPO | |
| UINT64_C(4026532224), // XSMULDP | |
| UINT64_C(4227858504), // XSMULQP | |
| UINT64_C(4227858505), // XSMULQPO | |
| UINT64_C(4026531968), // XSMULSP | |
| UINT64_C(4026533284), // XSNABSDP | |
| UINT64_C(4228384328), // XSNABSQP | |
| UINT64_C(4026533348), // XSNEGDP | |
| UINT64_C(4228908616), // XSNEGQP | |
| UINT64_C(4026533128), // XSNMADDADP | |
| UINT64_C(4026532872), // XSNMADDASP | |
| UINT64_C(4026533192), // XSNMADDMDP | |
| UINT64_C(4026532936), // XSNMADDMSP | |
| UINT64_C(4227859336), // XSNMADDQP | |
| UINT64_C(4227859337), // XSNMADDQPO | |
| UINT64_C(4026533256), // XSNMSUBADP | |
| UINT64_C(4026533000), // XSNMSUBASP | |
| UINT64_C(4026533320), // XSNMSUBMDP | |
| UINT64_C(4026533064), // XSNMSUBMSP | |
| UINT64_C(4227859400), // XSNMSUBQP | |
| UINT64_C(4227859401), // XSNMSUBQPO | |
| UINT64_C(4026532132), // XSRDPI | |
| UINT64_C(4026532268), // XSRDPIC | |
| UINT64_C(4026532324), // XSRDPIM | |
| UINT64_C(4026532260), // XSRDPIP | |
| UINT64_C(4026532196), // XSRDPIZ | |
| UINT64_C(4026532200), // XSREDP | |
| UINT64_C(4026531944), // XSRESP | |
| UINT64_C(4227858442), // XSRQPI | |
| UINT64_C(4227858443), // XSRQPIX | |
| UINT64_C(4227858506), // XSRQPXP | |
| UINT64_C(4026532964), // XSRSP | |
| UINT64_C(4026532136), // XSRSQRTEDP | |
| UINT64_C(4026531880), // XSRSQRTESP | |
| UINT64_C(4026532140), // XSSQRTDP | |
| UINT64_C(4229629512), // XSSQRTQP | |
| UINT64_C(4229629513), // XSSQRTQPO | |
| UINT64_C(4026531884), // XSSQRTSP | |
| UINT64_C(4026532160), // XSSUBDP | |
| UINT64_C(4227859464), // XSSUBQP | |
| UINT64_C(4227859465), // XSSUBQPO | |
| UINT64_C(4026531904), // XSSUBSP | |
| UINT64_C(4026532328), // XSTDIVDP | |
| UINT64_C(4026532264), // XSTSQRTDP | |
| UINT64_C(4026533288), // XSTSTDCDP | |
| UINT64_C(4227859848), // XSTSTDCQP | |
| UINT64_C(4026533032), // XSTSTDCSP | |
| UINT64_C(4026533228), // XSXEXPDP | |
| UINT64_C(4227991112), // XSXEXPQP | |
| UINT64_C(4026598764), // XSXSIGDP | |
| UINT64_C(4229039688), // XSXSIGQP | |
| UINT64_C(4026533732), // XVABSDP | |
| UINT64_C(4026533476), // XVABSSP | |
| UINT64_C(4026532608), // XVADDDP | |
| UINT64_C(4026532352), // XVADDSP | |
| UINT64_C(4026532632), // XVCMPEQDP | |
| UINT64_C(4026533656), // XVCMPEQDP_rec | |
| UINT64_C(4026532376), // XVCMPEQSP | |
| UINT64_C(4026533400), // XVCMPEQSP_rec | |
| UINT64_C(4026532760), // XVCMPGEDP | |
| UINT64_C(4026533784), // XVCMPGEDP_rec | |
| UINT64_C(4026532504), // XVCMPGESP | |
| UINT64_C(4026533528), // XVCMPGESP_rec | |
| UINT64_C(4026532696), // XVCMPGTDP | |
| UINT64_C(4026533720), // XVCMPGTDP_rec | |
| UINT64_C(4026532440), // XVCMPGTSP | |
| UINT64_C(4026533464), // XVCMPGTSP_rec | |
| UINT64_C(4026533760), // XVCPSGNDP | |
| UINT64_C(4026533504), // XVCPSGNSP | |
| UINT64_C(4026533412), // XVCVDPSP | |
| UINT64_C(4026533728), // XVCVDPSXDS | |
| UINT64_C(4026532704), // XVCVDPSXWS | |
| UINT64_C(4026533664), // XVCVDPUXDS | |
| UINT64_C(4026532640), // XVCVDPUXWS | |
| UINT64_C(4028106604), // XVCVHPSP | |
| UINT64_C(4026533668), // XVCVSPDP | |
| UINT64_C(4028172140), // XVCVSPHP | |
| UINT64_C(4026533472), // XVCVSPSXDS | |
| UINT64_C(4026532448), // XVCVSPSXWS | |
| UINT64_C(4026533408), // XVCVSPUXDS | |
| UINT64_C(4026532384), // XVCVSPUXWS | |
| UINT64_C(4026533856), // XVCVSXDDP | |
| UINT64_C(4026533600), // XVCVSXDSP | |
| UINT64_C(4026532832), // XVCVSXWDP | |
| UINT64_C(4026532576), // XVCVSXWSP | |
| UINT64_C(4026533792), // XVCVUXDDP | |
| UINT64_C(4026533536), // XVCVUXDSP | |
| UINT64_C(4026532768), // XVCVUXWDP | |
| UINT64_C(4026532512), // XVCVUXWSP | |
| UINT64_C(4026532800), // XVDIVDP | |
| UINT64_C(4026532544), // XVDIVSP | |
| UINT64_C(4026533824), // XVIEXPDP | |
| UINT64_C(4026533568), // XVIEXPSP | |
| UINT64_C(4026532616), // XVMADDADP | |
| UINT64_C(4026532360), // XVMADDASP | |
| UINT64_C(4026532680), // XVMADDMDP | |
| UINT64_C(4026532424), // XVMADDMSP | |
| UINT64_C(4026533632), // XVMAXDP | |
| UINT64_C(4026533376), // XVMAXSP | |
| UINT64_C(4026533696), // XVMINDP | |
| UINT64_C(4026533440), // XVMINSP | |
| UINT64_C(4026532744), // XVMSUBADP | |
| UINT64_C(4026532488), // XVMSUBASP | |
| UINT64_C(4026532808), // XVMSUBMDP | |
| UINT64_C(4026532552), // XVMSUBMSP | |
| UINT64_C(4026532736), // XVMULDP | |
| UINT64_C(4026532480), // XVMULSP | |
| UINT64_C(4026533796), // XVNABSDP | |
| UINT64_C(4026533540), // XVNABSSP | |
| UINT64_C(4026533860), // XVNEGDP | |
| UINT64_C(4026533604), // XVNEGSP | |
| UINT64_C(4026533640), // XVNMADDADP | |
| UINT64_C(4026533384), // XVNMADDASP | |
| UINT64_C(4026533704), // XVNMADDMDP | |
| UINT64_C(4026533448), // XVNMADDMSP | |
| UINT64_C(4026533768), // XVNMSUBADP | |
| UINT64_C(4026533512), // XVNMSUBASP | |
| UINT64_C(4026533832), // XVNMSUBMDP | |
| UINT64_C(4026533576), // XVNMSUBMSP | |
| UINT64_C(4026532644), // XVRDPI | |
| UINT64_C(4026532780), // XVRDPIC | |
| UINT64_C(4026532836), // XVRDPIM | |
| UINT64_C(4026532772), // XVRDPIP | |
| UINT64_C(4026532708), // XVRDPIZ | |
| UINT64_C(4026532712), // XVREDP | |
| UINT64_C(4026532456), // XVRESP | |
| UINT64_C(4026532388), // XVRSPI | |
| UINT64_C(4026532524), // XVRSPIC | |
| UINT64_C(4026532580), // XVRSPIM | |
| UINT64_C(4026532516), // XVRSPIP | |
| UINT64_C(4026532452), // XVRSPIZ | |
| UINT64_C(4026532648), // XVRSQRTEDP | |
| UINT64_C(4026532392), // XVRSQRTESP | |
| UINT64_C(4026532652), // XVSQRTDP | |
| UINT64_C(4026532396), // XVSQRTSP | |
| UINT64_C(4026532672), // XVSUBDP | |
| UINT64_C(4026532416), // XVSUBSP | |
| UINT64_C(4026532840), // XVTDIVDP | |
| UINT64_C(4026532584), // XVTDIVSP | |
| UINT64_C(4026532776), // XVTSQRTDP | |
| UINT64_C(4026532520), // XVTSQRTSP | |
| UINT64_C(4026533800), // XVTSTDCDP | |
| UINT64_C(4026533544), // XVTSTDCSP | |
| UINT64_C(4026533740), // XVXEXPDP | |
| UINT64_C(4027058028), // XVXEXPSP | |
| UINT64_C(4026599276), // XVXSIGDP | |
| UINT64_C(4027123564), // XVXSIGSP | |
| UINT64_C(4028041068), // XXBRD | |
| UINT64_C(4026992492), // XXBRH | |
| UINT64_C(4028565356), // XXBRQ | |
| UINT64_C(4027516780), // XXBRW | |
| UINT64_C(4026532500), // XXEXTRACTUW | |
| UINT64_C(4026532564), // XXINSERTW | |
| UINT64_C(4026532880), // XXLAND | |
| UINT64_C(4026532944), // XXLANDC | |
| UINT64_C(4026533328), // XXLEQV | |
| UINT64_C(4026533328), // XXLEQVOnes | |
| UINT64_C(4026533264), // XXLNAND | |
| UINT64_C(4026533136), // XXLNOR | |
| UINT64_C(4026533008), // XXLOR | |
| UINT64_C(4026533200), // XXLORC | |
| UINT64_C(4026533008), // XXLORf | |
| UINT64_C(4026533072), // XXLXOR | |
| UINT64_C(4026533072), // XXLXORdpz | |
| UINT64_C(4026533072), // XXLXORspz | |
| UINT64_C(4026533072), // XXLXORz | |
| UINT64_C(4026531984), // XXMRGHW | |
| UINT64_C(4026532240), // XXMRGLW | |
| UINT64_C(4026532048), // XXPERM | |
| UINT64_C(4026531920), // XXPERMDI | |
| UINT64_C(4026531920), // XXPERMDIs | |
| UINT64_C(4026532304), // XXPERMR | |
| UINT64_C(4026531888), // XXSEL | |
| UINT64_C(4026531856), // XXSLDWI | |
| UINT64_C(4026531856), // XXSLDWIs | |
| UINT64_C(4026532560), // XXSPLTIB | |
| UINT64_C(4026532496), // XXSPLTW | |
| UINT64_C(4026532496), // XXSPLTWs | |
| UINT64_C(1073741824), // gBC | |
| UINT64_C(1073741826), // gBCA | |
| UINT64_C(1073741826), // gBCAat | |
| UINT64_C(1275069472), // gBCCTR | |
| UINT64_C(1275069473), // gBCCTRL | |
| UINT64_C(1073741825), // gBCL | |
| UINT64_C(1073741827), // gBCLA | |
| UINT64_C(1073741827), // gBCLAat | |
| UINT64_C(1275068448), // gBCLR | |
| UINT64_C(1275068449), // gBCLRL | |
| UINT64_C(1073741825), // gBCLat | |
| UINT64_C(1073741824), // gBCat | |
| UINT64_C(0) | |
| }; | |
| const unsigned opcode = MI.getOpcode(); | |
| uint64_t Value = InstBits[opcode]; | |
| uint64_t op = 0; | |
| (void)op; // suppress warning | |
| switch (opcode) { | |
| case PPC::ADDISdtprelHA: | |
| case PPC::ADDISdtprelHA32: | |
| case PPC::ADDISgotTprelHA: | |
| case PPC::ADDIStlsgdHA: | |
| case PPC::ADDIStlsldHA: | |
| case PPC::ADDIStocHA: | |
| case PPC::ADDIStocHA8: | |
| case PPC::ADDIdtprelL: | |
| case PPC::ADDIdtprelL32: | |
| case PPC::ADDItlsgdL: | |
| case PPC::ADDItlsgdL32: | |
| case PPC::ADDItlsgdLADDR: | |
| case PPC::ADDItlsgdLADDR32: | |
| case PPC::ADDItlsldL: | |
| case PPC::ADDItlsldL32: | |
| case PPC::ADDItlsldLADDR: | |
| case PPC::ADDItlsldLADDR32: | |
| case PPC::ADDItocL: | |
| case PPC::ADJCALLSTACKDOWN: | |
| case PPC::ADJCALLSTACKUP: | |
| case PPC::ANDI_rec_1_EQ_BIT: | |
| case PPC::ANDI_rec_1_EQ_BIT8: | |
| case PPC::ANDI_rec_1_GT_BIT: | |
| case PPC::ANDI_rec_1_GT_BIT8: | |
| case PPC::ATOMIC_CMP_SWAP_I16: | |
| case PPC::ATOMIC_CMP_SWAP_I32: | |
| case PPC::ATOMIC_CMP_SWAP_I64: | |
| case PPC::ATOMIC_CMP_SWAP_I8: | |
| case PPC::ATOMIC_LOAD_ADD_I16: | |
| case PPC::ATOMIC_LOAD_ADD_I32: | |
| case PPC::ATOMIC_LOAD_ADD_I64: | |
| case PPC::ATOMIC_LOAD_ADD_I8: | |
| case PPC::ATOMIC_LOAD_AND_I16: | |
| case PPC::ATOMIC_LOAD_AND_I32: | |
| case PPC::ATOMIC_LOAD_AND_I64: | |
| case PPC::ATOMIC_LOAD_AND_I8: | |
| case PPC::ATOMIC_LOAD_MAX_I16: | |
| case PPC::ATOMIC_LOAD_MAX_I32: | |
| case PPC::ATOMIC_LOAD_MAX_I64: | |
| case PPC::ATOMIC_LOAD_MAX_I8: | |
| case PPC::ATOMIC_LOAD_MIN_I16: | |
| case PPC::ATOMIC_LOAD_MIN_I32: | |
| case PPC::ATOMIC_LOAD_MIN_I64: | |
| case PPC::ATOMIC_LOAD_MIN_I8: | |
| case PPC::ATOMIC_LOAD_NAND_I16: | |
| case PPC::ATOMIC_LOAD_NAND_I32: | |
| case PPC::ATOMIC_LOAD_NAND_I64: | |
| case PPC::ATOMIC_LOAD_NAND_I8: | |
| case PPC::ATOMIC_LOAD_OR_I16: | |
| case PPC::ATOMIC_LOAD_OR_I32: | |
| case PPC::ATOMIC_LOAD_OR_I64: | |
| case PPC::ATOMIC_LOAD_OR_I8: | |
| case PPC::ATOMIC_LOAD_SUB_I16: | |
| case PPC::ATOMIC_LOAD_SUB_I32: | |
| case PPC::ATOMIC_LOAD_SUB_I64: | |
| case PPC::ATOMIC_LOAD_SUB_I8: | |
| case PPC::ATOMIC_LOAD_UMAX_I16: | |
| case PPC::ATOMIC_LOAD_UMAX_I32: | |
| case PPC::ATOMIC_LOAD_UMAX_I64: | |
| case PPC::ATOMIC_LOAD_UMAX_I8: | |
| case PPC::ATOMIC_LOAD_UMIN_I16: | |
| case PPC::ATOMIC_LOAD_UMIN_I32: | |
| case PPC::ATOMIC_LOAD_UMIN_I64: | |
| case PPC::ATOMIC_LOAD_UMIN_I8: | |
| case PPC::ATOMIC_LOAD_XOR_I16: | |
| case PPC::ATOMIC_LOAD_XOR_I32: | |
| case PPC::ATOMIC_LOAD_XOR_I64: | |
| case PPC::ATOMIC_LOAD_XOR_I8: | |
| case PPC::ATOMIC_SWAP_I16: | |
| case PPC::ATOMIC_SWAP_I32: | |
| case PPC::ATOMIC_SWAP_I64: | |
| case PPC::ATOMIC_SWAP_I8: | |
| case PPC::ATTN: | |
| case PPC::BCTR: | |
| case PPC::BCTR8: | |
| case PPC::BCTRL: | |
| case PPC::BCTRL8: | |
| case PPC::BDNZLR: | |
| case PPC::BDNZLR8: | |
| case PPC::BDNZLRL: | |
| case PPC::BDNZLRLm: | |
| case PPC::BDNZLRLp: | |
| case PPC::BDNZLRm: | |
| case PPC::BDNZLRp: | |
| case PPC::BDZLR: | |
| case PPC::BDZLR8: | |
| case PPC::BDZLRL: | |
| case PPC::BDZLRLm: | |
| case PPC::BDZLRLp: | |
| case PPC::BDZLRm: | |
| case PPC::BDZLRp: | |
| case PPC::BLR: | |
| case PPC::BLR8: | |
| case PPC::BLRL: | |
| case PPC::CLRBHRB: | |
| case PPC::CP_ABORT: | |
| case PPC::CR6SET: | |
| case PPC::CR6UNSET: | |
| case PPC::DSSALL: | |
| case PPC::DYNALLOC: | |
| case PPC::DYNALLOC8: | |
| case PPC::DYNAREAOFFSET: | |
| case PPC::DYNAREAOFFSET8: | |
| case PPC::EH_SjLj_LongJmp32: | |
| case PPC::EH_SjLj_LongJmp64: | |
| case PPC::EH_SjLj_SetJmp32: | |
| case PPC::EH_SjLj_SetJmp64: | |
| case PPC::EH_SjLj_Setup: | |
| case PPC::EnforceIEIO: | |
| case PPC::FADDrtz: | |
| case PPC::GETtlsADDR: | |
| case PPC::GETtlsADDR32: | |
| case PPC::GETtlsldADDR: | |
| case PPC::GETtlsldADDR32: | |
| case PPC::HRFID: | |
| case PPC::ISYNC: | |
| case PPC::LDgotTprelL: | |
| case PPC::LDgotTprelL32: | |
| case PPC::LDtoc: | |
| case PPC::LDtocBA: | |
| case PPC::LDtocCPT: | |
| case PPC::LDtocJTI: | |
| case PPC::LDtocL: | |
| case PPC::LWZtoc: | |
| case PPC::LWZtocL: | |
| case PPC::MSGSYNC: | |
| case PPC::MSYNC: | |
| case PPC::MoveGOTtoLR: | |
| case PPC::MovePCtoLR: | |
| case PPC::MovePCtoLR8: | |
| case PPC::NAP: | |
| case PPC::NOP: | |
| case PPC::NOP_GT_PWR6: | |
| case PPC::NOP_GT_PWR7: | |
| case PPC::PPC32GOT: | |
| case PPC::PPC32PICGOT: | |
| case PPC::RESTORE_CR: | |
| case PPC::RESTORE_CRBIT: | |
| case PPC::RESTORE_VRSAVE: | |
| case PPC::RFCI: | |
| case PPC::RFDI: | |
| case PPC::RFI: | |
| case PPC::RFID: | |
| case PPC::RFMCI: | |
| case PPC::ReadTB: | |
| case PPC::SELECT_CC_F16: | |
| case PPC::SELECT_CC_F4: | |
| case PPC::SELECT_CC_F8: | |
| case PPC::SELECT_CC_I4: | |
| case PPC::SELECT_CC_I8: | |
| case PPC::SELECT_CC_QBRC: | |
| case PPC::SELECT_CC_QFRC: | |
| case PPC::SELECT_CC_QSRC: | |
| case PPC::SELECT_CC_SPE: | |
| case PPC::SELECT_CC_SPE4: | |
| case PPC::SELECT_CC_VRRC: | |
| case PPC::SELECT_CC_VSFRC: | |
| case PPC::SELECT_CC_VSRC: | |
| case PPC::SELECT_CC_VSSRC: | |
| case PPC::SELECT_F16: | |
| case PPC::SELECT_F4: | |
| case PPC::SELECT_F8: | |
| case PPC::SELECT_I4: | |
| case PPC::SELECT_I8: | |
| case PPC::SELECT_QBRC: | |
| case PPC::SELECT_QFRC: | |
| case PPC::SELECT_QSRC: | |
| case PPC::SELECT_SPE: | |
| case PPC::SELECT_SPE4: | |
| case PPC::SELECT_VRRC: | |
| case PPC::SELECT_VSFRC: | |
| case PPC::SELECT_VSRC: | |
| case PPC::SELECT_VSSRC: | |
| case PPC::SETRND: | |
| case PPC::SETRNDi: | |
| case PPC::SLBIA: | |
| case PPC::SLBSYNC: | |
| case PPC::SPILL_CR: | |
| case PPC::SPILL_CRBIT: | |
| case PPC::SPILL_VRSAVE: | |
| case PPC::STOP: | |
| case PPC::TAILBCTR: | |
| case PPC::TAILBCTR8: | |
| case PPC::TBEGIN_RET: | |
| case PPC::TCHECK_RET: | |
| case PPC::TCRETURNai: | |
| case PPC::TCRETURNai8: | |
| case PPC::TCRETURNdi: | |
| case PPC::TCRETURNdi8: | |
| case PPC::TCRETURNri: | |
| case PPC::TCRETURNri8: | |
| case PPC::TLBIA: | |
| case PPC::TLBRE: | |
| case PPC::TLBSYNC: | |
| case PPC::TLBWE: | |
| case PPC::TRAP: | |
| case PPC::TRECHKPT: | |
| case PPC::UNENCODED_NOP: | |
| case PPC::UPDATE_VRSAVE: | |
| case PPC::UpdateGBR: { | |
| break; | |
| } | |
| case PPC::TEND: { | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(1); | |
| op <<= 25; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::TABORT: | |
| case PPC::TRECLAIM: { | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::DCBA: | |
| case PPC::DCBFEP: | |
| case PPC::DCBI: | |
| case PPC::DCBST: | |
| case PPC::DCBSTEP: | |
| case PPC::DCBZ: | |
| case PPC::DCBZEP: | |
| case PPC::DCBZL: | |
| case PPC::DCBZLEP: | |
| case PPC::DCCCI: | |
| case PPC::ICBI: | |
| case PPC::ICBIEP: | |
| case PPC::ICCCI: | |
| case PPC::TLBIVAX: | |
| case PPC::TLBSX: { | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: B | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::EXTSWSLI: | |
| case PPC::EXTSWSLI_32_64: | |
| case PPC::EXTSWSLI_32_64_rec: | |
| case PPC::EXTSWSLI_rec: | |
| case PPC::SRADI: | |
| case PPC::SRADI_32: | |
| case PPC::SRADI_rec: { | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: RS | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: SH | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 11; | |
| Value |= (op & UINT64_C(32)) >> 4; | |
| break; | |
| } | |
| case PPC::CNTLZD: | |
| case PPC::CNTLZD_rec: | |
| case PPC::CNTLZW: | |
| case PPC::CNTLZW8: | |
| case PPC::CNTLZW8_rec: | |
| case PPC::CNTLZW_rec: | |
| case PPC::CNTTZD: | |
| case PPC::CNTTZD_rec: | |
| case PPC::CNTTZW: | |
| case PPC::CNTTZW8: | |
| case PPC::CNTTZW8_rec: | |
| case PPC::CNTTZW_rec: | |
| case PPC::EXTSB: | |
| case PPC::EXTSB8: | |
| case PPC::EXTSB8_32_64: | |
| case PPC::EXTSB8_rec: | |
| case PPC::EXTSB_rec: | |
| case PPC::EXTSH: | |
| case PPC::EXTSH8: | |
| case PPC::EXTSH8_32_64: | |
| case PPC::EXTSH8_rec: | |
| case PPC::EXTSH_rec: | |
| case PPC::EXTSW: | |
| case PPC::EXTSW_32: | |
| case PPC::EXTSW_32_64: | |
| case PPC::EXTSW_32_64_rec: | |
| case PPC::EXTSW_rec: | |
| case PPC::POPCNTB: | |
| case PPC::POPCNTD: | |
| case PPC::POPCNTW: | |
| case PPC::QVLPCLSXint: { | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: RST | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::AND: | |
| case PPC::AND8: | |
| case PPC::AND8_rec: | |
| case PPC::ANDC: | |
| case PPC::ANDC8: | |
| case PPC::ANDC8_rec: | |
| case PPC::ANDC_rec: | |
| case PPC::AND_rec: | |
| case PPC::BPERMD: | |
| case PPC::CMPB: | |
| case PPC::CMPB8: | |
| case PPC::EQV: | |
| case PPC::EQV8: | |
| case PPC::EQV8_rec: | |
| case PPC::EQV_rec: | |
| case PPC::NAND: | |
| case PPC::NAND8: | |
| case PPC::NAND8_rec: | |
| case PPC::NAND_rec: | |
| case PPC::NOR: | |
| case PPC::NOR8: | |
| case PPC::NOR8_rec: | |
| case PPC::NOR_rec: | |
| case PPC::OR: | |
| case PPC::OR8: | |
| case PPC::OR8_rec: | |
| case PPC::ORC: | |
| case PPC::ORC8: | |
| case PPC::ORC8_rec: | |
| case PPC::ORC_rec: | |
| case PPC::OR_rec: | |
| case PPC::SLD: | |
| case PPC::SLD_rec: | |
| case PPC::SLW: | |
| case PPC::SLW8: | |
| case PPC::SLW8_rec: | |
| case PPC::SLW_rec: | |
| case PPC::SRAD: | |
| case PPC::SRAD_rec: | |
| case PPC::SRAW: | |
| case PPC::SRAWI: | |
| case PPC::SRAWI_rec: | |
| case PPC::SRAW_rec: | |
| case PPC::SRD: | |
| case PPC::SRD_rec: | |
| case PPC::SRW: | |
| case PPC::SRW8: | |
| case PPC::SRW8_rec: | |
| case PPC::SRW_rec: | |
| case PPC::XOR: | |
| case PPC::XOR8: | |
| case PPC::XOR8_rec: | |
| case PPC::XOR_rec: { | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: RST | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: B | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::LBZ: | |
| case PPC::LBZ8: | |
| case PPC::LFD: | |
| case PPC::LFS: | |
| case PPC::LHA: | |
| case PPC::LHA8: | |
| case PPC::LHZ: | |
| case PPC::LHZ8: | |
| case PPC::LMW: | |
| case PPC::LWZ: | |
| case PPC::LWZ8: | |
| case PPC::SPELWZ: | |
| case PPC::SPESTW: | |
| case PPC::STB: | |
| case PPC::STB8: | |
| case PPC::STFD: | |
| case PPC::STFS: | |
| case PPC::STH: | |
| case PPC::STH8: | |
| case PPC::STMW: | |
| case PPC::STW: | |
| case PPC::STW8: { | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: Addr | |
| op = getMemRIEncoding(MI, 1, Fixups, STI); | |
| op &= UINT64_C(2097151); | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::LBZU: | |
| case PPC::LBZU8: | |
| case PPC::LFDU: | |
| case PPC::LFSU: | |
| case PPC::LHAU: | |
| case PPC::LHAU8: | |
| case PPC::LHZU: | |
| case PPC::LHZU8: | |
| case PPC::LWZU: | |
| case PPC::LWZU8: { | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: Addr | |
| op = getMemRIEncoding(MI, 2, Fixups, STI); | |
| op &= UINT64_C(2097151); | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::LI: | |
| case PPC::LI8: | |
| case PPC::LIS: | |
| case PPC::LIS8: { | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: B | |
| op = getImm16Encoding(MI, 1, Fixups, STI); | |
| op &= UINT64_C(65535); | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::ADDI: | |
| case PPC::ADDI8: | |
| case PPC::ADDIC: | |
| case PPC::ADDIC8: | |
| case PPC::ADDIC_rec: | |
| case PPC::ADDIS: | |
| case PPC::ADDIS8: | |
| case PPC::LA: | |
| case PPC::MULLI: | |
| case PPC::MULLI8: | |
| case PPC::SUBFIC: | |
| case PPC::SUBFIC8: | |
| case PPC::TDI: | |
| case PPC::TWI: { | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: B | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: C | |
| op = getImm16Encoding(MI, 2, Fixups, STI); | |
| op &= UINT64_C(65535); | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::STBU: | |
| case PPC::STBU8: | |
| case PPC::STFDU: | |
| case PPC::STFSU: | |
| case PPC::STHU: | |
| case PPC::STHU8: | |
| case PPC::STWU: | |
| case PPC::STWU8: { | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: Addr | |
| op = getMemRIEncoding(MI, 2, Fixups, STI); | |
| op &= UINT64_C(2097151); | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::SLBIE: | |
| case PPC::TLBIEL: | |
| case PPC::TLBLD: | |
| case PPC::TLBLI: { | |
| // op: B | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::ANDI8_rec: | |
| case PPC::ANDIS8_rec: | |
| case PPC::ANDIS_rec: | |
| case PPC::ANDI_rec: | |
| case PPC::ORI: | |
| case PPC::ORI8: | |
| case PPC::ORIS: | |
| case PPC::ORIS8: | |
| case PPC::XORI: | |
| case PPC::XORI8: | |
| case PPC::XORIS: | |
| case PPC::XORIS8: { | |
| // op: B | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: C | |
| op = getImm16Encoding(MI, 2, Fixups, STI); | |
| op &= UINT64_C(65535); | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::BDNZA: | |
| case PPC::BDNZAm: | |
| case PPC::BDNZAp: | |
| case PPC::BDNZLA: | |
| case PPC::BDNZLAm: | |
| case PPC::BDNZLAp: | |
| case PPC::BDZA: | |
| case PPC::BDZAm: | |
| case PPC::BDZAp: | |
| case PPC::BDZLA: | |
| case PPC::BDZLAm: | |
| case PPC::BDZLAp: { | |
| // op: BD | |
| op = getAbsCondBrEncoding(MI, 0, Fixups, STI); | |
| op &= UINT64_C(16383); | |
| op <<= 2; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::BCLalways: | |
| case PPC::BDNZ: | |
| case PPC::BDNZ8: | |
| case PPC::BDNZL: | |
| case PPC::BDNZLm: | |
| case PPC::BDNZLp: | |
| case PPC::BDNZm: | |
| case PPC::BDNZp: | |
| case PPC::BDZ: | |
| case PPC::BDZ8: | |
| case PPC::BDZL: | |
| case PPC::BDZLm: | |
| case PPC::BDZLp: | |
| case PPC::BDZm: | |
| case PPC::BDZp: { | |
| // op: BD | |
| op = getCondBrEncoding(MI, 0, Fixups, STI); | |
| op &= UINT64_C(16383); | |
| op <<= 2; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MCRXRX: | |
| case PPC::TCHECK: { | |
| // op: BF | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(7); | |
| op <<= 23; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MCRF: | |
| case PPC::MCRFS: { | |
| // op: BF | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(7); | |
| op <<= 23; | |
| Value |= op; | |
| // op: BFA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(7); | |
| op <<= 18; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::XSTSTDCQP: { | |
| // op: BF | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(7); | |
| op <<= 23; | |
| Value |= op; | |
| // op: DCMX | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(127); | |
| op <<= 16; | |
| Value |= op; | |
| // op: VB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::XSTSTDCDP: | |
| case PPC::XSTSTDCSP: { | |
| // op: BF | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(7); | |
| op <<= 23; | |
| Value |= op; | |
| // op: DCMX | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(127); | |
| op <<= 16; | |
| Value |= op; | |
| // op: XB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 11; | |
| Value |= (op & UINT64_C(32)) >> 4; | |
| break; | |
| } | |
| case PPC::FCMPUD: | |
| case PPC::FCMPUS: | |
| case PPC::FTDIV: | |
| case PPC::XSCMPEXPQP: | |
| case PPC::XSCMPOQP: | |
| case PPC::XSCMPUQP: { | |
| // op: BF | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(7); | |
| op <<= 23; | |
| Value |= op; | |
| // op: FRA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: FRB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::FTSQRT: { | |
| // op: BF | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(7); | |
| op <<= 23; | |
| Value |= op; | |
| // op: FRB | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::CMPRB: | |
| case PPC::CMPRB8: { | |
| // op: BF | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(7); | |
| op <<= 23; | |
| Value |= op; | |
| // op: L | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(1); | |
| op <<= 21; | |
| Value |= op; | |
| // op: RA | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: RB | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::CMPDI: | |
| case PPC::CMPLDI: | |
| case PPC::CMPLWI: | |
| case PPC::CMPWI: { | |
| // op: BF | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(7); | |
| op <<= 23; | |
| Value |= op; | |
| // op: RA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: I | |
| op = getImm16Encoding(MI, 2, Fixups, STI); | |
| op &= UINT64_C(65535); | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::CMPD: | |
| case PPC::CMPEQB: | |
| case PPC::CMPLD: | |
| case PPC::CMPLW: | |
| case PPC::CMPW: { | |
| // op: BF | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(7); | |
| op <<= 23; | |
| Value |= op; | |
| // op: RA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: RB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MTFSFI: | |
| case PPC::MTFSFI_rec: { | |
| // op: BF | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(7); | |
| op <<= 23; | |
| Value |= op; | |
| // op: W | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(1); | |
| op <<= 16; | |
| Value |= op; | |
| // op: U | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(15); | |
| op <<= 12; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::BCCTR: | |
| case PPC::BCCTR8: | |
| case PPC::BCCTR8n: | |
| case PPC::BCCTRL: | |
| case PPC::BCCTRL8: | |
| case PPC::BCCTRL8n: | |
| case PPC::BCCTRLn: | |
| case PPC::BCCTRn: | |
| case PPC::BCLR: | |
| case PPC::BCLRL: | |
| case PPC::BCLRLn: | |
| case PPC::BCLRn: { | |
| // op: BI | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::BC: | |
| case PPC::BCL: | |
| case PPC::BCLn: | |
| case PPC::BCn: { | |
| // op: BI | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: BD | |
| op = getCondBrEncoding(MI, 1, Fixups, STI); | |
| op &= UINT64_C(16383); | |
| op <<= 2; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::BCCCTR: | |
| case PPC::BCCCTR8: | |
| case PPC::BCCCTRL: | |
| case PPC::BCCCTRL8: | |
| case PPC::BCCLR: | |
| case PPC::BCCLRL: { | |
| // op: BIBO | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(96)) << 11; | |
| // op: CR | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(7); | |
| op <<= 18; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::BCCA: | |
| case PPC::BCCLA: { | |
| // op: BIBO | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(96)) << 11; | |
| // op: CR | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(7); | |
| op <<= 18; | |
| Value |= op; | |
| // op: BD | |
| op = getAbsCondBrEncoding(MI, 2, Fixups, STI); | |
| op &= UINT64_C(16383); | |
| op <<= 2; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::BCC: | |
| case PPC::BCCL: | |
| case PPC::CTRL_DEP: { | |
| // op: BIBO | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(96)) << 11; | |
| // op: CR | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(7); | |
| op <<= 18; | |
| Value |= op; | |
| // op: BD | |
| op = getCondBrEncoding(MI, 2, Fixups, STI); | |
| op &= UINT64_C(16383); | |
| op <<= 2; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::gBCAat: | |
| case PPC::gBCLAat: { | |
| // op: BO | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(28); | |
| op <<= 21; | |
| Value |= op; | |
| // op: at | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(3); | |
| op <<= 21; | |
| Value |= op; | |
| // op: BI | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: BD | |
| op = getAbsCondBrEncoding(MI, 3, Fixups, STI); | |
| op &= UINT64_C(16383); | |
| op <<= 2; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::gBCLat: | |
| case PPC::gBCat: { | |
| // op: BO | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(28); | |
| op <<= 21; | |
| Value |= op; | |
| // op: at | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(3); | |
| op <<= 21; | |
| Value |= op; | |
| // op: BI | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: BD | |
| op = getCondBrEncoding(MI, 3, Fixups, STI); | |
| op &= UINT64_C(16383); | |
| op <<= 2; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::gBCA: | |
| case PPC::gBCLA: { | |
| // op: BO | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: BI | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: BD | |
| op = getAbsCondBrEncoding(MI, 2, Fixups, STI); | |
| op &= UINT64_C(16383); | |
| op <<= 2; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::gBC: | |
| case PPC::gBCL: { | |
| // op: BO | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: BI | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: BD | |
| op = getCondBrEncoding(MI, 2, Fixups, STI); | |
| op &= UINT64_C(16383); | |
| op <<= 2; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::gBCCTR: | |
| case PPC::gBCCTRL: | |
| case PPC::gBCLR: | |
| case PPC::gBCLRL: { | |
| // op: BO | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: BI | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: BH | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(3); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::XSCMPEXPDP: | |
| case PPC::XSCMPODP: | |
| case PPC::XSCMPUDP: | |
| case PPC::XSTDIVDP: | |
| case PPC::XVTDIVDP: | |
| case PPC::XVTDIVSP: { | |
| // op: CR | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(7); | |
| op <<= 23; | |
| Value |= op; | |
| // op: XA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 16; | |
| Value |= (op & UINT64_C(32)) >> 3; | |
| // op: XB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 11; | |
| Value |= (op & UINT64_C(32)) >> 4; | |
| break; | |
| } | |
| case PPC::XSTSQRTDP: | |
| case PPC::XVTSQRTDP: | |
| case PPC::XVTSQRTSP: { | |
| // op: CR | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(7); | |
| op <<= 23; | |
| Value |= op; | |
| // op: XB | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 11; | |
| Value |= (op & UINT64_C(32)) >> 4; | |
| break; | |
| } | |
| case PPC::CRSET: | |
| case PPC::CRUNSET: { | |
| // op: CRD | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(31)) << 16; | |
| Value |= (op & UINT64_C(31)) << 11; | |
| break; | |
| } | |
| case PPC::CRAND: | |
| case PPC::CRANDC: | |
| case PPC::CREQV: | |
| case PPC::CRNAND: | |
| case PPC::CRNOR: | |
| case PPC::CROR: | |
| case PPC::CRORC: | |
| case PPC::CRXOR: { | |
| // op: CRD | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: CRA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: CRB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::ICBLC: | |
| case PPC::ICBLQ: | |
| case PPC::ICBT: | |
| case PPC::ICBTLS: { | |
| // op: CT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(15); | |
| op <<= 21; | |
| Value |= op; | |
| // op: RA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: RB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::BCTRL8_LDinto_toc: { | |
| // op: DS_RA | |
| op = getMemRIXEncoding(MI, 0, Fixups, STI); | |
| op &= UINT64_C(524287); | |
| op <<= 2; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::BCTRL_LWZinto_toc: { | |
| // op: D_RA | |
| op = getMemRIEncoding(MI, 0, Fixups, STI); | |
| op &= UINT64_C(2097151); | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::WRTEEI: { | |
| // op: E | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(1); | |
| op <<= 15; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MTFSFb: { | |
| // op: FM | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(255); | |
| op <<= 17; | |
| Value |= op; | |
| // op: rT | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MTFSB0: | |
| case PPC::MTFSB1: { | |
| // op: FM | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::FADD: | |
| case PPC::FADDS: | |
| case PPC::FADDS_rec: | |
| case PPC::FADD_rec: | |
| case PPC::FDIV: | |
| case PPC::FDIVS: | |
| case PPC::FDIVS_rec: | |
| case PPC::FDIV_rec: | |
| case PPC::FSUB: | |
| case PPC::FSUBS: | |
| case PPC::FSUBS_rec: | |
| case PPC::FSUB_rec: | |
| case PPC::QVFADD: | |
| case PPC::QVFADDS: | |
| case PPC::QVFADDSs: | |
| case PPC::QVFCMPEQ: | |
| case PPC::QVFCMPEQb: | |
| case PPC::QVFCMPEQbs: | |
| case PPC::QVFCMPGT: | |
| case PPC::QVFCMPGTb: | |
| case PPC::QVFCMPGTbs: | |
| case PPC::QVFCMPLT: | |
| case PPC::QVFCMPLTb: | |
| case PPC::QVFCMPLTbs: | |
| case PPC::QVFCPSGN: | |
| case PPC::QVFCPSGNs: | |
| case PPC::QVFSUB: | |
| case PPC::QVFSUBS: | |
| case PPC::QVFSUBSs: | |
| case PPC::QVFTSTNAN: | |
| case PPC::QVFTSTNANb: | |
| case PPC::QVFTSTNANbs: | |
| case PPC::XSIEXPQP: { | |
| // op: FRT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: FRA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: FRB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::QVALIGNI: | |
| case PPC::QVALIGNIb: | |
| case PPC::QVALIGNIs: { | |
| // op: FRT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: FRA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: FRB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| // op: idx | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(3); | |
| op <<= 9; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::QVFLOGICAL: | |
| case PPC::QVFLOGICALb: | |
| case PPC::QVFLOGICALs: { | |
| // op: FRT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: FRA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: FRB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| // op: tttt | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(15); | |
| op <<= 7; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::FMUL: | |
| case PPC::FMULS: | |
| case PPC::FMULS_rec: | |
| case PPC::FMUL_rec: | |
| case PPC::QVFMUL: | |
| case PPC::QVFMULS: | |
| case PPC::QVFMULSs: | |
| case PPC::QVFXMUL: | |
| case PPC::QVFXMULS: { | |
| // op: FRT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: FRA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: FRC | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 6; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::FMADD: | |
| case PPC::FMADDS: | |
| case PPC::FMADDS_rec: | |
| case PPC::FMADD_rec: | |
| case PPC::FMSUB: | |
| case PPC::FMSUBS: | |
| case PPC::FMSUBS_rec: | |
| case PPC::FMSUB_rec: | |
| case PPC::FNMADD: | |
| case PPC::FNMADDS: | |
| case PPC::FNMADDS_rec: | |
| case PPC::FNMADD_rec: | |
| case PPC::FNMSUB: | |
| case PPC::FNMSUBS: | |
| case PPC::FNMSUBS_rec: | |
| case PPC::FNMSUB_rec: | |
| case PPC::FSELD: | |
| case PPC::FSELD_rec: | |
| case PPC::FSELS: | |
| case PPC::FSELS_rec: { | |
| // op: FRT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: FRA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: FRC | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 6; | |
| Value |= op; | |
| // op: FRB | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::QVFMADD: | |
| case PPC::QVFMADDS: | |
| case PPC::QVFMADDSs: | |
| case PPC::QVFMSUB: | |
| case PPC::QVFMSUBS: | |
| case PPC::QVFMSUBSs: | |
| case PPC::QVFNMADD: | |
| case PPC::QVFNMADDS: | |
| case PPC::QVFNMADDSs: | |
| case PPC::QVFNMSUB: | |
| case PPC::QVFNMSUBS: | |
| case PPC::QVFNMSUBSs: | |
| case PPC::QVFPERM: | |
| case PPC::QVFPERMs: | |
| case PPC::QVFSEL: | |
| case PPC::QVFSELb: | |
| case PPC::QVFSELbb: | |
| case PPC::QVFSELbs: | |
| case PPC::QVFXMADD: | |
| case PPC::QVFXMADDS: | |
| case PPC::QVFXXCPNMADD: | |
| case PPC::QVFXXCPNMADDS: | |
| case PPC::QVFXXMADD: | |
| case PPC::QVFXXMADDS: | |
| case PPC::QVFXXNPMADD: | |
| case PPC::QVFXXNPMADDS: { | |
| // op: FRT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: FRA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: FRC | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 6; | |
| Value |= op; | |
| // op: FRB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::QVESPLATI: | |
| case PPC::QVESPLATIb: | |
| case PPC::QVESPLATIs: { | |
| // op: FRT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: FRA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: idx | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(3); | |
| op <<= 9; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::QVFABS: | |
| case PPC::QVFABSs: | |
| case PPC::QVFCFID: | |
| case PPC::QVFCFIDS: | |
| case PPC::QVFCFIDU: | |
| case PPC::QVFCFIDUS: | |
| case PPC::QVFCFIDb: | |
| case PPC::QVFCTID: | |
| case PPC::QVFCTIDU: | |
| case PPC::QVFCTIDUZ: | |
| case PPC::QVFCTIDZ: | |
| case PPC::QVFCTIDb: | |
| case PPC::QVFCTIW: | |
| case PPC::QVFCTIWU: | |
| case PPC::QVFCTIWUZ: | |
| case PPC::QVFCTIWZ: | |
| case PPC::QVFMR: | |
| case PPC::QVFMRb: | |
| case PPC::QVFMRs: | |
| case PPC::QVFNABS: | |
| case PPC::QVFNABSs: | |
| case PPC::QVFNEG: | |
| case PPC::QVFNEGs: | |
| case PPC::QVFRE: | |
| case PPC::QVFRES: | |
| case PPC::QVFRESs: | |
| case PPC::QVFRIM: | |
| case PPC::QVFRIMs: | |
| case PPC::QVFRIN: | |
| case PPC::QVFRINs: | |
| case PPC::QVFRIP: | |
| case PPC::QVFRIPs: | |
| case PPC::QVFRIZ: | |
| case PPC::QVFRIZs: | |
| case PPC::QVFRSP: | |
| case PPC::QVFRSPs: | |
| case PPC::QVFRSQRTE: | |
| case PPC::QVFRSQRTES: | |
| case PPC::QVFRSQRTESs: { | |
| // op: FRT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: FRB | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::QVGPCI: { | |
| // op: FRT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: idx | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(4095); | |
| op <<= 9; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MTCRF: | |
| case PPC::MTCRF8: { | |
| // op: FXM | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(255); | |
| op <<= 12; | |
| Value |= op; | |
| // op: rS | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::TSR: { | |
| // op: L | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(1); | |
| op <<= 21; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::SYNC: | |
| case PPC::WAIT: { | |
| // op: L | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(3); | |
| op <<= 21; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::CP_COPY: | |
| case PPC::CP_COPY8: | |
| case PPC::CP_PASTE: | |
| case PPC::CP_PASTE8: | |
| case PPC::CP_PASTE8_rec: | |
| case PPC::CP_PASTE_rec: { | |
| // op: L | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(1); | |
| op <<= 21; | |
| Value |= op; | |
| // op: RA | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: RB | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MTFSF: | |
| case PPC::MTFSF_rec: { | |
| // op: L | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(1); | |
| op <<= 25; | |
| Value |= op; | |
| // op: FLM | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(255); | |
| op <<= 17; | |
| Value |= op; | |
| // op: W | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(1); | |
| op <<= 16; | |
| Value |= op; | |
| // op: FRB | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::SC: { | |
| // op: LEV | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(127); | |
| op <<= 5; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::BA: | |
| case PPC::BLA: | |
| case PPC::BLA8: | |
| case PPC::TAILBA: | |
| case PPC::TAILBA8: { | |
| // op: LI | |
| op = getAbsDirectBrEncoding(MI, 0, Fixups, STI); | |
| op &= UINT64_C(16777215); | |
| op <<= 2; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::BLA8_NOP: { | |
| // op: LI | |
| op = getAbsDirectBrEncoding(MI, 0, Fixups, STI); | |
| op &= UINT64_C(16777215); | |
| op <<= 34; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::B: | |
| case PPC::BL: | |
| case PPC::BL8: | |
| case PPC::TAILB: | |
| case PPC::TAILB8: { | |
| // op: LI | |
| op = getDirectBrEncoding(MI, 0, Fixups, STI); | |
| op &= UINT64_C(16777215); | |
| op <<= 2; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::BL8_NOP: | |
| case PPC::BL_NOP: { | |
| // op: LI | |
| op = getDirectBrEncoding(MI, 0, Fixups, STI); | |
| op &= UINT64_C(16777215); | |
| op <<= 34; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::BL8_TLS: | |
| case PPC::BL8_TLS_: | |
| case PPC::BL_TLS: { | |
| // op: LI | |
| op = getTLSCallEncoding(MI, 0, Fixups, STI); | |
| op &= UINT64_C(16777215); | |
| op <<= 2; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::BL8_NOP_TLS: { | |
| // op: LI | |
| op = getTLSCallEncoding(MI, 0, Fixups, STI); | |
| op &= UINT64_C(16777215); | |
| op <<= 34; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MBAR: { | |
| // op: MO | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::TBEGIN: { | |
| // op: R | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(1); | |
| op <<= 21; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::RLWINM: | |
| case PPC::RLWINM8: | |
| case PPC::RLWINM8_rec: | |
| case PPC::RLWINM_rec: | |
| case PPC::RLWNM: | |
| case PPC::RLWNM8: | |
| case PPC::RLWNM8_rec: | |
| case PPC::RLWNM_rec: { | |
| // op: RA | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: RS | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: RB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| // op: MB | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 6; | |
| Value |= op; | |
| // op: ME | |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 1; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::RLDCL: | |
| case PPC::RLDCL_rec: | |
| case PPC::RLDCR: | |
| case PPC::RLDCR_rec: { | |
| // op: RA | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: RS | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: RB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| // op: MBE | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 6; | |
| Value |= (op & UINT64_C(32)); | |
| break; | |
| } | |
| case PPC::RLDIC: | |
| case PPC::RLDICL: | |
| case PPC::RLDICL_32: | |
| case PPC::RLDICL_32_64: | |
| case PPC::RLDICL_32_rec: | |
| case PPC::RLDICL_rec: | |
| case PPC::RLDICR: | |
| case PPC::RLDICR_32: | |
| case PPC::RLDICR_rec: | |
| case PPC::RLDIC_rec: { | |
| // op: RA | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: RS | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: SH | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 11; | |
| Value |= (op & UINT64_C(32)) >> 4; | |
| // op: MBE | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 6; | |
| Value |= (op & UINT64_C(32)); | |
| break; | |
| } | |
| case PPC::RLWIMI: | |
| case PPC::RLWIMI8: | |
| case PPC::RLWIMI8_rec: | |
| case PPC::RLWIMI_rec: { | |
| // op: RA | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: RS | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: RB | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| // op: MB | |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 6; | |
| Value |= op; | |
| // op: ME | |
| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 1; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::RLDIMI: | |
| case PPC::RLDIMI_rec: { | |
| // op: RA | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: RS | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: SH | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 11; | |
| Value |= (op & UINT64_C(32)) >> 4; | |
| // op: MBE | |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 6; | |
| Value |= (op & UINT64_C(32)); | |
| break; | |
| } | |
| case PPC::VCLZLSBB: | |
| case PPC::VCTZB: | |
| case PPC::VCTZD: | |
| case PPC::VCTZH: | |
| case PPC::VCTZLSBB: | |
| case PPC::VCTZW: | |
| case PPC::VEXTSB2D: | |
| case PPC::VEXTSB2Ds: | |
| case PPC::VEXTSB2W: | |
| case PPC::VEXTSB2Ws: | |
| case PPC::VEXTSH2D: | |
| case PPC::VEXTSH2Ds: | |
| case PPC::VEXTSH2W: | |
| case PPC::VEXTSH2Ws: | |
| case PPC::VEXTSW2D: | |
| case PPC::VEXTSW2Ds: | |
| case PPC::VNEGD: | |
| case PPC::VNEGW: | |
| case PPC::VPRTYBD: | |
| case PPC::VPRTYBQ: | |
| case PPC::VPRTYBW: { | |
| // op: RD | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: VB | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::WRTEE: { | |
| // op: RS | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MTMSR: | |
| case PPC::MTMSRD: { | |
| // op: RS | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: L | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(1); | |
| op <<= 16; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MFSRIN: | |
| case PPC::MTSRIN: { | |
| // op: RS | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: RB | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MFSR: | |
| case PPC::MTSR: { | |
| // op: RS | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: SR | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(15); | |
| op <<= 16; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MFFS: | |
| case PPC::MFFSCE: | |
| case PPC::MFFSL: | |
| case PPC::MFFS_rec: | |
| case PPC::MFMSR: { | |
| // op: RST | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::FCPSGND: | |
| case PPC::FCPSGND_rec: | |
| case PPC::FCPSGNS: | |
| case PPC::FCPSGNS_rec: | |
| case PPC::LBARX: | |
| case PPC::LBARXL: | |
| case PPC::LBEPX: | |
| case PPC::LBZCIX: | |
| case PPC::LBZX: | |
| case PPC::LBZX8: | |
| case PPC::LDARX: | |
| case PPC::LDARXL: | |
| case PPC::LDAT: | |
| case PPC::LDBRX: | |
| case PPC::LDCIX: | |
| case PPC::LDMX: | |
| case PPC::LDX: | |
| case PPC::LFDEPX: | |
| case PPC::LFDX: | |
| case PPC::LFIWAX: | |
| case PPC::LFIWZX: | |
| case PPC::LFSX: | |
| case PPC::LHARX: | |
| case PPC::LHARXL: | |
| case PPC::LHAX: | |
| case PPC::LHAX8: | |
| case PPC::LHBRX: | |
| case PPC::LHBRX8: | |
| case PPC::LHEPX: | |
| case PPC::LHZCIX: | |
| case PPC::LHZX: | |
| case PPC::LHZX8: | |
| case PPC::LSWI: | |
| case PPC::LVEBX: | |
| case PPC::LVEHX: | |
| case PPC::LVEWX: | |
| case PPC::LVSL: | |
| case PPC::LVSR: | |
| case PPC::LVX: | |
| case PPC::LVXL: | |
| case PPC::LWARX: | |
| case PPC::LWARXL: | |
| case PPC::LWAT: | |
| case PPC::LWAX: | |
| case PPC::LWAX_32: | |
| case PPC::LWBRX: | |
| case PPC::LWBRX8: | |
| case PPC::LWEPX: | |
| case PPC::LWZCIX: | |
| case PPC::LWZX: | |
| case PPC::LWZX8: | |
| case PPC::MODSD: | |
| case PPC::MODSW: | |
| case PPC::MODUD: | |
| case PPC::MODUW: | |
| case PPC::QVLFCDUX: | |
| case PPC::QVLFCDUXA: | |
| case PPC::QVLFCDX: | |
| case PPC::QVLFCDXA: | |
| case PPC::QVLFCSUX: | |
| case PPC::QVLFCSUXA: | |
| case PPC::QVLFCSX: | |
| case PPC::QVLFCSXA: | |
| case PPC::QVLFCSXs: | |
| case PPC::QVLFDUXA: | |
| case PPC::QVLFDX: | |
| case PPC::QVLFDXA: | |
| case PPC::QVLFDXb: | |
| case PPC::QVLFIWAX: | |
| case PPC::QVLFIWAXA: | |
| case PPC::QVLFIWZX: | |
| case PPC::QVLFIWZXA: | |
| case PPC::QVLFSUXA: | |
| case PPC::QVLFSX: | |
| case PPC::QVLFSXA: | |
| case PPC::QVLFSXb: | |
| case PPC::QVLFSXs: | |
| case PPC::QVLPCLDX: | |
| case PPC::QVLPCLSX: | |
| case PPC::QVLPCRDX: | |
| case PPC::QVLPCRSX: | |
| case PPC::QVSTFCDUX: | |
| case PPC::QVSTFCDUXA: | |
| case PPC::QVSTFCDUXI: | |
| case PPC::QVSTFCDUXIA: | |
| case PPC::QVSTFCDX: | |
| case PPC::QVSTFCDXA: | |
| case PPC::QVSTFCDXI: | |
| case PPC::QVSTFCDXIA: | |
| case PPC::QVSTFCSUX: | |
| case PPC::QVSTFCSUXA: | |
| case PPC::QVSTFCSUXI: | |
| case PPC::QVSTFCSUXIA: | |
| case PPC::QVSTFCSX: | |
| case PPC::QVSTFCSXA: | |
| case PPC::QVSTFCSXI: | |
| case PPC::QVSTFCSXIA: | |
| case PPC::QVSTFCSXs: | |
| case PPC::QVSTFDUXA: | |
| case PPC::QVSTFDUXI: | |
| case PPC::QVSTFDUXIA: | |
| case PPC::QVSTFDX: | |
| case PPC::QVSTFDXA: | |
| case PPC::QVSTFDXI: | |
| case PPC::QVSTFDXIA: | |
| case PPC::QVSTFDXb: | |
| case PPC::QVSTFIWX: | |
| case PPC::QVSTFIWXA: | |
| case PPC::QVSTFSUXA: | |
| case PPC::QVSTFSUXI: | |
| case PPC::QVSTFSUXIA: | |
| case PPC::QVSTFSX: | |
| case PPC::QVSTFSXA: | |
| case PPC::QVSTFSXI: | |
| case PPC::QVSTFSXIA: | |
| case PPC::QVSTFSXs: | |
| case PPC::SPELWZX: | |
| case PPC::SPESTWX: | |
| case PPC::STBCIX: | |
| case PPC::STBCX: | |
| case PPC::STBEPX: | |
| case PPC::STBX: | |
| case PPC::STBX8: | |
| case PPC::STDAT: | |
| case PPC::STDBRX: | |
| case PPC::STDCIX: | |
| case PPC::STDCX: | |
| case PPC::STDX: | |
| case PPC::STFDEPX: | |
| case PPC::STFDX: | |
| case PPC::STFIWX: | |
| case PPC::STFSX: | |
| case PPC::STHBRX: | |
| case PPC::STHCIX: | |
| case PPC::STHCX: | |
| case PPC::STHEPX: | |
| case PPC::STHX: | |
| case PPC::STHX8: | |
| case PPC::STSWI: | |
| case PPC::STVEBX: | |
| case PPC::STVEHX: | |
| case PPC::STVEWX: | |
| case PPC::STVX: | |
| case PPC::STVXL: | |
| case PPC::STWAT: | |
| case PPC::STWBRX: | |
| case PPC::STWCIX: | |
| case PPC::STWCX: | |
| case PPC::STWEPX: | |
| case PPC::STWX: | |
| case PPC::STWX8: | |
| case PPC::TABORTDC: | |
| case PPC::TABORTDCI: | |
| case PPC::TABORTWC: | |
| case PPC::TABORTWCI: | |
| case PPC::TD: | |
| case PPC::TLBSX2: | |
| case PPC::TLBSX2D: | |
| case PPC::TW: | |
| case PPC::XSADDQP: | |
| case PPC::XSADDQPO: | |
| case PPC::XSCPSGNQP: | |
| case PPC::XSDIVQP: | |
| case PPC::XSDIVQPO: | |
| case PPC::XSMULQP: | |
| case PPC::XSMULQPO: | |
| case PPC::XSSUBQP: | |
| case PPC::XSSUBQPO: { | |
| // op: RST | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: B | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::LBZXTLS: | |
| case PPC::LBZXTLS_: | |
| case PPC::LBZXTLS_32: | |
| case PPC::LDXTLS: | |
| case PPC::LDXTLS_: | |
| case PPC::LHZXTLS: | |
| case PPC::LHZXTLS_: | |
| case PPC::LHZXTLS_32: | |
| case PPC::LWZXTLS: | |
| case PPC::LWZXTLS_: | |
| case PPC::LWZXTLS_32: | |
| case PPC::STBXTLS: | |
| case PPC::STBXTLS_: | |
| case PPC::STBXTLS_32: | |
| case PPC::STDXTLS: | |
| case PPC::STDXTLS_: | |
| case PPC::STHXTLS: | |
| case PPC::STHXTLS_: | |
| case PPC::STHXTLS_32: | |
| case PPC::STWXTLS: | |
| case PPC::STWXTLS_: | |
| case PPC::STWXTLS_32: { | |
| // op: RST | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: B | |
| op = getTLSRegEncoding(MI, 2, Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::TLBRE2: | |
| case PPC::TLBWE2: { | |
| // op: RST | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: WS | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(1); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::LBZUX: | |
| case PPC::LBZUX8: | |
| case PPC::LDUX: | |
| case PPC::LFDUX: | |
| case PPC::LFSUX: | |
| case PPC::LHAUX: | |
| case PPC::LHAUX8: | |
| case PPC::LHZUX: | |
| case PPC::LHZUX8: | |
| case PPC::LWAUX: | |
| case PPC::LWZUX: | |
| case PPC::LWZUX8: | |
| case PPC::QVLFDUX: | |
| case PPC::QVLFSUX: | |
| case PPC::XSMADDQP: | |
| case PPC::XSMADDQPO: | |
| case PPC::XSMSUBQP: | |
| case PPC::XSMSUBQPO: | |
| case PPC::XSNMADDQP: | |
| case PPC::XSNMADDQPO: | |
| case PPC::XSNMSUBQP: | |
| case PPC::XSNMSUBQPO: { | |
| // op: RST | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: B | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::FABSD: | |
| case PPC::FABSD_rec: | |
| case PPC::FABSS: | |
| case PPC::FABSS_rec: | |
| case PPC::FCFID: | |
| case PPC::FCFIDS: | |
| case PPC::FCFIDS_rec: | |
| case PPC::FCFIDU: | |
| case PPC::FCFIDUS: | |
| case PPC::FCFIDUS_rec: | |
| case PPC::FCFIDU_rec: | |
| case PPC::FCFID_rec: | |
| case PPC::FCTID: | |
| case PPC::FCTIDU: | |
| case PPC::FCTIDUZ: | |
| case PPC::FCTIDUZ_rec: | |
| case PPC::FCTIDU_rec: | |
| case PPC::FCTIDZ: | |
| case PPC::FCTIDZ_rec: | |
| case PPC::FCTID_rec: | |
| case PPC::FCTIW: | |
| case PPC::FCTIWU: | |
| case PPC::FCTIWUZ: | |
| case PPC::FCTIWUZ_rec: | |
| case PPC::FCTIWU_rec: | |
| case PPC::FCTIWZ: | |
| case PPC::FCTIWZ_rec: | |
| case PPC::FCTIW_rec: | |
| case PPC::FMR: | |
| case PPC::FMR_rec: | |
| case PPC::FNABSD: | |
| case PPC::FNABSD_rec: | |
| case PPC::FNABSS: | |
| case PPC::FNABSS_rec: | |
| case PPC::FNEGD: | |
| case PPC::FNEGD_rec: | |
| case PPC::FNEGS: | |
| case PPC::FNEGS_rec: | |
| case PPC::FRE: | |
| case PPC::FRES: | |
| case PPC::FRES_rec: | |
| case PPC::FRE_rec: | |
| case PPC::FRIMD: | |
| case PPC::FRIMD_rec: | |
| case PPC::FRIMS: | |
| case PPC::FRIMS_rec: | |
| case PPC::FRIND: | |
| case PPC::FRIND_rec: | |
| case PPC::FRINS: | |
| case PPC::FRINS_rec: | |
| case PPC::FRIPD: | |
| case PPC::FRIPD_rec: | |
| case PPC::FRIPS: | |
| case PPC::FRIPS_rec: | |
| case PPC::FRIZD: | |
| case PPC::FRIZD_rec: | |
| case PPC::FRIZS: | |
| case PPC::FRIZS_rec: | |
| case PPC::FRSP: | |
| case PPC::FRSP_rec: | |
| case PPC::FRSQRTE: | |
| case PPC::FRSQRTES: | |
| case PPC::FRSQRTES_rec: | |
| case PPC::FRSQRTE_rec: | |
| case PPC::FSQRT: | |
| case PPC::FSQRTS: | |
| case PPC::FSQRTS_rec: | |
| case PPC::FSQRT_rec: | |
| case PPC::SLBFEE_rec: | |
| case PPC::SLBIEG: | |
| case PPC::SLBMFEE: | |
| case PPC::SLBMTE: | |
| case PPC::TLBIE: | |
| case PPC::XSABSQP: | |
| case PPC::XSCVDPQP: | |
| case PPC::XSCVQPDP: | |
| case PPC::XSCVQPDPO: | |
| case PPC::XSCVQPSDZ: | |
| case PPC::XSCVQPSWZ: | |
| case PPC::XSCVQPUDZ: | |
| case PPC::XSCVQPUWZ: | |
| case PPC::XSCVSDQP: | |
| case PPC::XSCVUDQP: | |
| case PPC::XSNABSQP: | |
| case PPC::XSNEGQP: | |
| case PPC::XSSQRTQP: | |
| case PPC::XSSQRTQPO: | |
| case PPC::XSXEXPQP: | |
| case PPC::XSXSIGQP: { | |
| // op: RST | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: B | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MFFSCDRNI: { | |
| // op: RST | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: DRM | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(7); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::LD: | |
| case PPC::LWA: | |
| case PPC::LWA_32: | |
| case PPC::LXSD: | |
| case PPC::LXSSP: | |
| case PPC::STD: | |
| case PPC::STXSD: | |
| case PPC::STXSSP: { | |
| // op: RST | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: DS_RA | |
| op = getMemRIXEncoding(MI, 1, Fixups, STI); | |
| op &= UINT64_C(524287); | |
| op <<= 2; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::LDU: { | |
| // op: RST | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: DS_RA | |
| op = getMemRIXEncoding(MI, 2, Fixups, STI); | |
| op &= UINT64_C(524287); | |
| op <<= 2; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MFFSCDRN: | |
| case PPC::MFFSCRN: { | |
| // op: RST | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: FRB | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MFFSCRNI: { | |
| // op: RST | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: RM | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(3); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::QVSTFDUX: | |
| case PPC::QVSTFSUX: | |
| case PPC::QVSTFSUXs: | |
| case PPC::STBUX: | |
| case PPC::STBUX8: | |
| case PPC::STDUX: | |
| case PPC::STFDUX: | |
| case PPC::STFSUX: | |
| case PPC::STHUX: | |
| case PPC::STHUX8: | |
| case PPC::STWUX: | |
| case PPC::STWUX8: { | |
| // op: RST | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: B | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::STDU: { | |
| // op: RST | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: DS_RA | |
| op = getMemRIXEncoding(MI, 2, Fixups, STI); | |
| op &= UINT64_C(524287); | |
| op <<= 2; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MFCR: | |
| case PPC::MFCR8: | |
| case PPC::MFCTR: | |
| case PPC::MFCTR8: | |
| case PPC::MFLR: | |
| case PPC::MFLR8: | |
| case PPC::MFTB8: | |
| case PPC::MFVRSAVE: | |
| case PPC::MFVRSAVEv: | |
| case PPC::MTCTR: | |
| case PPC::MTCTR8: | |
| case PPC::MTCTR8loop: | |
| case PPC::MTCTRloop: | |
| case PPC::MTLR: | |
| case PPC::MTLR8: | |
| case PPC::MTVRSAVE: | |
| case PPC::MTVRSAVEv: { | |
| // op: RT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::SETB: | |
| case PPC::SETB8: { | |
| // op: RT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: BFA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(7); | |
| op <<= 18; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::ADDPCIS: { | |
| // op: RT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: D | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| Value |= (op & UINT64_C(62)) << 15; | |
| Value |= (op & UINT64_C(65472)); | |
| Value |= (op & UINT64_C(1)); | |
| break; | |
| } | |
| case PPC::EVLHHESPLAT: | |
| case PPC::EVLHHOSSPLAT: | |
| case PPC::EVLHHOUSPLAT: { | |
| // op: RT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: D | |
| op = getSPE2DisEncoding(MI, 1, Fixups, STI); | |
| Value |= (op & UINT64_C(1)) << 20; | |
| Value |= (op & UINT64_C(2)) << 18; | |
| Value |= (op & UINT64_C(4)) << 16; | |
| Value |= (op & UINT64_C(8)) << 14; | |
| Value |= (op & UINT64_C(16)) << 12; | |
| Value |= (op & UINT64_C(32)) << 10; | |
| Value |= (op & UINT64_C(64)) << 8; | |
| Value |= (op & UINT64_C(128)) << 6; | |
| Value |= (op & UINT64_C(256)) << 4; | |
| Value |= (op & UINT64_C(512)) << 2; | |
| break; | |
| } | |
| case PPC::EVLWHE: | |
| case PPC::EVLWHOS: | |
| case PPC::EVLWHOU: | |
| case PPC::EVLWHSPLAT: | |
| case PPC::EVLWWSPLAT: | |
| case PPC::EVSTWHE: | |
| case PPC::EVSTWHO: | |
| case PPC::EVSTWWE: | |
| case PPC::EVSTWWO: { | |
| // op: RT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: D | |
| op = getSPE4DisEncoding(MI, 1, Fixups, STI); | |
| Value |= (op & UINT64_C(1)) << 20; | |
| Value |= (op & UINT64_C(2)) << 18; | |
| Value |= (op & UINT64_C(4)) << 16; | |
| Value |= (op & UINT64_C(8)) << 14; | |
| Value |= (op & UINT64_C(16)) << 12; | |
| Value |= (op & UINT64_C(32)) << 10; | |
| Value |= (op & UINT64_C(64)) << 8; | |
| Value |= (op & UINT64_C(128)) << 6; | |
| Value |= (op & UINT64_C(256)) << 4; | |
| Value |= (op & UINT64_C(512)) << 2; | |
| break; | |
| } | |
| case PPC::EVLDD: | |
| case PPC::EVLDH: | |
| case PPC::EVLDW: | |
| case PPC::EVSTDD: | |
| case PPC::EVSTDH: | |
| case PPC::EVSTDW: { | |
| // op: RT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: D | |
| op = getSPE8DisEncoding(MI, 1, Fixups, STI); | |
| Value |= (op & UINT64_C(1)) << 20; | |
| Value |= (op & UINT64_C(2)) << 18; | |
| Value |= (op & UINT64_C(4)) << 16; | |
| Value |= (op & UINT64_C(8)) << 14; | |
| Value |= (op & UINT64_C(16)) << 12; | |
| Value |= (op & UINT64_C(32)) << 10; | |
| Value |= (op & UINT64_C(64)) << 8; | |
| Value |= (op & UINT64_C(128)) << 6; | |
| Value |= (op & UINT64_C(256)) << 4; | |
| Value |= (op & UINT64_C(512)) << 2; | |
| break; | |
| } | |
| case PPC::MFBHRBE: { | |
| // op: RT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: Entry | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(1023); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::DARN: { | |
| // op: RT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: L | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(3); | |
| op <<= 16; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::ADDME: | |
| case PPC::ADDME8: | |
| case PPC::ADDME8O: | |
| case PPC::ADDME8O_rec: | |
| case PPC::ADDME8_rec: | |
| case PPC::ADDMEO: | |
| case PPC::ADDMEO_rec: | |
| case PPC::ADDME_rec: | |
| case PPC::ADDZE: | |
| case PPC::ADDZE8: | |
| case PPC::ADDZE8O: | |
| case PPC::ADDZE8O_rec: | |
| case PPC::ADDZE8_rec: | |
| case PPC::ADDZEO: | |
| case PPC::ADDZEO_rec: | |
| case PPC::ADDZE_rec: | |
| case PPC::EFDABS: | |
| case PPC::EFDNABS: | |
| case PPC::EFDNEG: | |
| case PPC::EFSABS: | |
| case PPC::EFSNABS: | |
| case PPC::EFSNEG: | |
| case PPC::EVABS: | |
| case PPC::EVADDSMIAAW: | |
| case PPC::EVADDSSIAAW: | |
| case PPC::EVADDUMIAAW: | |
| case PPC::EVADDUSIAAW: | |
| case PPC::EVCNTLSW: | |
| case PPC::EVCNTLZW: | |
| case PPC::EVEXTSB: | |
| case PPC::EVEXTSH: | |
| case PPC::EVFSABS: | |
| case PPC::EVFSNABS: | |
| case PPC::EVFSNEG: | |
| case PPC::EVMRA: | |
| case PPC::EVNEG: | |
| case PPC::EVRNDW: | |
| case PPC::EVSPLATFI: | |
| case PPC::EVSPLATI: | |
| case PPC::EVSUBFSMIAAW: | |
| case PPC::EVSUBFSSIAAW: | |
| case PPC::EVSUBFUMIAAW: | |
| case PPC::EVSUBFUSIAAW: | |
| case PPC::NEG: | |
| case PPC::NEG8: | |
| case PPC::NEG8O: | |
| case PPC::NEG8O_rec: | |
| case PPC::NEG8_rec: | |
| case PPC::NEGO: | |
| case PPC::NEGO_rec: | |
| case PPC::NEG_rec: | |
| case PPC::SUBFME: | |
| case PPC::SUBFME8: | |
| case PPC::SUBFME8O: | |
| case PPC::SUBFME8O_rec: | |
| case PPC::SUBFME8_rec: | |
| case PPC::SUBFMEO: | |
| case PPC::SUBFMEO_rec: | |
| case PPC::SUBFME_rec: | |
| case PPC::SUBFZE: | |
| case PPC::SUBFZE8: | |
| case PPC::SUBFZE8O: | |
| case PPC::SUBFZE8O_rec: | |
| case PPC::SUBFZE8_rec: | |
| case PPC::SUBFZEO: | |
| case PPC::SUBFZEO_rec: | |
| case PPC::SUBFZE_rec: { | |
| // op: RT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: RA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::ADD4: | |
| case PPC::ADD4O: | |
| case PPC::ADD4O_rec: | |
| case PPC::ADD4_rec: | |
| case PPC::ADD8: | |
| case PPC::ADD8O: | |
| case PPC::ADD8O_rec: | |
| case PPC::ADD8_rec: | |
| case PPC::ADDC: | |
| case PPC::ADDC8: | |
| case PPC::ADDC8O: | |
| case PPC::ADDC8O_rec: | |
| case PPC::ADDC8_rec: | |
| case PPC::ADDCO: | |
| case PPC::ADDCO_rec: | |
| case PPC::ADDC_rec: | |
| case PPC::ADDE: | |
| case PPC::ADDE8: | |
| case PPC::ADDE8O: | |
| case PPC::ADDE8O_rec: | |
| case PPC::ADDE8_rec: | |
| case PPC::ADDEO: | |
| case PPC::ADDEO_rec: | |
| case PPC::ADDE_rec: | |
| case PPC::BRINC: | |
| case PPC::DIVD: | |
| case PPC::DIVDE: | |
| case PPC::DIVDEO: | |
| case PPC::DIVDEO_rec: | |
| case PPC::DIVDEU: | |
| case PPC::DIVDEUO: | |
| case PPC::DIVDEUO_rec: | |
| case PPC::DIVDEU_rec: | |
| case PPC::DIVDE_rec: | |
| case PPC::DIVDO: | |
| case PPC::DIVDO_rec: | |
| case PPC::DIVDU: | |
| case PPC::DIVDUO: | |
| case PPC::DIVDUO_rec: | |
| case PPC::DIVDU_rec: | |
| case PPC::DIVD_rec: | |
| case PPC::DIVW: | |
| case PPC::DIVWE: | |
| case PPC::DIVWEO: | |
| case PPC::DIVWEO_rec: | |
| case PPC::DIVWEU: | |
| case PPC::DIVWEUO: | |
| case PPC::DIVWEUO_rec: | |
| case PPC::DIVWEU_rec: | |
| case PPC::DIVWE_rec: | |
| case PPC::DIVWO: | |
| case PPC::DIVWO_rec: | |
| case PPC::DIVWU: | |
| case PPC::DIVWUO: | |
| case PPC::DIVWUO_rec: | |
| case PPC::DIVWU_rec: | |
| case PPC::DIVW_rec: | |
| case PPC::EFDADD: | |
| case PPC::EFDDIV: | |
| case PPC::EFDMUL: | |
| case PPC::EFDSUB: | |
| case PPC::EFSADD: | |
| case PPC::EFSDIV: | |
| case PPC::EFSMUL: | |
| case PPC::EFSSUB: | |
| case PPC::EVADDIW: | |
| case PPC::EVADDW: | |
| case PPC::EVAND: | |
| case PPC::EVANDC: | |
| case PPC::EVDIVWS: | |
| case PPC::EVDIVWU: | |
| case PPC::EVEQV: | |
| case PPC::EVFSADD: | |
| case PPC::EVFSDIV: | |
| case PPC::EVFSMUL: | |
| case PPC::EVFSSUB: | |
| case PPC::EVLDDX: | |
| case PPC::EVLDHX: | |
| case PPC::EVLDWX: | |
| case PPC::EVLHHESPLATX: | |
| case PPC::EVLHHOSSPLATX: | |
| case PPC::EVLHHOUSPLATX: | |
| case PPC::EVLWHEX: | |
| case PPC::EVLWHOSX: | |
| case PPC::EVLWHOUX: | |
| case PPC::EVLWHSPLATX: | |
| case PPC::EVLWWSPLATX: | |
| case PPC::EVMERGEHI: | |
| case PPC::EVMERGEHILO: | |
| case PPC::EVMERGELO: | |
| case PPC::EVMERGELOHI: | |
| case PPC::EVMHEGSMFAA: | |
| case PPC::EVMHEGSMFAN: | |
| case PPC::EVMHEGSMIAA: | |
| case PPC::EVMHEGSMIAN: | |
| case PPC::EVMHEGUMIAA: | |
| case PPC::EVMHEGUMIAN: | |
| case PPC::EVMHESMF: | |
| case PPC::EVMHESMFA: | |
| case PPC::EVMHESMFAAW: | |
| case PPC::EVMHESMFANW: | |
| case PPC::EVMHESMI: | |
| case PPC::EVMHESMIA: | |
| case PPC::EVMHESMIAAW: | |
| case PPC::EVMHESMIANW: | |
| case PPC::EVMHESSF: | |
| case PPC::EVMHESSFA: | |
| case PPC::EVMHESSFAAW: | |
| case PPC::EVMHESSFANW: | |
| case PPC::EVMHESSIAAW: | |
| case PPC::EVMHESSIANW: | |
| case PPC::EVMHEUMI: | |
| case PPC::EVMHEUMIA: | |
| case PPC::EVMHEUMIAAW: | |
| case PPC::EVMHEUMIANW: | |
| case PPC::EVMHEUSIAAW: | |
| case PPC::EVMHEUSIANW: | |
| case PPC::EVMHOGSMFAA: | |
| case PPC::EVMHOGSMFAN: | |
| case PPC::EVMHOGSMIAA: | |
| case PPC::EVMHOGSMIAN: | |
| case PPC::EVMHOGUMIAA: | |
| case PPC::EVMHOGUMIAN: | |
| case PPC::EVMHOSMF: | |
| case PPC::EVMHOSMFA: | |
| case PPC::EVMHOSMFAAW: | |
| case PPC::EVMHOSMFANW: | |
| case PPC::EVMHOSMI: | |
| case PPC::EVMHOSMIA: | |
| case PPC::EVMHOSMIAAW: | |
| case PPC::EVMHOSMIANW: | |
| case PPC::EVMHOSSF: | |
| case PPC::EVMHOSSFA: | |
| case PPC::EVMHOSSFAAW: | |
| case PPC::EVMHOSSFANW: | |
| case PPC::EVMHOSSIAAW: | |
| case PPC::EVMHOSSIANW: | |
| case PPC::EVMHOUMI: | |
| case PPC::EVMHOUMIA: | |
| case PPC::EVMHOUMIAAW: | |
| case PPC::EVMHOUMIANW: | |
| case PPC::EVMHOUSIAAW: | |
| case PPC::EVMHOUSIANW: | |
| case PPC::EVMWHSMF: | |
| case PPC::EVMWHSMFA: | |
| case PPC::EVMWHSMI: | |
| case PPC::EVMWHSMIA: | |
| case PPC::EVMWHSSF: | |
| case PPC::EVMWHSSFA: | |
| case PPC::EVMWHUMI: | |
| case PPC::EVMWHUMIA: | |
| case PPC::EVMWLSMIAAW: | |
| case PPC::EVMWLSMIANW: | |
| case PPC::EVMWLSSIAAW: | |
| case PPC::EVMWLSSIANW: | |
| case PPC::EVMWLUMI: | |
| case PPC::EVMWLUMIA: | |
| case PPC::EVMWLUMIAAW: | |
| case PPC::EVMWLUMIANW: | |
| case PPC::EVMWLUSIAAW: | |
| case PPC::EVMWLUSIANW: | |
| case PPC::EVMWSMF: | |
| case PPC::EVMWSMFA: | |
| case PPC::EVMWSMFAA: | |
| case PPC::EVMWSMFAN: | |
| case PPC::EVMWSMI: | |
| case PPC::EVMWSMIA: | |
| case PPC::EVMWSMIAA: | |
| case PPC::EVMWSMIAN: | |
| case PPC::EVMWSSF: | |
| case PPC::EVMWSSFA: | |
| case PPC::EVMWSSFAA: | |
| case PPC::EVMWSSFAN: | |
| case PPC::EVMWUMI: | |
| case PPC::EVMWUMIA: | |
| case PPC::EVMWUMIAA: | |
| case PPC::EVMWUMIAN: | |
| case PPC::EVNAND: | |
| case PPC::EVNOR: | |
| case PPC::EVOR: | |
| case PPC::EVORC: | |
| case PPC::EVRLW: | |
| case PPC::EVRLWI: | |
| case PPC::EVSLW: | |
| case PPC::EVSLWI: | |
| case PPC::EVSRWIS: | |
| case PPC::EVSRWIU: | |
| case PPC::EVSRWS: | |
| case PPC::EVSRWU: | |
| case PPC::EVSTDDX: | |
| case PPC::EVSTDHX: | |
| case PPC::EVSTDWX: | |
| case PPC::EVSTWHEX: | |
| case PPC::EVSTWHOX: | |
| case PPC::EVSTWWEX: | |
| case PPC::EVSTWWOX: | |
| case PPC::EVSUBFW: | |
| case PPC::EVSUBIFW: | |
| case PPC::EVXOR: | |
| case PPC::MULHD: | |
| case PPC::MULHDU: | |
| case PPC::MULHDU_rec: | |
| case PPC::MULHD_rec: | |
| case PPC::MULHW: | |
| case PPC::MULHWU: | |
| case PPC::MULHWU_rec: | |
| case PPC::MULHW_rec: | |
| case PPC::MULLD: | |
| case PPC::MULLDO: | |
| case PPC::MULLDO_rec: | |
| case PPC::MULLD_rec: | |
| case PPC::MULLW: | |
| case PPC::MULLWO: | |
| case PPC::MULLWO_rec: | |
| case PPC::MULLW_rec: | |
| case PPC::SUBF: | |
| case PPC::SUBF8: | |
| case PPC::SUBF8O: | |
| case PPC::SUBF8O_rec: | |
| case PPC::SUBF8_rec: | |
| case PPC::SUBFC: | |
| case PPC::SUBFC8: | |
| case PPC::SUBFC8O: | |
| case PPC::SUBFC8O_rec: | |
| case PPC::SUBFC8_rec: | |
| case PPC::SUBFCO: | |
| case PPC::SUBFCO_rec: | |
| case PPC::SUBFC_rec: | |
| case PPC::SUBFE: | |
| case PPC::SUBFE8: | |
| case PPC::SUBFE8O: | |
| case PPC::SUBFE8O_rec: | |
| case PPC::SUBFE8_rec: | |
| case PPC::SUBFEO: | |
| case PPC::SUBFEO_rec: | |
| case PPC::SUBFE_rec: | |
| case PPC::SUBFO: | |
| case PPC::SUBFO_rec: | |
| case PPC::SUBF_rec: { | |
| // op: RT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: RA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: RB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::ISEL: | |
| case PPC::ISEL8: { | |
| // op: RT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: RA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: RB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| // op: COND | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 6; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::ADD4TLS: | |
| case PPC::ADD8TLS: | |
| case PPC::ADD8TLS_: { | |
| // op: RT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: RA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: RB | |
| op = getTLSRegEncoding(MI, 2, Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::EFDCFS: | |
| case PPC::EFDCFSF: | |
| case PPC::EFDCFSI: | |
| case PPC::EFDCFSID: | |
| case PPC::EFDCFUF: | |
| case PPC::EFDCFUI: | |
| case PPC::EFDCFUID: | |
| case PPC::EFDCTSF: | |
| case PPC::EFDCTSI: | |
| case PPC::EFDCTSIDZ: | |
| case PPC::EFDCTSIZ: | |
| case PPC::EFDCTUF: | |
| case PPC::EFDCTUI: | |
| case PPC::EFDCTUIDZ: | |
| case PPC::EFDCTUIZ: | |
| case PPC::EFSCFD: | |
| case PPC::EFSCFSF: | |
| case PPC::EFSCFSI: | |
| case PPC::EFSCFUF: | |
| case PPC::EFSCFUI: | |
| case PPC::EFSCTSF: | |
| case PPC::EFSCTSI: | |
| case PPC::EFSCTSIZ: | |
| case PPC::EFSCTUF: | |
| case PPC::EFSCTUI: | |
| case PPC::EFSCTUIZ: | |
| case PPC::EVFSCFSF: | |
| case PPC::EVFSCFSI: | |
| case PPC::EVFSCFUF: | |
| case PPC::EVFSCFUI: | |
| case PPC::EVFSCTSF: | |
| case PPC::EVFSCTSI: | |
| case PPC::EVFSCTSIZ: | |
| case PPC::EVFSCTUF: | |
| case PPC::EVFSCTUI: | |
| case PPC::EVFSCTUIZ: | |
| case PPC::SLBMFEV: { | |
| // op: RT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: RB | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MFDCR: | |
| case PPC::MFPMR: | |
| case PPC::MFSPR: | |
| case PPC::MFSPR8: | |
| case PPC::MFTB: | |
| case PPC::MTDCR: { | |
| // op: RT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: SPR | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 16; | |
| Value |= (op & UINT64_C(992)) << 6; | |
| break; | |
| } | |
| case PPC::XSXEXPDP: | |
| case PPC::XSXSIGDP: { | |
| // op: RT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: XB | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 11; | |
| Value |= (op & UINT64_C(32)) >> 4; | |
| break; | |
| } | |
| case PPC::MTPMR: | |
| case PPC::MTSPR: | |
| case PPC::MTSPR8: { | |
| // op: RT | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: SPR | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 16; | |
| Value |= (op & UINT64_C(992)) << 6; | |
| break; | |
| } | |
| case PPC::RFEBB: { | |
| // op: S | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(1); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MFOCRF: | |
| case PPC::MFOCRF8: { | |
| // op: ST | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: FXM | |
| op = get_crbitm_encoding(MI, 1, Fixups, STI); | |
| op &= UINT64_C(255); | |
| op <<= 12; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MTOCRF: | |
| case PPC::MTOCRF8: { | |
| // op: ST | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: FXM | |
| op = get_crbitm_encoding(MI, 0, Fixups, STI); | |
| op &= UINT64_C(255); | |
| op <<= 12; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::DSS: { | |
| // op: STRM | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(3); | |
| op <<= 21; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::DST: | |
| case PPC::DST64: | |
| case PPC::DSTST: | |
| case PPC::DSTST64: | |
| case PPC::DSTSTT: | |
| case PPC::DSTSTT64: | |
| case PPC::DSTT: | |
| case PPC::DSTT64: { | |
| // op: STRM | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(3); | |
| op <<= 21; | |
| Value |= op; | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: B | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::DCBF: | |
| case PPC::DCBT: | |
| case PPC::DCBTST: { | |
| // op: TH | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: B | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::DCBTEP: | |
| case PPC::DCBTSTEP: { | |
| // op: TH | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: B | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MTVSCR: { | |
| // op: VB | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::V_SET0: | |
| case PPC::V_SET0B: | |
| case PPC::V_SET0H: { | |
| // op: VD | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(31)) << 16; | |
| Value |= (op & UINT64_C(31)) << 11; | |
| break; | |
| } | |
| case PPC::MFVSCR: | |
| case PPC::V_SETALLONES: | |
| case PPC::V_SETALLONESB: | |
| case PPC::V_SETALLONESH: { | |
| // op: VD | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::VSPLTISB: | |
| case PPC::VSPLTISH: | |
| case PPC::VSPLTISW: { | |
| // op: VD | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: IMM | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::VMUL10CUQ: | |
| case PPC::VMUL10UQ: | |
| case PPC::VSBOX: { | |
| // op: VD | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: VA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::VSHASIGMAD: | |
| case PPC::VSHASIGMAW: { | |
| // op: VD | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: VA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: ST | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(1); | |
| op <<= 15; | |
| Value |= op; | |
| // op: SIX | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(15); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::BCDCPSGN_rec: | |
| case PPC::BCDUS_rec: | |
| case PPC::BCDUTRUNC_rec: | |
| case PPC::VABSDUB: | |
| case PPC::VABSDUH: | |
| case PPC::VABSDUW: | |
| case PPC::VADDCUQ: | |
| case PPC::VADDCUW: | |
| case PPC::VADDFP: | |
| case PPC::VADDSBS: | |
| case PPC::VADDSHS: | |
| case PPC::VADDSWS: | |
| case PPC::VADDUBM: | |
| case PPC::VADDUBS: | |
| case PPC::VADDUDM: | |
| case PPC::VADDUHM: | |
| case PPC::VADDUHS: | |
| case PPC::VADDUQM: | |
| case PPC::VADDUWM: | |
| case PPC::VADDUWS: | |
| case PPC::VAND: | |
| case PPC::VANDC: | |
| case PPC::VAVGSB: | |
| case PPC::VAVGSH: | |
| case PPC::VAVGSW: | |
| case PPC::VAVGUB: | |
| case PPC::VAVGUH: | |
| case PPC::VAVGUW: | |
| case PPC::VBPERMD: | |
| case PPC::VBPERMQ: | |
| case PPC::VCFSX: | |
| case PPC::VCFUX: | |
| case PPC::VCIPHER: | |
| case PPC::VCIPHERLAST: | |
| case PPC::VCMPBFP: | |
| case PPC::VCMPBFP_rec: | |
| case PPC::VCMPEQFP: | |
| case PPC::VCMPEQFP_rec: | |
| case PPC::VCMPEQUB: | |
| case PPC::VCMPEQUB_rec: | |
| case PPC::VCMPEQUD: | |
| case PPC::VCMPEQUD_rec: | |
| case PPC::VCMPEQUH: | |
| case PPC::VCMPEQUH_rec: | |
| case PPC::VCMPEQUW: | |
| case PPC::VCMPEQUW_rec: | |
| case PPC::VCMPGEFP: | |
| case PPC::VCMPGEFP_rec: | |
| case PPC::VCMPGTFP: | |
| case PPC::VCMPGTFP_rec: | |
| case PPC::VCMPGTSB: | |
| case PPC::VCMPGTSB_rec: | |
| case PPC::VCMPGTSD: | |
| case PPC::VCMPGTSD_rec: | |
| case PPC::VCMPGTSH: | |
| case PPC::VCMPGTSH_rec: | |
| case PPC::VCMPGTSW: | |
| case PPC::VCMPGTSW_rec: | |
| case PPC::VCMPGTUB: | |
| case PPC::VCMPGTUB_rec: | |
| case PPC::VCMPGTUD: | |
| case PPC::VCMPGTUD_rec: | |
| case PPC::VCMPGTUH: | |
| case PPC::VCMPGTUH_rec: | |
| case PPC::VCMPGTUW: | |
| case PPC::VCMPGTUW_rec: | |
| case PPC::VCMPNEB: | |
| case PPC::VCMPNEB_rec: | |
| case PPC::VCMPNEH: | |
| case PPC::VCMPNEH_rec: | |
| case PPC::VCMPNEW: | |
| case PPC::VCMPNEW_rec: | |
| case PPC::VCMPNEZB: | |
| case PPC::VCMPNEZB_rec: | |
| case PPC::VCMPNEZH: | |
| case PPC::VCMPNEZH_rec: | |
| case PPC::VCMPNEZW: | |
| case PPC::VCMPNEZW_rec: | |
| case PPC::VCTSXS: | |
| case PPC::VCTUXS: | |
| case PPC::VEQV: | |
| case PPC::VEXTRACTD: | |
| case PPC::VEXTRACTUB: | |
| case PPC::VEXTRACTUH: | |
| case PPC::VEXTRACTUW: | |
| case PPC::VEXTUBLX: | |
| case PPC::VEXTUBRX: | |
| case PPC::VEXTUHLX: | |
| case PPC::VEXTUHRX: | |
| case PPC::VEXTUWLX: | |
| case PPC::VEXTUWRX: | |
| case PPC::VINSERTD: | |
| case PPC::VINSERTW: | |
| case PPC::VMAXFP: | |
| case PPC::VMAXSB: | |
| case PPC::VMAXSD: | |
| case PPC::VMAXSH: | |
| case PPC::VMAXSW: | |
| case PPC::VMAXUB: | |
| case PPC::VMAXUD: | |
| case PPC::VMAXUH: | |
| case PPC::VMAXUW: | |
| case PPC::VMINFP: | |
| case PPC::VMINSB: | |
| case PPC::VMINSD: | |
| case PPC::VMINSH: | |
| case PPC::VMINSW: | |
| case PPC::VMINUB: | |
| case PPC::VMINUD: | |
| case PPC::VMINUH: | |
| case PPC::VMINUW: | |
| case PPC::VMRGEW: | |
| case PPC::VMRGHB: | |
| case PPC::VMRGHH: | |
| case PPC::VMRGHW: | |
| case PPC::VMRGLB: | |
| case PPC::VMRGLH: | |
| case PPC::VMRGLW: | |
| case PPC::VMRGOW: | |
| case PPC::VMUL10ECUQ: | |
| case PPC::VMUL10EUQ: | |
| case PPC::VMULESB: | |
| case PPC::VMULESH: | |
| case PPC::VMULESW: | |
| case PPC::VMULEUB: | |
| case PPC::VMULEUH: | |
| case PPC::VMULEUW: | |
| case PPC::VMULOSB: | |
| case PPC::VMULOSH: | |
| case PPC::VMULOSW: | |
| case PPC::VMULOUB: | |
| case PPC::VMULOUH: | |
| case PPC::VMULOUW: | |
| case PPC::VMULUWM: | |
| case PPC::VNAND: | |
| case PPC::VNCIPHER: | |
| case PPC::VNCIPHERLAST: | |
| case PPC::VNOR: | |
| case PPC::VOR: | |
| case PPC::VORC: | |
| case PPC::VPKPX: | |
| case PPC::VPKSDSS: | |
| case PPC::VPKSDUS: | |
| case PPC::VPKSHSS: | |
| case PPC::VPKSHUS: | |
| case PPC::VPKSWSS: | |
| case PPC::VPKSWUS: | |
| case PPC::VPKUDUM: | |
| case PPC::VPKUDUS: | |
| case PPC::VPKUHUM: | |
| case PPC::VPKUHUS: | |
| case PPC::VPKUWUM: | |
| case PPC::VPKUWUS: | |
| case PPC::VPMSUMB: | |
| case PPC::VPMSUMD: | |
| case PPC::VPMSUMH: | |
| case PPC::VPMSUMW: | |
| case PPC::VRLB: | |
| case PPC::VRLD: | |
| case PPC::VRLDMI: | |
| case PPC::VRLDNM: | |
| case PPC::VRLH: | |
| case PPC::VRLW: | |
| case PPC::VRLWMI: | |
| case PPC::VRLWNM: | |
| case PPC::VSL: | |
| case PPC::VSLB: | |
| case PPC::VSLD: | |
| case PPC::VSLH: | |
| case PPC::VSLO: | |
| case PPC::VSLV: | |
| case PPC::VSLW: | |
| case PPC::VSPLTB: | |
| case PPC::VSPLTBs: | |
| case PPC::VSPLTH: | |
| case PPC::VSPLTHs: | |
| case PPC::VSPLTW: | |
| case PPC::VSR: | |
| case PPC::VSRAB: | |
| case PPC::VSRAD: | |
| case PPC::VSRAH: | |
| case PPC::VSRAW: | |
| case PPC::VSRB: | |
| case PPC::VSRD: | |
| case PPC::VSRH: | |
| case PPC::VSRO: | |
| case PPC::VSRV: | |
| case PPC::VSRW: | |
| case PPC::VSUBCUQ: | |
| case PPC::VSUBCUW: | |
| case PPC::VSUBFP: | |
| case PPC::VSUBSBS: | |
| case PPC::VSUBSHS: | |
| case PPC::VSUBSWS: | |
| case PPC::VSUBUBM: | |
| case PPC::VSUBUBS: | |
| case PPC::VSUBUDM: | |
| case PPC::VSUBUHM: | |
| case PPC::VSUBUHS: | |
| case PPC::VSUBUQM: | |
| case PPC::VSUBUWM: | |
| case PPC::VSUBUWS: | |
| case PPC::VSUM2SWS: | |
| case PPC::VSUM4SBS: | |
| case PPC::VSUM4SHS: | |
| case PPC::VSUM4UBS: | |
| case PPC::VSUMSWS: | |
| case PPC::VXOR: { | |
| // op: VD | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: VA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: VB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::BCDSR_rec: | |
| case PPC::BCDS_rec: | |
| case PPC::BCDTRUNC_rec: { | |
| // op: VD | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: VA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: VB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| // op: PS | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(1); | |
| op <<= 9; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::VSLDOI: { | |
| // op: VD | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: VA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: VB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| // op: SH | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(15); | |
| op <<= 6; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MADDHD: | |
| case PPC::MADDHDU: | |
| case PPC::MADDLD: | |
| case PPC::MADDLD8: | |
| case PPC::VADDECUQ: | |
| case PPC::VADDEUQM: | |
| case PPC::VMHADDSHS: | |
| case PPC::VMHRADDSHS: | |
| case PPC::VMLADDUHM: | |
| case PPC::VMSUMMBM: | |
| case PPC::VMSUMSHM: | |
| case PPC::VMSUMSHS: | |
| case PPC::VMSUMUBM: | |
| case PPC::VMSUMUHM: | |
| case PPC::VMSUMUHS: | |
| case PPC::VPERM: | |
| case PPC::VPERMR: | |
| case PPC::VPERMXOR: | |
| case PPC::VSEL: | |
| case PPC::VSUBECUQ: | |
| case PPC::VSUBEUQM: { | |
| // op: VD | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: VA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: VB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| // op: VC | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 6; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::VMADDFP: | |
| case PPC::VNMSUBFP: { | |
| // op: VD | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: VA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: VC | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 6; | |
| Value |= op; | |
| // op: VB | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::VINSERTB: | |
| case PPC::VINSERTH: { | |
| // op: VD | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: VA | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: VB | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::BCDCTN_rec: | |
| case PPC::BCDCTSQ_rec: | |
| case PPC::VCFSX_0: | |
| case PPC::VCFUX_0: | |
| case PPC::VCLZB: | |
| case PPC::VCLZD: | |
| case PPC::VCLZH: | |
| case PPC::VCLZW: | |
| case PPC::VCTSXS_0: | |
| case PPC::VCTUXS_0: | |
| case PPC::VEXPTEFP: | |
| case PPC::VGBBD: | |
| case PPC::VLOGEFP: | |
| case PPC::VPOPCNTB: | |
| case PPC::VPOPCNTD: | |
| case PPC::VPOPCNTH: | |
| case PPC::VPOPCNTW: | |
| case PPC::VREFP: | |
| case PPC::VRFIM: | |
| case PPC::VRFIN: | |
| case PPC::VRFIP: | |
| case PPC::VRFIZ: | |
| case PPC::VRSQRTEFP: | |
| case PPC::VUPKHPX: | |
| case PPC::VUPKHSB: | |
| case PPC::VUPKHSH: | |
| case PPC::VUPKHSW: | |
| case PPC::VUPKLPX: | |
| case PPC::VUPKLSB: | |
| case PPC::VUPKLSH: | |
| case PPC::VUPKLSW: { | |
| // op: VD | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: VB | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::BCDCFN_rec: | |
| case PPC::BCDCFSQ_rec: | |
| case PPC::BCDCFZ_rec: | |
| case PPC::BCDCTZ_rec: | |
| case PPC::BCDSETSGN_rec: { | |
| // op: VD | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: VB | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| // op: PS | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(1); | |
| op <<= 9; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::XSRQPI: | |
| case PPC::XSRQPIX: | |
| case PPC::XSRQPXP: { | |
| // op: VRT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| // op: R | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(1); | |
| op <<= 16; | |
| Value |= op; | |
| // op: VRB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| // op: idx | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(3); | |
| op <<= 9; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::XXLEQVOnes: | |
| case PPC::XXLXORdpz: | |
| case PPC::XXLXORspz: | |
| case PPC::XXLXORz: { | |
| // op: XT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(31)) << 16; | |
| Value |= (op & UINT64_C(31)) << 11; | |
| Value |= (op & UINT64_C(32)) >> 3; | |
| Value |= (op & UINT64_C(32)) >> 4; | |
| Value |= (op & UINT64_C(32)) >> 5; | |
| break; | |
| } | |
| case PPC::LXV: | |
| case PPC::STXV: { | |
| // op: XT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(32)) >> 2; | |
| // op: DS_RA | |
| op = getMemRIX16Encoding(MI, 1, Fixups, STI); | |
| op &= UINT64_C(131071); | |
| op <<= 4; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MTVRD: | |
| case PPC::MTVRWA: | |
| case PPC::MTVRWZ: | |
| case PPC::MTVSRD: | |
| case PPC::MTVSRWA: | |
| case PPC::MTVSRWS: | |
| case PPC::MTVSRWZ: { | |
| // op: XT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(32)) >> 5; | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::LXSDX: | |
| case PPC::LXSIBZX: | |
| case PPC::LXSIHZX: | |
| case PPC::LXSIWAX: | |
| case PPC::LXSIWZX: | |
| case PPC::LXSSPX: | |
| case PPC::LXVB16X: | |
| case PPC::LXVD2X: | |
| case PPC::LXVDSX: | |
| case PPC::LXVH8X: | |
| case PPC::LXVL: | |
| case PPC::LXVLL: | |
| case PPC::LXVW4X: | |
| case PPC::LXVWSX: | |
| case PPC::LXVX: | |
| case PPC::MTVSRDD: | |
| case PPC::STXSDX: | |
| case PPC::STXSIBX: | |
| case PPC::STXSIBXv: | |
| case PPC::STXSIHX: | |
| case PPC::STXSIHXv: | |
| case PPC::STXSIWX: | |
| case PPC::STXSSPX: | |
| case PPC::STXVB16X: | |
| case PPC::STXVD2X: | |
| case PPC::STXVH8X: | |
| case PPC::STXVL: | |
| case PPC::STXVLL: | |
| case PPC::STXVW4X: | |
| case PPC::STXVX: | |
| case PPC::XSIEXPDP: { | |
| // op: XT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(32)) >> 5; | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: B | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::XVTSTDCDP: | |
| case PPC::XVTSTDCSP: { | |
| // op: XT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(32)) >> 5; | |
| // op: DCMX | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 16; | |
| Value |= (op & UINT64_C(64)); | |
| Value |= (op & UINT64_C(32)) >> 3; | |
| // op: XB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 11; | |
| Value |= (op & UINT64_C(32)) >> 4; | |
| break; | |
| } | |
| case PPC::XXSPLTIB: { | |
| // op: XT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(32)) >> 5; | |
| // op: IMM8 | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(255); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::XXPERMDIs: | |
| case PPC::XXSLDWIs: { | |
| // op: XT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(32)) >> 5; | |
| // op: XA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 16; | |
| Value |= (op & UINT64_C(31)) << 11; | |
| Value |= (op & UINT64_C(32)) >> 3; | |
| Value |= (op & UINT64_C(32)) >> 4; | |
| // op: D | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(3); | |
| op <<= 8; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::XSADDDP: | |
| case PPC::XSADDSP: | |
| case PPC::XSCMPEQDP: | |
| case PPC::XSCMPGEDP: | |
| case PPC::XSCMPGTDP: | |
| case PPC::XSCPSGNDP: | |
| case PPC::XSDIVDP: | |
| case PPC::XSDIVSP: | |
| case PPC::XSMAXCDP: | |
| case PPC::XSMAXDP: | |
| case PPC::XSMAXJDP: | |
| case PPC::XSMINCDP: | |
| case PPC::XSMINDP: | |
| case PPC::XSMINJDP: | |
| case PPC::XSMULDP: | |
| case PPC::XSMULSP: | |
| case PPC::XSSUBDP: | |
| case PPC::XSSUBSP: | |
| case PPC::XVADDDP: | |
| case PPC::XVADDSP: | |
| case PPC::XVCMPEQDP: | |
| case PPC::XVCMPEQDP_rec: | |
| case PPC::XVCMPEQSP: | |
| case PPC::XVCMPEQSP_rec: | |
| case PPC::XVCMPGEDP: | |
| case PPC::XVCMPGEDP_rec: | |
| case PPC::XVCMPGESP: | |
| case PPC::XVCMPGESP_rec: | |
| case PPC::XVCMPGTDP: | |
| case PPC::XVCMPGTDP_rec: | |
| case PPC::XVCMPGTSP: | |
| case PPC::XVCMPGTSP_rec: | |
| case PPC::XVCPSGNDP: | |
| case PPC::XVCPSGNSP: | |
| case PPC::XVDIVDP: | |
| case PPC::XVDIVSP: | |
| case PPC::XVIEXPDP: | |
| case PPC::XVIEXPSP: | |
| case PPC::XVMAXDP: | |
| case PPC::XVMAXSP: | |
| case PPC::XVMINDP: | |
| case PPC::XVMINSP: | |
| case PPC::XVMULDP: | |
| case PPC::XVMULSP: | |
| case PPC::XVSUBDP: | |
| case PPC::XVSUBSP: | |
| case PPC::XXLAND: | |
| case PPC::XXLANDC: | |
| case PPC::XXLEQV: | |
| case PPC::XXLNAND: | |
| case PPC::XXLNOR: | |
| case PPC::XXLOR: | |
| case PPC::XXLORC: | |
| case PPC::XXLORf: | |
| case PPC::XXLXOR: | |
| case PPC::XXMRGHW: | |
| case PPC::XXMRGLW: | |
| case PPC::XXPERM: | |
| case PPC::XXPERMR: { | |
| // op: XT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(32)) >> 5; | |
| // op: XA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 16; | |
| Value |= (op & UINT64_C(32)) >> 3; | |
| // op: XB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 11; | |
| Value |= (op & UINT64_C(32)) >> 4; | |
| break; | |
| } | |
| case PPC::XXPERMDI: | |
| case PPC::XXSLDWI: { | |
| // op: XT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(32)) >> 5; | |
| // op: XA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 16; | |
| Value |= (op & UINT64_C(32)) >> 3; | |
| // op: XB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 11; | |
| Value |= (op & UINT64_C(32)) >> 4; | |
| // op: D | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(3); | |
| op <<= 8; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::XXSEL: { | |
| // op: XT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(32)) >> 5; | |
| // op: XA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 16; | |
| Value |= (op & UINT64_C(32)) >> 3; | |
| // op: XB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 11; | |
| Value |= (op & UINT64_C(32)) >> 4; | |
| // op: XC | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 6; | |
| Value |= (op & UINT64_C(32)) >> 2; | |
| break; | |
| } | |
| case PPC::XSMADDADP: | |
| case PPC::XSMADDASP: | |
| case PPC::XSMADDMDP: | |
| case PPC::XSMADDMSP: | |
| case PPC::XSMSUBADP: | |
| case PPC::XSMSUBASP: | |
| case PPC::XSMSUBMDP: | |
| case PPC::XSMSUBMSP: | |
| case PPC::XSNMADDADP: | |
| case PPC::XSNMADDASP: | |
| case PPC::XSNMADDMDP: | |
| case PPC::XSNMADDMSP: | |
| case PPC::XSNMSUBADP: | |
| case PPC::XSNMSUBASP: | |
| case PPC::XSNMSUBMDP: | |
| case PPC::XSNMSUBMSP: | |
| case PPC::XVMADDADP: | |
| case PPC::XVMADDASP: | |
| case PPC::XVMADDMDP: | |
| case PPC::XVMADDMSP: | |
| case PPC::XVMSUBADP: | |
| case PPC::XVMSUBASP: | |
| case PPC::XVMSUBMDP: | |
| case PPC::XVMSUBMSP: | |
| case PPC::XVNMADDADP: | |
| case PPC::XVNMADDASP: | |
| case PPC::XVNMADDMDP: | |
| case PPC::XVNMADDMSP: | |
| case PPC::XVNMSUBADP: | |
| case PPC::XVNMSUBASP: | |
| case PPC::XVNMSUBMDP: | |
| case PPC::XVNMSUBMSP: { | |
| // op: XT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(32)) >> 5; | |
| // op: XA | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 16; | |
| Value |= (op & UINT64_C(32)) >> 3; | |
| // op: XB | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 11; | |
| Value |= (op & UINT64_C(32)) >> 4; | |
| break; | |
| } | |
| case PPC::XSABSDP: | |
| case PPC::XSCVDPHP: | |
| case PPC::XSCVDPSP: | |
| case PPC::XSCVDPSPN: | |
| case PPC::XSCVDPSXDS: | |
| case PPC::XSCVDPSXDSs: | |
| case PPC::XSCVDPSXWS: | |
| case PPC::XSCVDPSXWSs: | |
| case PPC::XSCVDPUXDS: | |
| case PPC::XSCVDPUXDSs: | |
| case PPC::XSCVDPUXWS: | |
| case PPC::XSCVDPUXWSs: | |
| case PPC::XSCVHPDP: | |
| case PPC::XSCVSPDP: | |
| case PPC::XSCVSPDPN: | |
| case PPC::XSCVSXDDP: | |
| case PPC::XSCVSXDSP: | |
| case PPC::XSCVUXDDP: | |
| case PPC::XSCVUXDSP: | |
| case PPC::XSNABSDP: | |
| case PPC::XSNEGDP: | |
| case PPC::XSRDPI: | |
| case PPC::XSRDPIC: | |
| case PPC::XSRDPIM: | |
| case PPC::XSRDPIP: | |
| case PPC::XSRDPIZ: | |
| case PPC::XSREDP: | |
| case PPC::XSRESP: | |
| case PPC::XSRSP: | |
| case PPC::XSRSQRTEDP: | |
| case PPC::XSRSQRTESP: | |
| case PPC::XSSQRTDP: | |
| case PPC::XSSQRTSP: | |
| case PPC::XVABSDP: | |
| case PPC::XVABSSP: | |
| case PPC::XVCVDPSP: | |
| case PPC::XVCVDPSXDS: | |
| case PPC::XVCVDPSXWS: | |
| case PPC::XVCVDPUXDS: | |
| case PPC::XVCVDPUXWS: | |
| case PPC::XVCVHPSP: | |
| case PPC::XVCVSPDP: | |
| case PPC::XVCVSPHP: | |
| case PPC::XVCVSPSXDS: | |
| case PPC::XVCVSPSXWS: | |
| case PPC::XVCVSPUXDS: | |
| case PPC::XVCVSPUXWS: | |
| case PPC::XVCVSXDDP: | |
| case PPC::XVCVSXDSP: | |
| case PPC::XVCVSXWDP: | |
| case PPC::XVCVSXWSP: | |
| case PPC::XVCVUXDDP: | |
| case PPC::XVCVUXDSP: | |
| case PPC::XVCVUXWDP: | |
| case PPC::XVCVUXWSP: | |
| case PPC::XVNABSDP: | |
| case PPC::XVNABSSP: | |
| case PPC::XVNEGDP: | |
| case PPC::XVNEGSP: | |
| case PPC::XVRDPI: | |
| case PPC::XVRDPIC: | |
| case PPC::XVRDPIM: | |
| case PPC::XVRDPIP: | |
| case PPC::XVRDPIZ: | |
| case PPC::XVREDP: | |
| case PPC::XVRESP: | |
| case PPC::XVRSPI: | |
| case PPC::XVRSPIC: | |
| case PPC::XVRSPIM: | |
| case PPC::XVRSPIP: | |
| case PPC::XVRSPIZ: | |
| case PPC::XVRSQRTEDP: | |
| case PPC::XVRSQRTESP: | |
| case PPC::XVSQRTDP: | |
| case PPC::XVSQRTSP: | |
| case PPC::XVXEXPDP: | |
| case PPC::XVXEXPSP: | |
| case PPC::XVXSIGDP: | |
| case PPC::XVXSIGSP: | |
| case PPC::XXBRD: | |
| case PPC::XXBRH: | |
| case PPC::XXBRQ: | |
| case PPC::XXBRW: { | |
| // op: XT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(32)) >> 5; | |
| // op: XB | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 11; | |
| Value |= (op & UINT64_C(32)) >> 4; | |
| break; | |
| } | |
| case PPC::XXSPLTW: | |
| case PPC::XXSPLTWs: { | |
| // op: XT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(32)) >> 5; | |
| // op: XB | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 11; | |
| Value |= (op & UINT64_C(32)) >> 4; | |
| // op: D | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(3); | |
| op <<= 16; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::XXEXTRACTUW: { | |
| // op: XT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(32)) >> 5; | |
| // op: XB | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 11; | |
| Value |= (op & UINT64_C(32)) >> 4; | |
| // op: UIM5 | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::XXINSERTW: { | |
| // op: XT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(32)) >> 5; | |
| // op: XB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 11; | |
| Value |= (op & UINT64_C(32)) >> 4; | |
| // op: UIM5 | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::MFVRD: | |
| case PPC::MFVRWZ: | |
| case PPC::MFVSRD: | |
| case PPC::MFVSRLD: | |
| case PPC::MFVSRWZ: { | |
| // op: XT | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| Value |= (op & UINT64_C(31)) << 21; | |
| Value |= (op & UINT64_C(32)) >> 5; | |
| // op: A | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::EFDCMPEQ: | |
| case PPC::EFDCMPGT: | |
| case PPC::EFDCMPLT: | |
| case PPC::EFDTSTEQ: | |
| case PPC::EFDTSTGT: | |
| case PPC::EFDTSTLT: | |
| case PPC::EFSCMPEQ: | |
| case PPC::EFSCMPGT: | |
| case PPC::EFSCMPLT: | |
| case PPC::EFSTSTEQ: | |
| case PPC::EFSTSTGT: | |
| case PPC::EFSTSTLT: | |
| case PPC::EVCMPEQ: | |
| case PPC::EVCMPGTS: | |
| case PPC::EVCMPGTU: | |
| case PPC::EVCMPLTS: | |
| case PPC::EVCMPLTU: | |
| case PPC::EVFSCMPEQ: | |
| case PPC::EVFSCMPGT: | |
| case PPC::EVFSCMPLT: | |
| case PPC::EVFSTSTEQ: | |
| case PPC::EVFSTSTGT: | |
| case PPC::EVFSTSTLT: { | |
| // op: crD | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(7); | |
| op <<= 23; | |
| Value |= op; | |
| // op: RA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: RB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| break; | |
| } | |
| case PPC::EVSEL: { | |
| // op: crD | |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); | |
| op &= UINT64_C(7); | |
| Value |= op; | |
| // op: RA | |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 16; | |
| Value |= op; | |
| // op: RB | |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 11; | |
| Value |= op; | |
| // op: RT | |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); | |
| op &= UINT64_C(31); | |
| op <<= 21; | |
| Value |= op; | |
| break; | |
| } | |
| default: | |
| std::string msg; | |
| raw_string_ostream Msg(msg); | |
| Msg << "Not supported instr: " << MI; | |
| report_fatal_error(Msg.str()); | |
| } | |
| return Value; | |
| } | |
| #ifdef ENABLE_INSTR_PREDICATE_VERIFIER | |
| #undef ENABLE_INSTR_PREDICATE_VERIFIER | |
| #include <sstream> | |
| // Bits for subtarget features that participate in instruction matching. | |
| enum SubtargetFeatureBits : uint8_t { | |
| }; | |
| #ifndef NDEBUG | |
| static const char *SubtargetFeatureNames[] = { | |
| nullptr | |
| }; | |
| #endif // NDEBUG | |
| FeatureBitset PPCMCCodeEmitter:: | |
| computeAvailableFeatures(const FeatureBitset& FB) const { | |
| FeatureBitset Features; | |
| return Features; | |
| } | |
| #ifndef NDEBUG | |
| // Feature bitsets. | |
| enum : uint8_t { | |
| CEFBS_None, | |
| }; | |
| static constexpr FeatureBitset FeatureBitsets[] = { | |
| {}, // CEFBS_None | |
| }; | |
| #endif // NDEBUG | |
| void PPCMCCodeEmitter::verifyInstructionPredicates( | |
| const MCInst &Inst, const FeatureBitset &AvailableFeatures) const { | |
| #ifndef NDEBUG | |
| static uint8_t RequiredFeaturesRefs[] = { | |
| CEFBS_None, // PHI = 0 | |
| CEFBS_None, // INLINEASM = 1 | |
| CEFBS_None, // INLINEASM_BR = 2 | |
| CEFBS_None, // CFI_INSTRUCTION = 3 | |
| CEFBS_None, // EH_LABEL = 4 | |
| CEFBS_None, // GC_LABEL = 5 | |
| CEFBS_None, // ANNOTATION_LABEL = 6 | |
| CEFBS_None, // KILL = 7 | |
| CEFBS_None, // EXTRACT_SUBREG = 8 | |
| CEFBS_None, // INSERT_SUBREG = 9 | |
| CEFBS_None, // IMPLICIT_DEF = 10 | |
| CEFBS_None, // SUBREG_TO_REG = 11 | |
| CEFBS_None, // COPY_TO_REGCLASS = 12 | |
| CEFBS_None, // DBG_VALUE = 13 | |
| CEFBS_None, // DBG_LABEL = 14 | |
| CEFBS_None, // REG_SEQUENCE = 15 | |
| CEFBS_None, // COPY = 16 | |
| CEFBS_None, // BUNDLE = 17 | |
| CEFBS_None, // LIFETIME_START = 18 | |
| CEFBS_None, // LIFETIME_END = 19 | |
| CEFBS_None, // STACKMAP = 20 | |
| CEFBS_None, // FENTRY_CALL = 21 | |
| CEFBS_None, // PATCHPOINT = 22 | |
| CEFBS_None, // LOAD_STACK_GUARD = 23 | |
| CEFBS_None, // STATEPOINT = 24 | |
| CEFBS_None, // LOCAL_ESCAPE = 25 | |
| CEFBS_None, // FAULTING_OP = 26 | |
| CEFBS_None, // PATCHABLE_OP = 27 | |
| CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 28 | |
| CEFBS_None, // PATCHABLE_RET = 29 | |
| CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 30 | |
| CEFBS_None, // PATCHABLE_TAIL_CALL = 31 | |
| CEFBS_None, // PATCHABLE_EVENT_CALL = 32 | |
| CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 33 | |
| CEFBS_None, // ICALL_BRANCH_FUNNEL = 34 | |
| CEFBS_None, // G_ADD = 35 | |
| CEFBS_None, // G_SUB = 36 | |
| CEFBS_None, // G_MUL = 37 | |
| CEFBS_None, // G_SDIV = 38 | |
| CEFBS_None, // G_UDIV = 39 | |
| CEFBS_None, // G_SREM = 40 | |
| CEFBS_None, // G_UREM = 41 | |
| CEFBS_None, // G_AND = 42 | |
| CEFBS_None, // G_OR = 43 | |
| CEFBS_None, // G_XOR = 44 | |
| CEFBS_None, // G_IMPLICIT_DEF = 45 | |
| CEFBS_None, // G_PHI = 46 | |
| CEFBS_None, // G_FRAME_INDEX = 47 | |
| CEFBS_None, // G_GLOBAL_VALUE = 48 | |
| CEFBS_None, // G_EXTRACT = 49 | |
| CEFBS_None, // G_UNMERGE_VALUES = 50 | |
| CEFBS_None, // G_INSERT = 51 | |
| CEFBS_None, // G_MERGE_VALUES = 52 | |
| CEFBS_None, // G_BUILD_VECTOR = 53 | |
| CEFBS_None, // G_BUILD_VECTOR_TRUNC = 54 | |
| CEFBS_None, // G_CONCAT_VECTORS = 55 | |
| CEFBS_None, // G_PTRTOINT = 56 | |
| CEFBS_None, // G_INTTOPTR = 57 | |
| CEFBS_None, // G_BITCAST = 58 | |
| CEFBS_None, // G_INTRINSIC_TRUNC = 59 | |
| CEFBS_None, // G_INTRINSIC_ROUND = 60 | |
| CEFBS_None, // G_READCYCLECOUNTER = 61 | |
| CEFBS_None, // G_LOAD = 62 | |
| CEFBS_None, // G_SEXTLOAD = 63 | |
| CEFBS_None, // G_ZEXTLOAD = 64 | |
| CEFBS_None, // G_INDEXED_LOAD = 65 | |
| CEFBS_None, // G_INDEXED_SEXTLOAD = 66 | |
| CEFBS_None, // G_INDEXED_ZEXTLOAD = 67 | |
| CEFBS_None, // G_STORE = 68 | |
| CEFBS_None, // G_INDEXED_STORE = 69 | |
| CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 70 | |
| CEFBS_None, // G_ATOMIC_CMPXCHG = 71 | |
| CEFBS_None, // G_ATOMICRMW_XCHG = 72 | |
| CEFBS_None, // G_ATOMICRMW_ADD = 73 | |
| CEFBS_None, // G_ATOMICRMW_SUB = 74 | |
| CEFBS_None, // G_ATOMICRMW_AND = 75 | |
| CEFBS_None, // G_ATOMICRMW_NAND = 76 | |
| CEFBS_None, // G_ATOMICRMW_OR = 77 | |
| CEFBS_None, // G_ATOMICRMW_XOR = 78 | |
| CEFBS_None, // G_ATOMICRMW_MAX = 79 | |
| CEFBS_None, // G_ATOMICRMW_MIN = 80 | |
| CEFBS_None, // G_ATOMICRMW_UMAX = 81 | |
| CEFBS_None, // G_ATOMICRMW_UMIN = 82 | |
| CEFBS_None, // G_ATOMICRMW_FADD = 83 | |
| CEFBS_None, // G_ATOMICRMW_FSUB = 84 | |
| CEFBS_None, // G_FENCE = 85 | |
| CEFBS_None, // G_BRCOND = 86 | |
| CEFBS_None, // G_BRINDIRECT = 87 | |
| CEFBS_None, // G_INTRINSIC = 88 | |
| CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 89 | |
| CEFBS_None, // G_ANYEXT = 90 | |
| CEFBS_None, // G_TRUNC = 91 | |
| CEFBS_None, // G_CONSTANT = 92 | |
| CEFBS_None, // G_FCONSTANT = 93 | |
| CEFBS_None, // G_VASTART = 94 | |
| CEFBS_None, // G_VAARG = 95 | |
| CEFBS_None, // G_SEXT = 96 | |
| CEFBS_None, // G_SEXT_INREG = 97 | |
| CEFBS_None, // G_ZEXT = 98 | |
| CEFBS_None, // G_SHL = 99 | |
| CEFBS_None, // G_LSHR = 100 | |
| CEFBS_None, // G_ASHR = 101 | |
| CEFBS_None, // G_ICMP = 102 | |
| CEFBS_None, // G_FCMP = 103 | |
| CEFBS_None, // G_SELECT = 104 | |
| CEFBS_None, // G_UADDO = 105 | |
| CEFBS_None, // G_UADDE = 106 | |
| CEFBS_None, // G_USUBO = 107 | |
| CEFBS_None, // G_USUBE = 108 | |
| CEFBS_None, // G_SADDO = 109 | |
| CEFBS_None, // G_SADDE = 110 | |
| CEFBS_None, // G_SSUBO = 111 | |
| CEFBS_None, // G_SSUBE = 112 | |
| CEFBS_None, // G_UMULO = 113 | |
| CEFBS_None, // G_SMULO = 114 | |
| CEFBS_None, // G_UMULH = 115 | |
| CEFBS_None, // G_SMULH = 116 | |
| CEFBS_None, // G_FADD = 117 | |
| CEFBS_None, // G_FSUB = 118 | |
| CEFBS_None, // G_FMUL = 119 | |
| CEFBS_None, // G_FMA = 120 | |
| CEFBS_None, // G_FMAD = 121 | |
| CEFBS_None, // G_FDIV = 122 | |
| CEFBS_None, // G_FREM = 123 | |
| CEFBS_None, // G_FPOW = 124 | |
| CEFBS_None, // G_FEXP = 125 | |
| CEFBS_None, // G_FEXP2 = 126 | |
| CEFBS_None, // G_FLOG = 127 | |
| CEFBS_None, // G_FLOG2 = 128 | |
| CEFBS_None, // G_FLOG10 = 129 | |
| CEFBS_None, // G_FNEG = 130 | |
| CEFBS_None, // G_FPEXT = 131 | |
| CEFBS_None, // G_FPTRUNC = 132 | |
| CEFBS_None, // G_FPTOSI = 133 | |
| CEFBS_None, // G_FPTOUI = 134 | |
| CEFBS_None, // G_SITOFP = 135 | |
| CEFBS_None, // G_UITOFP = 136 | |
| CEFBS_None, // G_FABS = 137 | |
| CEFBS_None, // G_FCOPYSIGN = 138 | |
| CEFBS_None, // G_FCANONICALIZE = 139 | |
| CEFBS_None, // G_FMINNUM = 140 | |
| CEFBS_None, // G_FMAXNUM = 141 | |
| CEFBS_None, // G_FMINNUM_IEEE = 142 | |
| CEFBS_None, // G_FMAXNUM_IEEE = 143 | |
| CEFBS_None, // G_FMINIMUM = 144 | |
| CEFBS_None, // G_FMAXIMUM = 145 | |
| CEFBS_None, // G_PTR_ADD = 146 | |
| CEFBS_None, // G_PTR_MASK = 147 | |
| CEFBS_None, // G_SMIN = 148 | |
| CEFBS_None, // G_SMAX = 149 | |
| CEFBS_None, // G_UMIN = 150 | |
| CEFBS_None, // G_UMAX = 151 | |
| CEFBS_None, // G_BR = 152 | |
| CEFBS_None, // G_BRJT = 153 | |
| CEFBS_None, // G_INSERT_VECTOR_ELT = 154 | |
| CEFBS_None, // G_EXTRACT_VECTOR_ELT = 155 | |
| CEFBS_None, // G_SHUFFLE_VECTOR = 156 | |
| CEFBS_None, // G_CTTZ = 157 | |
| CEFBS_None, // G_CTTZ_ZERO_UNDEF = 158 | |
| CEFBS_None, // G_CTLZ = 159 | |
| CEFBS_None, // G_CTLZ_ZERO_UNDEF = 160 | |
| CEFBS_None, // G_CTPOP = 161 | |
| CEFBS_None, // G_BSWAP = 162 | |
| CEFBS_None, // G_BITREVERSE = 163 | |
| CEFBS_None, // G_FCEIL = 164 | |
| CEFBS_None, // G_FCOS = 165 | |
| CEFBS_None, // G_FSIN = 166 | |
| CEFBS_None, // G_FSQRT = 167 | |
| CEFBS_None, // G_FFLOOR = 168 | |
| CEFBS_None, // G_FRINT = 169 | |
| CEFBS_None, // G_FNEARBYINT = 170 | |
| CEFBS_None, // G_ADDRSPACE_CAST = 171 | |
| CEFBS_None, // G_BLOCK_ADDR = 172 | |
| CEFBS_None, // G_JUMP_TABLE = 173 | |
| CEFBS_None, // G_DYN_STACKALLOC = 174 | |
| CEFBS_None, // G_READ_REGISTER = 175 | |
| CEFBS_None, // G_WRITE_REGISTER = 176 | |
| CEFBS_None, // CFENCE8 = 177 | |
| CEFBS_None, // CLRLSLDI = 178 | |
| CEFBS_None, // CLRLSLDI_rec = 179 | |
| CEFBS_None, // CLRLSLWI = 180 | |
| CEFBS_None, // CLRLSLWI_rec = 181 | |
| CEFBS_None, // CLRRDI = 182 | |
| CEFBS_None, // CLRRDI_rec = 183 | |
| CEFBS_None, // CLRRWI = 184 | |
| CEFBS_None, // CLRRWI_rec = 185 | |
| CEFBS_None, // CP_COPY_FIRST = 186 | |
| CEFBS_None, // CP_COPYx = 187 | |
| CEFBS_None, // CP_PASTE_LAST = 188 | |
| CEFBS_None, // CP_PASTEx = 189 | |
| CEFBS_None, // DCBFL = 190 | |
| CEFBS_None, // DCBFLP = 191 | |
| CEFBS_None, // DCBFx = 192 | |
| CEFBS_None, // DCBTCT = 193 | |
| CEFBS_None, // DCBTDS = 194 | |
| CEFBS_None, // DCBTSTCT = 195 | |
| CEFBS_None, // DCBTSTDS = 196 | |
| CEFBS_None, // DCBTSTT = 197 | |
| CEFBS_None, // DCBTSTx = 198 | |
| CEFBS_None, // DCBTT = 199 | |
| CEFBS_None, // DCBTx = 200 | |
| CEFBS_None, // DFLOADf32 = 201 | |
| CEFBS_None, // DFLOADf64 = 202 | |
| CEFBS_None, // DFSTOREf32 = 203 | |
| CEFBS_None, // DFSTOREf64 = 204 | |
| CEFBS_None, // EXTLDI = 205 | |
| CEFBS_None, // EXTLDI_rec = 206 | |
| CEFBS_None, // EXTLWI = 207 | |
| CEFBS_None, // EXTLWI_rec = 208 | |
| CEFBS_None, // EXTRDI = 209 | |
| CEFBS_None, // EXTRDI_rec = 210 | |
| CEFBS_None, // EXTRWI = 211 | |
| CEFBS_None, // EXTRWI_rec = 212 | |
| CEFBS_None, // INSLWI = 213 | |
| CEFBS_None, // INSLWI_rec = 214 | |
| CEFBS_None, // INSRDI = 215 | |
| CEFBS_None, // INSRDI_rec = 216 | |
| CEFBS_None, // INSRWI = 217 | |
| CEFBS_None, // INSRWI_rec = 218 | |
| CEFBS_None, // LAx = 219 | |
| CEFBS_None, // LIWAX = 220 | |
| CEFBS_None, // LIWZX = 221 | |
| CEFBS_None, // RLWIMIbm = 222 | |
| CEFBS_None, // RLWIMIbm_rec = 223 | |
| CEFBS_None, // RLWINMbm = 224 | |
| CEFBS_None, // RLWINMbm_rec = 225 | |
| CEFBS_None, // RLWNMbm = 226 | |
| CEFBS_None, // RLWNMbm_rec = 227 | |
| CEFBS_None, // ROTRDI = 228 | |
| CEFBS_None, // ROTRDI_rec = 229 | |
| CEFBS_None, // ROTRWI = 230 | |
| CEFBS_None, // ROTRWI_rec = 231 | |
| CEFBS_None, // SLDI = 232 | |
| CEFBS_None, // SLDI_rec = 233 | |
| CEFBS_None, // SLWI = 234 | |
| CEFBS_None, // SLWI_rec = 235 | |
| CEFBS_None, // SPILLTOVSR_LD = 236 | |
| CEFBS_None, // SPILLTOVSR_LDX = 237 | |
| CEFBS_None, // SPILLTOVSR_ST = 238 | |
| CEFBS_None, // SPILLTOVSR_STX = 239 | |
| CEFBS_None, // SRDI = 240 | |
| CEFBS_None, // SRDI_rec = 241 | |
| CEFBS_None, // SRWI = 242 | |
| CEFBS_None, // SRWI_rec = 243 | |
| CEFBS_None, // STIWX = 244 | |
| CEFBS_None, // SUBI = 245 | |
| CEFBS_None, // SUBIC = 246 | |
| CEFBS_None, // SUBIC_rec = 247 | |
| CEFBS_None, // SUBIS = 248 | |
| CEFBS_None, // SUBPCIS = 249 | |
| CEFBS_None, // XFLOADf32 = 250 | |
| CEFBS_None, // XFLOADf64 = 251 | |
| CEFBS_None, // XFSTOREf32 = 252 | |
| CEFBS_None, // XFSTOREf64 = 253 | |
| CEFBS_None, // ADD4 = 254 | |
| CEFBS_None, // ADD4O = 255 | |
| CEFBS_None, // ADD4O_rec = 256 | |
| CEFBS_None, // ADD4TLS = 257 | |
| CEFBS_None, // ADD4_rec = 258 | |
| CEFBS_None, // ADD8 = 259 | |
| CEFBS_None, // ADD8O = 260 | |
| CEFBS_None, // ADD8O_rec = 261 | |
| CEFBS_None, // ADD8TLS = 262 | |
| CEFBS_None, // ADD8TLS_ = 263 | |
| CEFBS_None, // ADD8_rec = 264 | |
| CEFBS_None, // ADDC = 265 | |
| CEFBS_None, // ADDC8 = 266 | |
| CEFBS_None, // ADDC8O = 267 | |
| CEFBS_None, // ADDC8O_rec = 268 | |
| CEFBS_None, // ADDC8_rec = 269 | |
| CEFBS_None, // ADDCO = 270 | |
| CEFBS_None, // ADDCO_rec = 271 | |
| CEFBS_None, // ADDC_rec = 272 | |
| CEFBS_None, // ADDE = 273 | |
| CEFBS_None, // ADDE8 = 274 | |
| CEFBS_None, // ADDE8O = 275 | |
| CEFBS_None, // ADDE8O_rec = 276 | |
| CEFBS_None, // ADDE8_rec = 277 | |
| CEFBS_None, // ADDEO = 278 | |
| CEFBS_None, // ADDEO_rec = 279 | |
| CEFBS_None, // ADDE_rec = 280 | |
| CEFBS_None, // ADDI = 281 | |
| CEFBS_None, // ADDI8 = 282 | |
| CEFBS_None, // ADDIC = 283 | |
| CEFBS_None, // ADDIC8 = 284 | |
| CEFBS_None, // ADDIC_rec = 285 | |
| CEFBS_None, // ADDIS = 286 | |
| CEFBS_None, // ADDIS8 = 287 | |
| CEFBS_None, // ADDISdtprelHA = 288 | |
| CEFBS_None, // ADDISdtprelHA32 = 289 | |
| CEFBS_None, // ADDISgotTprelHA = 290 | |
| CEFBS_None, // ADDIStlsgdHA = 291 | |
| CEFBS_None, // ADDIStlsldHA = 292 | |
| CEFBS_None, // ADDIStocHA = 293 | |
| CEFBS_None, // ADDIStocHA8 = 294 | |
| CEFBS_None, // ADDIdtprelL = 295 | |
| CEFBS_None, // ADDIdtprelL32 = 296 | |
| CEFBS_None, // ADDItlsgdL = 297 | |
| CEFBS_None, // ADDItlsgdL32 = 298 | |
| CEFBS_None, // ADDItlsgdLADDR = 299 | |
| CEFBS_None, // ADDItlsgdLADDR32 = 300 | |
| CEFBS_None, // ADDItlsldL = 301 | |
| CEFBS_None, // ADDItlsldL32 = 302 | |
| CEFBS_None, // ADDItlsldLADDR = 303 | |
| CEFBS_None, // ADDItlsldLADDR32 = 304 | |
| CEFBS_None, // ADDItocL = 305 | |
| CEFBS_None, // ADDME = 306 | |
| CEFBS_None, // ADDME8 = 307 | |
| CEFBS_None, // ADDME8O = 308 | |
| CEFBS_None, // ADDME8O_rec = 309 | |
| CEFBS_None, // ADDME8_rec = 310 | |
| CEFBS_None, // ADDMEO = 311 | |
| CEFBS_None, // ADDMEO_rec = 312 | |
| CEFBS_None, // ADDME_rec = 313 | |
| CEFBS_None, // ADDPCIS = 314 | |
| CEFBS_None, // ADDZE = 315 | |
| CEFBS_None, // ADDZE8 = 316 | |
| CEFBS_None, // ADDZE8O = 317 | |
| CEFBS_None, // ADDZE8O_rec = 318 | |
| CEFBS_None, // ADDZE8_rec = 319 | |
| CEFBS_None, // ADDZEO = 320 | |
| CEFBS_None, // ADDZEO_rec = 321 | |
| CEFBS_None, // ADDZE_rec = 322 | |
| CEFBS_None, // ADJCALLSTACKDOWN = 323 | |
| CEFBS_None, // ADJCALLSTACKUP = 324 | |
| CEFBS_None, // AND = 325 | |
| CEFBS_None, // AND8 = 326 | |
| CEFBS_None, // AND8_rec = 327 | |
| CEFBS_None, // ANDC = 328 | |
| CEFBS_None, // ANDC8 = 329 | |
| CEFBS_None, // ANDC8_rec = 330 | |
| CEFBS_None, // ANDC_rec = 331 | |
| CEFBS_None, // ANDI8_rec = 332 | |
| CEFBS_None, // ANDIS8_rec = 333 | |
| CEFBS_None, // ANDIS_rec = 334 | |
| CEFBS_None, // ANDI_rec = 335 | |
| CEFBS_None, // ANDI_rec_1_EQ_BIT = 336 | |
| CEFBS_None, // ANDI_rec_1_EQ_BIT8 = 337 | |
| CEFBS_None, // ANDI_rec_1_GT_BIT = 338 | |
| CEFBS_None, // ANDI_rec_1_GT_BIT8 = 339 | |
| CEFBS_None, // AND_rec = 340 | |
| CEFBS_None, // ATOMIC_CMP_SWAP_I16 = 341 | |
| CEFBS_None, // ATOMIC_CMP_SWAP_I32 = 342 | |
| CEFBS_None, // ATOMIC_CMP_SWAP_I64 = 343 | |
| CEFBS_None, // ATOMIC_CMP_SWAP_I8 = 344 | |
| CEFBS_None, // ATOMIC_LOAD_ADD_I16 = 345 | |
| CEFBS_None, // ATOMIC_LOAD_ADD_I32 = 346 | |
| CEFBS_None, // ATOMIC_LOAD_ADD_I64 = 347 | |
| CEFBS_None, // ATOMIC_LOAD_ADD_I8 = 348 | |
| CEFBS_None, // ATOMIC_LOAD_AND_I16 = 349 | |
| CEFBS_None, // ATOMIC_LOAD_AND_I32 = 350 | |
| CEFBS_None, // ATOMIC_LOAD_AND_I64 = 351 | |
| CEFBS_None, // ATOMIC_LOAD_AND_I8 = 352 | |
| CEFBS_None, // ATOMIC_LOAD_MAX_I16 = 353 | |
| CEFBS_None, // ATOMIC_LOAD_MAX_I32 = 354 | |
| CEFBS_None, // ATOMIC_LOAD_MAX_I64 = 355 | |
| CEFBS_None, // ATOMIC_LOAD_MAX_I8 = 356 | |
| CEFBS_None, // ATOMIC_LOAD_MIN_I16 = 357 | |
| CEFBS_None, // ATOMIC_LOAD_MIN_I32 = 358 | |
| CEFBS_None, // ATOMIC_LOAD_MIN_I64 = 359 | |
| CEFBS_None, // ATOMIC_LOAD_MIN_I8 = 360 | |
| CEFBS_None, // ATOMIC_LOAD_NAND_I16 = 361 | |
| CEFBS_None, // ATOMIC_LOAD_NAND_I32 = 362 | |
| CEFBS_None, // ATOMIC_LOAD_NAND_I64 = 363 | |
| CEFBS_None, // ATOMIC_LOAD_NAND_I8 = 364 | |
| CEFBS_None, // ATOMIC_LOAD_OR_I16 = 365 | |
| CEFBS_None, // ATOMIC_LOAD_OR_I32 = 366 | |
| CEFBS_None, // ATOMIC_LOAD_OR_I64 = 367 | |
| CEFBS_None, // ATOMIC_LOAD_OR_I8 = 368 | |
| CEFBS_None, // ATOMIC_LOAD_SUB_I16 = 369 | |
| CEFBS_None, // ATOMIC_LOAD_SUB_I32 = 370 | |
| CEFBS_None, // ATOMIC_LOAD_SUB_I64 = 371 | |
| CEFBS_None, // ATOMIC_LOAD_SUB_I8 = 372 | |
| CEFBS_None, // ATOMIC_LOAD_UMAX_I16 = 373 | |
| CEFBS_None, // ATOMIC_LOAD_UMAX_I32 = 374 | |
| CEFBS_None, // ATOMIC_LOAD_UMAX_I64 = 375 | |
| CEFBS_None, // ATOMIC_LOAD_UMAX_I8 = 376 | |
| CEFBS_None, // ATOMIC_LOAD_UMIN_I16 = 377 | |
| CEFBS_None, // ATOMIC_LOAD_UMIN_I32 = 378 | |
| CEFBS_None, // ATOMIC_LOAD_UMIN_I64 = 379 | |
| CEFBS_None, // ATOMIC_LOAD_UMIN_I8 = 380 | |
| CEFBS_None, // ATOMIC_LOAD_XOR_I16 = 381 | |
| CEFBS_None, // ATOMIC_LOAD_XOR_I32 = 382 | |
| CEFBS_None, // ATOMIC_LOAD_XOR_I64 = 383 | |
| CEFBS_None, // ATOMIC_LOAD_XOR_I8 = 384 | |
| CEFBS_None, // ATOMIC_SWAP_I16 = 385 | |
| CEFBS_None, // ATOMIC_SWAP_I32 = 386 | |
| CEFBS_None, // ATOMIC_SWAP_I64 = 387 | |
| CEFBS_None, // ATOMIC_SWAP_I8 = 388 | |
| CEFBS_None, // ATTN = 389 | |
| CEFBS_None, // B = 390 | |
| CEFBS_None, // BA = 391 | |
| CEFBS_None, // BC = 392 | |
| CEFBS_None, // BCC = 393 | |
| CEFBS_None, // BCCA = 394 | |
| CEFBS_None, // BCCCTR = 395 | |
| CEFBS_None, // BCCCTR8 = 396 | |
| CEFBS_None, // BCCCTRL = 397 | |
| CEFBS_None, // BCCCTRL8 = 398 | |
| CEFBS_None, // BCCL = 399 | |
| CEFBS_None, // BCCLA = 400 | |
| CEFBS_None, // BCCLR = 401 | |
| CEFBS_None, // BCCLRL = 402 | |
| CEFBS_None, // BCCTR = 403 | |
| CEFBS_None, // BCCTR8 = 404 | |
| CEFBS_None, // BCCTR8n = 405 | |
| CEFBS_None, // BCCTRL = 406 | |
| CEFBS_None, // BCCTRL8 = 407 | |
| CEFBS_None, // BCCTRL8n = 408 | |
| CEFBS_None, // BCCTRLn = 409 | |
| CEFBS_None, // BCCTRn = 410 | |
| CEFBS_None, // BCDCFN_rec = 411 | |
| CEFBS_None, // BCDCFSQ_rec = 412 | |
| CEFBS_None, // BCDCFZ_rec = 413 | |
| CEFBS_None, // BCDCPSGN_rec = 414 | |
| CEFBS_None, // BCDCTN_rec = 415 | |
| CEFBS_None, // BCDCTSQ_rec = 416 | |
| CEFBS_None, // BCDCTZ_rec = 417 | |
| CEFBS_None, // BCDSETSGN_rec = 418 | |
| CEFBS_None, // BCDSR_rec = 419 | |
| CEFBS_None, // BCDS_rec = 420 | |
| CEFBS_None, // BCDTRUNC_rec = 421 | |
| CEFBS_None, // BCDUS_rec = 422 | |
| CEFBS_None, // BCDUTRUNC_rec = 423 | |
| CEFBS_None, // BCL = 424 | |
| CEFBS_None, // BCLR = 425 | |
| CEFBS_None, // BCLRL = 426 | |
| CEFBS_None, // BCLRLn = 427 | |
| CEFBS_None, // BCLRn = 428 | |
| CEFBS_None, // BCLalways = 429 | |
| CEFBS_None, // BCLn = 430 | |
| CEFBS_None, // BCTR = 431 | |
| CEFBS_None, // BCTR8 = 432 | |
| CEFBS_None, // BCTRL = 433 | |
| CEFBS_None, // BCTRL8 = 434 | |
| CEFBS_None, // BCTRL8_LDinto_toc = 435 | |
| CEFBS_None, // BCTRL_LWZinto_toc = 436 | |
| CEFBS_None, // BCn = 437 | |
| CEFBS_None, // BDNZ = 438 | |
| CEFBS_None, // BDNZ8 = 439 | |
| CEFBS_None, // BDNZA = 440 | |
| CEFBS_None, // BDNZAm = 441 | |
| CEFBS_None, // BDNZAp = 442 | |
| CEFBS_None, // BDNZL = 443 | |
| CEFBS_None, // BDNZLA = 444 | |
| CEFBS_None, // BDNZLAm = 445 | |
| CEFBS_None, // BDNZLAp = 446 | |
| CEFBS_None, // BDNZLR = 447 | |
| CEFBS_None, // BDNZLR8 = 448 | |
| CEFBS_None, // BDNZLRL = 449 | |
| CEFBS_None, // BDNZLRLm = 450 | |
| CEFBS_None, // BDNZLRLp = 451 | |
| CEFBS_None, // BDNZLRm = 452 | |
| CEFBS_None, // BDNZLRp = 453 | |
| CEFBS_None, // BDNZLm = 454 | |
| CEFBS_None, // BDNZLp = 455 | |
| CEFBS_None, // BDNZm = 456 | |
| CEFBS_None, // BDNZp = 457 | |
| CEFBS_None, // BDZ = 458 | |
| CEFBS_None, // BDZ8 = 459 | |
| CEFBS_None, // BDZA = 460 | |
| CEFBS_None, // BDZAm = 461 | |
| CEFBS_None, // BDZAp = 462 | |
| CEFBS_None, // BDZL = 463 | |
| CEFBS_None, // BDZLA = 464 | |
| CEFBS_None, // BDZLAm = 465 | |
| CEFBS_None, // BDZLAp = 466 | |
| CEFBS_None, // BDZLR = 467 | |
| CEFBS_None, // BDZLR8 = 468 | |
| CEFBS_None, // BDZLRL = 469 | |
| CEFBS_None, // BDZLRLm = 470 | |
| CEFBS_None, // BDZLRLp = 471 | |
| CEFBS_None, // BDZLRm = 472 | |
| CEFBS_None, // BDZLRp = 473 | |
| CEFBS_None, // BDZLm = 474 | |
| CEFBS_None, // BDZLp = 475 | |
| CEFBS_None, // BDZm = 476 | |
| CEFBS_None, // BDZp = 477 | |
| CEFBS_None, // BL = 478 | |
| CEFBS_None, // BL8 = 479 | |
| CEFBS_None, // BL8_NOP = 480 | |
| CEFBS_None, // BL8_NOP_TLS = 481 | |
| CEFBS_None, // BL8_TLS = 482 | |
| CEFBS_None, // BL8_TLS_ = 483 | |
| CEFBS_None, // BLA = 484 | |
| CEFBS_None, // BLA8 = 485 | |
| CEFBS_None, // BLA8_NOP = 486 | |
| CEFBS_None, // BLR = 487 | |
| CEFBS_None, // BLR8 = 488 | |
| CEFBS_None, // BLRL = 489 | |
| CEFBS_None, // BL_NOP = 490 | |
| CEFBS_None, // BL_TLS = 491 | |
| CEFBS_None, // BPERMD = 492 | |
| CEFBS_None, // BRINC = 493 | |
| CEFBS_None, // CLRBHRB = 494 | |
| CEFBS_None, // CMPB = 495 | |
| CEFBS_None, // CMPB8 = 496 | |
| CEFBS_None, // CMPD = 497 | |
| CEFBS_None, // CMPDI = 498 | |
| CEFBS_None, // CMPEQB = 499 | |
| CEFBS_None, // CMPLD = 500 | |
| CEFBS_None, // CMPLDI = 501 | |
| CEFBS_None, // CMPLW = 502 | |
| CEFBS_None, // CMPLWI = 503 | |
| CEFBS_None, // CMPRB = 504 | |
| CEFBS_None, // CMPRB8 = 505 | |
| CEFBS_None, // CMPW = 506 | |
| CEFBS_None, // CMPWI = 507 | |
| CEFBS_None, // CNTLZD = 508 | |
| CEFBS_None, // CNTLZD_rec = 509 | |
| CEFBS_None, // CNTLZW = 510 | |
| CEFBS_None, // CNTLZW8 = 511 | |
| CEFBS_None, // CNTLZW8_rec = 512 | |
| CEFBS_None, // CNTLZW_rec = 513 | |
| CEFBS_None, // CNTTZD = 514 | |
| CEFBS_None, // CNTTZD_rec = 515 | |
| CEFBS_None, // CNTTZW = 516 | |
| CEFBS_None, // CNTTZW8 = 517 | |
| CEFBS_None, // CNTTZW8_rec = 518 | |
| CEFBS_None, // CNTTZW_rec = 519 | |
| CEFBS_None, // CP_ABORT = 520 | |
| CEFBS_None, // CP_COPY = 521 | |
| CEFBS_None, // CP_COPY8 = 522 | |
| CEFBS_None, // CP_PASTE = 523 | |
| CEFBS_None, // CP_PASTE8 = 524 | |
| CEFBS_None, // CP_PASTE8_rec = 525 | |
| CEFBS_None, // CP_PASTE_rec = 526 | |
| CEFBS_None, // CR6SET = 527 | |
| CEFBS_None, // CR6UNSET = 528 | |
| CEFBS_None, // CRAND = 529 | |
| CEFBS_None, // CRANDC = 530 | |
| CEFBS_None, // CREQV = 531 | |
| CEFBS_None, // CRNAND = 532 | |
| CEFBS_None, // CRNOR = 533 | |
| CEFBS_None, // CROR = 534 | |
| CEFBS_None, // CRORC = 535 | |
| CEFBS_None, // CRSET = 536 | |
| CEFBS_None, // CRUNSET = 537 | |
| CEFBS_None, // CRXOR = 538 | |
| CEFBS_None, // CTRL_DEP = 539 | |
| CEFBS_None, // DARN = 540 | |
| CEFBS_None, // DCBA = 541 | |
| CEFBS_None, // DCBF = 542 | |
| CEFBS_None, // DCBFEP = 543 | |
| CEFBS_None, // DCBI = 544 | |
| CEFBS_None, // DCBST = 545 | |
| CEFBS_None, // DCBSTEP = 546 | |
| CEFBS_None, // DCBT = 547 | |
| CEFBS_None, // DCBTEP = 548 | |
| CEFBS_None, // DCBTST = 549 | |
| CEFBS_None, // DCBTSTEP = 550 | |
| CEFBS_None, // DCBZ = 551 | |
| CEFBS_None, // DCBZEP = 552 | |
| CEFBS_None, // DCBZL = 553 | |
| CEFBS_None, // DCBZLEP = 554 | |
| CEFBS_None, // DCCCI = 555 | |
| CEFBS_None, // DIVD = 556 | |
| CEFBS_None, // DIVDE = 557 | |
| CEFBS_None, // DIVDEO = 558 | |
| CEFBS_None, // DIVDEO_rec = 559 | |
| CEFBS_None, // DIVDEU = 560 | |
| CEFBS_None, // DIVDEUO = 561 | |
| CEFBS_None, // DIVDEUO_rec = 562 | |
| CEFBS_None, // DIVDEU_rec = 563 | |
| CEFBS_None, // DIVDE_rec = 564 | |
| CEFBS_None, // DIVDO = 565 | |
| CEFBS_None, // DIVDO_rec = 566 | |
| CEFBS_None, // DIVDU = 567 | |
| CEFBS_None, // DIVDUO = 568 | |
| CEFBS_None, // DIVDUO_rec = 569 | |
| CEFBS_None, // DIVDU_rec = 570 | |
| CEFBS_None, // DIVD_rec = 571 | |
| CEFBS_None, // DIVW = 572 | |
| CEFBS_None, // DIVWE = 573 | |
| CEFBS_None, // DIVWEO = 574 | |
| CEFBS_None, // DIVWEO_rec = 575 | |
| CEFBS_None, // DIVWEU = 576 | |
| CEFBS_None, // DIVWEUO = 577 | |
| CEFBS_None, // DIVWEUO_rec = 578 | |
| CEFBS_None, // DIVWEU_rec = 579 | |
| CEFBS_None, // DIVWE_rec = 580 | |
| CEFBS_None, // DIVWO = 581 | |
| CEFBS_None, // DIVWO_rec = 582 | |
| CEFBS_None, // DIVWU = 583 | |
| CEFBS_None, // DIVWUO = 584 | |
| CEFBS_None, // DIVWUO_rec = 585 | |
| CEFBS_None, // DIVWU_rec = 586 | |
| CEFBS_None, // DIVW_rec = 587 | |
| CEFBS_None, // DSS = 588 | |
| CEFBS_None, // DSSALL = 589 | |
| CEFBS_None, // DST = 590 | |
| CEFBS_None, // DST64 = 591 | |
| CEFBS_None, // DSTST = 592 | |
| CEFBS_None, // DSTST64 = 593 | |
| CEFBS_None, // DSTSTT = 594 | |
| CEFBS_None, // DSTSTT64 = 595 | |
| CEFBS_None, // DSTT = 596 | |
| CEFBS_None, // DSTT64 = 597 | |
| CEFBS_None, // DYNALLOC = 598 | |
| CEFBS_None, // DYNALLOC8 = 599 | |
| CEFBS_None, // DYNAREAOFFSET = 600 | |
| CEFBS_None, // DYNAREAOFFSET8 = 601 | |
| CEFBS_None, // EFDABS = 602 | |
| CEFBS_None, // EFDADD = 603 | |
| CEFBS_None, // EFDCFS = 604 | |
| CEFBS_None, // EFDCFSF = 605 | |
| CEFBS_None, // EFDCFSI = 606 | |
| CEFBS_None, // EFDCFSID = 607 | |
| CEFBS_None, // EFDCFUF = 608 | |
| CEFBS_None, // EFDCFUI = 609 | |
| CEFBS_None, // EFDCFUID = 610 | |
| CEFBS_None, // EFDCMPEQ = 611 | |
| CEFBS_None, // EFDCMPGT = 612 | |
| CEFBS_None, // EFDCMPLT = 613 | |
| CEFBS_None, // EFDCTSF = 614 | |
| CEFBS_None, // EFDCTSI = 615 | |
| CEFBS_None, // EFDCTSIDZ = 616 | |
| CEFBS_None, // EFDCTSIZ = 617 | |
| CEFBS_None, // EFDCTUF = 618 | |
| CEFBS_None, // EFDCTUI = 619 | |
| CEFBS_None, // EFDCTUIDZ = 620 | |
| CEFBS_None, // EFDCTUIZ = 621 | |
| CEFBS_None, // EFDDIV = 622 | |
| CEFBS_None, // EFDMUL = 623 | |
| CEFBS_None, // EFDNABS = 624 | |
| CEFBS_None, // EFDNEG = 625 | |
| CEFBS_None, // EFDSUB = 626 | |
| CEFBS_None, // EFDTSTEQ = 627 | |
| CEFBS_None, // EFDTSTGT = 628 | |
| CEFBS_None, // EFDTSTLT = 629 | |
| CEFBS_None, // EFSABS = 630 | |
| CEFBS_None, // EFSADD = 631 | |
| CEFBS_None, // EFSCFD = 632 | |
| CEFBS_None, // EFSCFSF = 633 | |
| CEFBS_None, // EFSCFSI = 634 | |
| CEFBS_None, // EFSCFUF = 635 | |
| CEFBS_None, // EFSCFUI = 636 | |
| CEFBS_None, // EFSCMPEQ = 637 | |
| CEFBS_None, // EFSCMPGT = 638 | |
| CEFBS_None, // EFSCMPLT = 639 | |
| CEFBS_None, // EFSCTSF = 640 | |
| CEFBS_None, // EFSCTSI = 641 | |
| CEFBS_None, // EFSCTSIZ = 642 | |
| CEFBS_None, // EFSCTUF = 643 | |
| CEFBS_None, // EFSCTUI = 644 | |
| CEFBS_None, // EFSCTUIZ = 645 | |
| CEFBS_None, // EFSDIV = 646 | |
| CEFBS_None, // EFSMUL = 647 | |
| CEFBS_None, // EFSNABS = 648 | |
| CEFBS_None, // EFSNEG = 649 | |
| CEFBS_None, // EFSSUB = 650 | |
| CEFBS_None, // EFSTSTEQ = 651 | |
| CEFBS_None, // EFSTSTGT = 652 | |
| CEFBS_None, // EFSTSTLT = 653 | |
| CEFBS_None, // EH_SjLj_LongJmp32 = 654 | |
| CEFBS_None, // EH_SjLj_LongJmp64 = 655 | |
| CEFBS_None, // EH_SjLj_SetJmp32 = 656 | |
| CEFBS_None, // EH_SjLj_SetJmp64 = 657 | |
| CEFBS_None, // EH_SjLj_Setup = 658 | |
| CEFBS_None, // EQV = 659 | |
| CEFBS_None, // EQV8 = 660 | |
| CEFBS_None, // EQV8_rec = 661 | |
| CEFBS_None, // EQV_rec = 662 | |
| CEFBS_None, // EVABS = 663 | |
| CEFBS_None, // EVADDIW = 664 | |
| CEFBS_None, // EVADDSMIAAW = 665 | |
| CEFBS_None, // EVADDSSIAAW = 666 | |
| CEFBS_None, // EVADDUMIAAW = 667 | |
| CEFBS_None, // EVADDUSIAAW = 668 | |
| CEFBS_None, // EVADDW = 669 | |
| CEFBS_None, // EVAND = 670 | |
| CEFBS_None, // EVANDC = 671 | |
| CEFBS_None, // EVCMPEQ = 672 | |
| CEFBS_None, // EVCMPGTS = 673 | |
| CEFBS_None, // EVCMPGTU = 674 | |
| CEFBS_None, // EVCMPLTS = 675 | |
| CEFBS_None, // EVCMPLTU = 676 | |
| CEFBS_None, // EVCNTLSW = 677 | |
| CEFBS_None, // EVCNTLZW = 678 | |
| CEFBS_None, // EVDIVWS = 679 | |
| CEFBS_None, // EVDIVWU = 680 | |
| CEFBS_None, // EVEQV = 681 | |
| CEFBS_None, // EVEXTSB = 682 | |
| CEFBS_None, // EVEXTSH = 683 | |
| CEFBS_None, // EVFSABS = 684 | |
| CEFBS_None, // EVFSADD = 685 | |
| CEFBS_None, // EVFSCFSF = 686 | |
| CEFBS_None, // EVFSCFSI = 687 | |
| CEFBS_None, // EVFSCFUF = 688 | |
| CEFBS_None, // EVFSCFUI = 689 | |
| CEFBS_None, // EVFSCMPEQ = 690 | |
| CEFBS_None, // EVFSCMPGT = 691 | |
| CEFBS_None, // EVFSCMPLT = 692 | |
| CEFBS_None, // EVFSCTSF = 693 | |
| CEFBS_None, // EVFSCTSI = 694 | |
| CEFBS_None, // EVFSCTSIZ = 695 | |
| CEFBS_None, // EVFSCTUF = 696 | |
| CEFBS_None, // EVFSCTUI = 697 | |
| CEFBS_None, // EVFSCTUIZ = 698 | |
| CEFBS_None, // EVFSDIV = 699 | |
| CEFBS_None, // EVFSMUL = 700 | |
| CEFBS_None, // EVFSNABS = 701 | |
| CEFBS_None, // EVFSNEG = 702 | |
| CEFBS_None, // EVFSSUB = 703 | |
| CEFBS_None, // EVFSTSTEQ = 704 | |
| CEFBS_None, // EVFSTSTGT = 705 | |
| CEFBS_None, // EVFSTSTLT = 706 | |
| CEFBS_None, // EVLDD = 707 | |
| CEFBS_None, // EVLDDX = 708 | |
| CEFBS_None, // EVLDH = 709 | |
| CEFBS_None, // EVLDHX = 710 | |
| CEFBS_None, // EVLDW = 711 | |
| CEFBS_None, // EVLDWX = 712 | |
| CEFBS_None, // EVLHHESPLAT = 713 | |
| CEFBS_None, // EVLHHESPLATX = 714 | |
| CEFBS_None, // EVLHHOSSPLAT = 715 | |
| CEFBS_None, // EVLHHOSSPLATX = 716 | |
| CEFBS_None, // EVLHHOUSPLAT = 717 | |
| CEFBS_None, // EVLHHOUSPLATX = 718 | |
| CEFBS_None, // EVLWHE = 719 | |
| CEFBS_None, // EVLWHEX = 720 | |
| CEFBS_None, // EVLWHOS = 721 | |
| CEFBS_None, // EVLWHOSX = 722 | |
| CEFBS_None, // EVLWHOU = 723 | |
| CEFBS_None, // EVLWHOUX = 724 | |
| CEFBS_None, // EVLWHSPLAT = 725 | |
| CEFBS_None, // EVLWHSPLATX = 726 | |
| CEFBS_None, // EVLWWSPLAT = 727 | |
| CEFBS_None, // EVLWWSPLATX = 728 | |
| CEFBS_None, // EVMERGEHI = 729 | |
| CEFBS_None, // EVMERGEHILO = 730 | |
| CEFBS_None, // EVMERGELO = 731 | |
| CEFBS_None, // EVMERGELOHI = 732 | |
| CEFBS_None, // EVMHEGSMFAA = 733 | |
| CEFBS_None, // EVMHEGSMFAN = 734 | |
| CEFBS_None, // EVMHEGSMIAA = 735 | |
| CEFBS_None, // EVMHEGSMIAN = 736 | |
| CEFBS_None, // EVMHEGUMIAA = 737 | |
| CEFBS_None, // EVMHEGUMIAN = 738 | |
| CEFBS_None, // EVMHESMF = 739 | |
| CEFBS_None, // EVMHESMFA = 740 | |
| CEFBS_None, // EVMHESMFAAW = 741 | |
| CEFBS_None, // EVMHESMFANW = 742 | |
| CEFBS_None, // EVMHESMI = 743 | |
| CEFBS_None, // EVMHESMIA = 744 | |
| CEFBS_None, // EVMHESMIAAW = 745 | |
| CEFBS_None, // EVMHESMIANW = 746 | |
| CEFBS_None, // EVMHESSF = 747 | |
| CEFBS_None, // EVMHESSFA = 748 | |
| CEFBS_None, // EVMHESSFAAW = 749 | |
| CEFBS_None, // EVMHESSFANW = 750 | |
| CEFBS_None, // EVMHESSIAAW = 751 | |
| CEFBS_None, // EVMHESSIANW = 752 | |
| CEFBS_None, // EVMHEUMI = 753 | |
| CEFBS_None, // EVMHEUMIA = 754 | |
| CEFBS_None, // EVMHEUMIAAW = 755 | |
| CEFBS_None, // EVMHEUMIANW = 756 | |
| CEFBS_None, // EVMHEUSIAAW = 757 | |
| CEFBS_None, // EVMHEUSIANW = 758 | |
| CEFBS_None, // EVMHOGSMFAA = 759 | |
| CEFBS_None, // EVMHOGSMFAN = 760 | |
| CEFBS_None, // EVMHOGSMIAA = 761 | |
| CEFBS_None, // EVMHOGSMIAN = 762 | |
| CEFBS_None, // EVMHOGUMIAA = 763 | |
| CEFBS_None, // EVMHOGUMIAN = 764 | |
| CEFBS_None, // EVMHOSMF = 765 | |
| CEFBS_None, // EVMHOSMFA = 766 | |
| CEFBS_None, // EVMHOSMFAAW = 767 | |
| CEFBS_None, // EVMHOSMFANW = 768 | |
| CEFBS_None, // EVMHOSMI = 769 | |
| CEFBS_None, // EVMHOSMIA = 770 | |
| CEFBS_None, // EVMHOSMIAAW = 771 | |
| CEFBS_None, // EVMHOSMIANW = 772 | |
| CEFBS_None, // EVMHOSSF = 773 | |
| CEFBS_None, // EVMHOSSFA = 774 | |
| CEFBS_None, // EVMHOSSFAAW = 775 | |
| CEFBS_None, // EVMHOSSFANW = 776 | |
| CEFBS_None, // EVMHOSSIAAW = 777 | |
| CEFBS_None, // EVMHOSSIANW = 778 | |
| CEFBS_None, // EVMHOUMI = 779 | |
| CEFBS_None, // EVMHOUMIA = 780 | |
| CEFBS_None, // EVMHOUMIAAW = 781 | |
| CEFBS_None, // EVMHOUMIANW = 782 | |
| CEFBS_None, // EVMHOUSIAAW = 783 | |
| CEFBS_None, // EVMHOUSIANW = 784 | |
| CEFBS_None, // EVMRA = 785 | |
| CEFBS_None, // EVMWHSMF = 786 | |
| CEFBS_None, // EVMWHSMFA = 787 | |
| CEFBS_None, // EVMWHSMI = 788 | |
| CEFBS_None, // EVMWHSMIA = 789 | |
| CEFBS_None, // EVMWHSSF = 790 | |
| CEFBS_None, // EVMWHSSFA = 791 | |
| CEFBS_None, // EVMWHUMI = 792 | |
| CEFBS_None, // EVMWHUMIA = 793 | |
| CEFBS_None, // EVMWLSMIAAW = 794 | |
| CEFBS_None, // EVMWLSMIANW = 795 | |
| CEFBS_None, // EVMWLSSIAAW = 796 | |
| CEFBS_None, // EVMWLSSIANW = 797 | |
| CEFBS_None, // EVMWLUMI = 798 | |
| CEFBS_None, // EVMWLUMIA = 799 | |
| CEFBS_None, // EVMWLUMIAAW = 800 | |
| CEFBS_None, // EVMWLUMIANW = 801 | |
| CEFBS_None, // EVMWLUSIAAW = 802 | |
| CEFBS_None, // EVMWLUSIANW = 803 | |
| CEFBS_None, // EVMWSMF = 804 | |
| CEFBS_None, // EVMWSMFA = 805 | |
| CEFBS_None, // EVMWSMFAA = 806 | |
| CEFBS_None, // EVMWSMFAN = 807 | |
| CEFBS_None, // EVMWSMI = 808 | |
| CEFBS_None, // EVMWSMIA = 809 | |
| CEFBS_None, // EVMWSMIAA = 810 | |
| CEFBS_None, // EVMWSMIAN = 811 | |
| CEFBS_None, // EVMWSSF = 812 | |
| CEFBS_None, // EVMWSSFA = 813 | |
| CEFBS_None, // EVMWSSFAA = 814 | |
| CEFBS_None, // EVMWSSFAN = 815 | |
| CEFBS_None, // EVMWUMI = 816 | |
| CEFBS_None, // EVMWUMIA = 817 | |
| CEFBS_None, // EVMWUMIAA = 818 | |
| CEFBS_None, // EVMWUMIAN = 819 | |
| CEFBS_None, // EVNAND = 820 | |
| CEFBS_None, // EVNEG = 821 | |
| CEFBS_None, // EVNOR = 822 | |
| CEFBS_None, // EVOR = 823 | |
| CEFBS_None, // EVORC = 824 | |
| CEFBS_None, // EVRLW = 825 | |
| CEFBS_None, // EVRLWI = 826 | |
| CEFBS_None, // EVRNDW = 827 | |
| CEFBS_None, // EVSEL = 828 | |
| CEFBS_None, // EVSLW = 829 | |
| CEFBS_None, // EVSLWI = 830 | |
| CEFBS_None, // EVSPLATFI = 831 | |
| CEFBS_None, // EVSPLATI = 832 | |
| CEFBS_None, // EVSRWIS = 833 | |
| CEFBS_None, // EVSRWIU = 834 | |
| CEFBS_None, // EVSRWS = 835 | |
| CEFBS_None, // EVSRWU = 836 | |
| CEFBS_None, // EVSTDD = 837 | |
| CEFBS_None, // EVSTDDX = 838 | |
| CEFBS_None, // EVSTDH = 839 | |
| CEFBS_None, // EVSTDHX = 840 | |
| CEFBS_None, // EVSTDW = 841 | |
| CEFBS_None, // EVSTDWX = 842 | |
| CEFBS_None, // EVSTWHE = 843 | |
| CEFBS_None, // EVSTWHEX = 844 | |
| CEFBS_None, // EVSTWHO = 845 | |
| CEFBS_None, // EVSTWHOX = 846 | |
| CEFBS_None, // EVSTWWE = 847 | |
| CEFBS_None, // EVSTWWEX = 848 | |
| CEFBS_None, // EVSTWWO = 849 | |
| CEFBS_None, // EVSTWWOX = 850 | |
| CEFBS_None, // EVSUBFSMIAAW = 851 | |
| CEFBS_None, // EVSUBFSSIAAW = 852 | |
| CEFBS_None, // EVSUBFUMIAAW = 853 | |
| CEFBS_None, // EVSUBFUSIAAW = 854 | |
| CEFBS_None, // EVSUBFW = 855 | |
| CEFBS_None, // EVSUBIFW = 856 | |
| CEFBS_None, // EVXOR = 857 | |
| CEFBS_None, // EXTSB = 858 | |
| CEFBS_None, // EXTSB8 = 859 | |
| CEFBS_None, // EXTSB8_32_64 = 860 | |
| CEFBS_None, // EXTSB8_rec = 861 | |
| CEFBS_None, // EXTSB_rec = 862 | |
| CEFBS_None, // EXTSH = 863 | |
| CEFBS_None, // EXTSH8 = 864 | |
| CEFBS_None, // EXTSH8_32_64 = 865 | |
| CEFBS_None, // EXTSH8_rec = 866 | |
| CEFBS_None, // EXTSH_rec = 867 | |
| CEFBS_None, // EXTSW = 868 | |
| CEFBS_None, // EXTSWSLI = 869 | |
| CEFBS_None, // EXTSWSLI_32_64 = 870 | |
| CEFBS_None, // EXTSWSLI_32_64_rec = 871 | |
| CEFBS_None, // EXTSWSLI_rec = 872 | |
| CEFBS_None, // EXTSW_32 = 873 | |
| CEFBS_None, // EXTSW_32_64 = 874 | |
| CEFBS_None, // EXTSW_32_64_rec = 875 | |
| CEFBS_None, // EXTSW_rec = 876 | |
| CEFBS_None, // EnforceIEIO = 877 | |
| CEFBS_None, // FABSD = 878 | |
| CEFBS_None, // FABSD_rec = 879 | |
| CEFBS_None, // FABSS = 880 | |
| CEFBS_None, // FABSS_rec = 881 | |
| CEFBS_None, // FADD = 882 | |
| CEFBS_None, // FADDS = 883 | |
| CEFBS_None, // FADDS_rec = 884 | |
| CEFBS_None, // FADD_rec = 885 | |
| CEFBS_None, // FADDrtz = 886 | |
| CEFBS_None, // FCFID = 887 | |
| CEFBS_None, // FCFIDS = 888 | |
| CEFBS_None, // FCFIDS_rec = 889 | |
| CEFBS_None, // FCFIDU = 890 | |
| CEFBS_None, // FCFIDUS = 891 | |
| CEFBS_None, // FCFIDUS_rec = 892 | |
| CEFBS_None, // FCFIDU_rec = 893 | |
| CEFBS_None, // FCFID_rec = 894 | |
| CEFBS_None, // FCMPUD = 895 | |
| CEFBS_None, // FCMPUS = 896 | |
| CEFBS_None, // FCPSGND = 897 | |
| CEFBS_None, // FCPSGND_rec = 898 | |
| CEFBS_None, // FCPSGNS = 899 | |
| CEFBS_None, // FCPSGNS_rec = 900 | |
| CEFBS_None, // FCTID = 901 | |
| CEFBS_None, // FCTIDU = 902 | |
| CEFBS_None, // FCTIDUZ = 903 | |
| CEFBS_None, // FCTIDUZ_rec = 904 | |
| CEFBS_None, // FCTIDU_rec = 905 | |
| CEFBS_None, // FCTIDZ = 906 | |
| CEFBS_None, // FCTIDZ_rec = 907 | |
| CEFBS_None, // FCTID_rec = 908 | |
| CEFBS_None, // FCTIW = 909 | |
| CEFBS_None, // FCTIWU = 910 | |
| CEFBS_None, // FCTIWUZ = 911 | |
| CEFBS_None, // FCTIWUZ_rec = 912 | |
| CEFBS_None, // FCTIWU_rec = 913 | |
| CEFBS_None, // FCTIWZ = 914 | |
| CEFBS_None, // FCTIWZ_rec = 915 | |
| CEFBS_None, // FCTIW_rec = 916 | |
| CEFBS_None, // FDIV = 917 | |
| CEFBS_None, // FDIVS = 918 | |
| CEFBS_None, // FDIVS_rec = 919 | |
| CEFBS_None, // FDIV_rec = 920 | |
| CEFBS_None, // FMADD = 921 | |
| CEFBS_None, // FMADDS = 922 | |
| CEFBS_None, // FMADDS_rec = 923 | |
| CEFBS_None, // FMADD_rec = 924 | |
| CEFBS_None, // FMR = 925 | |
| CEFBS_None, // FMR_rec = 926 | |
| CEFBS_None, // FMSUB = 927 | |
| CEFBS_None, // FMSUBS = 928 | |
| CEFBS_None, // FMSUBS_rec = 929 | |
| CEFBS_None, // FMSUB_rec = 930 | |
| CEFBS_None, // FMUL = 931 | |
| CEFBS_None, // FMULS = 932 | |
| CEFBS_None, // FMULS_rec = 933 | |
| CEFBS_None, // FMUL_rec = 934 | |
| CEFBS_None, // FNABSD = 935 | |
| CEFBS_None, // FNABSD_rec = 936 | |
| CEFBS_None, // FNABSS = 937 | |
| CEFBS_None, // FNABSS_rec = 938 | |
| CEFBS_None, // FNEGD = 939 | |
| CEFBS_None, // FNEGD_rec = 940 | |
| CEFBS_None, // FNEGS = 941 | |
| CEFBS_None, // FNEGS_rec = 942 | |
| CEFBS_None, // FNMADD = 943 | |
| CEFBS_None, // FNMADDS = 944 | |
| CEFBS_None, // FNMADDS_rec = 945 | |
| CEFBS_None, // FNMADD_rec = 946 | |
| CEFBS_None, // FNMSUB = 947 | |
| CEFBS_None, // FNMSUBS = 948 | |
| CEFBS_None, // FNMSUBS_rec = 949 | |
| CEFBS_None, // FNMSUB_rec = 950 | |
| CEFBS_None, // FRE = 951 | |
| CEFBS_None, // FRES = 952 | |
| CEFBS_None, // FRES_rec = 953 | |
| CEFBS_None, // FRE_rec = 954 | |
| CEFBS_None, // FRIMD = 955 | |
| CEFBS_None, // FRIMD_rec = 956 | |
| CEFBS_None, // FRIMS = 957 | |
| CEFBS_None, // FRIMS_rec = 958 | |
| CEFBS_None, // FRIND = 959 | |
| CEFBS_None, // FRIND_rec = 960 | |
| CEFBS_None, // FRINS = 961 | |
| CEFBS_None, // FRINS_rec = 962 | |
| CEFBS_None, // FRIPD = 963 | |
| CEFBS_None, // FRIPD_rec = 964 | |
| CEFBS_None, // FRIPS = 965 | |
| CEFBS_None, // FRIPS_rec = 966 | |
| CEFBS_None, // FRIZD = 967 | |
| CEFBS_None, // FRIZD_rec = 968 | |
| CEFBS_None, // FRIZS = 969 | |
| CEFBS_None, // FRIZS_rec = 970 | |
| CEFBS_None, // FRSP = 971 | |
| CEFBS_None, // FRSP_rec = 972 | |
| CEFBS_None, // FRSQRTE = 973 | |
| CEFBS_None, // FRSQRTES = 974 | |
| CEFBS_None, // FRSQRTES_rec = 975 | |
| CEFBS_None, // FRSQRTE_rec = 976 | |
| CEFBS_None, // FSELD = 977 | |
| CEFBS_None, // FSELD_rec = 978 | |
| CEFBS_None, // FSELS = 979 | |
| CEFBS_None, // FSELS_rec = 980 | |
| CEFBS_None, // FSQRT = 981 | |
| CEFBS_None, // FSQRTS = 982 | |
| CEFBS_None, // FSQRTS_rec = 983 | |
| CEFBS_None, // FSQRT_rec = 984 | |
| CEFBS_None, // FSUB = 985 | |
| CEFBS_None, // FSUBS = 986 | |
| CEFBS_None, // FSUBS_rec = 987 | |
| CEFBS_None, // FSUB_rec = 988 | |
| CEFBS_None, // FTDIV = 989 | |
| CEFBS_None, // FTSQRT = 990 | |
| CEFBS_None, // GETtlsADDR = 991 | |
| CEFBS_None, // GETtlsADDR32 = 992 | |
| CEFBS_None, // GETtlsldADDR = 993 | |
| CEFBS_None, // GETtlsldADDR32 = 994 | |
| CEFBS_None, // HRFID = 995 | |
| CEFBS_None, // ICBI = 996 | |
| CEFBS_None, // ICBIEP = 997 | |
| CEFBS_None, // ICBLC = 998 | |
| CEFBS_None, // ICBLQ = 999 | |
| CEFBS_None, // ICBT = 1000 | |
| CEFBS_None, // ICBTLS = 1001 | |
| CEFBS_None, // ICCCI = 1002 | |
| CEFBS_None, // ISEL = 1003 | |
| CEFBS_None, // ISEL8 = 1004 | |
| CEFBS_None, // ISYNC = 1005 | |
| CEFBS_None, // LA = 1006 | |
| CEFBS_None, // LBARX = 1007 | |
| CEFBS_None, // LBARXL = 1008 | |
| CEFBS_None, // LBEPX = 1009 | |
| CEFBS_None, // LBZ = 1010 | |
| CEFBS_None, // LBZ8 = 1011 | |
| CEFBS_None, // LBZCIX = 1012 | |
| CEFBS_None, // LBZU = 1013 | |
| CEFBS_None, // LBZU8 = 1014 | |
| CEFBS_None, // LBZUX = 1015 | |
| CEFBS_None, // LBZUX8 = 1016 | |
| CEFBS_None, // LBZX = 1017 | |
| CEFBS_None, // LBZX8 = 1018 | |
| CEFBS_None, // LBZXTLS = 1019 | |
| CEFBS_None, // LBZXTLS_ = 1020 | |
| CEFBS_None, // LBZXTLS_32 = 1021 | |
| CEFBS_None, // LD = 1022 | |
| CEFBS_None, // LDARX = 1023 | |
| CEFBS_None, // LDARXL = 1024 | |
| CEFBS_None, // LDAT = 1025 | |
| CEFBS_None, // LDBRX = 1026 | |
| CEFBS_None, // LDCIX = 1027 | |
| CEFBS_None, // LDMX = 1028 | |
| CEFBS_None, // LDU = 1029 | |
| CEFBS_None, // LDUX = 1030 | |
| CEFBS_None, // LDX = 1031 | |
| CEFBS_None, // LDXTLS = 1032 | |
| CEFBS_None, // LDXTLS_ = 1033 | |
| CEFBS_None, // LDgotTprelL = 1034 | |
| CEFBS_None, // LDgotTprelL32 = 1035 | |
| CEFBS_None, // LDtoc = 1036 | |
| CEFBS_None, // LDtocBA = 1037 | |
| CEFBS_None, // LDtocCPT = 1038 | |
| CEFBS_None, // LDtocJTI = 1039 | |
| CEFBS_None, // LDtocL = 1040 | |
| CEFBS_None, // LFD = 1041 | |
| CEFBS_None, // LFDEPX = 1042 | |
| CEFBS_None, // LFDU = 1043 | |
| CEFBS_None, // LFDUX = 1044 | |
| CEFBS_None, // LFDX = 1045 | |
| CEFBS_None, // LFIWAX = 1046 | |
| CEFBS_None, // LFIWZX = 1047 | |
| CEFBS_None, // LFS = 1048 | |
| CEFBS_None, // LFSU = 1049 | |
| CEFBS_None, // LFSUX = 1050 | |
| CEFBS_None, // LFSX = 1051 | |
| CEFBS_None, // LHA = 1052 | |
| CEFBS_None, // LHA8 = 1053 | |
| CEFBS_None, // LHARX = 1054 | |
| CEFBS_None, // LHARXL = 1055 | |
| CEFBS_None, // LHAU = 1056 | |
| CEFBS_None, // LHAU8 = 1057 | |
| CEFBS_None, // LHAUX = 1058 | |
| CEFBS_None, // LHAUX8 = 1059 | |
| CEFBS_None, // LHAX = 1060 | |
| CEFBS_None, // LHAX8 = 1061 | |
| CEFBS_None, // LHBRX = 1062 | |
| CEFBS_None, // LHBRX8 = 1063 | |
| CEFBS_None, // LHEPX = 1064 | |
| CEFBS_None, // LHZ = 1065 | |
| CEFBS_None, // LHZ8 = 1066 | |
| CEFBS_None, // LHZCIX = 1067 | |
| CEFBS_None, // LHZU = 1068 | |
| CEFBS_None, // LHZU8 = 1069 | |
| CEFBS_None, // LHZUX = 1070 | |
| CEFBS_None, // LHZUX8 = 1071 | |
| CEFBS_None, // LHZX = 1072 | |
| CEFBS_None, // LHZX8 = 1073 | |
| CEFBS_None, // LHZXTLS = 1074 | |
| CEFBS_None, // LHZXTLS_ = 1075 | |
| CEFBS_None, // LHZXTLS_32 = 1076 | |
| CEFBS_None, // LI = 1077 | |
| CEFBS_None, // LI8 = 1078 | |
| CEFBS_None, // LIS = 1079 | |
| CEFBS_None, // LIS8 = 1080 | |
| CEFBS_None, // LMW = 1081 | |
| CEFBS_None, // LSWI = 1082 | |
| CEFBS_None, // LVEBX = 1083 | |
| CEFBS_None, // LVEHX = 1084 | |
| CEFBS_None, // LVEWX = 1085 | |
| CEFBS_None, // LVSL = 1086 | |
| CEFBS_None, // LVSR = 1087 | |
| CEFBS_None, // LVX = 1088 | |
| CEFBS_None, // LVXL = 1089 | |
| CEFBS_None, // LWA = 1090 | |
| CEFBS_None, // LWARX = 1091 | |
| CEFBS_None, // LWARXL = 1092 | |
| CEFBS_None, // LWAT = 1093 | |
| CEFBS_None, // LWAUX = 1094 | |
| CEFBS_None, // LWAX = 1095 | |
| CEFBS_None, // LWAX_32 = 1096 | |
| CEFBS_None, // LWA_32 = 1097 | |
| CEFBS_None, // LWBRX = 1098 | |
| CEFBS_None, // LWBRX8 = 1099 | |
| CEFBS_None, // LWEPX = 1100 | |
| CEFBS_None, // LWZ = 1101 | |
| CEFBS_None, // LWZ8 = 1102 | |
| CEFBS_None, // LWZCIX = 1103 | |
| CEFBS_None, // LWZU = 1104 | |
| CEFBS_None, // LWZU8 = 1105 | |
| CEFBS_None, // LWZUX = 1106 | |
| CEFBS_None, // LWZUX8 = 1107 | |
| CEFBS_None, // LWZX = 1108 | |
| CEFBS_None, // LWZX8 = 1109 | |
| CEFBS_None, // LWZXTLS = 1110 | |
| CEFBS_None, // LWZXTLS_ = 1111 | |
| CEFBS_None, // LWZXTLS_32 = 1112 | |
| CEFBS_None, // LWZtoc = 1113 | |
| CEFBS_None, // LWZtocL = 1114 | |
| CEFBS_None, // LXSD = 1115 | |
| CEFBS_None, // LXSDX = 1116 | |
| CEFBS_None, // LXSIBZX = 1117 | |
| CEFBS_None, // LXSIHZX = 1118 | |
| CEFBS_None, // LXSIWAX = 1119 | |
| CEFBS_None, // LXSIWZX = 1120 | |
| CEFBS_None, // LXSSP = 1121 | |
| CEFBS_None, // LXSSPX = 1122 | |
| CEFBS_None, // LXV = 1123 | |
| CEFBS_None, // LXVB16X = 1124 | |
| CEFBS_None, // LXVD2X = 1125 | |
| CEFBS_None, // LXVDSX = 1126 | |
| CEFBS_None, // LXVH8X = 1127 | |
| CEFBS_None, // LXVL = 1128 | |
| CEFBS_None, // LXVLL = 1129 | |
| CEFBS_None, // LXVW4X = 1130 | |
| CEFBS_None, // LXVWSX = 1131 | |
| CEFBS_None, // LXVX = 1132 | |
| CEFBS_None, // MADDHD = 1133 | |
| CEFBS_None, // MADDHDU = 1134 | |
| CEFBS_None, // MADDLD = 1135 | |
| CEFBS_None, // MADDLD8 = 1136 | |
| CEFBS_None, // MBAR = 1137 | |
| CEFBS_None, // MCRF = 1138 | |
| CEFBS_None, // MCRFS = 1139 | |
| CEFBS_None, // MCRXRX = 1140 | |
| CEFBS_None, // MFBHRBE = 1141 | |
| CEFBS_None, // MFCR = 1142 | |
| CEFBS_None, // MFCR8 = 1143 | |
| CEFBS_None, // MFCTR = 1144 | |
| CEFBS_None, // MFCTR8 = 1145 | |
| CEFBS_None, // MFDCR = 1146 | |
| CEFBS_None, // MFFS = 1147 | |
| CEFBS_None, // MFFSCDRN = 1148 | |
| CEFBS_None, // MFFSCDRNI = 1149 | |
| CEFBS_None, // MFFSCE = 1150 | |
| CEFBS_None, // MFFSCRN = 1151 | |
| CEFBS_None, // MFFSCRNI = 1152 | |
| CEFBS_None, // MFFSL = 1153 | |
| CEFBS_None, // MFFS_rec = 1154 | |
| CEFBS_None, // MFLR = 1155 | |
| CEFBS_None, // MFLR8 = 1156 | |
| CEFBS_None, // MFMSR = 1157 | |
| CEFBS_None, // MFOCRF = 1158 | |
| CEFBS_None, // MFOCRF8 = 1159 | |
| CEFBS_None, // MFPMR = 1160 | |
| CEFBS_None, // MFSPR = 1161 | |
| CEFBS_None, // MFSPR8 = 1162 | |
| CEFBS_None, // MFSR = 1163 | |
| CEFBS_None, // MFSRIN = 1164 | |
| CEFBS_None, // MFTB = 1165 | |
| CEFBS_None, // MFTB8 = 1166 | |
| CEFBS_None, // MFVRD = 1167 | |
| CEFBS_None, // MFVRSAVE = 1168 | |
| CEFBS_None, // MFVRSAVEv = 1169 | |
| CEFBS_None, // MFVRWZ = 1170 | |
| CEFBS_None, // MFVSCR = 1171 | |
| CEFBS_None, // MFVSRD = 1172 | |
| CEFBS_None, // MFVSRLD = 1173 | |
| CEFBS_None, // MFVSRWZ = 1174 | |
| CEFBS_None, // MODSD = 1175 | |
| CEFBS_None, // MODSW = 1176 | |
| CEFBS_None, // MODUD = 1177 | |
| CEFBS_None, // MODUW = 1178 | |
| CEFBS_None, // MSGSYNC = 1179 | |
| CEFBS_None, // MSYNC = 1180 | |
| CEFBS_None, // MTCRF = 1181 | |
| CEFBS_None, // MTCRF8 = 1182 | |
| CEFBS_None, // MTCTR = 1183 | |
| CEFBS_None, // MTCTR8 = 1184 | |
| CEFBS_None, // MTCTR8loop = 1185 | |
| CEFBS_None, // MTCTRloop = 1186 | |
| CEFBS_None, // MTDCR = 1187 | |
| CEFBS_None, // MTFSB0 = 1188 | |
| CEFBS_None, // MTFSB1 = 1189 | |
| CEFBS_None, // MTFSF = 1190 | |
| CEFBS_None, // MTFSFI = 1191 | |
| CEFBS_None, // MTFSFI_rec = 1192 | |
| CEFBS_None, // MTFSF_rec = 1193 | |
| CEFBS_None, // MTFSFb = 1194 | |
| CEFBS_None, // MTLR = 1195 | |
| CEFBS_None, // MTLR8 = 1196 | |
| CEFBS_None, // MTMSR = 1197 | |
| CEFBS_None, // MTMSRD = 1198 | |
| CEFBS_None, // MTOCRF = 1199 | |
| CEFBS_None, // MTOCRF8 = 1200 | |
| CEFBS_None, // MTPMR = 1201 | |
| CEFBS_None, // MTSPR = 1202 | |
| CEFBS_None, // MTSPR8 = 1203 | |
| CEFBS_None, // MTSR = 1204 | |
| CEFBS_None, // MTSRIN = 1205 | |
| CEFBS_None, // MTVRD = 1206 | |
| CEFBS_None, // MTVRSAVE = 1207 | |
| CEFBS_None, // MTVRSAVEv = 1208 | |
| CEFBS_None, // MTVRWA = 1209 | |
| CEFBS_None, // MTVRWZ = 1210 | |
| CEFBS_None, // MTVSCR = 1211 | |
| CEFBS_None, // MTVSRD = 1212 | |
| CEFBS_None, // MTVSRDD = 1213 | |
| CEFBS_None, // MTVSRWA = 1214 | |
| CEFBS_None, // MTVSRWS = 1215 | |
| CEFBS_None, // MTVSRWZ = 1216 | |
| CEFBS_None, // MULHD = 1217 | |
| CEFBS_None, // MULHDU = 1218 | |
| CEFBS_None, // MULHDU_rec = 1219 | |
| CEFBS_None, // MULHD_rec = 1220 | |
| CEFBS_None, // MULHW = 1221 | |
| CEFBS_None, // MULHWU = 1222 | |
| CEFBS_None, // MULHWU_rec = 1223 | |
| CEFBS_None, // MULHW_rec = 1224 | |
| CEFBS_None, // MULLD = 1225 | |
| CEFBS_None, // MULLDO = 1226 | |
| CEFBS_None, // MULLDO_rec = 1227 | |
| CEFBS_None, // MULLD_rec = 1228 | |
| CEFBS_None, // MULLI = 1229 | |
| CEFBS_None, // MULLI8 = 1230 | |
| CEFBS_None, // MULLW = 1231 | |
| CEFBS_None, // MULLWO = 1232 | |
| CEFBS_None, // MULLWO_rec = 1233 | |
| CEFBS_None, // MULLW_rec = 1234 | |
| CEFBS_None, // MoveGOTtoLR = 1235 | |
| CEFBS_None, // MovePCtoLR = 1236 | |
| CEFBS_None, // MovePCtoLR8 = 1237 | |
| CEFBS_None, // NAND = 1238 | |
| CEFBS_None, // NAND8 = 1239 | |
| CEFBS_None, // NAND8_rec = 1240 | |
| CEFBS_None, // NAND_rec = 1241 | |
| CEFBS_None, // NAP = 1242 | |
| CEFBS_None, // NEG = 1243 | |
| CEFBS_None, // NEG8 = 1244 | |
| CEFBS_None, // NEG8O = 1245 | |
| CEFBS_None, // NEG8O_rec = 1246 | |
| CEFBS_None, // NEG8_rec = 1247 | |
| CEFBS_None, // NEGO = 1248 | |
| CEFBS_None, // NEGO_rec = 1249 | |
| CEFBS_None, // NEG_rec = 1250 | |
| CEFBS_None, // NOP = 1251 | |
| CEFBS_None, // NOP_GT_PWR6 = 1252 | |
| CEFBS_None, // NOP_GT_PWR7 = 1253 | |
| CEFBS_None, // NOR = 1254 | |
| CEFBS_None, // NOR8 = 1255 | |
| CEFBS_None, // NOR8_rec = 1256 | |
| CEFBS_None, // NOR_rec = 1257 | |
| CEFBS_None, // OR = 1258 | |
| CEFBS_None, // OR8 = 1259 | |
| CEFBS_None, // OR8_rec = 1260 | |
| CEFBS_None, // ORC = 1261 | |
| CEFBS_None, // ORC8 = 1262 | |
| CEFBS_None, // ORC8_rec = 1263 | |
| CEFBS_None, // ORC_rec = 1264 | |
| CEFBS_None, // ORI = 1265 | |
| CEFBS_None, // ORI8 = 1266 | |
| CEFBS_None, // ORIS = 1267 | |
| CEFBS_None, // ORIS8 = 1268 | |
| CEFBS_None, // OR_rec = 1269 | |
| CEFBS_None, // POPCNTB = 1270 | |
| CEFBS_None, // POPCNTD = 1271 | |
| CEFBS_None, // POPCNTW = 1272 | |
| CEFBS_None, // PPC32GOT = 1273 | |
| CEFBS_None, // PPC32PICGOT = 1274 | |
| CEFBS_None, // QVALIGNI = 1275 | |
| CEFBS_None, // QVALIGNIb = 1276 | |
| CEFBS_None, // QVALIGNIs = 1277 | |
| CEFBS_None, // QVESPLATI = 1278 | |
| CEFBS_None, // QVESPLATIb = 1279 | |
| CEFBS_None, // QVESPLATIs = 1280 | |
| CEFBS_None, // QVFABS = 1281 | |
| CEFBS_None, // QVFABSs = 1282 | |
| CEFBS_None, // QVFADD = 1283 | |
| CEFBS_None, // QVFADDS = 1284 | |
| CEFBS_None, // QVFADDSs = 1285 | |
| CEFBS_None, // QVFCFID = 1286 | |
| CEFBS_None, // QVFCFIDS = 1287 | |
| CEFBS_None, // QVFCFIDU = 1288 | |
| CEFBS_None, // QVFCFIDUS = 1289 | |
| CEFBS_None, // QVFCFIDb = 1290 | |
| CEFBS_None, // QVFCMPEQ = 1291 | |
| CEFBS_None, // QVFCMPEQb = 1292 | |
| CEFBS_None, // QVFCMPEQbs = 1293 | |
| CEFBS_None, // QVFCMPGT = 1294 | |
| CEFBS_None, // QVFCMPGTb = 1295 | |
| CEFBS_None, // QVFCMPGTbs = 1296 | |
| CEFBS_None, // QVFCMPLT = 1297 | |
| CEFBS_None, // QVFCMPLTb = 1298 | |
| CEFBS_None, // QVFCMPLTbs = 1299 | |
| CEFBS_None, // QVFCPSGN = 1300 | |
| CEFBS_None, // QVFCPSGNs = 1301 | |
| CEFBS_None, // QVFCTID = 1302 | |
| CEFBS_None, // QVFCTIDU = 1303 | |
| CEFBS_None, // QVFCTIDUZ = 1304 | |
| CEFBS_None, // QVFCTIDZ = 1305 | |
| CEFBS_None, // QVFCTIDb = 1306 | |
| CEFBS_None, // QVFCTIW = 1307 | |
| CEFBS_None, // QVFCTIWU = 1308 | |
| CEFBS_None, // QVFCTIWUZ = 1309 | |
| CEFBS_None, // QVFCTIWZ = 1310 | |
| CEFBS_None, // QVFLOGICAL = 1311 | |
| CEFBS_None, // QVFLOGICALb = 1312 | |
| CEFBS_None, // QVFLOGICALs = 1313 | |
| CEFBS_None, // QVFMADD = 1314 | |
| CEFBS_None, // QVFMADDS = 1315 | |
| CEFBS_None, // QVFMADDSs = 1316 | |
| CEFBS_None, // QVFMR = 1317 | |
| CEFBS_None, // QVFMRb = 1318 | |
| CEFBS_None, // QVFMRs = 1319 | |
| CEFBS_None, // QVFMSUB = 1320 | |
| CEFBS_None, // QVFMSUBS = 1321 | |
| CEFBS_None, // QVFMSUBSs = 1322 | |
| CEFBS_None, // QVFMUL = 1323 | |
| CEFBS_None, // QVFMULS = 1324 | |
| CEFBS_None, // QVFMULSs = 1325 | |
| CEFBS_None, // QVFNABS = 1326 | |
| CEFBS_None, // QVFNABSs = 1327 | |
| CEFBS_None, // QVFNEG = 1328 | |
| CEFBS_None, // QVFNEGs = 1329 | |
| CEFBS_None, // QVFNMADD = 1330 | |
| CEFBS_None, // QVFNMADDS = 1331 | |
| CEFBS_None, // QVFNMADDSs = 1332 | |
| CEFBS_None, // QVFNMSUB = 1333 | |
| CEFBS_None, // QVFNMSUBS = 1334 | |
| CEFBS_None, // QVFNMSUBSs = 1335 | |
| CEFBS_None, // QVFPERM = 1336 | |
| CEFBS_None, // QVFPERMs = 1337 | |
| CEFBS_None, // QVFRE = 1338 | |
| CEFBS_None, // QVFRES = 1339 | |
| CEFBS_None, // QVFRESs = 1340 | |
| CEFBS_None, // QVFRIM = 1341 | |
| CEFBS_None, // QVFRIMs = 1342 | |
| CEFBS_None, // QVFRIN = 1343 | |
| CEFBS_None, // QVFRINs = 1344 | |
| CEFBS_None, // QVFRIP = 1345 | |
| CEFBS_None, // QVFRIPs = 1346 | |
| CEFBS_None, // QVFRIZ = 1347 | |
| CEFBS_None, // QVFRIZs = 1348 | |
| CEFBS_None, // QVFRSP = 1349 | |
| CEFBS_None, // QVFRSPs = 1350 | |
| CEFBS_None, // QVFRSQRTE = 1351 | |
| CEFBS_None, // QVFRSQRTES = 1352 | |
| CEFBS_None, // QVFRSQRTESs = 1353 | |
| CEFBS_None, // QVFSEL = 1354 | |
| CEFBS_None, // QVFSELb = 1355 | |
| CEFBS_None, // QVFSELbb = 1356 | |
| CEFBS_None, // QVFSELbs = 1357 | |
| CEFBS_None, // QVFSUB = 1358 | |
| CEFBS_None, // QVFSUBS = 1359 | |
| CEFBS_None, // QVFSUBSs = 1360 | |
| CEFBS_None, // QVFTSTNAN = 1361 | |
| CEFBS_None, // QVFTSTNANb = 1362 | |
| CEFBS_None, // QVFTSTNANbs = 1363 | |
| CEFBS_None, // QVFXMADD = 1364 | |
| CEFBS_None, // QVFXMADDS = 1365 | |
| CEFBS_None, // QVFXMUL = 1366 | |
| CEFBS_None, // QVFXMULS = 1367 | |
| CEFBS_None, // QVFXXCPNMADD = 1368 | |
| CEFBS_None, // QVFXXCPNMADDS = 1369 | |
| CEFBS_None, // QVFXXMADD = 1370 | |
| CEFBS_None, // QVFXXMADDS = 1371 | |
| CEFBS_None, // QVFXXNPMADD = 1372 | |
| CEFBS_None, // QVFXXNPMADDS = 1373 | |
| CEFBS_None, // QVGPCI = 1374 | |
| CEFBS_None, // QVLFCDUX = 1375 | |
| CEFBS_None, // QVLFCDUXA = 1376 | |
| CEFBS_None, // QVLFCDX = 1377 | |
| CEFBS_None, // QVLFCDXA = 1378 | |
| CEFBS_None, // QVLFCSUX = 1379 | |
| CEFBS_None, // QVLFCSUXA = 1380 | |
| CEFBS_None, // QVLFCSX = 1381 | |
| CEFBS_None, // QVLFCSXA = 1382 | |
| CEFBS_None, // QVLFCSXs = 1383 | |
| CEFBS_None, // QVLFDUX = 1384 | |
| CEFBS_None, // QVLFDUXA = 1385 | |
| CEFBS_None, // QVLFDX = 1386 | |
| CEFBS_None, // QVLFDXA = 1387 | |
| CEFBS_None, // QVLFDXb = 1388 | |
| CEFBS_None, // QVLFIWAX = 1389 | |
| CEFBS_None, // QVLFIWAXA = 1390 | |
| CEFBS_None, // QVLFIWZX = 1391 | |
| CEFBS_None, // QVLFIWZXA = 1392 | |
| CEFBS_None, // QVLFSUX = 1393 | |
| CEFBS_None, // QVLFSUXA = 1394 | |
| CEFBS_None, // QVLFSX = 1395 | |
| CEFBS_None, // QVLFSXA = 1396 | |
| CEFBS_None, // QVLFSXb = 1397 | |
| CEFBS_None, // QVLFSXs = 1398 | |
| CEFBS_None, // QVLPCLDX = 1399 | |
| CEFBS_None, // QVLPCLSX = 1400 | |
| CEFBS_None, // QVLPCLSXint = 1401 | |
| CEFBS_None, // QVLPCRDX = 1402 | |
| CEFBS_None, // QVLPCRSX = 1403 | |
| CEFBS_None, // QVSTFCDUX = 1404 | |
| CEFBS_None, // QVSTFCDUXA = 1405 | |
| CEFBS_None, // QVSTFCDUXI = 1406 | |
| CEFBS_None, // QVSTFCDUXIA = 1407 | |
| CEFBS_None, // QVSTFCDX = 1408 | |
| CEFBS_None, // QVSTFCDXA = 1409 | |
| CEFBS_None, // QVSTFCDXI = 1410 | |
| CEFBS_None, // QVSTFCDXIA = 1411 | |
| CEFBS_None, // QVSTFCSUX = 1412 | |
| CEFBS_None, // QVSTFCSUXA = 1413 | |
| CEFBS_None, // QVSTFCSUXI = 1414 | |
| CEFBS_None, // QVSTFCSUXIA = 1415 | |
| CEFBS_None, // QVSTFCSX = 1416 | |
| CEFBS_None, // QVSTFCSXA = 1417 | |
| CEFBS_None, // QVSTFCSXI = 1418 | |
| CEFBS_None, // QVSTFCSXIA = 1419 | |
| CEFBS_None, // QVSTFCSXs = 1420 | |
| CEFBS_None, // QVSTFDUX = 1421 | |
| CEFBS_None, // QVSTFDUXA = 1422 | |
| CEFBS_None, // QVSTFDUXI = 1423 | |
| CEFBS_None, // QVSTFDUXIA = 1424 | |
| CEFBS_None, // QVSTFDX = 1425 | |
| CEFBS_None, // QVSTFDXA = 1426 | |
| CEFBS_None, // QVSTFDXI = 1427 | |
| CEFBS_None, // QVSTFDXIA = 1428 | |
| CEFBS_None, // QVSTFDXb = 1429 | |
| CEFBS_None, // QVSTFIWX = 1430 | |
| CEFBS_None, // QVSTFIWXA = 1431 | |
| CEFBS_None, // QVSTFSUX = 1432 | |
| CEFBS_None, // QVSTFSUXA = 1433 | |
| CEFBS_None, // QVSTFSUXI = 1434 | |
| CEFBS_None, // QVSTFSUXIA = 1435 | |
| CEFBS_None, // QVSTFSUXs = 1436 | |
| CEFBS_None, // QVSTFSX = 1437 | |
| CEFBS_None, // QVSTFSXA = 1438 | |
| CEFBS_None, // QVSTFSXI = 1439 | |
| CEFBS_None, // QVSTFSXIA = 1440 | |
| CEFBS_None, // QVSTFSXs = 1441 | |
| CEFBS_None, // RESTORE_CR = 1442 | |
| CEFBS_None, // RESTORE_CRBIT = 1443 | |
| CEFBS_None, // RESTORE_VRSAVE = 1444 | |
| CEFBS_None, // RFCI = 1445 | |
| CEFBS_None, // RFDI = 1446 | |
| CEFBS_None, // RFEBB = 1447 | |
| CEFBS_None, // RFI = 1448 | |
| CEFBS_None, // RFID = 1449 | |
| CEFBS_None, // RFMCI = 1450 | |
| CEFBS_None, // RLDCL = 1451 | |
| CEFBS_None, // RLDCL_rec = 1452 | |
| CEFBS_None, // RLDCR = 1453 | |
| CEFBS_None, // RLDCR_rec = 1454 | |
| CEFBS_None, // RLDIC = 1455 | |
| CEFBS_None, // RLDICL = 1456 | |
| CEFBS_None, // RLDICL_32 = 1457 | |
| CEFBS_None, // RLDICL_32_64 = 1458 | |
| CEFBS_None, // RLDICL_32_rec = 1459 | |
| CEFBS_None, // RLDICL_rec = 1460 | |
| CEFBS_None, // RLDICR = 1461 | |
| CEFBS_None, // RLDICR_32 = 1462 | |
| CEFBS_None, // RLDICR_rec = 1463 | |
| CEFBS_None, // RLDIC_rec = 1464 | |
| CEFBS_None, // RLDIMI = 1465 | |
| CEFBS_None, // RLDIMI_rec = 1466 | |
| CEFBS_None, // RLWIMI = 1467 | |
| CEFBS_None, // RLWIMI8 = 1468 | |
| CEFBS_None, // RLWIMI8_rec = 1469 | |
| CEFBS_None, // RLWIMI_rec = 1470 | |
| CEFBS_None, // RLWINM = 1471 | |
| CEFBS_None, // RLWINM8 = 1472 | |
| CEFBS_None, // RLWINM8_rec = 1473 | |
| CEFBS_None, // RLWINM_rec = 1474 | |
| CEFBS_None, // RLWNM = 1475 | |
| CEFBS_None, // RLWNM8 = 1476 | |
| CEFBS_None, // RLWNM8_rec = 1477 | |
| CEFBS_None, // RLWNM_rec = 1478 | |
| CEFBS_None, // ReadTB = 1479 | |
| CEFBS_None, // SC = 1480 | |
| CEFBS_None, // SELECT_CC_F16 = 1481 | |
| CEFBS_None, // SELECT_CC_F4 = 1482 | |
| CEFBS_None, // SELECT_CC_F8 = 1483 | |
| CEFBS_None, // SELECT_CC_I4 = 1484 | |
| CEFBS_None, // SELECT_CC_I8 = 1485 | |
| CEFBS_None, // SELECT_CC_QBRC = 1486 | |
| CEFBS_None, // SELECT_CC_QFRC = 1487 | |
| CEFBS_None, // SELECT_CC_QSRC = 1488 | |
| CEFBS_None, // SELECT_CC_SPE = 1489 | |
| CEFBS_None, // SELECT_CC_SPE4 = 1490 | |
| CEFBS_None, // SELECT_CC_VRRC = 1491 | |
| CEFBS_None, // SELECT_CC_VSFRC = 1492 | |
| CEFBS_None, // SELECT_CC_VSRC = 1493 | |
| CEFBS_None, // SELECT_CC_VSSRC = 1494 | |
| CEFBS_None, // SELECT_F16 = 1495 | |
| CEFBS_None, // SELECT_F4 = 1496 | |
| CEFBS_None, // SELECT_F8 = 1497 | |
| CEFBS_None, // SELECT_I4 = 1498 | |
| CEFBS_None, // SELECT_I8 = 1499 | |
| CEFBS_None, // SELECT_QBRC = 1500 | |
| CEFBS_None, // SELECT_QFRC = 1501 | |
| CEFBS_None, // SELECT_QSRC = 1502 | |
| CEFBS_None, // SELECT_SPE = 1503 | |
| CEFBS_None, // SELECT_SPE4 = 1504 | |
| CEFBS_None, // SELECT_VRRC = 1505 | |
| CEFBS_None, // SELECT_VSFRC = 1506 | |
| CEFBS_None, // SELECT_VSRC = 1507 | |
| CEFBS_None, // SELECT_VSSRC = 1508 | |
| CEFBS_None, // SETB = 1509 | |
| CEFBS_None, // SETB8 = 1510 | |
| CEFBS_None, // SETRND = 1511 | |
| CEFBS_None, // SETRNDi = 1512 | |
| CEFBS_None, // SLBFEE_rec = 1513 | |
| CEFBS_None, // SLBIA = 1514 | |
| CEFBS_None, // SLBIE = 1515 | |
| CEFBS_None, // SLBIEG = 1516 | |
| CEFBS_None, // SLBMFEE = 1517 | |
| CEFBS_None, // SLBMFEV = 1518 | |
| CEFBS_None, // SLBMTE = 1519 | |
| CEFBS_None, // SLBSYNC = 1520 | |
| CEFBS_None, // SLD = 1521 | |
| CEFBS_None, // SLD_rec = 1522 | |
| CEFBS_None, // SLW = 1523 | |
| CEFBS_None, // SLW8 = 1524 | |
| CEFBS_None, // SLW8_rec = 1525 | |
| CEFBS_None, // SLW_rec = 1526 | |
| CEFBS_None, // SPELWZ = 1527 | |
| CEFBS_None, // SPELWZX = 1528 | |
| CEFBS_None, // SPESTW = 1529 | |
| CEFBS_None, // SPESTWX = 1530 | |
| CEFBS_None, // SPILL_CR = 1531 | |
| CEFBS_None, // SPILL_CRBIT = 1532 | |
| CEFBS_None, // SPILL_VRSAVE = 1533 | |
| CEFBS_None, // SRAD = 1534 | |
| CEFBS_None, // SRADI = 1535 | |
| CEFBS_None, // SRADI_32 = 1536 | |
| CEFBS_None, // SRADI_rec = 1537 | |
| CEFBS_None, // SRAD_rec = 1538 | |
| CEFBS_None, // SRAW = 1539 | |
| CEFBS_None, // SRAWI = 1540 | |
| CEFBS_None, // SRAWI_rec = 1541 | |
| CEFBS_None, // SRAW_rec = 1542 | |
| CEFBS_None, // SRD = 1543 | |
| CEFBS_None, // SRD_rec = 1544 | |
| CEFBS_None, // SRW = 1545 | |
| CEFBS_None, // SRW8 = 1546 | |
| CEFBS_None, // SRW8_rec = 1547 | |
| CEFBS_None, // SRW_rec = 1548 | |
| CEFBS_None, // STB = 1549 | |
| CEFBS_None, // STB8 = 1550 | |
| CEFBS_None, // STBCIX = 1551 | |
| CEFBS_None, // STBCX = 1552 | |
| CEFBS_None, // STBEPX = 1553 | |
| CEFBS_None, // STBU = 1554 | |
| CEFBS_None, // STBU8 = 1555 | |
| CEFBS_None, // STBUX = 1556 | |
| CEFBS_None, // STBUX8 = 1557 | |
| CEFBS_None, // STBX = 1558 | |
| CEFBS_None, // STBX8 = 1559 | |
| CEFBS_None, // STBXTLS = 1560 | |
| CEFBS_None, // STBXTLS_ = 1561 | |
| CEFBS_None, // STBXTLS_32 = 1562 | |
| CEFBS_None, // STD = 1563 | |
| CEFBS_None, // STDAT = 1564 | |
| CEFBS_None, // STDBRX = 1565 | |
| CEFBS_None, // STDCIX = 1566 | |
| CEFBS_None, // STDCX = 1567 | |
| CEFBS_None, // STDU = 1568 | |
| CEFBS_None, // STDUX = 1569 | |
| CEFBS_None, // STDX = 1570 | |
| CEFBS_None, // STDXTLS = 1571 | |
| CEFBS_None, // STDXTLS_ = 1572 | |
| CEFBS_None, // STFD = 1573 | |
| CEFBS_None, // STFDEPX = 1574 | |
| CEFBS_None, // STFDU = 1575 | |
| CEFBS_None, // STFDUX = 1576 | |
| CEFBS_None, // STFDX = 1577 | |
| CEFBS_None, // STFIWX = 1578 | |
| CEFBS_None, // STFS = 1579 | |
| CEFBS_None, // STFSU = 1580 | |
| CEFBS_None, // STFSUX = 1581 | |
| CEFBS_None, // STFSX = 1582 | |
| CEFBS_None, // STH = 1583 | |
| CEFBS_None, // STH8 = 1584 | |
| CEFBS_None, // STHBRX = 1585 | |
| CEFBS_None, // STHCIX = 1586 | |
| CEFBS_None, // STHCX = 1587 | |
| CEFBS_None, // STHEPX = 1588 | |
| CEFBS_None, // STHU = 1589 | |
| CEFBS_None, // STHU8 = 1590 | |
| CEFBS_None, // STHUX = 1591 | |
| CEFBS_None, // STHUX8 = 1592 | |
| CEFBS_None, // STHX = 1593 | |
| CEFBS_None, // STHX8 = 1594 | |
| CEFBS_None, // STHXTLS = 1595 | |
| CEFBS_None, // STHXTLS_ = 1596 | |
| CEFBS_None, // STHXTLS_32 = 1597 | |
| CEFBS_None, // STMW = 1598 | |
| CEFBS_None, // STOP = 1599 | |
| CEFBS_None, // STSWI = 1600 | |
| CEFBS_None, // STVEBX = 1601 | |
| CEFBS_None, // STVEHX = 1602 | |
| CEFBS_None, // STVEWX = 1603 | |
| CEFBS_None, // STVX = 1604 | |
| CEFBS_None, // STVXL = 1605 | |
| CEFBS_None, // STW = 1606 | |
| CEFBS_None, // STW8 = 1607 | |
| CEFBS_None, // STWAT = 1608 | |
| CEFBS_None, // STWBRX = 1609 | |
| CEFBS_None, // STWCIX = 1610 | |
| CEFBS_None, // STWCX = 1611 | |
| CEFBS_None, // STWEPX = 1612 | |
| CEFBS_None, // STWU = 1613 | |
| CEFBS_None, // STWU8 = 1614 | |
| CEFBS_None, // STWUX = 1615 | |
| CEFBS_None, // STWUX8 = 1616 | |
| CEFBS_None, // STWX = 1617 | |
| CEFBS_None, // STWX8 = 1618 | |
| CEFBS_None, // STWXTLS = 1619 | |
| CEFBS_None, // STWXTLS_ = 1620 | |
| CEFBS_None, // STWXTLS_32 = 1621 | |
| CEFBS_None, // STXSD = 1622 | |
| CEFBS_None, // STXSDX = 1623 | |
| CEFBS_None, // STXSIBX = 1624 | |
| CEFBS_None, // STXSIBXv = 1625 | |
| CEFBS_None, // STXSIHX = 1626 | |
| CEFBS_None, // STXSIHXv = 1627 | |
| CEFBS_None, // STXSIWX = 1628 | |
| CEFBS_None, // STXSSP = 1629 | |
| CEFBS_None, // STXSSPX = 1630 | |
| CEFBS_None, // STXV = 1631 | |
| CEFBS_None, // STXVB16X = 1632 | |
| CEFBS_None, // STXVD2X = 1633 | |
| CEFBS_None, // STXVH8X = 1634 | |
| CEFBS_None, // STXVL = 1635 | |
| CEFBS_None, // STXVLL = 1636 | |
| CEFBS_None, // STXVW4X = 1637 | |
| CEFBS_None, // STXVX = 1638 | |
| CEFBS_None, // SUBF = 1639 | |
| CEFBS_None, // SUBF8 = 1640 | |
| CEFBS_None, // SUBF8O = 1641 | |
| CEFBS_None, // SUBF8O_rec = 1642 | |
| CEFBS_None, // SUBF8_rec = 1643 | |
| CEFBS_None, // SUBFC = 1644 | |
| CEFBS_None, // SUBFC8 = 1645 | |
| CEFBS_None, // SUBFC8O = 1646 | |
| CEFBS_None, // SUBFC8O_rec = 1647 | |
| CEFBS_None, // SUBFC8_rec = 1648 | |
| CEFBS_None, // SUBFCO = 1649 | |
| CEFBS_None, // SUBFCO_rec = 1650 | |
| CEFBS_None, // SUBFC_rec = 1651 | |
| CEFBS_None, // SUBFE = 1652 | |
| CEFBS_None, // SUBFE8 = 1653 | |
| CEFBS_None, // SUBFE8O = 1654 | |
| CEFBS_None, // SUBFE8O_rec = 1655 | |
| CEFBS_None, // SUBFE8_rec = 1656 | |
| CEFBS_None, // SUBFEO = 1657 | |
| CEFBS_None, // SUBFEO_rec = 1658 | |
| CEFBS_None, // SUBFE_rec = 1659 | |
| CEFBS_None, // SUBFIC = 1660 | |
| CEFBS_None, // SUBFIC8 = 1661 | |
| CEFBS_None, // SUBFME = 1662 | |
| CEFBS_None, // SUBFME8 = 1663 | |
| CEFBS_None, // SUBFME8O = 1664 | |
| CEFBS_None, // SUBFME8O_rec = 1665 | |
| CEFBS_None, // SUBFME8_rec = 1666 | |
| CEFBS_None, // SUBFMEO = 1667 | |
| CEFBS_None, // SUBFMEO_rec = 1668 | |
| CEFBS_None, // SUBFME_rec = 1669 | |
| CEFBS_None, // SUBFO = 1670 | |
| CEFBS_None, // SUBFO_rec = 1671 | |
| CEFBS_None, // SUBFZE = 1672 | |
| CEFBS_None, // SUBFZE8 = 1673 | |
| CEFBS_None, // SUBFZE8O = 1674 | |
| CEFBS_None, // SUBFZE8O_rec = 1675 | |
| CEFBS_None, // SUBFZE8_rec = 1676 | |
| CEFBS_None, // SUBFZEO = 1677 | |
| CEFBS_None, // SUBFZEO_rec = 1678 | |
| CEFBS_None, // SUBFZE_rec = 1679 | |
| CEFBS_None, // SUBF_rec = 1680 | |
| CEFBS_None, // SYNC = 1681 | |
| CEFBS_None, // TABORT = 1682 | |
| CEFBS_None, // TABORTDC = 1683 | |
| CEFBS_None, // TABORTDCI = 1684 | |
| CEFBS_None, // TABORTWC = 1685 | |
| CEFBS_None, // TABORTWCI = 1686 | |
| CEFBS_None, // TAILB = 1687 | |
| CEFBS_None, // TAILB8 = 1688 | |
| CEFBS_None, // TAILBA = 1689 | |
| CEFBS_None, // TAILBA8 = 1690 | |
| CEFBS_None, // TAILBCTR = 1691 | |
| CEFBS_None, // TAILBCTR8 = 1692 | |
| CEFBS_None, // TBEGIN = 1693 | |
| CEFBS_None, // TBEGIN_RET = 1694 | |
| CEFBS_None, // TCHECK = 1695 | |
| CEFBS_None, // TCHECK_RET = 1696 | |
| CEFBS_None, // TCRETURNai = 1697 | |
| CEFBS_None, // TCRETURNai8 = 1698 | |
| CEFBS_None, // TCRETURNdi = 1699 | |
| CEFBS_None, // TCRETURNdi8 = 1700 | |
| CEFBS_None, // TCRETURNri = 1701 | |
| CEFBS_None, // TCRETURNri8 = 1702 | |
| CEFBS_None, // TD = 1703 | |
| CEFBS_None, // TDI = 1704 | |
| CEFBS_None, // TEND = 1705 | |
| CEFBS_None, // TLBIA = 1706 | |
| CEFBS_None, // TLBIE = 1707 | |
| CEFBS_None, // TLBIEL = 1708 | |
| CEFBS_None, // TLBIVAX = 1709 | |
| CEFBS_None, // TLBLD = 1710 | |
| CEFBS_None, // TLBLI = 1711 | |
| CEFBS_None, // TLBRE = 1712 | |
| CEFBS_None, // TLBRE2 = 1713 | |
| CEFBS_None, // TLBSX = 1714 | |
| CEFBS_None, // TLBSX2 = 1715 | |
| CEFBS_None, // TLBSX2D = 1716 | |
| CEFBS_None, // TLBSYNC = 1717 | |
| CEFBS_None, // TLBWE = 1718 | |
| CEFBS_None, // TLBWE2 = 1719 | |
| CEFBS_None, // TRAP = 1720 | |
| CEFBS_None, // TRECHKPT = 1721 | |
| CEFBS_None, // TRECLAIM = 1722 | |
| CEFBS_None, // TSR = 1723 | |
| CEFBS_None, // TW = 1724 | |
| CEFBS_None, // TWI = 1725 | |
| CEFBS_None, // UNENCODED_NOP = 1726 | |
| CEFBS_None, // UPDATE_VRSAVE = 1727 | |
| CEFBS_None, // UpdateGBR = 1728 | |
| CEFBS_None, // VABSDUB = 1729 | |
| CEFBS_None, // VABSDUH = 1730 | |
| CEFBS_None, // VABSDUW = 1731 | |
| CEFBS_None, // VADDCUQ = 1732 | |
| CEFBS_None, // VADDCUW = 1733 | |
| CEFBS_None, // VADDECUQ = 1734 | |
| CEFBS_None, // VADDEUQM = 1735 | |
| CEFBS_None, // VADDFP = 1736 | |
| CEFBS_None, // VADDSBS = 1737 | |
| CEFBS_None, // VADDSHS = 1738 | |
| CEFBS_None, // VADDSWS = 1739 | |
| CEFBS_None, // VADDUBM = 1740 | |
| CEFBS_None, // VADDUBS = 1741 | |
| CEFBS_None, // VADDUDM = 1742 | |
| CEFBS_None, // VADDUHM = 1743 | |
| CEFBS_None, // VADDUHS = 1744 | |
| CEFBS_None, // VADDUQM = 1745 | |
| CEFBS_None, // VADDUWM = 1746 | |
| CEFBS_None, // VADDUWS = 1747 | |
| CEFBS_None, // VAND = 1748 | |
| CEFBS_None, // VANDC = 1749 | |
| CEFBS_None, // VAVGSB = 1750 | |
| CEFBS_None, // VAVGSH = 1751 | |
| CEFBS_None, // VAVGSW = 1752 | |
| CEFBS_None, // VAVGUB = 1753 | |
| CEFBS_None, // VAVGUH = 1754 | |
| CEFBS_None, // VAVGUW = 1755 | |
| CEFBS_None, // VBPERMD = 1756 | |
| CEFBS_None, // VBPERMQ = 1757 | |
| CEFBS_None, // VCFSX = 1758 | |
| CEFBS_None, // VCFSX_0 = 1759 | |
| CEFBS_None, // VCFUX = 1760 | |
| CEFBS_None, // VCFUX_0 = 1761 | |
| CEFBS_None, // VCIPHER = 1762 | |
| CEFBS_None, // VCIPHERLAST = 1763 | |
| CEFBS_None, // VCLZB = 1764 | |
| CEFBS_None, // VCLZD = 1765 | |
| CEFBS_None, // VCLZH = 1766 | |
| CEFBS_None, // VCLZLSBB = 1767 | |
| CEFBS_None, // VCLZW = 1768 | |
| CEFBS_None, // VCMPBFP = 1769 | |
| CEFBS_None, // VCMPBFP_rec = 1770 | |
| CEFBS_None, // VCMPEQFP = 1771 | |
| CEFBS_None, // VCMPEQFP_rec = 1772 | |
| CEFBS_None, // VCMPEQUB = 1773 | |
| CEFBS_None, // VCMPEQUB_rec = 1774 | |
| CEFBS_None, // VCMPEQUD = 1775 | |
| CEFBS_None, // VCMPEQUD_rec = 1776 | |
| CEFBS_None, // VCMPEQUH = 1777 | |
| CEFBS_None, // VCMPEQUH_rec = 1778 | |
| CEFBS_None, // VCMPEQUW = 1779 | |
| CEFBS_None, // VCMPEQUW_rec = 1780 | |
| CEFBS_None, // VCMPGEFP = 1781 | |
| CEFBS_None, // VCMPGEFP_rec = 1782 | |
| CEFBS_None, // VCMPGTFP = 1783 | |
| CEFBS_None, // VCMPGTFP_rec = 1784 | |
| CEFBS_None, // VCMPGTSB = 1785 | |
| CEFBS_None, // VCMPGTSB_rec = 1786 | |
| CEFBS_None, // VCMPGTSD = 1787 | |
| CEFBS_None, // VCMPGTSD_rec = 1788 | |
| CEFBS_None, // VCMPGTSH = 1789 | |
| CEFBS_None, // VCMPGTSH_rec = 1790 | |
| CEFBS_None, // VCMPGTSW = 1791 | |
| CEFBS_None, // VCMPGTSW_rec = 1792 | |
| CEFBS_None, // VCMPGTUB = 1793 | |
| CEFBS_None, // VCMPGTUB_rec = 1794 | |
| CEFBS_None, // VCMPGTUD = 1795 | |
| CEFBS_None, // VCMPGTUD_rec = 1796 | |
| CEFBS_None, // VCMPGTUH = 1797 | |
| CEFBS_None, // VCMPGTUH_rec = 1798 | |
| CEFBS_None, // VCMPGTUW = 1799 | |
| CEFBS_None, // VCMPGTUW_rec = 1800 | |
| CEFBS_None, // VCMPNEB = 1801 | |
| CEFBS_None, // VCMPNEB_rec = 1802 | |
| CEFBS_None, // VCMPNEH = 1803 | |
| CEFBS_None, // VCMPNEH_rec = 1804 | |
| CEFBS_None, // VCMPNEW = 1805 | |
| CEFBS_None, // VCMPNEW_rec = 1806 | |
| CEFBS_None, // VCMPNEZB = 1807 | |
| CEFBS_None, // VCMPNEZB_rec = 1808 | |
| CEFBS_None, // VCMPNEZH = 1809 | |
| CEFBS_None, // VCMPNEZH_rec = 1810 | |
| CEFBS_None, // VCMPNEZW = 1811 | |
| CEFBS_None, // VCMPNEZW_rec = 1812 | |
| CEFBS_None, // VCTSXS = 1813 | |
| CEFBS_None, // VCTSXS_0 = 1814 | |
| CEFBS_None, // VCTUXS = 1815 | |
| CEFBS_None, // VCTUXS_0 = 1816 | |
| CEFBS_None, // VCTZB = 1817 | |
| CEFBS_None, // VCTZD = 1818 | |
| CEFBS_None, // VCTZH = 1819 | |
| CEFBS_None, // VCTZLSBB = 1820 | |
| CEFBS_None, // VCTZW = 1821 | |
| CEFBS_None, // VEQV = 1822 | |
| CEFBS_None, // VEXPTEFP = 1823 | |
| CEFBS_None, // VEXTRACTD = 1824 | |
| CEFBS_None, // VEXTRACTUB = 1825 | |
| CEFBS_None, // VEXTRACTUH = 1826 | |
| CEFBS_None, // VEXTRACTUW = 1827 | |
| CEFBS_None, // VEXTSB2D = 1828 | |
| CEFBS_None, // VEXTSB2Ds = 1829 | |
| CEFBS_None, // VEXTSB2W = 1830 | |
| CEFBS_None, // VEXTSB2Ws = 1831 | |
| CEFBS_None, // VEXTSH2D = 1832 | |
| CEFBS_None, // VEXTSH2Ds = 1833 | |
| CEFBS_None, // VEXTSH2W = 1834 | |
| CEFBS_None, // VEXTSH2Ws = 1835 | |
| CEFBS_None, // VEXTSW2D = 1836 | |
| CEFBS_None, // VEXTSW2Ds = 1837 | |
| CEFBS_None, // VEXTUBLX = 1838 | |
| CEFBS_None, // VEXTUBRX = 1839 | |
| CEFBS_None, // VEXTUHLX = 1840 | |
| CEFBS_None, // VEXTUHRX = 1841 | |
| CEFBS_None, // VEXTUWLX = 1842 | |
| CEFBS_None, // VEXTUWRX = 1843 | |
| CEFBS_None, // VGBBD = 1844 | |
| CEFBS_None, // VINSERTB = 1845 | |
| CEFBS_None, // VINSERTD = 1846 | |
| CEFBS_None, // VINSERTH = 1847 | |
| CEFBS_None, // VINSERTW = 1848 | |
| CEFBS_None, // VLOGEFP = 1849 | |
| CEFBS_None, // VMADDFP = 1850 | |
| CEFBS_None, // VMAXFP = 1851 | |
| CEFBS_None, // VMAXSB = 1852 | |
| CEFBS_None, // VMAXSD = 1853 | |
| CEFBS_None, // VMAXSH = 1854 | |
| CEFBS_None, // VMAXSW = 1855 | |
| CEFBS_None, // VMAXUB = 1856 | |
| CEFBS_None, // VMAXUD = 1857 | |
| CEFBS_None, // VMAXUH = 1858 | |
| CEFBS_None, // VMAXUW = 1859 | |
| CEFBS_None, // VMHADDSHS = 1860 | |
| CEFBS_None, // VMHRADDSHS = 1861 | |
| CEFBS_None, // VMINFP = 1862 | |
| CEFBS_None, // VMINSB = 1863 | |
| CEFBS_None, // VMINSD = 1864 | |
| CEFBS_None, // VMINSH = 1865 | |
| CEFBS_None, // VMINSW = 1866 | |
| CEFBS_None, // VMINUB = 1867 | |
| CEFBS_None, // VMINUD = 1868 | |
| CEFBS_None, // VMINUH = 1869 | |
| CEFBS_None, // VMINUW = 1870 | |
| CEFBS_None, // VMLADDUHM = 1871 | |
| CEFBS_None, // VMRGEW = 1872 | |
| CEFBS_None, // VMRGHB = 1873 | |
| CEFBS_None, // VMRGHH = 1874 | |
| CEFBS_None, // VMRGHW = 1875 | |
| CEFBS_None, // VMRGLB = 1876 | |
| CEFBS_None, // VMRGLH = 1877 | |
| CEFBS_None, // VMRGLW = 1878 | |
| CEFBS_None, // VMRGOW = 1879 | |
| CEFBS_None, // VMSUMMBM = 1880 | |
| CEFBS_None, // VMSUMSHM = 1881 | |
| CEFBS_None, // VMSUMSHS = 1882 | |
| CEFBS_None, // VMSUMUBM = 1883 | |
| CEFBS_None, // VMSUMUHM = 1884 | |
| CEFBS_None, // VMSUMUHS = 1885 | |
| CEFBS_None, // VMUL10CUQ = 1886 | |
| CEFBS_None, // VMUL10ECUQ = 1887 | |
| CEFBS_None, // VMUL10EUQ = 1888 | |
| CEFBS_None, // VMUL10UQ = 1889 | |
| CEFBS_None, // VMULESB = 1890 | |
| CEFBS_None, // VMULESH = 1891 | |
| CEFBS_None, // VMULESW = 1892 | |
| CEFBS_None, // VMULEUB = 1893 | |
| CEFBS_None, // VMULEUH = 1894 | |
| CEFBS_None, // VMULEUW = 1895 | |
| CEFBS_None, // VMULOSB = 1896 | |
| CEFBS_None, // VMULOSH = 1897 | |
| CEFBS_None, // VMULOSW = 1898 | |
| CEFBS_None, // VMULOUB = 1899 | |
| CEFBS_None, // VMULOUH = 1900 | |
| CEFBS_None, // VMULOUW = 1901 | |
| CEFBS_None, // VMULUWM = 1902 | |
| CEFBS_None, // VNAND = 1903 | |
| CEFBS_None, // VNCIPHER = 1904 | |
| CEFBS_None, // VNCIPHERLAST = 1905 | |
| CEFBS_None, // VNEGD = 1906 | |
| CEFBS_None, // VNEGW = 1907 | |
| CEFBS_None, // VNMSUBFP = 1908 | |
| CEFBS_None, // VNOR = 1909 | |
| CEFBS_None, // VOR = 1910 | |
| CEFBS_None, // VORC = 1911 | |
| CEFBS_None, // VPERM = 1912 | |
| CEFBS_None, // VPERMR = 1913 | |
| CEFBS_None, // VPERMXOR = 1914 | |
| CEFBS_None, // VPKPX = 1915 | |
| CEFBS_None, // VPKSDSS = 1916 | |
| CEFBS_None, // VPKSDUS = 1917 | |
| CEFBS_None, // VPKSHSS = 1918 | |
| CEFBS_None, // VPKSHUS = 1919 | |
| CEFBS_None, // VPKSWSS = 1920 | |
| CEFBS_None, // VPKSWUS = 1921 | |
| CEFBS_None, // VPKUDUM = 1922 | |
| CEFBS_None, // VPKUDUS = 1923 | |
| CEFBS_None, // VPKUHUM = 1924 | |
| CEFBS_None, // VPKUHUS = 1925 | |
| CEFBS_None, // VPKUWUM = 1926 | |
| CEFBS_None, // VPKUWUS = 1927 | |
| CEFBS_None, // VPMSUMB = 1928 | |
| CEFBS_None, // VPMSUMD = 1929 | |
| CEFBS_None, // VPMSUMH = 1930 | |
| CEFBS_None, // VPMSUMW = 1931 | |
| CEFBS_None, // VPOPCNTB = 1932 | |
| CEFBS_None, // VPOPCNTD = 1933 | |
| CEFBS_None, // VPOPCNTH = 1934 | |
| CEFBS_None, // VPOPCNTW = 1935 | |
| CEFBS_None, // VPRTYBD = 1936 | |
| CEFBS_None, // VPRTYBQ = 1937 | |
| CEFBS_None, // VPRTYBW = 1938 | |
| CEFBS_None, // VREFP = 1939 | |
| CEFBS_None, // VRFIM = 1940 | |
| CEFBS_None, // VRFIN = 1941 | |
| CEFBS_None, // VRFIP = 1942 | |
| CEFBS_None, // VRFIZ = 1943 | |
| CEFBS_None, // VRLB = 1944 | |
| CEFBS_None, // VRLD = 1945 | |
| CEFBS_None, // VRLDMI = 1946 | |
| CEFBS_None, // VRLDNM = 1947 | |
| CEFBS_None, // VRLH = 1948 | |
| CEFBS_None, // VRLW = 1949 | |
| CEFBS_None, // VRLWMI = 1950 | |
| CEFBS_None, // VRLWNM = 1951 | |
| CEFBS_None, // VRSQRTEFP = 1952 | |
| CEFBS_None, // VSBOX = 1953 | |
| CEFBS_None, // VSEL = 1954 | |
| CEFBS_None, // VSHASIGMAD = 1955 | |
| CEFBS_None, // VSHASIGMAW = 1956 | |
| CEFBS_None, // VSL = 1957 | |
| CEFBS_None, // VSLB = 1958 | |
| CEFBS_None, // VSLD = 1959 | |
| CEFBS_None, // VSLDOI = 1960 | |
| CEFBS_None, // VSLH = 1961 | |
| CEFBS_None, // VSLO = 1962 | |
| CEFBS_None, // VSLV = 1963 | |
| CEFBS_None, // VSLW = 1964 | |
| CEFBS_None, // VSPLTB = 1965 | |
| CEFBS_None, // VSPLTBs = 1966 | |
| CEFBS_None, // VSPLTH = 1967 | |
| CEFBS_None, // VSPLTHs = 1968 | |
| CEFBS_None, // VSPLTISB = 1969 | |
| CEFBS_None, // VSPLTISH = 1970 | |
| CEFBS_None, // VSPLTISW = 1971 | |
| CEFBS_None, // VSPLTW = 1972 | |
| CEFBS_None, // VSR = 1973 | |
| CEFBS_None, // VSRAB = 1974 | |
| CEFBS_None, // VSRAD = 1975 | |
| CEFBS_None, // VSRAH = 1976 | |
| CEFBS_None, // VSRAW = 1977 | |
| CEFBS_None, // VSRB = 1978 | |
| CEFBS_None, // VSRD = 1979 | |
| CEFBS_None, // VSRH = 1980 | |
| CEFBS_None, // VSRO = 1981 | |
| CEFBS_None, // VSRV = 1982 | |
| CEFBS_None, // VSRW = 1983 | |
| CEFBS_None, // VSUBCUQ = 1984 | |
| CEFBS_None, // VSUBCUW = 1985 | |
| CEFBS_None, // VSUBECUQ = 1986 | |
| CEFBS_None, // VSUBEUQM = 1987 | |
| CEFBS_None, // VSUBFP = 1988 | |
| CEFBS_None, // VSUBSBS = 1989 | |
| CEFBS_None, // VSUBSHS = 1990 | |
| CEFBS_None, // VSUBSWS = 1991 | |
| CEFBS_None, // VSUBUBM = 1992 | |
| CEFBS_None, // VSUBUBS = 1993 | |
| CEFBS_None, // VSUBUDM = 1994 | |
| CEFBS_None, // VSUBUHM = 1995 | |
| CEFBS_None, // VSUBUHS = 1996 | |
| CEFBS_None, // VSUBUQM = 1997 | |
| CEFBS_None, // VSUBUWM = 1998 | |
| CEFBS_None, // VSUBUWS = 1999 | |
| CEFBS_None, // VSUM2SWS = 2000 | |
| CEFBS_None, // VSUM4SBS = 2001 | |
| CEFBS_None, // VSUM4SHS = 2002 | |
| CEFBS_None, // VSUM4UBS = 2003 | |
| CEFBS_None, // VSUMSWS = 2004 | |
| CEFBS_None, // VUPKHPX = 2005 | |
| CEFBS_None, // VUPKHSB = 2006 | |
| CEFBS_None, // VUPKHSH = 2007 | |
| CEFBS_None, // VUPKHSW = 2008 | |
| CEFBS_None, // VUPKLPX = 2009 | |
| CEFBS_None, // VUPKLSB = 2010 | |
| CEFBS_None, // VUPKLSH = 2011 | |
| CEFBS_None, // VUPKLSW = 2012 | |
| CEFBS_None, // VXOR = 2013 | |
| CEFBS_None, // V_SET0 = 2014 | |
| CEFBS_None, // V_SET0B = 2015 | |
| CEFBS_None, // V_SET0H = 2016 | |
| CEFBS_None, // V_SETALLONES = 2017 | |
| CEFBS_None, // V_SETALLONESB = 2018 | |
| CEFBS_None, // V_SETALLONESH = 2019 | |
| CEFBS_None, // WAIT = 2020 | |
| CEFBS_None, // WRTEE = 2021 | |
| CEFBS_None, // WRTEEI = 2022 | |
| CEFBS_None, // XOR = 2023 | |
| CEFBS_None, // XOR8 = 2024 | |
| CEFBS_None, // XOR8_rec = 2025 | |
| CEFBS_None, // XORI = 2026 | |
| CEFBS_None, // XORI8 = 2027 | |
| CEFBS_None, // XORIS = 2028 | |
| CEFBS_None, // XORIS8 = 2029 | |
| CEFBS_None, // XOR_rec = 2030 | |
| CEFBS_None, // XSABSDP = 2031 | |
| CEFBS_None, // XSABSQP = 2032 | |
| CEFBS_None, // XSADDDP = 2033 | |
| CEFBS_None, // XSADDQP = 2034 | |
| CEFBS_None, // XSADDQPO = 2035 | |
| CEFBS_None, // XSADDSP = 2036 | |
| CEFBS_None, // XSCMPEQDP = 2037 | |
| CEFBS_None, // XSCMPEXPDP = 2038 | |
| CEFBS_None, // XSCMPEXPQP = 2039 | |
| CEFBS_None, // XSCMPGEDP = 2040 | |
| CEFBS_None, // XSCMPGTDP = 2041 | |
| CEFBS_None, // XSCMPODP = 2042 | |
| CEFBS_None, // XSCMPOQP = 2043 | |
| CEFBS_None, // XSCMPUDP = 2044 | |
| CEFBS_None, // XSCMPUQP = 2045 | |
| CEFBS_None, // XSCPSGNDP = 2046 | |
| CEFBS_None, // XSCPSGNQP = 2047 | |
| CEFBS_None, // XSCVDPHP = 2048 | |
| CEFBS_None, // XSCVDPQP = 2049 | |
| CEFBS_None, // XSCVDPSP = 2050 | |
| CEFBS_None, // XSCVDPSPN = 2051 | |
| CEFBS_None, // XSCVDPSXDS = 2052 | |
| CEFBS_None, // XSCVDPSXDSs = 2053 | |
| CEFBS_None, // XSCVDPSXWS = 2054 | |
| CEFBS_None, // XSCVDPSXWSs = 2055 | |
| CEFBS_None, // XSCVDPUXDS = 2056 | |
| CEFBS_None, // XSCVDPUXDSs = 2057 | |
| CEFBS_None, // XSCVDPUXWS = 2058 | |
| CEFBS_None, // XSCVDPUXWSs = 2059 | |
| CEFBS_None, // XSCVHPDP = 2060 | |
| CEFBS_None, // XSCVQPDP = 2061 | |
| CEFBS_None, // XSCVQPDPO = 2062 | |
| CEFBS_None, // XSCVQPSDZ = 2063 | |
| CEFBS_None, // XSCVQPSWZ = 2064 | |
| CEFBS_None, // XSCVQPUDZ = 2065 | |
| CEFBS_None, // XSCVQPUWZ = 2066 | |
| CEFBS_None, // XSCVSDQP = 2067 | |
| CEFBS_None, // XSCVSPDP = 2068 | |
| CEFBS_None, // XSCVSPDPN = 2069 | |
| CEFBS_None, // XSCVSXDDP = 2070 | |
| CEFBS_None, // XSCVSXDSP = 2071 | |
| CEFBS_None, // XSCVUDQP = 2072 | |
| CEFBS_None, // XSCVUXDDP = 2073 | |
| CEFBS_None, // XSCVUXDSP = 2074 | |
| CEFBS_None, // XSDIVDP = 2075 | |
| CEFBS_None, // XSDIVQP = 2076 | |
| CEFBS_None, // XSDIVQPO = 2077 | |
| CEFBS_None, // XSDIVSP = 2078 | |
| CEFBS_None, // XSIEXPDP = 2079 | |
| CEFBS_None, // XSIEXPQP = 2080 | |
| CEFBS_None, // XSMADDADP = 2081 | |
| CEFBS_None, // XSMADDASP = 2082 | |
| CEFBS_None, // XSMADDMDP = 2083 | |
| CEFBS_None, // XSMADDMSP = 2084 | |
| CEFBS_None, // XSMADDQP = 2085 | |
| CEFBS_None, // XSMADDQPO = 2086 | |
| CEFBS_None, // XSMAXCDP = 2087 | |
| CEFBS_None, // XSMAXDP = 2088 | |
| CEFBS_None, // XSMAXJDP = 2089 | |
| CEFBS_None, // XSMINCDP = 2090 | |
| CEFBS_None, // XSMINDP = 2091 | |
| CEFBS_None, // XSMINJDP = 2092 | |
| CEFBS_None, // XSMSUBADP = 2093 | |
| CEFBS_None, // XSMSUBASP = 2094 | |
| CEFBS_None, // XSMSUBMDP = 2095 | |
| CEFBS_None, // XSMSUBMSP = 2096 | |
| CEFBS_None, // XSMSUBQP = 2097 | |
| CEFBS_None, // XSMSUBQPO = 2098 | |
| CEFBS_None, // XSMULDP = 2099 | |
| CEFBS_None, // XSMULQP = 2100 | |
| CEFBS_None, // XSMULQPO = 2101 | |
| CEFBS_None, // XSMULSP = 2102 | |
| CEFBS_None, // XSNABSDP = 2103 | |
| CEFBS_None, // XSNABSQP = 2104 | |
| CEFBS_None, // XSNEGDP = 2105 | |
| CEFBS_None, // XSNEGQP = 2106 | |
| CEFBS_None, // XSNMADDADP = 2107 | |
| CEFBS_None, // XSNMADDASP = 2108 | |
| CEFBS_None, // XSNMADDMDP = 2109 | |
| CEFBS_None, // XSNMADDMSP = 2110 | |
| CEFBS_None, // XSNMADDQP = 2111 | |
| CEFBS_None, // XSNMADDQPO = 2112 | |
| CEFBS_None, // XSNMSUBADP = 2113 | |
| CEFBS_None, // XSNMSUBASP = 2114 | |
| CEFBS_None, // XSNMSUBMDP = 2115 | |
| CEFBS_None, // XSNMSUBMSP = 2116 | |
| CEFBS_None, // XSNMSUBQP = 2117 | |
| CEFBS_None, // XSNMSUBQPO = 2118 | |
| CEFBS_None, // XSRDPI = 2119 | |
| CEFBS_None, // XSRDPIC = 2120 | |
| CEFBS_None, // XSRDPIM = 2121 | |
| CEFBS_None, // XSRDPIP = 2122 | |
| CEFBS_None, // XSRDPIZ = 2123 | |
| CEFBS_None, // XSREDP = 2124 | |
| CEFBS_None, // XSRESP = 2125 | |
| CEFBS_None, // XSRQPI = 2126 | |
| CEFBS_None, // XSRQPIX = 2127 | |
| CEFBS_None, // XSRQPXP = 2128 | |
| CEFBS_None, // XSRSP = 2129 | |
| CEFBS_None, // XSRSQRTEDP = 2130 | |
| CEFBS_None, // XSRSQRTESP = 2131 | |
| CEFBS_None, // XSSQRTDP = 2132 | |
| CEFBS_None, // XSSQRTQP = 2133 | |
| CEFBS_None, // XSSQRTQPO = 2134 | |
| CEFBS_None, // XSSQRTSP = 2135 | |
| CEFBS_None, // XSSUBDP = 2136 | |
| CEFBS_None, // XSSUBQP = 2137 | |
| CEFBS_None, // XSSUBQPO = 2138 | |
| CEFBS_None, // XSSUBSP = 2139 | |
| CEFBS_None, // XSTDIVDP = 2140 | |
| CEFBS_None, // XSTSQRTDP = 2141 | |
| CEFBS_None, // XSTSTDCDP = 2142 | |
| CEFBS_None, // XSTSTDCQP = 2143 | |
| CEFBS_None, // XSTSTDCSP = 2144 | |
| CEFBS_None, // XSXEXPDP = 2145 | |
| CEFBS_None, // XSXEXPQP = 2146 | |
| CEFBS_None, // XSXSIGDP = 2147 | |
| CEFBS_None, // XSXSIGQP = 2148 | |
| CEFBS_None, // XVABSDP = 2149 | |
| CEFBS_None, // XVABSSP = 2150 | |
| CEFBS_None, // XVADDDP = 2151 | |
| CEFBS_None, // XVADDSP = 2152 | |
| CEFBS_None, // XVCMPEQDP = 2153 | |
| CEFBS_None, // XVCMPEQDP_rec = 2154 | |
| CEFBS_None, // XVCMPEQSP = 2155 | |
| CEFBS_None, // XVCMPEQSP_rec = 2156 | |
| CEFBS_None, // XVCMPGEDP = 2157 | |
| CEFBS_None, // XVCMPGEDP_rec = 2158 | |
| CEFBS_None, // XVCMPGESP = 2159 | |
| CEFBS_None, // XVCMPGESP_rec = 2160 | |
| CEFBS_None, // XVCMPGTDP = 2161 | |
| CEFBS_None, // XVCMPGTDP_rec = 2162 | |
| CEFBS_None, // XVCMPGTSP = 2163 | |
| CEFBS_None, // XVCMPGTSP_rec = 2164 | |
| CEFBS_None, // XVCPSGNDP = 2165 | |
| CEFBS_None, // XVCPSGNSP = 2166 | |
| CEFBS_None, // XVCVDPSP = 2167 | |
| CEFBS_None, // XVCVDPSXDS = 2168 | |
| CEFBS_None, // XVCVDPSXWS = 2169 | |
| CEFBS_None, // XVCVDPUXDS = 2170 | |
| CEFBS_None, // XVCVDPUXWS = 2171 | |
| CEFBS_None, // XVCVHPSP = 2172 | |
| CEFBS_None, // XVCVSPDP = 2173 | |
| CEFBS_None, // XVCVSPHP = 2174 | |
| CEFBS_None, // XVCVSPSXDS = 2175 | |
| CEFBS_None, // XVCVSPSXWS = 2176 | |
| CEFBS_None, // XVCVSPUXDS = 2177 | |
| CEFBS_None, // XVCVSPUXWS = 2178 | |
| CEFBS_None, // XVCVSXDDP = 2179 | |
| CEFBS_None, // XVCVSXDSP = 2180 | |
| CEFBS_None, // XVCVSXWDP = 2181 | |
| CEFBS_None, // XVCVSXWSP = 2182 | |
| CEFBS_None, // XVCVUXDDP = 2183 | |
| CEFBS_None, // XVCVUXDSP = 2184 | |
| CEFBS_None, // XVCVUXWDP = 2185 | |
| CEFBS_None, // XVCVUXWSP = 2186 | |
| CEFBS_None, // XVDIVDP = 2187 | |
| CEFBS_None, // XVDIVSP = 2188 | |
| CEFBS_None, // XVIEXPDP = 2189 | |
| CEFBS_None, // XVIEXPSP = 2190 | |
| CEFBS_None, // XVMADDADP = 2191 | |
| CEFBS_None, // XVMADDASP = 2192 | |
| CEFBS_None, // XVMADDMDP = 2193 | |
| CEFBS_None, // XVMADDMSP = 2194 | |
| CEFBS_None, // XVMAXDP = 2195 | |
| CEFBS_None, // XVMAXSP = 2196 | |
| CEFBS_None, // XVMINDP = 2197 | |
| CEFBS_None, // XVMINSP = 2198 | |
| CEFBS_None, // XVMSUBADP = 2199 | |
| CEFBS_None, // XVMSUBASP = 2200 | |
| CEFBS_None, // XVMSUBMDP = 2201 | |
| CEFBS_None, // XVMSUBMSP = 2202 | |
| CEFBS_None, // XVMULDP = 2203 | |
| CEFBS_None, // XVMULSP = 2204 | |
| CEFBS_None, // XVNABSDP = 2205 | |
| CEFBS_None, // XVNABSSP = 2206 | |
| CEFBS_None, // XVNEGDP = 2207 | |
| CEFBS_None, // XVNEGSP = 2208 | |
| CEFBS_None, // XVNMADDADP = 2209 | |
| CEFBS_None, // XVNMADDASP = 2210 | |
| CEFBS_None, // XVNMADDMDP = 2211 | |
| CEFBS_None, // XVNMADDMSP = 2212 | |
| CEFBS_None, // XVNMSUBADP = 2213 | |
| CEFBS_None, // XVNMSUBASP = 2214 | |
| CEFBS_None, // XVNMSUBMDP = 2215 | |
| CEFBS_None, // XVNMSUBMSP = 2216 | |
| CEFBS_None, // XVRDPI = 2217 | |
| CEFBS_None, // XVRDPIC = 2218 | |
| CEFBS_None, // XVRDPIM = 2219 | |
| CEFBS_None, // XVRDPIP = 2220 | |
| CEFBS_None, // XVRDPIZ = 2221 | |
| CEFBS_None, // XVREDP = 2222 | |
| CEFBS_None, // XVRESP = 2223 | |
| CEFBS_None, // XVRSPI = 2224 | |
| CEFBS_None, // XVRSPIC = 2225 | |
| CEFBS_None, // XVRSPIM = 2226 | |
| CEFBS_None, // XVRSPIP = 2227 | |
| CEFBS_None, // XVRSPIZ = 2228 | |
| CEFBS_None, // XVRSQRTEDP = 2229 | |
| CEFBS_None, // XVRSQRTESP = 2230 | |
| CEFBS_None, // XVSQRTDP = 2231 | |
| CEFBS_None, // XVSQRTSP = 2232 | |
| CEFBS_None, // XVSUBDP = 2233 | |
| CEFBS_None, // XVSUBSP = 2234 | |
| CEFBS_None, // XVTDIVDP = 2235 | |
| CEFBS_None, // XVTDIVSP = 2236 | |
| CEFBS_None, // XVTSQRTDP = 2237 | |
| CEFBS_None, // XVTSQRTSP = 2238 | |
| CEFBS_None, // XVTSTDCDP = 2239 | |
| CEFBS_None, // XVTSTDCSP = 2240 | |
| CEFBS_None, // XVXEXPDP = 2241 | |
| CEFBS_None, // XVXEXPSP = 2242 | |
| CEFBS_None, // XVXSIGDP = 2243 | |
| CEFBS_None, // XVXSIGSP = 2244 | |
| CEFBS_None, // XXBRD = 2245 | |
| CEFBS_None, // XXBRH = 2246 | |
| CEFBS_None, // XXBRQ = 2247 | |
| CEFBS_None, // XXBRW = 2248 | |
| CEFBS_None, // XXEXTRACTUW = 2249 | |
| CEFBS_None, // XXINSERTW = 2250 | |
| CEFBS_None, // XXLAND = 2251 | |
| CEFBS_None, // XXLANDC = 2252 | |
| CEFBS_None, // XXLEQV = 2253 | |
| CEFBS_None, // XXLEQVOnes = 2254 | |
| CEFBS_None, // XXLNAND = 2255 | |
| CEFBS_None, // XXLNOR = 2256 | |
| CEFBS_None, // XXLOR = 2257 | |
| CEFBS_None, // XXLORC = 2258 | |
| CEFBS_None, // XXLORf = 2259 | |
| CEFBS_None, // XXLXOR = 2260 | |
| CEFBS_None, // XXLXORdpz = 2261 | |
| CEFBS_None, // XXLXORspz = 2262 | |
| CEFBS_None, // XXLXORz = 2263 | |
| CEFBS_None, // XXMRGHW = 2264 | |
| CEFBS_None, // XXMRGLW = 2265 | |
| CEFBS_None, // XXPERM = 2266 | |
| CEFBS_None, // XXPERMDI = 2267 | |
| CEFBS_None, // XXPERMDIs = 2268 | |
| CEFBS_None, // XXPERMR = 2269 | |
| CEFBS_None, // XXSEL = 2270 | |
| CEFBS_None, // XXSLDWI = 2271 | |
| CEFBS_None, // XXSLDWIs = 2272 | |
| CEFBS_None, // XXSPLTIB = 2273 | |
| CEFBS_None, // XXSPLTW = 2274 | |
| CEFBS_None, // XXSPLTWs = 2275 | |
| CEFBS_None, // gBC = 2276 | |
| CEFBS_None, // gBCA = 2277 | |
| CEFBS_None, // gBCAat = 2278 | |
| CEFBS_None, // gBCCTR = 2279 | |
| CEFBS_None, // gBCCTRL = 2280 | |
| CEFBS_None, // gBCL = 2281 | |
| CEFBS_None, // gBCLA = 2282 | |
| CEFBS_None, // gBCLAat = 2283 | |
| CEFBS_None, // gBCLR = 2284 | |
| CEFBS_None, // gBCLRL = 2285 | |
| CEFBS_None, // gBCLat = 2286 | |
| CEFBS_None, // gBCat = 2287 | |
| }; | |
| assert(Inst.getOpcode() < 2288); | |
| const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Inst.getOpcode()]]; | |
| FeatureBitset MissingFeatures = | |
| (AvailableFeatures & RequiredFeatures) ^ | |
| RequiredFeatures; | |
| if (MissingFeatures.any()) { | |
| std::ostringstream Msg; | |
| Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str() | |
| << " instruction but the "; | |
| for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) | |
| if (MissingFeatures.test(i)) | |
| Msg << SubtargetFeatureNames[i] << " "; | |
| Msg << "predicate(s) are not met"; | |
| report_fatal_error(Msg.str()); | |
| } | |
| #else | |
| // Silence unused variable warning on targets that don't use MCII for other purposes (e.g. BPF). | |
| (void)MCII; | |
| #endif // NDEBUG | |
| } | |
| #endif |