| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ | |
| |* *| | |
| |* Target Instruction Enum Values and Descriptors *| | |
| |* *| | |
| |* Automatically generated file, do not edit! *| | |
| |* *| | |
| \*===----------------------------------------------------------------------===*/ | |
| #ifdef GET_INSTRINFO_ENUM | |
| #undef GET_INSTRINFO_ENUM | |
| namespace llvm { | |
| namespace PPC { | |
| enum { | |
| PHI = 0, | |
| INLINEASM = 1, | |
| INLINEASM_BR = 2, | |
| CFI_INSTRUCTION = 3, | |
| EH_LABEL = 4, | |
| GC_LABEL = 5, | |
| ANNOTATION_LABEL = 6, | |
| KILL = 7, | |
| EXTRACT_SUBREG = 8, | |
| INSERT_SUBREG = 9, | |
| IMPLICIT_DEF = 10, | |
| SUBREG_TO_REG = 11, | |
| COPY_TO_REGCLASS = 12, | |
| DBG_VALUE = 13, | |
| DBG_LABEL = 14, | |
| REG_SEQUENCE = 15, | |
| COPY = 16, | |
| BUNDLE = 17, | |
| LIFETIME_START = 18, | |
| LIFETIME_END = 19, | |
| STACKMAP = 20, | |
| FENTRY_CALL = 21, | |
| PATCHPOINT = 22, | |
| LOAD_STACK_GUARD = 23, | |
| STATEPOINT = 24, | |
| LOCAL_ESCAPE = 25, | |
| FAULTING_OP = 26, | |
| PATCHABLE_OP = 27, | |
| PATCHABLE_FUNCTION_ENTER = 28, | |
| PATCHABLE_RET = 29, | |
| PATCHABLE_FUNCTION_EXIT = 30, | |
| PATCHABLE_TAIL_CALL = 31, | |
| PATCHABLE_EVENT_CALL = 32, | |
| PATCHABLE_TYPED_EVENT_CALL = 33, | |
| ICALL_BRANCH_FUNNEL = 34, | |
| G_ADD = 35, | |
| G_SUB = 36, | |
| G_MUL = 37, | |
| G_SDIV = 38, | |
| G_UDIV = 39, | |
| G_SREM = 40, | |
| G_UREM = 41, | |
| G_AND = 42, | |
| G_OR = 43, | |
| G_XOR = 44, | |
| G_IMPLICIT_DEF = 45, | |
| G_PHI = 46, | |
| G_FRAME_INDEX = 47, | |
| G_GLOBAL_VALUE = 48, | |
| G_EXTRACT = 49, | |
| G_UNMERGE_VALUES = 50, | |
| G_INSERT = 51, | |
| G_MERGE_VALUES = 52, | |
| G_BUILD_VECTOR = 53, | |
| G_BUILD_VECTOR_TRUNC = 54, | |
| G_CONCAT_VECTORS = 55, | |
| G_PTRTOINT = 56, | |
| G_INTTOPTR = 57, | |
| G_BITCAST = 58, | |
| G_INTRINSIC_TRUNC = 59, | |
| G_INTRINSIC_ROUND = 60, | |
| G_READCYCLECOUNTER = 61, | |
| G_LOAD = 62, | |
| G_SEXTLOAD = 63, | |
| G_ZEXTLOAD = 64, | |
| G_INDEXED_LOAD = 65, | |
| G_INDEXED_SEXTLOAD = 66, | |
| G_INDEXED_ZEXTLOAD = 67, | |
| G_STORE = 68, | |
| G_INDEXED_STORE = 69, | |
| G_ATOMIC_CMPXCHG_WITH_SUCCESS = 70, | |
| G_ATOMIC_CMPXCHG = 71, | |
| G_ATOMICRMW_XCHG = 72, | |
| G_ATOMICRMW_ADD = 73, | |
| G_ATOMICRMW_SUB = 74, | |
| G_ATOMICRMW_AND = 75, | |
| G_ATOMICRMW_NAND = 76, | |
| G_ATOMICRMW_OR = 77, | |
| G_ATOMICRMW_XOR = 78, | |
| G_ATOMICRMW_MAX = 79, | |
| G_ATOMICRMW_MIN = 80, | |
| G_ATOMICRMW_UMAX = 81, | |
| G_ATOMICRMW_UMIN = 82, | |
| G_ATOMICRMW_FADD = 83, | |
| G_ATOMICRMW_FSUB = 84, | |
| G_FENCE = 85, | |
| G_BRCOND = 86, | |
| G_BRINDIRECT = 87, | |
| G_INTRINSIC = 88, | |
| G_INTRINSIC_W_SIDE_EFFECTS = 89, | |
| G_ANYEXT = 90, | |
| G_TRUNC = 91, | |
| G_CONSTANT = 92, | |
| G_FCONSTANT = 93, | |
| G_VASTART = 94, | |
| G_VAARG = 95, | |
| G_SEXT = 96, | |
| G_SEXT_INREG = 97, | |
| G_ZEXT = 98, | |
| G_SHL = 99, | |
| G_LSHR = 100, | |
| G_ASHR = 101, | |
| G_ICMP = 102, | |
| G_FCMP = 103, | |
| G_SELECT = 104, | |
| G_UADDO = 105, | |
| G_UADDE = 106, | |
| G_USUBO = 107, | |
| G_USUBE = 108, | |
| G_SADDO = 109, | |
| G_SADDE = 110, | |
| G_SSUBO = 111, | |
| G_SSUBE = 112, | |
| G_UMULO = 113, | |
| G_SMULO = 114, | |
| G_UMULH = 115, | |
| G_SMULH = 116, | |
| G_FADD = 117, | |
| G_FSUB = 118, | |
| G_FMUL = 119, | |
| G_FMA = 120, | |
| G_FMAD = 121, | |
| G_FDIV = 122, | |
| G_FREM = 123, | |
| G_FPOW = 124, | |
| G_FEXP = 125, | |
| G_FEXP2 = 126, | |
| G_FLOG = 127, | |
| G_FLOG2 = 128, | |
| G_FLOG10 = 129, | |
| G_FNEG = 130, | |
| G_FPEXT = 131, | |
| G_FPTRUNC = 132, | |
| G_FPTOSI = 133, | |
| G_FPTOUI = 134, | |
| G_SITOFP = 135, | |
| G_UITOFP = 136, | |
| G_FABS = 137, | |
| G_FCOPYSIGN = 138, | |
| G_FCANONICALIZE = 139, | |
| G_FMINNUM = 140, | |
| G_FMAXNUM = 141, | |
| G_FMINNUM_IEEE = 142, | |
| G_FMAXNUM_IEEE = 143, | |
| G_FMINIMUM = 144, | |
| G_FMAXIMUM = 145, | |
| G_PTR_ADD = 146, | |
| G_PTR_MASK = 147, | |
| G_SMIN = 148, | |
| G_SMAX = 149, | |
| G_UMIN = 150, | |
| G_UMAX = 151, | |
| G_BR = 152, | |
| G_BRJT = 153, | |
| G_INSERT_VECTOR_ELT = 154, | |
| G_EXTRACT_VECTOR_ELT = 155, | |
| G_SHUFFLE_VECTOR = 156, | |
| G_CTTZ = 157, | |
| G_CTTZ_ZERO_UNDEF = 158, | |
| G_CTLZ = 159, | |
| G_CTLZ_ZERO_UNDEF = 160, | |
| G_CTPOP = 161, | |
| G_BSWAP = 162, | |
| G_BITREVERSE = 163, | |
| G_FCEIL = 164, | |
| G_FCOS = 165, | |
| G_FSIN = 166, | |
| G_FSQRT = 167, | |
| G_FFLOOR = 168, | |
| G_FRINT = 169, | |
| G_FNEARBYINT = 170, | |
| G_ADDRSPACE_CAST = 171, | |
| G_BLOCK_ADDR = 172, | |
| G_JUMP_TABLE = 173, | |
| G_DYN_STACKALLOC = 174, | |
| G_READ_REGISTER = 175, | |
| G_WRITE_REGISTER = 176, | |
| CFENCE8 = 177, | |
| CLRLSLDI = 178, | |
| CLRLSLDI_rec = 179, | |
| CLRLSLWI = 180, | |
| CLRLSLWI_rec = 181, | |
| CLRRDI = 182, | |
| CLRRDI_rec = 183, | |
| CLRRWI = 184, | |
| CLRRWI_rec = 185, | |
| CP_COPY_FIRST = 186, | |
| CP_COPYx = 187, | |
| CP_PASTE_LAST = 188, | |
| CP_PASTEx = 189, | |
| DCBFL = 190, | |
| DCBFLP = 191, | |
| DCBFx = 192, | |
| DCBTCT = 193, | |
| DCBTDS = 194, | |
| DCBTSTCT = 195, | |
| DCBTSTDS = 196, | |
| DCBTSTT = 197, | |
| DCBTSTx = 198, | |
| DCBTT = 199, | |
| DCBTx = 200, | |
| DFLOADf32 = 201, | |
| DFLOADf64 = 202, | |
| DFSTOREf32 = 203, | |
| DFSTOREf64 = 204, | |
| EXTLDI = 205, | |
| EXTLDI_rec = 206, | |
| EXTLWI = 207, | |
| EXTLWI_rec = 208, | |
| EXTRDI = 209, | |
| EXTRDI_rec = 210, | |
| EXTRWI = 211, | |
| EXTRWI_rec = 212, | |
| INSLWI = 213, | |
| INSLWI_rec = 214, | |
| INSRDI = 215, | |
| INSRDI_rec = 216, | |
| INSRWI = 217, | |
| INSRWI_rec = 218, | |
| LAx = 219, | |
| LIWAX = 220, | |
| LIWZX = 221, | |
| RLWIMIbm = 222, | |
| RLWIMIbm_rec = 223, | |
| RLWINMbm = 224, | |
| RLWINMbm_rec = 225, | |
| RLWNMbm = 226, | |
| RLWNMbm_rec = 227, | |
| ROTRDI = 228, | |
| ROTRDI_rec = 229, | |
| ROTRWI = 230, | |
| ROTRWI_rec = 231, | |
| SLDI = 232, | |
| SLDI_rec = 233, | |
| SLWI = 234, | |
| SLWI_rec = 235, | |
| SPILLTOVSR_LD = 236, | |
| SPILLTOVSR_LDX = 237, | |
| SPILLTOVSR_ST = 238, | |
| SPILLTOVSR_STX = 239, | |
| SRDI = 240, | |
| SRDI_rec = 241, | |
| SRWI = 242, | |
| SRWI_rec = 243, | |
| STIWX = 244, | |
| SUBI = 245, | |
| SUBIC = 246, | |
| SUBIC_rec = 247, | |
| SUBIS = 248, | |
| SUBPCIS = 249, | |
| XFLOADf32 = 250, | |
| XFLOADf64 = 251, | |
| XFSTOREf32 = 252, | |
| XFSTOREf64 = 253, | |
| ADD4 = 254, | |
| ADD4O = 255, | |
| ADD4O_rec = 256, | |
| ADD4TLS = 257, | |
| ADD4_rec = 258, | |
| ADD8 = 259, | |
| ADD8O = 260, | |
| ADD8O_rec = 261, | |
| ADD8TLS = 262, | |
| ADD8TLS_ = 263, | |
| ADD8_rec = 264, | |
| ADDC = 265, | |
| ADDC8 = 266, | |
| ADDC8O = 267, | |
| ADDC8O_rec = 268, | |
| ADDC8_rec = 269, | |
| ADDCO = 270, | |
| ADDCO_rec = 271, | |
| ADDC_rec = 272, | |
| ADDE = 273, | |
| ADDE8 = 274, | |
| ADDE8O = 275, | |
| ADDE8O_rec = 276, | |
| ADDE8_rec = 277, | |
| ADDEO = 278, | |
| ADDEO_rec = 279, | |
| ADDE_rec = 280, | |
| ADDI = 281, | |
| ADDI8 = 282, | |
| ADDIC = 283, | |
| ADDIC8 = 284, | |
| ADDIC_rec = 285, | |
| ADDIS = 286, | |
| ADDIS8 = 287, | |
| ADDISdtprelHA = 288, | |
| ADDISdtprelHA32 = 289, | |
| ADDISgotTprelHA = 290, | |
| ADDIStlsgdHA = 291, | |
| ADDIStlsldHA = 292, | |
| ADDIStocHA = 293, | |
| ADDIStocHA8 = 294, | |
| ADDIdtprelL = 295, | |
| ADDIdtprelL32 = 296, | |
| ADDItlsgdL = 297, | |
| ADDItlsgdL32 = 298, | |
| ADDItlsgdLADDR = 299, | |
| ADDItlsgdLADDR32 = 300, | |
| ADDItlsldL = 301, | |
| ADDItlsldL32 = 302, | |
| ADDItlsldLADDR = 303, | |
| ADDItlsldLADDR32 = 304, | |
| ADDItocL = 305, | |
| ADDME = 306, | |
| ADDME8 = 307, | |
| ADDME8O = 308, | |
| ADDME8O_rec = 309, | |
| ADDME8_rec = 310, | |
| ADDMEO = 311, | |
| ADDMEO_rec = 312, | |
| ADDME_rec = 313, | |
| ADDPCIS = 314, | |
| ADDZE = 315, | |
| ADDZE8 = 316, | |
| ADDZE8O = 317, | |
| ADDZE8O_rec = 318, | |
| ADDZE8_rec = 319, | |
| ADDZEO = 320, | |
| ADDZEO_rec = 321, | |
| ADDZE_rec = 322, | |
| ADJCALLSTACKDOWN = 323, | |
| ADJCALLSTACKUP = 324, | |
| AND = 325, | |
| AND8 = 326, | |
| AND8_rec = 327, | |
| ANDC = 328, | |
| ANDC8 = 329, | |
| ANDC8_rec = 330, | |
| ANDC_rec = 331, | |
| ANDI8_rec = 332, | |
| ANDIS8_rec = 333, | |
| ANDIS_rec = 334, | |
| ANDI_rec = 335, | |
| ANDI_rec_1_EQ_BIT = 336, | |
| ANDI_rec_1_EQ_BIT8 = 337, | |
| ANDI_rec_1_GT_BIT = 338, | |
| ANDI_rec_1_GT_BIT8 = 339, | |
| AND_rec = 340, | |
| ATOMIC_CMP_SWAP_I16 = 341, | |
| ATOMIC_CMP_SWAP_I32 = 342, | |
| ATOMIC_CMP_SWAP_I64 = 343, | |
| ATOMIC_CMP_SWAP_I8 = 344, | |
| ATOMIC_LOAD_ADD_I16 = 345, | |
| ATOMIC_LOAD_ADD_I32 = 346, | |
| ATOMIC_LOAD_ADD_I64 = 347, | |
| ATOMIC_LOAD_ADD_I8 = 348, | |
| ATOMIC_LOAD_AND_I16 = 349, | |
| ATOMIC_LOAD_AND_I32 = 350, | |
| ATOMIC_LOAD_AND_I64 = 351, | |
| ATOMIC_LOAD_AND_I8 = 352, | |
| ATOMIC_LOAD_MAX_I16 = 353, | |
| ATOMIC_LOAD_MAX_I32 = 354, | |
| ATOMIC_LOAD_MAX_I64 = 355, | |
| ATOMIC_LOAD_MAX_I8 = 356, | |
| ATOMIC_LOAD_MIN_I16 = 357, | |
| ATOMIC_LOAD_MIN_I32 = 358, | |
| ATOMIC_LOAD_MIN_I64 = 359, | |
| ATOMIC_LOAD_MIN_I8 = 360, | |
| ATOMIC_LOAD_NAND_I16 = 361, | |
| ATOMIC_LOAD_NAND_I32 = 362, | |
| ATOMIC_LOAD_NAND_I64 = 363, | |
| ATOMIC_LOAD_NAND_I8 = 364, | |
| ATOMIC_LOAD_OR_I16 = 365, | |
| ATOMIC_LOAD_OR_I32 = 366, | |
| ATOMIC_LOAD_OR_I64 = 367, | |
| ATOMIC_LOAD_OR_I8 = 368, | |
| ATOMIC_LOAD_SUB_I16 = 369, | |
| ATOMIC_LOAD_SUB_I32 = 370, | |
| ATOMIC_LOAD_SUB_I64 = 371, | |
| ATOMIC_LOAD_SUB_I8 = 372, | |
| ATOMIC_LOAD_UMAX_I16 = 373, | |
| ATOMIC_LOAD_UMAX_I32 = 374, | |
| ATOMIC_LOAD_UMAX_I64 = 375, | |
| ATOMIC_LOAD_UMAX_I8 = 376, | |
| ATOMIC_LOAD_UMIN_I16 = 377, | |
| ATOMIC_LOAD_UMIN_I32 = 378, | |
| ATOMIC_LOAD_UMIN_I64 = 379, | |
| ATOMIC_LOAD_UMIN_I8 = 380, | |
| ATOMIC_LOAD_XOR_I16 = 381, | |
| ATOMIC_LOAD_XOR_I32 = 382, | |
| ATOMIC_LOAD_XOR_I64 = 383, | |
| ATOMIC_LOAD_XOR_I8 = 384, | |
| ATOMIC_SWAP_I16 = 385, | |
| ATOMIC_SWAP_I32 = 386, | |
| ATOMIC_SWAP_I64 = 387, | |
| ATOMIC_SWAP_I8 = 388, | |
| ATTN = 389, | |
| B = 390, | |
| BA = 391, | |
| BC = 392, | |
| BCC = 393, | |
| BCCA = 394, | |
| BCCCTR = 395, | |
| BCCCTR8 = 396, | |
| BCCCTRL = 397, | |
| BCCCTRL8 = 398, | |
| BCCL = 399, | |
| BCCLA = 400, | |
| BCCLR = 401, | |
| BCCLRL = 402, | |
| BCCTR = 403, | |
| BCCTR8 = 404, | |
| BCCTR8n = 405, | |
| BCCTRL = 406, | |
| BCCTRL8 = 407, | |
| BCCTRL8n = 408, | |
| BCCTRLn = 409, | |
| BCCTRn = 410, | |
| BCDCFN_rec = 411, | |
| BCDCFSQ_rec = 412, | |
| BCDCFZ_rec = 413, | |
| BCDCPSGN_rec = 414, | |
| BCDCTN_rec = 415, | |
| BCDCTSQ_rec = 416, | |
| BCDCTZ_rec = 417, | |
| BCDSETSGN_rec = 418, | |
| BCDSR_rec = 419, | |
| BCDS_rec = 420, | |
| BCDTRUNC_rec = 421, | |
| BCDUS_rec = 422, | |
| BCDUTRUNC_rec = 423, | |
| BCL = 424, | |
| BCLR = 425, | |
| BCLRL = 426, | |
| BCLRLn = 427, | |
| BCLRn = 428, | |
| BCLalways = 429, | |
| BCLn = 430, | |
| BCTR = 431, | |
| BCTR8 = 432, | |
| BCTRL = 433, | |
| BCTRL8 = 434, | |
| BCTRL8_LDinto_toc = 435, | |
| BCTRL_LWZinto_toc = 436, | |
| BCn = 437, | |
| BDNZ = 438, | |
| BDNZ8 = 439, | |
| BDNZA = 440, | |
| BDNZAm = 441, | |
| BDNZAp = 442, | |
| BDNZL = 443, | |
| BDNZLA = 444, | |
| BDNZLAm = 445, | |
| BDNZLAp = 446, | |
| BDNZLR = 447, | |
| BDNZLR8 = 448, | |
| BDNZLRL = 449, | |
| BDNZLRLm = 450, | |
| BDNZLRLp = 451, | |
| BDNZLRm = 452, | |
| BDNZLRp = 453, | |
| BDNZLm = 454, | |
| BDNZLp = 455, | |
| BDNZm = 456, | |
| BDNZp = 457, | |
| BDZ = 458, | |
| BDZ8 = 459, | |
| BDZA = 460, | |
| BDZAm = 461, | |
| BDZAp = 462, | |
| BDZL = 463, | |
| BDZLA = 464, | |
| BDZLAm = 465, | |
| BDZLAp = 466, | |
| BDZLR = 467, | |
| BDZLR8 = 468, | |
| BDZLRL = 469, | |
| BDZLRLm = 470, | |
| BDZLRLp = 471, | |
| BDZLRm = 472, | |
| BDZLRp = 473, | |
| BDZLm = 474, | |
| BDZLp = 475, | |
| BDZm = 476, | |
| BDZp = 477, | |
| BL = 478, | |
| BL8 = 479, | |
| BL8_NOP = 480, | |
| BL8_NOP_TLS = 481, | |
| BL8_TLS = 482, | |
| BL8_TLS_ = 483, | |
| BLA = 484, | |
| BLA8 = 485, | |
| BLA8_NOP = 486, | |
| BLR = 487, | |
| BLR8 = 488, | |
| BLRL = 489, | |
| BL_NOP = 490, | |
| BL_TLS = 491, | |
| BPERMD = 492, | |
| BRINC = 493, | |
| CLRBHRB = 494, | |
| CMPB = 495, | |
| CMPB8 = 496, | |
| CMPD = 497, | |
| CMPDI = 498, | |
| CMPEQB = 499, | |
| CMPLD = 500, | |
| CMPLDI = 501, | |
| CMPLW = 502, | |
| CMPLWI = 503, | |
| CMPRB = 504, | |
| CMPRB8 = 505, | |
| CMPW = 506, | |
| CMPWI = 507, | |
| CNTLZD = 508, | |
| CNTLZD_rec = 509, | |
| CNTLZW = 510, | |
| CNTLZW8 = 511, | |
| CNTLZW8_rec = 512, | |
| CNTLZW_rec = 513, | |
| CNTTZD = 514, | |
| CNTTZD_rec = 515, | |
| CNTTZW = 516, | |
| CNTTZW8 = 517, | |
| CNTTZW8_rec = 518, | |
| CNTTZW_rec = 519, | |
| CP_ABORT = 520, | |
| CP_COPY = 521, | |
| CP_COPY8 = 522, | |
| CP_PASTE = 523, | |
| CP_PASTE8 = 524, | |
| CP_PASTE8_rec = 525, | |
| CP_PASTE_rec = 526, | |
| CR6SET = 527, | |
| CR6UNSET = 528, | |
| CRAND = 529, | |
| CRANDC = 530, | |
| CREQV = 531, | |
| CRNAND = 532, | |
| CRNOR = 533, | |
| CROR = 534, | |
| CRORC = 535, | |
| CRSET = 536, | |
| CRUNSET = 537, | |
| CRXOR = 538, | |
| CTRL_DEP = 539, | |
| DARN = 540, | |
| DCBA = 541, | |
| DCBF = 542, | |
| DCBFEP = 543, | |
| DCBI = 544, | |
| DCBST = 545, | |
| DCBSTEP = 546, | |
| DCBT = 547, | |
| DCBTEP = 548, | |
| DCBTST = 549, | |
| DCBTSTEP = 550, | |
| DCBZ = 551, | |
| DCBZEP = 552, | |
| DCBZL = 553, | |
| DCBZLEP = 554, | |
| DCCCI = 555, | |
| DIVD = 556, | |
| DIVDE = 557, | |
| DIVDEO = 558, | |
| DIVDEO_rec = 559, | |
| DIVDEU = 560, | |
| DIVDEUO = 561, | |
| DIVDEUO_rec = 562, | |
| DIVDEU_rec = 563, | |
| DIVDE_rec = 564, | |
| DIVDO = 565, | |
| DIVDO_rec = 566, | |
| DIVDU = 567, | |
| DIVDUO = 568, | |
| DIVDUO_rec = 569, | |
| DIVDU_rec = 570, | |
| DIVD_rec = 571, | |
| DIVW = 572, | |
| DIVWE = 573, | |
| DIVWEO = 574, | |
| DIVWEO_rec = 575, | |
| DIVWEU = 576, | |
| DIVWEUO = 577, | |
| DIVWEUO_rec = 578, | |
| DIVWEU_rec = 579, | |
| DIVWE_rec = 580, | |
| DIVWO = 581, | |
| DIVWO_rec = 582, | |
| DIVWU = 583, | |
| DIVWUO = 584, | |
| DIVWUO_rec = 585, | |
| DIVWU_rec = 586, | |
| DIVW_rec = 587, | |
| DSS = 588, | |
| DSSALL = 589, | |
| DST = 590, | |
| DST64 = 591, | |
| DSTST = 592, | |
| DSTST64 = 593, | |
| DSTSTT = 594, | |
| DSTSTT64 = 595, | |
| DSTT = 596, | |
| DSTT64 = 597, | |
| DYNALLOC = 598, | |
| DYNALLOC8 = 599, | |
| DYNAREAOFFSET = 600, | |
| DYNAREAOFFSET8 = 601, | |
| EFDABS = 602, | |
| EFDADD = 603, | |
| EFDCFS = 604, | |
| EFDCFSF = 605, | |
| EFDCFSI = 606, | |
| EFDCFSID = 607, | |
| EFDCFUF = 608, | |
| EFDCFUI = 609, | |
| EFDCFUID = 610, | |
| EFDCMPEQ = 611, | |
| EFDCMPGT = 612, | |
| EFDCMPLT = 613, | |
| EFDCTSF = 614, | |
| EFDCTSI = 615, | |
| EFDCTSIDZ = 616, | |
| EFDCTSIZ = 617, | |
| EFDCTUF = 618, | |
| EFDCTUI = 619, | |
| EFDCTUIDZ = 620, | |
| EFDCTUIZ = 621, | |
| EFDDIV = 622, | |
| EFDMUL = 623, | |
| EFDNABS = 624, | |
| EFDNEG = 625, | |
| EFDSUB = 626, | |
| EFDTSTEQ = 627, | |
| EFDTSTGT = 628, | |
| EFDTSTLT = 629, | |
| EFSABS = 630, | |
| EFSADD = 631, | |
| EFSCFD = 632, | |
| EFSCFSF = 633, | |
| EFSCFSI = 634, | |
| EFSCFUF = 635, | |
| EFSCFUI = 636, | |
| EFSCMPEQ = 637, | |
| EFSCMPGT = 638, | |
| EFSCMPLT = 639, | |
| EFSCTSF = 640, | |
| EFSCTSI = 641, | |
| EFSCTSIZ = 642, | |
| EFSCTUF = 643, | |
| EFSCTUI = 644, | |
| EFSCTUIZ = 645, | |
| EFSDIV = 646, | |
| EFSMUL = 647, | |
| EFSNABS = 648, | |
| EFSNEG = 649, | |
| EFSSUB = 650, | |
| EFSTSTEQ = 651, | |
| EFSTSTGT = 652, | |
| EFSTSTLT = 653, | |
| EH_SjLj_LongJmp32 = 654, | |
| EH_SjLj_LongJmp64 = 655, | |
| EH_SjLj_SetJmp32 = 656, | |
| EH_SjLj_SetJmp64 = 657, | |
| EH_SjLj_Setup = 658, | |
| EQV = 659, | |
| EQV8 = 660, | |
| EQV8_rec = 661, | |
| EQV_rec = 662, | |
| EVABS = 663, | |
| EVADDIW = 664, | |
| EVADDSMIAAW = 665, | |
| EVADDSSIAAW = 666, | |
| EVADDUMIAAW = 667, | |
| EVADDUSIAAW = 668, | |
| EVADDW = 669, | |
| EVAND = 670, | |
| EVANDC = 671, | |
| EVCMPEQ = 672, | |
| EVCMPGTS = 673, | |
| EVCMPGTU = 674, | |
| EVCMPLTS = 675, | |
| EVCMPLTU = 676, | |
| EVCNTLSW = 677, | |
| EVCNTLZW = 678, | |
| EVDIVWS = 679, | |
| EVDIVWU = 680, | |
| EVEQV = 681, | |
| EVEXTSB = 682, | |
| EVEXTSH = 683, | |
| EVFSABS = 684, | |
| EVFSADD = 685, | |
| EVFSCFSF = 686, | |
| EVFSCFSI = 687, | |
| EVFSCFUF = 688, | |
| EVFSCFUI = 689, | |
| EVFSCMPEQ = 690, | |
| EVFSCMPGT = 691, | |
| EVFSCMPLT = 692, | |
| EVFSCTSF = 693, | |
| EVFSCTSI = 694, | |
| EVFSCTSIZ = 695, | |
| EVFSCTUF = 696, | |
| EVFSCTUI = 697, | |
| EVFSCTUIZ = 698, | |
| EVFSDIV = 699, | |
| EVFSMUL = 700, | |
| EVFSNABS = 701, | |
| EVFSNEG = 702, | |
| EVFSSUB = 703, | |
| EVFSTSTEQ = 704, | |
| EVFSTSTGT = 705, | |
| EVFSTSTLT = 706, | |
| EVLDD = 707, | |
| EVLDDX = 708, | |
| EVLDH = 709, | |
| EVLDHX = 710, | |
| EVLDW = 711, | |
| EVLDWX = 712, | |
| EVLHHESPLAT = 713, | |
| EVLHHESPLATX = 714, | |
| EVLHHOSSPLAT = 715, | |
| EVLHHOSSPLATX = 716, | |
| EVLHHOUSPLAT = 717, | |
| EVLHHOUSPLATX = 718, | |
| EVLWHE = 719, | |
| EVLWHEX = 720, | |
| EVLWHOS = 721, | |
| EVLWHOSX = 722, | |
| EVLWHOU = 723, | |
| EVLWHOUX = 724, | |
| EVLWHSPLAT = 725, | |
| EVLWHSPLATX = 726, | |
| EVLWWSPLAT = 727, | |
| EVLWWSPLATX = 728, | |
| EVMERGEHI = 729, | |
| EVMERGEHILO = 730, | |
| EVMERGELO = 731, | |
| EVMERGELOHI = 732, | |
| EVMHEGSMFAA = 733, | |
| EVMHEGSMFAN = 734, | |
| EVMHEGSMIAA = 735, | |
| EVMHEGSMIAN = 736, | |
| EVMHEGUMIAA = 737, | |
| EVMHEGUMIAN = 738, | |
| EVMHESMF = 739, | |
| EVMHESMFA = 740, | |
| EVMHESMFAAW = 741, | |
| EVMHESMFANW = 742, | |
| EVMHESMI = 743, | |
| EVMHESMIA = 744, | |
| EVMHESMIAAW = 745, | |
| EVMHESMIANW = 746, | |
| EVMHESSF = 747, | |
| EVMHESSFA = 748, | |
| EVMHESSFAAW = 749, | |
| EVMHESSFANW = 750, | |
| EVMHESSIAAW = 751, | |
| EVMHESSIANW = 752, | |
| EVMHEUMI = 753, | |
| EVMHEUMIA = 754, | |
| EVMHEUMIAAW = 755, | |
| EVMHEUMIANW = 756, | |
| EVMHEUSIAAW = 757, | |
| EVMHEUSIANW = 758, | |
| EVMHOGSMFAA = 759, | |
| EVMHOGSMFAN = 760, | |
| EVMHOGSMIAA = 761, | |
| EVMHOGSMIAN = 762, | |
| EVMHOGUMIAA = 763, | |
| EVMHOGUMIAN = 764, | |
| EVMHOSMF = 765, | |
| EVMHOSMFA = 766, | |
| EVMHOSMFAAW = 767, | |
| EVMHOSMFANW = 768, | |
| EVMHOSMI = 769, | |
| EVMHOSMIA = 770, | |
| EVMHOSMIAAW = 771, | |
| EVMHOSMIANW = 772, | |
| EVMHOSSF = 773, | |
| EVMHOSSFA = 774, | |
| EVMHOSSFAAW = 775, | |
| EVMHOSSFANW = 776, | |
| EVMHOSSIAAW = 777, | |
| EVMHOSSIANW = 778, | |
| EVMHOUMI = 779, | |
| EVMHOUMIA = 780, | |
| EVMHOUMIAAW = 781, | |
| EVMHOUMIANW = 782, | |
| EVMHOUSIAAW = 783, | |
| EVMHOUSIANW = 784, | |
| EVMRA = 785, | |
| EVMWHSMF = 786, | |
| EVMWHSMFA = 787, | |
| EVMWHSMI = 788, | |
| EVMWHSMIA = 789, | |
| EVMWHSSF = 790, | |
| EVMWHSSFA = 791, | |
| EVMWHUMI = 792, | |
| EVMWHUMIA = 793, | |
| EVMWLSMIAAW = 794, | |
| EVMWLSMIANW = 795, | |
| EVMWLSSIAAW = 796, | |
| EVMWLSSIANW = 797, | |
| EVMWLUMI = 798, | |
| EVMWLUMIA = 799, | |
| EVMWLUMIAAW = 800, | |
| EVMWLUMIANW = 801, | |
| EVMWLUSIAAW = 802, | |
| EVMWLUSIANW = 803, | |
| EVMWSMF = 804, | |
| EVMWSMFA = 805, | |
| EVMWSMFAA = 806, | |
| EVMWSMFAN = 807, | |
| EVMWSMI = 808, | |
| EVMWSMIA = 809, | |
| EVMWSMIAA = 810, | |
| EVMWSMIAN = 811, | |
| EVMWSSF = 812, | |
| EVMWSSFA = 813, | |
| EVMWSSFAA = 814, | |
| EVMWSSFAN = 815, | |
| EVMWUMI = 816, | |
| EVMWUMIA = 817, | |
| EVMWUMIAA = 818, | |
| EVMWUMIAN = 819, | |
| EVNAND = 820, | |
| EVNEG = 821, | |
| EVNOR = 822, | |
| EVOR = 823, | |
| EVORC = 824, | |
| EVRLW = 825, | |
| EVRLWI = 826, | |
| EVRNDW = 827, | |
| EVSEL = 828, | |
| EVSLW = 829, | |
| EVSLWI = 830, | |
| EVSPLATFI = 831, | |
| EVSPLATI = 832, | |
| EVSRWIS = 833, | |
| EVSRWIU = 834, | |
| EVSRWS = 835, | |
| EVSRWU = 836, | |
| EVSTDD = 837, | |
| EVSTDDX = 838, | |
| EVSTDH = 839, | |
| EVSTDHX = 840, | |
| EVSTDW = 841, | |
| EVSTDWX = 842, | |
| EVSTWHE = 843, | |
| EVSTWHEX = 844, | |
| EVSTWHO = 845, | |
| EVSTWHOX = 846, | |
| EVSTWWE = 847, | |
| EVSTWWEX = 848, | |
| EVSTWWO = 849, | |
| EVSTWWOX = 850, | |
| EVSUBFSMIAAW = 851, | |
| EVSUBFSSIAAW = 852, | |
| EVSUBFUMIAAW = 853, | |
| EVSUBFUSIAAW = 854, | |
| EVSUBFW = 855, | |
| EVSUBIFW = 856, | |
| EVXOR = 857, | |
| EXTSB = 858, | |
| EXTSB8 = 859, | |
| EXTSB8_32_64 = 860, | |
| EXTSB8_rec = 861, | |
| EXTSB_rec = 862, | |
| EXTSH = 863, | |
| EXTSH8 = 864, | |
| EXTSH8_32_64 = 865, | |
| EXTSH8_rec = 866, | |
| EXTSH_rec = 867, | |
| EXTSW = 868, | |
| EXTSWSLI = 869, | |
| EXTSWSLI_32_64 = 870, | |
| EXTSWSLI_32_64_rec = 871, | |
| EXTSWSLI_rec = 872, | |
| EXTSW_32 = 873, | |
| EXTSW_32_64 = 874, | |
| EXTSW_32_64_rec = 875, | |
| EXTSW_rec = 876, | |
| EnforceIEIO = 877, | |
| FABSD = 878, | |
| FABSD_rec = 879, | |
| FABSS = 880, | |
| FABSS_rec = 881, | |
| FADD = 882, | |
| FADDS = 883, | |
| FADDS_rec = 884, | |
| FADD_rec = 885, | |
| FADDrtz = 886, | |
| FCFID = 887, | |
| FCFIDS = 888, | |
| FCFIDS_rec = 889, | |
| FCFIDU = 890, | |
| FCFIDUS = 891, | |
| FCFIDUS_rec = 892, | |
| FCFIDU_rec = 893, | |
| FCFID_rec = 894, | |
| FCMPUD = 895, | |
| FCMPUS = 896, | |
| FCPSGND = 897, | |
| FCPSGND_rec = 898, | |
| FCPSGNS = 899, | |
| FCPSGNS_rec = 900, | |
| FCTID = 901, | |
| FCTIDU = 902, | |
| FCTIDUZ = 903, | |
| FCTIDUZ_rec = 904, | |
| FCTIDU_rec = 905, | |
| FCTIDZ = 906, | |
| FCTIDZ_rec = 907, | |
| FCTID_rec = 908, | |
| FCTIW = 909, | |
| FCTIWU = 910, | |
| FCTIWUZ = 911, | |
| FCTIWUZ_rec = 912, | |
| FCTIWU_rec = 913, | |
| FCTIWZ = 914, | |
| FCTIWZ_rec = 915, | |
| FCTIW_rec = 916, | |
| FDIV = 917, | |
| FDIVS = 918, | |
| FDIVS_rec = 919, | |
| FDIV_rec = 920, | |
| FMADD = 921, | |
| FMADDS = 922, | |
| FMADDS_rec = 923, | |
| FMADD_rec = 924, | |
| FMR = 925, | |
| FMR_rec = 926, | |
| FMSUB = 927, | |
| FMSUBS = 928, | |
| FMSUBS_rec = 929, | |
| FMSUB_rec = 930, | |
| FMUL = 931, | |
| FMULS = 932, | |
| FMULS_rec = 933, | |
| FMUL_rec = 934, | |
| FNABSD = 935, | |
| FNABSD_rec = 936, | |
| FNABSS = 937, | |
| FNABSS_rec = 938, | |
| FNEGD = 939, | |
| FNEGD_rec = 940, | |
| FNEGS = 941, | |
| FNEGS_rec = 942, | |
| FNMADD = 943, | |
| FNMADDS = 944, | |
| FNMADDS_rec = 945, | |
| FNMADD_rec = 946, | |
| FNMSUB = 947, | |
| FNMSUBS = 948, | |
| FNMSUBS_rec = 949, | |
| FNMSUB_rec = 950, | |
| FRE = 951, | |
| FRES = 952, | |
| FRES_rec = 953, | |
| FRE_rec = 954, | |
| FRIMD = 955, | |
| FRIMD_rec = 956, | |
| FRIMS = 957, | |
| FRIMS_rec = 958, | |
| FRIND = 959, | |
| FRIND_rec = 960, | |
| FRINS = 961, | |
| FRINS_rec = 962, | |
| FRIPD = 963, | |
| FRIPD_rec = 964, | |
| FRIPS = 965, | |
| FRIPS_rec = 966, | |
| FRIZD = 967, | |
| FRIZD_rec = 968, | |
| FRIZS = 969, | |
| FRIZS_rec = 970, | |
| FRSP = 971, | |
| FRSP_rec = 972, | |
| FRSQRTE = 973, | |
| FRSQRTES = 974, | |
| FRSQRTES_rec = 975, | |
| FRSQRTE_rec = 976, | |
| FSELD = 977, | |
| FSELD_rec = 978, | |
| FSELS = 979, | |
| FSELS_rec = 980, | |
| FSQRT = 981, | |
| FSQRTS = 982, | |
| FSQRTS_rec = 983, | |
| FSQRT_rec = 984, | |
| FSUB = 985, | |
| FSUBS = 986, | |
| FSUBS_rec = 987, | |
| FSUB_rec = 988, | |
| FTDIV = 989, | |
| FTSQRT = 990, | |
| GETtlsADDR = 991, | |
| GETtlsADDR32 = 992, | |
| GETtlsldADDR = 993, | |
| GETtlsldADDR32 = 994, | |
| HRFID = 995, | |
| ICBI = 996, | |
| ICBIEP = 997, | |
| ICBLC = 998, | |
| ICBLQ = 999, | |
| ICBT = 1000, | |
| ICBTLS = 1001, | |
| ICCCI = 1002, | |
| ISEL = 1003, | |
| ISEL8 = 1004, | |
| ISYNC = 1005, | |
| LA = 1006, | |
| LBARX = 1007, | |
| LBARXL = 1008, | |
| LBEPX = 1009, | |
| LBZ = 1010, | |
| LBZ8 = 1011, | |
| LBZCIX = 1012, | |
| LBZU = 1013, | |
| LBZU8 = 1014, | |
| LBZUX = 1015, | |
| LBZUX8 = 1016, | |
| LBZX = 1017, | |
| LBZX8 = 1018, | |
| LBZXTLS = 1019, | |
| LBZXTLS_ = 1020, | |
| LBZXTLS_32 = 1021, | |
| LD = 1022, | |
| LDARX = 1023, | |
| LDARXL = 1024, | |
| LDAT = 1025, | |
| LDBRX = 1026, | |
| LDCIX = 1027, | |
| LDMX = 1028, | |
| LDU = 1029, | |
| LDUX = 1030, | |
| LDX = 1031, | |
| LDXTLS = 1032, | |
| LDXTLS_ = 1033, | |
| LDgotTprelL = 1034, | |
| LDgotTprelL32 = 1035, | |
| LDtoc = 1036, | |
| LDtocBA = 1037, | |
| LDtocCPT = 1038, | |
| LDtocJTI = 1039, | |
| LDtocL = 1040, | |
| LFD = 1041, | |
| LFDEPX = 1042, | |
| LFDU = 1043, | |
| LFDUX = 1044, | |
| LFDX = 1045, | |
| LFIWAX = 1046, | |
| LFIWZX = 1047, | |
| LFS = 1048, | |
| LFSU = 1049, | |
| LFSUX = 1050, | |
| LFSX = 1051, | |
| LHA = 1052, | |
| LHA8 = 1053, | |
| LHARX = 1054, | |
| LHARXL = 1055, | |
| LHAU = 1056, | |
| LHAU8 = 1057, | |
| LHAUX = 1058, | |
| LHAUX8 = 1059, | |
| LHAX = 1060, | |
| LHAX8 = 1061, | |
| LHBRX = 1062, | |
| LHBRX8 = 1063, | |
| LHEPX = 1064, | |
| LHZ = 1065, | |
| LHZ8 = 1066, | |
| LHZCIX = 1067, | |
| LHZU = 1068, | |
| LHZU8 = 1069, | |
| LHZUX = 1070, | |
| LHZUX8 = 1071, | |
| LHZX = 1072, | |
| LHZX8 = 1073, | |
| LHZXTLS = 1074, | |
| LHZXTLS_ = 1075, | |
| LHZXTLS_32 = 1076, | |
| LI = 1077, | |
| LI8 = 1078, | |
| LIS = 1079, | |
| LIS8 = 1080, | |
| LMW = 1081, | |
| LSWI = 1082, | |
| LVEBX = 1083, | |
| LVEHX = 1084, | |
| LVEWX = 1085, | |
| LVSL = 1086, | |
| LVSR = 1087, | |
| LVX = 1088, | |
| LVXL = 1089, | |
| LWA = 1090, | |
| LWARX = 1091, | |
| LWARXL = 1092, | |
| LWAT = 1093, | |
| LWAUX = 1094, | |
| LWAX = 1095, | |
| LWAX_32 = 1096, | |
| LWA_32 = 1097, | |
| LWBRX = 1098, | |
| LWBRX8 = 1099, | |
| LWEPX = 1100, | |
| LWZ = 1101, | |
| LWZ8 = 1102, | |
| LWZCIX = 1103, | |
| LWZU = 1104, | |
| LWZU8 = 1105, | |
| LWZUX = 1106, | |
| LWZUX8 = 1107, | |
| LWZX = 1108, | |
| LWZX8 = 1109, | |
| LWZXTLS = 1110, | |
| LWZXTLS_ = 1111, | |
| LWZXTLS_32 = 1112, | |
| LWZtoc = 1113, | |
| LWZtocL = 1114, | |
| LXSD = 1115, | |
| LXSDX = 1116, | |
| LXSIBZX = 1117, | |
| LXSIHZX = 1118, | |
| LXSIWAX = 1119, | |
| LXSIWZX = 1120, | |
| LXSSP = 1121, | |
| LXSSPX = 1122, | |
| LXV = 1123, | |
| LXVB16X = 1124, | |
| LXVD2X = 1125, | |
| LXVDSX = 1126, | |
| LXVH8X = 1127, | |
| LXVL = 1128, | |
| LXVLL = 1129, | |
| LXVW4X = 1130, | |
| LXVWSX = 1131, | |
| LXVX = 1132, | |
| MADDHD = 1133, | |
| MADDHDU = 1134, | |
| MADDLD = 1135, | |
| MADDLD8 = 1136, | |
| MBAR = 1137, | |
| MCRF = 1138, | |
| MCRFS = 1139, | |
| MCRXRX = 1140, | |
| MFBHRBE = 1141, | |
| MFCR = 1142, | |
| MFCR8 = 1143, | |
| MFCTR = 1144, | |
| MFCTR8 = 1145, | |
| MFDCR = 1146, | |
| MFFS = 1147, | |
| MFFSCDRN = 1148, | |
| MFFSCDRNI = 1149, | |
| MFFSCE = 1150, | |
| MFFSCRN = 1151, | |
| MFFSCRNI = 1152, | |
| MFFSL = 1153, | |
| MFFS_rec = 1154, | |
| MFLR = 1155, | |
| MFLR8 = 1156, | |
| MFMSR = 1157, | |
| MFOCRF = 1158, | |
| MFOCRF8 = 1159, | |
| MFPMR = 1160, | |
| MFSPR = 1161, | |
| MFSPR8 = 1162, | |
| MFSR = 1163, | |
| MFSRIN = 1164, | |
| MFTB = 1165, | |
| MFTB8 = 1166, | |
| MFVRD = 1167, | |
| MFVRSAVE = 1168, | |
| MFVRSAVEv = 1169, | |
| MFVRWZ = 1170, | |
| MFVSCR = 1171, | |
| MFVSRD = 1172, | |
| MFVSRLD = 1173, | |
| MFVSRWZ = 1174, | |
| MODSD = 1175, | |
| MODSW = 1176, | |
| MODUD = 1177, | |
| MODUW = 1178, | |
| MSGSYNC = 1179, | |
| MSYNC = 1180, | |
| MTCRF = 1181, | |
| MTCRF8 = 1182, | |
| MTCTR = 1183, | |
| MTCTR8 = 1184, | |
| MTCTR8loop = 1185, | |
| MTCTRloop = 1186, | |
| MTDCR = 1187, | |
| MTFSB0 = 1188, | |
| MTFSB1 = 1189, | |
| MTFSF = 1190, | |
| MTFSFI = 1191, | |
| MTFSFI_rec = 1192, | |
| MTFSF_rec = 1193, | |
| MTFSFb = 1194, | |
| MTLR = 1195, | |
| MTLR8 = 1196, | |
| MTMSR = 1197, | |
| MTMSRD = 1198, | |
| MTOCRF = 1199, | |
| MTOCRF8 = 1200, | |
| MTPMR = 1201, | |
| MTSPR = 1202, | |
| MTSPR8 = 1203, | |
| MTSR = 1204, | |
| MTSRIN = 1205, | |
| MTVRD = 1206, | |
| MTVRSAVE = 1207, | |
| MTVRSAVEv = 1208, | |
| MTVRWA = 1209, | |
| MTVRWZ = 1210, | |
| MTVSCR = 1211, | |
| MTVSRD = 1212, | |
| MTVSRDD = 1213, | |
| MTVSRWA = 1214, | |
| MTVSRWS = 1215, | |
| MTVSRWZ = 1216, | |
| MULHD = 1217, | |
| MULHDU = 1218, | |
| MULHDU_rec = 1219, | |
| MULHD_rec = 1220, | |
| MULHW = 1221, | |
| MULHWU = 1222, | |
| MULHWU_rec = 1223, | |
| MULHW_rec = 1224, | |
| MULLD = 1225, | |
| MULLDO = 1226, | |
| MULLDO_rec = 1227, | |
| MULLD_rec = 1228, | |
| MULLI = 1229, | |
| MULLI8 = 1230, | |
| MULLW = 1231, | |
| MULLWO = 1232, | |
| MULLWO_rec = 1233, | |
| MULLW_rec = 1234, | |
| MoveGOTtoLR = 1235, | |
| MovePCtoLR = 1236, | |
| MovePCtoLR8 = 1237, | |
| NAND = 1238, | |
| NAND8 = 1239, | |
| NAND8_rec = 1240, | |
| NAND_rec = 1241, | |
| NAP = 1242, | |
| NEG = 1243, | |
| NEG8 = 1244, | |
| NEG8O = 1245, | |
| NEG8O_rec = 1246, | |
| NEG8_rec = 1247, | |
| NEGO = 1248, | |
| NEGO_rec = 1249, | |
| NEG_rec = 1250, | |
| NOP = 1251, | |
| NOP_GT_PWR6 = 1252, | |
| NOP_GT_PWR7 = 1253, | |
| NOR = 1254, | |
| NOR8 = 1255, | |
| NOR8_rec = 1256, | |
| NOR_rec = 1257, | |
| OR = 1258, | |
| OR8 = 1259, | |
| OR8_rec = 1260, | |
| ORC = 1261, | |
| ORC8 = 1262, | |
| ORC8_rec = 1263, | |
| ORC_rec = 1264, | |
| ORI = 1265, | |
| ORI8 = 1266, | |
| ORIS = 1267, | |
| ORIS8 = 1268, | |
| OR_rec = 1269, | |
| POPCNTB = 1270, | |
| POPCNTD = 1271, | |
| POPCNTW = 1272, | |
| PPC32GOT = 1273, | |
| PPC32PICGOT = 1274, | |
| QVALIGNI = 1275, | |
| QVALIGNIb = 1276, | |
| QVALIGNIs = 1277, | |
| QVESPLATI = 1278, | |
| QVESPLATIb = 1279, | |
| QVESPLATIs = 1280, | |
| QVFABS = 1281, | |
| QVFABSs = 1282, | |
| QVFADD = 1283, | |
| QVFADDS = 1284, | |
| QVFADDSs = 1285, | |
| QVFCFID = 1286, | |
| QVFCFIDS = 1287, | |
| QVFCFIDU = 1288, | |
| QVFCFIDUS = 1289, | |
| QVFCFIDb = 1290, | |
| QVFCMPEQ = 1291, | |
| QVFCMPEQb = 1292, | |
| QVFCMPEQbs = 1293, | |
| QVFCMPGT = 1294, | |
| QVFCMPGTb = 1295, | |
| QVFCMPGTbs = 1296, | |
| QVFCMPLT = 1297, | |
| QVFCMPLTb = 1298, | |
| QVFCMPLTbs = 1299, | |
| QVFCPSGN = 1300, | |
| QVFCPSGNs = 1301, | |
| QVFCTID = 1302, | |
| QVFCTIDU = 1303, | |
| QVFCTIDUZ = 1304, | |
| QVFCTIDZ = 1305, | |
| QVFCTIDb = 1306, | |
| QVFCTIW = 1307, | |
| QVFCTIWU = 1308, | |
| QVFCTIWUZ = 1309, | |
| QVFCTIWZ = 1310, | |
| QVFLOGICAL = 1311, | |
| QVFLOGICALb = 1312, | |
| QVFLOGICALs = 1313, | |
| QVFMADD = 1314, | |
| QVFMADDS = 1315, | |
| QVFMADDSs = 1316, | |
| QVFMR = 1317, | |
| QVFMRb = 1318, | |
| QVFMRs = 1319, | |
| QVFMSUB = 1320, | |
| QVFMSUBS = 1321, | |
| QVFMSUBSs = 1322, | |
| QVFMUL = 1323, | |
| QVFMULS = 1324, | |
| QVFMULSs = 1325, | |
| QVFNABS = 1326, | |
| QVFNABSs = 1327, | |
| QVFNEG = 1328, | |
| QVFNEGs = 1329, | |
| QVFNMADD = 1330, | |
| QVFNMADDS = 1331, | |
| QVFNMADDSs = 1332, | |
| QVFNMSUB = 1333, | |
| QVFNMSUBS = 1334, | |
| QVFNMSUBSs = 1335, | |
| QVFPERM = 1336, | |
| QVFPERMs = 1337, | |
| QVFRE = 1338, | |
| QVFRES = 1339, | |
| QVFRESs = 1340, | |
| QVFRIM = 1341, | |
| QVFRIMs = 1342, | |
| QVFRIN = 1343, | |
| QVFRINs = 1344, | |
| QVFRIP = 1345, | |
| QVFRIPs = 1346, | |
| QVFRIZ = 1347, | |
| QVFRIZs = 1348, | |
| QVFRSP = 1349, | |
| QVFRSPs = 1350, | |
| QVFRSQRTE = 1351, | |
| QVFRSQRTES = 1352, | |
| QVFRSQRTESs = 1353, | |
| QVFSEL = 1354, | |
| QVFSELb = 1355, | |
| QVFSELbb = 1356, | |
| QVFSELbs = 1357, | |
| QVFSUB = 1358, | |
| QVFSUBS = 1359, | |
| QVFSUBSs = 1360, | |
| QVFTSTNAN = 1361, | |
| QVFTSTNANb = 1362, | |
| QVFTSTNANbs = 1363, | |
| QVFXMADD = 1364, | |
| QVFXMADDS = 1365, | |
| QVFXMUL = 1366, | |
| QVFXMULS = 1367, | |
| QVFXXCPNMADD = 1368, | |
| QVFXXCPNMADDS = 1369, | |
| QVFXXMADD = 1370, | |
| QVFXXMADDS = 1371, | |
| QVFXXNPMADD = 1372, | |
| QVFXXNPMADDS = 1373, | |
| QVGPCI = 1374, | |
| QVLFCDUX = 1375, | |
| QVLFCDUXA = 1376, | |
| QVLFCDX = 1377, | |
| QVLFCDXA = 1378, | |
| QVLFCSUX = 1379, | |
| QVLFCSUXA = 1380, | |
| QVLFCSX = 1381, | |
| QVLFCSXA = 1382, | |
| QVLFCSXs = 1383, | |
| QVLFDUX = 1384, | |
| QVLFDUXA = 1385, | |
| QVLFDX = 1386, | |
| QVLFDXA = 1387, | |
| QVLFDXb = 1388, | |
| QVLFIWAX = 1389, | |
| QVLFIWAXA = 1390, | |
| QVLFIWZX = 1391, | |
| QVLFIWZXA = 1392, | |
| QVLFSUX = 1393, | |
| QVLFSUXA = 1394, | |
| QVLFSX = 1395, | |
| QVLFSXA = 1396, | |
| QVLFSXb = 1397, | |
| QVLFSXs = 1398, | |
| QVLPCLDX = 1399, | |
| QVLPCLSX = 1400, | |
| QVLPCLSXint = 1401, | |
| QVLPCRDX = 1402, | |
| QVLPCRSX = 1403, | |
| QVSTFCDUX = 1404, | |
| QVSTFCDUXA = 1405, | |
| QVSTFCDUXI = 1406, | |
| QVSTFCDUXIA = 1407, | |
| QVSTFCDX = 1408, | |
| QVSTFCDXA = 1409, | |
| QVSTFCDXI = 1410, | |
| QVSTFCDXIA = 1411, | |
| QVSTFCSUX = 1412, | |
| QVSTFCSUXA = 1413, | |
| QVSTFCSUXI = 1414, | |
| QVSTFCSUXIA = 1415, | |
| QVSTFCSX = 1416, | |
| QVSTFCSXA = 1417, | |
| QVSTFCSXI = 1418, | |
| QVSTFCSXIA = 1419, | |
| QVSTFCSXs = 1420, | |
| QVSTFDUX = 1421, | |
| QVSTFDUXA = 1422, | |
| QVSTFDUXI = 1423, | |
| QVSTFDUXIA = 1424, | |
| QVSTFDX = 1425, | |
| QVSTFDXA = 1426, | |
| QVSTFDXI = 1427, | |
| QVSTFDXIA = 1428, | |
| QVSTFDXb = 1429, | |
| QVSTFIWX = 1430, | |
| QVSTFIWXA = 1431, | |
| QVSTFSUX = 1432, | |
| QVSTFSUXA = 1433, | |
| QVSTFSUXI = 1434, | |
| QVSTFSUXIA = 1435, | |
| QVSTFSUXs = 1436, | |
| QVSTFSX = 1437, | |
| QVSTFSXA = 1438, | |
| QVSTFSXI = 1439, | |
| QVSTFSXIA = 1440, | |
| QVSTFSXs = 1441, | |
| RESTORE_CR = 1442, | |
| RESTORE_CRBIT = 1443, | |
| RESTORE_VRSAVE = 1444, | |
| RFCI = 1445, | |
| RFDI = 1446, | |
| RFEBB = 1447, | |
| RFI = 1448, | |
| RFID = 1449, | |
| RFMCI = 1450, | |
| RLDCL = 1451, | |
| RLDCL_rec = 1452, | |
| RLDCR = 1453, | |
| RLDCR_rec = 1454, | |
| RLDIC = 1455, | |
| RLDICL = 1456, | |
| RLDICL_32 = 1457, | |
| RLDICL_32_64 = 1458, | |
| RLDICL_32_rec = 1459, | |
| RLDICL_rec = 1460, | |
| RLDICR = 1461, | |
| RLDICR_32 = 1462, | |
| RLDICR_rec = 1463, | |
| RLDIC_rec = 1464, | |
| RLDIMI = 1465, | |
| RLDIMI_rec = 1466, | |
| RLWIMI = 1467, | |
| RLWIMI8 = 1468, | |
| RLWIMI8_rec = 1469, | |
| RLWIMI_rec = 1470, | |
| RLWINM = 1471, | |
| RLWINM8 = 1472, | |
| RLWINM8_rec = 1473, | |
| RLWINM_rec = 1474, | |
| RLWNM = 1475, | |
| RLWNM8 = 1476, | |
| RLWNM8_rec = 1477, | |
| RLWNM_rec = 1478, | |
| ReadTB = 1479, | |
| SC = 1480, | |
| SELECT_CC_F16 = 1481, | |
| SELECT_CC_F4 = 1482, | |
| SELECT_CC_F8 = 1483, | |
| SELECT_CC_I4 = 1484, | |
| SELECT_CC_I8 = 1485, | |
| SELECT_CC_QBRC = 1486, | |
| SELECT_CC_QFRC = 1487, | |
| SELECT_CC_QSRC = 1488, | |
| SELECT_CC_SPE = 1489, | |
| SELECT_CC_SPE4 = 1490, | |
| SELECT_CC_VRRC = 1491, | |
| SELECT_CC_VSFRC = 1492, | |
| SELECT_CC_VSRC = 1493, | |
| SELECT_CC_VSSRC = 1494, | |
| SELECT_F16 = 1495, | |
| SELECT_F4 = 1496, | |
| SELECT_F8 = 1497, | |
| SELECT_I4 = 1498, | |
| SELECT_I8 = 1499, | |
| SELECT_QBRC = 1500, | |
| SELECT_QFRC = 1501, | |
| SELECT_QSRC = 1502, | |
| SELECT_SPE = 1503, | |
| SELECT_SPE4 = 1504, | |
| SELECT_VRRC = 1505, | |
| SELECT_VSFRC = 1506, | |
| SELECT_VSRC = 1507, | |
| SELECT_VSSRC = 1508, | |
| SETB = 1509, | |
| SETB8 = 1510, | |
| SETRND = 1511, | |
| SETRNDi = 1512, | |
| SLBFEE_rec = 1513, | |
| SLBIA = 1514, | |
| SLBIE = 1515, | |
| SLBIEG = 1516, | |
| SLBMFEE = 1517, | |
| SLBMFEV = 1518, | |
| SLBMTE = 1519, | |
| SLBSYNC = 1520, | |
| SLD = 1521, | |
| SLD_rec = 1522, | |
| SLW = 1523, | |
| SLW8 = 1524, | |
| SLW8_rec = 1525, | |
| SLW_rec = 1526, | |
| SPELWZ = 1527, | |
| SPELWZX = 1528, | |
| SPESTW = 1529, | |
| SPESTWX = 1530, | |
| SPILL_CR = 1531, | |
| SPILL_CRBIT = 1532, | |
| SPILL_VRSAVE = 1533, | |
| SRAD = 1534, | |
| SRADI = 1535, | |
| SRADI_32 = 1536, | |
| SRADI_rec = 1537, | |
| SRAD_rec = 1538, | |
| SRAW = 1539, | |
| SRAWI = 1540, | |
| SRAWI_rec = 1541, | |
| SRAW_rec = 1542, | |
| SRD = 1543, | |
| SRD_rec = 1544, | |
| SRW = 1545, | |
| SRW8 = 1546, | |
| SRW8_rec = 1547, | |
| SRW_rec = 1548, | |
| STB = 1549, | |
| STB8 = 1550, | |
| STBCIX = 1551, | |
| STBCX = 1552, | |
| STBEPX = 1553, | |
| STBU = 1554, | |
| STBU8 = 1555, | |
| STBUX = 1556, | |
| STBUX8 = 1557, | |
| STBX = 1558, | |
| STBX8 = 1559, | |
| STBXTLS = 1560, | |
| STBXTLS_ = 1561, | |
| STBXTLS_32 = 1562, | |
| STD = 1563, | |
| STDAT = 1564, | |
| STDBRX = 1565, | |
| STDCIX = 1566, | |
| STDCX = 1567, | |
| STDU = 1568, | |
| STDUX = 1569, | |
| STDX = 1570, | |
| STDXTLS = 1571, | |
| STDXTLS_ = 1572, | |
| STFD = 1573, | |
| STFDEPX = 1574, | |
| STFDU = 1575, | |
| STFDUX = 1576, | |
| STFDX = 1577, | |
| STFIWX = 1578, | |
| STFS = 1579, | |
| STFSU = 1580, | |
| STFSUX = 1581, | |
| STFSX = 1582, | |
| STH = 1583, | |
| STH8 = 1584, | |
| STHBRX = 1585, | |
| STHCIX = 1586, | |
| STHCX = 1587, | |
| STHEPX = 1588, | |
| STHU = 1589, | |
| STHU8 = 1590, | |
| STHUX = 1591, | |
| STHUX8 = 1592, | |
| STHX = 1593, | |
| STHX8 = 1594, | |
| STHXTLS = 1595, | |
| STHXTLS_ = 1596, | |
| STHXTLS_32 = 1597, | |
| STMW = 1598, | |
| STOP = 1599, | |
| STSWI = 1600, | |
| STVEBX = 1601, | |
| STVEHX = 1602, | |
| STVEWX = 1603, | |
| STVX = 1604, | |
| STVXL = 1605, | |
| STW = 1606, | |
| STW8 = 1607, | |
| STWAT = 1608, | |
| STWBRX = 1609, | |
| STWCIX = 1610, | |
| STWCX = 1611, | |
| STWEPX = 1612, | |
| STWU = 1613, | |
| STWU8 = 1614, | |
| STWUX = 1615, | |
| STWUX8 = 1616, | |
| STWX = 1617, | |
| STWX8 = 1618, | |
| STWXTLS = 1619, | |
| STWXTLS_ = 1620, | |
| STWXTLS_32 = 1621, | |
| STXSD = 1622, | |
| STXSDX = 1623, | |
| STXSIBX = 1624, | |
| STXSIBXv = 1625, | |
| STXSIHX = 1626, | |
| STXSIHXv = 1627, | |
| STXSIWX = 1628, | |
| STXSSP = 1629, | |
| STXSSPX = 1630, | |
| STXV = 1631, | |
| STXVB16X = 1632, | |
| STXVD2X = 1633, | |
| STXVH8X = 1634, | |
| STXVL = 1635, | |
| STXVLL = 1636, | |
| STXVW4X = 1637, | |
| STXVX = 1638, | |
| SUBF = 1639, | |
| SUBF8 = 1640, | |
| SUBF8O = 1641, | |
| SUBF8O_rec = 1642, | |
| SUBF8_rec = 1643, | |
| SUBFC = 1644, | |
| SUBFC8 = 1645, | |
| SUBFC8O = 1646, | |
| SUBFC8O_rec = 1647, | |
| SUBFC8_rec = 1648, | |
| SUBFCO = 1649, | |
| SUBFCO_rec = 1650, | |
| SUBFC_rec = 1651, | |
| SUBFE = 1652, | |
| SUBFE8 = 1653, | |
| SUBFE8O = 1654, | |
| SUBFE8O_rec = 1655, | |
| SUBFE8_rec = 1656, | |
| SUBFEO = 1657, | |
| SUBFEO_rec = 1658, | |
| SUBFE_rec = 1659, | |
| SUBFIC = 1660, | |
| SUBFIC8 = 1661, | |
| SUBFME = 1662, | |
| SUBFME8 = 1663, | |
| SUBFME8O = 1664, | |
| SUBFME8O_rec = 1665, | |
| SUBFME8_rec = 1666, | |
| SUBFMEO = 1667, | |
| SUBFMEO_rec = 1668, | |
| SUBFME_rec = 1669, | |
| SUBFO = 1670, | |
| SUBFO_rec = 1671, | |
| SUBFZE = 1672, | |
| SUBFZE8 = 1673, | |
| SUBFZE8O = 1674, | |
| SUBFZE8O_rec = 1675, | |
| SUBFZE8_rec = 1676, | |
| SUBFZEO = 1677, | |
| SUBFZEO_rec = 1678, | |
| SUBFZE_rec = 1679, | |
| SUBF_rec = 1680, | |
| SYNC = 1681, | |
| TABORT = 1682, | |
| TABORTDC = 1683, | |
| TABORTDCI = 1684, | |
| TABORTWC = 1685, | |
| TABORTWCI = 1686, | |
| TAILB = 1687, | |
| TAILB8 = 1688, | |
| TAILBA = 1689, | |
| TAILBA8 = 1690, | |
| TAILBCTR = 1691, | |
| TAILBCTR8 = 1692, | |
| TBEGIN = 1693, | |
| TBEGIN_RET = 1694, | |
| TCHECK = 1695, | |
| TCHECK_RET = 1696, | |
| TCRETURNai = 1697, | |
| TCRETURNai8 = 1698, | |
| TCRETURNdi = 1699, | |
| TCRETURNdi8 = 1700, | |
| TCRETURNri = 1701, | |
| TCRETURNri8 = 1702, | |
| TD = 1703, | |
| TDI = 1704, | |
| TEND = 1705, | |
| TLBIA = 1706, | |
| TLBIE = 1707, | |
| TLBIEL = 1708, | |
| TLBIVAX = 1709, | |
| TLBLD = 1710, | |
| TLBLI = 1711, | |
| TLBRE = 1712, | |
| TLBRE2 = 1713, | |
| TLBSX = 1714, | |
| TLBSX2 = 1715, | |
| TLBSX2D = 1716, | |
| TLBSYNC = 1717, | |
| TLBWE = 1718, | |
| TLBWE2 = 1719, | |
| TRAP = 1720, | |
| TRECHKPT = 1721, | |
| TRECLAIM = 1722, | |
| TSR = 1723, | |
| TW = 1724, | |
| TWI = 1725, | |
| UNENCODED_NOP = 1726, | |
| UPDATE_VRSAVE = 1727, | |
| UpdateGBR = 1728, | |
| VABSDUB = 1729, | |
| VABSDUH = 1730, | |
| VABSDUW = 1731, | |
| VADDCUQ = 1732, | |
| VADDCUW = 1733, | |
| VADDECUQ = 1734, | |
| VADDEUQM = 1735, | |
| VADDFP = 1736, | |
| VADDSBS = 1737, | |
| VADDSHS = 1738, | |
| VADDSWS = 1739, | |
| VADDUBM = 1740, | |
| VADDUBS = 1741, | |
| VADDUDM = 1742, | |
| VADDUHM = 1743, | |
| VADDUHS = 1744, | |
| VADDUQM = 1745, | |
| VADDUWM = 1746, | |
| VADDUWS = 1747, | |
| VAND = 1748, | |
| VANDC = 1749, | |
| VAVGSB = 1750, | |
| VAVGSH = 1751, | |
| VAVGSW = 1752, | |
| VAVGUB = 1753, | |
| VAVGUH = 1754, | |
| VAVGUW = 1755, | |
| VBPERMD = 1756, | |
| VBPERMQ = 1757, | |
| VCFSX = 1758, | |
| VCFSX_0 = 1759, | |
| VCFUX = 1760, | |
| VCFUX_0 = 1761, | |
| VCIPHER = 1762, | |
| VCIPHERLAST = 1763, | |
| VCLZB = 1764, | |
| VCLZD = 1765, | |
| VCLZH = 1766, | |
| VCLZLSBB = 1767, | |
| VCLZW = 1768, | |
| VCMPBFP = 1769, | |
| VCMPBFP_rec = 1770, | |
| VCMPEQFP = 1771, | |
| VCMPEQFP_rec = 1772, | |
| VCMPEQUB = 1773, | |
| VCMPEQUB_rec = 1774, | |
| VCMPEQUD = 1775, | |
| VCMPEQUD_rec = 1776, | |
| VCMPEQUH = 1777, | |
| VCMPEQUH_rec = 1778, | |
| VCMPEQUW = 1779, | |
| VCMPEQUW_rec = 1780, | |
| VCMPGEFP = 1781, | |
| VCMPGEFP_rec = 1782, | |
| VCMPGTFP = 1783, | |
| VCMPGTFP_rec = 1784, | |
| VCMPGTSB = 1785, | |
| VCMPGTSB_rec = 1786, | |
| VCMPGTSD = 1787, | |
| VCMPGTSD_rec = 1788, | |
| VCMPGTSH = 1789, | |
| VCMPGTSH_rec = 1790, | |
| VCMPGTSW = 1791, | |
| VCMPGTSW_rec = 1792, | |
| VCMPGTUB = 1793, | |
| VCMPGTUB_rec = 1794, | |
| VCMPGTUD = 1795, | |
| VCMPGTUD_rec = 1796, | |
| VCMPGTUH = 1797, | |
| VCMPGTUH_rec = 1798, | |
| VCMPGTUW = 1799, | |
| VCMPGTUW_rec = 1800, | |
| VCMPNEB = 1801, | |
| VCMPNEB_rec = 1802, | |
| VCMPNEH = 1803, | |
| VCMPNEH_rec = 1804, | |
| VCMPNEW = 1805, | |
| VCMPNEW_rec = 1806, | |
| VCMPNEZB = 1807, | |
| VCMPNEZB_rec = 1808, | |
| VCMPNEZH = 1809, | |
| VCMPNEZH_rec = 1810, | |
| VCMPNEZW = 1811, | |
| VCMPNEZW_rec = 1812, | |
| VCTSXS = 1813, | |
| VCTSXS_0 = 1814, | |
| VCTUXS = 1815, | |
| VCTUXS_0 = 1816, | |
| VCTZB = 1817, | |
| VCTZD = 1818, | |
| VCTZH = 1819, | |
| VCTZLSBB = 1820, | |
| VCTZW = 1821, | |
| VEQV = 1822, | |
| VEXPTEFP = 1823, | |
| VEXTRACTD = 1824, | |
| VEXTRACTUB = 1825, | |
| VEXTRACTUH = 1826, | |
| VEXTRACTUW = 1827, | |
| VEXTSB2D = 1828, | |
| VEXTSB2Ds = 1829, | |
| VEXTSB2W = 1830, | |
| VEXTSB2Ws = 1831, | |
| VEXTSH2D = 1832, | |
| VEXTSH2Ds = 1833, | |
| VEXTSH2W = 1834, | |
| VEXTSH2Ws = 1835, | |
| VEXTSW2D = 1836, | |
| VEXTSW2Ds = 1837, | |
| VEXTUBLX = 1838, | |
| VEXTUBRX = 1839, | |
| VEXTUHLX = 1840, | |
| VEXTUHRX = 1841, | |
| VEXTUWLX = 1842, | |
| VEXTUWRX = 1843, | |
| VGBBD = 1844, | |
| VINSERTB = 1845, | |
| VINSERTD = 1846, | |
| VINSERTH = 1847, | |
| VINSERTW = 1848, | |
| VLOGEFP = 1849, | |
| VMADDFP = 1850, | |
| VMAXFP = 1851, | |
| VMAXSB = 1852, | |
| VMAXSD = 1853, | |
| VMAXSH = 1854, | |
| VMAXSW = 1855, | |
| VMAXUB = 1856, | |
| VMAXUD = 1857, | |
| VMAXUH = 1858, | |
| VMAXUW = 1859, | |
| VMHADDSHS = 1860, | |
| VMHRADDSHS = 1861, | |
| VMINFP = 1862, | |
| VMINSB = 1863, | |
| VMINSD = 1864, | |
| VMINSH = 1865, | |
| VMINSW = 1866, | |
| VMINUB = 1867, | |
| VMINUD = 1868, | |
| VMINUH = 1869, | |
| VMINUW = 1870, | |
| VMLADDUHM = 1871, | |
| VMRGEW = 1872, | |
| VMRGHB = 1873, | |
| VMRGHH = 1874, | |
| VMRGHW = 1875, | |
| VMRGLB = 1876, | |
| VMRGLH = 1877, | |
| VMRGLW = 1878, | |
| VMRGOW = 1879, | |
| VMSUMMBM = 1880, | |
| VMSUMSHM = 1881, | |
| VMSUMSHS = 1882, | |
| VMSUMUBM = 1883, | |
| VMSUMUHM = 1884, | |
| VMSUMUHS = 1885, | |
| VMUL10CUQ = 1886, | |
| VMUL10ECUQ = 1887, | |
| VMUL10EUQ = 1888, | |
| VMUL10UQ = 1889, | |
| VMULESB = 1890, | |
| VMULESH = 1891, | |
| VMULESW = 1892, | |
| VMULEUB = 1893, | |
| VMULEUH = 1894, | |
| VMULEUW = 1895, | |
| VMULOSB = 1896, | |
| VMULOSH = 1897, | |
| VMULOSW = 1898, | |
| VMULOUB = 1899, | |
| VMULOUH = 1900, | |
| VMULOUW = 1901, | |
| VMULUWM = 1902, | |
| VNAND = 1903, | |
| VNCIPHER = 1904, | |
| VNCIPHERLAST = 1905, | |
| VNEGD = 1906, | |
| VNEGW = 1907, | |
| VNMSUBFP = 1908, | |
| VNOR = 1909, | |
| VOR = 1910, | |
| VORC = 1911, | |
| VPERM = 1912, | |
| VPERMR = 1913, | |
| VPERMXOR = 1914, | |
| VPKPX = 1915, | |
| VPKSDSS = 1916, | |
| VPKSDUS = 1917, | |
| VPKSHSS = 1918, | |
| VPKSHUS = 1919, | |
| VPKSWSS = 1920, | |
| VPKSWUS = 1921, | |
| VPKUDUM = 1922, | |
| VPKUDUS = 1923, | |
| VPKUHUM = 1924, | |
| VPKUHUS = 1925, | |
| VPKUWUM = 1926, | |
| VPKUWUS = 1927, | |
| VPMSUMB = 1928, | |
| VPMSUMD = 1929, | |
| VPMSUMH = 1930, | |
| VPMSUMW = 1931, | |
| VPOPCNTB = 1932, | |
| VPOPCNTD = 1933, | |
| VPOPCNTH = 1934, | |
| VPOPCNTW = 1935, | |
| VPRTYBD = 1936, | |
| VPRTYBQ = 1937, | |
| VPRTYBW = 1938, | |
| VREFP = 1939, | |
| VRFIM = 1940, | |
| VRFIN = 1941, | |
| VRFIP = 1942, | |
| VRFIZ = 1943, | |
| VRLB = 1944, | |
| VRLD = 1945, | |
| VRLDMI = 1946, | |
| VRLDNM = 1947, | |
| VRLH = 1948, | |
| VRLW = 1949, | |
| VRLWMI = 1950, | |
| VRLWNM = 1951, | |
| VRSQRTEFP = 1952, | |
| VSBOX = 1953, | |
| VSEL = 1954, | |
| VSHASIGMAD = 1955, | |
| VSHASIGMAW = 1956, | |
| VSL = 1957, | |
| VSLB = 1958, | |
| VSLD = 1959, | |
| VSLDOI = 1960, | |
| VSLH = 1961, | |
| VSLO = 1962, | |
| VSLV = 1963, | |
| VSLW = 1964, | |
| VSPLTB = 1965, | |
| VSPLTBs = 1966, | |
| VSPLTH = 1967, | |
| VSPLTHs = 1968, | |
| VSPLTISB = 1969, | |
| VSPLTISH = 1970, | |
| VSPLTISW = 1971, | |
| VSPLTW = 1972, | |
| VSR = 1973, | |
| VSRAB = 1974, | |
| VSRAD = 1975, | |
| VSRAH = 1976, | |
| VSRAW = 1977, | |
| VSRB = 1978, | |
| VSRD = 1979, | |
| VSRH = 1980, | |
| VSRO = 1981, | |
| VSRV = 1982, | |
| VSRW = 1983, | |
| VSUBCUQ = 1984, | |
| VSUBCUW = 1985, | |
| VSUBECUQ = 1986, | |
| VSUBEUQM = 1987, | |
| VSUBFP = 1988, | |
| VSUBSBS = 1989, | |
| VSUBSHS = 1990, | |
| VSUBSWS = 1991, | |
| VSUBUBM = 1992, | |
| VSUBUBS = 1993, | |
| VSUBUDM = 1994, | |
| VSUBUHM = 1995, | |
| VSUBUHS = 1996, | |
| VSUBUQM = 1997, | |
| VSUBUWM = 1998, | |
| VSUBUWS = 1999, | |
| VSUM2SWS = 2000, | |
| VSUM4SBS = 2001, | |
| VSUM4SHS = 2002, | |
| VSUM4UBS = 2003, | |
| VSUMSWS = 2004, | |
| VUPKHPX = 2005, | |
| VUPKHSB = 2006, | |
| VUPKHSH = 2007, | |
| VUPKHSW = 2008, | |
| VUPKLPX = 2009, | |
| VUPKLSB = 2010, | |
| VUPKLSH = 2011, | |
| VUPKLSW = 2012, | |
| VXOR = 2013, | |
| V_SET0 = 2014, | |
| V_SET0B = 2015, | |
| V_SET0H = 2016, | |
| V_SETALLONES = 2017, | |
| V_SETALLONESB = 2018, | |
| V_SETALLONESH = 2019, | |
| WAIT = 2020, | |
| WRTEE = 2021, | |
| WRTEEI = 2022, | |
| XOR = 2023, | |
| XOR8 = 2024, | |
| XOR8_rec = 2025, | |
| XORI = 2026, | |
| XORI8 = 2027, | |
| XORIS = 2028, | |
| XORIS8 = 2029, | |
| XOR_rec = 2030, | |
| XSABSDP = 2031, | |
| XSABSQP = 2032, | |
| XSADDDP = 2033, | |
| XSADDQP = 2034, | |
| XSADDQPO = 2035, | |
| XSADDSP = 2036, | |
| XSCMPEQDP = 2037, | |
| XSCMPEXPDP = 2038, | |
| XSCMPEXPQP = 2039, | |
| XSCMPGEDP = 2040, | |
| XSCMPGTDP = 2041, | |
| XSCMPODP = 2042, | |
| XSCMPOQP = 2043, | |
| XSCMPUDP = 2044, | |
| XSCMPUQP = 2045, | |
| XSCPSGNDP = 2046, | |
| XSCPSGNQP = 2047, | |
| XSCVDPHP = 2048, | |
| XSCVDPQP = 2049, | |
| XSCVDPSP = 2050, | |
| XSCVDPSPN = 2051, | |
| XSCVDPSXDS = 2052, | |
| XSCVDPSXDSs = 2053, | |
| XSCVDPSXWS = 2054, | |
| XSCVDPSXWSs = 2055, | |
| XSCVDPUXDS = 2056, | |
| XSCVDPUXDSs = 2057, | |
| XSCVDPUXWS = 2058, | |
| XSCVDPUXWSs = 2059, | |
| XSCVHPDP = 2060, | |
| XSCVQPDP = 2061, | |
| XSCVQPDPO = 2062, | |
| XSCVQPSDZ = 2063, | |
| XSCVQPSWZ = 2064, | |
| XSCVQPUDZ = 2065, | |
| XSCVQPUWZ = 2066, | |
| XSCVSDQP = 2067, | |
| XSCVSPDP = 2068, | |
| XSCVSPDPN = 2069, | |
| XSCVSXDDP = 2070, | |
| XSCVSXDSP = 2071, | |
| XSCVUDQP = 2072, | |
| XSCVUXDDP = 2073, | |
| XSCVUXDSP = 2074, | |
| XSDIVDP = 2075, | |
| XSDIVQP = 2076, | |
| XSDIVQPO = 2077, | |
| XSDIVSP = 2078, | |
| XSIEXPDP = 2079, | |
| XSIEXPQP = 2080, | |
| XSMADDADP = 2081, | |
| XSMADDASP = 2082, | |
| XSMADDMDP = 2083, | |
| XSMADDMSP = 2084, | |
| XSMADDQP = 2085, | |
| XSMADDQPO = 2086, | |
| XSMAXCDP = 2087, | |
| XSMAXDP = 2088, | |
| XSMAXJDP = 2089, | |
| XSMINCDP = 2090, | |
| XSMINDP = 2091, | |
| XSMINJDP = 2092, | |
| XSMSUBADP = 2093, | |
| XSMSUBASP = 2094, | |
| XSMSUBMDP = 2095, | |
| XSMSUBMSP = 2096, | |
| XSMSUBQP = 2097, | |
| XSMSUBQPO = 2098, | |
| XSMULDP = 2099, | |
| XSMULQP = 2100, | |
| XSMULQPO = 2101, | |
| XSMULSP = 2102, | |
| XSNABSDP = 2103, | |
| XSNABSQP = 2104, | |
| XSNEGDP = 2105, | |
| XSNEGQP = 2106, | |
| XSNMADDADP = 2107, | |
| XSNMADDASP = 2108, | |
| XSNMADDMDP = 2109, | |
| XSNMADDMSP = 2110, | |
| XSNMADDQP = 2111, | |
| XSNMADDQPO = 2112, | |
| XSNMSUBADP = 2113, | |
| XSNMSUBASP = 2114, | |
| XSNMSUBMDP = 2115, | |
| XSNMSUBMSP = 2116, | |
| XSNMSUBQP = 2117, | |
| XSNMSUBQPO = 2118, | |
| XSRDPI = 2119, | |
| XSRDPIC = 2120, | |
| XSRDPIM = 2121, | |
| XSRDPIP = 2122, | |
| XSRDPIZ = 2123, | |
| XSREDP = 2124, | |
| XSRESP = 2125, | |
| XSRQPI = 2126, | |
| XSRQPIX = 2127, | |
| XSRQPXP = 2128, | |
| XSRSP = 2129, | |
| XSRSQRTEDP = 2130, | |
| XSRSQRTESP = 2131, | |
| XSSQRTDP = 2132, | |
| XSSQRTQP = 2133, | |
| XSSQRTQPO = 2134, | |
| XSSQRTSP = 2135, | |
| XSSUBDP = 2136, | |
| XSSUBQP = 2137, | |
| XSSUBQPO = 2138, | |
| XSSUBSP = 2139, | |
| XSTDIVDP = 2140, | |
| XSTSQRTDP = 2141, | |
| XSTSTDCDP = 2142, | |
| XSTSTDCQP = 2143, | |
| XSTSTDCSP = 2144, | |
| XSXEXPDP = 2145, | |
| XSXEXPQP = 2146, | |
| XSXSIGDP = 2147, | |
| XSXSIGQP = 2148, | |
| XVABSDP = 2149, | |
| XVABSSP = 2150, | |
| XVADDDP = 2151, | |
| XVADDSP = 2152, | |
| XVCMPEQDP = 2153, | |
| XVCMPEQDP_rec = 2154, | |
| XVCMPEQSP = 2155, | |
| XVCMPEQSP_rec = 2156, | |
| XVCMPGEDP = 2157, | |
| XVCMPGEDP_rec = 2158, | |
| XVCMPGESP = 2159, | |
| XVCMPGESP_rec = 2160, | |
| XVCMPGTDP = 2161, | |
| XVCMPGTDP_rec = 2162, | |
| XVCMPGTSP = 2163, | |
| XVCMPGTSP_rec = 2164, | |
| XVCPSGNDP = 2165, | |
| XVCPSGNSP = 2166, | |
| XVCVDPSP = 2167, | |
| XVCVDPSXDS = 2168, | |
| XVCVDPSXWS = 2169, | |
| XVCVDPUXDS = 2170, | |
| XVCVDPUXWS = 2171, | |
| XVCVHPSP = 2172, | |
| XVCVSPDP = 2173, | |
| XVCVSPHP = 2174, | |
| XVCVSPSXDS = 2175, | |
| XVCVSPSXWS = 2176, | |
| XVCVSPUXDS = 2177, | |
| XVCVSPUXWS = 2178, | |
| XVCVSXDDP = 2179, | |
| XVCVSXDSP = 2180, | |
| XVCVSXWDP = 2181, | |
| XVCVSXWSP = 2182, | |
| XVCVUXDDP = 2183, | |
| XVCVUXDSP = 2184, | |
| XVCVUXWDP = 2185, | |
| XVCVUXWSP = 2186, | |
| XVDIVDP = 2187, | |
| XVDIVSP = 2188, | |
| XVIEXPDP = 2189, | |
| XVIEXPSP = 2190, | |
| XVMADDADP = 2191, | |
| XVMADDASP = 2192, | |
| XVMADDMDP = 2193, | |
| XVMADDMSP = 2194, | |
| XVMAXDP = 2195, | |
| XVMAXSP = 2196, | |
| XVMINDP = 2197, | |
| XVMINSP = 2198, | |
| XVMSUBADP = 2199, | |
| XVMSUBASP = 2200, | |
| XVMSUBMDP = 2201, | |
| XVMSUBMSP = 2202, | |
| XVMULDP = 2203, | |
| XVMULSP = 2204, | |
| XVNABSDP = 2205, | |
| XVNABSSP = 2206, | |
| XVNEGDP = 2207, | |
| XVNEGSP = 2208, | |
| XVNMADDADP = 2209, | |
| XVNMADDASP = 2210, | |
| XVNMADDMDP = 2211, | |
| XVNMADDMSP = 2212, | |
| XVNMSUBADP = 2213, | |
| XVNMSUBASP = 2214, | |
| XVNMSUBMDP = 2215, | |
| XVNMSUBMSP = 2216, | |
| XVRDPI = 2217, | |
| XVRDPIC = 2218, | |
| XVRDPIM = 2219, | |
| XVRDPIP = 2220, | |
| XVRDPIZ = 2221, | |
| XVREDP = 2222, | |
| XVRESP = 2223, | |
| XVRSPI = 2224, | |
| XVRSPIC = 2225, | |
| XVRSPIM = 2226, | |
| XVRSPIP = 2227, | |
| XVRSPIZ = 2228, | |
| XVRSQRTEDP = 2229, | |
| XVRSQRTESP = 2230, | |
| XVSQRTDP = 2231, | |
| XVSQRTSP = 2232, | |
| XVSUBDP = 2233, | |
| XVSUBSP = 2234, | |
| XVTDIVDP = 2235, | |
| XVTDIVSP = 2236, | |
| XVTSQRTDP = 2237, | |
| XVTSQRTSP = 2238, | |
| XVTSTDCDP = 2239, | |
| XVTSTDCSP = 2240, | |
| XVXEXPDP = 2241, | |
| XVXEXPSP = 2242, | |
| XVXSIGDP = 2243, | |
| XVXSIGSP = 2244, | |
| XXBRD = 2245, | |
| XXBRH = 2246, | |
| XXBRQ = 2247, | |
| XXBRW = 2248, | |
| XXEXTRACTUW = 2249, | |
| XXINSERTW = 2250, | |
| XXLAND = 2251, | |
| XXLANDC = 2252, | |
| XXLEQV = 2253, | |
| XXLEQVOnes = 2254, | |
| XXLNAND = 2255, | |
| XXLNOR = 2256, | |
| XXLOR = 2257, | |
| XXLORC = 2258, | |
| XXLORf = 2259, | |
| XXLXOR = 2260, | |
| XXLXORdpz = 2261, | |
| XXLXORspz = 2262, | |
| XXLXORz = 2263, | |
| XXMRGHW = 2264, | |
| XXMRGLW = 2265, | |
| XXPERM = 2266, | |
| XXPERMDI = 2267, | |
| XXPERMDIs = 2268, | |
| XXPERMR = 2269, | |
| XXSEL = 2270, | |
| XXSLDWI = 2271, | |
| XXSLDWIs = 2272, | |
| XXSPLTIB = 2273, | |
| XXSPLTW = 2274, | |
| XXSPLTWs = 2275, | |
| gBC = 2276, | |
| gBCA = 2277, | |
| gBCAat = 2278, | |
| gBCCTR = 2279, | |
| gBCCTRL = 2280, | |
| gBCL = 2281, | |
| gBCLA = 2282, | |
| gBCLAat = 2283, | |
| gBCLR = 2284, | |
| gBCLRL = 2285, | |
| gBCLat = 2286, | |
| gBCat = 2287, | |
| INSTRUCTION_LIST_END = 2288 | |
| }; | |
| } // end namespace PPC | |
| } // end namespace llvm | |
| #endif // GET_INSTRINFO_ENUM | |
| #ifdef GET_INSTRINFO_SCHED_ENUM | |
| #undef GET_INSTRINFO_SCHED_ENUM | |
| namespace llvm { | |
| namespace PPC { | |
| namespace Sched { | |
| enum { | |
| NoInstrModel = 0, | |
| IIC_LdStSync = 1, | |
| IIC_IntSimple = 2, | |
| IIC_IntGeneral = 3, | |
| IIC_BrB = 4, | |
| IIC_VecFP = 5, | |
| IIC_IntCompare = 6, | |
| IIC_SprABORT = 7, | |
| IIC_LdStCOPY = 8, | |
| IIC_LdStPASTE = 9, | |
| IIC_BrCR = 10, | |
| IIC_LdStLD = 11, | |
| IIC_LdStDCBF = 12, | |
| IIC_LdStLoad = 13, | |
| IIC_IntDivD = 14, | |
| IIC_IntDivW = 15, | |
| IIC_FPDGeneral = 16, | |
| IIC_FPAddSub = 17, | |
| IIC_FPDivD = 18, | |
| IIC_FPSGeneral = 19, | |
| IIC_FPCompare = 20, | |
| IIC_FPGeneral = 21, | |
| IIC_VecGeneral = 22, | |
| IIC_VecComplex = 23, | |
| IIC_LdStStore = 24, | |
| IIC_IntRotateDI = 25, | |
| IIC_FPDivS = 26, | |
| IIC_FPFused = 27, | |
| IIC_FPSqrtD = 28, | |
| IIC_FPSqrtS = 29, | |
| IIC_LdStICBI = 30, | |
| IIC_IntISEL = 31, | |
| IIC_SprISYNC = 32, | |
| IIC_LdStLWARX = 33, | |
| IIC_LdStLoadUpd = 34, | |
| IIC_LdStLoadUpdX = 35, | |
| IIC_LdStLDARX = 36, | |
| IIC_LdStLDU = 37, | |
| IIC_LdStLDUX = 38, | |
| IIC_LdStLFD = 39, | |
| IIC_LdStLFDU = 40, | |
| IIC_LdStLFDUX = 41, | |
| IIC_LdStLHA = 42, | |
| IIC_LdStLHAU = 43, | |
| IIC_LdStLHAUX = 44, | |
| IIC_LdStLMW = 45, | |
| IIC_LdStLWA = 46, | |
| IIC_IntMulHD = 47, | |
| IIC_BrMCR = 48, | |
| IIC_BrMCRX = 49, | |
| IIC_SprMFCR = 50, | |
| IIC_SprMFSPR = 51, | |
| IIC_IntMFFS = 52, | |
| IIC_SprMFMSR = 53, | |
| IIC_SprMFCRF = 54, | |
| IIC_SprMFPMR = 55, | |
| IIC_SprMFSR = 56, | |
| IIC_SprMFTB = 57, | |
| IIC_SprMSGSYNC = 58, | |
| IIC_SprMTSPR = 59, | |
| IIC_IntMTFSB0 = 60, | |
| IIC_SprMTMSR = 61, | |
| IIC_SprMTMSRD = 62, | |
| IIC_SprMTPMR = 63, | |
| IIC_SprMTSR = 64, | |
| IIC_IntMulHW = 65, | |
| IIC_IntMulHWU = 66, | |
| IIC_IntMulLI = 67, | |
| IIC_VecPerm = 68, | |
| IIC_LdStSTFD = 69, | |
| IIC_LdStSTFDU = 70, | |
| IIC_SprRFI = 71, | |
| IIC_IntRFID = 72, | |
| IIC_IntRotateD = 73, | |
| IIC_IntRotate = 74, | |
| IIC_SprSLBFEE = 75, | |
| IIC_SprSLBIA = 76, | |
| IIC_SprSLBIE = 77, | |
| IIC_SprSLBIEG = 78, | |
| IIC_SprSLBMFEE = 79, | |
| IIC_SprSLBMFEV = 80, | |
| IIC_SprSLBMTE = 81, | |
| IIC_SprSLBSYNC = 82, | |
| IIC_IntShift = 83, | |
| IIC_LdStSTWCX = 84, | |
| IIC_LdStSTU = 85, | |
| IIC_LdStSTUX = 86, | |
| IIC_LdStSTD = 87, | |
| IIC_LdStSTDCX = 88, | |
| IIC_SprSTOP = 89, | |
| IIC_IntTrapD = 90, | |
| IIC_SprTLBIA = 91, | |
| IIC_SprTLBIE = 92, | |
| IIC_SprTLBIEL = 93, | |
| IIC_SprTLBSYNC = 94, | |
| IIC_IntTrapW = 95, | |
| IIC_VecFPCompare = 96, | |
| VADDUBM_VADDUDM_VADDUHM_VADDUWM_VEXTSB2D_VEXTSB2Ds_VEXTSB2W_VEXTSB2Ws_VEXTSH2D_VEXTSH2Ds_VEXTSH2W_VEXTSH2Ws_VEXTSW2D_VEXTSW2Ds_VSLD_VSRD_VSUBUBM_VSUBUDM_VSUBUHM_VSUBUWM_VPOPCNTB_VPOPCNTH_VSRAD_MTVSRDD_VEQV_VNAND_VNEGD_VNEGW_VORC_XXLAND_XXLANDC_XXLEQV_XXLEQVOnes_XXLNAND_XXLNOR_XXLOR_XXLORf_XXLORC_XXLXOR_XXLXORdpz_XXLXORspz_XXLXORz = 97, | |
| VAND_VANDC_V_SET0_V_SET0B_V_SET0H_VSLB_VSLH_VSLW_VSRB_VSRH_VSRW_VRLB_VRLD_VRLH_VRLW_VSRAB_VSRAH_VSRAW_XVABSDP_XVABSSP_XVNABSDP_XVNABSSP_XVCPSGNDP_XVCPSGNSP_XVIEXPDP_XVIEXPSP_XVXEXPDP_XVXEXPSP_VRLDMI_VRLDNM_VRLWMI_VRLWNM_VMRGEW_VMRGOW_VNOR_VOR_VSEL_VXOR_XVNEGDP_XVNEGSP_XSABSQP_XSCPSGNQP_XSIEXPQP_XSNABSQP_XSNEGQP_XSXEXPQP = 98, | |
| XXSEL = 99, | |
| TABORTDC_TABORTDCI_TABORTWC_TABORTWCI = 100, | |
| MTFSB0_MTFSB1 = 101, | |
| MFFSCDRN_MFFSCDRNI_MFFSCRN_MFFSCRNI = 102, | |
| CMPRB_CMPRB8_CMPEQB = 103, | |
| TD_TDI = 104, | |
| TW_TWI = 105, | |
| FCMPUD_FCMPUS_FTDIV_FTSQRT = 106, | |
| XSTSTDCDP_XSTSTDCSP = 107, | |
| XSMAXCDP_XSMAXDP_XSMAXJDP_XSMINCDP_XSMINDP_XSMINJDP_XSXSIGDP_XSCVSPDPN = 108, | |
| XSCMPEQDP_XSCMPEXPDP_XSCMPGEDP_XSCMPGTDP_XSCMPODP_XSCMPUDP_XSTDIVDP_XSTSQRTDP = 109, | |
| CNTLZD_CNTLZD_rec_CNTLZW_CNTLZW8_CNTLZW8_rec_CNTLZW_rec_CNTTZD_CNTTZD_rec_CNTTZW_CNTTZW8_CNTTZW8_rec_CNTTZW_rec_POPCNTD_POPCNTW_CMPB_CMPB8_SETB_SETB8_BPERMD = 110, | |
| SLD_SRD_SRAD = 111, | |
| SRADI_EXTSWSLI_32_64_EXTSWSLI_SRADI_32_RLDIC = 112, | |
| MFVRD_MFVSRD_MTVRD_MTVSRD_MTVRWA_MTVRWZ_MTVSRWA_MTVSRWZ_MFVSRWZ_MFVRWZ = 113, | |
| CMPLW_CMPLWI_CMPW_CMPWI_CMPD_CMPDI_CMPLD_CMPLDI = 114, | |
| SUBFC_SUBFC8_SUBFC8O_SUBFCO_SUBFIC_SUBFIC8_ANDI8_rec_ANDIS8_rec_ANDIS_rec_ANDI_rec_ADDC_ADDC8_ADDC8O_ADDCO_ADDIC_ADDIC8_ADDIC_rec_ADDE_ADDE8_ADDE8O_ADDE8O_rec_ADDE8_rec_ADDEO_ADDEO_rec_ADDE_rec_ADDME_ADDME8_ADDME8O_ADDME8O_rec_ADDME8_rec_ADDMEO_ADDMEO_rec_ADDME_rec_ADDZE_ADDZE8_ADDZE8O_ADDZE8O_rec_ADDZE8_rec_ADDZEO_ADDZEO_rec_ADDZE_rec_SUBF_SUBF8_SUBF8O_SUBF8O_rec_SUBF8_rec_SUBFE_SUBFE8_SUBFE8O_SUBFE8O_rec_SUBFE8_rec_SUBFEO_SUBFEO_rec_SUBFE_rec_SUBFME_SUBFME8_SUBFME8O_SUBFME8O_rec_SUBFME8_rec_SUBFMEO_SUBFMEO_rec_SUBFME_rec_SUBFO_SUBFO_rec_SUBFZE_SUBFZE8_SUBFZE8O_SUBFZE8O_rec_SUBFZE8_rec_SUBFZEO_SUBFZEO_rec_SUBFZE_rec_SUBF_rec_POPCNTB_LA = 115, | |
| ADD4_ADD4O_ADD4O_rec_ADD4_rec_ADD8_ADD8O_ADD8O_rec_ADD8_rec_NEG_NEG8_NEG8O_NEG8O_rec_NEG8_rec_NEGO_NEGO_rec_NEG_rec_ADDI_ADDI8_ADDIS_ADDIS8_LI_LI8_LIS_LIS8_OR_OR8_OR8_rec_ORI_ORI8_ORIS_ORIS8_OR_rec_XOR_XOR8_XOR8_rec_XORI_XORI8_XORIS_XORIS8_XOR_rec_NAND_NAND8_NAND8_rec_NAND_rec_AND_AND8_AND8_rec_ANDC_ANDC8_ANDC8_rec_ANDC_rec_AND_rec_NOR_NOR8_NOR8_rec_NOR_rec_ORC_ORC8_ORC8_rec_ORC_rec_EQV_EQV8_EQV8_rec_EQV_rec_EXTSB_EXTSB8_EXTSB8_32_64_EXTSB8_rec_EXTSB_rec_EXTSH_EXTSH8_EXTSH8_32_64_EXTSH8_rec_EXTSH_rec_EXTSW_EXTSW_32_EXTSW_32_64_EXTSW_32_64_rec_EXTSW_rec_ADD4TLS_ADD8TLS_ADD8TLS__NOP = 116, | |
| ADDIStocHA_ADDIStocHA8_ADDItocL_COPY = 117, | |
| MCRF = 118, | |
| MCRXRX = 119, | |
| XSNABSDP_XSXEXPDP_XSABSDP_XSNEGDP_XSCPSGNDP = 120, | |
| RFEBB = 121, | |
| TBEGIN_TRECHKPT = 122, | |
| WAIT = 123, | |
| RLDCL_RLDCR = 124, | |
| RLWIMI_RLWIMI8 = 125, | |
| RLDICL_RLDICL_32_RLDICL_32_64_RLDICR_RLDICR_32_RLDIMI = 126, | |
| MFOCRF_MFOCRF8 = 127, | |
| MTOCRF_MTOCRF8 = 128, | |
| CR6SET_CR6UNSET_CRSET_CRUNSET_CRAND_CRANDC_CRNAND_CRNOR_CROR_CRORC_CREQV_CRXOR = 129, | |
| SLW_SLW8_SRW_SRW8_RLWINM_RLWINM8_RLWNM_RLWNM8 = 130, | |
| FABSD_FABSS_FNABSD_FNABSS_FNEGD_FNEGS_FCPSGND_FCPSGNS_FMR = 131, | |
| SRAW_SRAWI = 132, | |
| ISEL_ISEL8 = 133, | |
| XSIEXPDP = 134, | |
| TRECLAIM_TSR_TABORT = 135, | |
| MFVSCR = 136, | |
| MTVSCR = 137, | |
| VCMPNEZB_VCMPNEZH_VCMPNEZW_VCMPEQUB_VCMPEQUD_VCMPEQUH_VCMPEQUW_VCMPNEB_VCMPNEH_VCMPNEW_VCMPEQFP_VCMPEQFP_rec_VCMPGEFP_VCMPGEFP_rec_VCMPGTFP_VCMPGTFP_rec_VCMPBFP_VCMPBFP_rec_VCMPGTSB_VCMPGTSB_rec_VCMPGTSD_VCMPGTSD_rec_VCMPGTSH_VCMPGTSH_rec_VCMPGTSW_VCMPGTSW_rec_VCMPGTUB_VCMPGTUB_rec_VCMPGTUD_VCMPGTUD_rec_VCMPGTUH_VCMPGTUH_rec_VCMPGTUW_VCMPGTUW_rec_VCMPNEB_rec_VCMPNEH_rec_VCMPNEW_rec_VCMPNEZB_rec_VCMPNEZH_rec_VCMPNEZW_rec_VCMPEQUB_rec_VCMPEQUD_rec_VCMPEQUH_rec_VCMPEQUW_rec_XVCMPEQDP_XVCMPEQDP_rec_XVCMPEQSP_XVCMPEQSP_rec_XVCMPGEDP_XVCMPGEDP_rec_XVCMPGESP_XVCMPGESP_rec_XVCMPGTDP_XVCMPGTDP_rec_XVCMPGTSP_XVCMPGTSP_rec = 138, | |
| VABSDUB_VABSDUH_VABSDUW_VCLZB_VCLZD_VCLZH_VCLZW_VCTZB_VCTZD_VCTZH_VCTZW_VPOPCNTW_VPOPCNTD_VPRTYBD_VPRTYBW = 139, | |
| VADDUBS_VADDUHS_VADDUWS_VAVGSB_VAVGSH_VAVGSW_VAVGUB_VAVGUH_VAVGUW_VADDSBS_VADDSHS_VADDSWS_VMAXFP_VMINFP_VMAXSB_VMAXSD_VMAXSH_VMAXSW_VMAXUB_VMAXUD_VMAXUH_VMAXUW_VMINSB_VMINSD_VMINSH_VMINSW_VMINUB_VMINUD_VMINUH_VMINUW_VBPERMD_VADDCUW_VSHASIGMAD_VSHASIGMAW_VSUBSBS_VSUBSHS_VSUBSWS_VSUBUBS_VSUBUHS_VSUBUWS_VSUBCUW_XVMAXDP_XVMAXSP_XVMINDP_XVMINSP_XVTSTDCDP_XVTSTDCSP_XVXSIGDP_XVXSIGSP = 140, | |
| XVTDIVDP_XVTDIVSP_XVTSQRTDP_XVTSQRTSP = 141, | |
| VADDFP_VCTSXS_VCTSXS_0_VCTUXS_VCTUXS_0_VEXPTEFP_VLOGEFP_VMADDFP_VMHADDSHS_VNMSUBFP_VREFP_VRFIM_VRFIN_VRFIP_VRFIZ_VRSQRTEFP_XVADDDP_XVADDSP_XVCVDPSP_XVCVDPSXDS_XVCVDPSXWS_XVCVDPUXDS_XVCVDPUXWS_XVCVHPSP_XVCVSPDP_XVCVSPHP_XVCVSPSXDS_XVCVSPSXWS_XVCVSPUXDS_XVCVSPUXWS_XVCVSXDDP_XVCVSXDSP_XVCVSXWDP_XVCVSXWSP_XVCVUXDDP_XVCVUXDSP_XVCVUXWDP_XVCVUXWSP_XVMADDADP_XVMADDASP_XVMADDMDP_XVMADDMSP_XVMSUBADP_XVMSUBASP_XVMSUBMDP_XVMSUBMSP_XVMULDP_XVMULSP_XVNMADDADP_XVNMADDASP_XVNMADDMDP_XVNMADDMSP_XVNMSUBADP_XVNMSUBASP_XVNMSUBMDP_XVNMSUBMSP_XVRDPI_XVRDPIC_XVRDPIM_XVRDPIP_XVRDPIZ_XVREDP_XVRESP_XVRSPI_XVRSPIC_XVRSPIM_XVRSPIP_XVRSPIZ_XVRSQRTEDP_XVRSQRTESP_XVSUBDP_XVSUBSP_VCFSX_VCFSX_0_VCFUX_VCFUX_0_VMHRADDSHS_VMLADDUHM_VMSUMMBM_VMSUMSHM_VMSUMSHS_VMSUMUBM_VMSUMUHM_VMSUMUHS_VMULESB_VMULESH_VMULESW_VMULEUB_VMULEUH_VMULEUW_VMULOSB_VMULOSH_VMULOSW_VMULOUB_VMULOUH_VMULOUW_VSUM2SWS_VSUM4SBS_VSUM4SHS_VSUM4UBS_VSUMSWS = 142, | |
| VSUBFP_VMULUWM = 143, | |
| MADDHD_MADDHDU_MADDLD_MADDLD8_MULLD_MULLDO = 144, | |
| MULHD_MULHW_MULLW_MULLWO = 145, | |
| MULHDU_MULHWU = 146, | |
| MULLI_MULLI8 = 147, | |
| FRSP_FRIMD_FRIMS_FRIND_FRINS_FRIPD_FRIPS_FRIZD_FRIZS_FRE_FRES_FADDS_FMSUBS_FMADDS_FSUBS_FCFID_FCFIDS_FCFIDU_FCFIDUS_FCTID_FCTIDU_FCTIDUZ_FCTIDZ_FCTIW_FCTIWU_FCTIWUZ_FCTIWZ_FRSQRTE_FRSQRTES_FNMADDS_FNMSUBS_FSELD_FSELS_FMULS = 148, | |
| FADD_FSUB = 149, | |
| FMSUB_FMADD_FNMADD_FNMSUB_FMUL = 150, | |
| XSMADDADP_XSMADDASP_XSMADDMDP_XSMADDMSP_XSMSUBADP_XSMSUBASP_XSMSUBMDP_XSMSUBMSP_XSMULDP_XSMULSP_XSNMADDADP_XSNMADDASP_XSNMADDMDP_XSNMADDMSP_XSNMSUBADP_XSNMSUBASP_XSNMSUBMDP_XSNMSUBMSP = 151, | |
| FSELD_rec_FSELS_rec = 152, | |
| MULHDU_rec_MULHWU_rec = 153, | |
| MULHD_rec_MULHW_rec_MULLWO_rec_MULLW_rec = 154, | |
| MULLDO_rec_MULLD_rec = 155, | |
| FRIMD_rec_FRIMS_rec_FRIND_rec_FRINS_rec_FRIPD_rec_FRIPS_rec_FRIZD_rec_FRIZS_rec_FRES_rec_FRE_rec_FADDS_rec_FSUBS_rec_FMSUBS_rec_FNMSUBS_rec_FMADDS_rec_FNMADDS_rec_FCFIDS_rec_FCFIDUS_rec_FCFIDU_rec_FCFID_rec_FCTIDUZ_rec_FCTIDU_rec_FCTIDZ_rec_FCTID_rec_FCTIWUZ_rec_FCTIWU_rec_FCTIWZ_rec_FCTIW_rec_FMULS_rec_FRSQRTES_rec_FRSQRTE_rec_FRSP_rec = 156, | |
| FADD_rec_FSUB_rec = 157, | |
| FMSUB_rec_FNMSUB_rec_FMADD_rec_FNMADD_rec_FMUL_rec = 158, | |
| XSADDDP_XSADDSP_XSCVDPHP_XSCVDPSP_XSCVDPSXDS_XSCVDPSXDSs_XSCVDPSXWS_XSCVDPUXDS_XSCVDPUXDSs_XSCVDPUXWS_XSCVDPSXWSs_XSCVDPUXWSs_XSCVHPDP_XSCVSPDP_XSCVSXDDP_XSCVSXDSP_XSCVUXDDP_XSCVUXDSP_XSRDPI_XSRDPIC_XSRDPIM_XSRDPIP_XSRDPIZ_XSREDP_XSRESP_XSRSQRTEDP_XSRSQRTESP_XSSUBDP_XSSUBSP_XSCVDPSPN_XSRSP = 159, | |
| LVSL_LVSR = 160, | |
| VSPLTISB_VSPLTISH_VSPLTISW_VSPLTB_VSPLTBs_VSPLTH_VSPLTHs_VSPLTW_XXMRGHW_XXMRGLW_XXPERM_XXPERMR_XXSLDWI_XXSLDWIs_XXSPLTIB_XXSPLTW_XXSPLTWs_XXPERMDI_XXPERMDIs = 161, | |
| V_SETALLONES_V_SETALLONESB_V_SETALLONESH_VBPERMQ_VGBBD_VMRGHB_VMRGHH_VMRGHW_VMRGLB_VMRGLH_VMRGLW_VPERM_VPERMR_VPERMXOR_VPKPX_VPKSDSS_VPKSDUS_VPKSHSS_VPKSHUS_VPKSWSS_VPKSWUS_VPKUDUM_VPKUDUS_VPKUHUM_VPKUHUS_VPKUWUM_VPKUWUS_VSL_VSLDOI_VSLO_VSLV_VSR_VSRO_VSRV_VUPKHPX_VUPKHSB_VUPKHSH_VUPKHSW_VUPKLPX_VUPKLSB_VUPKLSH_VUPKLSW_XXBRD_XXBRH_XXBRQ_XXBRW_XXEXTRACTUW_XXINSERTW_VADDCUQ_VADDECUQ_VADDEUQM_VMUL10CUQ_VMUL10ECUQ_VMUL10EUQ_VMUL10UQ_VSUBCUQ_VSUBECUQ_VSUBEUQM_XSTSTDCQP_XSXSIGQP_BCDCFN_rec_BCDCFZ_rec_BCDCPSGN_rec_BCDCTN_rec_BCDCTZ_rec_BCDSETSGN_rec_BCDS_rec_BCDTRUNC_rec_BCDUS_rec_BCDUTRUNC_rec = 162, | |
| VEXTRACTUB_VEXTRACTUH_VEXTRACTUW_VINSERTB_VINSERTD_VINSERTH_VINSERTW_MFVSRLD_MTVSRWS_VCLZLSBB_VCTZLSBB_VEXTRACTD_VEXTUBLX_VEXTUBRX_VEXTUHLX_VEXTUHRX_VEXTUWLX_VEXTUWRX_VPRTYBQ_VADDUQM_VSUBUQM = 163, | |
| XSCMPEXPQP_XSCMPOQP_XSCMPUQP = 164, | |
| BCDSR_rec_XSADDQP_XSADDQPO_XSCVDPQP_XSCVQPDP_XSCVQPDPO_XSCVQPSDZ_XSCVQPSWZ_XSCVQPUDZ_XSCVQPUWZ_XSCVSDQP_XSCVUDQP_XSRQPI_XSRQPIX_XSRQPXP_XSSUBQP_XSSUBQPO = 165, | |
| BCDCTSQ_rec = 166, | |
| XSMADDQP_XSMADDQPO_XSMSUBQP_XSMSUBQPO_XSMULQP_XSMULQPO_XSNMADDQP_XSNMADDQPO_XSNMSUBQP_XSNMSUBQPO = 167, | |
| BCDCFSQ_rec = 168, | |
| XSDIVQP_XSDIVQPO = 169, | |
| XSSQRTQP_XSSQRTQPO = 170, | |
| LXVL_LXVLL = 171, | |
| LVEBX_LVEHX_LVEWX_LVX_LVXL = 172, | |
| LXSIBZX_LXSIHZX_LXSDX_LXVB16X_LXVD2X_LXVWSX_LXSIWZX_LXV_LXVX_LXSD = 173, | |
| DFLOADf64_XFLOADf64_LIWZX = 174, | |
| DCBF_DCBFEP_DCBST_DCBSTEP_DCBT_DCBTEP_DCBZ_DCBZEP_DCBZL_DCBZLEP_DCBTST_DCBTSTEP = 175, | |
| CP_COPY_CP_COPY8 = 176, | |
| CP_PASTE_CP_PASTE8 = 177, | |
| ICBI_ICBIEP = 178, | |
| ICBT_ICBTLS_LBZ_LBZ8_LBZCIX_LBZX_LBZX8_LBZXTLS_LBZXTLS__LBZXTLS_32_LDBRX_LDCIX_LHBRX_LHBRX8_LHZ_LHZ8_LHZCIX_LHZX_LHZX8_LHZXTLS_LHZXTLS__LHZXTLS_32_LWBRX_LWBRX8_LWZ_LWZ8_LWZCIX_LWZX_LWZX8_LWZXTLS_LWZXTLS__LWZXTLS_32_EnforceIEIO_LSWI = 179, | |
| LBARX_LBARXL_LHARX_LHARXL_LWARX_LWARXL = 180, | |
| LD_LDX_LDXTLS_LDXTLS__DARN = 181, | |
| LDARX_LDARXL = 182, | |
| CP_ABORT = 183, | |
| ISYNC = 184, | |
| MSGSYNC = 185, | |
| TLBSYNC = 186, | |
| SYNC = 187, | |
| LMW = 188, | |
| LFIWZX_LFDX_LFD = 189, | |
| SLBIA = 190, | |
| SLBIE = 191, | |
| SLBMFEE = 192, | |
| SLBMFEV = 193, | |
| SLBMTE = 194, | |
| TLBIEL = 195, | |
| LHZU_LHZU8_LWZU_LWZU8 = 196, | |
| LHZUX_LHZUX8_LWZUX_LWZUX8 = 197, | |
| TEND = 198, | |
| STBCX_STHCX_STWCX = 199, | |
| STDCX = 200, | |
| LDMX = 201, | |
| LHA_LHA8_LHAX_LHAX8_LWAX_LWAX_32 = 202, | |
| CP_PASTE8_rec_CP_PASTE_rec = 203, | |
| LWA_LWA_32 = 204, | |
| TCHECK = 205, | |
| LFIWAX = 206, | |
| LXSIWAX = 207, | |
| LIWAX = 208, | |
| LFSX_LFS = 209, | |
| LXSSP_LXSSPX = 210, | |
| XFLOADf32_DFLOADf32 = 211, | |
| LHAU_LHAU8 = 212, | |
| LHAUX_LHAUX8_LWAUX = 213, | |
| LXVH8X_LXVDSX_LXVW4X = 214, | |
| STFD_STFDX_STFIWX_STFS_STFSX_STXSD_STXSDX_STXSIBX_STXSIBXv_STXSIHX_STXSIHXv_STXSIWX_STXSSP_STXSSPX = 215, | |
| STW_STW8_STDBRX_STHBRX_STWBRX_STB_STB8_STH_STH8_STBX_STBX8_STBXTLS_STBXTLS__STBXTLS_32_STHX_STHX8_STHXTLS_STHXTLS__STHXTLS_32_STWX_STWX8_STWXTLS_STWXTLS__STWXTLS_32 = 216, | |
| DFSTOREf32_DFSTOREf64_XFSTOREf32_XFSTOREf64_STIWX = 217, | |
| STD_STDX_STDXTLS_STDXTLS_ = 218, | |
| STBCIX_STDCIX_STHCIX_STWCIX_STSWI = 219, | |
| SLBIEG = 220, | |
| STMW = 221, | |
| TLBIE = 222, | |
| STVEBX_STVEHX_STVEWX_STVX_STVXL = 223, | |
| STXV_STXVB16X_STXVD2X_STXVH8X_STXVW4X_STXVX = 224, | |
| STXVL_STXVLL = 225, | |
| MTCTR_MTCTR8_MTCTR8loop_MTCTRloop_MTLR_MTLR8 = 226, | |
| MFVRSAVE_MFVRSAVEv_MTVRSAVE_MTVRSAVEv = 227, | |
| MFPMR = 228, | |
| MTPMR = 229, | |
| MFTB_MFTB8 = 230, | |
| MFCTR_MFCTR8_MFLR_MFLR8_MFSPR_MFSPR8 = 231, | |
| MFMSR = 232, | |
| MTMSR = 233, | |
| MTMSRD = 234, | |
| MTSPR_MTSPR8 = 235, | |
| DIVW_DIVWO_DIVWU_DIVWUO_MODSW = 236, | |
| DIVWE_DIVWEO_DIVWEU_DIVWEUO_MODSD_MODUD_MODUW = 237, | |
| DIVD_DIVDO_DIVDU_DIVDUO = 238, | |
| DIVDE_DIVDEO_DIVDEU_DIVDEUO = 239, | |
| DIVWO_rec_DIVWUO_rec_DIVWU_rec_DIVW_rec = 240, | |
| DIVD_rec_DIVDO_rec_DIVDU_rec_DIVDUO_rec = 241, | |
| DIVWE_rec_DIVWEO_rec_DIVWEU_rec_DIVWEUO_rec = 242, | |
| DIVDE_rec_DIVDEO_rec_DIVDEU_rec_DIVDEUO_rec = 243, | |
| MTCRF_MTCRF8 = 244, | |
| ADDC8O_rec_ADDC8_rec_ADDCO_rec_ADDC_rec_SUBFC8O_rec_SUBFC8_rec_SUBFCO_rec_SUBFC_rec = 245, | |
| FABSD_rec_FABSS_rec_FNABSD_rec_FNABSS_rec_FCPSGND_rec_FCPSGNS_rec_FNEGD_rec_FNEGS_rec_FMR_rec = 246, | |
| MCRFS = 247, | |
| MTFSF_MTFSF_rec_MTFSFI_MTFSFI_rec = 248, | |
| MTFSFb = 249, | |
| RLDCL_rec_RLDCR_rec = 250, | |
| RLDICL_rec_RLDICR_rec_RLDICL_32_rec_RLDIMI_rec = 251, | |
| RLWIMI8_rec_RLWIMI_rec = 252, | |
| RLWINM8_rec_RLWINM_rec_RLWNM8_rec_RLWNM_rec_SLW8_rec_SLW_rec_SRW8_rec_SRW_rec = 253, | |
| SRAWI_rec_SRAW_rec = 254, | |
| MFFS_MFFSCE_MFFSL_MFFS_rec = 255, | |
| MFCR_MFCR8 = 256, | |
| EXTSWSLI_32_64_rec_SRADI_rec_EXTSWSLI_rec_RLDIC_rec = 257, | |
| SRAD_rec_SLD_rec_SRD_rec = 258, | |
| FDIV = 259, | |
| FDIV_rec = 260, | |
| XSSQRTDP = 261, | |
| FSQRT = 262, | |
| XVSQRTDP = 263, | |
| XVSQRTSP = 264, | |
| FSQRT_rec = 265, | |
| XSSQRTSP = 266, | |
| FSQRTS = 267, | |
| FSQRTS_rec = 268, | |
| XSDIVDP = 269, | |
| FDIVS = 270, | |
| FDIVS_rec = 271, | |
| XSDIVSP = 272, | |
| XVDIVSP = 273, | |
| XVDIVDP = 274, | |
| LFSU = 275, | |
| LFSUX = 276, | |
| STFDU_STFDUX_STFSU_STFSUX = 277, | |
| STBU_STBU8_STDU_STHU_STHU8_STWU_STWU8 = 278, | |
| STBUX_STBUX8_STDUX_STHUX_STHUX8_STWUX_STWUX8 = 279, | |
| LBZU_LBZU8 = 280, | |
| LBZUX_LBZUX8 = 281, | |
| LDU = 282, | |
| LDUX = 283, | |
| LFDU = 284, | |
| LFDUX = 285, | |
| VPMSUMB_VPMSUMD_VPMSUMH_VPMSUMW_VCIPHER_VCIPHERLAST_VNCIPHER_VNCIPHERLAST_VSBOX = 286, | |
| BCCCTR_BCCCTR8_BCCCTRL_BCCCTRL8_BCCL_BCCLA_BCCLR_BCCLRL_BCCTR_BCCTR8_BCCTR8n_BCCTRL_BCCTRL8_BCCTRL8n_BCCTRLn_BCCTRn_BDNZ_BDNZ8_BDNZA_BDNZAm_BDNZAp_BDNZm_BDNZp_BDZ_BDZ8_BDZA_BDZAm_BDZAp_BDZm_BDZp_BDNZL_BDNZLA_BDNZLAm_BDNZLAp_BDNZLR_BDNZLR8_BDNZLRL_BDNZLRLm_BDNZLRLp_BDNZLRm_BDNZLRp_BDNZLm_BDNZLp_BDZL_BDZLA_BDZLAm_BDZLAp_BDZLR_BDZLR8_BDZLRL_BDZLRLm_BDZLRLp_BDZLRm_BDZLRp_BDZLm_BDZLp_BL_BL_NOP_BL_TLS_BL8_BL8_NOP_BL8_NOP_TLS_BL8_TLS_BL8_TLS__BLA_BLA8_BLA8_NOP_BLR_BLR8_BLRL_TAILB_TAILB8_TAILBA_TAILBA8_TAILBCTR_TAILBCTR8_gBC_gBCA_gBCAat_gBCCTR_gBCCTRL_gBCL_gBCLA_gBCLAat_gBCLR_gBCLRL_gBCLat_gBCat_BCLR_BCLRL_BCLRLn_BCLRn_BCTR_BCTR8_BCTRL_BCTRL8_B_BA_BC_BCC_BCCA_BCL_BCLalways_BCLn_BCTRL8_LDinto_toc_BCTRL_LWZinto_toc_BCn_CTRL_DEP = 287, | |
| ADDPCIS = 288, | |
| LDAT_LWAT = 289, | |
| STDAT_STWAT = 290, | |
| BRINC = 291, | |
| EVABS_EVEQV_EVNAND_EVNEG_EVADDIW_EVADDW_EVAND_EVANDC_EVCMPEQ_EVCMPGTS_EVCMPGTU_EVCMPLTS_EVCMPLTU_EVCNTLSW_EVCNTLZW_EVEXTSB_EVEXTSH_EVMERGEHI_EVMERGEHILO_EVMERGELO_EVMERGELOHI_EVNOR_EVOR_EVORC_EVXOR_EVRLW_EVRLWI_EVRNDW_EVSLW_EVSLWI_EVSPLATFI_EVSPLATI_EVSRWIS_EVSRWIU_EVSRWS_EVSRWU_EVSUBFW_EVSUBIFW = 292, | |
| EVMRA_EVADDSMIAAW_EVADDSSIAAW_EVADDUMIAAW_EVADDUSIAAW_EVDIVWS_EVDIVWU_EVMHEGSMFAA_EVMHEGSMFAN_EVMHEGSMIAA_EVMHEGSMIAN_EVMHEGUMIAA_EVMHEGUMIAN_EVMHESMF_EVMHESMFA_EVMHESMFAAW_EVMHESMFANW_EVMHESMI_EVMHESMIA_EVMHESMIAAW_EVMHESMIANW_EVMHESSF_EVMHESSFA_EVMHESSFAAW_EVMHESSFANW_EVMHESSIAAW_EVMHESSIANW_EVMHEUMI_EVMHEUMIA_EVMHEUMIAAW_EVMHEUMIANW_EVMHEUSIAAW_EVMHEUSIANW_EVMHOGSMFAA_EVMHOGSMFAN_EVMHOGSMIAA_EVMHOGSMIAN_EVMHOGUMIAA_EVMHOGUMIAN_EVMHOSMF_EVMHOSMFA_EVMHOSMFAAW_EVMHOSMFANW_EVMHOSMI_EVMHOSMIA_EVMHOSMIAAW_EVMHOSMIANW_EVMHOSSF_EVMHOSSFA_EVMHOSSFAAW_EVMHOSSFANW_EVMHOSSIAAW_EVMHOSSIANW_EVMHOUMI_EVMHOUMIA_EVMHOUMIAAW_EVMHOUMIANW_EVMHOUSIAAW_EVMHOUSIANW_EVMWHSMF_EVMWHSMFA_EVMWHSMI_EVMWHSMIA_EVMWHSSF_EVMWHSSFA_EVMWHUMI_EVMWHUMIA_EVMWLSMIAAW_EVMWLSMIANW_EVMWLSSIAAW_EVMWLSSIANW_EVMWLUMI_EVMWLUMIA_EVMWLUMIAAW_EVMWLUMIANW_EVMWLUSIAAW_EVMWLUSIANW_EVMWSMF_EVMWSMFA_EVMWSMFAA_EVMWSMFAN_EVMWSMI_EVMWSMIA_EVMWSMIAA_EVMWSMIAN_EVMWSSF_EVMWSSFA_EVMWSSFAA_EVMWSSFAN_EVMWUMI_EVMWUMIA_EVMWUMIAA_EVMWUMIAN_EVSUBFSMIAAW_EVSUBFSSIAAW_EVSUBFUMIAAW_EVSUBFUSIAAW = 293, | |
| EVLDD_EVLDDX_EVLDH_EVLDHX_EVLDW_EVLDWX_EVLHHESPLAT_EVLHHESPLATX_EVLHHOSSPLAT_EVLHHOSSPLATX_EVLHHOUSPLAT_EVLHHOUSPLATX_EVLWHE_EVLWHEX_EVLWHOS_EVLWHOSX_EVLWHOU_EVLWHOUX_EVLWHSPLAT_EVLWHSPLATX_EVLWWSPLAT_EVLWWSPLATX = 294, | |
| EVSTDD_EVSTDDX_EVSTDH_EVSTDHX_EVSTDW_EVSTDWX_EVSTWHE_EVSTWHEX_EVSTWHO_EVSTWHOX_EVSTWWE_EVSTWWEX_EVSTWWO_EVSTWWOX = 295, | |
| HRFID_ATTN_CLRBHRB_MFBHRBE_NAP_RFCI_RFDI_RFMCI_SC = 296, | |
| RFI = 297, | |
| RFID = 298, | |
| DSS_DSSALL_DST_DST64_DSTST_DSTST64_DSTSTT_DSTSTT64_DSTT_DSTT64_ICBLQ_LBEPX_LHEPX_LWEPX_TLBIVAX_TLBLD_TLBLI_TLBRE_TLBRE2_TLBSX_TLBSX2_TLBSX2D_TLBWE_TLBWE2_MBAR_TRAP_DCCCI_ICCCI = 299, | |
| ICBLC_STBEPX_STHEPX_STWEPX = 300, | |
| LFDEPX = 301, | |
| STFDEPX = 302, | |
| MFSR_MFSRIN = 303, | |
| MTSR_MTSRIN = 304, | |
| MFDCR = 305, | |
| MTDCR = 306, | |
| NOP_GT_PWR6_NOP_GT_PWR7 = 307, | |
| TLBIA = 308, | |
| WRTEE_WRTEEI = 309, | |
| MSYNC = 310, | |
| SLBSYNC = 311, | |
| SLBFEE_rec = 312, | |
| STOP = 313, | |
| DCBA_DCBI = 314, | |
| SCHED_LIST_END = 315 | |
| }; | |
| } // end namespace Sched | |
| } // end namespace PPC | |
| } // end namespace llvm | |
| #endif // GET_INSTRINFO_SCHED_ENUM | |
| #ifdef GET_INSTRINFO_MC_DESC | |
| #undef GET_INSTRINFO_MC_DESC | |
| namespace llvm { | |
| static const MCPhysReg ImplicitList1[] = { PPC::CR7, 0 }; | |
| static const MCPhysReg ImplicitList2[] = { PPC::XER, 0 }; | |
| static const MCPhysReg ImplicitList3[] = { PPC::XER, PPC::CR0, 0 }; | |
| static const MCPhysReg ImplicitList4[] = { PPC::CR0, 0 }; | |
| static const MCPhysReg ImplicitList5[] = { PPC::CARRY, 0 }; | |
| static const MCPhysReg ImplicitList6[] = { PPC::CARRY, PPC::XER, 0 }; | |
| static const MCPhysReg ImplicitList7[] = { PPC::CARRY, PPC::XER, PPC::CR0, 0 }; | |
| static const MCPhysReg ImplicitList8[] = { PPC::CARRY, PPC::CR0, 0 }; | |
| static const MCPhysReg ImplicitList9[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::LR8, PPC::CTR8, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, 0 }; | |
| static const MCPhysReg ImplicitList10[] = { PPC::R0, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, 0 }; | |
| static const MCPhysReg ImplicitList11[] = { PPC::R1, 0 }; | |
| static const MCPhysReg ImplicitList12[] = { PPC::CTR, 0 }; | |
| static const MCPhysReg ImplicitList13[] = { PPC::CTR8, 0 }; | |
| static const MCPhysReg ImplicitList14[] = { PPC::CTR, PPC::RM, 0 }; | |
| static const MCPhysReg ImplicitList15[] = { PPC::LR, 0 }; | |
| static const MCPhysReg ImplicitList16[] = { PPC::CTR8, PPC::RM, 0 }; | |
| static const MCPhysReg ImplicitList17[] = { PPC::LR8, 0 }; | |
| static const MCPhysReg ImplicitList18[] = { PPC::RM, 0 }; | |
| static const MCPhysReg ImplicitList19[] = { PPC::LR, PPC::RM, 0 }; | |
| static const MCPhysReg ImplicitList20[] = { PPC::CR6, 0 }; | |
| static const MCPhysReg ImplicitList21[] = { PPC::LR8, PPC::X2, 0 }; | |
| static const MCPhysReg ImplicitList22[] = { PPC::LR, PPC::R2, 0 }; | |
| static const MCPhysReg ImplicitList23[] = { PPC::CTR, PPC::LR, PPC::RM, 0 }; | |
| static const MCPhysReg ImplicitList24[] = { PPC::CTR8, PPC::LR8, PPC::RM, 0 }; | |
| static const MCPhysReg ImplicitList25[] = { PPC::LR8, PPC::RM, 0 }; | |
| static const MCPhysReg ImplicitList26[] = { PPC::CR1EQ, 0 }; | |
| static const MCPhysReg ImplicitList27[] = { PPC::X1, 0 }; | |
| static const MCPhysReg ImplicitList28[] = { PPC::CR1, 0 }; | |
| static const MCPhysReg ImplicitList29[] = { PPC::X0, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::LR8, PPC::CTR8, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, 0 }; | |
| static const MCPhysReg ImplicitList30[] = { PPC::R0, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, 0 }; | |
| static const MCPhysReg ImplicitList31[] = { PPC::LR, PPC::CTR, 0 }; | |
| static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo12[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; | |
| static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; | |
| static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; | |
| static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; | |
| static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo32[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; | |
| static const MCOperandInfo OperandInfo33[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; | |
| static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; | |
| static const MCOperandInfo OperandInfo35[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; | |
| static const MCOperandInfo OperandInfo38[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo39[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo40[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo41[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo42[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo43[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo44[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo45[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo46[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo47[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo48[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo49[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo50[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo51[] = { { PPC::SPILLTOVSRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo52[] = { { PPC::SPILLTOVSRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo53[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo54[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo55[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo56[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo57[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo58[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo59[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo60[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo61[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo62[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo63[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo64[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo65[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo66[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo67[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo68[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo69[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo70[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo71[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo72[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo73[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo74[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo75[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo76[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo77[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo78[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; | |
| static const MCOperandInfo OperandInfo79[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo80[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo81[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo82[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo83[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo84[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo85[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo86[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo87[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo88[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo89[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo90[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo91[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo92[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo93[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo94[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo95[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo96[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo97[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo98[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo99[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo100[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo101[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo102[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo103[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo104[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo105[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo106[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo107[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo108[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo109[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo110[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo111[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo112[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo113[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo114[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo115[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo116[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo117[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo118[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo119[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo120[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo121[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo122[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo123[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, }; | |
| static const MCOperandInfo OperandInfo124[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, }; | |
| static const MCOperandInfo OperandInfo125[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo126[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo127[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo128[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo129[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo130[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo131[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo132[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo133[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo134[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo135[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, }; | |
| static const MCOperandInfo OperandInfo136[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo137[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo138[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, }; | |
| static const MCOperandInfo OperandInfo139[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo140[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo141[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo142[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo143[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo144[] = { { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo145[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo146[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo147[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo148[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo149[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo150[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo151[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo152[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo153[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo154[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo155[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo156[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo157[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo158[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRSAVERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo159[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo160[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo161[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo162[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo163[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo164[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo165[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo166[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo167[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo168[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo169[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo170[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo171[] = { { PPC::VRSAVERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo172[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo173[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo174[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo175[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo176[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo177[] = { { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo178[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo179[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo180[] = { { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo181[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo182[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo183[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo184[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo185[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo186[] = { { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo187[] = { { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo188[] = { { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo189[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo190[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo191[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo192[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo193[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo194[] = { { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo195[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo196[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo197[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo198[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo199[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo200[] = { { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo201[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo202[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo203[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo204[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo205[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo206[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo207[] = { { PPC::VRSAVERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo208[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo209[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo210[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo211[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo212[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo213[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo214[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo215[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo216[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo217[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo218[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo219[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo220[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo221[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo222[] = { { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo223[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo224[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo225[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo226[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo227[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo228[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo229[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo230[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo231[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo232[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo233[] = { { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo234[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo235[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo236[] = { { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::SPERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo237[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo238[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo239[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo240[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo241[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo242[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo243[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; | |
| static const MCOperandInfo OperandInfo244[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; | |
| static const MCOperandInfo OperandInfo245[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo246[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo247[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; | |
| static const MCOperandInfo OperandInfo248[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo249[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; | |
| static const MCOperandInfo OperandInfo250[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo251[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo252[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo253[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo254[] = { { PPC::CTRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo255[] = { { PPC::CTRRC8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo256[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo257[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo258[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| static const MCOperandInfo OperandInfo259[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo260[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo261[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo262[] = { { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo263[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo264[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo265[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; | |
| static const MCOperandInfo OperandInfo266[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo267[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo268[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo269[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo270[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo271[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo272[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo273[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo274[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo275[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo276[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo277[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo278[] = { { PPC::VFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo279[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo280[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo281[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo282[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo283[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo284[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo285[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo286[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo287[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo288[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo289[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo290[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo291[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo292[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo293[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo294[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo295[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo296[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo297[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo298[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo299[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo300[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo301[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo302[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo303[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; | |
| static const MCOperandInfo OperandInfo304[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo305[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo306[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo307[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; | |
| static const MCOperandInfo OperandInfo308[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; | |
| extern const MCInstrDesc PPCInsts[] = { | |
| { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI | |
| { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM | |
| { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR | |
| { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION | |
| { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL | |
| { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL | |
| { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL | |
| { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL | |
| { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG | |
| { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG | |
| { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF | |
| { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG | |
| { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS | |
| { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE | |
| { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL | |
| { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE | |
| { 16, 2, 1, 0, 117, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY | |
| { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE | |
| { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START | |
| { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END | |
| { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP | |
| { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL | |
| { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT | |
| { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD | |
| { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT | |
| { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE | |
| { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP | |
| { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP | |
| { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER | |
| { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET | |
| { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT | |
| { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL | |
| { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL | |
| { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL | |
| { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL | |
| { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #35 = G_ADD | |
| { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #36 = G_SUB | |
| { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #37 = G_MUL | |
| { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #38 = G_SDIV | |
| { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #39 = G_UDIV | |
| { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #40 = G_SREM | |
| { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #41 = G_UREM | |
| { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #42 = G_AND | |
| { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #43 = G_OR | |
| { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #44 = G_XOR | |
| { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF | |
| { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #46 = G_PHI | |
| { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX | |
| { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE | |
| { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #49 = G_EXTRACT | |
| { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES | |
| { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #51 = G_INSERT | |
| { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES | |
| { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR | |
| { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC | |
| { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS | |
| { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #56 = G_PTRTOINT | |
| { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #57 = G_INTTOPTR | |
| { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #58 = G_BITCAST | |
| { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC | |
| { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND | |
| { 61, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #61 = G_READCYCLECOUNTER | |
| { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #62 = G_LOAD | |
| { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #63 = G_SEXTLOAD | |
| { 64, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #64 = G_ZEXTLOAD | |
| { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #65 = G_INDEXED_LOAD | |
| { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #66 = G_INDEXED_SEXTLOAD | |
| { 67, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #67 = G_INDEXED_ZEXTLOAD | |
| { 68, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #68 = G_STORE | |
| { 69, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_INDEXED_STORE | |
| { 70, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG_WITH_SUCCESS | |
| { 71, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMIC_CMPXCHG | |
| { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_XCHG | |
| { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_ADD | |
| { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_SUB | |
| { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_AND | |
| { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_NAND | |
| { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_OR | |
| { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_XOR | |
| { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MAX | |
| { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_MIN | |
| { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMAX | |
| { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_UMIN | |
| { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FADD | |
| { 84, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #84 = G_ATOMICRMW_FSUB | |
| { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #85 = G_FENCE | |
| { 86, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #86 = G_BRCOND | |
| { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #87 = G_BRINDIRECT | |
| { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC | |
| { 89, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #89 = G_INTRINSIC_W_SIDE_EFFECTS | |
| { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #90 = G_ANYEXT | |
| { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #91 = G_TRUNC | |
| { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #92 = G_CONSTANT | |
| { 93, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #93 = G_FCONSTANT | |
| { 94, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #94 = G_VASTART | |
| { 95, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_VAARG | |
| { 96, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #96 = G_SEXT | |
| { 97, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #97 = G_SEXT_INREG | |
| { 98, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #98 = G_ZEXT | |
| { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #99 = G_SHL | |
| { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #100 = G_LSHR | |
| { 101, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ASHR | |
| { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #102 = G_ICMP | |
| { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #103 = G_FCMP | |
| { 104, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #104 = G_SELECT | |
| { 105, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #105 = G_UADDO | |
| { 106, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #106 = G_UADDE | |
| { 107, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #107 = G_USUBO | |
| { 108, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #108 = G_USUBE | |
| { 109, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #109 = G_SADDO | |
| { 110, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #110 = G_SADDE | |
| { 111, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #111 = G_SSUBO | |
| { 112, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #112 = G_SSUBE | |
| { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #113 = G_UMULO | |
| { 114, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #114 = G_SMULO | |
| { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #115 = G_UMULH | |
| { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #116 = G_SMULH | |
| { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #117 = G_FADD | |
| { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #118 = G_FSUB | |
| { 119, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #119 = G_FMUL | |
| { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #120 = G_FMA | |
| { 121, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #121 = G_FMAD | |
| { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #122 = G_FDIV | |
| { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #123 = G_FREM | |
| { 124, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #124 = G_FPOW | |
| { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #125 = G_FEXP | |
| { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #126 = G_FEXP2 | |
| { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #127 = G_FLOG | |
| { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #128 = G_FLOG2 | |
| { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #129 = G_FLOG10 | |
| { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #130 = G_FNEG | |
| { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #131 = G_FPEXT | |
| { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #132 = G_FPTRUNC | |
| { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #133 = G_FPTOSI | |
| { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #134 = G_FPTOUI | |
| { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #135 = G_SITOFP | |
| { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #136 = G_UITOFP | |
| { 137, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #137 = G_FABS | |
| { 138, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #138 = G_FCOPYSIGN | |
| { 139, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #139 = G_FCANONICALIZE | |
| { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #140 = G_FMINNUM | |
| { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #141 = G_FMAXNUM | |
| { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #142 = G_FMINNUM_IEEE | |
| { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #143 = G_FMAXNUM_IEEE | |
| { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #144 = G_FMINIMUM | |
| { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #145 = G_FMAXIMUM | |
| { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #146 = G_PTR_ADD | |
| { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #147 = G_PTR_MASK | |
| { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #148 = G_SMIN | |
| { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #149 = G_SMAX | |
| { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #150 = G_UMIN | |
| { 151, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #151 = G_UMAX | |
| { 152, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #152 = G_BR | |
| { 153, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_BRJT | |
| { 154, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_INSERT_VECTOR_ELT | |
| { 155, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_EXTRACT_VECTOR_ELT | |
| { 156, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #156 = G_SHUFFLE_VECTOR | |
| { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #157 = G_CTTZ | |
| { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #158 = G_CTTZ_ZERO_UNDEF | |
| { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #159 = G_CTLZ | |
| { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #160 = G_CTLZ_ZERO_UNDEF | |
| { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #161 = G_CTPOP | |
| { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #162 = G_BSWAP | |
| { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #163 = G_BITREVERSE | |
| { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #164 = G_FCEIL | |
| { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #165 = G_FCOS | |
| { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #166 = G_FSIN | |
| { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #167 = G_FSQRT | |
| { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #168 = G_FFLOOR | |
| { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #169 = G_FRINT | |
| { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #170 = G_FNEARBYINT | |
| { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #171 = G_ADDRSPACE_CAST | |
| { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #172 = G_BLOCK_ADDR | |
| { 173, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #173 = G_JUMP_TABLE | |
| { 174, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #174 = G_DYN_STACKALLOC | |
| { 175, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #175 = G_READ_REGISTER | |
| { 176, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #176 = G_WRITE_REGISTER | |
| { 177, 1, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #177 = CFENCE8 | |
| { 178, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #178 = CLRLSLDI | |
| { 179, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #179 = CLRLSLDI_rec | |
| { 180, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #180 = CLRLSLWI | |
| { 181, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #181 = CLRLSLWI_rec | |
| { 182, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #182 = CLRRDI | |
| { 183, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #183 = CLRRDI_rec | |
| { 184, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #184 = CLRRWI | |
| { 185, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #185 = CLRRWI_rec | |
| { 186, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #186 = CP_COPY_FIRST | |
| { 187, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #187 = CP_COPYx | |
| { 188, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #188 = CP_PASTE_LAST | |
| { 189, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #189 = CP_PASTEx | |
| { 190, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #190 = DCBFL | |
| { 191, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #191 = DCBFLP | |
| { 192, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #192 = DCBFx | |
| { 193, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #193 = DCBTCT | |
| { 194, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #194 = DCBTDS | |
| { 195, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #195 = DCBTSTCT | |
| { 196, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #196 = DCBTSTDS | |
| { 197, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #197 = DCBTSTT | |
| { 198, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #198 = DCBTSTx | |
| { 199, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #199 = DCBTT | |
| { 200, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #200 = DCBTx | |
| { 201, 3, 1, 4, 211, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #201 = DFLOADf32 | |
| { 202, 3, 1, 4, 174, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #202 = DFLOADf64 | |
| { 203, 3, 0, 4, 217, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #203 = DFSTOREf32 | |
| { 204, 3, 0, 4, 217, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #204 = DFSTOREf64 | |
| { 205, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #205 = EXTLDI | |
| { 206, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #206 = EXTLDI_rec | |
| { 207, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #207 = EXTLWI | |
| { 208, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #208 = EXTLWI_rec | |
| { 209, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #209 = EXTRDI | |
| { 210, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #210 = EXTRDI_rec | |
| { 211, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #211 = EXTRWI | |
| { 212, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #212 = EXTRWI_rec | |
| { 213, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #213 = INSLWI | |
| { 214, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #214 = INSLWI_rec | |
| { 215, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #215 = INSRDI | |
| { 216, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #216 = INSRDI_rec | |
| { 217, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #217 = INSRWI | |
| { 218, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #218 = INSRWI_rec | |
| { 219, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #219 = LAx | |
| { 220, 3, 1, 4, 208, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #220 = LIWAX | |
| { 221, 3, 1, 4, 174, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #221 = LIWZX | |
| { 222, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #222 = RLWIMIbm | |
| { 223, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #223 = RLWIMIbm_rec | |
| { 224, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #224 = RLWINMbm | |
| { 225, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #225 = RLWINMbm_rec | |
| { 226, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #226 = RLWNMbm | |
| { 227, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #227 = RLWNMbm_rec | |
| { 228, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #228 = ROTRDI | |
| { 229, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #229 = ROTRDI_rec | |
| { 230, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #230 = ROTRWI | |
| { 231, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #231 = ROTRWI_rec | |
| { 232, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #232 = SLDI | |
| { 233, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #233 = SLDI_rec | |
| { 234, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #234 = SLWI | |
| { 235, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #235 = SLWI_rec | |
| { 236, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #236 = SPILLTOVSR_LD | |
| { 237, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #237 = SPILLTOVSR_LDX | |
| { 238, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #238 = SPILLTOVSR_ST | |
| { 239, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #239 = SPILLTOVSR_STX | |
| { 240, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #240 = SRDI | |
| { 241, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #241 = SRDI_rec | |
| { 242, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #242 = SRWI | |
| { 243, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #243 = SRWI_rec | |
| { 244, 3, 0, 4, 217, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #244 = STIWX | |
| { 245, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #245 = SUBI | |
| { 246, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #246 = SUBIC | |
| { 247, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #247 = SUBIC_rec | |
| { 248, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #248 = SUBIS | |
| { 249, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #249 = SUBPCIS | |
| { 250, 3, 1, 4, 211, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #250 = XFLOADf32 | |
| { 251, 3, 1, 4, 174, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #251 = XFLOADf64 | |
| { 252, 3, 0, 4, 217, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #252 = XFSTOREf32 | |
| { 253, 3, 0, 4, 217, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #253 = XFSTOREf64 | |
| { 254, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #254 = ADD4 | |
| { 255, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList2, OperandInfo55, -1 ,nullptr }, // Inst #255 = ADD4O | |
| { 256, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo55, -1 ,nullptr }, // Inst #256 = ADD4O_rec | |
| { 257, 3, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #257 = ADD4TLS | |
| { 258, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList4, OperandInfo55, -1 ,nullptr }, // Inst #258 = ADD4_rec | |
| { 259, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #259 = ADD8 | |
| { 260, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList2, OperandInfo56, -1 ,nullptr }, // Inst #260 = ADD8O | |
| { 261, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo56, -1 ,nullptr }, // Inst #261 = ADD8O_rec | |
| { 262, 3, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #262 = ADD8TLS | |
| { 263, 3, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #263 = ADD8TLS_ | |
| { 264, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #264 = ADD8_rec | |
| { 265, 3, 1, 4, 115, 0|(1ULL<<MCID::Commutable), 0xcULL, nullptr, ImplicitList5, OperandInfo55, -1 ,nullptr }, // Inst #265 = ADDC | |
| { 266, 3, 1, 4, 115, 0|(1ULL<<MCID::Commutable), 0xcULL, nullptr, ImplicitList5, OperandInfo56, -1 ,nullptr }, // Inst #266 = ADDC8 | |
| { 267, 3, 1, 4, 115, 0|(1ULL<<MCID::Commutable), 0xcULL, nullptr, ImplicitList6, OperandInfo56, -1 ,nullptr }, // Inst #267 = ADDC8O | |
| { 268, 3, 1, 4, 245, 0|(1ULL<<MCID::Commutable), 0xcULL, nullptr, ImplicitList7, OperandInfo56, -1 ,nullptr }, // Inst #268 = ADDC8O_rec | |
| { 269, 3, 1, 4, 245, 0|(1ULL<<MCID::Commutable), 0xcULL, nullptr, ImplicitList8, OperandInfo56, -1 ,nullptr }, // Inst #269 = ADDC8_rec | |
| { 270, 3, 1, 4, 115, 0|(1ULL<<MCID::Commutable), 0xcULL, nullptr, ImplicitList6, OperandInfo55, -1 ,nullptr }, // Inst #270 = ADDCO | |
| { 271, 3, 1, 4, 245, 0|(1ULL<<MCID::Commutable), 0xcULL, nullptr, ImplicitList7, OperandInfo55, -1 ,nullptr }, // Inst #271 = ADDCO_rec | |
| { 272, 3, 1, 4, 245, 0|(1ULL<<MCID::Commutable), 0xcULL, nullptr, ImplicitList8, OperandInfo55, -1 ,nullptr }, // Inst #272 = ADDC_rec | |
| { 273, 3, 1, 4, 115, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList5, ImplicitList5, OperandInfo55, -1 ,nullptr }, // Inst #273 = ADDE | |
| { 274, 3, 1, 4, 115, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList5, ImplicitList5, OperandInfo56, -1 ,nullptr }, // Inst #274 = ADDE8 | |
| { 275, 3, 1, 4, 115, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList5, ImplicitList6, OperandInfo56, -1 ,nullptr }, // Inst #275 = ADDE8O | |
| { 276, 3, 1, 4, 115, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList5, ImplicitList7, OperandInfo56, -1 ,nullptr }, // Inst #276 = ADDE8O_rec | |
| { 277, 3, 1, 4, 115, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList5, ImplicitList8, OperandInfo56, -1 ,nullptr }, // Inst #277 = ADDE8_rec | |
| { 278, 3, 1, 4, 115, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList5, ImplicitList6, OperandInfo55, -1 ,nullptr }, // Inst #278 = ADDEO | |
| { 279, 3, 1, 4, 115, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList5, ImplicitList7, OperandInfo55, -1 ,nullptr }, // Inst #279 = ADDEO_rec | |
| { 280, 3, 1, 4, 115, 0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList5, ImplicitList8, OperandInfo55, -1 ,nullptr }, // Inst #280 = ADDE_rec | |
| { 281, 3, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #281 = ADDI | |
| { 282, 3, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #282 = ADDI8 | |
| { 283, 3, 1, 4, 115, 0, 0xcULL, nullptr, ImplicitList5, OperandInfo42, -1 ,nullptr }, // Inst #283 = ADDIC | |
| { 284, 3, 1, 4, 115, 0, 0x8ULL, nullptr, ImplicitList5, OperandInfo41, -1 ,nullptr }, // Inst #284 = ADDIC8 | |
| { 285, 3, 1, 4, 115, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL, nullptr, ImplicitList8, OperandInfo42, -1 ,nullptr }, // Inst #285 = ADDIC_rec | |
| { 286, 3, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #286 = ADDIS | |
| { 287, 3, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #287 = ADDIS8 | |
| { 288, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #288 = ADDISdtprelHA | |
| { 289, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #289 = ADDISdtprelHA32 | |
| { 290, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #290 = ADDISgotTprelHA | |
| { 291, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #291 = ADDIStlsgdHA | |
| { 292, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #292 = ADDIStlsldHA | |
| { 293, 3, 1, 4, 117, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #293 = ADDIStocHA | |
| { 294, 3, 1, 4, 117, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #294 = ADDIStocHA8 | |
| { 295, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #295 = ADDIdtprelL | |
| { 296, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #296 = ADDIdtprelL32 | |
| { 297, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #297 = ADDItlsgdL | |
| { 298, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #298 = ADDItlsgdL32 | |
| { 299, 4, 1, 4, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList9, OperandInfo59, -1 ,nullptr }, // Inst #299 = ADDItlsgdLADDR | |
| { 300, 4, 1, 4, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList10, OperandInfo60, -1 ,nullptr }, // Inst #300 = ADDItlsgdLADDR32 | |
| { 301, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #301 = ADDItlsldL | |
| { 302, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #302 = ADDItlsldL32 | |
| { 303, 4, 1, 4, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList9, OperandInfo59, -1 ,nullptr }, // Inst #303 = ADDItlsldLADDR | |
| { 304, 4, 1, 4, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList10, OperandInfo60, -1 ,nullptr }, // Inst #304 = ADDItlsldLADDR32 | |
| { 305, 3, 1, 4, 117, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #305 = ADDItocL | |
| { 306, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList5, OperandInfo43, -1 ,nullptr }, // Inst #306 = ADDME | |
| { 307, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList5, OperandInfo61, -1 ,nullptr }, // Inst #307 = ADDME8 | |
| { 308, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList6, OperandInfo61, -1 ,nullptr }, // Inst #308 = ADDME8O | |
| { 309, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList7, OperandInfo61, -1 ,nullptr }, // Inst #309 = ADDME8O_rec | |
| { 310, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList8, OperandInfo61, -1 ,nullptr }, // Inst #310 = ADDME8_rec | |
| { 311, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList6, OperandInfo43, -1 ,nullptr }, // Inst #311 = ADDMEO | |
| { 312, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList7, OperandInfo43, -1 ,nullptr }, // Inst #312 = ADDMEO_rec | |
| { 313, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList8, OperandInfo43, -1 ,nullptr }, // Inst #313 = ADDME_rec | |
| { 314, 2, 1, 4, 288, 0, 0x8ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #314 = ADDPCIS | |
| { 315, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList5, OperandInfo43, -1 ,nullptr }, // Inst #315 = ADDZE | |
| { 316, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList5, OperandInfo61, -1 ,nullptr }, // Inst #316 = ADDZE8 | |
| { 317, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList6, OperandInfo61, -1 ,nullptr }, // Inst #317 = ADDZE8O | |
| { 318, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList7, OperandInfo61, -1 ,nullptr }, // Inst #318 = ADDZE8O_rec | |
| { 319, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList8, OperandInfo61, -1 ,nullptr }, // Inst #319 = ADDZE8_rec | |
| { 320, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList6, OperandInfo43, -1 ,nullptr }, // Inst #320 = ADDZEO | |
| { 321, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList7, OperandInfo43, -1 ,nullptr }, // Inst #321 = ADDZEO_rec | |
| { 322, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList8, OperandInfo43, -1 ,nullptr }, // Inst #322 = ADDZE_rec | |
| { 323, 2, 0, 4, 0, 0, 0x0ULL, ImplicitList11, ImplicitList11, OperandInfo7, -1 ,nullptr }, // Inst #323 = ADJCALLSTACKDOWN | |
| { 324, 2, 0, 4, 0, 0, 0x0ULL, ImplicitList11, ImplicitList11, OperandInfo7, -1 ,nullptr }, // Inst #324 = ADJCALLSTACKUP | |
| { 325, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #325 = AND | |
| { 326, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #326 = AND8 | |
| { 327, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #327 = AND8_rec | |
| { 328, 3, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #328 = ANDC | |
| { 329, 3, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #329 = ANDC8 | |
| { 330, 3, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #330 = ANDC8_rec | |
| { 331, 3, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo55, -1 ,nullptr }, // Inst #331 = ANDC_rec | |
| { 332, 3, 1, 4, 115, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo41, -1 ,nullptr }, // Inst #332 = ANDI8_rec | |
| { 333, 3, 1, 4, 115, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo41, -1 ,nullptr }, // Inst #333 = ANDIS8_rec | |
| { 334, 3, 1, 4, 115, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo42, -1 ,nullptr }, // Inst #334 = ANDIS_rec | |
| { 335, 3, 1, 4, 115, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo42, -1 ,nullptr }, // Inst #335 = ANDI_rec | |
| { 336, 2, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #336 = ANDI_rec_1_EQ_BIT | |
| { 337, 2, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #337 = ANDI_rec_1_EQ_BIT8 | |
| { 338, 2, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #338 = ANDI_rec_1_GT_BIT | |
| { 339, 2, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #339 = ANDI_rec_1_GT_BIT8 | |
| { 340, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList4, OperandInfo55, -1 ,nullptr }, // Inst #340 = AND_rec | |
| { 341, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo65, -1 ,nullptr }, // Inst #341 = ATOMIC_CMP_SWAP_I16 | |
| { 342, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo65, -1 ,nullptr }, // Inst #342 = ATOMIC_CMP_SWAP_I32 | |
| { 343, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo66, -1 ,nullptr }, // Inst #343 = ATOMIC_CMP_SWAP_I64 | |
| { 344, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo65, -1 ,nullptr }, // Inst #344 = ATOMIC_CMP_SWAP_I8 | |
| { 345, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #345 = ATOMIC_LOAD_ADD_I16 | |
| { 346, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #346 = ATOMIC_LOAD_ADD_I32 | |
| { 347, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr }, // Inst #347 = ATOMIC_LOAD_ADD_I64 | |
| { 348, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #348 = ATOMIC_LOAD_ADD_I8 | |
| { 349, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #349 = ATOMIC_LOAD_AND_I16 | |
| { 350, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #350 = ATOMIC_LOAD_AND_I32 | |
| { 351, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr }, // Inst #351 = ATOMIC_LOAD_AND_I64 | |
| { 352, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #352 = ATOMIC_LOAD_AND_I8 | |
| { 353, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #353 = ATOMIC_LOAD_MAX_I16 | |
| { 354, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #354 = ATOMIC_LOAD_MAX_I32 | |
| { 355, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr }, // Inst #355 = ATOMIC_LOAD_MAX_I64 | |
| { 356, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #356 = ATOMIC_LOAD_MAX_I8 | |
| { 357, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #357 = ATOMIC_LOAD_MIN_I16 | |
| { 358, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #358 = ATOMIC_LOAD_MIN_I32 | |
| { 359, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr }, // Inst #359 = ATOMIC_LOAD_MIN_I64 | |
| { 360, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #360 = ATOMIC_LOAD_MIN_I8 | |
| { 361, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #361 = ATOMIC_LOAD_NAND_I16 | |
| { 362, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #362 = ATOMIC_LOAD_NAND_I32 | |
| { 363, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr }, // Inst #363 = ATOMIC_LOAD_NAND_I64 | |
| { 364, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #364 = ATOMIC_LOAD_NAND_I8 | |
| { 365, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #365 = ATOMIC_LOAD_OR_I16 | |
| { 366, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #366 = ATOMIC_LOAD_OR_I32 | |
| { 367, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr }, // Inst #367 = ATOMIC_LOAD_OR_I64 | |
| { 368, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #368 = ATOMIC_LOAD_OR_I8 | |
| { 369, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #369 = ATOMIC_LOAD_SUB_I16 | |
| { 370, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #370 = ATOMIC_LOAD_SUB_I32 | |
| { 371, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr }, // Inst #371 = ATOMIC_LOAD_SUB_I64 | |
| { 372, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #372 = ATOMIC_LOAD_SUB_I8 | |
| { 373, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #373 = ATOMIC_LOAD_UMAX_I16 | |
| { 374, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #374 = ATOMIC_LOAD_UMAX_I32 | |
| { 375, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr }, // Inst #375 = ATOMIC_LOAD_UMAX_I64 | |
| { 376, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #376 = ATOMIC_LOAD_UMAX_I8 | |
| { 377, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #377 = ATOMIC_LOAD_UMIN_I16 | |
| { 378, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #378 = ATOMIC_LOAD_UMIN_I32 | |
| { 379, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr }, // Inst #379 = ATOMIC_LOAD_UMIN_I64 | |
| { 380, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #380 = ATOMIC_LOAD_UMIN_I8 | |
| { 381, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #381 = ATOMIC_LOAD_XOR_I16 | |
| { 382, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #382 = ATOMIC_LOAD_XOR_I32 | |
| { 383, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr }, // Inst #383 = ATOMIC_LOAD_XOR_I64 | |
| { 384, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #384 = ATOMIC_LOAD_XOR_I8 | |
| { 385, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #385 = ATOMIC_SWAP_I16 | |
| { 386, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #386 = ATOMIC_SWAP_I32 | |
| { 387, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo68, -1 ,nullptr }, // Inst #387 = ATOMIC_SWAP_I64 | |
| { 388, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList4, OperandInfo67, -1 ,nullptr }, // Inst #388 = ATOMIC_SWAP_I8 | |
| { 389, 0, 0, 4, 296, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #389 = ATTN | |
| { 390, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x38ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #390 = B | |
| { 391, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #391 = BA | |
| { 392, 2, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #392 = BC | |
| { 393, 3, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #393 = BCC | |
| { 394, 3, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #394 = BCCA | |
| { 395, 2, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList12, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #395 = BCCCTR | |
| { 396, 2, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #396 = BCCCTR8 | |
| { 397, 2, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList15, OperandInfo71, -1 ,nullptr }, // Inst #397 = BCCCTRL | |
| { 398, 2, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList16, ImplicitList17, OperandInfo71, -1 ,nullptr }, // Inst #398 = BCCCTRL8 | |
| { 399, 3, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList15, OperandInfo70, -1 ,nullptr }, // Inst #399 = BCCL | |
| { 400, 3, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList15, OperandInfo70, -1 ,nullptr }, // Inst #400 = BCCLA | |
| { 401, 2, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList19, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #401 = BCCLR | |
| { 402, 2, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList19, ImplicitList15, OperandInfo71, -1 ,nullptr }, // Inst #402 = BCCLRL | |
| { 403, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList12, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #403 = BCCTR | |
| { 404, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #404 = BCCTR8 | |
| { 405, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #405 = BCCTR8n | |
| { 406, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList15, OperandInfo72, -1 ,nullptr }, // Inst #406 = BCCTRL | |
| { 407, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList16, ImplicitList17, OperandInfo72, -1 ,nullptr }, // Inst #407 = BCCTRL8 | |
| { 408, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList16, ImplicitList17, OperandInfo72, -1 ,nullptr }, // Inst #408 = BCCTRL8n | |
| { 409, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList15, OperandInfo72, -1 ,nullptr }, // Inst #409 = BCCTRLn | |
| { 410, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList12, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #410 = BCCTRn | |
| { 411, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList20, OperandInfo73, -1 ,nullptr }, // Inst #411 = BCDCFN_rec | |
| { 412, 3, 1, 4, 168, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList20, OperandInfo73, -1 ,nullptr }, // Inst #412 = BCDCFSQ_rec | |
| { 413, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList20, OperandInfo73, -1 ,nullptr }, // Inst #413 = BCDCFZ_rec | |
| { 414, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #414 = BCDCPSGN_rec | |
| { 415, 2, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #415 = BCDCTN_rec | |
| { 416, 2, 1, 4, 166, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList20, OperandInfo75, -1 ,nullptr }, // Inst #416 = BCDCTSQ_rec | |
| { 417, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList20, OperandInfo73, -1 ,nullptr }, // Inst #417 = BCDCTZ_rec | |
| { 418, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList20, OperandInfo73, -1 ,nullptr }, // Inst #418 = BCDSETSGN_rec | |
| { 419, 4, 1, 4, 165, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList20, OperandInfo76, -1 ,nullptr }, // Inst #419 = BCDSR_rec | |
| { 420, 4, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList20, OperandInfo76, -1 ,nullptr }, // Inst #420 = BCDS_rec | |
| { 421, 4, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList20, OperandInfo76, -1 ,nullptr }, // Inst #421 = BCDTRUNC_rec | |
| { 422, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #422 = BCDUS_rec | |
| { 423, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #423 = BCDUTRUNC_rec | |
| { 424, 2, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList15, OperandInfo69, -1 ,nullptr }, // Inst #424 = BCL | |
| { 425, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList19, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #425 = BCLR | |
| { 426, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList19, ImplicitList15, OperandInfo72, -1 ,nullptr }, // Inst #426 = BCLRL | |
| { 427, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList19, ImplicitList15, OperandInfo72, -1 ,nullptr }, // Inst #427 = BCLRLn | |
| { 428, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #428 = BCLRn | |
| { 429, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList15, OperandInfo2, -1 ,nullptr }, // Inst #429 = BCLalways | |
| { 430, 2, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList15, OperandInfo69, -1 ,nullptr }, // Inst #430 = BCLn | |
| { 431, 0, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList12, nullptr, nullptr, -1 ,nullptr }, // Inst #431 = BCTR | |
| { 432, 0, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, nullptr, nullptr, -1 ,nullptr }, // Inst #432 = BCTR8 | |
| { 433, 0, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x38ULL, ImplicitList14, ImplicitList15, nullptr, -1 ,nullptr }, // Inst #433 = BCTRL | |
| { 434, 0, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x38ULL, ImplicitList16, ImplicitList17, nullptr, -1 ,nullptr }, // Inst #434 = BCTRL8 | |
| { 435, 2, 0, 8, 287, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList16, ImplicitList21, OperandInfo77, -1 ,nullptr }, // Inst #435 = BCTRL8_LDinto_toc | |
| { 436, 2, 0, 8, 287, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList14, ImplicitList22, OperandInfo77, -1 ,nullptr }, // Inst #436 = BCTRL_LWZinto_toc | |
| { 437, 2, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #437 = BCn | |
| { 438, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList12, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #438 = BDNZ | |
| { 439, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, ImplicitList13, OperandInfo2, -1 ,nullptr }, // Inst #439 = BDNZ8 | |
| { 440, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList12, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #440 = BDNZA | |
| { 441, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList12, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #441 = BDNZAm | |
| { 442, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList12, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #442 = BDNZAp | |
| { 443, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #443 = BDNZL | |
| { 444, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #444 = BDNZLA | |
| { 445, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #445 = BDNZLAm | |
| { 446, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #446 = BDNZLAp | |
| { 447, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList23, ImplicitList12, nullptr, -1 ,nullptr }, // Inst #447 = BDNZLR | |
| { 448, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList24, ImplicitList13, nullptr, -1 ,nullptr }, // Inst #448 = BDNZLR8 | |
| { 449, 0, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList23, ImplicitList12, nullptr, -1 ,nullptr }, // Inst #449 = BDNZLRL | |
| { 450, 0, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList23, ImplicitList12, nullptr, -1 ,nullptr }, // Inst #450 = BDNZLRLm | |
| { 451, 0, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList23, ImplicitList12, nullptr, -1 ,nullptr }, // Inst #451 = BDNZLRLp | |
| { 452, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList23, ImplicitList12, nullptr, -1 ,nullptr }, // Inst #452 = BDNZLRm | |
| { 453, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList23, ImplicitList12, nullptr, -1 ,nullptr }, // Inst #453 = BDNZLRp | |
| { 454, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #454 = BDNZLm | |
| { 455, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #455 = BDNZLp | |
| { 456, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList12, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #456 = BDNZm | |
| { 457, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList12, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #457 = BDNZp | |
| { 458, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList12, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #458 = BDZ | |
| { 459, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, ImplicitList13, OperandInfo2, -1 ,nullptr }, // Inst #459 = BDZ8 | |
| { 460, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList12, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #460 = BDZA | |
| { 461, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList12, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #461 = BDZAm | |
| { 462, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList12, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #462 = BDZAp | |
| { 463, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #463 = BDZL | |
| { 464, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #464 = BDZLA | |
| { 465, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #465 = BDZLAm | |
| { 466, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #466 = BDZLAp | |
| { 467, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList23, ImplicitList12, nullptr, -1 ,nullptr }, // Inst #467 = BDZLR | |
| { 468, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList24, ImplicitList13, nullptr, -1 ,nullptr }, // Inst #468 = BDZLR8 | |
| { 469, 0, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList23, ImplicitList12, nullptr, -1 ,nullptr }, // Inst #469 = BDZLRL | |
| { 470, 0, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList23, ImplicitList12, nullptr, -1 ,nullptr }, // Inst #470 = BDZLRLm | |
| { 471, 0, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList23, ImplicitList12, nullptr, -1 ,nullptr }, // Inst #471 = BDZLRLp | |
| { 472, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList23, ImplicitList12, nullptr, -1 ,nullptr }, // Inst #472 = BDZLRm | |
| { 473, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList23, ImplicitList12, nullptr, -1 ,nullptr }, // Inst #473 = BDZLRp | |
| { 474, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #474 = BDZLm | |
| { 475, 1, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #475 = BDZLp | |
| { 476, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList12, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #476 = BDZm | |
| { 477, 1, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList12, ImplicitList12, OperandInfo2, -1 ,nullptr }, // Inst #477 = BDZp | |
| { 478, 1, 0, 4, 287, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList18, ImplicitList15, OperandInfo78, -1 ,nullptr }, // Inst #478 = BL | |
| { 479, 1, 0, 4, 287, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList18, ImplicitList17, OperandInfo78, -1 ,nullptr }, // Inst #479 = BL8 | |
| { 480, 1, 0, 8, 287, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList18, ImplicitList17, OperandInfo78, -1 ,nullptr }, // Inst #480 = BL8_NOP | |
| { 481, 2, 0, 8, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList17, OperandInfo7, -1 ,nullptr }, // Inst #481 = BL8_NOP_TLS | |
| { 482, 2, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList17, OperandInfo7, -1 ,nullptr }, // Inst #482 = BL8_TLS | |
| { 483, 2, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList17, OperandInfo7, -1 ,nullptr }, // Inst #483 = BL8_TLS_ | |
| { 484, 1, 0, 4, 287, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList18, ImplicitList15, OperandInfo2, -1 ,nullptr }, // Inst #484 = BLA | |
| { 485, 1, 0, 4, 287, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList18, ImplicitList17, OperandInfo2, -1 ,nullptr }, // Inst #485 = BLA8 | |
| { 486, 1, 0, 8, 287, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList18, ImplicitList17, OperandInfo2, -1 ,nullptr }, // Inst #486 = BLA8_NOP | |
| { 487, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList19, nullptr, nullptr, -1 ,nullptr }, // Inst #487 = BLR | |
| { 488, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList25, nullptr, nullptr, -1 ,nullptr }, // Inst #488 = BLR8 | |
| { 489, 0, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList19, ImplicitList15, nullptr, -1 ,nullptr }, // Inst #489 = BLRL | |
| { 490, 1, 0, 8, 287, 0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList18, ImplicitList15, OperandInfo78, -1 ,nullptr }, // Inst #490 = BL_NOP | |
| { 491, 2, 0, 4, 287, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, ImplicitList15, OperandInfo7, -1 ,nullptr }, // Inst #491 = BL_TLS | |
| { 492, 3, 1, 4, 110, 0, 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #492 = BPERMD | |
| { 493, 3, 1, 4, 291, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #493 = BRINC | |
| { 494, 0, 0, 4, 296, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #494 = CLRBHRB | |
| { 495, 3, 1, 4, 110, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #495 = CMPB | |
| { 496, 3, 1, 4, 110, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #496 = CMPB8 | |
| { 497, 3, 1, 4, 114, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #497 = CMPD | |
| { 498, 3, 1, 4, 114, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #498 = CMPDI | |
| { 499, 3, 1, 4, 103, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #499 = CMPEQB | |
| { 500, 3, 1, 4, 114, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #500 = CMPLD | |
| { 501, 3, 1, 4, 114, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #501 = CMPLDI | |
| { 502, 3, 1, 4, 114, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #502 = CMPLW | |
| { 503, 3, 1, 4, 114, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #503 = CMPLWI | |
| { 504, 4, 1, 4, 103, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #504 = CMPRB | |
| { 505, 4, 1, 4, 103, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #505 = CMPRB8 | |
| { 506, 3, 1, 4, 114, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #506 = CMPW | |
| { 507, 3, 1, 4, 114, 0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #507 = CMPWI | |
| { 508, 2, 1, 4, 110, 0, 0x8ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #508 = CNTLZD | |
| { 509, 2, 1, 4, 110, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo61, -1 ,nullptr }, // Inst #509 = CNTLZD_rec | |
| { 510, 2, 1, 4, 110, 0, 0x8ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #510 = CNTLZW | |
| { 511, 2, 1, 4, 110, 0, 0x8ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #511 = CNTLZW8 | |
| { 512, 2, 1, 4, 110, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo61, -1 ,nullptr }, // Inst #512 = CNTLZW8_rec | |
| { 513, 2, 1, 4, 110, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo43, -1 ,nullptr }, // Inst #513 = CNTLZW_rec | |
| { 514, 2, 1, 4, 110, 0, 0x8ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #514 = CNTTZD | |
| { 515, 2, 1, 4, 110, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo61, -1 ,nullptr }, // Inst #515 = CNTTZD_rec | |
| { 516, 2, 1, 4, 110, 0, 0x8ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #516 = CNTTZW | |
| { 517, 2, 1, 4, 110, 0, 0x8ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #517 = CNTTZW8 | |
| { 518, 2, 1, 4, 110, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo61, -1 ,nullptr }, // Inst #518 = CNTTZW8_rec | |
| { 519, 2, 1, 4, 110, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo43, -1 ,nullptr }, // Inst #519 = CNTTZW_rec | |
| { 520, 0, 0, 4, 183, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #520 = CP_ABORT | |
| { 521, 3, 0, 4, 176, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #521 = CP_COPY | |
| { 522, 3, 0, 4, 176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #522 = CP_COPY8 | |
| { 523, 3, 0, 4, 177, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #523 = CP_PASTE | |
| { 524, 3, 0, 4, 177, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #524 = CP_PASTE8 | |
| { 525, 3, 0, 4, 203, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #525 = CP_PASTE8_rec | |
| { 526, 3, 0, 4, 203, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo42, -1 ,nullptr }, // Inst #526 = CP_PASTE_rec | |
| { 527, 0, 0, 4, 129, 0, 0x0ULL, nullptr, ImplicitList26, nullptr, -1 ,nullptr }, // Inst #527 = CR6SET | |
| { 528, 0, 0, 4, 129, 0, 0x0ULL, nullptr, ImplicitList26, nullptr, -1 ,nullptr }, // Inst #528 = CR6UNSET | |
| { 529, 3, 1, 4, 129, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #529 = CRAND | |
| { 530, 3, 1, 4, 129, 0, 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #530 = CRANDC | |
| { 531, 3, 1, 4, 129, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #531 = CREQV | |
| { 532, 3, 1, 4, 129, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #532 = CRNAND | |
| { 533, 3, 1, 4, 129, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #533 = CRNOR | |
| { 534, 3, 1, 4, 129, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #534 = CROR | |
| { 535, 3, 1, 4, 129, 0, 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #535 = CRORC | |
| { 536, 1, 1, 4, 129, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #536 = CRSET | |
| { 537, 1, 1, 4, 129, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #537 = CRUNSET | |
| { 538, 3, 1, 4, 129, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #538 = CRXOR | |
| { 539, 3, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #539 = CTRL_DEP | |
| { 540, 2, 1, 4, 181, 0, 0x8ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #540 = DARN | |
| { 541, 2, 0, 4, 314, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #541 = DCBA | |
| { 542, 3, 0, 4, 175, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #542 = DCBF | |
| { 543, 2, 0, 4, 175, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #543 = DCBFEP | |
| { 544, 2, 0, 4, 314, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #544 = DCBI | |
| { 545, 2, 0, 4, 175, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #545 = DCBST | |
| { 546, 2, 0, 4, 175, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #546 = DCBSTEP | |
| { 547, 3, 0, 4, 175, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #547 = DCBT | |
| { 548, 3, 0, 4, 175, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #548 = DCBTEP | |
| { 549, 3, 0, 4, 175, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #549 = DCBTST | |
| { 550, 3, 0, 4, 175, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #550 = DCBTSTEP | |
| { 551, 2, 0, 4, 175, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #551 = DCBZ | |
| { 552, 2, 0, 4, 175, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #552 = DCBZEP | |
| { 553, 2, 0, 4, 175, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #553 = DCBZL | |
| { 554, 2, 0, 4, 175, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #554 = DCBZLEP | |
| { 555, 2, 0, 4, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #555 = DCCCI | |
| { 556, 3, 1, 4, 238, 0, 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #556 = DIVD | |
| { 557, 3, 1, 4, 239, 0, 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #557 = DIVDE | |
| { 558, 3, 1, 4, 239, 0, 0x8ULL, nullptr, ImplicitList2, OperandInfo56, -1 ,nullptr }, // Inst #558 = DIVDEO | |
| { 559, 3, 1, 4, 243, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo56, -1 ,nullptr }, // Inst #559 = DIVDEO_rec | |
| { 560, 3, 1, 4, 239, 0, 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #560 = DIVDEU | |
| { 561, 3, 1, 4, 239, 0, 0x8ULL, nullptr, ImplicitList2, OperandInfo56, -1 ,nullptr }, // Inst #561 = DIVDEUO | |
| { 562, 3, 1, 4, 243, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo56, -1 ,nullptr }, // Inst #562 = DIVDEUO_rec | |
| { 563, 3, 1, 4, 243, 0, 0xdULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #563 = DIVDEU_rec | |
| { 564, 3, 1, 4, 243, 0, 0xdULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #564 = DIVDE_rec | |
| { 565, 3, 1, 4, 238, 0, 0x8ULL, nullptr, ImplicitList2, OperandInfo56, -1 ,nullptr }, // Inst #565 = DIVDO | |
| { 566, 3, 1, 4, 241, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo56, -1 ,nullptr }, // Inst #566 = DIVDO_rec | |
| { 567, 3, 1, 4, 238, 0, 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #567 = DIVDU | |
| { 568, 3, 1, 4, 238, 0, 0x8ULL, nullptr, ImplicitList2, OperandInfo56, -1 ,nullptr }, // Inst #568 = DIVDUO | |
| { 569, 3, 1, 4, 241, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo56, -1 ,nullptr }, // Inst #569 = DIVDUO_rec | |
| { 570, 3, 1, 4, 241, 0, 0xdULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #570 = DIVDU_rec | |
| { 571, 3, 1, 4, 241, 0, 0xdULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #571 = DIVD_rec | |
| { 572, 3, 1, 4, 236, 0, 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #572 = DIVW | |
| { 573, 3, 1, 4, 237, 0, 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #573 = DIVWE | |
| { 574, 3, 1, 4, 237, 0, 0x8ULL, nullptr, ImplicitList2, OperandInfo55, -1 ,nullptr }, // Inst #574 = DIVWEO | |
| { 575, 3, 1, 4, 242, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo55, -1 ,nullptr }, // Inst #575 = DIVWEO_rec | |
| { 576, 3, 1, 4, 237, 0, 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #576 = DIVWEU | |
| { 577, 3, 1, 4, 237, 0, 0x8ULL, nullptr, ImplicitList2, OperandInfo55, -1 ,nullptr }, // Inst #577 = DIVWEUO | |
| { 578, 3, 1, 4, 242, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo55, -1 ,nullptr }, // Inst #578 = DIVWEUO_rec | |
| { 579, 3, 1, 4, 242, 0, 0xdULL, nullptr, ImplicitList4, OperandInfo55, -1 ,nullptr }, // Inst #579 = DIVWEU_rec | |
| { 580, 3, 1, 4, 242, 0, 0xdULL, nullptr, ImplicitList4, OperandInfo55, -1 ,nullptr }, // Inst #580 = DIVWE_rec | |
| { 581, 3, 1, 4, 236, 0, 0x8ULL, nullptr, ImplicitList2, OperandInfo55, -1 ,nullptr }, // Inst #581 = DIVWO | |
| { 582, 3, 1, 4, 240, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo55, -1 ,nullptr }, // Inst #582 = DIVWO_rec | |
| { 583, 3, 1, 4, 236, 0, 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #583 = DIVWU | |
| { 584, 3, 1, 4, 236, 0, 0x8ULL, nullptr, ImplicitList2, OperandInfo55, -1 ,nullptr }, // Inst #584 = DIVWUO | |
| { 585, 3, 1, 4, 240, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo55, -1 ,nullptr }, // Inst #585 = DIVWUO_rec | |
| { 586, 3, 1, 4, 240, 0, 0xdULL, nullptr, ImplicitList4, OperandInfo55, -1 ,nullptr }, // Inst #586 = DIVWU_rec | |
| { 587, 3, 1, 4, 240, 0, 0xdULL, nullptr, ImplicitList4, OperandInfo55, -1 ,nullptr }, // Inst #587 = DIVW_rec | |
| { 588, 1, 0, 4, 299, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, PPC::DeprecatedDST ,nullptr }, // Inst #588 = DSS | |
| { 589, 0, 0, 4, 299, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, PPC::DeprecatedDST ,nullptr }, // Inst #589 = DSSALL | |
| { 590, 3, 0, 4, 299, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, PPC::DeprecatedDST ,nullptr }, // Inst #590 = DST | |
| { 591, 3, 0, 4, 299, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo88, PPC::DeprecatedDST ,nullptr }, // Inst #591 = DST64 | |
| { 592, 3, 0, 4, 299, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, PPC::DeprecatedDST ,nullptr }, // Inst #592 = DSTST | |
| { 593, 3, 0, 4, 299, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo88, PPC::DeprecatedDST ,nullptr }, // Inst #593 = DSTST64 | |
| { 594, 3, 0, 4, 299, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, PPC::DeprecatedDST ,nullptr }, // Inst #594 = DSTSTT | |
| { 595, 3, 0, 4, 299, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo88, PPC::DeprecatedDST ,nullptr }, // Inst #595 = DSTSTT64 | |
| { 596, 3, 0, 4, 299, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, PPC::DeprecatedDST ,nullptr }, // Inst #596 = DSTT | |
| { 597, 3, 0, 4, 299, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo88, PPC::DeprecatedDST ,nullptr }, // Inst #597 = DSTT64 | |
| { 598, 4, 1, 4, 0, 0, 0x0ULL, ImplicitList11, ImplicitList11, OperandInfo89, -1 ,nullptr }, // Inst #598 = DYNALLOC | |
| { 599, 4, 1, 4, 0, 0, 0x0ULL, ImplicitList27, ImplicitList27, OperandInfo90, -1 ,nullptr }, // Inst #599 = DYNALLOC8 | |
| { 600, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #600 = DYNAREAOFFSET | |
| { 601, 3, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #601 = DYNAREAOFFSET8 | |
| { 602, 2, 1, 4, 16, 0, 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #602 = EFDABS | |
| { 603, 3, 1, 4, 17, 0, 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #603 = EFDADD | |
| { 604, 2, 1, 4, 16, 0, 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #604 = EFDCFS | |
| { 605, 2, 1, 4, 16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #605 = EFDCFSF | |
| { 606, 2, 1, 4, 16, 0, 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #606 = EFDCFSI | |
| { 607, 2, 1, 4, 16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #607 = EFDCFSID | |
| { 608, 2, 1, 4, 16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #608 = EFDCFUF | |
| { 609, 2, 1, 4, 16, 0, 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #609 = EFDCFUI | |
| { 610, 2, 1, 4, 16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #610 = EFDCFUID | |
| { 611, 3, 1, 4, 16, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #611 = EFDCMPEQ | |
| { 612, 3, 1, 4, 16, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #612 = EFDCMPGT | |
| { 613, 3, 1, 4, 16, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #613 = EFDCMPLT | |
| { 614, 2, 1, 4, 16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #614 = EFDCTSF | |
| { 615, 2, 1, 4, 16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #615 = EFDCTSI | |
| { 616, 2, 1, 4, 16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #616 = EFDCTSIDZ | |
| { 617, 2, 1, 4, 16, 0, 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #617 = EFDCTSIZ | |
| { 618, 2, 1, 4, 16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #618 = EFDCTUF | |
| { 619, 2, 1, 4, 16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #619 = EFDCTUI | |
| { 620, 2, 1, 4, 16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #620 = EFDCTUIDZ | |
| { 621, 2, 1, 4, 16, 0, 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #621 = EFDCTUIZ | |
| { 622, 3, 1, 4, 18, 0, 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #622 = EFDDIV | |
| { 623, 3, 1, 4, 16, 0, 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #623 = EFDMUL | |
| { 624, 2, 1, 4, 16, 0, 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #624 = EFDNABS | |
| { 625, 2, 1, 4, 16, 0, 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #625 = EFDNEG | |
| { 626, 3, 1, 4, 16, 0, 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #626 = EFDSUB | |
| { 627, 3, 1, 4, 16, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #627 = EFDTSTEQ | |
| { 628, 3, 1, 4, 16, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #628 = EFDTSTGT | |
| { 629, 3, 1, 4, 16, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #629 = EFDTSTLT | |
| { 630, 2, 1, 4, 19, 0, 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #630 = EFSABS | |
| { 631, 3, 1, 4, 17, 0, 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #631 = EFSADD | |
| { 632, 2, 1, 4, 19, 0, 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #632 = EFSCFD | |
| { 633, 2, 1, 4, 19, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #633 = EFSCFSF | |
| { 634, 2, 1, 4, 19, 0, 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #634 = EFSCFSI | |
| { 635, 2, 1, 4, 19, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #635 = EFSCFUF | |
| { 636, 2, 1, 4, 19, 0, 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #636 = EFSCFUI | |
| { 637, 3, 1, 4, 20, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #637 = EFSCMPEQ | |
| { 638, 3, 1, 4, 20, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #638 = EFSCMPGT | |
| { 639, 3, 1, 4, 20, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #639 = EFSCMPLT | |
| { 640, 2, 1, 4, 19, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #640 = EFSCTSF | |
| { 641, 2, 1, 4, 19, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #641 = EFSCTSI | |
| { 642, 2, 1, 4, 19, 0, 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #642 = EFSCTSIZ | |
| { 643, 2, 1, 4, 19, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #643 = EFSCTUF | |
| { 644, 2, 1, 4, 19, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #644 = EFSCTUI | |
| { 645, 2, 1, 4, 19, 0, 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #645 = EFSCTUIZ | |
| { 646, 3, 1, 4, 18, 0, 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #646 = EFSDIV | |
| { 647, 3, 1, 4, 21, 0, 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #647 = EFSMUL | |
| { 648, 2, 1, 4, 21, 0, 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #648 = EFSNABS | |
| { 649, 2, 1, 4, 21, 0, 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #649 = EFSNEG | |
| { 650, 3, 1, 4, 19, 0, 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #650 = EFSSUB | |
| { 651, 3, 1, 4, 20, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #651 = EFSTSTEQ | |
| { 652, 3, 1, 4, 20, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #652 = EFSTSTGT | |
| { 653, 3, 1, 4, 20, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #653 = EFSTSTLT | |
| { 654, 1, 0, 4, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #654 = EH_SjLj_LongJmp32 | |
| { 655, 1, 0, 4, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #655 = EH_SjLj_LongJmp64 | |
| { 656, 2, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList12, OperandInfo98, -1 ,nullptr }, // Inst #656 = EH_SjLj_SetJmp32 | |
| { 657, 2, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList13, OperandInfo98, -1 ,nullptr }, // Inst #657 = EH_SjLj_SetJmp64 | |
| { 658, 1, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #658 = EH_SjLj_Setup | |
| { 659, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #659 = EQV | |
| { 660, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #660 = EQV8 | |
| { 661, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #661 = EQV8_rec | |
| { 662, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList4, OperandInfo55, -1 ,nullptr }, // Inst #662 = EQV_rec | |
| { 663, 2, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #663 = EVABS | |
| { 664, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #664 = EVADDIW | |
| { 665, 2, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #665 = EVADDSMIAAW | |
| { 666, 2, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #666 = EVADDSSIAAW | |
| { 667, 2, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #667 = EVADDUMIAAW | |
| { 668, 2, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #668 = EVADDUSIAAW | |
| { 669, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #669 = EVADDW | |
| { 670, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #670 = EVAND | |
| { 671, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #671 = EVANDC | |
| { 672, 3, 1, 4, 292, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #672 = EVCMPEQ | |
| { 673, 3, 1, 4, 292, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #673 = EVCMPGTS | |
| { 674, 3, 1, 4, 292, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #674 = EVCMPGTU | |
| { 675, 3, 1, 4, 292, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #675 = EVCMPLTS | |
| { 676, 3, 1, 4, 292, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #676 = EVCMPLTU | |
| { 677, 2, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #677 = EVCNTLSW | |
| { 678, 2, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #678 = EVCNTLZW | |
| { 679, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #679 = EVDIVWS | |
| { 680, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #680 = EVDIVWU | |
| { 681, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #681 = EVEQV | |
| { 682, 2, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #682 = EVEXTSB | |
| { 683, 2, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #683 = EVEXTSH | |
| { 684, 2, 1, 4, 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #684 = EVFSABS | |
| { 685, 3, 1, 4, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #685 = EVFSADD | |
| { 686, 2, 1, 4, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #686 = EVFSCFSF | |
| { 687, 2, 1, 4, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #687 = EVFSCFSI | |
| { 688, 2, 1, 4, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #688 = EVFSCFUF | |
| { 689, 2, 1, 4, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #689 = EVFSCFUI | |
| { 690, 3, 1, 4, 19, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #690 = EVFSCMPEQ | |
| { 691, 3, 1, 4, 19, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #691 = EVFSCMPGT | |
| { 692, 3, 1, 4, 19, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #692 = EVFSCMPLT | |
| { 693, 2, 1, 4, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #693 = EVFSCTSF | |
| { 694, 2, 1, 4, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #694 = EVFSCTSI | |
| { 695, 2, 1, 4, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #695 = EVFSCTSIZ | |
| { 696, 2, 1, 4, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #696 = EVFSCTUF | |
| { 697, 2, 1, 4, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #697 = EVFSCTUI | |
| { 698, 2, 1, 4, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #698 = EVFSCTUIZ | |
| { 699, 3, 1, 4, 18, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #699 = EVFSDIV | |
| { 700, 3, 1, 4, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #700 = EVFSMUL | |
| { 701, 2, 1, 4, 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #701 = EVFSNABS | |
| { 702, 2, 1, 4, 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #702 = EVFSNEG | |
| { 703, 3, 1, 4, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #703 = EVFSSUB | |
| { 704, 3, 1, 4, 22, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #704 = EVFSTSTEQ | |
| { 705, 3, 1, 4, 22, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #705 = EVFSTSTGT | |
| { 706, 3, 1, 4, 22, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #706 = EVFSTSTLT | |
| { 707, 3, 1, 4, 294, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #707 = EVLDD | |
| { 708, 3, 1, 4, 294, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #708 = EVLDDX | |
| { 709, 3, 1, 4, 294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #709 = EVLDH | |
| { 710, 3, 1, 4, 294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #710 = EVLDHX | |
| { 711, 3, 1, 4, 294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #711 = EVLDW | |
| { 712, 3, 1, 4, 294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #712 = EVLDWX | |
| { 713, 3, 1, 4, 294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #713 = EVLHHESPLAT | |
| { 714, 3, 1, 4, 294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #714 = EVLHHESPLATX | |
| { 715, 3, 1, 4, 294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #715 = EVLHHOSSPLAT | |
| { 716, 3, 1, 4, 294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #716 = EVLHHOSSPLATX | |
| { 717, 3, 1, 4, 294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #717 = EVLHHOUSPLAT | |
| { 718, 3, 1, 4, 294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #718 = EVLHHOUSPLATX | |
| { 719, 3, 1, 4, 294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #719 = EVLWHE | |
| { 720, 3, 1, 4, 294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #720 = EVLWHEX | |
| { 721, 3, 1, 4, 294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #721 = EVLWHOS | |
| { 722, 3, 1, 4, 294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #722 = EVLWHOSX | |
| { 723, 3, 1, 4, 294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #723 = EVLWHOU | |
| { 724, 3, 1, 4, 294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #724 = EVLWHOUX | |
| { 725, 3, 1, 4, 294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #725 = EVLWHSPLAT | |
| { 726, 3, 1, 4, 294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #726 = EVLWHSPLATX | |
| { 727, 3, 1, 4, 294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #727 = EVLWWSPLAT | |
| { 728, 3, 1, 4, 294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #728 = EVLWWSPLATX | |
| { 729, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #729 = EVMERGEHI | |
| { 730, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #730 = EVMERGEHILO | |
| { 731, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #731 = EVMERGELO | |
| { 732, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #732 = EVMERGELOHI | |
| { 733, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #733 = EVMHEGSMFAA | |
| { 734, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #734 = EVMHEGSMFAN | |
| { 735, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #735 = EVMHEGSMIAA | |
| { 736, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #736 = EVMHEGSMIAN | |
| { 737, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #737 = EVMHEGUMIAA | |
| { 738, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #738 = EVMHEGUMIAN | |
| { 739, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #739 = EVMHESMF | |
| { 740, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #740 = EVMHESMFA | |
| { 741, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #741 = EVMHESMFAAW | |
| { 742, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #742 = EVMHESMFANW | |
| { 743, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #743 = EVMHESMI | |
| { 744, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #744 = EVMHESMIA | |
| { 745, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #745 = EVMHESMIAAW | |
| { 746, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #746 = EVMHESMIANW | |
| { 747, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #747 = EVMHESSF | |
| { 748, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #748 = EVMHESSFA | |
| { 749, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #749 = EVMHESSFAAW | |
| { 750, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #750 = EVMHESSFANW | |
| { 751, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #751 = EVMHESSIAAW | |
| { 752, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #752 = EVMHESSIANW | |
| { 753, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #753 = EVMHEUMI | |
| { 754, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #754 = EVMHEUMIA | |
| { 755, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #755 = EVMHEUMIAAW | |
| { 756, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #756 = EVMHEUMIANW | |
| { 757, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #757 = EVMHEUSIAAW | |
| { 758, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #758 = EVMHEUSIANW | |
| { 759, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #759 = EVMHOGSMFAA | |
| { 760, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #760 = EVMHOGSMFAN | |
| { 761, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #761 = EVMHOGSMIAA | |
| { 762, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #762 = EVMHOGSMIAN | |
| { 763, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #763 = EVMHOGUMIAA | |
| { 764, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #764 = EVMHOGUMIAN | |
| { 765, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #765 = EVMHOSMF | |
| { 766, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #766 = EVMHOSMFA | |
| { 767, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #767 = EVMHOSMFAAW | |
| { 768, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #768 = EVMHOSMFANW | |
| { 769, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #769 = EVMHOSMI | |
| { 770, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #770 = EVMHOSMIA | |
| { 771, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #771 = EVMHOSMIAAW | |
| { 772, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #772 = EVMHOSMIANW | |
| { 773, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #773 = EVMHOSSF | |
| { 774, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #774 = EVMHOSSFA | |
| { 775, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #775 = EVMHOSSFAAW | |
| { 776, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #776 = EVMHOSSFANW | |
| { 777, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #777 = EVMHOSSIAAW | |
| { 778, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #778 = EVMHOSSIANW | |
| { 779, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #779 = EVMHOUMI | |
| { 780, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #780 = EVMHOUMIA | |
| { 781, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #781 = EVMHOUMIAAW | |
| { 782, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #782 = EVMHOUMIANW | |
| { 783, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #783 = EVMHOUSIAAW | |
| { 784, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #784 = EVMHOUSIANW | |
| { 785, 2, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #785 = EVMRA | |
| { 786, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #786 = EVMWHSMF | |
| { 787, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #787 = EVMWHSMFA | |
| { 788, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #788 = EVMWHSMI | |
| { 789, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #789 = EVMWHSMIA | |
| { 790, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #790 = EVMWHSSF | |
| { 791, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #791 = EVMWHSSFA | |
| { 792, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #792 = EVMWHUMI | |
| { 793, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #793 = EVMWHUMIA | |
| { 794, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #794 = EVMWLSMIAAW | |
| { 795, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #795 = EVMWLSMIANW | |
| { 796, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #796 = EVMWLSSIAAW | |
| { 797, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #797 = EVMWLSSIANW | |
| { 798, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #798 = EVMWLUMI | |
| { 799, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #799 = EVMWLUMIA | |
| { 800, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #800 = EVMWLUMIAAW | |
| { 801, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #801 = EVMWLUMIANW | |
| { 802, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #802 = EVMWLUSIAAW | |
| { 803, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #803 = EVMWLUSIANW | |
| { 804, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #804 = EVMWSMF | |
| { 805, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #805 = EVMWSMFA | |
| { 806, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #806 = EVMWSMFAA | |
| { 807, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #807 = EVMWSMFAN | |
| { 808, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #808 = EVMWSMI | |
| { 809, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #809 = EVMWSMIA | |
| { 810, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #810 = EVMWSMIAA | |
| { 811, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #811 = EVMWSMIAN | |
| { 812, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #812 = EVMWSSF | |
| { 813, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #813 = EVMWSSFA | |
| { 814, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #814 = EVMWSSFAA | |
| { 815, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #815 = EVMWSSFAN | |
| { 816, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #816 = EVMWUMI | |
| { 817, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #817 = EVMWUMIA | |
| { 818, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #818 = EVMWUMIAA | |
| { 819, 3, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #819 = EVMWUMIAN | |
| { 820, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #820 = EVNAND | |
| { 821, 2, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #821 = EVNEG | |
| { 822, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #822 = EVNOR | |
| { 823, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #823 = EVOR | |
| { 824, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #824 = EVORC | |
| { 825, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #825 = EVRLW | |
| { 826, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #826 = EVRLWI | |
| { 827, 2, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #827 = EVRNDW | |
| { 828, 4, 1, 4, 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #828 = EVSEL | |
| { 829, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #829 = EVSLW | |
| { 830, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #830 = EVSLWI | |
| { 831, 2, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #831 = EVSPLATFI | |
| { 832, 2, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #832 = EVSPLATI | |
| { 833, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #833 = EVSRWIS | |
| { 834, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #834 = EVSRWIU | |
| { 835, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #835 = EVSRWS | |
| { 836, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #836 = EVSRWU | |
| { 837, 3, 0, 4, 295, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #837 = EVSTDD | |
| { 838, 3, 0, 4, 295, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #838 = EVSTDDX | |
| { 839, 3, 0, 4, 295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #839 = EVSTDH | |
| { 840, 3, 0, 4, 295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #840 = EVSTDHX | |
| { 841, 3, 0, 4, 295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #841 = EVSTDW | |
| { 842, 3, 0, 4, 295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #842 = EVSTDWX | |
| { 843, 3, 0, 4, 295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #843 = EVSTWHE | |
| { 844, 3, 0, 4, 295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #844 = EVSTWHEX | |
| { 845, 3, 0, 4, 295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #845 = EVSTWHO | |
| { 846, 3, 0, 4, 295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #846 = EVSTWHOX | |
| { 847, 3, 0, 4, 295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #847 = EVSTWWE | |
| { 848, 3, 0, 4, 295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #848 = EVSTWWEX | |
| { 849, 3, 0, 4, 295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #849 = EVSTWWO | |
| { 850, 3, 0, 4, 295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #850 = EVSTWWOX | |
| { 851, 2, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #851 = EVSUBFSMIAAW | |
| { 852, 2, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #852 = EVSUBFSSIAAW | |
| { 853, 2, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #853 = EVSUBFUMIAAW | |
| { 854, 2, 1, 4, 293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #854 = EVSUBFUSIAAW | |
| { 855, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #855 = EVSUBFW | |
| { 856, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #856 = EVSUBIFW | |
| { 857, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #857 = EVXOR | |
| { 858, 2, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #858 = EXTSB | |
| { 859, 2, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #859 = EXTSB8 | |
| { 860, 2, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #860 = EXTSB8_32_64 | |
| { 861, 2, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo61, -1 ,nullptr }, // Inst #861 = EXTSB8_rec | |
| { 862, 2, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo43, -1 ,nullptr }, // Inst #862 = EXTSB_rec | |
| { 863, 2, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #863 = EXTSH | |
| { 864, 2, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #864 = EXTSH8 | |
| { 865, 2, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #865 = EXTSH8_32_64 | |
| { 866, 2, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo61, -1 ,nullptr }, // Inst #866 = EXTSH8_rec | |
| { 867, 2, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo43, -1 ,nullptr }, // Inst #867 = EXTSH_rec | |
| { 868, 2, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #868 = EXTSW | |
| { 869, 3, 1, 4, 112, 0, 0x8ULL, nullptr, ImplicitList5, OperandInfo41, -1 ,nullptr }, // Inst #869 = EXTSWSLI | |
| { 870, 3, 1, 4, 112, 0, 0x8ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #870 = EXTSWSLI_32_64 | |
| { 871, 3, 1, 4, 257, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo107, -1 ,nullptr }, // Inst #871 = EXTSWSLI_32_64_rec | |
| { 872, 3, 1, 4, 257, 0, 0x8ULL, nullptr, ImplicitList8, OperandInfo41, -1 ,nullptr }, // Inst #872 = EXTSWSLI_rec | |
| { 873, 2, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #873 = EXTSW_32 | |
| { 874, 2, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #874 = EXTSW_32_64 | |
| { 875, 2, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo106, -1 ,nullptr }, // Inst #875 = EXTSW_32_64_rec | |
| { 876, 2, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo61, -1 ,nullptr }, // Inst #876 = EXTSW_rec | |
| { 877, 0, 0, 4, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #877 = EnforceIEIO | |
| { 878, 2, 1, 4, 131, 0, 0x18ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #878 = FABSD | |
| { 879, 2, 1, 4, 246, 0, 0x18ULL, nullptr, ImplicitList28, OperandInfo108, -1 ,nullptr }, // Inst #879 = FABSD_rec | |
| { 880, 2, 1, 4, 131, 0, 0x18ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #880 = FABSS | |
| { 881, 2, 1, 4, 246, 0, 0x18ULL, nullptr, ImplicitList28, OperandInfo109, -1 ,nullptr }, // Inst #881 = FABSS_rec | |
| { 882, 3, 1, 4, 149, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #882 = FADD | |
| { 883, 3, 1, 4, 148, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #883 = FADDS | |
| { 884, 3, 1, 4, 156, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo111, -1 ,nullptr }, // Inst #884 = FADDS_rec | |
| { 885, 3, 1, 4, 157, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo110, -1 ,nullptr }, // Inst #885 = FADD_rec | |
| { 886, 3, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList18, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #886 = FADDrtz | |
| { 887, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #887 = FCFID | |
| { 888, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #888 = FCFIDS | |
| { 889, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo112, -1 ,nullptr }, // Inst #889 = FCFIDS_rec | |
| { 890, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #890 = FCFIDU | |
| { 891, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #891 = FCFIDUS | |
| { 892, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo112, -1 ,nullptr }, // Inst #892 = FCFIDUS_rec | |
| { 893, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo108, -1 ,nullptr }, // Inst #893 = FCFIDU_rec | |
| { 894, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo108, -1 ,nullptr }, // Inst #894 = FCFID_rec | |
| { 895, 3, 1, 4, 106, 0|(1ULL<<MCID::Compare), 0x18ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #895 = FCMPUD | |
| { 896, 3, 1, 4, 106, 0|(1ULL<<MCID::Compare), 0x18ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #896 = FCMPUS | |
| { 897, 3, 1, 4, 131, 0, 0x18ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #897 = FCPSGND | |
| { 898, 3, 1, 4, 246, 0, 0x18ULL, nullptr, ImplicitList28, OperandInfo110, -1 ,nullptr }, // Inst #898 = FCPSGND_rec | |
| { 899, 3, 1, 4, 131, 0, 0x18ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #899 = FCPSGNS | |
| { 900, 3, 1, 4, 246, 0, 0x18ULL, nullptr, ImplicitList28, OperandInfo111, -1 ,nullptr }, // Inst #900 = FCPSGNS_rec | |
| { 901, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #901 = FCTID | |
| { 902, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #902 = FCTIDU | |
| { 903, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #903 = FCTIDUZ | |
| { 904, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo108, -1 ,nullptr }, // Inst #904 = FCTIDUZ_rec | |
| { 905, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo108, -1 ,nullptr }, // Inst #905 = FCTIDU_rec | |
| { 906, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #906 = FCTIDZ | |
| { 907, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo108, -1 ,nullptr }, // Inst #907 = FCTIDZ_rec | |
| { 908, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo108, -1 ,nullptr }, // Inst #908 = FCTID_rec | |
| { 909, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #909 = FCTIW | |
| { 910, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #910 = FCTIWU | |
| { 911, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #911 = FCTIWUZ | |
| { 912, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo108, -1 ,nullptr }, // Inst #912 = FCTIWUZ_rec | |
| { 913, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo108, -1 ,nullptr }, // Inst #913 = FCTIWU_rec | |
| { 914, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #914 = FCTIWZ | |
| { 915, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo108, -1 ,nullptr }, // Inst #915 = FCTIWZ_rec | |
| { 916, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo108, -1 ,nullptr }, // Inst #916 = FCTIW_rec | |
| { 917, 3, 1, 4, 259, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #917 = FDIV | |
| { 918, 3, 1, 4, 270, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #918 = FDIVS | |
| { 919, 3, 1, 4, 271, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo111, -1 ,nullptr }, // Inst #919 = FDIVS_rec | |
| { 920, 3, 1, 4, 260, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo110, -1 ,nullptr }, // Inst #920 = FDIV_rec | |
| { 921, 4, 1, 4, 150, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #921 = FMADD | |
| { 922, 4, 1, 4, 148, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #922 = FMADDS | |
| { 923, 4, 1, 4, 156, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo116, -1 ,nullptr }, // Inst #923 = FMADDS_rec | |
| { 924, 4, 1, 4, 158, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo115, -1 ,nullptr }, // Inst #924 = FMADD_rec | |
| { 925, 2, 1, 4, 131, 0, 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #925 = FMR | |
| { 926, 2, 1, 4, 246, 0, 0x0ULL, nullptr, ImplicitList28, OperandInfo109, -1 ,nullptr }, // Inst #926 = FMR_rec | |
| { 927, 4, 1, 4, 150, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #927 = FMSUB | |
| { 928, 4, 1, 4, 148, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #928 = FMSUBS | |
| { 929, 4, 1, 4, 156, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo116, -1 ,nullptr }, // Inst #929 = FMSUBS_rec | |
| { 930, 4, 1, 4, 158, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo115, -1 ,nullptr }, // Inst #930 = FMSUB_rec | |
| { 931, 3, 1, 4, 150, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #931 = FMUL | |
| { 932, 3, 1, 4, 148, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #932 = FMULS | |
| { 933, 3, 1, 4, 156, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo111, -1 ,nullptr }, // Inst #933 = FMULS_rec | |
| { 934, 3, 1, 4, 158, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo110, -1 ,nullptr }, // Inst #934 = FMUL_rec | |
| { 935, 2, 1, 4, 131, 0, 0x18ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #935 = FNABSD | |
| { 936, 2, 1, 4, 246, 0, 0x18ULL, nullptr, ImplicitList28, OperandInfo108, -1 ,nullptr }, // Inst #936 = FNABSD_rec | |
| { 937, 2, 1, 4, 131, 0, 0x18ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #937 = FNABSS | |
| { 938, 2, 1, 4, 246, 0, 0x18ULL, nullptr, ImplicitList28, OperandInfo109, -1 ,nullptr }, // Inst #938 = FNABSS_rec | |
| { 939, 2, 1, 4, 131, 0, 0x18ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #939 = FNEGD | |
| { 940, 2, 1, 4, 246, 0, 0x18ULL, nullptr, ImplicitList28, OperandInfo108, -1 ,nullptr }, // Inst #940 = FNEGD_rec | |
| { 941, 2, 1, 4, 131, 0, 0x18ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #941 = FNEGS | |
| { 942, 2, 1, 4, 246, 0, 0x18ULL, nullptr, ImplicitList28, OperandInfo109, -1 ,nullptr }, // Inst #942 = FNEGS_rec | |
| { 943, 4, 1, 4, 150, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #943 = FNMADD | |
| { 944, 4, 1, 4, 148, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #944 = FNMADDS | |
| { 945, 4, 1, 4, 156, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo116, -1 ,nullptr }, // Inst #945 = FNMADDS_rec | |
| { 946, 4, 1, 4, 158, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo115, -1 ,nullptr }, // Inst #946 = FNMADD_rec | |
| { 947, 4, 1, 4, 150, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #947 = FNMSUB | |
| { 948, 4, 1, 4, 148, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #948 = FNMSUBS | |
| { 949, 4, 1, 4, 156, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo116, -1 ,nullptr }, // Inst #949 = FNMSUBS_rec | |
| { 950, 4, 1, 4, 158, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo115, -1 ,nullptr }, // Inst #950 = FNMSUB_rec | |
| { 951, 2, 1, 4, 148, 0, 0x18ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #951 = FRE | |
| { 952, 2, 1, 4, 148, 0, 0x18ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #952 = FRES | |
| { 953, 2, 1, 4, 156, 0, 0x18ULL, nullptr, ImplicitList28, OperandInfo109, -1 ,nullptr }, // Inst #953 = FRES_rec | |
| { 954, 2, 1, 4, 156, 0, 0x18ULL, nullptr, ImplicitList28, OperandInfo108, -1 ,nullptr }, // Inst #954 = FRE_rec | |
| { 955, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #955 = FRIMD | |
| { 956, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo108, -1 ,nullptr }, // Inst #956 = FRIMD_rec | |
| { 957, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #957 = FRIMS | |
| { 958, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo109, -1 ,nullptr }, // Inst #958 = FRIMS_rec | |
| { 959, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #959 = FRIND | |
| { 960, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo108, -1 ,nullptr }, // Inst #960 = FRIND_rec | |
| { 961, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #961 = FRINS | |
| { 962, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo109, -1 ,nullptr }, // Inst #962 = FRINS_rec | |
| { 963, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #963 = FRIPD | |
| { 964, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo108, -1 ,nullptr }, // Inst #964 = FRIPD_rec | |
| { 965, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #965 = FRIPS | |
| { 966, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo109, -1 ,nullptr }, // Inst #966 = FRIPS_rec | |
| { 967, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #967 = FRIZD | |
| { 968, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo108, -1 ,nullptr }, // Inst #968 = FRIZD_rec | |
| { 969, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #969 = FRIZS | |
| { 970, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo109, -1 ,nullptr }, // Inst #970 = FRIZS_rec | |
| { 971, 2, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #971 = FRSP | |
| { 972, 2, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo112, -1 ,nullptr }, // Inst #972 = FRSP_rec | |
| { 973, 2, 1, 4, 148, 0, 0x18ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #973 = FRSQRTE | |
| { 974, 2, 1, 4, 148, 0, 0x18ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #974 = FRSQRTES | |
| { 975, 2, 1, 4, 156, 0, 0x18ULL, nullptr, ImplicitList28, OperandInfo109, -1 ,nullptr }, // Inst #975 = FRSQRTES_rec | |
| { 976, 2, 1, 4, 156, 0, 0x18ULL, nullptr, ImplicitList28, OperandInfo108, -1 ,nullptr }, // Inst #976 = FRSQRTE_rec | |
| { 977, 4, 1, 4, 148, 0, 0x18ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #977 = FSELD | |
| { 978, 4, 1, 4, 152, 0, 0x18ULL, nullptr, ImplicitList28, OperandInfo115, -1 ,nullptr }, // Inst #978 = FSELD_rec | |
| { 979, 4, 1, 4, 148, 0, 0x18ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #979 = FSELS | |
| { 980, 4, 1, 4, 152, 0, 0x18ULL, nullptr, ImplicitList28, OperandInfo117, -1 ,nullptr }, // Inst #980 = FSELS_rec | |
| { 981, 2, 1, 4, 262, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #981 = FSQRT | |
| { 982, 2, 1, 4, 267, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #982 = FSQRTS | |
| { 983, 2, 1, 4, 268, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo109, -1 ,nullptr }, // Inst #983 = FSQRTS_rec | |
| { 984, 2, 1, 4, 265, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo108, -1 ,nullptr }, // Inst #984 = FSQRT_rec | |
| { 985, 3, 1, 4, 149, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #985 = FSUB | |
| { 986, 3, 1, 4, 148, 0, 0x18ULL, ImplicitList18, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #986 = FSUBS | |
| { 987, 3, 1, 4, 156, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo111, -1 ,nullptr }, // Inst #987 = FSUBS_rec | |
| { 988, 3, 1, 4, 157, 0, 0x18ULL, ImplicitList18, ImplicitList28, OperandInfo110, -1 ,nullptr }, // Inst #988 = FSUB_rec | |
| { 989, 3, 1, 4, 106, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x18ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #989 = FTDIV | |
| { 990, 2, 1, 4, 106, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x18ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #990 = FTSQRT | |
| { 991, 3, 1, 8, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList29, OperandInfo41, -1 ,nullptr }, // Inst #991 = GETtlsADDR | |
| { 992, 3, 1, 4, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList30, OperandInfo42, -1 ,nullptr }, // Inst #992 = GETtlsADDR32 | |
| { 993, 3, 1, 4, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList29, OperandInfo41, -1 ,nullptr }, // Inst #993 = GETtlsldADDR | |
| { 994, 3, 1, 4, 0, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList30, OperandInfo42, -1 ,nullptr }, // Inst #994 = GETtlsldADDR32 | |
| { 995, 0, 0, 4, 296, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #995 = HRFID | |
| { 996, 2, 0, 4, 178, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #996 = ICBI | |
| { 997, 2, 0, 4, 178, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #997 = ICBIEP | |
| { 998, 3, 0, 4, 300, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #998 = ICBLC | |
| { 999, 3, 0, 4, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #999 = ICBLQ | |
| { 1000, 3, 0, 4, 179, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1000 = ICBT | |
| { 1001, 3, 0, 4, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #1001 = ICBTLS | |
| { 1002, 2, 0, 4, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #1002 = ICCCI | |
| { 1003, 4, 1, 4, 133, 0|(1ULL<<MCID::Select), 0x8ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #1003 = ISEL | |
| { 1004, 4, 1, 4, 133, 0|(1ULL<<MCID::Select), 0x8ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #1004 = ISEL8 | |
| { 1005, 0, 0, 4, 184, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1005 = ISYNC | |
| { 1006, 3, 1, 4, 115, 0, 0x8ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1006 = LA | |
| { 1007, 3, 1, 4, 180, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1007 = LBARX | |
| { 1008, 3, 1, 4, 180, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1008 = LBARXL | |
| { 1009, 3, 1, 4, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1009 = LBEPX | |
| { 1010, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #1010 = LBZ | |
| { 1011, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1011 = LBZ8 | |
| { 1012, 3, 1, 4, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1012 = LBZCIX | |
| { 1013, 4, 2, 4, 280, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1013 = LBZU | |
| { 1014, 4, 2, 4, 280, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #1014 = LBZU8 | |
| { 1015, 4, 2, 4, 281, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #1015 = LBZUX | |
| { 1016, 4, 2, 4, 281, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #1016 = LBZUX8 | |
| { 1017, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1017 = LBZX | |
| { 1018, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #1018 = LBZX8 | |
| { 1019, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1019 = LBZXTLS | |
| { 1020, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1020 = LBZXTLS_ | |
| { 1021, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #1021 = LBZXTLS_32 | |
| { 1022, 3, 1, 4, 181, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1022 = LD | |
| { 1023, 3, 1, 4, 182, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #1023 = LDARX | |
| { 1024, 3, 1, 4, 182, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #1024 = LDARXL | |
| { 1025, 3, 1, 4, 289, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x80ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1025 = LDAT | |
| { 1026, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #1026 = LDBRX | |
| { 1027, 3, 1, 4, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1027 = LDCIX | |
| { 1028, 3, 1, 4, 201, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #1028 = LDMX | |
| { 1029, 4, 2, 4, 282, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #1029 = LDU | |
| { 1030, 4, 2, 4, 283, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #1030 = LDUX | |
| { 1031, 3, 1, 4, 181, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #1031 = LDX | |
| { 1032, 3, 1, 4, 181, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1032 = LDXTLS | |
| { 1033, 3, 1, 4, 181, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1033 = LDXTLS_ | |
| { 1034, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #1034 = LDgotTprelL | |
| { 1035, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1035 = LDgotTprelL32 | |
| { 1036, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1036 = LDtoc | |
| { 1037, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1037 = LDtocBA | |
| { 1038, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1038 = LDtocCPT | |
| { 1039, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1039 = LDtocJTI | |
| { 1040, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #1040 = LDtocL | |
| { 1041, 3, 1, 4, 189, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1041 = LFD | |
| { 1042, 3, 1, 4, 301, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1042 = LFDEPX | |
| { 1043, 4, 2, 4, 284, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1043 = LFDU | |
| { 1044, 4, 2, 4, 285, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1044 = LFDUX | |
| { 1045, 3, 1, 4, 189, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1045 = LFDX | |
| { 1046, 3, 1, 4, 206, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1046 = LFIWAX | |
| { 1047, 3, 1, 4, 189, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1047 = LFIWZX | |
| { 1048, 3, 1, 4, 209, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1048 = LFS | |
| { 1049, 4, 2, 4, 275, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1049 = LFSU | |
| { 1050, 4, 2, 4, 276, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1050 = LFSUX | |
| { 1051, 3, 1, 4, 209, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #1051 = LFSX | |
| { 1052, 3, 1, 4, 202, 0|(1ULL<<MCID::MayLoad), 0x14ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #1052 = LHA | |
| { 1053, 3, 1, 4, 202, 0|(1ULL<<MCID::MayLoad), 0x14ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1053 = LHA8 | |
| { 1054, 3, 1, 4, 180, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1054 = LHARX | |
| { 1055, 3, 1, 4, 180, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1055 = LHARXL | |
| { 1056, 4, 2, 4, 212, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1056 = LHAU | |
| { 1057, 4, 2, 4, 212, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #1057 = LHAU8 | |
| { 1058, 4, 2, 4, 213, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #1058 = LHAUX | |
| { 1059, 4, 2, 4, 213, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #1059 = LHAUX8 | |
| { 1060, 3, 1, 4, 202, 0|(1ULL<<MCID::MayLoad), 0x94ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1060 = LHAX | |
| { 1061, 3, 1, 4, 202, 0|(1ULL<<MCID::MayLoad), 0x94ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #1061 = LHAX8 | |
| { 1062, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1062 = LHBRX | |
| { 1063, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #1063 = LHBRX8 | |
| { 1064, 3, 1, 4, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1064 = LHEPX | |
| { 1065, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #1065 = LHZ | |
| { 1066, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1066 = LHZ8 | |
| { 1067, 3, 1, 4, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1067 = LHZCIX | |
| { 1068, 4, 2, 4, 196, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1068 = LHZU | |
| { 1069, 4, 2, 4, 196, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #1069 = LHZU8 | |
| { 1070, 4, 2, 4, 197, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #1070 = LHZUX | |
| { 1071, 4, 2, 4, 197, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #1071 = LHZUX8 | |
| { 1072, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1072 = LHZX | |
| { 1073, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #1073 = LHZX8 | |
| { 1074, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1074 = LHZXTLS | |
| { 1075, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1075 = LHZXTLS_ | |
| { 1076, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #1076 = LHZXTLS_32 | |
| { 1077, 2, 1, 4, 116, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x8ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1077 = LI | |
| { 1078, 2, 1, 4, 116, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x8ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #1078 = LI8 | |
| { 1079, 2, 1, 4, 116, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x8ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1079 = LIS | |
| { 1080, 2, 1, 4, 116, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x8ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #1080 = LIS8 | |
| { 1081, 3, 1, 4, 188, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #1081 = LMW | |
| { 1082, 3, 1, 4, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #1082 = LSWI | |
| { 1083, 3, 1, 4, 172, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1083 = LVEBX | |
| { 1084, 3, 1, 4, 172, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1084 = LVEHX | |
| { 1085, 3, 1, 4, 172, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1085 = LVEWX | |
| { 1086, 3, 1, 4, 160, 0, 0x90ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1086 = LVSL | |
| { 1087, 3, 1, 4, 160, 0, 0x90ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1087 = LVSR | |
| { 1088, 3, 1, 4, 172, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1088 = LVX | |
| { 1089, 3, 1, 4, 172, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1089 = LVXL | |
| { 1090, 3, 1, 4, 204, 0|(1ULL<<MCID::MayLoad), 0x14ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1090 = LWA | |
| { 1091, 3, 1, 4, 180, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1091 = LWARX | |
| { 1092, 3, 1, 4, 180, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1092 = LWARXL | |
| { 1093, 3, 1, 4, 289, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x80ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #1093 = LWAT | |
| { 1094, 4, 2, 4, 213, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #1094 = LWAUX | |
| { 1095, 3, 1, 4, 202, 0|(1ULL<<MCID::MayLoad), 0x94ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #1095 = LWAX | |
| { 1096, 3, 1, 4, 202, 0|(1ULL<<MCID::MayLoad), 0x94ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1096 = LWAX_32 | |
| { 1097, 3, 1, 4, 204, 0|(1ULL<<MCID::MayLoad), 0x14ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #1097 = LWA_32 | |
| { 1098, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1098 = LWBRX | |
| { 1099, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #1099 = LWBRX8 | |
| { 1100, 3, 1, 4, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1100 = LWEPX | |
| { 1101, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #1101 = LWZ | |
| { 1102, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1102 = LWZ8 | |
| { 1103, 3, 1, 4, 179, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1103 = LWZCIX | |
| { 1104, 4, 2, 4, 196, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #1104 = LWZU | |
| { 1105, 4, 2, 4, 196, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #1105 = LWZU8 | |
| { 1106, 4, 2, 4, 197, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #1106 = LWZUX | |
| { 1107, 4, 2, 4, 197, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #1107 = LWZUX8 | |
| { 1108, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1108 = LWZX | |
| { 1109, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x90ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #1109 = LWZX8 | |
| { 1110, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1110 = LWZXTLS | |
| { 1111, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1111 = LWZXTLS_ | |
| { 1112, 3, 1, 4, 179, 0|(1ULL<<MCID::MayLoad), 0x8ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #1112 = LWZXTLS_32 | |
| { 1113, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #1113 = LWZtoc | |
| { 1114, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1114 = LWZtocL | |
| { 1115, 3, 1, 4, 173, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #1115 = LXSD | |
| { 1116, 3, 1, 4, 173, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #1116 = LXSDX | |
| { 1117, 3, 1, 4, 173, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #1117 = LXSIBZX | |
| { 1118, 3, 1, 4, 173, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #1118 = LXSIHZX | |
| { 1119, 3, 1, 4, 207, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #1119 = LXSIWAX | |
| { 1120, 3, 1, 4, 173, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #1120 = LXSIWZX | |
| { 1121, 3, 1, 4, 210, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #1121 = LXSSP | |
| { 1122, 3, 1, 4, 210, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #1122 = LXSSPX | |
| { 1123, 3, 1, 4, 173, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr }, // Inst #1123 = LXV | |
| { 1124, 3, 1, 4, 173, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #1124 = LXVB16X | |
| { 1125, 3, 1, 4, 173, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #1125 = LXVD2X | |
| { 1126, 3, 1, 4, 214, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #1126 = LXVDSX | |
| { 1127, 3, 1, 4, 214, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #1127 = LXVH8X | |
| { 1128, 3, 1, 4, 171, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1128 = LXVL | |
| { 1129, 3, 1, 4, 171, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1129 = LXVLL | |
| { 1130, 3, 1, 4, 214, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #1130 = LXVW4X | |
| { 1131, 3, 1, 4, 173, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #1131 = LXVWSX | |
| { 1132, 3, 1, 4, 173, 0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #1132 = LXVX | |
| { 1133, 4, 1, 4, 144, 0, 0x8ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #1133 = MADDHD | |
| { 1134, 4, 1, 4, 144, 0, 0x8ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #1134 = MADDHDU | |
| { 1135, 4, 1, 4, 144, 0, 0x8ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1135 = MADDLD | |
| { 1136, 4, 1, 4, 144, 0, 0x8ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #1136 = MADDLD8 | |
| { 1137, 1, 0, 4, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1137 = MBAR | |
| { 1138, 2, 1, 4, 118, 0, 0x21ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #1138 = MCRF | |
| { 1139, 2, 1, 4, 247, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #1139 = MCRFS | |
| { 1140, 1, 1, 4, 119, 0, 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1140 = MCRXRX | |
| { 1141, 3, 1, 4, 296, 0, 0x1ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1141 = MFBHRBE | |
| { 1142, 1, 1, 4, 256, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x20ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1142 = MFCR | |
| { 1143, 1, 1, 4, 256, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x20ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1143 = MFCR8 | |
| { 1144, 1, 1, 4, 231, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, ImplicitList12, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1144 = MFCTR | |
| { 1145, 1, 1, 4, 231, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, ImplicitList13, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1145 = MFCTR8 | |
| { 1146, 2, 1, 4, 305, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1146 = MFDCR | |
| { 1147, 1, 1, 4, 255, 0, 0x1aULL, ImplicitList18, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1147 = MFFS | |
| { 1148, 2, 1, 4, 102, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList18, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1148 = MFFSCDRN | |
| { 1149, 2, 1, 4, 102, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList18, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #1149 = MFFSCDRNI | |
| { 1150, 1, 1, 4, 255, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList18, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1150 = MFFSCE | |
| { 1151, 2, 1, 4, 102, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList18, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #1151 = MFFSCRN | |
| { 1152, 2, 1, 4, 102, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList18, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #1152 = MFFSCRNI | |
| { 1153, 1, 1, 4, 255, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList18, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1153 = MFFSL | |
| { 1154, 1, 1, 4, 255, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList18, ImplicitList28, OperandInfo155, -1 ,nullptr }, // Inst #1154 = MFFS_rec | |
| { 1155, 1, 1, 4, 231, 0, 0x9ULL, ImplicitList15, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1155 = MFLR | |
| { 1156, 1, 1, 4, 231, 0, 0x9ULL, ImplicitList17, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1156 = MFLR8 | |
| { 1157, 1, 1, 4, 232, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1157 = MFMSR | |
| { 1158, 2, 1, 4, 127, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x21ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1158 = MFOCRF | |
| { 1159, 2, 1, 4, 127, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x21ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #1159 = MFOCRF8 | |
| { 1160, 2, 1, 4, 228, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1160 = MFPMR | |
| { 1161, 2, 1, 4, 231, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1161 = MFSPR | |
| { 1162, 2, 1, 4, 231, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1162 = MFSPR8 | |
| { 1163, 2, 1, 4, 303, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1163 = MFSR | |
| { 1164, 2, 1, 4, 303, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #1164 = MFSRIN | |
| { 1165, 2, 1, 4, 230, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1165 = MFTB | |
| { 1166, 1, 1, 4, 230, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1166 = MFTB8 | |
| { 1167, 2, 1, 4, 113, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #1167 = MFVRD | |
| { 1168, 1, 1, 4, 227, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1168 = MFVRSAVE | |
| { 1169, 2, 1, 4, 227, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1169 = MFVRSAVEv | |
| { 1170, 2, 1, 4, 113, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #1170 = MFVRWZ | |
| { 1171, 1, 1, 4, 136, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #1171 = MFVSCR | |
| { 1172, 2, 1, 4, 113, 0, 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #1172 = MFVSRD | |
| { 1173, 2, 1, 4, 163, 0, 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #1173 = MFVSRLD | |
| { 1174, 2, 1, 4, 113, 0, 0x0ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #1174 = MFVSRWZ | |
| { 1175, 3, 1, 4, 237, 0, 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1175 = MODSD | |
| { 1176, 3, 1, 4, 236, 0, 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1176 = MODSW | |
| { 1177, 3, 1, 4, 237, 0, 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1177 = MODUD | |
| { 1178, 3, 1, 4, 237, 0, 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1178 = MODUW | |
| { 1179, 0, 0, 4, 185, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1179 = MSGSYNC | |
| { 1180, 0, 0, 4, 310, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1180 = MSYNC | |
| { 1181, 2, 0, 4, 244, 0|(1ULL<<MCID::ExtraDefRegAllocReq), 0x20ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1181 = MTCRF | |
| { 1182, 2, 0, 4, 244, 0|(1ULL<<MCID::ExtraDefRegAllocReq), 0x20ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1182 = MTCRF8 | |
| { 1183, 1, 0, 4, 226, 0, 0x9ULL, nullptr, ImplicitList12, OperandInfo153, -1 ,nullptr }, // Inst #1183 = MTCTR | |
| { 1184, 1, 0, 4, 226, 0, 0x9ULL, nullptr, ImplicitList13, OperandInfo38, -1 ,nullptr }, // Inst #1184 = MTCTR8 | |
| { 1185, 1, 0, 4, 226, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, ImplicitList13, OperandInfo38, -1 ,nullptr }, // Inst #1185 = MTCTR8loop | |
| { 1186, 1, 0, 4, 226, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, ImplicitList12, OperandInfo153, -1 ,nullptr }, // Inst #1186 = MTCTRloop | |
| { 1187, 2, 0, 4, 306, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1187 = MTDCR | |
| { 1188, 1, 0, 4, 101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList18, ImplicitList18, OperandInfo2, -1 ,nullptr }, // Inst #1188 = MTFSB0 | |
| { 1189, 1, 0, 4, 101, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList18, ImplicitList18, OperandInfo2, -1 ,nullptr }, // Inst #1189 = MTFSB1 | |
| { 1190, 4, 0, 4, 248, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #1190 = MTFSF | |
| { 1191, 3, 1, 4, 248, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1191 = MTFSFI | |
| { 1192, 3, 1, 4, 248, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1192 = MTFSFI_rec | |
| { 1193, 4, 0, 4, 248, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #1193 = MTFSF_rec | |
| { 1194, 2, 0, 4, 249, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList18, ImplicitList18, OperandInfo167, -1 ,nullptr }, // Inst #1194 = MTFSFb | |
| { 1195, 1, 0, 4, 226, 0, 0x9ULL, nullptr, ImplicitList15, OperandInfo153, -1 ,nullptr }, // Inst #1195 = MTLR | |
| { 1196, 1, 0, 4, 226, 0, 0x9ULL, nullptr, ImplicitList17, OperandInfo38, -1 ,nullptr }, // Inst #1196 = MTLR8 | |
| { 1197, 2, 0, 4, 233, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1197 = MTMSR | |
| { 1198, 2, 0, 4, 234, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1198 = MTMSRD | |
| { 1199, 2, 1, 4, 128, 0|(1ULL<<MCID::ExtraDefRegAllocReq), 0x21ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1199 = MTOCRF | |
| { 1200, 2, 1, 4, 128, 0|(1ULL<<MCID::ExtraDefRegAllocReq), 0x21ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1200 = MTOCRF8 | |
| { 1201, 2, 0, 4, 229, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1201 = MTPMR | |
| { 1202, 2, 0, 4, 235, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1202 = MTSPR | |
| { 1203, 2, 0, 4, 235, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1203 = MTSPR8 | |
| { 1204, 2, 0, 4, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1204 = MTSR | |
| { 1205, 2, 0, 4, 304, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #1205 = MTSRIN | |
| { 1206, 2, 1, 4, 113, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr }, // Inst #1206 = MTVRD | |
| { 1207, 1, 0, 4, 227, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xaULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1207 = MTVRSAVE | |
| { 1208, 2, 1, 4, 227, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xaULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1208 = MTVRSAVEv | |
| { 1209, 2, 1, 4, 113, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1209 = MTVRWA | |
| { 1210, 2, 1, 4, 113, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1210 = MTVRWZ | |
| { 1211, 1, 0, 4, 137, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #1211 = MTVSCR | |
| { 1212, 2, 1, 4, 113, 0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #1212 = MTVSRD | |
| { 1213, 3, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #1213 = MTVSRDD | |
| { 1214, 2, 1, 4, 113, 0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1214 = MTVSRWA | |
| { 1215, 2, 1, 4, 163, 0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1215 = MTVSRWS | |
| { 1216, 2, 1, 4, 113, 0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1216 = MTVSRWZ | |
| { 1217, 3, 1, 4, 145, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1217 = MULHD | |
| { 1218, 3, 1, 4, 146, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1218 = MULHDU | |
| { 1219, 3, 1, 4, 153, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #1219 = MULHDU_rec | |
| { 1220, 3, 1, 4, 154, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #1220 = MULHD_rec | |
| { 1221, 3, 1, 4, 145, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1221 = MULHW | |
| { 1222, 3, 1, 4, 146, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1222 = MULHWU | |
| { 1223, 3, 1, 4, 153, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList4, OperandInfo55, -1 ,nullptr }, // Inst #1223 = MULHWU_rec | |
| { 1224, 3, 1, 4, 154, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList4, OperandInfo55, -1 ,nullptr }, // Inst #1224 = MULHW_rec | |
| { 1225, 3, 1, 4, 144, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1225 = MULLD | |
| { 1226, 3, 1, 4, 144, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList2, OperandInfo56, -1 ,nullptr }, // Inst #1226 = MULLDO | |
| { 1227, 3, 1, 4, 155, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo56, -1 ,nullptr }, // Inst #1227 = MULLDO_rec | |
| { 1228, 3, 1, 4, 155, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #1228 = MULLD_rec | |
| { 1229, 3, 1, 4, 147, 0, 0x8ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #1229 = MULLI | |
| { 1230, 3, 1, 4, 147, 0, 0x8ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1230 = MULLI8 | |
| { 1231, 3, 1, 4, 145, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1231 = MULLW | |
| { 1232, 3, 1, 4, 145, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList2, OperandInfo55, -1 ,nullptr }, // Inst #1232 = MULLWO | |
| { 1233, 3, 1, 4, 154, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList3, OperandInfo55, -1 ,nullptr }, // Inst #1233 = MULLWO_rec | |
| { 1234, 3, 1, 4, 154, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList4, OperandInfo55, -1 ,nullptr }, // Inst #1234 = MULLW_rec | |
| { 1235, 0, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, ImplicitList15, nullptr, -1 ,nullptr }, // Inst #1235 = MoveGOTtoLR | |
| { 1236, 0, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, ImplicitList15, nullptr, -1 ,nullptr }, // Inst #1236 = MovePCtoLR | |
| { 1237, 0, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, ImplicitList17, nullptr, -1 ,nullptr }, // Inst #1237 = MovePCtoLR8 | |
| { 1238, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1238 = NAND | |
| { 1239, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1239 = NAND8 | |
| { 1240, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #1240 = NAND8_rec | |
| { 1241, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList4, OperandInfo55, -1 ,nullptr }, // Inst #1241 = NAND_rec | |
| { 1242, 0, 0, 4, 296, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1242 = NAP | |
| { 1243, 2, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #1243 = NEG | |
| { 1244, 2, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #1244 = NEG8 | |
| { 1245, 2, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList2, OperandInfo61, -1 ,nullptr }, // Inst #1245 = NEG8O | |
| { 1246, 2, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo61, -1 ,nullptr }, // Inst #1246 = NEG8O_rec | |
| { 1247, 2, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo61, -1 ,nullptr }, // Inst #1247 = NEG8_rec | |
| { 1248, 2, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #1248 = NEGO | |
| { 1249, 2, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo43, -1 ,nullptr }, // Inst #1249 = NEGO_rec | |
| { 1250, 2, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo43, -1 ,nullptr }, // Inst #1250 = NEG_rec | |
| { 1251, 0, 0, 4, 116, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1251 = NOP | |
| { 1252, 0, 0, 4, 307, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1252 = NOP_GT_PWR6 | |
| { 1253, 0, 0, 4, 307, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1253 = NOP_GT_PWR7 | |
| { 1254, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1254 = NOR | |
| { 1255, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1255 = NOR8 | |
| { 1256, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #1256 = NOR8_rec | |
| { 1257, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList4, OperandInfo55, -1 ,nullptr }, // Inst #1257 = NOR_rec | |
| { 1258, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1258 = OR | |
| { 1259, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1259 = OR8 | |
| { 1260, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #1260 = OR8_rec | |
| { 1261, 3, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1261 = ORC | |
| { 1262, 3, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1262 = ORC8 | |
| { 1263, 3, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #1263 = ORC8_rec | |
| { 1264, 3, 1, 4, 116, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo55, -1 ,nullptr }, // Inst #1264 = ORC_rec | |
| { 1265, 3, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #1265 = ORI | |
| { 1266, 3, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1266 = ORI8 | |
| { 1267, 3, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #1267 = ORIS | |
| { 1268, 3, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1268 = ORIS8 | |
| { 1269, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList4, OperandInfo55, -1 ,nullptr }, // Inst #1269 = OR_rec | |
| { 1270, 2, 1, 4, 115, 0, 0x8ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #1270 = POPCNTB | |
| { 1271, 2, 1, 4, 110, 0, 0x8ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #1271 = POPCNTD | |
| { 1272, 2, 1, 4, 110, 0, 0x8ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #1272 = POPCNTW | |
| { 1273, 1, 1, 4, 0, 0, 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1273 = PPC32GOT | |
| { 1274, 2, 2, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #1274 = PPC32PICGOT | |
| { 1275, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1275 = QVALIGNI | |
| { 1276, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #1276 = QVALIGNIb | |
| { 1277, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #1277 = QVALIGNIs | |
| { 1278, 3, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo179, -1 ,nullptr }, // Inst #1278 = QVESPLATI | |
| { 1279, 3, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1279 = QVESPLATIb | |
| { 1280, 3, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1280 = QVESPLATIs | |
| { 1281, 2, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1281 = QVFABS | |
| { 1282, 2, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1282 = QVFABSs | |
| { 1283, 3, 1, 4, 21, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1283 = QVFADD | |
| { 1284, 3, 1, 4, 21, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1284 = QVFADDS | |
| { 1285, 3, 1, 4, 21, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1285 = QVFADDSs | |
| { 1286, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1286 = QVFCFID | |
| { 1287, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1287 = QVFCFIDS | |
| { 1288, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1288 = QVFCFIDU | |
| { 1289, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1289 = QVFCFIDUS | |
| { 1290, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1290 = QVFCFIDb | |
| { 1291, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1291 = QVFCMPEQ | |
| { 1292, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1292 = QVFCMPEQb | |
| { 1293, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #1293 = QVFCMPEQbs | |
| { 1294, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1294 = QVFCMPGT | |
| { 1295, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1295 = QVFCMPGTb | |
| { 1296, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #1296 = QVFCMPGTbs | |
| { 1297, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1297 = QVFCMPLT | |
| { 1298, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1298 = QVFCMPLTb | |
| { 1299, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #1299 = QVFCMPLTbs | |
| { 1300, 3, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1300 = QVFCPSGN | |
| { 1301, 3, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1301 = QVFCPSGNs | |
| { 1302, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1302 = QVFCTID | |
| { 1303, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1303 = QVFCTIDU | |
| { 1304, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1304 = QVFCTIDUZ | |
| { 1305, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1305 = QVFCTIDZ | |
| { 1306, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1306 = QVFCTIDb | |
| { 1307, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1307 = QVFCTIW | |
| { 1308, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1308 = QVFCTIWU | |
| { 1309, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1309 = QVFCTIWUZ | |
| { 1310, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1310 = QVFCTIWZ | |
| { 1311, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1311 = QVFLOGICAL | |
| { 1312, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #1312 = QVFLOGICALb | |
| { 1313, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #1313 = QVFLOGICALs | |
| { 1314, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1314 = QVFMADD | |
| { 1315, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1315 = QVFMADDS | |
| { 1316, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1316 = QVFMADDSs | |
| { 1317, 2, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1317 = QVFMR | |
| { 1318, 2, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1318 = QVFMRb | |
| { 1319, 2, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1319 = QVFMRs | |
| { 1320, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1320 = QVFMSUB | |
| { 1321, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1321 = QVFMSUBS | |
| { 1322, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1322 = QVFMSUBSs | |
| { 1323, 3, 1, 4, 21, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1323 = QVFMUL | |
| { 1324, 3, 1, 4, 21, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1324 = QVFMULS | |
| { 1325, 3, 1, 4, 21, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1325 = QVFMULSs | |
| { 1326, 2, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1326 = QVFNABS | |
| { 1327, 2, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1327 = QVFNABSs | |
| { 1328, 2, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1328 = QVFNEG | |
| { 1329, 2, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1329 = QVFNEGs | |
| { 1330, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1330 = QVFNMADD | |
| { 1331, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1331 = QVFNMADDS | |
| { 1332, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1332 = QVFNMADDSs | |
| { 1333, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1333 = QVFNMSUB | |
| { 1334, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1334 = QVFNMSUBS | |
| { 1335, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1335 = QVFNMSUBSs | |
| { 1336, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1336 = QVFPERM | |
| { 1337, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1337 = QVFPERMs | |
| { 1338, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1338 = QVFRE | |
| { 1339, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1339 = QVFRES | |
| { 1340, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1340 = QVFRESs | |
| { 1341, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1341 = QVFRIM | |
| { 1342, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1342 = QVFRIMs | |
| { 1343, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1343 = QVFRIN | |
| { 1344, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1344 = QVFRINs | |
| { 1345, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1345 = QVFRIP | |
| { 1346, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1346 = QVFRIPs | |
| { 1347, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1347 = QVFRIZ | |
| { 1348, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1348 = QVFRIZs | |
| { 1349, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1349 = QVFRSP | |
| { 1350, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1350 = QVFRSPs | |
| { 1351, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1351 = QVFRSQRTE | |
| { 1352, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1352 = QVFRSQRTES | |
| { 1353, 2, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1353 = QVFRSQRTESs | |
| { 1354, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1354 = QVFSEL | |
| { 1355, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1355 = QVFSELb | |
| { 1356, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1356 = QVFSELbb | |
| { 1357, 4, 1, 4, 68, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1357 = QVFSELbs | |
| { 1358, 3, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1358 = QVFSUB | |
| { 1359, 3, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1359 = QVFSUBS | |
| { 1360, 3, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1360 = QVFSUBSs | |
| { 1361, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1361 = QVFTSTNAN | |
| { 1362, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1362 = QVFTSTNANb | |
| { 1363, 3, 1, 4, 20, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #1363 = QVFTSTNANbs | |
| { 1364, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1364 = QVFXMADD | |
| { 1365, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1365 = QVFXMADDS | |
| { 1366, 3, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1366 = QVFXMUL | |
| { 1367, 3, 1, 4, 21, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1367 = QVFXMULS | |
| { 1368, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1368 = QVFXXCPNMADD | |
| { 1369, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1369 = QVFXXCPNMADDS | |
| { 1370, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1370 = QVFXXMADD | |
| { 1371, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1371 = QVFXXMADDS | |
| { 1372, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1372 = QVFXXNPMADD | |
| { 1373, 4, 1, 4, 27, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1373 = QVFXXNPMADDS | |
| { 1374, 2, 1, 4, 68, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, ImplicitList18, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1374 = QVGPCI | |
| { 1375, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1375 = QVLFCDUX | |
| { 1376, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1376 = QVLFCDUXA | |
| { 1377, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1377 = QVLFCDX | |
| { 1378, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1378 = QVLFCDXA | |
| { 1379, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1379 = QVLFCSUX | |
| { 1380, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1380 = QVLFCSUXA | |
| { 1381, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1381 = QVLFCSX | |
| { 1382, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1382 = QVLFCSXA | |
| { 1383, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList18, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #1383 = QVLFCSXs | |
| { 1384, 4, 2, 4, 40, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList18, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1384 = QVLFDUX | |
| { 1385, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1385 = QVLFDUXA | |
| { 1386, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x80ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1386 = QVLFDX | |
| { 1387, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1387 = QVLFDXA | |
| { 1388, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x80ULL, ImplicitList18, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1388 = QVLFDXb | |
| { 1389, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1389 = QVLFIWAX | |
| { 1390, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1390 = QVLFIWAXA | |
| { 1391, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1391 = QVLFIWZX | |
| { 1392, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1392 = QVLFIWZXA | |
| { 1393, 4, 2, 4, 40, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList18, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1393 = QVLFSUX | |
| { 1394, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1394 = QVLFSUXA | |
| { 1395, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x80ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1395 = QVLFSX | |
| { 1396, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1396 = QVLFSXA | |
| { 1397, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList18, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1397 = QVLFSXb | |
| { 1398, 3, 1, 4, 39, 0|(1ULL<<MCID::MayLoad), 0x80ULL, ImplicitList18, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #1398 = QVLFSXs | |
| { 1399, 3, 1, 4, 39, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1399 = QVLPCLDX | |
| { 1400, 3, 1, 4, 39, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1400 = QVLPCLSX | |
| { 1401, 2, 1, 4, 39, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1401 = QVLPCLSXint | |
| { 1402, 3, 1, 4, 39, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1402 = QVLPCRDX | |
| { 1403, 3, 1, 4, 39, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1403 = QVLPCRSX | |
| { 1404, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1404 = QVSTFCDUX | |
| { 1405, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1405 = QVSTFCDUXA | |
| { 1406, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1406 = QVSTFCDUXI | |
| { 1407, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1407 = QVSTFCDUXIA | |
| { 1408, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1408 = QVSTFCDX | |
| { 1409, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1409 = QVSTFCDXA | |
| { 1410, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1410 = QVSTFCDXI | |
| { 1411, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1411 = QVSTFCDXIA | |
| { 1412, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1412 = QVSTFCSUX | |
| { 1413, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1413 = QVSTFCSUXA | |
| { 1414, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1414 = QVSTFCSUXI | |
| { 1415, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1415 = QVSTFCSUXIA | |
| { 1416, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1416 = QVSTFCSX | |
| { 1417, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1417 = QVSTFCSXA | |
| { 1418, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1418 = QVSTFCSXI | |
| { 1419, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1419 = QVSTFCSXIA | |
| { 1420, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #1420 = QVSTFCSXs | |
| { 1421, 4, 1, 4, 70, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1421 = QVSTFDUX | |
| { 1422, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1422 = QVSTFDUXA | |
| { 1423, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1423 = QVSTFDUXI | |
| { 1424, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1424 = QVSTFDUXIA | |
| { 1425, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x80ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1425 = QVSTFDX | |
| { 1426, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1426 = QVSTFDXA | |
| { 1427, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1427 = QVSTFDXI | |
| { 1428, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1428 = QVSTFDXIA | |
| { 1429, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x80ULL, ImplicitList18, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1429 = QVSTFDXb | |
| { 1430, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1430 = QVSTFIWX | |
| { 1431, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1431 = QVSTFIWXA | |
| { 1432, 4, 1, 4, 70, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1432 = QVSTFSUX | |
| { 1433, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1433 = QVSTFSUXA | |
| { 1434, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1434 = QVSTFSUXI | |
| { 1435, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1435 = QVSTFSUXIA | |
| { 1436, 4, 1, 4, 70, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1436 = QVSTFSUXs | |
| { 1437, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x80ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1437 = QVSTFSX | |
| { 1438, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1438 = QVSTFSXA | |
| { 1439, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1439 = QVSTFSXI | |
| { 1440, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList18, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1440 = QVSTFSXIA | |
| { 1441, 3, 0, 4, 69, 0|(1ULL<<MCID::MayStore), 0x80ULL, ImplicitList18, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #1441 = QVSTFSXs | |
| { 1442, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1442 = RESTORE_CR | |
| { 1443, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1443 = RESTORE_CRBIT | |
| { 1444, 3, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1444 = RESTORE_VRSAVE | |
| { 1445, 0, 0, 4, 296, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1445 = RFCI | |
| { 1446, 0, 0, 4, 296, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1446 = RFDI | |
| { 1447, 1, 0, 4, 121, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1447 = RFEBB | |
| { 1448, 0, 0, 4, 297, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1448 = RFI | |
| { 1449, 0, 0, 4, 298, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1449 = RFID | |
| { 1450, 0, 0, 4, 296, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1450 = RFMCI | |
| { 1451, 4, 1, 4, 124, 0, 0x8ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1451 = RLDCL | |
| { 1452, 4, 1, 4, 250, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo208, -1 ,nullptr }, // Inst #1452 = RLDCL_rec | |
| { 1453, 4, 1, 4, 124, 0, 0x8ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1453 = RLDCR | |
| { 1454, 4, 1, 4, 250, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo208, -1 ,nullptr }, // Inst #1454 = RLDCR_rec | |
| { 1455, 4, 1, 4, 112, 0, 0x8ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1455 = RLDIC | |
| { 1456, 4, 1, 4, 126, 0, 0x8ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1456 = RLDICL | |
| { 1457, 4, 1, 4, 126, 0, 0x8ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1457 = RLDICL_32 | |
| { 1458, 4, 1, 4, 126, 0, 0x8ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1458 = RLDICL_32_64 | |
| { 1459, 4, 1, 4, 251, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo40, -1 ,nullptr }, // Inst #1459 = RLDICL_32_rec | |
| { 1460, 4, 1, 4, 251, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo39, -1 ,nullptr }, // Inst #1460 = RLDICL_rec | |
| { 1461, 4, 1, 4, 126, 0, 0x8ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1461 = RLDICR | |
| { 1462, 4, 1, 4, 126, 0, 0x8ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1462 = RLDICR_32 | |
| { 1463, 4, 1, 4, 251, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo39, -1 ,nullptr }, // Inst #1463 = RLDICR_rec | |
| { 1464, 4, 1, 4, 257, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo39, -1 ,nullptr }, // Inst #1464 = RLDIC_rec | |
| { 1465, 5, 1, 4, 126, 0, 0x8ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1465 = RLDIMI | |
| { 1466, 5, 1, 4, 251, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo210, -1 ,nullptr }, // Inst #1466 = RLDIMI_rec | |
| { 1467, 6, 1, 4, 125, 0|(1ULL<<MCID::Commutable), 0xcULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1467 = RLWIMI | |
| { 1468, 6, 1, 4, 125, 0, 0xcULL, nullptr, nullptr, OperandInfo212, -1 ,nullptr }, // Inst #1468 = RLWIMI8 | |
| { 1469, 6, 1, 4, 252, 0, 0xcULL, nullptr, ImplicitList4, OperandInfo212, -1 ,nullptr }, // Inst #1469 = RLWIMI8_rec | |
| { 1470, 6, 1, 4, 252, 0|(1ULL<<MCID::Commutable), 0xcULL, nullptr, ImplicitList4, OperandInfo211, -1 ,nullptr }, // Inst #1470 = RLWIMI_rec | |
| { 1471, 5, 1, 4, 130, 0, 0x8ULL, nullptr, nullptr, OperandInfo213, -1 ,nullptr }, // Inst #1471 = RLWINM | |
| { 1472, 5, 1, 4, 130, 0, 0x8ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr }, // Inst #1472 = RLWINM8 | |
| { 1473, 5, 1, 4, 253, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo214, -1 ,nullptr }, // Inst #1473 = RLWINM8_rec | |
| { 1474, 5, 1, 4, 253, 0, 0xcULL, nullptr, ImplicitList4, OperandInfo213, -1 ,nullptr }, // Inst #1474 = RLWINM_rec | |
| { 1475, 5, 1, 4, 130, 0, 0x8ULL, nullptr, nullptr, OperandInfo215, -1 ,nullptr }, // Inst #1475 = RLWNM | |
| { 1476, 5, 1, 4, 130, 0, 0x8ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1476 = RLWNM8 | |
| { 1477, 5, 1, 4, 253, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo216, -1 ,nullptr }, // Inst #1477 = RLWNM8_rec | |
| { 1478, 5, 1, 4, 253, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo215, -1 ,nullptr }, // Inst #1478 = RLWNM_rec | |
| { 1479, 2, 2, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #1479 = ReadTB | |
| { 1480, 1, 0, 4, 296, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #1480 = SC | |
| { 1481, 5, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1481 = SELECT_CC_F16 | |
| { 1482, 5, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1482 = SELECT_CC_F4 | |
| { 1483, 5, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1483 = SELECT_CC_F8 | |
| { 1484, 5, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1484 = SELECT_CC_I4 | |
| { 1485, 5, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1485 = SELECT_CC_I8 | |
| { 1486, 5, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList18, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1486 = SELECT_CC_QBRC | |
| { 1487, 5, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList18, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1487 = SELECT_CC_QFRC | |
| { 1488, 5, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList18, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1488 = SELECT_CC_QSRC | |
| { 1489, 5, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1489 = SELECT_CC_SPE | |
| { 1490, 5, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1490 = SELECT_CC_SPE4 | |
| { 1491, 5, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1491 = SELECT_CC_VRRC | |
| { 1492, 5, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1492 = SELECT_CC_VSFRC | |
| { 1493, 5, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1493 = SELECT_CC_VSRC | |
| { 1494, 5, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1494 = SELECT_CC_VSSRC | |
| { 1495, 4, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1495 = SELECT_F16 | |
| { 1496, 4, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1496 = SELECT_F4 | |
| { 1497, 4, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1497 = SELECT_F8 | |
| { 1498, 4, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1498 = SELECT_I4 | |
| { 1499, 4, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, nullptr, OperandInfo232, -1 ,nullptr }, // Inst #1499 = SELECT_I8 | |
| { 1500, 4, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList18, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1500 = SELECT_QBRC | |
| { 1501, 4, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList18, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #1501 = SELECT_QFRC | |
| { 1502, 4, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList18, nullptr, OperandInfo235, -1 ,nullptr }, // Inst #1502 = SELECT_QSRC | |
| { 1503, 4, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr }, // Inst #1503 = SELECT_SPE | |
| { 1504, 4, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr }, // Inst #1504 = SELECT_SPE4 | |
| { 1505, 4, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1505 = SELECT_VRRC | |
| { 1506, 4, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1506 = SELECT_VSFRC | |
| { 1507, 4, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1507 = SELECT_VSRC | |
| { 1508, 4, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1508 = SELECT_VSSRC | |
| { 1509, 2, 1, 4, 110, 0, 0x8ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #1509 = SETB | |
| { 1510, 2, 1, 4, 110, 0, 0x8ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1510 = SETB8 | |
| { 1511, 2, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList18, ImplicitList18, OperandInfo241, -1 ,nullptr }, // Inst #1511 = SETRND | |
| { 1512, 2, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList18, ImplicitList18, OperandInfo156, -1 ,nullptr }, // Inst #1512 = SETRNDi | |
| { 1513, 2, 1, 4, 312, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo43, -1 ,nullptr }, // Inst #1513 = SLBFEE_rec | |
| { 1514, 0, 0, 4, 190, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1514 = SLBIA | |
| { 1515, 1, 0, 4, 191, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1515 = SLBIE | |
| { 1516, 2, 0, 4, 220, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #1516 = SLBIEG | |
| { 1517, 2, 1, 4, 192, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #1517 = SLBMFEE | |
| { 1518, 2, 1, 4, 193, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #1518 = SLBMFEV | |
| { 1519, 2, 0, 4, 194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #1519 = SLBMTE | |
| { 1520, 0, 0, 4, 311, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1520 = SLBSYNC | |
| { 1521, 3, 1, 4, 111, 0, 0x8ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #1521 = SLD | |
| { 1522, 3, 1, 4, 258, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo242, -1 ,nullptr }, // Inst #1522 = SLD_rec | |
| { 1523, 3, 1, 4, 130, 0, 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1523 = SLW | |
| { 1524, 3, 1, 4, 130, 0, 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1524 = SLW8 | |
| { 1525, 3, 1, 4, 253, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #1525 = SLW8_rec | |
| { 1526, 3, 1, 4, 253, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo55, -1 ,nullptr }, // Inst #1526 = SLW_rec | |
| { 1527, 3, 1, 4, 13, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #1527 = SPELWZ | |
| { 1528, 3, 1, 4, 13, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1528 = SPELWZX | |
| { 1529, 3, 0, 4, 24, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #1529 = SPESTW | |
| { 1530, 3, 0, 4, 24, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1530 = SPESTWX | |
| { 1531, 3, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1531 = SPILL_CR | |
| { 1532, 3, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1532 = SPILL_CRBIT | |
| { 1533, 3, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1533 = SPILL_VRSAVE | |
| { 1534, 3, 1, 4, 111, 0, 0x8ULL, nullptr, ImplicitList5, OperandInfo242, -1 ,nullptr }, // Inst #1534 = SRAD | |
| { 1535, 3, 1, 4, 112, 0, 0x8ULL, nullptr, ImplicitList5, OperandInfo41, -1 ,nullptr }, // Inst #1535 = SRADI | |
| { 1536, 3, 1, 4, 112, 0, 0x8ULL, nullptr, ImplicitList5, OperandInfo42, -1 ,nullptr }, // Inst #1536 = SRADI_32 | |
| { 1537, 3, 1, 4, 257, 0, 0x8ULL, nullptr, ImplicitList8, OperandInfo41, -1 ,nullptr }, // Inst #1537 = SRADI_rec | |
| { 1538, 3, 1, 4, 258, 0, 0x8ULL, nullptr, ImplicitList8, OperandInfo242, -1 ,nullptr }, // Inst #1538 = SRAD_rec | |
| { 1539, 3, 1, 4, 132, 0, 0x8ULL, nullptr, ImplicitList5, OperandInfo55, -1 ,nullptr }, // Inst #1539 = SRAW | |
| { 1540, 3, 1, 4, 132, 0, 0x8ULL, nullptr, ImplicitList5, OperandInfo42, -1 ,nullptr }, // Inst #1540 = SRAWI | |
| { 1541, 3, 1, 4, 254, 0, 0x8ULL, nullptr, ImplicitList8, OperandInfo42, -1 ,nullptr }, // Inst #1541 = SRAWI_rec | |
| { 1542, 3, 1, 4, 254, 0, 0x8ULL, nullptr, ImplicitList8, OperandInfo55, -1 ,nullptr }, // Inst #1542 = SRAW_rec | |
| { 1543, 3, 1, 4, 111, 0, 0x8ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #1543 = SRD | |
| { 1544, 3, 1, 4, 258, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo242, -1 ,nullptr }, // Inst #1544 = SRD_rec | |
| { 1545, 3, 1, 4, 130, 0, 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1545 = SRW | |
| { 1546, 3, 1, 4, 130, 0, 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1546 = SRW8 | |
| { 1547, 3, 1, 4, 253, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #1547 = SRW8_rec | |
| { 1548, 3, 1, 4, 253, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo55, -1 ,nullptr }, // Inst #1548 = SRW_rec | |
| { 1549, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #1549 = STB | |
| { 1550, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1550 = STB8 | |
| { 1551, 3, 0, 4, 219, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1551 = STBCIX | |
| { 1552, 3, 0, 4, 199, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, ImplicitList4, OperandInfo121, -1 ,nullptr }, // Inst #1552 = STBCX | |
| { 1553, 3, 0, 4, 300, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1553 = STBEPX | |
| { 1554, 4, 1, 4, 278, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #1554 = STBU | |
| { 1555, 4, 1, 4, 278, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #1555 = STBU8 | |
| { 1556, 4, 1, 4, 279, 0|(1ULL<<MCID::MayStore), 0x94ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #1556 = STBUX | |
| { 1557, 4, 1, 4, 279, 0|(1ULL<<MCID::MayStore), 0x94ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #1557 = STBUX8 | |
| { 1558, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0x94ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1558 = STBX | |
| { 1559, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0x94ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #1559 = STBX8 | |
| { 1560, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1560 = STBXTLS | |
| { 1561, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1561 = STBXTLS_ | |
| { 1562, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #1562 = STBXTLS_32 | |
| { 1563, 3, 0, 4, 218, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1563 = STD | |
| { 1564, 3, 0, 4, 290, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1564 = STDAT | |
| { 1565, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0x94ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #1565 = STDBRX | |
| { 1566, 3, 0, 4, 219, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1566 = STDCIX | |
| { 1567, 3, 0, 4, 200, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, ImplicitList4, OperandInfo127, -1 ,nullptr }, // Inst #1567 = STDCX | |
| { 1568, 4, 1, 4, 278, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #1568 = STDU | |
| { 1569, 4, 1, 4, 279, 0|(1ULL<<MCID::MayStore), 0x94ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #1569 = STDUX | |
| { 1570, 3, 0, 4, 218, 0|(1ULL<<MCID::MayStore), 0x94ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #1570 = STDX | |
| { 1571, 3, 0, 4, 218, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1571 = STDXTLS | |
| { 1572, 3, 0, 4, 218, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1572 = STDXTLS_ | |
| { 1573, 3, 0, 4, 215, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1573 = STFD | |
| { 1574, 3, 0, 4, 302, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1574 = STFDEPX | |
| { 1575, 4, 1, 4, 277, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #1575 = STFDU | |
| { 1576, 4, 1, 4, 277, 0|(1ULL<<MCID::MayStore), 0x94ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #1576 = STFDUX | |
| { 1577, 3, 0, 4, 215, 0|(1ULL<<MCID::MayStore), 0x90ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1577 = STFDX | |
| { 1578, 3, 0, 4, 215, 0|(1ULL<<MCID::MayStore), 0x90ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1578 = STFIWX | |
| { 1579, 3, 0, 4, 215, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1579 = STFS | |
| { 1580, 4, 1, 4, 277, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #1580 = STFSU | |
| { 1581, 4, 1, 4, 277, 0|(1ULL<<MCID::MayStore), 0x94ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #1581 = STFSUX | |
| { 1582, 3, 0, 4, 215, 0|(1ULL<<MCID::MayStore), 0x90ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #1582 = STFSX | |
| { 1583, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #1583 = STH | |
| { 1584, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1584 = STH8 | |
| { 1585, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0x94ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1585 = STHBRX | |
| { 1586, 3, 0, 4, 219, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1586 = STHCIX | |
| { 1587, 3, 0, 4, 199, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, ImplicitList4, OperandInfo121, -1 ,nullptr }, // Inst #1587 = STHCX | |
| { 1588, 3, 0, 4, 300, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1588 = STHEPX | |
| { 1589, 4, 1, 4, 278, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #1589 = STHU | |
| { 1590, 4, 1, 4, 278, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #1590 = STHU8 | |
| { 1591, 4, 1, 4, 279, 0|(1ULL<<MCID::MayStore), 0x94ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #1591 = STHUX | |
| { 1592, 4, 1, 4, 279, 0|(1ULL<<MCID::MayStore), 0x94ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #1592 = STHUX8 | |
| { 1593, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0x94ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1593 = STHX | |
| { 1594, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0x94ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #1594 = STHX8 | |
| { 1595, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1595 = STHXTLS | |
| { 1596, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1596 = STHXTLS_ | |
| { 1597, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #1597 = STHXTLS_32 | |
| { 1598, 3, 0, 4, 221, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #1598 = STMW | |
| { 1599, 0, 0, 4, 313, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1599 = STOP | |
| { 1600, 3, 0, 4, 219, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #1600 = STSWI | |
| { 1601, 3, 0, 4, 223, 0|(1ULL<<MCID::MayStore), 0x90ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1601 = STVEBX | |
| { 1602, 3, 0, 4, 223, 0|(1ULL<<MCID::MayStore), 0x90ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1602 = STVEHX | |
| { 1603, 3, 0, 4, 223, 0|(1ULL<<MCID::MayStore), 0x90ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1603 = STVEWX | |
| { 1604, 3, 0, 4, 223, 0|(1ULL<<MCID::MayStore), 0x90ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1604 = STVX | |
| { 1605, 3, 0, 4, 223, 0|(1ULL<<MCID::MayStore), 0x90ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1605 = STVXL | |
| { 1606, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #1606 = STW | |
| { 1607, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #1607 = STW8 | |
| { 1608, 3, 0, 4, 290, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #1608 = STWAT | |
| { 1609, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0x94ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1609 = STWBRX | |
| { 1610, 3, 0, 4, 219, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1610 = STWCIX | |
| { 1611, 3, 0, 4, 199, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, ImplicitList4, OperandInfo121, -1 ,nullptr }, // Inst #1611 = STWCX | |
| { 1612, 3, 0, 4, 300, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1612 = STWEPX | |
| { 1613, 4, 1, 4, 278, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #1613 = STWU | |
| { 1614, 4, 1, 4, 278, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #1614 = STWU8 | |
| { 1615, 4, 1, 4, 279, 0|(1ULL<<MCID::MayStore), 0x94ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #1615 = STWUX | |
| { 1616, 4, 1, 4, 279, 0|(1ULL<<MCID::MayStore), 0x94ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #1616 = STWUX8 | |
| { 1617, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0x94ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #1617 = STWX | |
| { 1618, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0x94ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #1618 = STWX8 | |
| { 1619, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1619 = STWXTLS | |
| { 1620, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1620 = STWXTLS_ | |
| { 1621, 3, 0, 4, 216, 0|(1ULL<<MCID::MayStore), 0xcULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #1621 = STWXTLS_32 | |
| { 1622, 3, 0, 4, 215, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #1622 = STXSD | |
| { 1623, 3, 0, 4, 215, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #1623 = STXSDX | |
| { 1624, 3, 0, 4, 215, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #1624 = STXSIBX | |
| { 1625, 3, 0, 4, 215, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #1625 = STXSIBXv | |
| { 1626, 3, 0, 4, 215, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #1626 = STXSIHX | |
| { 1627, 3, 0, 4, 215, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #1627 = STXSIHXv | |
| { 1628, 3, 0, 4, 215, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #1628 = STXSIWX | |
| { 1629, 3, 0, 4, 215, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #1629 = STXSSP | |
| { 1630, 3, 0, 4, 215, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #1630 = STXSSPX | |
| { 1631, 3, 0, 4, 224, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr }, // Inst #1631 = STXV | |
| { 1632, 3, 0, 4, 224, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #1632 = STXVB16X | |
| { 1633, 3, 0, 4, 224, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #1633 = STXVD2X | |
| { 1634, 3, 0, 4, 224, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #1634 = STXVH8X | |
| { 1635, 3, 0, 4, 225, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1635 = STXVL | |
| { 1636, 3, 0, 4, 225, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1636 = STXVLL | |
| { 1637, 3, 0, 4, 224, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #1637 = STXVW4X | |
| { 1638, 3, 0, 4, 224, 0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #1638 = STXVX | |
| { 1639, 3, 1, 4, 115, 0, 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1639 = SUBF | |
| { 1640, 3, 1, 4, 115, 0, 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1640 = SUBF8 | |
| { 1641, 3, 1, 4, 115, 0, 0x8ULL, nullptr, ImplicitList2, OperandInfo56, -1 ,nullptr }, // Inst #1641 = SUBF8O | |
| { 1642, 3, 1, 4, 115, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo56, -1 ,nullptr }, // Inst #1642 = SUBF8O_rec | |
| { 1643, 3, 1, 4, 115, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #1643 = SUBF8_rec | |
| { 1644, 3, 1, 4, 115, 0, 0xcULL, nullptr, ImplicitList5, OperandInfo55, -1 ,nullptr }, // Inst #1644 = SUBFC | |
| { 1645, 3, 1, 4, 115, 0, 0xcULL, nullptr, ImplicitList5, OperandInfo56, -1 ,nullptr }, // Inst #1645 = SUBFC8 | |
| { 1646, 3, 1, 4, 115, 0, 0xcULL, nullptr, ImplicitList6, OperandInfo56, -1 ,nullptr }, // Inst #1646 = SUBFC8O | |
| { 1647, 3, 1, 4, 245, 0, 0xcULL, nullptr, ImplicitList7, OperandInfo56, -1 ,nullptr }, // Inst #1647 = SUBFC8O_rec | |
| { 1648, 3, 1, 4, 245, 0, 0xcULL, nullptr, ImplicitList8, OperandInfo56, -1 ,nullptr }, // Inst #1648 = SUBFC8_rec | |
| { 1649, 3, 1, 4, 115, 0, 0xcULL, nullptr, ImplicitList6, OperandInfo55, -1 ,nullptr }, // Inst #1649 = SUBFCO | |
| { 1650, 3, 1, 4, 245, 0, 0xcULL, nullptr, ImplicitList7, OperandInfo55, -1 ,nullptr }, // Inst #1650 = SUBFCO_rec | |
| { 1651, 3, 1, 4, 245, 0, 0xcULL, nullptr, ImplicitList8, OperandInfo55, -1 ,nullptr }, // Inst #1651 = SUBFC_rec | |
| { 1652, 3, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList5, OperandInfo55, -1 ,nullptr }, // Inst #1652 = SUBFE | |
| { 1653, 3, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList5, OperandInfo56, -1 ,nullptr }, // Inst #1653 = SUBFE8 | |
| { 1654, 3, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList6, OperandInfo56, -1 ,nullptr }, // Inst #1654 = SUBFE8O | |
| { 1655, 3, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList7, OperandInfo56, -1 ,nullptr }, // Inst #1655 = SUBFE8O_rec | |
| { 1656, 3, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList8, OperandInfo56, -1 ,nullptr }, // Inst #1656 = SUBFE8_rec | |
| { 1657, 3, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList6, OperandInfo55, -1 ,nullptr }, // Inst #1657 = SUBFEO | |
| { 1658, 3, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList7, OperandInfo55, -1 ,nullptr }, // Inst #1658 = SUBFEO_rec | |
| { 1659, 3, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList8, OperandInfo55, -1 ,nullptr }, // Inst #1659 = SUBFE_rec | |
| { 1660, 3, 1, 4, 115, 0, 0x8ULL, nullptr, ImplicitList5, OperandInfo42, -1 ,nullptr }, // Inst #1660 = SUBFIC | |
| { 1661, 3, 1, 4, 115, 0, 0x8ULL, nullptr, ImplicitList5, OperandInfo41, -1 ,nullptr }, // Inst #1661 = SUBFIC8 | |
| { 1662, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList5, OperandInfo43, -1 ,nullptr }, // Inst #1662 = SUBFME | |
| { 1663, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList5, OperandInfo61, -1 ,nullptr }, // Inst #1663 = SUBFME8 | |
| { 1664, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList6, OperandInfo61, -1 ,nullptr }, // Inst #1664 = SUBFME8O | |
| { 1665, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList7, OperandInfo61, -1 ,nullptr }, // Inst #1665 = SUBFME8O_rec | |
| { 1666, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList8, OperandInfo61, -1 ,nullptr }, // Inst #1666 = SUBFME8_rec | |
| { 1667, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList6, OperandInfo43, -1 ,nullptr }, // Inst #1667 = SUBFMEO | |
| { 1668, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList7, OperandInfo43, -1 ,nullptr }, // Inst #1668 = SUBFMEO_rec | |
| { 1669, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList8, OperandInfo43, -1 ,nullptr }, // Inst #1669 = SUBFME_rec | |
| { 1670, 3, 1, 4, 115, 0, 0x8ULL, nullptr, ImplicitList2, OperandInfo55, -1 ,nullptr }, // Inst #1670 = SUBFO | |
| { 1671, 3, 1, 4, 115, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo55, -1 ,nullptr }, // Inst #1671 = SUBFO_rec | |
| { 1672, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList5, OperandInfo43, -1 ,nullptr }, // Inst #1672 = SUBFZE | |
| { 1673, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList5, OperandInfo61, -1 ,nullptr }, // Inst #1673 = SUBFZE8 | |
| { 1674, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList6, OperandInfo61, -1 ,nullptr }, // Inst #1674 = SUBFZE8O | |
| { 1675, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList7, OperandInfo61, -1 ,nullptr }, // Inst #1675 = SUBFZE8O_rec | |
| { 1676, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList8, OperandInfo61, -1 ,nullptr }, // Inst #1676 = SUBFZE8_rec | |
| { 1677, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList6, OperandInfo43, -1 ,nullptr }, // Inst #1677 = SUBFZEO | |
| { 1678, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList7, OperandInfo43, -1 ,nullptr }, // Inst #1678 = SUBFZEO_rec | |
| { 1679, 2, 1, 4, 115, 0, 0x8ULL, ImplicitList5, ImplicitList8, OperandInfo43, -1 ,nullptr }, // Inst #1679 = SUBFZE_rec | |
| { 1680, 3, 1, 4, 115, 0, 0x8ULL, nullptr, ImplicitList4, OperandInfo55, -1 ,nullptr }, // Inst #1680 = SUBF_rec | |
| { 1681, 1, 0, 4, 187, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #1681 = SYNC | |
| { 1682, 1, 0, 4, 135, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo153, -1 ,nullptr }, // Inst #1682 = TABORT | |
| { 1683, 3, 0, 4, 100, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo87, -1 ,nullptr }, // Inst #1683 = TABORTDC | |
| { 1684, 3, 0, 4, 100, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo251, -1 ,nullptr }, // Inst #1684 = TABORTDCI | |
| { 1685, 3, 0, 4, 100, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo87, -1 ,nullptr }, // Inst #1685 = TABORTWC | |
| { 1686, 3, 0, 4, 100, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo251, -1 ,nullptr }, // Inst #1686 = TABORTWCI | |
| { 1687, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #1687 = TAILB | |
| { 1688, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #1688 = TAILB8 | |
| { 1689, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1689 = TAILBA | |
| { 1690, 1, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList18, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1690 = TAILBA8 | |
| { 1691, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, nullptr, nullptr, -1 ,nullptr }, // Inst #1691 = TAILBCTR | |
| { 1692, 0, 0, 4, 287, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList16, nullptr, nullptr, -1 ,nullptr }, // Inst #1692 = TAILBCTR8 | |
| { 1693, 1, 0, 4, 122, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo2, -1 ,nullptr }, // Inst #1693 = TBEGIN | |
| { 1694, 2, 1, 4, 0, 0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1694 = TBEGIN_RET | |
| { 1695, 1, 1, 4, 205, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1695 = TCHECK | |
| { 1696, 1, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1696 = TCHECK_RET | |
| { 1697, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList18, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #1697 = TCRETURNai | |
| { 1698, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList18, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #1698 = TCRETURNai8 | |
| { 1699, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList18, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #1699 = TCRETURNdi | |
| { 1700, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList18, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #1700 = TCRETURNdi8 | |
| { 1701, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList18, nullptr, OperandInfo254, -1 ,nullptr }, // Inst #1701 = TCRETURNri | |
| { 1702, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList18, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #1702 = TCRETURNri8 | |
| { 1703, 3, 0, 4, 104, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #1703 = TD | |
| { 1704, 3, 0, 4, 104, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1704 = TDI | |
| { 1705, 1, 0, 4, 198, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo2, -1 ,nullptr }, // Inst #1705 = TEND | |
| { 1706, 0, 0, 4, 308, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1706 = TLBIA | |
| { 1707, 2, 0, 4, 222, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #1707 = TLBIE | |
| { 1708, 1, 0, 4, 195, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1708 = TLBIEL | |
| { 1709, 2, 0, 4, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #1709 = TLBIVAX | |
| { 1710, 1, 0, 4, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1710 = TLBLD | |
| { 1711, 1, 0, 4, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1711 = TLBLI | |
| { 1712, 0, 0, 4, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1712 = TLBRE | |
| { 1713, 3, 1, 4, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #1713 = TLBRE2 | |
| { 1714, 2, 0, 4, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #1714 = TLBSX | |
| { 1715, 3, 0, 4, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1715 = TLBSX2 | |
| { 1716, 3, 0, 4, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1716 = TLBSX2D | |
| { 1717, 0, 0, 4, 186, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1717 = TLBSYNC | |
| { 1718, 0, 0, 4, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1718 = TLBWE | |
| { 1719, 3, 0, 4, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #1719 = TLBWE2 | |
| { 1720, 0, 0, 4, 299, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1720 = TRAP | |
| { 1721, 0, 0, 4, 122, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, nullptr, -1 ,nullptr }, // Inst #1721 = TRECHKPT | |
| { 1722, 1, 0, 4, 135, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo153, -1 ,nullptr }, // Inst #1722 = TRECLAIM | |
| { 1723, 1, 0, 4, 135, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo2, -1 ,nullptr }, // Inst #1723 = TSR | |
| { 1724, 3, 0, 4, 105, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1724 = TW | |
| { 1725, 3, 0, 4, 105, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #1725 = TWI | |
| { 1726, 0, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1726 = UNENCODED_NOP | |
| { 1727, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #1727 = UPDATE_VRSAVE | |
| { 1728, 3, 2, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #1728 = UpdateGBR | |
| { 1729, 3, 1, 4, 139, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1729 = VABSDUB | |
| { 1730, 3, 1, 4, 139, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1730 = VABSDUH | |
| { 1731, 3, 1, 4, 139, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1731 = VABSDUW | |
| { 1732, 3, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1732 = VADDCUQ | |
| { 1733, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1733 = VADDCUW | |
| { 1734, 4, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1734 = VADDECUQ | |
| { 1735, 4, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1735 = VADDEUQM | |
| { 1736, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1736 = VADDFP | |
| { 1737, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1737 = VADDSBS | |
| { 1738, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1738 = VADDSHS | |
| { 1739, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1739 = VADDSWS | |
| { 1740, 3, 1, 4, 97, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1740 = VADDUBM | |
| { 1741, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1741 = VADDUBS | |
| { 1742, 3, 1, 4, 97, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1742 = VADDUDM | |
| { 1743, 3, 1, 4, 97, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1743 = VADDUHM | |
| { 1744, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1744 = VADDUHS | |
| { 1745, 3, 1, 4, 163, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1745 = VADDUQM | |
| { 1746, 3, 1, 4, 97, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1746 = VADDUWM | |
| { 1747, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1747 = VADDUWS | |
| { 1748, 3, 1, 4, 98, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1748 = VAND | |
| { 1749, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1749 = VANDC | |
| { 1750, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1750 = VAVGSB | |
| { 1751, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1751 = VAVGSH | |
| { 1752, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1752 = VAVGSW | |
| { 1753, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1753 = VAVGUB | |
| { 1754, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1754 = VAVGUH | |
| { 1755, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1755 = VAVGUW | |
| { 1756, 3, 1, 4, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1756 = VBPERMD | |
| { 1757, 3, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1757 = VBPERMQ | |
| { 1758, 3, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #1758 = VCFSX | |
| { 1759, 2, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1759 = VCFSX_0 | |
| { 1760, 3, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #1760 = VCFUX | |
| { 1761, 2, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1761 = VCFUX_0 | |
| { 1762, 3, 1, 4, 286, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1762 = VCIPHER | |
| { 1763, 3, 1, 4, 286, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1763 = VCIPHERLAST | |
| { 1764, 2, 1, 4, 139, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1764 = VCLZB | |
| { 1765, 2, 1, 4, 139, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1765 = VCLZD | |
| { 1766, 2, 1, 4, 139, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1766 = VCLZH | |
| { 1767, 2, 1, 4, 163, 0, 0x0ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #1767 = VCLZLSBB | |
| { 1768, 2, 1, 4, 139, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1768 = VCLZW | |
| { 1769, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1769 = VCMPBFP | |
| { 1770, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1770 = VCMPBFP_rec | |
| { 1771, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1771 = VCMPEQFP | |
| { 1772, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1772 = VCMPEQFP_rec | |
| { 1773, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1773 = VCMPEQUB | |
| { 1774, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1774 = VCMPEQUB_rec | |
| { 1775, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1775 = VCMPEQUD | |
| { 1776, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1776 = VCMPEQUD_rec | |
| { 1777, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1777 = VCMPEQUH | |
| { 1778, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1778 = VCMPEQUH_rec | |
| { 1779, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1779 = VCMPEQUW | |
| { 1780, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1780 = VCMPEQUW_rec | |
| { 1781, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1781 = VCMPGEFP | |
| { 1782, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1782 = VCMPGEFP_rec | |
| { 1783, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1783 = VCMPGTFP | |
| { 1784, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1784 = VCMPGTFP_rec | |
| { 1785, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1785 = VCMPGTSB | |
| { 1786, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1786 = VCMPGTSB_rec | |
| { 1787, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1787 = VCMPGTSD | |
| { 1788, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1788 = VCMPGTSD_rec | |
| { 1789, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1789 = VCMPGTSH | |
| { 1790, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1790 = VCMPGTSH_rec | |
| { 1791, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1791 = VCMPGTSW | |
| { 1792, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1792 = VCMPGTSW_rec | |
| { 1793, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1793 = VCMPGTUB | |
| { 1794, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1794 = VCMPGTUB_rec | |
| { 1795, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1795 = VCMPGTUD | |
| { 1796, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1796 = VCMPGTUD_rec | |
| { 1797, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1797 = VCMPGTUH | |
| { 1798, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1798 = VCMPGTUH_rec | |
| { 1799, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1799 = VCMPGTUW | |
| { 1800, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1800 = VCMPGTUW_rec | |
| { 1801, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1801 = VCMPNEB | |
| { 1802, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1802 = VCMPNEB_rec | |
| { 1803, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1803 = VCMPNEH | |
| { 1804, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1804 = VCMPNEH_rec | |
| { 1805, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1805 = VCMPNEW | |
| { 1806, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1806 = VCMPNEW_rec | |
| { 1807, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1807 = VCMPNEZB | |
| { 1808, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1808 = VCMPNEZB_rec | |
| { 1809, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1809 = VCMPNEZH | |
| { 1810, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1810 = VCMPNEZH_rec | |
| { 1811, 3, 1, 4, 138, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1811 = VCMPNEZW | |
| { 1812, 3, 1, 4, 138, 0, 0x28ULL, nullptr, ImplicitList20, OperandInfo74, -1 ,nullptr }, // Inst #1812 = VCMPNEZW_rec | |
| { 1813, 3, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #1813 = VCTSXS | |
| { 1814, 2, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1814 = VCTSXS_0 | |
| { 1815, 3, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #1815 = VCTUXS | |
| { 1816, 2, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1816 = VCTUXS_0 | |
| { 1817, 2, 1, 4, 139, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1817 = VCTZB | |
| { 1818, 2, 1, 4, 139, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1818 = VCTZD | |
| { 1819, 2, 1, 4, 139, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1819 = VCTZH | |
| { 1820, 2, 1, 4, 163, 0, 0x0ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #1820 = VCTZLSBB | |
| { 1821, 2, 1, 4, 139, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1821 = VCTZW | |
| { 1822, 3, 1, 4, 97, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1822 = VEQV | |
| { 1823, 2, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1823 = VEXPTEFP | |
| { 1824, 3, 1, 4, 163, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #1824 = VEXTRACTD | |
| { 1825, 3, 1, 4, 163, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #1825 = VEXTRACTUB | |
| { 1826, 3, 1, 4, 163, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #1826 = VEXTRACTUH | |
| { 1827, 3, 1, 4, 163, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #1827 = VEXTRACTUW | |
| { 1828, 2, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1828 = VEXTSB2D | |
| { 1829, 2, 1, 4, 97, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #1829 = VEXTSB2Ds | |
| { 1830, 2, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1830 = VEXTSB2W | |
| { 1831, 2, 1, 4, 97, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #1831 = VEXTSB2Ws | |
| { 1832, 2, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1832 = VEXTSH2D | |
| { 1833, 2, 1, 4, 97, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #1833 = VEXTSH2Ds | |
| { 1834, 2, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1834 = VEXTSH2W | |
| { 1835, 2, 1, 4, 97, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #1835 = VEXTSH2Ws | |
| { 1836, 2, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1836 = VEXTSW2D | |
| { 1837, 2, 1, 4, 97, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #1837 = VEXTSW2Ds | |
| { 1838, 3, 1, 4, 163, 0, 0x0ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #1838 = VEXTUBLX | |
| { 1839, 3, 1, 4, 163, 0, 0x0ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #1839 = VEXTUBRX | |
| { 1840, 3, 1, 4, 163, 0, 0x0ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #1840 = VEXTUHLX | |
| { 1841, 3, 1, 4, 163, 0, 0x0ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #1841 = VEXTUHRX | |
| { 1842, 3, 1, 4, 163, 0, 0x0ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #1842 = VEXTUWLX | |
| { 1843, 3, 1, 4, 163, 0, 0x0ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #1843 = VEXTUWRX | |
| { 1844, 2, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1844 = VGBBD | |
| { 1845, 4, 1, 4, 163, 0, 0x0ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #1845 = VINSERTB | |
| { 1846, 3, 1, 4, 163, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #1846 = VINSERTD | |
| { 1847, 4, 1, 4, 163, 0, 0x0ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #1847 = VINSERTH | |
| { 1848, 3, 1, 4, 163, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #1848 = VINSERTW | |
| { 1849, 2, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1849 = VLOGEFP | |
| { 1850, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1850 = VMADDFP | |
| { 1851, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1851 = VMAXFP | |
| { 1852, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1852 = VMAXSB | |
| { 1853, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1853 = VMAXSD | |
| { 1854, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1854 = VMAXSH | |
| { 1855, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1855 = VMAXSW | |
| { 1856, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1856 = VMAXUB | |
| { 1857, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1857 = VMAXUD | |
| { 1858, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1858 = VMAXUH | |
| { 1859, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1859 = VMAXUW | |
| { 1860, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1860 = VMHADDSHS | |
| { 1861, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1861 = VMHRADDSHS | |
| { 1862, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1862 = VMINFP | |
| { 1863, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1863 = VMINSB | |
| { 1864, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1864 = VMINSD | |
| { 1865, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1865 = VMINSH | |
| { 1866, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1866 = VMINSW | |
| { 1867, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1867 = VMINUB | |
| { 1868, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1868 = VMINUD | |
| { 1869, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1869 = VMINUH | |
| { 1870, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1870 = VMINUW | |
| { 1871, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1871 = VMLADDUHM | |
| { 1872, 3, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1872 = VMRGEW | |
| { 1873, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1873 = VMRGHB | |
| { 1874, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1874 = VMRGHH | |
| { 1875, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1875 = VMRGHW | |
| { 1876, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1876 = VMRGLB | |
| { 1877, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1877 = VMRGLH | |
| { 1878, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1878 = VMRGLW | |
| { 1879, 3, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1879 = VMRGOW | |
| { 1880, 4, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1880 = VMSUMMBM | |
| { 1881, 4, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1881 = VMSUMSHM | |
| { 1882, 4, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1882 = VMSUMSHS | |
| { 1883, 4, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1883 = VMSUMUBM | |
| { 1884, 4, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1884 = VMSUMUHM | |
| { 1885, 4, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1885 = VMSUMUHS | |
| { 1886, 2, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1886 = VMUL10CUQ | |
| { 1887, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1887 = VMUL10ECUQ | |
| { 1888, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1888 = VMUL10EUQ | |
| { 1889, 2, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1889 = VMUL10UQ | |
| { 1890, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1890 = VMULESB | |
| { 1891, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1891 = VMULESH | |
| { 1892, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1892 = VMULESW | |
| { 1893, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1893 = VMULEUB | |
| { 1894, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1894 = VMULEUH | |
| { 1895, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1895 = VMULEUW | |
| { 1896, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1896 = VMULOSB | |
| { 1897, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1897 = VMULOSH | |
| { 1898, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1898 = VMULOSW | |
| { 1899, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1899 = VMULOUB | |
| { 1900, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1900 = VMULOUH | |
| { 1901, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1901 = VMULOUW | |
| { 1902, 3, 1, 4, 143, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1902 = VMULUWM | |
| { 1903, 3, 1, 4, 97, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1903 = VNAND | |
| { 1904, 3, 1, 4, 286, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1904 = VNCIPHER | |
| { 1905, 3, 1, 4, 286, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1905 = VNCIPHERLAST | |
| { 1906, 2, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1906 = VNEGD | |
| { 1907, 2, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1907 = VNEGW | |
| { 1908, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1908 = VNMSUBFP | |
| { 1909, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1909 = VNOR | |
| { 1910, 3, 1, 4, 98, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1910 = VOR | |
| { 1911, 3, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1911 = VORC | |
| { 1912, 4, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1912 = VPERM | |
| { 1913, 4, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1913 = VPERMR | |
| { 1914, 4, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1914 = VPERMXOR | |
| { 1915, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1915 = VPKPX | |
| { 1916, 3, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1916 = VPKSDSS | |
| { 1917, 3, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1917 = VPKSDUS | |
| { 1918, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1918 = VPKSHSS | |
| { 1919, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1919 = VPKSHUS | |
| { 1920, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1920 = VPKSWSS | |
| { 1921, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1921 = VPKSWUS | |
| { 1922, 3, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1922 = VPKUDUM | |
| { 1923, 3, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1923 = VPKUDUS | |
| { 1924, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1924 = VPKUHUM | |
| { 1925, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1925 = VPKUHUS | |
| { 1926, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1926 = VPKUWUM | |
| { 1927, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1927 = VPKUWUS | |
| { 1928, 3, 1, 4, 286, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1928 = VPMSUMB | |
| { 1929, 3, 1, 4, 286, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1929 = VPMSUMD | |
| { 1930, 3, 1, 4, 286, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1930 = VPMSUMH | |
| { 1931, 3, 1, 4, 286, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1931 = VPMSUMW | |
| { 1932, 2, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1932 = VPOPCNTB | |
| { 1933, 2, 1, 4, 139, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1933 = VPOPCNTD | |
| { 1934, 2, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1934 = VPOPCNTH | |
| { 1935, 2, 1, 4, 139, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1935 = VPOPCNTW | |
| { 1936, 2, 1, 4, 139, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1936 = VPRTYBD | |
| { 1937, 2, 1, 4, 163, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1937 = VPRTYBQ | |
| { 1938, 2, 1, 4, 139, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1938 = VPRTYBW | |
| { 1939, 2, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1939 = VREFP | |
| { 1940, 2, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1940 = VRFIM | |
| { 1941, 2, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1941 = VRFIN | |
| { 1942, 2, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1942 = VRFIP | |
| { 1943, 2, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1943 = VRFIZ | |
| { 1944, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1944 = VRLB | |
| { 1945, 3, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1945 = VRLD | |
| { 1946, 4, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1946 = VRLDMI | |
| { 1947, 3, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1947 = VRLDNM | |
| { 1948, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1948 = VRLH | |
| { 1949, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1949 = VRLW | |
| { 1950, 4, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1950 = VRLWMI | |
| { 1951, 3, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1951 = VRLWNM | |
| { 1952, 2, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1952 = VRSQRTEFP | |
| { 1953, 2, 1, 4, 286, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #1953 = VSBOX | |
| { 1954, 4, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1954 = VSEL | |
| { 1955, 4, 1, 4, 140, 0, 0x0ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #1955 = VSHASIGMAD | |
| { 1956, 4, 1, 4, 140, 0, 0x0ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #1956 = VSHASIGMAW | |
| { 1957, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1957 = VSL | |
| { 1958, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1958 = VSLB | |
| { 1959, 3, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1959 = VSLD | |
| { 1960, 4, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #1960 = VSLDOI | |
| { 1961, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1961 = VSLH | |
| { 1962, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1962 = VSLO | |
| { 1963, 3, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1963 = VSLV | |
| { 1964, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1964 = VSLW | |
| { 1965, 3, 1, 4, 161, 0, 0x28ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #1965 = VSPLTB | |
| { 1966, 3, 1, 4, 161, 0, 0x28ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1966 = VSPLTBs | |
| { 1967, 3, 1, 4, 161, 0, 0x28ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #1967 = VSPLTH | |
| { 1968, 3, 1, 4, 161, 0, 0x28ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1968 = VSPLTHs | |
| { 1969, 2, 1, 4, 161, 0, 0x28ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #1969 = VSPLTISB | |
| { 1970, 2, 1, 4, 161, 0, 0x28ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #1970 = VSPLTISH | |
| { 1971, 2, 1, 4, 161, 0, 0x28ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #1971 = VSPLTISW | |
| { 1972, 3, 1, 4, 161, 0, 0x28ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #1972 = VSPLTW | |
| { 1973, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1973 = VSR | |
| { 1974, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1974 = VSRAB | |
| { 1975, 3, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1975 = VSRAD | |
| { 1976, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1976 = VSRAH | |
| { 1977, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1977 = VSRAW | |
| { 1978, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1978 = VSRB | |
| { 1979, 3, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1979 = VSRD | |
| { 1980, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1980 = VSRH | |
| { 1981, 3, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1981 = VSRO | |
| { 1982, 3, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1982 = VSRV | |
| { 1983, 3, 1, 4, 98, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1983 = VSRW | |
| { 1984, 3, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1984 = VSUBCUQ | |
| { 1985, 3, 1, 4, 140, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1985 = VSUBCUW | |
| { 1986, 4, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1986 = VSUBECUQ | |
| { 1987, 4, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1987 = VSUBEUQM | |
| { 1988, 3, 1, 4, 143, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1988 = VSUBFP | |
| { 1989, 3, 1, 4, 140, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1989 = VSUBSBS | |
| { 1990, 3, 1, 4, 140, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1990 = VSUBSHS | |
| { 1991, 3, 1, 4, 140, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1991 = VSUBSWS | |
| { 1992, 3, 1, 4, 97, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1992 = VSUBUBM | |
| { 1993, 3, 1, 4, 140, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1993 = VSUBUBS | |
| { 1994, 3, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1994 = VSUBUDM | |
| { 1995, 3, 1, 4, 97, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1995 = VSUBUHM | |
| { 1996, 3, 1, 4, 140, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1996 = VSUBUHS | |
| { 1997, 3, 1, 4, 163, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1997 = VSUBUQM | |
| { 1998, 3, 1, 4, 97, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1998 = VSUBUWM | |
| { 1999, 3, 1, 4, 140, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #1999 = VSUBUWS | |
| { 2000, 3, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #2000 = VSUM2SWS | |
| { 2001, 3, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #2001 = VSUM4SBS | |
| { 2002, 3, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #2002 = VSUM4SHS | |
| { 2003, 3, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #2003 = VSUM4UBS | |
| { 2004, 3, 1, 4, 142, 0, 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #2004 = VSUMSWS | |
| { 2005, 2, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #2005 = VUPKHPX | |
| { 2006, 2, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #2006 = VUPKHSB | |
| { 2007, 2, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #2007 = VUPKHSH | |
| { 2008, 2, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #2008 = VUPKHSW | |
| { 2009, 2, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #2009 = VUPKLPX | |
| { 2010, 2, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #2010 = VUPKLSB | |
| { 2011, 2, 1, 4, 162, 0, 0x28ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #2011 = VUPKLSH | |
| { 2012, 2, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #2012 = VUPKLSW | |
| { 2013, 3, 1, 4, 98, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #2013 = VXOR | |
| { 2014, 1, 1, 4, 98, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #2014 = V_SET0 | |
| { 2015, 1, 1, 4, 98, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #2015 = V_SET0B | |
| { 2016, 1, 1, 4, 98, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #2016 = V_SET0H | |
| { 2017, 1, 1, 4, 162, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #2017 = V_SETALLONES | |
| { 2018, 1, 1, 4, 162, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #2018 = V_SETALLONESB | |
| { 2019, 1, 1, 4, 162, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #2019 = V_SETALLONESH | |
| { 2020, 1, 0, 4, 123, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2020 = WAIT | |
| { 2021, 1, 0, 4, 309, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2021 = WRTEE | |
| { 2022, 1, 0, 4, 309, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2022 = WRTEEI | |
| { 2023, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #2023 = XOR | |
| { 2024, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #2024 = XOR8 | |
| { 2025, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #2025 = XOR8_rec | |
| { 2026, 3, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #2026 = XORI | |
| { 2027, 3, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2027 = XORI8 | |
| { 2028, 3, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #2028 = XORIS | |
| { 2029, 3, 1, 4, 116, 0, 0x8ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2029 = XORIS8 | |
| { 2030, 3, 1, 4, 116, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList4, OperandInfo55, -1 ,nullptr }, // Inst #2030 = XOR_rec | |
| { 2031, 2, 1, 4, 120, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2031 = XSABSDP | |
| { 2032, 2, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #2032 = XSABSQP | |
| { 2033, 3, 1, 4, 159, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2033 = XSADDDP | |
| { 2034, 3, 1, 4, 165, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #2034 = XSADDQP | |
| { 2035, 3, 1, 4, 165, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #2035 = XSADDQPO | |
| { 2036, 3, 1, 4, 159, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2036 = XSADDSP | |
| { 2037, 3, 1, 4, 109, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2037 = XSCMPEQDP | |
| { 2038, 3, 1, 4, 109, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2038 = XSCMPEXPDP | |
| { 2039, 3, 1, 4, 164, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2039 = XSCMPEXPQP | |
| { 2040, 3, 1, 4, 109, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2040 = XSCMPGEDP | |
| { 2041, 3, 1, 4, 109, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2041 = XSCMPGTDP | |
| { 2042, 3, 1, 4, 109, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2042 = XSCMPODP | |
| { 2043, 3, 1, 4, 164, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2043 = XSCMPOQP | |
| { 2044, 3, 1, 4, 109, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2044 = XSCMPUDP | |
| { 2045, 3, 1, 4, 164, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2045 = XSCMPUQP | |
| { 2046, 3, 1, 4, 120, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2046 = XSCPSGNDP | |
| { 2047, 3, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #2047 = XSCPSGNQP | |
| { 2048, 2, 1, 4, 159, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2048 = XSCVDPHP | |
| { 2049, 2, 1, 4, 165, 0, 0x0ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2049 = XSCVDPQP | |
| { 2050, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2050 = XSCVDPSP | |
| { 2051, 2, 1, 4, 159, 0, 0x0ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2051 = XSCVDPSPN | |
| { 2052, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2052 = XSCVDPSXDS | |
| { 2053, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2053 = XSCVDPSXDSs | |
| { 2054, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2054 = XSCVDPSXWS | |
| { 2055, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2055 = XSCVDPSXWSs | |
| { 2056, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2056 = XSCVDPUXDS | |
| { 2057, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2057 = XSCVDPUXDSs | |
| { 2058, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2058 = XSCVDPUXWS | |
| { 2059, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2059 = XSCVDPUXWSs | |
| { 2060, 2, 1, 4, 159, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2060 = XSCVHPDP | |
| { 2061, 2, 1, 4, 165, 0, 0x0ULL, nullptr, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #2061 = XSCVQPDP | |
| { 2062, 2, 1, 4, 165, 0, 0x0ULL, nullptr, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #2062 = XSCVQPDPO | |
| { 2063, 2, 1, 4, 165, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #2063 = XSCVQPSDZ | |
| { 2064, 2, 1, 4, 165, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #2064 = XSCVQPSWZ | |
| { 2065, 2, 1, 4, 165, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #2065 = XSCVQPUDZ | |
| { 2066, 2, 1, 4, 165, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #2066 = XSCVQPUWZ | |
| { 2067, 2, 1, 4, 165, 0, 0x0ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2067 = XSCVSDQP | |
| { 2068, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2068 = XSCVSPDP | |
| { 2069, 2, 1, 4, 108, 0, 0x0ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #2069 = XSCVSPDPN | |
| { 2070, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2070 = XSCVSXDDP | |
| { 2071, 2, 1, 4, 159, 0, 0x0ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #2071 = XSCVSXDSP | |
| { 2072, 2, 1, 4, 165, 0, 0x0ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2072 = XSCVUDQP | |
| { 2073, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2073 = XSCVUXDDP | |
| { 2074, 2, 1, 4, 159, 0, 0x0ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #2074 = XSCVUXDSP | |
| { 2075, 3, 1, 4, 269, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2075 = XSDIVDP | |
| { 2076, 3, 1, 4, 169, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #2076 = XSDIVQP | |
| { 2077, 3, 1, 4, 169, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #2077 = XSDIVQPO | |
| { 2078, 3, 1, 4, 272, 0, 0x0ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2078 = XSDIVSP | |
| { 2079, 3, 1, 4, 134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #2079 = XSIEXPDP | |
| { 2080, 3, 1, 4, 98, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2080 = XSIEXPQP | |
| { 2081, 4, 1, 4, 151, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2081 = XSMADDADP | |
| { 2082, 4, 1, 4, 151, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2082 = XSMADDASP | |
| { 2083, 4, 1, 4, 151, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2083 = XSMADDMDP | |
| { 2084, 4, 1, 4, 151, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2084 = XSMADDMSP | |
| { 2085, 4, 1, 4, 167, 0, 0x0ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2085 = XSMADDQP | |
| { 2086, 4, 1, 4, 167, 0, 0x0ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2086 = XSMADDQPO | |
| { 2087, 3, 1, 4, 108, 0, 0x0ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2087 = XSMAXCDP | |
| { 2088, 3, 1, 4, 108, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2088 = XSMAXDP | |
| { 2089, 3, 1, 4, 108, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2089 = XSMAXJDP | |
| { 2090, 3, 1, 4, 108, 0, 0x0ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2090 = XSMINCDP | |
| { 2091, 3, 1, 4, 108, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2091 = XSMINDP | |
| { 2092, 3, 1, 4, 108, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2092 = XSMINJDP | |
| { 2093, 4, 1, 4, 151, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2093 = XSMSUBADP | |
| { 2094, 4, 1, 4, 151, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2094 = XSMSUBASP | |
| { 2095, 4, 1, 4, 151, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2095 = XSMSUBMDP | |
| { 2096, 4, 1, 4, 151, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2096 = XSMSUBMSP | |
| { 2097, 4, 1, 4, 167, 0, 0x0ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2097 = XSMSUBQP | |
| { 2098, 4, 1, 4, 167, 0, 0x0ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2098 = XSMSUBQPO | |
| { 2099, 3, 1, 4, 151, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2099 = XSMULDP | |
| { 2100, 3, 1, 4, 167, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #2100 = XSMULQP | |
| { 2101, 3, 1, 4, 167, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #2101 = XSMULQPO | |
| { 2102, 3, 1, 4, 151, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2102 = XSMULSP | |
| { 2103, 2, 1, 4, 120, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2103 = XSNABSDP | |
| { 2104, 2, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #2104 = XSNABSQP | |
| { 2105, 2, 1, 4, 120, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2105 = XSNEGDP | |
| { 2106, 2, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #2106 = XSNEGQP | |
| { 2107, 4, 1, 4, 151, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2107 = XSNMADDADP | |
| { 2108, 4, 1, 4, 151, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2108 = XSNMADDASP | |
| { 2109, 4, 1, 4, 151, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2109 = XSNMADDMDP | |
| { 2110, 4, 1, 4, 151, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2110 = XSNMADDMSP | |
| { 2111, 4, 1, 4, 167, 0, 0x0ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2111 = XSNMADDQP | |
| { 2112, 4, 1, 4, 167, 0, 0x0ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2112 = XSNMADDQPO | |
| { 2113, 4, 1, 4, 151, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2113 = XSNMSUBADP | |
| { 2114, 4, 1, 4, 151, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2114 = XSNMSUBASP | |
| { 2115, 4, 1, 4, 151, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2115 = XSNMSUBMDP | |
| { 2116, 4, 1, 4, 151, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2116 = XSNMSUBMSP | |
| { 2117, 4, 1, 4, 167, 0, 0x0ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2117 = XSNMSUBQP | |
| { 2118, 4, 1, 4, 167, 0, 0x0ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2118 = XSNMSUBQPO | |
| { 2119, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2119 = XSRDPI | |
| { 2120, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2120 = XSRDPIC | |
| { 2121, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2121 = XSRDPIM | |
| { 2122, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2122 = XSRDPIP | |
| { 2123, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2123 = XSRDPIZ | |
| { 2124, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2124 = XSREDP | |
| { 2125, 2, 1, 4, 159, 0, 0x0ULL, nullptr, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2125 = XSRESP | |
| { 2126, 4, 1, 4, 165, 0, 0x0ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #2126 = XSRQPI | |
| { 2127, 4, 1, 4, 165, 0, 0x0ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #2127 = XSRQPIX | |
| { 2128, 4, 1, 4, 165, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #2128 = XSRQPXP | |
| { 2129, 2, 1, 4, 159, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #2129 = XSRSP | |
| { 2130, 2, 1, 4, 159, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2130 = XSRSQRTEDP | |
| { 2131, 2, 1, 4, 159, 0, 0x0ULL, nullptr, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2131 = XSRSQRTESP | |
| { 2132, 2, 1, 4, 261, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2132 = XSSQRTDP | |
| { 2133, 2, 1, 4, 170, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #2133 = XSSQRTQP | |
| { 2134, 2, 1, 4, 170, 0, 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #2134 = XSSQRTQPO | |
| { 2135, 2, 1, 4, 266, 0, 0x0ULL, nullptr, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2135 = XSSQRTSP | |
| { 2136, 3, 1, 4, 159, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2136 = XSSUBDP | |
| { 2137, 3, 1, 4, 165, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #2137 = XSSUBQP | |
| { 2138, 3, 1, 4, 165, 0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #2138 = XSSUBQPO | |
| { 2139, 3, 1, 4, 159, 0, 0x0ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2139 = XSSUBSP | |
| { 2140, 3, 1, 4, 109, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #2140 = XSTDIVDP | |
| { 2141, 2, 1, 4, 109, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2141 = XSTSQRTDP | |
| { 2142, 3, 1, 4, 107, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2142 = XSTSTDCDP | |
| { 2143, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2143 = XSTSTDCQP | |
| { 2144, 3, 1, 4, 107, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2144 = XSTSTDCSP | |
| { 2145, 2, 1, 4, 120, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #2145 = XSXEXPDP | |
| { 2146, 2, 1, 4, 98, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #2146 = XSXEXPQP | |
| { 2147, 2, 1, 4, 108, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #2147 = XSXSIGDP | |
| { 2148, 2, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #2148 = XSXSIGQP | |
| { 2149, 2, 1, 4, 98, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2149 = XVABSDP | |
| { 2150, 2, 1, 4, 98, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2150 = XVABSSP | |
| { 2151, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2151 = XVADDDP | |
| { 2152, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2152 = XVADDSP | |
| { 2153, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2153 = XVCMPEQDP | |
| { 2154, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList18, ImplicitList20, OperandInfo291, -1 ,nullptr }, // Inst #2154 = XVCMPEQDP_rec | |
| { 2155, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2155 = XVCMPEQSP | |
| { 2156, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList18, ImplicitList20, OperandInfo291, -1 ,nullptr }, // Inst #2156 = XVCMPEQSP_rec | |
| { 2157, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2157 = XVCMPGEDP | |
| { 2158, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList18, ImplicitList20, OperandInfo291, -1 ,nullptr }, // Inst #2158 = XVCMPGEDP_rec | |
| { 2159, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2159 = XVCMPGESP | |
| { 2160, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList18, ImplicitList20, OperandInfo291, -1 ,nullptr }, // Inst #2160 = XVCMPGESP_rec | |
| { 2161, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2161 = XVCMPGTDP | |
| { 2162, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList18, ImplicitList20, OperandInfo291, -1 ,nullptr }, // Inst #2162 = XVCMPGTDP_rec | |
| { 2163, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2163 = XVCMPGTSP | |
| { 2164, 3, 1, 4, 138, 0, 0x0ULL, ImplicitList18, ImplicitList20, OperandInfo291, -1 ,nullptr }, // Inst #2164 = XVCMPGTSP_rec | |
| { 2165, 3, 1, 4, 98, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2165 = XVCPSGNDP | |
| { 2166, 3, 1, 4, 98, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2166 = XVCPSGNSP | |
| { 2167, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2167 = XVCVDPSP | |
| { 2168, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2168 = XVCVDPSXDS | |
| { 2169, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2169 = XVCVDPSXWS | |
| { 2170, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2170 = XVCVDPUXDS | |
| { 2171, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2171 = XVCVDPUXWS | |
| { 2172, 2, 1, 4, 142, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2172 = XVCVHPSP | |
| { 2173, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2173 = XVCVSPDP | |
| { 2174, 2, 1, 4, 142, 0, 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2174 = XVCVSPHP | |
| { 2175, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2175 = XVCVSPSXDS | |
| { 2176, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2176 = XVCVSPSXWS | |
| { 2177, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2177 = XVCVSPUXDS | |
| { 2178, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2178 = XVCVSPUXWS | |
| { 2179, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2179 = XVCVSXDDP | |
| { 2180, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2180 = XVCVSXDSP | |
| { 2181, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2181 = XVCVSXWDP | |
| { 2182, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2182 = XVCVSXWSP | |
| { 2183, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2183 = XVCVUXDDP | |
| { 2184, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2184 = XVCVUXDSP | |
| { 2185, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2185 = XVCVUXWDP | |
| { 2186, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2186 = XVCVUXWSP | |
| { 2187, 3, 1, 4, 274, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2187 = XVDIVDP | |
| { 2188, 3, 1, 4, 273, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2188 = XVDIVSP | |
| { 2189, 3, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2189 = XVIEXPDP | |
| { 2190, 3, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2190 = XVIEXPSP | |
| { 2191, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2191 = XVMADDADP | |
| { 2192, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2192 = XVMADDASP | |
| { 2193, 4, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2193 = XVMADDMDP | |
| { 2194, 4, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2194 = XVMADDMSP | |
| { 2195, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2195 = XVMAXDP | |
| { 2196, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2196 = XVMAXSP | |
| { 2197, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2197 = XVMINDP | |
| { 2198, 3, 1, 4, 140, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2198 = XVMINSP | |
| { 2199, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2199 = XVMSUBADP | |
| { 2200, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2200 = XVMSUBASP | |
| { 2201, 4, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2201 = XVMSUBMDP | |
| { 2202, 4, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2202 = XVMSUBMSP | |
| { 2203, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2203 = XVMULDP | |
| { 2204, 3, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2204 = XVMULSP | |
| { 2205, 2, 1, 4, 98, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2205 = XVNABSDP | |
| { 2206, 2, 1, 4, 98, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2206 = XVNABSSP | |
| { 2207, 2, 1, 4, 98, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2207 = XVNEGDP | |
| { 2208, 2, 1, 4, 98, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2208 = XVNEGSP | |
| { 2209, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2209 = XVNMADDADP | |
| { 2210, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2210 = XVNMADDASP | |
| { 2211, 4, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2211 = XVNMADDMDP | |
| { 2212, 4, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2212 = XVNMADDMSP | |
| { 2213, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2213 = XVNMSUBADP | |
| { 2214, 4, 1, 4, 142, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList18, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2214 = XVNMSUBASP | |
| { 2215, 4, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2215 = XVNMSUBMDP | |
| { 2216, 4, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2216 = XVNMSUBMSP | |
| { 2217, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2217 = XVRDPI | |
| { 2218, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2218 = XVRDPIC | |
| { 2219, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2219 = XVRDPIM | |
| { 2220, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2220 = XVRDPIP | |
| { 2221, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2221 = XVRDPIZ | |
| { 2222, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2222 = XVREDP | |
| { 2223, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2223 = XVRESP | |
| { 2224, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2224 = XVRSPI | |
| { 2225, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2225 = XVRSPIC | |
| { 2226, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2226 = XVRSPIM | |
| { 2227, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2227 = XVRSPIP | |
| { 2228, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2228 = XVRSPIZ | |
| { 2229, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2229 = XVRSQRTEDP | |
| { 2230, 2, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2230 = XVRSQRTESP | |
| { 2231, 2, 1, 4, 263, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2231 = XVSQRTDP | |
| { 2232, 2, 1, 4, 264, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2232 = XVSQRTSP | |
| { 2233, 3, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2233 = XVSUBDP | |
| { 2234, 3, 1, 4, 142, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2234 = XVSUBSP | |
| { 2235, 3, 1, 4, 141, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #2235 = XVTDIVDP | |
| { 2236, 3, 1, 4, 141, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #2236 = XVTDIVSP | |
| { 2237, 2, 1, 4, 141, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2237 = XVTSQRTDP | |
| { 2238, 2, 1, 4, 141, 0, 0x0ULL, ImplicitList18, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2238 = XVTSQRTSP | |
| { 2239, 3, 1, 4, 140, 0, 0x0ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2239 = XVTSTDCDP | |
| { 2240, 3, 1, 4, 140, 0, 0x0ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2240 = XVTSTDCSP | |
| { 2241, 2, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2241 = XVXEXPDP | |
| { 2242, 2, 1, 4, 98, 0, 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2242 = XVXEXPSP | |
| { 2243, 2, 1, 4, 140, 0, 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2243 = XVXSIGDP | |
| { 2244, 2, 1, 4, 140, 0, 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2244 = XVXSIGSP | |
| { 2245, 2, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2245 = XXBRD | |
| { 2246, 2, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2246 = XXBRH | |
| { 2247, 2, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2247 = XXBRQ | |
| { 2248, 2, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2248 = XXBRW | |
| { 2249, 3, 1, 4, 162, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #2249 = XXEXTRACTUW | |
| { 2250, 4, 1, 4, 162, 0, 0x0ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #2250 = XXINSERTW | |
| { 2251, 3, 1, 4, 97, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2251 = XXLAND | |
| { 2252, 3, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2252 = XXLANDC | |
| { 2253, 3, 1, 4, 97, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2253 = XXLEQV | |
| { 2254, 1, 1, 4, 97, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #2254 = XXLEQVOnes | |
| { 2255, 3, 1, 4, 97, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2255 = XXLNAND | |
| { 2256, 3, 1, 4, 97, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2256 = XXLNOR | |
| { 2257, 3, 1, 4, 97, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2257 = XXLOR | |
| { 2258, 3, 1, 4, 97, 0, 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2258 = XXLORC | |
| { 2259, 3, 1, 4, 97, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2259 = XXLORf | |
| { 2260, 3, 1, 4, 97, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2260 = XXLXOR | |
| { 2261, 1, 1, 4, 97, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #2261 = XXLXORdpz | |
| { 2262, 1, 1, 4, 97, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #2262 = XXLXORspz | |
| { 2263, 1, 1, 4, 97, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #2263 = XXLXORz | |
| { 2264, 3, 1, 4, 161, 0, 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2264 = XXMRGHW | |
| { 2265, 3, 1, 4, 161, 0, 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2265 = XXMRGLW | |
| { 2266, 3, 1, 4, 161, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2266 = XXPERM | |
| { 2267, 4, 1, 4, 161, 0, 0x0ULL, nullptr, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #2267 = XXPERMDI | |
| { 2268, 3, 1, 4, 161, 0, 0x0ULL, nullptr, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #2268 = XXPERMDIs | |
| { 2269, 3, 1, 4, 161, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2269 = XXPERMR | |
| { 2270, 4, 1, 4, 99, 0, 0x0ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2270 = XXSEL | |
| { 2271, 4, 1, 4, 161, 0, 0x0ULL, nullptr, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #2271 = XXSLDWI | |
| { 2272, 3, 1, 4, 161, 0, 0x0ULL, nullptr, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #2272 = XXSLDWIs | |
| { 2273, 2, 1, 4, 161, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #2273 = XXSPLTIB | |
| { 2274, 3, 1, 4, 161, 0, 0x0ULL, nullptr, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #2274 = XXSPLTW | |
| { 2275, 3, 1, 4, 161, 0, 0x0ULL, nullptr, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #2275 = XXSPLTWs | |
| { 2276, 3, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList12, OperandInfo306, -1 ,nullptr }, // Inst #2276 = gBC | |
| { 2277, 3, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList12, OperandInfo306, -1 ,nullptr }, // Inst #2277 = gBCA | |
| { 2278, 4, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList12, OperandInfo307, -1 ,nullptr }, // Inst #2278 = gBCAat | |
| { 2279, 3, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList23, ImplicitList12, OperandInfo308, -1 ,nullptr }, // Inst #2279 = gBCCTR | |
| { 2280, 3, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList23, ImplicitList31, OperandInfo308, -1 ,nullptr }, // Inst #2280 = gBCCTRL | |
| { 2281, 3, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList31, OperandInfo306, -1 ,nullptr }, // Inst #2281 = gBCL | |
| { 2282, 3, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList31, OperandInfo306, -1 ,nullptr }, // Inst #2282 = gBCLA | |
| { 2283, 4, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList31, OperandInfo307, -1 ,nullptr }, // Inst #2283 = gBCLAat | |
| { 2284, 3, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList23, ImplicitList12, OperandInfo308, -1 ,nullptr }, // Inst #2284 = gBCLR | |
| { 2285, 3, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList23, ImplicitList31, OperandInfo308, -1 ,nullptr }, // Inst #2285 = gBCLRL | |
| { 2286, 4, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList31, OperandInfo307, -1 ,nullptr }, // Inst #2286 = gBCLat | |
| { 2287, 4, 0, 4, 287, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList12, OperandInfo307, -1 ,nullptr }, // Inst #2287 = gBCat | |
| }; | |
| extern const char PPCInstrNameData[] = { | |
| /* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0, | |
| /* 9 */ 'M', 'T', 'F', 'S', 'B', '0', 0, | |
| /* 16 */ 'V', '_', 'S', 'E', 'T', '0', 0, | |
| /* 23 */ 'V', 'C', 'T', 'S', 'X', 'S', '_', '0', 0, | |
| /* 32 */ 'V', 'C', 'T', 'U', 'X', 'S', '_', '0', 0, | |
| /* 41 */ 'V', 'C', 'F', 'S', 'X', '_', '0', 0, | |
| /* 49 */ 'V', 'C', 'F', 'U', 'X', '_', '0', 0, | |
| /* 57 */ 'M', 'T', 'F', 'S', 'B', '1', 0, | |
| /* 64 */ 'A', 'D', 'D', 'I', 'S', 'd', 't', 'p', 'r', 'e', 'l', 'H', 'A', '3', '2', 0, | |
| /* 80 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '3', '2', 0, | |
| /* 100 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '3', '2', 0, | |
| /* 120 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '3', '2', 0, | |
| /* 141 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '3', '2', 0, | |
| /* 161 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '3', '2', 0, | |
| /* 182 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '3', '2', 0, | |
| /* 202 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', 0, | |
| /* 218 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', 0, | |
| /* 238 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '3', '2', 0, | |
| /* 258 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '3', '2', 0, | |
| /* 277 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '3', '2', 0, | |
| /* 298 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '3', '2', 0, | |
| /* 318 */ 'A', 'D', 'D', 'I', 't', 'l', 's', 'g', 'd', 'L', '3', '2', 0, | |
| /* 331 */ 'A', 'D', 'D', 'I', 't', 'l', 's', 'l', 'd', 'L', '3', '2', 0, | |
| /* 344 */ 'L', 'D', 'g', 'o', 't', 'T', 'p', 'r', 'e', 'l', 'L', '3', '2', 0, | |
| /* 358 */ 'A', 'D', 'D', 'I', 'd', 't', 'p', 'r', 'e', 'l', 'L', '3', '2', 0, | |
| /* 372 */ 'A', 'D', 'D', 'I', 't', 'l', 's', 'g', 'd', 'L', 'A', 'D', 'D', 'R', '3', '2', 0, | |
| /* 389 */ 'A', 'D', 'D', 'I', 't', 'l', 's', 'l', 'd', 'L', 'A', 'D', 'D', 'R', '3', '2', 0, | |
| /* 406 */ 'G', 'E', 'T', 't', 'l', 's', 'l', 'd', 'A', 'D', 'D', 'R', '3', '2', 0, | |
| /* 421 */ 'G', 'E', 'T', 't', 'l', 's', 'A', 'D', 'D', 'R', '3', '2', 0, | |
| /* 434 */ 'L', 'W', 'A', '_', '3', '2', 0, | |
| /* 441 */ 'S', 'R', 'A', 'D', 'I', '_', '3', '2', 0, | |
| /* 450 */ 'R', 'L', 'D', 'I', 'C', 'L', '_', '3', '2', 0, | |
| /* 460 */ 'R', 'L', 'D', 'I', 'C', 'R', '_', '3', '2', 0, | |
| /* 470 */ 'S', 'T', 'B', 'X', 'T', 'L', 'S', '_', '3', '2', 0, | |
| /* 481 */ 'S', 'T', 'H', 'X', 'T', 'L', 'S', '_', '3', '2', 0, | |
| /* 492 */ 'S', 'T', 'W', 'X', 'T', 'L', 'S', '_', '3', '2', 0, | |
| /* 503 */ 'L', 'B', 'Z', 'X', 'T', 'L', 'S', '_', '3', '2', 0, | |
| /* 514 */ 'L', 'H', 'Z', 'X', 'T', 'L', 'S', '_', '3', '2', 0, | |
| /* 525 */ 'L', 'W', 'Z', 'X', 'T', 'L', 'S', '_', '3', '2', 0, | |
| /* 536 */ 'E', 'X', 'T', 'S', 'W', '_', '3', '2', 0, | |
| /* 545 */ 'L', 'W', 'A', 'X', '_', '3', '2', 0, | |
| /* 553 */ 'D', 'F', 'L', 'O', 'A', 'D', 'f', '3', '2', 0, | |
| /* 563 */ 'X', 'F', 'L', 'O', 'A', 'D', 'f', '3', '2', 0, | |
| /* 573 */ 'D', 'F', 'S', 'T', 'O', 'R', 'E', 'f', '3', '2', 0, | |
| /* 584 */ 'X', 'F', 'S', 'T', 'O', 'R', 'E', 'f', '3', '2', 0, | |
| /* 595 */ 'E', 'H', '_', 'S', 'j', 'L', 'j', '_', 'L', 'o', 'n', 'g', 'J', 'm', 'p', '3', '2', 0, | |
| /* 613 */ 'E', 'H', '_', 'S', 'j', 'L', 'j', '_', 'S', 'e', 't', 'J', 'm', 'p', '3', '2', 0, | |
| /* 630 */ 'T', 'L', 'B', 'R', 'E', '2', 0, | |
| /* 637 */ 'T', 'L', 'B', 'W', 'E', '2', 0, | |
| /* 644 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0, | |
| /* 652 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0, | |
| /* 660 */ 'T', 'L', 'B', 'S', 'X', '2', 0, | |
| /* 667 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '6', '4', 0, | |
| /* 687 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '6', '4', 0, | |
| /* 707 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '6', '4', 0, | |
| /* 728 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '6', '4', 0, | |
| /* 748 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '6', '4', 0, | |
| /* 769 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '6', '4', 0, | |
| /* 789 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', 0, | |
| /* 805 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', 0, | |
| /* 825 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '6', '4', 0, | |
| /* 845 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '6', '4', 0, | |
| /* 864 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '6', '4', 0, | |
| /* 885 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '6', '4', 0, | |
| /* 905 */ 'D', 'S', 'T', '6', '4', 0, | |
| /* 911 */ 'D', 'S', 'T', 'S', 'T', '6', '4', 0, | |
| /* 919 */ 'D', 'S', 'T', 'T', '6', '4', 0, | |
| /* 926 */ 'D', 'S', 'T', 'S', 'T', 'T', '6', '4', 0, | |
| /* 935 */ 'E', 'X', 'T', 'S', 'B', '8', '_', '3', '2', '_', '6', '4', 0, | |
| /* 948 */ 'E', 'X', 'T', 'S', 'H', '8', '_', '3', '2', '_', '6', '4', 0, | |
| /* 961 */ 'E', 'X', 'T', 'S', 'W', 'S', 'L', 'I', '_', '3', '2', '_', '6', '4', 0, | |
| /* 976 */ 'R', 'L', 'D', 'I', 'C', 'L', '_', '3', '2', '_', '6', '4', 0, | |
| /* 989 */ 'E', 'X', 'T', 'S', 'W', '_', '3', '2', '_', '6', '4', 0, | |
| /* 1001 */ 'D', 'F', 'L', 'O', 'A', 'D', 'f', '6', '4', 0, | |
| /* 1011 */ 'X', 'F', 'L', 'O', 'A', 'D', 'f', '6', '4', 0, | |
| /* 1021 */ 'D', 'F', 'S', 'T', 'O', 'R', 'E', 'f', '6', '4', 0, | |
| /* 1032 */ 'X', 'F', 'S', 'T', 'O', 'R', 'E', 'f', '6', '4', 0, | |
| /* 1043 */ 'E', 'H', '_', 'S', 'j', 'L', 'j', '_', 'L', 'o', 'n', 'g', 'J', 'm', 'p', '6', '4', 0, | |
| /* 1061 */ 'E', 'H', '_', 'S', 'j', 'L', 'j', '_', 'S', 'e', 't', 'J', 'm', 'p', '6', '4', 0, | |
| /* 1078 */ 'A', 'D', 'D', '4', 0, | |
| /* 1083 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'S', 'P', 'E', '4', 0, | |
| /* 1098 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'S', 'P', 'E', '4', 0, | |
| /* 1110 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', '4', 0, | |
| /* 1123 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'F', '4', 0, | |
| /* 1133 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', '4', 0, | |
| /* 1146 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', '4', 0, | |
| /* 1156 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', '1', '6', 0, | |
| /* 1170 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'F', '1', '6', 0, | |
| /* 1181 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '1', '6', 0, | |
| /* 1201 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '1', '6', 0, | |
| /* 1221 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '1', '6', 0, | |
| /* 1242 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '1', '6', 0, | |
| /* 1262 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '1', '6', 0, | |
| /* 1283 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '1', '6', 0, | |
| /* 1303 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', 0, | |
| /* 1319 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', 0, | |
| /* 1339 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '1', '6', 0, | |
| /* 1359 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '1', '6', 0, | |
| /* 1378 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '1', '6', 0, | |
| /* 1399 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '1', '6', 0, | |
| /* 1419 */ 'N', 'O', 'P', '_', 'G', 'T', '_', 'P', 'W', 'R', '6', 0, | |
| /* 1431 */ 'N', 'O', 'P', '_', 'G', 'T', '_', 'P', 'W', 'R', '7', 0, | |
| /* 1443 */ 'T', 'A', 'I', 'L', 'B', 'A', '8', 0, | |
| /* 1451 */ 'L', 'H', 'A', '8', 0, | |
| /* 1456 */ 'A', 'D', 'D', 'I', 'S', 't', 'o', 'c', 'H', 'A', '8', 0, | |
| /* 1468 */ 'B', 'L', 'A', '8', 0, | |
| /* 1473 */ 'T', 'A', 'I', 'L', 'B', '8', 0, | |
| /* 1480 */ 'C', 'M', 'P', 'B', '8', 0, | |
| /* 1486 */ 'C', 'M', 'P', 'R', 'B', '8', 0, | |
| /* 1493 */ 'E', 'X', 'T', 'S', 'B', '8', 0, | |
| /* 1500 */ 'S', 'E', 'T', 'B', '8', 0, | |
| /* 1506 */ 'M', 'F', 'T', 'B', '8', 0, | |
| /* 1512 */ 'S', 'T', 'B', '8', 0, | |
| /* 1517 */ 'A', 'D', 'D', 'C', '8', 0, | |
| /* 1523 */ 'A', 'N', 'D', 'C', '8', 0, | |
| /* 1529 */ 'S', 'U', 'B', 'F', 'C', '8', 0, | |
| /* 1536 */ 'A', 'D', 'D', 'I', 'C', '8', 0, | |
| /* 1543 */ 'S', 'U', 'B', 'F', 'I', 'C', '8', 0, | |
| /* 1551 */ 'D', 'Y', 'N', 'A', 'L', 'L', 'O', 'C', '8', 0, | |
| /* 1561 */ 'O', 'R', 'C', '8', 0, | |
| /* 1566 */ 'A', 'D', 'D', '8', 0, | |
| /* 1571 */ 'M', 'A', 'D', 'D', 'L', 'D', '8', 0, | |
| /* 1579 */ 'N', 'A', 'N', 'D', '8', 0, | |
| /* 1585 */ 'C', 'F', 'E', 'N', 'C', 'E', '8', 0, | |
| /* 1593 */ 'A', 'D', 'D', 'E', '8', 0, | |
| /* 1599 */ 'S', 'U', 'B', 'F', 'E', '8', 0, | |
| /* 1606 */ 'A', 'D', 'D', 'M', 'E', '8', 0, | |
| /* 1613 */ 'S', 'U', 'B', 'F', 'M', 'E', '8', 0, | |
| /* 1621 */ 'C', 'P', '_', 'P', 'A', 'S', 'T', 'E', '8', 0, | |
| /* 1631 */ 'A', 'D', 'D', 'Z', 'E', '8', 0, | |
| /* 1638 */ 'S', 'U', 'B', 'F', 'Z', 'E', '8', 0, | |
| /* 1646 */ 'S', 'U', 'B', 'F', '8', 0, | |
| /* 1652 */ 'M', 'F', 'O', 'C', 'R', 'F', '8', 0, | |
| /* 1660 */ 'M', 'T', 'O', 'C', 'R', 'F', '8', 0, | |
| /* 1668 */ 'M', 'T', 'C', 'R', 'F', '8', 0, | |
| /* 1675 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', '8', 0, | |
| /* 1688 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'F', '8', 0, | |
| /* 1698 */ 'N', 'E', 'G', '8', 0, | |
| /* 1703 */ 'E', 'X', 'T', 'S', 'H', '8', 0, | |
| /* 1710 */ 'S', 'T', 'H', '8', 0, | |
| /* 1715 */ 'A', 'D', 'D', 'I', '8', 0, | |
| /* 1721 */ 'M', 'U', 'L', 'L', 'I', '8', 0, | |
| /* 1728 */ 'R', 'L', 'W', 'I', 'M', 'I', '8', 0, | |
| /* 1736 */ 'X', 'O', 'R', 'I', '8', 0, | |
| /* 1742 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '8', 0, | |
| /* 1761 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', '8', 0, | |
| /* 1774 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '8', 0, | |
| /* 1793 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '8', 0, | |
| /* 1813 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '8', 0, | |
| /* 1832 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '8', 0, | |
| /* 1852 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '8', 0, | |
| /* 1871 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '8', 0, | |
| /* 1886 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '8', 0, | |
| /* 1905 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '8', 0, | |
| /* 1924 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '8', 0, | |
| /* 1942 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', '8', 0, | |
| /* 1952 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '8', 0, | |
| /* 1972 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '8', 0, | |
| /* 1991 */ 'B', 'L', '8', 0, | |
| /* 1995 */ 'I', 'S', 'E', 'L', '8', 0, | |
| /* 2001 */ 'B', 'C', 'T', 'R', 'L', '8', 0, | |
| /* 2008 */ 'B', 'C', 'C', 'T', 'R', 'L', '8', 0, | |
| /* 2016 */ 'B', 'C', 'C', 'C', 'T', 'R', 'L', '8', 0, | |
| /* 2025 */ 'R', 'L', 'W', 'I', 'N', 'M', '8', 0, | |
| /* 2033 */ 'R', 'L', 'W', 'N', 'M', '8', 0, | |
| /* 2040 */ 'M', 'F', 'C', 'R', '8', 0, | |
| /* 2046 */ 'B', 'L', 'R', '8', 0, | |
| /* 2051 */ 'M', 'F', 'L', 'R', '8', 0, | |
| /* 2057 */ 'M', 'T', 'L', 'R', '8', 0, | |
| /* 2063 */ 'B', 'D', 'Z', 'L', 'R', '8', 0, | |
| /* 2070 */ 'B', 'D', 'N', 'Z', 'L', 'R', '8', 0, | |
| /* 2078 */ 'M', 'o', 'v', 'e', 'P', 'C', 't', 'o', 'L', 'R', '8', 0, | |
| /* 2090 */ 'N', 'O', 'R', '8', 0, | |
| /* 2095 */ 'X', 'O', 'R', '8', 0, | |
| /* 2100 */ 'M', 'F', 'S', 'P', 'R', '8', 0, | |
| /* 2107 */ 'M', 'T', 'S', 'P', 'R', '8', 0, | |
| /* 2114 */ 'T', 'A', 'I', 'L', 'B', 'C', 'T', 'R', '8', 0, | |
| /* 2124 */ 'B', 'C', 'C', 'T', 'R', '8', 0, | |
| /* 2131 */ 'B', 'C', 'C', 'C', 'T', 'R', '8', 0, | |
| /* 2139 */ 'M', 'F', 'C', 'T', 'R', '8', 0, | |
| /* 2146 */ 'M', 'T', 'C', 'T', 'R', '8', 0, | |
| /* 2153 */ 'A', 'D', 'D', 'I', 'S', '8', 0, | |
| /* 2160 */ 'L', 'I', 'S', '8', 0, | |
| /* 2165 */ 'X', 'O', 'R', 'I', 'S', '8', 0, | |
| /* 2172 */ 'D', 'Y', 'N', 'A', 'R', 'E', 'A', 'O', 'F', 'F', 'S', 'E', 'T', '8', 0, | |
| /* 2187 */ 'A', 'N', 'D', 'I', '_', 'r', 'e', 'c', '_', '1', '_', 'E', 'Q', '_', 'B', 'I', 'T', '8', 0, | |
| /* 2206 */ 'A', 'N', 'D', 'I', '_', 'r', 'e', 'c', '_', '1', '_', 'G', 'T', '_', 'B', 'I', 'T', '8', 0, | |
| /* 2225 */ 'L', 'H', 'A', 'U', '8', 0, | |
| /* 2231 */ 'S', 'T', 'B', 'U', '8', 0, | |
| /* 2237 */ 'S', 'T', 'H', 'U', '8', 0, | |
| /* 2243 */ 'S', 'T', 'W', 'U', '8', 0, | |
| /* 2249 */ 'L', 'B', 'Z', 'U', '8', 0, | |
| /* 2255 */ 'L', 'H', 'Z', 'U', '8', 0, | |
| /* 2261 */ 'L', 'W', 'Z', 'U', '8', 0, | |
| /* 2267 */ 'E', 'Q', 'V', '8', 0, | |
| /* 2272 */ 'S', 'L', 'W', '8', 0, | |
| /* 2277 */ 'S', 'R', 'W', '8', 0, | |
| /* 2282 */ 'S', 'T', 'W', '8', 0, | |
| /* 2287 */ 'C', 'N', 'T', 'L', 'Z', 'W', '8', 0, | |
| /* 2295 */ 'C', 'N', 'T', 'T', 'Z', 'W', '8', 0, | |
| /* 2303 */ 'L', 'H', 'A', 'X', '8', 0, | |
| /* 2309 */ 'S', 'T', 'B', 'X', '8', 0, | |
| /* 2315 */ 'S', 'T', 'H', 'X', '8', 0, | |
| /* 2321 */ 'L', 'H', 'B', 'R', 'X', '8', 0, | |
| /* 2328 */ 'L', 'W', 'B', 'R', 'X', '8', 0, | |
| /* 2335 */ 'L', 'H', 'A', 'U', 'X', '8', 0, | |
| /* 2342 */ 'S', 'T', 'B', 'U', 'X', '8', 0, | |
| /* 2349 */ 'S', 'T', 'H', 'U', 'X', '8', 0, | |
| /* 2356 */ 'S', 'T', 'W', 'U', 'X', '8', 0, | |
| /* 2363 */ 'L', 'B', 'Z', 'U', 'X', '8', 0, | |
| /* 2370 */ 'L', 'H', 'Z', 'U', 'X', '8', 0, | |
| /* 2377 */ 'L', 'W', 'Z', 'U', 'X', '8', 0, | |
| /* 2384 */ 'S', 'T', 'W', 'X', '8', 0, | |
| /* 2390 */ 'L', 'B', 'Z', 'X', '8', 0, | |
| /* 2396 */ 'L', 'H', 'Z', 'X', '8', 0, | |
| /* 2402 */ 'L', 'W', 'Z', 'X', '8', 0, | |
| /* 2408 */ 'C', 'P', '_', 'C', 'O', 'P', 'Y', '8', 0, | |
| /* 2417 */ 'L', 'B', 'Z', '8', 0, | |
| /* 2422 */ 'B', 'D', 'Z', '8', 0, | |
| /* 2427 */ 'L', 'H', 'Z', '8', 0, | |
| /* 2432 */ 'B', 'D', 'N', 'Z', '8', 0, | |
| /* 2438 */ 'L', 'W', 'Z', '8', 0, | |
| /* 2443 */ 'T', 'C', 'R', 'E', 'T', 'U', 'R', 'N', 'a', 'i', '8', 0, | |
| /* 2455 */ 'T', 'C', 'R', 'E', 'T', 'U', 'R', 'N', 'd', 'i', '8', 0, | |
| /* 2467 */ 'T', 'C', 'R', 'E', 'T', 'U', 'R', 'N', 'r', 'i', '8', 0, | |
| /* 2479 */ 'E', 'V', 'M', 'H', 'E', 'G', 'S', 'M', 'F', 'A', 'A', 0, | |
| /* 2491 */ 'E', 'V', 'M', 'H', 'O', 'G', 'S', 'M', 'F', 'A', 'A', 0, | |
| /* 2503 */ 'E', 'V', 'M', 'W', 'S', 'M', 'F', 'A', 'A', 0, | |
| /* 2513 */ 'E', 'V', 'M', 'W', 'S', 'S', 'F', 'A', 'A', 0, | |
| /* 2523 */ 'E', 'V', 'M', 'H', 'E', 'G', 'S', 'M', 'I', 'A', 'A', 0, | |
| /* 2535 */ 'E', 'V', 'M', 'H', 'O', 'G', 'S', 'M', 'I', 'A', 'A', 0, | |
| /* 2547 */ 'E', 'V', 'M', 'W', 'S', 'M', 'I', 'A', 'A', 0, | |
| /* 2557 */ 'E', 'V', 'M', 'H', 'E', 'G', 'U', 'M', 'I', 'A', 'A', 0, | |
| /* 2569 */ 'E', 'V', 'M', 'H', 'O', 'G', 'U', 'M', 'I', 'A', 'A', 0, | |
| /* 2581 */ 'E', 'V', 'M', 'W', 'U', 'M', 'I', 'A', 'A', 0, | |
| /* 2591 */ 'D', 'C', 'B', 'A', 0, | |
| /* 2596 */ 'T', 'A', 'I', 'L', 'B', 'A', 0, | |
| /* 2603 */ 'L', 'D', 't', 'o', 'c', 'B', 'A', 0, | |
| /* 2611 */ 'g', 'B', 'C', 'A', 0, | |
| /* 2616 */ 'B', 'C', 'C', 'A', 0, | |
| /* 2621 */ 'E', 'V', 'M', 'H', 'E', 'S', 'M', 'F', 'A', 0, | |
| /* 2631 */ 'E', 'V', 'M', 'W', 'H', 'S', 'M', 'F', 'A', 0, | |
| /* 2641 */ 'E', 'V', 'M', 'H', 'O', 'S', 'M', 'F', 'A', 0, | |
| /* 2651 */ 'E', 'V', 'M', 'W', 'S', 'M', 'F', 'A', 0, | |
| /* 2660 */ 'E', 'V', 'M', 'H', 'E', 'S', 'S', 'F', 'A', 0, | |
| /* 2670 */ 'E', 'V', 'M', 'W', 'H', 'S', 'S', 'F', 'A', 0, | |
| /* 2680 */ 'E', 'V', 'M', 'H', 'O', 'S', 'S', 'F', 'A', 0, | |
| /* 2690 */ 'E', 'V', 'M', 'W', 'S', 'S', 'F', 'A', 0, | |
| /* 2699 */ 'L', 'H', 'A', 0, | |
| /* 2703 */ 'A', 'D', 'D', 'I', 'S', 't', 'o', 'c', 'H', 'A', 0, | |
| /* 2714 */ 'A', 'D', 'D', 'I', 'S', 't', 'l', 's', 'g', 'd', 'H', 'A', 0, | |
| /* 2727 */ 'A', 'D', 'D', 'I', 'S', 't', 'l', 's', 'l', 'd', 'H', 'A', 0, | |
| /* 2740 */ 'A', 'D', 'D', 'I', 'S', 'g', 'o', 't', 'T', 'p', 'r', 'e', 'l', 'H', 'A', 0, | |
| /* 2756 */ 'A', 'D', 'D', 'I', 'S', 'd', 't', 'p', 'r', 'e', 'l', 'H', 'A', 0, | |
| /* 2770 */ 'S', 'L', 'B', 'I', 'A', 0, | |
| /* 2776 */ 'T', 'L', 'B', 'I', 'A', 0, | |
| /* 2782 */ 'E', 'V', 'M', 'H', 'E', 'S', 'M', 'I', 'A', 0, | |
| /* 2792 */ 'E', 'V', 'M', 'W', 'H', 'S', 'M', 'I', 'A', 0, | |
| /* 2802 */ 'E', 'V', 'M', 'H', 'O', 'S', 'M', 'I', 'A', 0, | |
| /* 2812 */ 'E', 'V', 'M', 'W', 'S', 'M', 'I', 'A', 0, | |
| /* 2821 */ 'E', 'V', 'M', 'H', 'E', 'U', 'M', 'I', 'A', 0, | |
| /* 2831 */ 'E', 'V', 'M', 'W', 'H', 'U', 'M', 'I', 'A', 0, | |
| /* 2841 */ 'E', 'V', 'M', 'W', 'L', 'U', 'M', 'I', 'A', 0, | |
| /* 2851 */ 'E', 'V', 'M', 'H', 'O', 'U', 'M', 'I', 'A', 0, | |
| /* 2861 */ 'E', 'V', 'M', 'W', 'U', 'M', 'I', 'A', 0, | |
| /* 2870 */ 'Q', 'V', 'S', 'T', 'F', 'C', 'D', 'X', 'I', 'A', 0, | |
| /* 2881 */ 'Q', 'V', 'S', 'T', 'F', 'D', 'X', 'I', 'A', 0, | |
| /* 2891 */ 'Q', 'V', 'S', 'T', 'F', 'C', 'S', 'X', 'I', 'A', 0, | |
| /* 2902 */ 'Q', 'V', 'S', 'T', 'F', 'S', 'X', 'I', 'A', 0, | |
| /* 2912 */ 'Q', 'V', 'S', 'T', 'F', 'C', 'D', 'U', 'X', 'I', 'A', 0, | |
| /* 2924 */ 'Q', 'V', 'S', 'T', 'F', 'D', 'U', 'X', 'I', 'A', 0, | |
| /* 2935 */ 'Q', 'V', 'S', 'T', 'F', 'C', 'S', 'U', 'X', 'I', 'A', 0, | |
| /* 2947 */ 'Q', 'V', 'S', 'T', 'F', 'S', 'U', 'X', 'I', 'A', 0, | |
| /* 2958 */ 'B', 'L', 'A', 0, | |
| /* 2962 */ 'g', 'B', 'C', 'L', 'A', 0, | |
| /* 2968 */ 'B', 'C', 'C', 'L', 'A', 0, | |
| /* 2974 */ 'B', 'D', 'Z', 'L', 'A', 0, | |
| /* 2980 */ 'B', 'D', 'N', 'Z', 'L', 'A', 0, | |
| /* 2987 */ 'G', '_', 'F', 'M', 'A', 0, | |
| /* 2993 */ 'E', 'V', 'M', 'R', 'A', 0, | |
| /* 2999 */ 'L', 'W', 'A', 0, | |
| /* 3003 */ 'M', 'T', 'V', 'S', 'R', 'W', 'A', 0, | |
| /* 3011 */ 'M', 'T', 'V', 'R', 'W', 'A', 0, | |
| /* 3018 */ 'Q', 'V', 'L', 'F', 'I', 'W', 'A', 'X', 'A', 0, | |
| /* 3028 */ 'Q', 'V', 'L', 'F', 'C', 'D', 'X', 'A', 0, | |
| /* 3037 */ 'Q', 'V', 'S', 'T', 'F', 'C', 'D', 'X', 'A', 0, | |
| /* 3047 */ 'Q', 'V', 'L', 'F', 'D', 'X', 'A', 0, | |
| /* 3055 */ 'Q', 'V', 'S', 'T', 'F', 'D', 'X', 'A', 0, | |
| /* 3064 */ 'Q', 'V', 'L', 'F', 'C', 'S', 'X', 'A', 0, | |
| /* 3073 */ 'Q', 'V', 'S', 'T', 'F', 'C', 'S', 'X', 'A', 0, | |
| /* 3083 */ 'Q', 'V', 'L', 'F', 'S', 'X', 'A', 0, | |
| /* 3091 */ 'Q', 'V', 'S', 'T', 'F', 'S', 'X', 'A', 0, | |
| /* 3100 */ 'Q', 'V', 'L', 'F', 'C', 'D', 'U', 'X', 'A', 0, | |
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| /* 5563 */ 'E', 'V', 'F', 'S', 'C', 'F', 'S', 'F', 0, | |
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| /* 5646 */ 'E', 'F', 'S', 'C', 'F', 'U', 'F', 0, | |
| /* 5654 */ 'E', 'V', 'F', 'S', 'C', 'F', 'U', 'F', 0, | |
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| /* 5679 */ 'E', 'V', 'F', 'S', 'C', 'T', 'U', 'F', 0, | |
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| /* 5973 */ 'V', 'S', 'P', 'L', 'T', 'I', 'S', 'H', 0, | |
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| /* 5990 */ 'V', 'M', 'I', 'N', 'S', 'H', 0, | |
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| /* 6005 */ 'V', 'C', 'M', 'P', 'G', 'T', 'S', 'H', 0, | |
| /* 6014 */ 'E', 'V', 'E', 'X', 'T', 'S', 'H', 0, | |
| /* 6022 */ 'V', 'M', 'A', 'X', 'S', 'H', 0, | |
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| /* 6045 */ 'V', 'I', 'N', 'S', 'E', 'R', 'T', 'H', 0, | |
| /* 6054 */ 'S', 'T', 'H', 0, | |
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| /* 6066 */ 'V', 'M', 'U', 'L', 'E', 'U', 'H', 0, | |
| /* 6074 */ 'V', 'A', 'V', 'G', 'U', 'H', 0, | |
| /* 6081 */ 'V', 'M', 'I', 'N', 'U', 'H', 0, | |
| /* 6088 */ 'V', 'M', 'U', 'L', 'O', 'U', 'H', 0, | |
| /* 6096 */ 'V', 'C', 'M', 'P', 'E', 'Q', 'U', 'H', 0, | |
| /* 6105 */ 'V', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 'U', 'H', 0, | |
| /* 6116 */ 'V', 'C', 'M', 'P', 'G', 'T', 'U', 'H', 0, | |
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| /* 6132 */ 'V', 'C', 'M', 'P', 'N', 'E', 'Z', 'H', 0, | |
| /* 6141 */ 'V', 'C', 'L', 'Z', 'H', 0, | |
| /* 6147 */ 'V', 'C', 'T', 'Z', 'H', 0, | |
| /* 6153 */ 'D', 'C', 'B', 'I', 0, | |
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| /* 6163 */ 'S', 'U', 'B', 'I', 0, | |
| /* 6168 */ 'D', 'C', 'C', 'C', 'I', 0, | |
| /* 6174 */ 'I', 'C', 'C', 'C', 'I', 0, | |
| /* 6180 */ 'T', 'A', 'B', 'O', 'R', 'T', 'D', 'C', 'I', 0, | |
| /* 6190 */ 'R', 'F', 'C', 'I', 0, | |
| /* 6195 */ 'R', 'F', 'M', 'C', 'I', 0, | |
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| /* 6218 */ 'S', 'R', 'A', 'D', 'I', 0, | |
| /* 6224 */ 'A', 'D', 'D', 'I', 0, | |
| /* 6229 */ 'R', 'F', 'D', 'I', 0, | |
| /* 6234 */ 'C', 'M', 'P', 'L', 'D', 'I', 0, | |
| /* 6241 */ 'C', 'L', 'R', 'L', 'S', 'L', 'D', 'I', 0, | |
| /* 6250 */ 'E', 'X', 'T', 'L', 'D', 'I', 0, | |
| /* 6257 */ 'X', 'X', 'P', 'E', 'R', 'M', 'D', 'I', 0, | |
| /* 6266 */ 'C', 'M', 'P', 'D', 'I', 0, | |
| /* 6272 */ 'C', 'L', 'R', 'R', 'D', 'I', 0, | |
| /* 6279 */ 'I', 'N', 'S', 'R', 'D', 'I', 0, | |
| /* 6286 */ 'R', 'O', 'T', 'R', 'D', 'I', 0, | |
| /* 6293 */ 'E', 'X', 'T', 'R', 'D', 'I', 0, | |
| /* 6300 */ 'T', 'D', 'I', 0, | |
| /* 6304 */ 'W', 'R', 'T', 'E', 'E', 'I', 0, | |
| /* 6311 */ 'R', 'F', 'I', 0, | |
| /* 6315 */ 'M', 'T', 'F', 'S', 'F', 'I', 0, | |
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| /* 6332 */ 'E', 'V', 'M', 'E', 'R', 'G', 'E', 'H', 'I', 0, | |
| /* 6342 */ 'E', 'V', 'M', 'E', 'R', 'G', 'E', 'L', 'O', 'H', 'I', 0, | |
| /* 6354 */ 'G', '_', 'P', 'H', 'I', 0, | |
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| /* 6402 */ 'E', 'V', 'M', 'H', 'E', 'S', 'M', 'I', 0, | |
| /* 6411 */ 'E', 'V', 'M', 'W', 'H', 'S', 'M', 'I', 0, | |
| /* 6420 */ 'E', 'V', 'M', 'H', 'O', 'S', 'M', 'I', 0, | |
| /* 6429 */ 'E', 'V', 'M', 'W', 'S', 'M', 'I', 0, | |
| /* 6437 */ 'E', 'V', 'M', 'H', 'E', 'U', 'M', 'I', 0, | |
| /* 6446 */ 'E', 'V', 'M', 'W', 'H', 'U', 'M', 'I', 0, | |
| /* 6455 */ 'E', 'V', 'M', 'W', 'L', 'U', 'M', 'I', 0, | |
| /* 6464 */ 'E', 'V', 'M', 'H', 'O', 'U', 'M', 'I', 0, | |
| /* 6473 */ 'E', 'V', 'M', 'W', 'U', 'M', 'I', 0, | |
| /* 6481 */ 'V', 'R', 'L', 'W', 'M', 'I', 0, | |
| /* 6488 */ 'Q', 'V', 'A', 'L', 'I', 'G', 'N', 'I', 0, | |
| /* 6497 */ 'M', 'F', 'F', 'S', 'C', 'R', 'N', 'I', 0, | |
| /* 6506 */ 'M', 'F', 'F', 'S', 'C', 'D', 'R', 'N', 'I', 0, | |
| /* 6516 */ 'V', 'S', 'L', 'D', 'O', 'I', 0, | |
| /* 6523 */ 'X', 'S', 'R', 'D', 'P', 'I', 0, | |
| /* 6530 */ 'X', 'V', 'R', 'D', 'P', 'I', 0, | |
| /* 6537 */ 'X', 'S', 'R', 'Q', 'P', 'I', 0, | |
| /* 6544 */ 'X', 'V', 'R', 'S', 'P', 'I', 0, | |
| /* 6551 */ 'X', 'O', 'R', 'I', 0, | |
| /* 6556 */ 'E', 'F', 'D', 'C', 'F', 'S', 'I', 0, | |
| /* 6564 */ 'E', 'F', 'S', 'C', 'F', 'S', 'I', 0, | |
| /* 6572 */ 'E', 'V', 'F', 'S', 'C', 'F', 'S', 'I', 0, | |
| /* 6581 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0, | |
| /* 6590 */ 'E', 'F', 'D', 'C', 'T', 'S', 'I', 0, | |
| /* 6598 */ 'E', 'F', 'S', 'C', 'T', 'S', 'I', 0, | |
| /* 6606 */ 'E', 'V', 'F', 'S', 'C', 'T', 'S', 'I', 0, | |
| /* 6615 */ 'Q', 'V', 'E', 'S', 'P', 'L', 'A', 'T', 'I', 0, | |
| /* 6625 */ 'E', 'V', 'S', 'P', 'L', 'A', 'T', 'I', 0, | |
| /* 6634 */ 'L', 'D', 't', 'o', 'c', 'J', 'T', 'I', 0, | |
| /* 6643 */ 'E', 'F', 'D', 'C', 'F', 'U', 'I', 0, | |
| /* 6651 */ 'E', 'F', 'S', 'C', 'F', 'U', 'I', 0, | |
| /* 6659 */ 'E', 'V', 'F', 'S', 'C', 'F', 'U', 'I', 0, | |
| /* 6668 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0, | |
| /* 6677 */ 'E', 'F', 'D', 'C', 'T', 'U', 'I', 0, | |
| /* 6685 */ 'E', 'F', 'S', 'C', 'T', 'U', 'I', 0, | |
| /* 6693 */ 'E', 'V', 'F', 'S', 'C', 'T', 'U', 'I', 0, | |
| /* 6702 */ 'S', 'R', 'A', 'W', 'I', 0, | |
| /* 6708 */ 'X', 'X', 'S', 'L', 'D', 'W', 'I', 0, | |
| /* 6716 */ 'C', 'M', 'P', 'L', 'W', 'I', 0, | |
| /* 6723 */ 'E', 'V', 'R', 'L', 'W', 'I', 0, | |
| /* 6730 */ 'C', 'L', 'R', 'L', 'S', 'L', 'W', 'I', 0, | |
| /* 6739 */ 'I', 'N', 'S', 'L', 'W', 'I', 0, | |
| /* 6746 */ 'E', 'V', 'S', 'L', 'W', 'I', 0, | |
| /* 6753 */ 'E', 'X', 'T', 'L', 'W', 'I', 0, | |
| /* 6760 */ 'C', 'M', 'P', 'W', 'I', 0, | |
| /* 6766 */ 'C', 'L', 'R', 'R', 'W', 'I', 0, | |
| /* 6773 */ 'I', 'N', 'S', 'R', 'W', 'I', 0, | |
| /* 6780 */ 'R', 'O', 'T', 'R', 'W', 'I', 0, | |
| /* 6787 */ 'E', 'X', 'T', 'R', 'W', 'I', 0, | |
| /* 6794 */ 'L', 'S', 'W', 'I', 0, | |
| /* 6799 */ 'S', 'T', 'S', 'W', 'I', 0, | |
| /* 6805 */ 'T', 'W', 'I', 0, | |
| /* 6809 */ 'Q', 'V', 'S', 'T', 'F', 'C', 'D', 'X', 'I', 0, | |
| /* 6819 */ 'Q', 'V', 'S', 'T', 'F', 'D', 'X', 'I', 0, | |
| /* 6828 */ 'Q', 'V', 'S', 'T', 'F', 'C', 'S', 'X', 'I', 0, | |
| /* 6838 */ 'Q', 'V', 'S', 'T', 'F', 'S', 'X', 'I', 0, | |
| /* 6847 */ 'Q', 'V', 'S', 'T', 'F', 'C', 'D', 'U', 'X', 'I', 0, | |
| /* 6858 */ 'Q', 'V', 'S', 'T', 'F', 'D', 'U', 'X', 'I', 0, | |
| /* 6868 */ 'Q', 'V', 'S', 'T', 'F', 'C', 'S', 'U', 'X', 'I', 0, | |
| /* 6879 */ 'Q', 'V', 'S', 'T', 'F', 'S', 'U', 'X', 'I', 0, | |
| /* 6889 */ 'T', 'C', 'H', 'E', 'C', 'K', 0, | |
| /* 6896 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0, | |
| /* 6907 */ 'Q', 'V', 'F', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 0, | |
| /* 6918 */ 'B', 'L', 0, | |
| /* 6921 */ 'g', 'B', 'C', 'L', 0, | |
| /* 6926 */ 'B', 'C', 'C', 'L', 0, | |
| /* 6931 */ 'R', 'L', 'D', 'C', 'L', 0, | |
| /* 6937 */ 'R', 'L', 'D', 'I', 'C', 'L', 0, | |
| /* 6944 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0, | |
| /* 6953 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, | |
| /* 6963 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0, | |
| /* 6972 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0, | |
| /* 6989 */ 'T', 'L', 'B', 'I', 'E', 'L', 0, | |
| /* 6996 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0, | |
| /* 7016 */ 'Q', 'V', 'F', 'S', 'E', 'L', 0, | |
| /* 7023 */ 'I', 'S', 'E', 'L', 0, | |
| /* 7028 */ 'E', 'V', 'S', 'E', 'L', 0, | |
| /* 7034 */ 'X', 'X', 'S', 'E', 'L', 0, | |
| /* 7040 */ 'D', 'C', 'B', 'F', 'L', 0, | |
| /* 7046 */ 'G', '_', 'S', 'H', 'L', 0, | |
| /* 7052 */ 'G', '_', 'F', 'C', 'E', 'I', 'L', 0, | |
| /* 7060 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0, | |
| /* 7080 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0, | |
| /* 7107 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0, | |
| /* 7128 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0, | |
| /* 7140 */ 'D', 'S', 'S', 'A', 'L', 'L', 0, | |
| /* 7147 */ 'K', 'I', 'L', 'L', 0, | |
| /* 7152 */ 'L', 'X', 'V', 'L', 'L', 0, | |
| /* 7158 */ 'S', 'T', 'X', 'V', 'L', 'L', 0, | |
| /* 7165 */ 'B', 'L', 'R', 'L', 0, | |
| /* 7170 */ 'g', 'B', 'C', 'L', 'R', 'L', 0, | |
| /* 7177 */ 'B', 'C', 'C', 'L', 'R', 'L', 0, | |
| /* 7184 */ 'B', 'D', 'Z', 'L', 'R', 'L', 0, | |
| /* 7191 */ 'B', 'D', 'N', 'Z', 'L', 'R', 'L', 0, | |
| /* 7199 */ 'B', 'C', 'T', 'R', 'L', 0, | |
| /* 7205 */ 'g', 'B', 'C', 'C', 'T', 'R', 'L', 0, | |
| /* 7213 */ 'B', 'C', 'C', 'C', 'T', 'R', 'L', 0, | |
| /* 7221 */ 'M', 'F', 'F', 'S', 'L', 0, | |
| /* 7227 */ 'L', 'V', 'S', 'L', 0, | |
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| /* 10455 */ 'I', 'C', 'B', 'L', 'Q', 0, | |
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| /* 10469 */ 'X', 'X', 'B', 'R', 'Q', 0, | |
| /* 10475 */ 'V', 'M', 'U', 'L', '1', '0', 'U', 'Q', 0, | |
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| /* 10502 */ 'V', 'A', 'D', 'D', 'C', 'U', 'Q', 0, | |
| /* 10510 */ 'V', 'M', 'U', 'L', '1', '0', 'E', 'C', 'U', 'Q', 0, | |
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| /* 10530 */ 'V', 'A', 'D', 'D', 'E', 'C', 'U', 'Q', 0, | |
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| /* 10549 */ 'M', 'B', 'A', 'R', 0, | |
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| /* 10564 */ 'G', '_', 'B', 'R', 0, | |
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| /* 10582 */ 'M', 'F', 'D', 'C', 'R', 0, | |
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| /* 10605 */ 'R', 'L', 'D', 'I', 'C', 'R', 0, | |
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| /* 10637 */ 'S', 'P', 'I', 'L', 'L', '_', 'C', 'R', 0, | |
| /* 10646 */ 'A', 'D', 'D', 'I', 't', 'l', 's', 'g', 'd', 'L', 'A', 'D', 'D', 'R', 0, | |
| /* 10661 */ 'A', 'D', 'D', 'I', 't', 'l', 's', 'l', 'd', 'L', 'A', 'D', 'D', 'R', 0, | |
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| /* 10689 */ 'G', 'E', 'T', 't', 'l', 's', 'l', 'd', 'A', 'D', 'D', 'R', 0, | |
| /* 10702 */ 'G', 'E', 'T', 't', 'l', 's', 'A', 'D', 'D', 'R', 0, | |
| /* 10713 */ 'V', 'N', 'C', 'I', 'P', 'H', 'E', 'R', 0, | |
| /* 10722 */ 'V', 'C', 'I', 'P', 'H', 'E', 'R', 0, | |
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| /* 10755 */ 'G', '_', 'R', 'E', 'A', 'D', 'C', 'Y', 'C', 'L', 'E', 'C', 'O', 'U', 'N', 'T', 'E', 'R', 0, | |
| /* 10774 */ 'G', '_', 'R', 'E', 'A', 'D', '_', 'R', 'E', 'G', 'I', 'S', 'T', 'E', 'R', 0, | |
| /* 10790 */ 'G', '_', 'W', 'R', 'I', 'T', 'E', '_', 'R', 'E', 'G', 'I', 'S', 'T', 'E', 'R', 0, | |
| /* 10807 */ 'G', '_', 'A', 'S', 'H', 'R', 0, | |
| /* 10814 */ 'G', '_', 'L', 'S', 'H', 'R', 0, | |
| /* 10821 */ 'B', 'L', 'R', 0, | |
| /* 10825 */ 'g', 'B', 'C', 'L', 'R', 0, | |
| /* 10831 */ 'B', 'C', 'C', 'L', 'R', 0, | |
| /* 10837 */ 'M', 'F', 'L', 'R', 0, | |
| /* 10842 */ 'M', 'T', 'L', 'R', 0, | |
| /* 10847 */ 'B', 'D', 'Z', 'L', 'R', 0, | |
| /* 10853 */ 'B', 'D', 'N', 'Z', 'L', 'R', 0, | |
| /* 10860 */ 'M', 'o', 'v', 'e', 'P', 'C', 't', 'o', 'L', 'R', 0, | |
| /* 10871 */ 'M', 'o', 'v', 'e', 'G', 'O', 'T', 't', 'o', 'L', 'R', 0, | |
| /* 10883 */ 'Q', 'V', 'F', 'M', 'R', 0, | |
| /* 10889 */ 'M', 'F', 'P', 'M', 'R', 0, | |
| /* 10895 */ 'M', 'T', 'P', 'M', 'R', 0, | |
| /* 10901 */ 'V', 'P', 'E', 'R', 'M', 'R', 0, | |
| /* 10908 */ 'X', 'X', 'P', 'E', 'R', 'M', 'R', 0, | |
| /* 10916 */ 'X', 'X', 'L', 'O', 'R', 0, | |
| /* 10922 */ 'X', 'X', 'L', 'N', 'O', 'R', 0, | |
| /* 10929 */ 'C', 'R', 'N', 'O', 'R', 0, | |
| /* 10935 */ 'E', 'V', 'N', 'O', 'R', 0, | |
| /* 10941 */ 'G', '_', 'F', 'F', 'L', 'O', 'O', 'R', 0, | |
| /* 10950 */ 'C', 'R', 'O', 'R', 0, | |
| /* 10955 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0, | |
| /* 10970 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0, | |
| /* 10987 */ 'E', 'V', 'O', 'R', 0, | |
| /* 10992 */ 'X', 'X', 'L', 'X', 'O', 'R', 0, | |
| /* 10999 */ 'V', 'P', 'E', 'R', 'M', 'X', 'O', 'R', 0, | |
| /* 11008 */ 'C', 'R', 'X', 'O', 'R', 0, | |
| /* 11014 */ 'E', 'V', 'X', 'O', 'R', 0, | |
| /* 11020 */ 'G', '_', 'X', 'O', 'R', 0, | |
| /* 11026 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0, | |
| /* 11042 */ 'G', '_', 'O', 'R', 0, | |
| /* 11047 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0, | |
| /* 11062 */ 'M', 'F', 'S', 'P', 'R', 0, | |
| /* 11068 */ 'M', 'T', 'S', 'P', 'R', 0, | |
| /* 11074 */ 'M', 'F', 'S', 'R', 0, | |
| /* 11079 */ 'M', 'F', 'M', 'S', 'R', 0, | |
| /* 11085 */ 'M', 'T', 'M', 'S', 'R', 0, | |
| /* 11091 */ 'M', 'T', 'S', 'R', 0, | |
| /* 11096 */ 'L', 'V', 'S', 'R', 0, | |
| /* 11101 */ 'T', 'A', 'I', 'L', 'B', 'C', 'T', 'R', 0, | |
| /* 11110 */ 'g', 'B', 'C', 'C', 'T', 'R', 0, | |
| /* 11117 */ 'B', 'C', 'C', 'C', 'T', 'R', 0, | |
| /* 11124 */ 'M', 'F', 'C', 'T', 'R', 0, | |
| /* 11130 */ 'M', 'T', 'C', 'T', 'R', 0, | |
| /* 11136 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0, | |
| /* 11147 */ 'E', 'F', 'D', 'A', 'B', 'S', 0, | |
| /* 11154 */ 'Q', 'V', 'F', 'A', 'B', 'S', 0, | |
| /* 11161 */ 'G', '_', 'F', 'A', 'B', 'S', 0, | |
| /* 11168 */ 'E', 'F', 'D', 'N', 'A', 'B', 'S', 0, | |
| /* 11176 */ 'Q', 'V', 'F', 'N', 'A', 'B', 'S', 0, | |
| /* 11184 */ 'E', 'F', 'S', 'N', 'A', 'B', 'S', 0, | |
| /* 11192 */ 'E', 'V', 'F', 'S', 'N', 'A', 'B', 'S', 0, | |
| /* 11201 */ 'E', 'F', 'S', 'A', 'B', 'S', 0, | |
| /* 11208 */ 'E', 'V', 'F', 'S', 'A', 'B', 'S', 0, | |
| /* 11216 */ 'E', 'V', 'A', 'B', 'S', 0, | |
| /* 11222 */ 'V', 'S', 'U', 'M', '4', 'S', 'B', 'S', 0, | |
| /* 11231 */ 'V', 'S', 'U', 'B', 'S', 'B', 'S', 0, | |
| /* 11239 */ 'V', 'A', 'D', 'D', 'S', 'B', 'S', 0, | |
| /* 11247 */ 'V', 'S', 'U', 'M', '4', 'U', 'B', 'S', 0, | |
| /* 11256 */ 'V', 'S', 'U', 'B', 'U', 'B', 'S', 0, | |
| /* 11264 */ 'V', 'A', 'D', 'D', 'U', 'B', 'S', 0, | |
| /* 11272 */ 'Q', 'V', 'F', 'S', 'U', 'B', 'S', 0, | |
| /* 11280 */ 'Q', 'V', 'F', 'M', 'S', 'U', 'B', 'S', 0, | |
| /* 11289 */ 'Q', 'V', 'F', 'N', 'M', 'S', 'U', 'B', 'S', 0, | |
| /* 11299 */ 'Q', 'V', 'F', 'A', 'D', 'D', 'S', 0, | |
| /* 11307 */ 'Q', 'V', 'F', 'M', 'A', 'D', 'D', 'S', 0, | |
| /* 11316 */ 'Q', 'V', 'F', 'N', 'M', 'A', 'D', 'D', 'S', 0, | |
| /* 11326 */ 'Q', 'V', 'F', 'X', 'X', 'C', 'P', 'N', 'M', 'A', 'D', 'D', 'S', 0, | |
| /* 11340 */ 'Q', 'V', 'F', 'X', 'X', 'N', 'P', 'M', 'A', 'D', 'D', 'S', 0, | |
| /* 11353 */ 'Q', 'V', 'F', 'X', 'M', 'A', 'D', 'D', 'S', 0, | |
| /* 11363 */ 'Q', 'V', 'F', 'X', 'X', 'M', 'A', 'D', 'D', 'S', 0, | |
| /* 11374 */ 'Q', 'V', 'F', 'C', 'F', 'I', 'D', 'S', 0, | |
| /* 11383 */ 'D', 'C', 'B', 'T', 'D', 'S', 0, | |
| /* 11390 */ 'D', 'C', 'B', 'T', 'S', 'T', 'D', 'S', 0, | |
| /* 11399 */ 'X', 'S', 'C', 'V', 'D', 'P', 'S', 'X', 'D', 'S', 0, | |
| /* 11410 */ 'X', 'V', 'C', 'V', 'D', 'P', 'S', 'X', 'D', 'S', 0, | |
| /* 11421 */ 'X', 'V', 'C', 'V', 'S', 'P', 'S', 'X', 'D', 'S', 0, | |
| /* 11432 */ 'X', 'S', 'C', 'V', 'D', 'P', 'U', 'X', 'D', 'S', 0, | |
| /* 11443 */ 'X', 'V', 'C', 'V', 'D', 'P', 'U', 'X', 'D', 'S', 0, | |
| /* 11454 */ 'X', 'V', 'C', 'V', 'S', 'P', 'U', 'X', 'D', 'S', 0, | |
| /* 11465 */ 'V', '_', 'S', 'E', 'T', 'A', 'L', 'L', 'O', 'N', 'E', 'S', 0, | |
| /* 11478 */ 'Q', 'V', 'F', 'R', 'E', 'S', 0, | |
| /* 11485 */ 'Q', 'V', 'F', 'R', 'S', 'Q', 'R', 'T', 'E', 'S', 0, | |
| /* 11496 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0, | |
| /* 11513 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0, | |
| /* 11528 */ 'E', 'F', 'D', 'C', 'F', 'S', 0, | |
| /* 11535 */ 'M', 'F', 'F', 'S', 0, | |
| /* 11540 */ 'L', 'F', 'S', 0, | |
| /* 11544 */ 'M', 'C', 'R', 'F', 'S', 0, | |
| /* 11550 */ 'S', 'T', 'F', 'S', 0, | |
| /* 11555 */ 'F', 'N', 'E', 'G', 'S', 0, | |
| /* 11561 */ 'V', 'S', 'U', 'M', '4', 'S', 'H', 'S', 0, | |
| /* 11570 */ 'V', 'S', 'U', 'B', 'S', 'H', 'S', 0, | |
| /* 11578 */ 'V', 'M', 'H', 'A', 'D', 'D', 'S', 'H', 'S', 0, | |
| /* 11588 */ 'V', 'M', 'H', 'R', 'A', 'D', 'D', 'S', 'H', 'S', 0, | |
| /* 11599 */ 'V', 'A', 'D', 'D', 'S', 'H', 'S', 0, | |
| /* 11607 */ 'V', 'M', 'S', 'U', 'M', 'S', 'H', 'S', 0, | |
| /* 11616 */ 'V', 'S', 'U', 'B', 'U', 'H', 'S', 0, | |
| /* 11624 */ 'V', 'A', 'D', 'D', 'U', 'H', 'S', 0, | |
| /* 11632 */ 'V', 'M', 'S', 'U', 'M', 'U', 'H', 'S', 0, | |
| /* 11641 */ 'S', 'U', 'B', 'I', 'S', 0, | |
| /* 11647 */ 'S', 'U', 'B', 'P', 'C', 'I', 'S', 0, | |
| /* 11655 */ 'A', 'D', 'D', 'P', 'C', 'I', 'S', 0, | |
| /* 11663 */ 'A', 'D', 'D', 'I', 'S', 0, | |
| /* 11669 */ 'L', 'I', 'S', 0, | |
| /* 11673 */ 'X', 'O', 'R', 'I', 'S', 0, | |
| /* 11679 */ 'E', 'V', 'S', 'R', 'W', 'I', 'S', 0, | |
| /* 11687 */ 'F', 'S', 'E', 'L', 'S', 0, | |
| /* 11693 */ 'A', 'D', 'D', '4', 'T', 'L', 'S', 0, | |
| /* 11701 */ 'A', 'D', 'D', '8', 'T', 'L', 'S', 0, | |
| /* 11709 */ 'I', 'C', 'B', 'T', 'L', 'S', 0, | |
| /* 11716 */ 'S', 'T', 'B', 'X', 'T', 'L', 'S', 0, | |
| /* 11724 */ 'L', 'D', 'X', 'T', 'L', 'S', 0, | |
| /* 11731 */ 'S', 'T', 'D', 'X', 'T', 'L', 'S', 0, | |
| /* 11739 */ 'S', 'T', 'H', 'X', 'T', 'L', 'S', 0, | |
| /* 11747 */ 'S', 'T', 'W', 'X', 'T', 'L', 'S', 0, | |
| /* 11755 */ 'L', 'B', 'Z', 'X', 'T', 'L', 'S', 0, | |
| /* 11763 */ 'L', 'H', 'Z', 'X', 'T', 'L', 'S', 0, | |
| /* 11771 */ 'L', 'W', 'Z', 'X', 'T', 'L', 'S', 0, | |
| /* 11779 */ 'B', 'L', '8', '_', 'T', 'L', 'S', 0, | |
| /* 11787 */ 'B', 'L', '_', 'T', 'L', 'S', 0, | |
| /* 11794 */ 'B', 'L', '8', '_', 'N', 'O', 'P', '_', 'T', 'L', 'S', 0, | |
| /* 11806 */ 'Q', 'V', 'F', 'M', 'U', 'L', 'S', 0, | |
| /* 11814 */ 'Q', 'V', 'F', 'X', 'M', 'U', 'L', 'S', 0, | |
| /* 11823 */ 'F', 'R', 'I', 'M', 'S', 0, | |
| /* 11829 */ 'F', 'C', 'P', 'S', 'G', 'N', 'S', 0, | |
| /* 11837 */ 'F', 'R', 'I', 'N', 'S', 0, | |
| /* 11843 */ 'G', '_', 'F', 'C', 'O', 'S', 0, | |
| /* 11850 */ 'E', 'V', 'L', 'W', 'H', 'O', 'S', 0, | |
| /* 11858 */ 'F', 'R', 'I', 'P', 'S', 0, | |
| /* 11864 */ 'G', '_', 'C', 'O', 'N', 'C', 'A', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', 'S', 0, | |
| /* 11881 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0, | |
| /* 11898 */ 'F', 'A', 'B', 'S', 'S', 0, | |
| /* 11904 */ 'F', 'N', 'A', 'B', 'S', 'S', 0, | |
| /* 11911 */ 'V', 'P', 'K', 'S', 'D', 'S', 'S', 0, | |
| /* 11919 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0, | |
| /* 11949 */ 'V', 'P', 'K', 'S', 'H', 'S', 'S', 0, | |
| /* 11957 */ 'V', 'P', 'K', 'S', 'W', 'S', 'S', 0, | |
| /* 11965 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0, | |
| /* 11992 */ 'E', 'V', 'C', 'M', 'P', 'G', 'T', 'S', 0, | |
| /* 12001 */ 'E', 'V', 'C', 'M', 'P', 'L', 'T', 'S', 0, | |
| /* 12010 */ 'F', 'S', 'Q', 'R', 'T', 'S', 0, | |
| /* 12017 */ 'Q', 'V', 'F', 'C', 'F', 'I', 'D', 'U', 'S', 0, | |
| /* 12027 */ 'V', 'P', 'K', 'S', 'D', 'U', 'S', 0, | |
| /* 12035 */ 'V', 'P', 'K', 'U', 'D', 'U', 'S', 0, | |
| /* 12043 */ 'V', 'P', 'K', 'S', 'H', 'U', 'S', 0, | |
| /* 12051 */ 'V', 'P', 'K', 'U', 'H', 'U', 'S', 0, | |
| /* 12059 */ 'F', 'C', 'M', 'P', 'U', 'S', 0, | |
| /* 12066 */ 'V', 'P', 'K', 'S', 'W', 'U', 'S', 0, | |
| /* 12074 */ 'V', 'P', 'K', 'U', 'W', 'U', 'S', 0, | |
| /* 12082 */ 'F', 'D', 'I', 'V', 'S', 0, | |
| /* 12088 */ 'E', 'V', 'S', 'R', 'W', 'S', 0, | |
| /* 12095 */ 'M', 'T', 'V', 'S', 'R', 'W', 'S', 0, | |
| /* 12103 */ 'V', 'S', 'U', 'M', '2', 'S', 'W', 'S', 0, | |
| /* 12112 */ 'V', 'S', 'U', 'B', 'S', 'W', 'S', 0, | |
| /* 12120 */ 'V', 'A', 'D', 'D', 'S', 'W', 'S', 0, | |
| /* 12128 */ 'V', 'S', 'U', 'M', 'S', 'W', 'S', 0, | |
| /* 12136 */ 'V', 'S', 'U', 'B', 'U', 'W', 'S', 0, | |
| /* 12144 */ 'V', 'A', 'D', 'D', 'U', 'W', 'S', 0, | |
| /* 12152 */ 'E', 'V', 'D', 'I', 'V', 'W', 'S', 0, | |
| /* 12160 */ 'X', 'S', 'C', 'V', 'D', 'P', 'S', 'X', 'W', 'S', 0, | |
| /* 12171 */ 'X', 'V', 'C', 'V', 'D', 'P', 'S', 'X', 'W', 'S', 0, | |
| /* 12182 */ 'X', 'V', 'C', 'V', 'S', 'P', 'S', 'X', 'W', 'S', 0, | |
| /* 12193 */ 'X', 'S', 'C', 'V', 'D', 'P', 'U', 'X', 'W', 'S', 0, | |
| /* 12204 */ 'X', 'V', 'C', 'V', 'D', 'P', 'U', 'X', 'W', 'S', 0, | |
| /* 12215 */ 'X', 'V', 'C', 'V', 'S', 'P', 'U', 'X', 'W', 'S', 0, | |
| /* 12226 */ 'V', 'C', 'T', 'S', 'X', 'S', 0, | |
| /* 12233 */ 'V', 'C', 'T', 'U', 'X', 'S', 0, | |
| /* 12240 */ 'F', 'R', 'I', 'Z', 'S', 0, | |
| /* 12246 */ 'L', 'D', 'A', 'T', 0, | |
| /* 12251 */ 'S', 'T', 'D', 'A', 'T', 0, | |
| /* 12257 */ 'E', 'V', 'L', 'H', 'H', 'E', 'S', 'P', 'L', 'A', 'T', 0, | |
| /* 12269 */ 'E', 'V', 'L', 'W', 'H', 'S', 'P', 'L', 'A', 'T', 0, | |
| /* 12280 */ 'E', 'V', 'L', 'H', 'H', 'O', 'S', 'S', 'P', 'L', 'A', 'T', 0, | |
| /* 12293 */ 'E', 'V', 'L', 'H', 'H', 'O', 'U', 'S', 'P', 'L', 'A', 'T', 0, | |
| /* 12306 */ 'E', 'V', 'L', 'W', 'W', 'S', 'P', 'L', 'A', 'T', 0, | |
| /* 12317 */ 'L', 'W', 'A', 'T', 0, | |
| /* 12322 */ 'S', 'T', 'W', 'A', 'T', 0, | |
| /* 12328 */ 'D', 'C', 'B', 'T', 0, | |
| /* 12333 */ 'I', 'C', 'B', 'T', 0, | |
| /* 12338 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0, | |
| /* 12348 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0, | |
| /* 12357 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0, | |
| /* 12370 */ 'D', 'C', 'B', 'T', 'C', 'T', 0, | |
| /* 12377 */ 'D', 'C', 'B', 'T', 'S', 'T', 'C', 'T', 0, | |
| /* 12386 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0, | |
| /* 12400 */ 'T', 'C', 'H', 'E', 'C', 'K', '_', 'R', 'E', 'T', 0, | |
| /* 12411 */ 'T', 'B', 'E', 'G', 'I', 'N', '_', 'R', 'E', 'T', 0, | |
| /* 12422 */ 'C', 'R', '6', 'S', 'E', 'T', 0, | |
| /* 12429 */ 'D', 'Y', 'N', 'A', 'R', 'E', 'A', 'O', 'F', 'F', 'S', 'E', 'T', 0, | |
| /* 12443 */ 'C', 'R', '6', 'U', 'N', 'S', 'E', 'T', 0, | |
| /* 12452 */ 'C', 'R', 'U', 'N', 'S', 'E', 'T', 0, | |
| /* 12460 */ 'C', 'R', 'S', 'E', 'T', 0, | |
| /* 12466 */ 'E', 'F', 'D', 'C', 'M', 'P', 'G', 'T', 0, | |
| /* 12475 */ 'Q', 'V', 'F', 'C', 'M', 'P', 'G', 'T', 0, | |
| /* 12484 */ 'E', 'F', 'S', 'C', 'M', 'P', 'G', 'T', 0, | |
| /* 12493 */ 'E', 'V', 'F', 'S', 'C', 'M', 'P', 'G', 'T', 0, | |
| /* 12503 */ 'E', 'F', 'D', 'T', 'S', 'T', 'G', 'T', 0, | |
| /* 12512 */ 'E', 'F', 'S', 'T', 'S', 'T', 'G', 'T', 0, | |
| /* 12521 */ 'E', 'V', 'F', 'S', 'T', 'S', 'T', 'G', 'T', 0, | |
| /* 12531 */ 'W', 'A', 'I', 'T', 0, | |
| /* 12536 */ 'R', 'E', 'S', 'T', 'O', 'R', 'E', '_', 'C', 'R', 'B', 'I', 'T', 0, | |
| /* 12550 */ 'S', 'P', 'I', 'L', 'L', '_', 'C', 'R', 'B', 'I', 'T', 0, | |
| /* 12562 */ 'A', 'N', 'D', 'I', '_', 'r', 'e', 'c', '_', '1', '_', 'E', 'Q', '_', 'B', 'I', 'T', 0, | |
| /* 12580 */ 'A', 'N', 'D', 'I', '_', 'r', 'e', 'c', '_', '1', '_', 'G', 'T', '_', 'B', 'I', 'T', 0, | |
| /* 12598 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0, | |
| /* 12622 */ 'G', '_', 'B', 'R', 'J', 'T', 0, | |
| /* 12629 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0, | |
| /* 12650 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0, | |
| /* 12670 */ 'E', 'F', 'D', 'C', 'M', 'P', 'L', 'T', 0, | |
| /* 12679 */ 'Q', 'V', 'F', 'C', 'M', 'P', 'L', 'T', 0, | |
| /* 12688 */ 'E', 'F', 'S', 'C', 'M', 'P', 'L', 'T', 0, | |
| /* 12697 */ 'E', 'V', 'F', 'S', 'C', 'M', 'P', 'L', 'T', 0, | |
| /* 12707 */ 'E', 'F', 'D', 'T', 'S', 'T', 'L', 'T', 0, | |
| /* 12716 */ 'E', 'F', 'S', 'T', 'S', 'T', 'L', 'T', 0, | |
| /* 12725 */ 'E', 'V', 'F', 'S', 'T', 'S', 'T', 'L', 'T', 0, | |
| /* 12735 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0, | |
| /* 12747 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0, | |
| /* 12758 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0, | |
| /* 12769 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0, | |
| /* 12780 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0, | |
| /* 12791 */ 'G', '_', 'F', 'R', 'I', 'N', 'T', 0, | |
| /* 12799 */ 'G', '_', 'F', 'N', 'E', 'A', 'R', 'B', 'Y', 'I', 'N', 'T', 0, | |
| /* 12812 */ 'P', 'P', 'C', '3', '2', 'G', 'O', 'T', 0, | |
| /* 12821 */ 'P', 'P', 'C', '3', '2', 'P', 'I', 'C', 'G', 'O', 'T', 0, | |
| /* 12833 */ 'L', 'D', 't', 'o', 'c', 'C', 'P', 'T', 0, | |
| /* 12842 */ 'T', 'R', 'E', 'C', 'H', 'K', 'P', 'T', 0, | |
| /* 12851 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0, | |
| /* 12861 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, | |
| /* 12876 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0, | |
| /* 12885 */ 'T', 'A', 'B', 'O', 'R', 'T', 0, | |
| /* 12892 */ 'C', 'P', '_', 'A', 'B', 'O', 'R', 'T', 0, | |
| /* 12901 */ 'G', '_', 'F', 'S', 'Q', 'R', 'T', 0, | |
| /* 12909 */ 'F', 'T', 'S', 'Q', 'R', 'T', 0, | |
| /* 12916 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0, | |
| /* 12926 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0, | |
| /* 12943 */ 'V', 'N', 'C', 'I', 'P', 'H', 'E', 'R', 'L', 'A', 'S', 'T', 0, | |
| /* 12956 */ 'V', 'C', 'I', 'P', 'H', 'E', 'R', 'L', 'A', 'S', 'T', 0, | |
| /* 12968 */ 'C', 'P', '_', 'P', 'A', 'S', 'T', 'E', '_', 'L', 'A', 'S', 'T', 0, | |
| /* 12982 */ 'D', 'C', 'B', 'S', 'T', 0, | |
| /* 12988 */ 'D', 'S', 'T', 0, | |
| /* 12992 */ 'C', 'P', '_', 'C', 'O', 'P', 'Y', '_', 'F', 'I', 'R', 'S', 'T', 0, | |
| /* 13006 */ 'D', 'C', 'B', 'T', 'S', 'T', 0, | |
| /* 13013 */ 'D', 'S', 'T', 'S', 'T', 0, | |
| /* 13019 */ 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', '_', 'S', 'T', 0, | |
| /* 13033 */ 'D', 'C', 'B', 'T', 'T', 0, | |
| /* 13039 */ 'D', 'S', 'T', 'T', 0, | |
| /* 13044 */ 'D', 'C', 'B', 'T', 'S', 'T', 'T', 0, | |
| /* 13052 */ 'D', 'S', 'T', 'S', 'T', 'T', 0, | |
| /* 13059 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0, | |
| /* 13067 */ 'G', '_', 'S', 'E', 'X', 'T', 0, | |
| /* 13074 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0, | |
| /* 13083 */ 'G', '_', 'Z', 'E', 'X', 'T', 0, | |
| /* 13090 */ 'L', 'H', 'A', 'U', 0, | |
| /* 13095 */ 'S', 'T', 'B', 'U', 0, | |
| /* 13100 */ 'L', 'F', 'D', 'U', 0, | |
| /* 13105 */ 'S', 'T', 'F', 'D', 'U', 0, | |
| /* 13111 */ 'M', 'A', 'D', 'D', 'H', 'D', 'U', 0, | |
| /* 13119 */ 'M', 'U', 'L', 'H', 'D', 'U', 0, | |
| /* 13126 */ 'Q', 'V', 'F', 'C', 'F', 'I', 'D', 'U', 0, | |
| /* 13135 */ 'Q', 'V', 'F', 'C', 'T', 'I', 'D', 'U', 0, | |
| /* 13144 */ 'L', 'D', 'U', 0, | |
| /* 13148 */ 'S', 'T', 'D', 'U', 0, | |
| /* 13153 */ 'D', 'I', 'V', 'D', 'U', 0, | |
| /* 13159 */ 'D', 'I', 'V', 'D', 'E', 'U', 0, | |
| /* 13166 */ 'D', 'I', 'V', 'W', 'E', 'U', 0, | |
| /* 13173 */ 'S', 'T', 'H', 'U', 0, | |
| /* 13178 */ 'E', 'V', 'S', 'R', 'W', 'I', 'U', 0, | |
| /* 13186 */ 'E', 'V', 'L', 'W', 'H', 'O', 'U', 0, | |
| /* 13194 */ 'L', 'F', 'S', 'U', 0, | |
| /* 13199 */ 'S', 'T', 'F', 'S', 'U', 0, | |
| /* 13205 */ 'E', 'V', 'C', 'M', 'P', 'G', 'T', 'U', 0, | |
| /* 13214 */ 'E', 'V', 'C', 'M', 'P', 'L', 'T', 'U', 0, | |
| /* 13223 */ 'M', 'U', 'L', 'H', 'W', 'U', 0, | |
| /* 13230 */ 'Q', 'V', 'F', 'C', 'T', 'I', 'W', 'U', 0, | |
| /* 13239 */ 'E', 'V', 'S', 'R', 'W', 'U', 0, | |
| /* 13246 */ 'S', 'T', 'W', 'U', 0, | |
| /* 13251 */ 'E', 'V', 'D', 'I', 'V', 'W', 'U', 0, | |
| /* 13259 */ 'L', 'B', 'Z', 'U', 0, | |
| /* 13264 */ 'L', 'H', 'Z', 'U', 0, | |
| /* 13269 */ 'L', 'W', 'Z', 'U', 0, | |
| /* 13274 */ 'S', 'L', 'B', 'M', 'F', 'E', 'V', 0, | |
| /* 13282 */ 'E', 'F', 'D', 'D', 'I', 'V', 0, | |
| /* 13289 */ 'G', '_', 'F', 'D', 'I', 'V', 0, | |
| /* 13296 */ 'E', 'F', 'S', 'D', 'I', 'V', 0, | |
| /* 13303 */ 'E', 'V', 'F', 'S', 'D', 'I', 'V', 0, | |
| /* 13311 */ 'G', '_', 'S', 'D', 'I', 'V', 0, | |
| /* 13318 */ 'F', 'T', 'D', 'I', 'V', 0, | |
| /* 13324 */ 'G', '_', 'U', 'D', 'I', 'V', 0, | |
| /* 13331 */ 'V', 'S', 'L', 'V', 0, | |
| /* 13336 */ 'X', 'X', 'L', 'E', 'Q', 'V', 0, | |
| /* 13343 */ 'C', 'R', 'E', 'Q', 'V', 0, | |
| /* 13349 */ 'E', 'V', 'E', 'Q', 'V', 0, | |
| /* 13355 */ 'V', 'S', 'R', 'V', 0, | |
| /* 13360 */ 'L', 'X', 'V', 0, | |
| /* 13364 */ 'S', 'T', 'X', 'V', 0, | |
| /* 13369 */ 'V', 'E', 'X', 'T', 'S', 'B', '2', 'W', 0, | |
| /* 13378 */ 'V', 'E', 'X', 'T', 'S', 'H', '2', 'W', 0, | |
| /* 13387 */ 'E', 'V', 'M', 'H', 'E', 'S', 'M', 'F', 'A', 'A', 'W', 0, | |
| /* 13399 */ 'E', 'V', 'M', 'H', 'O', 'S', 'M', 'F', 'A', 'A', 'W', 0, | |
| /* 13411 */ 'E', 'V', 'M', 'H', 'E', 'S', 'S', 'F', 'A', 'A', 'W', 0, | |
| /* 13423 */ 'E', 'V', 'M', 'H', 'O', 'S', 'S', 'F', 'A', 'A', 'W', 0, | |
| /* 13435 */ 'E', 'V', 'A', 'D', 'D', 'S', 'M', 'I', 'A', 'A', 'W', 0, | |
| /* 13447 */ 'E', 'V', 'M', 'H', 'E', 'S', 'M', 'I', 'A', 'A', 'W', 0, | |
| /* 13459 */ 'E', 'V', 'S', 'U', 'B', 'F', 'S', 'M', 'I', 'A', 'A', 'W', 0, | |
| /* 13472 */ 'E', 'V', 'M', 'W', 'L', 'S', 'M', 'I', 'A', 'A', 'W', 0, | |
| /* 13484 */ 'E', 'V', 'M', 'H', 'O', 'S', 'M', 'I', 'A', 'A', 'W', 0, | |
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| /* 14438 */ 'L', 'H', 'A', 'X', 0, | |
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| /* 14474 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0, | |
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| /* 14902 */ 'L', 'H', 'E', 'P', 'X', 0, | |
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| /* 14965 */ 'L', 'B', 'A', 'R', 'X', 0, | |
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| /* 15024 */ 'L', 'W', 'B', 'R', 'X', 0, | |
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| /* 15055 */ 'M', 'C', 'R', 'X', 'R', 'X', 0, | |
| /* 15062 */ 'T', 'L', 'B', 'S', 'X', 0, | |
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| /* 15172 */ 'E', 'V', 'L', 'H', 'H', 'O', 'S', 'S', 'P', 'L', 'A', 'T', 'X', 0, | |
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| /* 15212 */ 'S', 'P', 'I', 'L', 'L', 'T', 'O', 'V', 'S', 'R', '_', 'S', 'T', 'X', 0, | |
| /* 15227 */ 'L', 'H', 'A', 'U', 'X', 0, | |
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| /* 15281 */ 'L', 'D', 'U', 'X', 0, | |
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| /* 15355 */ 'L', 'B', 'Z', 'U', 'X', 0, | |
| /* 15361 */ 'L', 'H', 'Z', 'U', 'X', 0, | |
| /* 15367 */ 'L', 'W', 'Z', 'U', 'X', 0, | |
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| /* 15382 */ 'L', 'X', 'V', 'X', 0, | |
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| /* 15430 */ 'S', 'T', 'X', 'S', 'I', 'W', 'X', 0, | |
| /* 15438 */ 'S', 'T', 'I', 'W', 'X', 0, | |
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| /* 15473 */ 'L', 'H', 'Z', 'X', 0, | |
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| /* 15493 */ 'L', 'X', 'S', 'I', 'W', 'Z', 'X', 0, | |
| /* 15501 */ 'S', 'P', 'E', 'L', 'W', 'Z', 'X', 0, | |
| /* 15509 */ 'C', 'P', '_', 'C', 'O', 'P', 'Y', 0, | |
| /* 15517 */ 'D', 'C', 'B', 'Z', 0, | |
| /* 15522 */ 'L', 'B', 'Z', 0, | |
| /* 15526 */ 'B', 'D', 'Z', 0, | |
| /* 15530 */ 'E', 'F', 'D', 'C', 'T', 'S', 'I', 'D', 'Z', 0, | |
| /* 15540 */ 'Q', 'V', 'F', 'C', 'T', 'I', 'D', 'Z', 0, | |
| /* 15549 */ 'E', 'F', 'D', 'C', 'T', 'U', 'I', 'D', 'Z', 0, | |
| /* 15559 */ 'X', 'S', 'C', 'V', 'Q', 'P', 'S', 'D', 'Z', 0, | |
| /* 15569 */ 'X', 'S', 'C', 'V', 'Q', 'P', 'U', 'D', 'Z', 0, | |
| /* 15579 */ 'L', 'H', 'Z', 0, | |
| /* 15583 */ 'V', 'R', 'F', 'I', 'Z', 0, | |
| /* 15589 */ 'X', 'S', 'R', 'D', 'P', 'I', 'Z', 0, | |
| /* 15597 */ 'X', 'V', 'R', 'D', 'P', 'I', 'Z', 0, | |
| /* 15605 */ 'X', 'V', 'R', 'S', 'P', 'I', 'Z', 0, | |
| /* 15613 */ 'Q', 'V', 'F', 'R', 'I', 'Z', 0, | |
| /* 15620 */ 'E', 'F', 'D', 'C', 'T', 'S', 'I', 'Z', 0, | |
| /* 15629 */ 'E', 'F', 'S', 'C', 'T', 'S', 'I', 'Z', 0, | |
| /* 15638 */ 'E', 'V', 'F', 'S', 'C', 'T', 'S', 'I', 'Z', 0, | |
| /* 15648 */ 'E', 'F', 'D', 'C', 'T', 'U', 'I', 'Z', 0, | |
| /* 15657 */ 'E', 'F', 'S', 'C', 'T', 'U', 'I', 'Z', 0, | |
| /* 15666 */ 'E', 'V', 'F', 'S', 'C', 'T', 'U', 'I', 'Z', 0, | |
| /* 15676 */ 'G', '_', 'C', 'T', 'L', 'Z', 0, | |
| /* 15683 */ 'B', 'D', 'N', 'Z', 0, | |
| /* 15688 */ 'G', '_', 'C', 'T', 'T', 'Z', 0, | |
| /* 15695 */ 'Q', 'V', 'F', 'C', 'T', 'I', 'D', 'U', 'Z', 0, | |
| /* 15705 */ 'Q', 'V', 'F', 'C', 'T', 'I', 'W', 'U', 'Z', 0, | |
| /* 15715 */ 'Q', 'V', 'F', 'C', 'T', 'I', 'W', 'Z', 0, | |
| /* 15724 */ 'S', 'P', 'E', 'L', 'W', 'Z', 0, | |
| /* 15731 */ 'M', 'F', 'V', 'S', 'R', 'W', 'Z', 0, | |
| /* 15739 */ 'M', 'T', 'V', 'S', 'R', 'W', 'Z', 0, | |
| /* 15747 */ 'M', 'F', 'V', 'R', 'W', 'Z', 0, | |
| /* 15754 */ 'M', 'T', 'V', 'R', 'W', 'Z', 0, | |
| /* 15761 */ 'X', 'S', 'C', 'V', 'Q', 'P', 'S', 'W', 'Z', 0, | |
| /* 15771 */ 'X', 'S', 'C', 'V', 'Q', 'P', 'U', 'W', 'Z', 0, | |
| /* 15781 */ 'A', 'D', 'D', '8', 'T', 'L', 'S', '_', 0, | |
| /* 15790 */ 'S', 'T', 'B', 'X', 'T', 'L', 'S', '_', 0, | |
| /* 15799 */ 'L', 'D', 'X', 'T', 'L', 'S', '_', 0, | |
| /* 15807 */ 'S', 'T', 'D', 'X', 'T', 'L', 'S', '_', 0, | |
| /* 15816 */ 'S', 'T', 'H', 'X', 'T', 'L', 'S', '_', 0, | |
| /* 15825 */ 'S', 'T', 'W', 'X', 'T', 'L', 'S', '_', 0, | |
| /* 15834 */ 'L', 'B', 'Z', 'X', 'T', 'L', 'S', '_', 0, | |
| /* 15843 */ 'L', 'H', 'Z', 'X', 'T', 'L', 'S', '_', 0, | |
| /* 15852 */ 'L', 'W', 'Z', 'X', 'T', 'L', 'S', '_', 0, | |
| /* 15861 */ 'B', 'L', '8', '_', 'T', 'L', 'S', '_', 0, | |
| /* 15870 */ 'Q', 'V', 'F', 'C', 'F', 'I', 'D', 'b', 0, | |
| /* 15879 */ 'Q', 'V', 'F', 'C', 'T', 'I', 'D', 'b', 0, | |
| /* 15888 */ 'M', 'T', 'F', 'S', 'F', 'b', 0, | |
| /* 15895 */ 'Q', 'V', 'A', 'L', 'I', 'G', 'N', 'I', 'b', 0, | |
| /* 15905 */ 'Q', 'V', 'E', 'S', 'P', 'L', 'A', 'T', 'I', 'b', 0, | |
| /* 15916 */ 'Q', 'V', 'F', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 'b', 0, | |
| /* 15928 */ 'Q', 'V', 'F', 'S', 'E', 'L', 'b', 0, | |
| /* 15936 */ 'Q', 'V', 'F', 'T', 'S', 'T', 'N', 'A', 'N', 'b', 0, | |
| /* 15947 */ 'Q', 'V', 'F', 'C', 'M', 'P', 'E', 'Q', 'b', 0, | |
| /* 15957 */ 'Q', 'V', 'F', 'M', 'R', 'b', 0, | |
| /* 15964 */ 'Q', 'V', 'F', 'C', 'M', 'P', 'G', 'T', 'b', 0, | |
| /* 15974 */ 'Q', 'V', 'F', 'C', 'M', 'P', 'L', 'T', 'b', 0, | |
| /* 15984 */ 'Q', 'V', 'L', 'F', 'D', 'X', 'b', 0, | |
| /* 15992 */ 'Q', 'V', 'S', 'T', 'F', 'D', 'X', 'b', 0, | |
| /* 16001 */ 'Q', 'V', 'L', 'F', 'S', 'X', 'b', 0, | |
| /* 16009 */ 'Q', 'V', 'F', 'S', 'E', 'L', 'b', 'b', 0, | |
| /* 16018 */ 'R', 'L', 'D', 'I', 'C', 'L', '_', '3', '2', '_', 'r', 'e', 'c', 0, | |
| /* 16032 */ 'E', 'X', 'T', 'S', 'W', 'S', 'L', 'I', '_', '3', '2', '_', '6', '4', '_', 'r', 'e', 'c', 0, | |
| /* 16051 */ 'E', 'X', 'T', 'S', 'W', '_', '3', '2', '_', '6', '4', '_', 'r', 'e', 'c', 0, | |
| /* 16067 */ 'A', 'D', 'D', '4', '_', 'r', 'e', 'c', 0, | |
| /* 16076 */ 'E', 'X', 'T', 'S', 'B', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16087 */ 'A', 'D', 'D', 'C', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16097 */ 'A', 'N', 'D', 'C', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16107 */ 'S', 'U', 'B', 'F', 'C', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16118 */ 'O', 'R', 'C', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16127 */ 'A', 'D', 'D', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16136 */ 'N', 'A', 'N', 'D', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16146 */ 'A', 'D', 'D', 'E', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16156 */ 'S', 'U', 'B', 'F', 'E', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16167 */ 'A', 'D', 'D', 'M', 'E', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16178 */ 'S', 'U', 'B', 'F', 'M', 'E', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16190 */ 'C', 'P', '_', 'P', 'A', 'S', 'T', 'E', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16204 */ 'A', 'D', 'D', 'Z', 'E', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16215 */ 'S', 'U', 'B', 'F', 'Z', 'E', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16227 */ 'S', 'U', 'B', 'F', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16237 */ 'N', 'E', 'G', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16246 */ 'E', 'X', 'T', 'S', 'H', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16257 */ 'A', 'N', 'D', 'I', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16267 */ 'R', 'L', 'W', 'I', 'M', 'I', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16279 */ 'R', 'L', 'W', 'I', 'N', 'M', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16291 */ 'R', 'L', 'W', 'N', 'M', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16302 */ 'N', 'O', 'R', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16311 */ 'X', 'O', 'R', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16320 */ 'A', 'N', 'D', 'I', 'S', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16331 */ 'E', 'Q', 'V', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16340 */ 'S', 'L', 'W', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16349 */ 'S', 'R', 'W', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16358 */ 'C', 'N', 'T', 'L', 'Z', 'W', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16370 */ 'C', 'N', 'T', 'T', 'Z', 'W', '8', '_', 'r', 'e', 'c', 0, | |
| /* 16382 */ 'V', 'C', 'M', 'P', 'N', 'E', 'B', '_', 'r', 'e', 'c', 0, | |
| /* 16394 */ 'V', 'C', 'M', 'P', 'G', 'T', 'S', 'B', '_', 'r', 'e', 'c', 0, | |
| /* 16407 */ 'E', 'X', 'T', 'S', 'B', '_', 'r', 'e', 'c', 0, | |
| /* 16417 */ 'V', 'C', 'M', 'P', 'E', 'Q', 'U', 'B', '_', 'r', 'e', 'c', 0, | |
| /* 16430 */ 'F', 'S', 'U', 'B', '_', 'r', 'e', 'c', 0, | |
| /* 16439 */ 'F', 'M', 'S', 'U', 'B', '_', 'r', 'e', 'c', 0, | |
| /* 16449 */ 'F', 'N', 'M', 'S', 'U', 'B', '_', 'r', 'e', 'c', 0, | |
| /* 16460 */ 'V', 'C', 'M', 'P', 'G', 'T', 'U', 'B', '_', 'r', 'e', 'c', 0, | |
| /* 16473 */ 'V', 'C', 'M', 'P', 'N', 'E', 'Z', 'B', '_', 'r', 'e', 'c', 0, | |
| /* 16486 */ 'A', 'D', 'D', 'C', '_', 'r', 'e', 'c', 0, | |
| /* 16495 */ 'A', 'N', 'D', 'C', '_', 'r', 'e', 'c', 0, | |
| /* 16504 */ 'S', 'U', 'B', 'F', 'C', '_', 'r', 'e', 'c', 0, | |
| /* 16514 */ 'S', 'U', 'B', 'I', 'C', '_', 'r', 'e', 'c', 0, | |
| /* 16524 */ 'A', 'D', 'D', 'I', 'C', '_', 'r', 'e', 'c', 0, | |
| /* 16534 */ 'R', 'L', 'D', 'I', 'C', '_', 'r', 'e', 'c', 0, | |
| /* 16544 */ 'B', 'C', 'D', 'T', 'R', 'U', 'N', 'C', '_', 'r', 'e', 'c', 0, | |
| /* 16557 */ 'B', 'C', 'D', 'U', 'T', 'R', 'U', 'N', 'C', '_', 'r', 'e', 'c', 0, | |
| /* 16571 */ 'O', 'R', 'C', '_', 'r', 'e', 'c', 0, | |
| /* 16579 */ 'S', 'R', 'A', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16588 */ 'F', 'A', 'D', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16597 */ 'F', 'M', 'A', 'D', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16607 */ 'F', 'N', 'M', 'A', 'D', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16618 */ 'F', 'N', 'E', 'G', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16628 */ 'M', 'U', 'L', 'H', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16638 */ 'F', 'C', 'F', 'I', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16648 */ 'F', 'C', 'T', 'I', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16658 */ 'F', 'S', 'E', 'L', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16668 */ 'M', 'U', 'L', 'L', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16678 */ 'S', 'L', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16686 */ 'F', 'R', 'I', 'M', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16696 */ 'N', 'A', 'N', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16705 */ 'F', 'C', 'P', 'S', 'G', 'N', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16717 */ 'F', 'R', 'I', 'N', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16727 */ 'F', 'R', 'I', 'P', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16737 */ 'S', 'R', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16745 */ 'F', 'A', 'B', 'S', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16755 */ 'F', 'N', 'A', 'B', 'S', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16766 */ 'V', 'C', 'M', 'P', 'G', 'T', 'S', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16779 */ 'V', 'C', 'M', 'P', 'E', 'Q', 'U', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16792 */ 'V', 'C', 'M', 'P', 'G', 'T', 'U', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16805 */ 'D', 'I', 'V', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16814 */ 'F', 'R', 'I', 'Z', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16824 */ 'C', 'N', 'T', 'L', 'Z', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16835 */ 'C', 'N', 'T', 'T', 'Z', 'D', '_', 'r', 'e', 'c', 0, | |
| /* 16846 */ 'A', 'D', 'D', 'E', '_', 'r', 'e', 'c', 0, | |
| /* 16855 */ 'D', 'I', 'V', 'D', 'E', '_', 'r', 'e', 'c', 0, | |
| /* 16865 */ 'S', 'L', 'B', 'F', 'E', 'E', '_', 'r', 'e', 'c', 0, | |
| /* 16876 */ 'S', 'U', 'B', 'F', 'E', '_', 'r', 'e', 'c', 0, | |
| /* 16886 */ 'A', 'D', 'D', 'M', 'E', '_', 'r', 'e', 'c', 0, | |
| /* 16896 */ 'S', 'U', 'B', 'F', 'M', 'E', '_', 'r', 'e', 'c', 0, | |
| /* 16907 */ 'F', 'R', 'E', '_', 'r', 'e', 'c', 0, | |
| /* 16915 */ 'F', 'R', 'S', 'Q', 'R', 'T', 'E', '_', 'r', 'e', 'c', 0, | |
| /* 16927 */ 'C', 'P', '_', 'P', 'A', 'S', 'T', 'E', '_', 'r', 'e', 'c', 0, | |
| /* 16940 */ 'D', 'I', 'V', 'W', 'E', '_', 'r', 'e', 'c', 0, | |
| /* 16950 */ 'A', 'D', 'D', 'Z', 'E', '_', 'r', 'e', 'c', 0, | |
| /* 16960 */ 'S', 'U', 'B', 'F', 'Z', 'E', '_', 'r', 'e', 'c', 0, | |
| /* 16971 */ 'S', 'U', 'B', 'F', '_', 'r', 'e', 'c', 0, | |
| /* 16980 */ 'M', 'T', 'F', 'S', 'F', '_', 'r', 'e', 'c', 0, | |
| /* 16990 */ 'N', 'E', 'G', '_', 'r', 'e', 'c', 0, | |
| /* 16998 */ 'V', 'C', 'M', 'P', 'N', 'E', 'H', '_', 'r', 'e', 'c', 0, | |
| /* 17010 */ 'V', 'C', 'M', 'P', 'G', 'T', 'S', 'H', '_', 'r', 'e', 'c', 0, | |
| /* 17023 */ 'E', 'X', 'T', 'S', 'H', '_', 'r', 'e', 'c', 0, | |
| /* 17033 */ 'V', 'C', 'M', 'P', 'E', 'Q', 'U', 'H', '_', 'r', 'e', 'c', 0, | |
| /* 17046 */ 'V', 'C', 'M', 'P', 'G', 'T', 'U', 'H', '_', 'r', 'e', 'c', 0, | |
| /* 17059 */ 'V', 'C', 'M', 'P', 'N', 'E', 'Z', 'H', '_', 'r', 'e', 'c', 0, | |
| /* 17072 */ 'S', 'R', 'A', 'D', 'I', '_', 'r', 'e', 'c', 0, | |
| /* 17082 */ 'C', 'L', 'R', 'L', 'S', 'L', 'D', 'I', '_', 'r', 'e', 'c', 0, | |
| /* 17095 */ 'E', 'X', 'T', 'L', 'D', 'I', '_', 'r', 'e', 'c', 0, | |
| /* 17106 */ 'A', 'N', 'D', 'I', '_', 'r', 'e', 'c', 0, | |
| /* 17115 */ 'C', 'L', 'R', 'R', 'D', 'I', '_', 'r', 'e', 'c', 0, | |
| /* 17126 */ 'I', 'N', 'S', 'R', 'D', 'I', '_', 'r', 'e', 'c', 0, | |
| /* 17137 */ 'R', 'O', 'T', 'R', 'D', 'I', '_', 'r', 'e', 'c', 0, | |
| /* 17148 */ 'E', 'X', 'T', 'R', 'D', 'I', '_', 'r', 'e', 'c', 0, | |
| /* 17159 */ 'M', 'T', 'F', 'S', 'F', 'I', '_', 'r', 'e', 'c', 0, | |
| /* 17170 */ 'E', 'X', 'T', 'S', 'W', 'S', 'L', 'I', '_', 'r', 'e', 'c', 0, | |
| /* 17183 */ 'R', 'L', 'D', 'I', 'M', 'I', '_', 'r', 'e', 'c', 0, | |
| /* 17194 */ 'R', 'L', 'W', 'I', 'M', 'I', '_', 'r', 'e', 'c', 0, | |
| /* 17205 */ 'S', 'R', 'A', 'W', 'I', '_', 'r', 'e', 'c', 0, | |
| /* 17215 */ 'C', 'L', 'R', 'L', 'S', 'L', 'W', 'I', '_', 'r', 'e', 'c', 0, | |
| /* 17228 */ 'I', 'N', 'S', 'L', 'W', 'I', '_', 'r', 'e', 'c', 0, | |
| /* 17239 */ 'E', 'X', 'T', 'L', 'W', 'I', '_', 'r', 'e', 'c', 0, | |
| /* 17250 */ 'C', 'L', 'R', 'R', 'W', 'I', '_', 'r', 'e', 'c', 0, | |
| /* 17261 */ 'I', 'N', 'S', 'R', 'W', 'I', '_', 'r', 'e', 'c', 0, | |
| /* 17272 */ 'R', 'O', 'T', 'R', 'W', 'I', '_', 'r', 'e', 'c', 0, | |
| /* 17283 */ 'E', 'X', 'T', 'R', 'W', 'I', '_', 'r', 'e', 'c', 0, | |
| /* 17294 */ 'R', 'L', 'D', 'C', 'L', '_', 'r', 'e', 'c', 0, | |
| /* 17304 */ 'R', 'L', 'D', 'I', 'C', 'L', '_', 'r', 'e', 'c', 0, | |
| /* 17315 */ 'F', 'M', 'U', 'L', '_', 'r', 'e', 'c', 0, | |
| /* 17324 */ 'R', 'L', 'W', 'I', 'N', 'M', '_', 'r', 'e', 'c', 0, | |
| /* 17335 */ 'R', 'L', 'W', 'N', 'M', '_', 'r', 'e', 'c', 0, | |
| /* 17345 */ 'B', 'C', 'D', 'C', 'F', 'N', '_', 'r', 'e', 'c', 0, | |
| /* 17356 */ 'B', 'C', 'D', 'C', 'P', 'S', 'G', 'N', '_', 'r', 'e', 'c', 0, | |
| /* 17369 */ 'B', 'C', 'D', 'S', 'E', 'T', 'S', 'G', 'N', '_', 'r', 'e', 'c', 0, | |
| /* 17383 */ 'B', 'C', 'D', 'C', 'T', 'N', '_', 'r', 'e', 'c', 0, | |
| /* 17394 */ 'A', 'D', 'D', '4', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17404 */ 'A', 'D', 'D', 'C', '8', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17415 */ 'S', 'U', 'B', 'F', 'C', '8', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17427 */ 'A', 'D', 'D', '8', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17437 */ 'A', 'D', 'D', 'E', '8', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17448 */ 'S', 'U', 'B', 'F', 'E', '8', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17460 */ 'A', 'D', 'D', 'M', 'E', '8', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17472 */ 'S', 'U', 'B', 'F', 'M', 'E', '8', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17485 */ 'A', 'D', 'D', 'Z', 'E', '8', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17497 */ 'S', 'U', 'B', 'F', 'Z', 'E', '8', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17510 */ 'S', 'U', 'B', 'F', '8', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17521 */ 'N', 'E', 'G', '8', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17531 */ 'A', 'D', 'D', 'C', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17541 */ 'S', 'U', 'B', 'F', 'C', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17552 */ 'M', 'U', 'L', 'L', 'D', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17563 */ 'D', 'I', 'V', 'D', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17573 */ 'A', 'D', 'D', 'E', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17583 */ 'D', 'I', 'V', 'D', 'E', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17594 */ 'S', 'U', 'B', 'F', 'E', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17605 */ 'A', 'D', 'D', 'M', 'E', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17616 */ 'S', 'U', 'B', 'F', 'M', 'E', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17628 */ 'D', 'I', 'V', 'W', 'E', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17639 */ 'A', 'D', 'D', 'Z', 'E', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17650 */ 'S', 'U', 'B', 'F', 'Z', 'E', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17662 */ 'S', 'U', 'B', 'F', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17672 */ 'N', 'E', 'G', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17681 */ 'D', 'I', 'V', 'D', 'U', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17692 */ 'D', 'I', 'V', 'D', 'E', 'U', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17704 */ 'D', 'I', 'V', 'W', 'E', 'U', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17716 */ 'D', 'I', 'V', 'W', 'U', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17727 */ 'M', 'U', 'L', 'L', 'W', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17738 */ 'D', 'I', 'V', 'W', 'O', '_', 'r', 'e', 'c', 0, | |
| /* 17748 */ 'X', 'V', 'C', 'M', 'P', 'G', 'E', 'D', 'P', '_', 'r', 'e', 'c', 0, | |
| /* 17762 */ 'X', 'V', 'C', 'M', 'P', 'E', 'Q', 'D', 'P', '_', 'r', 'e', 'c', 0, | |
| /* 17776 */ 'X', 'V', 'C', 'M', 'P', 'G', 'T', 'D', 'P', '_', 'r', 'e', 'c', 0, | |
| /* 17790 */ 'V', 'C', 'M', 'P', 'B', 'F', 'P', '_', 'r', 'e', 'c', 0, | |
| /* 17802 */ 'V', 'C', 'M', 'P', 'G', 'E', 'F', 'P', '_', 'r', 'e', 'c', 0, | |
| /* 17815 */ 'V', 'C', 'M', 'P', 'E', 'Q', 'F', 'P', '_', 'r', 'e', 'c', 0, | |
| /* 17828 */ 'V', 'C', 'M', 'P', 'G', 'T', 'F', 'P', '_', 'r', 'e', 'c', 0, | |
| /* 17841 */ 'X', 'V', 'C', 'M', 'P', 'G', 'E', 'S', 'P', '_', 'r', 'e', 'c', 0, | |
| /* 17855 */ 'X', 'V', 'C', 'M', 'P', 'E', 'Q', 'S', 'P', '_', 'r', 'e', 'c', 0, | |
| /* 17869 */ 'F', 'R', 'S', 'P', '_', 'r', 'e', 'c', 0, | |
| /* 17878 */ 'X', 'V', 'C', 'M', 'P', 'G', 'T', 'S', 'P', '_', 'r', 'e', 'c', 0, | |
| /* 17892 */ 'B', 'C', 'D', 'C', 'F', 'S', 'Q', '_', 'r', 'e', 'c', 0, | |
| /* 17904 */ 'B', 'C', 'D', 'C', 'T', 'S', 'Q', '_', 'r', 'e', 'c', 0, | |
| /* 17916 */ 'R', 'L', 'D', 'C', 'R', '_', 'r', 'e', 'c', 0, | |
| /* 17926 */ 'R', 'L', 'D', 'I', 'C', 'R', '_', 'r', 'e', 'c', 0, | |
| /* 17937 */ 'F', 'M', 'R', '_', 'r', 'e', 'c', 0, | |
| /* 17945 */ 'N', 'O', 'R', '_', 'r', 'e', 'c', 0, | |
| /* 17953 */ 'X', 'O', 'R', '_', 'r', 'e', 'c', 0, | |
| /* 17961 */ 'B', 'C', 'D', 'S', 'R', '_', 'r', 'e', 'c', 0, | |
| /* 17971 */ 'F', 'S', 'U', 'B', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 17981 */ 'F', 'M', 'S', 'U', 'B', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 17992 */ 'F', 'N', 'M', 'S', 'U', 'B', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18004 */ 'B', 'C', 'D', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18013 */ 'F', 'A', 'D', 'D', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18023 */ 'F', 'M', 'A', 'D', 'D', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18034 */ 'F', 'N', 'M', 'A', 'D', 'D', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18046 */ 'F', 'C', 'F', 'I', 'D', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18057 */ 'F', 'R', 'E', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18066 */ 'F', 'R', 'S', 'Q', 'R', 'T', 'E', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18079 */ 'M', 'F', 'F', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18088 */ 'F', 'N', 'E', 'G', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18098 */ 'A', 'N', 'D', 'I', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18108 */ 'F', 'S', 'E', 'L', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18118 */ 'F', 'M', 'U', 'L', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18128 */ 'F', 'R', 'I', 'M', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18138 */ 'F', 'C', 'P', 'S', 'G', 'N', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18150 */ 'F', 'R', 'I', 'N', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18160 */ 'F', 'R', 'I', 'P', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18170 */ 'F', 'A', 'B', 'S', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18180 */ 'F', 'N', 'A', 'B', 'S', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18191 */ 'F', 'S', 'Q', 'R', 'T', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18202 */ 'B', 'C', 'D', 'U', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18212 */ 'F', 'C', 'F', 'I', 'D', 'U', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18224 */ 'F', 'D', 'I', 'V', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18234 */ 'F', 'R', 'I', 'Z', 'S', '_', 'r', 'e', 'c', 0, | |
| /* 18244 */ 'F', 'S', 'Q', 'R', 'T', '_', 'r', 'e', 'c', 0, | |
| /* 18254 */ 'M', 'U', 'L', 'H', 'D', 'U', '_', 'r', 'e', 'c', 0, | |
| /* 18265 */ 'F', 'C', 'F', 'I', 'D', 'U', '_', 'r', 'e', 'c', 0, | |
| /* 18276 */ 'F', 'C', 'T', 'I', 'D', 'U', '_', 'r', 'e', 'c', 0, | |
| /* 18287 */ 'D', 'I', 'V', 'D', 'U', '_', 'r', 'e', 'c', 0, | |
| /* 18297 */ 'D', 'I', 'V', 'D', 'E', 'U', '_', 'r', 'e', 'c', 0, | |
| /* 18308 */ 'D', 'I', 'V', 'W', 'E', 'U', '_', 'r', 'e', 'c', 0, | |
| /* 18319 */ 'M', 'U', 'L', 'H', 'W', 'U', '_', 'r', 'e', 'c', 0, | |
| /* 18330 */ 'F', 'C', 'T', 'I', 'W', 'U', '_', 'r', 'e', 'c', 0, | |
| /* 18341 */ 'D', 'I', 'V', 'W', 'U', '_', 'r', 'e', 'c', 0, | |
| /* 18351 */ 'F', 'D', 'I', 'V', '_', 'r', 'e', 'c', 0, | |
| /* 18360 */ 'E', 'Q', 'V', '_', 'r', 'e', 'c', 0, | |
| /* 18368 */ 'S', 'R', 'A', 'W', '_', 'r', 'e', 'c', 0, | |
| /* 18377 */ 'V', 'C', 'M', 'P', 'N', 'E', 'W', '_', 'r', 'e', 'c', 0, | |
| /* 18389 */ 'M', 'U', 'L', 'H', 'W', '_', 'r', 'e', 'c', 0, | |
| /* 18399 */ 'F', 'C', 'T', 'I', 'W', '_', 'r', 'e', 'c', 0, | |
| /* 18409 */ 'M', 'U', 'L', 'L', 'W', '_', 'r', 'e', 'c', 0, | |
| /* 18419 */ 'S', 'L', 'W', '_', 'r', 'e', 'c', 0, | |
| /* 18427 */ 'S', 'R', 'W', '_', 'r', 'e', 'c', 0, | |
| /* 18435 */ 'V', 'C', 'M', 'P', 'G', 'T', 'S', 'W', '_', 'r', 'e', 'c', 0, | |
| /* 18448 */ 'E', 'X', 'T', 'S', 'W', '_', 'r', 'e', 'c', 0, | |
| /* 18458 */ 'V', 'C', 'M', 'P', 'E', 'Q', 'U', 'W', '_', 'r', 'e', 'c', 0, | |
| /* 18471 */ 'V', 'C', 'M', 'P', 'G', 'T', 'U', 'W', '_', 'r', 'e', 'c', 0, | |
| /* 18484 */ 'D', 'I', 'V', 'W', '_', 'r', 'e', 'c', 0, | |
| /* 18493 */ 'V', 'C', 'M', 'P', 'N', 'E', 'Z', 'W', '_', 'r', 'e', 'c', 0, | |
| /* 18506 */ 'C', 'N', 'T', 'L', 'Z', 'W', '_', 'r', 'e', 'c', 0, | |
| /* 18517 */ 'C', 'N', 'T', 'T', 'Z', 'W', '_', 'r', 'e', 'c', 0, | |
| /* 18528 */ 'F', 'C', 'T', 'I', 'D', 'Z', '_', 'r', 'e', 'c', 0, | |
| /* 18539 */ 'B', 'C', 'D', 'C', 'F', 'Z', '_', 'r', 'e', 'c', 0, | |
| /* 18550 */ 'B', 'C', 'D', 'C', 'T', 'Z', '_', 'r', 'e', 'c', 0, | |
| /* 18561 */ 'F', 'C', 'T', 'I', 'D', 'U', 'Z', '_', 'r', 'e', 'c', 0, | |
| /* 18573 */ 'F', 'C', 'T', 'I', 'W', 'U', 'Z', '_', 'r', 'e', 'c', 0, | |
| /* 18585 */ 'F', 'C', 'T', 'I', 'W', 'Z', '_', 'r', 'e', 'c', 0, | |
| /* 18596 */ 'R', 'L', 'W', 'I', 'M', 'I', 'b', 'm', '_', 'r', 'e', 'c', 0, | |
| /* 18609 */ 'R', 'L', 'W', 'I', 'N', 'M', 'b', 'm', '_', 'r', 'e', 'c', 0, | |
| /* 18622 */ 'R', 'L', 'W', 'N', 'M', 'b', 'm', '_', 'r', 'e', 'c', 0, | |
| /* 18634 */ 'L', 'D', 't', 'o', 'c', 0, | |
| /* 18640 */ 'L', 'W', 'Z', 't', 'o', 'c', 0, | |
| /* 18647 */ 'B', 'C', 'T', 'R', 'L', '8', '_', 'L', 'D', 'i', 'n', 't', 'o', '_', 't', 'o', 'c', 0, | |
| /* 18665 */ 'B', 'C', 'T', 'R', 'L', '_', 'L', 'W', 'Z', 'i', 'n', 't', 'o', '_', 't', 'o', 'c', 0, | |
| /* 18683 */ 'X', 'X', 'L', 'O', 'R', 'f', 0, | |
| /* 18690 */ 'S', 'E', 'T', 'R', 'N', 'D', 'i', 0, | |
| /* 18698 */ 'T', 'C', 'R', 'E', 'T', 'U', 'R', 'N', 'a', 'i', 0, | |
| /* 18709 */ 'T', 'C', 'R', 'E', 'T', 'U', 'R', 'N', 'd', 'i', 0, | |
| /* 18720 */ 'T', 'C', 'R', 'E', 'T', 'U', 'R', 'N', 'r', 'i', 0, | |
| /* 18731 */ 'B', 'D', 'Z', 'L', 'A', 'm', 0, | |
| /* 18738 */ 'B', 'D', 'N', 'Z', 'L', 'A', 'm', 0, | |
| /* 18746 */ 'B', 'D', 'Z', 'A', 'm', 0, | |
| /* 18752 */ 'B', 'D', 'N', 'Z', 'A', 'm', 0, | |
| /* 18759 */ 'B', 'D', 'Z', 'L', 'R', 'L', 'm', 0, | |
| /* 18767 */ 'B', 'D', 'N', 'Z', 'L', 'R', 'L', 'm', 0, | |
| /* 18776 */ 'B', 'D', 'Z', 'L', 'm', 0, | |
| /* 18782 */ 'B', 'D', 'N', 'Z', 'L', 'm', 0, | |
| /* 18789 */ 'B', 'D', 'Z', 'L', 'R', 'm', 0, | |
| /* 18796 */ 'B', 'D', 'N', 'Z', 'L', 'R', 'm', 0, | |
| /* 18804 */ 'B', 'D', 'Z', 'm', 0, | |
| /* 18809 */ 'B', 'D', 'N', 'Z', 'm', 0, | |
| /* 18815 */ 'R', 'L', 'W', 'I', 'M', 'I', 'b', 'm', 0, | |
| /* 18824 */ 'R', 'L', 'W', 'I', 'N', 'M', 'b', 'm', 0, | |
| /* 18833 */ 'R', 'L', 'W', 'N', 'M', 'b', 'm', 0, | |
| /* 18841 */ 'B', 'C', 'C', 'T', 'R', 'L', '8', 'n', 0, | |
| /* 18850 */ 'B', 'C', 'C', 'T', 'R', '8', 'n', 0, | |
| /* 18858 */ 'B', 'C', 'n', 0, | |
| /* 18862 */ 'B', 'C', 'L', 'n', 0, | |
| /* 18867 */ 'B', 'C', 'L', 'R', 'L', 'n', 0, | |
| /* 18874 */ 'B', 'C', 'C', 'T', 'R', 'L', 'n', 0, | |
| /* 18882 */ 'B', 'C', 'L', 'R', 'n', 0, | |
| /* 18888 */ 'B', 'C', 'C', 'T', 'R', 'n', 0, | |
| /* 18895 */ 'B', 'D', 'Z', 'L', 'A', 'p', 0, | |
| /* 18902 */ 'B', 'D', 'N', 'Z', 'L', 'A', 'p', 0, | |
| /* 18910 */ 'B', 'D', 'Z', 'A', 'p', 0, | |
| /* 18916 */ 'B', 'D', 'N', 'Z', 'A', 'p', 0, | |
| /* 18923 */ 'B', 'D', 'Z', 'L', 'R', 'L', 'p', 0, | |
| /* 18931 */ 'B', 'D', 'N', 'Z', 'L', 'R', 'L', 'p', 0, | |
| /* 18940 */ 'B', 'D', 'Z', 'L', 'p', 0, | |
| /* 18946 */ 'B', 'D', 'N', 'Z', 'L', 'p', 0, | |
| /* 18953 */ 'B', 'D', 'Z', 'L', 'R', 'p', 0, | |
| /* 18960 */ 'B', 'D', 'N', 'Z', 'L', 'R', 'p', 0, | |
| /* 18968 */ 'B', 'D', 'Z', 'p', 0, | |
| /* 18973 */ 'B', 'D', 'N', 'Z', 'p', 0, | |
| /* 18979 */ 'M', 'T', 'C', 'T', 'R', '8', 'l', 'o', 'o', 'p', 0, | |
| /* 18990 */ 'M', 'T', 'C', 'T', 'R', 'l', 'o', 'o', 'p', 0, | |
| /* 19000 */ 'E', 'H', '_', 'S', 'j', 'L', 'j', '_', 'S', 'e', 't', 'u', 'p', 0, | |
| /* 19014 */ 'V', 'S', 'P', 'L', 'T', 'B', 's', 0, | |
| /* 19022 */ 'V', 'E', 'X', 'T', 'S', 'B', '2', 'D', 's', 0, | |
| /* 19032 */ 'V', 'E', 'X', 'T', 'S', 'H', '2', 'D', 's', 0, | |
| /* 19042 */ 'V', 'E', 'X', 'T', 'S', 'W', '2', 'D', 's', 0, | |
| /* 19052 */ 'Q', 'V', 'F', 'N', 'E', 'G', 's', 0, | |
| /* 19060 */ 'V', 'S', 'P', 'L', 'T', 'H', 's', 0, | |
| /* 19068 */ 'X', 'X', 'P', 'E', 'R', 'M', 'D', 'I', 's', 0, | |
| /* 19078 */ 'Q', 'V', 'A', 'L', 'I', 'G', 'N', 'I', 's', 0, | |
| /* 19088 */ 'Q', 'V', 'E', 'S', 'P', 'L', 'A', 'T', 'I', 's', 0, | |
| /* 19099 */ 'X', 'X', 'S', 'L', 'D', 'W', 'I', 's', 0, | |
| /* 19108 */ 'Q', 'V', 'F', 'L', 'O', 'G', 'I', 'C', 'A', 'L', 's', 0, | |
| /* 19120 */ 'Q', 'V', 'F', 'R', 'I', 'M', 's', 0, | |
| /* 19128 */ 'Q', 'V', 'F', 'P', 'E', 'R', 'M', 's', 0, | |
| /* 19137 */ 'Q', 'V', 'F', 'C', 'P', 'S', 'G', 'N', 's', 0, | |
| /* 19147 */ 'Q', 'V', 'F', 'R', 'I', 'N', 's', 0, | |
| /* 19155 */ 'Q', 'V', 'F', 'R', 'I', 'P', 's', 0, | |
| /* 19163 */ 'Q', 'V', 'F', 'R', 'S', 'P', 's', 0, | |
| /* 19171 */ 'Q', 'V', 'F', 'M', 'R', 's', 0, | |
| /* 19178 */ 'Q', 'V', 'F', 'A', 'B', 'S', 's', 0, | |
| /* 19186 */ 'Q', 'V', 'F', 'N', 'A', 'B', 'S', 's', 0, | |
| /* 19195 */ 'Q', 'V', 'F', 'S', 'U', 'B', 'S', 's', 0, | |
| /* 19204 */ 'Q', 'V', 'F', 'M', 'S', 'U', 'B', 'S', 's', 0, | |
| /* 19214 */ 'Q', 'V', 'F', 'N', 'M', 'S', 'U', 'B', 'S', 's', 0, | |
| /* 19225 */ 'Q', 'V', 'F', 'A', 'D', 'D', 'S', 's', 0, | |
| /* 19234 */ 'Q', 'V', 'F', 'M', 'A', 'D', 'D', 'S', 's', 0, | |
| /* 19244 */ 'Q', 'V', 'F', 'N', 'M', 'A', 'D', 'D', 'S', 's', 0, | |
| /* 19255 */ 'X', 'S', 'C', 'V', 'D', 'P', 'S', 'X', 'D', 'S', 's', 0, | |
| /* 19267 */ 'X', 'S', 'C', 'V', 'D', 'P', 'U', 'X', 'D', 'S', 's', 0, | |
| /* 19279 */ 'Q', 'V', 'F', 'R', 'E', 'S', 's', 0, | |
| /* 19287 */ 'Q', 'V', 'F', 'R', 'S', 'Q', 'R', 'T', 'E', 'S', 's', 0, | |
| /* 19299 */ 'Q', 'V', 'F', 'M', 'U', 'L', 'S', 's', 0, | |
| /* 19308 */ 'X', 'S', 'C', 'V', 'D', 'P', 'S', 'X', 'W', 'S', 's', 0, | |
| /* 19320 */ 'X', 'S', 'C', 'V', 'D', 'P', 'U', 'X', 'W', 'S', 's', 0, | |
| /* 19332 */ 'V', 'E', 'X', 'T', 'S', 'B', '2', 'W', 's', 0, | |
| /* 19342 */ 'V', 'E', 'X', 'T', 'S', 'H', '2', 'W', 's', 0, | |
| /* 19352 */ 'X', 'X', 'S', 'P', 'L', 'T', 'W', 's', 0, | |
| /* 19361 */ 'Q', 'V', 'L', 'F', 'C', 'S', 'X', 's', 0, | |
| /* 19370 */ 'Q', 'V', 'S', 'T', 'F', 'C', 'S', 'X', 's', 0, | |
| /* 19380 */ 'Q', 'V', 'L', 'F', 'S', 'X', 's', 0, | |
| /* 19388 */ 'Q', 'V', 'S', 'T', 'F', 'S', 'X', 's', 0, | |
| /* 19397 */ 'Q', 'V', 'S', 'T', 'F', 'S', 'U', 'X', 's', 0, | |
| /* 19407 */ 'Q', 'V', 'F', 'R', 'I', 'Z', 's', 0, | |
| /* 19415 */ 'Q', 'V', 'F', 'S', 'E', 'L', 'b', 's', 0, | |
| /* 19424 */ 'Q', 'V', 'F', 'T', 'S', 'T', 'N', 'A', 'N', 'b', 's', 0, | |
| /* 19436 */ 'Q', 'V', 'F', 'C', 'M', 'P', 'E', 'Q', 'b', 's', 0, | |
| /* 19447 */ 'Q', 'V', 'F', 'C', 'M', 'P', 'G', 'T', 'b', 's', 0, | |
| /* 19458 */ 'Q', 'V', 'F', 'C', 'M', 'P', 'L', 'T', 'b', 's', 0, | |
| /* 19469 */ 'X', 'X', 'L', 'E', 'Q', 'V', 'O', 'n', 'e', 's', 0, | |
| /* 19480 */ 'B', 'C', 'L', 'a', 'l', 'w', 'a', 'y', 's', 0, | |
| /* 19490 */ 'g', 'B', 'C', 'A', 'a', 't', 0, | |
| /* 19497 */ 'g', 'B', 'C', 'L', 'A', 'a', 't', 0, | |
| /* 19505 */ 'g', 'B', 'C', 'a', 't', 0, | |
| /* 19511 */ 'g', 'B', 'C', 'L', 'a', 't', 0, | |
| /* 19518 */ 'Q', 'V', 'L', 'P', 'C', 'L', 'S', 'X', 'i', 'n', 't', 0, | |
| /* 19530 */ 'M', 'F', 'V', 'R', 'S', 'A', 'V', 'E', 'v', 0, | |
| /* 19540 */ 'M', 'T', 'V', 'R', 'S', 'A', 'V', 'E', 'v', 0, | |
| /* 19550 */ 'S', 'T', 'X', 'S', 'I', 'B', 'X', 'v', 0, | |
| /* 19559 */ 'S', 'T', 'X', 'S', 'I', 'H', 'X', 'v', 0, | |
| /* 19568 */ 'L', 'A', 'x', 0, | |
| /* 19572 */ 'C', 'P', '_', 'P', 'A', 'S', 'T', 'E', 'x', 0, | |
| /* 19582 */ 'D', 'C', 'B', 'F', 'x', 0, | |
| /* 19588 */ 'D', 'C', 'B', 'T', 'x', 0, | |
| /* 19594 */ 'D', 'C', 'B', 'T', 'S', 'T', 'x', 0, | |
| /* 19602 */ 'C', 'P', '_', 'C', 'O', 'P', 'Y', 'x', 0, | |
| /* 19611 */ 'X', 'X', 'L', 'X', 'O', 'R', 'z', 0, | |
| /* 19619 */ 'X', 'X', 'L', 'X', 'O', 'R', 'd', 'p', 'z', 0, | |
| /* 19629 */ 'X', 'X', 'L', 'X', 'O', 'R', 's', 'p', 'z', 0, | |
| /* 19639 */ 'F', 'A', 'D', 'D', 'r', 't', 'z', 0, | |
| }; | |
| extern const unsigned PPCInstrNameIndices[] = { | |
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| 5737U, 5752U, 5474U, 5779U, 11881U, 5292U, 6953U, 5027U, | |
| 15512U, 5159U, 12861U, 4700U, 8499U, 7128U, 12769U, 4772U, | |
| 12758U, 5179U, 9579U, 9566U, 10730U, 12386U, 12598U, 7060U, | |
| 7107U, 7080U, 6996U, 4396U, 3591U, 7276U, 13311U, 13324U, | |
| 7476U, 7483U, 4673U, 11042U, 11020U, 5472U, 6354U, 14674U, | |
| 5302U, 12338U, 11496U, 12876U, 11513U, 10955U, 3820U, 11864U, | |
| 12780U, 11136U, 12916U, 3794U, 4743U, 10755U, 4255U, 4199U, | |
| 4229U, 4240U, 4180U, 4210U, 5245U, 5229U, 11919U, 5793U, | |
| 5810U, 4412U, 3597U, 4679U, 4644U, 11047U, 11026U, 14474U, | |
| 7943U, 14457U, 7926U, 4303U, 3542U, 5019U, 4727U, 12357U, | |
| 3760U, 11965U, 13074U, 3812U, 12747U, 12735U, 12851U, 5834U, | |
| 13067U, 5766U, 13083U, 7046U, 10814U, 10807U, 9508U, 9501U, | |
| 12348U, 8193U, 5055U, 8164U, 5011U, 8185U, 5047U, 8156U, | |
| 5003U, 8337U, 8329U, 5909U, 5901U, 4296U, 3535U, 7246U, | |
| 2987U, 4162U, 13289U, 7469U, 14061U, 10359U, 652U, 5827U, | |
| 644U, 0U, 5709U, 13059U, 3784U, 6581U, 6668U, 9396U, | |
| 9405U, 11161U, 7878U, 5410U, 7704U, 7714U, 5069U, 5084U, | |
| 7682U, 7693U, 4402U, 6896U, 7912U, 14443U, 7919U, 14450U, | |
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| 3296U, 4607U, 5917U, 13854U, 3445U, 4891U, 6036U, 14191U, | |
| 4274U, 10374U, 13696U, 9364U, 7543U, 7899U, 9457U, 15583U, | |
| 3286U, 4569U, 6381U, 7580U, 5891U, 13834U, 6481U, 7594U, | |
| 9379U, 14850U, 7029U, 4169U, 13679U, 7228U, 3291U, 4574U, | |
| 6516U, 5896U, 8324U, 13331U, 13840U, 3438U, 19014U, 6029U, | |
| 19060U, 3372U, 5973U, 14113U, 14176U, 11097U, 3219U, 4262U, | |
| 5850U, 13690U, 3330U, 4804U, 5931U, 8443U, 13355U, 14079U, | |
| 10494U, 14226U, 10521U, 7617U, 9325U, 11231U, 11570U, 12112U, | |
| 7428U, 11256U, 7453U, 7499U, 11616U, 7601U, 7732U, 12136U, | |
| 12103U, 11222U, 11561U, 11247U, 12128U, 14928U, 3364U, 5965U, | |
| 14105U, 14942U, 3381U, 5982U, 14122U, 11015U, 16U, 3211U, | |
| 5842U, 11465U, 3343U, 5944U, 12531U, 5107U, 6304U, 10995U, | |
| 2095U, 16311U, 6551U, 1736U, 11673U, 2165U, 17953U, 9093U, | |
| 9764U, 8663U, 9647U, 8406U, 9918U, 9055U, 9026U, 9735U, | |
| 8719U, 9109U, 8963U, 9708U, 9167U, 9781U, 8927U, 9698U, | |
| 9439U, 9717U, 10155U, 8013U, 11399U, 19255U, 12160U, 19308U, | |
| 11432U, 19267U, 12193U, 19320U, 8972U, 8981U, 8345U, 15559U, | |
| 15761U, 15569U, 15771U, 9655U, 8990U, 8003U, 8679U, 9934U, | |
| 9664U, 8699U, 9954U, 9176U, 9790U, 8434U, 10291U, 9008U, | |
| 9726U, 8589U, 9862U, 8907U, 10117U, 9638U, 8396U, 8654U, | |
| 9230U, 8818U, 8645U, 8947U, 8809U, 8547U, 9820U, 8865U, | |
| 10075U, 9601U, 8366U, 8827U, 9690U, 8415U, 10037U, 9075U, | |
| 9755U, 8775U, 9673U, 8567U, 9840U, 8885U, 10095U, 9628U, | |
| 8385U, 8525U, 9798U, 8843U, 10053U, 9591U, 8355U, 6523U, | |
| 3736U, 7549U, 9463U, 15589U, 8739U, 9984U, 6537U, 14810U, | |
| 10366U, 10217U, 8753U, 9998U, 9129U, 9772U, 8424U, 10263U, | |
| 8609U, 9610U, 8376U, 9882U, 9184U, 9138U, 8625U, 9618U, | |
| 9898U, 9037U, 9746U, 8791U, 9681U, 9101U, 10232U, 8671U, | |
| 9926U, 9065U, 17762U, 10200U, 17855U, 8729U, 17748U, 9974U, | |
| 17841U, 9119U, 17776U, 10253U, 17878U, 8937U, 10137U, 10164U, | |
| 11410U, 12171U, 11443U, 12204U, 10173U, 8999U, 9448U, 11421U, | |
| 12182U, 11454U, 12215U, 8689U, 9944U, 9210U, 10316U, 8709U, | |
| 9964U, 9220U, 10326U, 9202U, 10308U, 9017U, 10182U, 8599U, | |
| 9872U, 8917U, 10127U, 9238U, 10336U, 8955U, 10147U, 8557U, | |
| 9830U, 8875U, 10085U, 8835U, 10045U, 9084U, 10223U, 8783U, | |
| 10020U, 8578U, 9851U, 8896U, 10106U, 8536U, 9809U, 8854U, | |
| 10064U, 6530U, 3744U, 7557U, 9471U, 15597U, 8746U, 9991U, | |
| 6544U, 3752U, 7565U, 9479U, 15605U, 8764U, 10009U, 9158U, | |
| 10282U, 8617U, 9890U, 9193U, 10299U, 9148U, 10272U, 8635U, | |
| 9908U, 9046U, 10191U, 8800U, 10028U, 4789U, 5925U, 10469U, | |
| 14073U, 14306U, 14209U, 4615U, 3674U, 13336U, 19469U, 4622U, | |
| 10922U, 10916U, 3986U, 18683U, 10992U, 19619U, 19629U, 19611U, | |
| 13776U, 13813U, 7649U, 6257U, 19068U, 10908U, 7034U, 6708U, | |
| 19099U, 3264U, 14183U, 19352U, 3661U, 2611U, 19490U, 11110U, | |
| 7205U, 6921U, 2962U, 19497U, 10825U, 7170U, 19511U, 19505U, | |
| }; | |
| static inline void InitPPCMCInstrInfo(MCInstrInfo *II) { | |
| II->InitMCInstrInfo(PPCInsts, PPCInstrNameIndices, PPCInstrNameData, 2288); | |
| } | |
| } // end namespace llvm | |
| #endif // GET_INSTRINFO_MC_DESC | |
| #ifdef GET_INSTRINFO_HEADER | |
| #undef GET_INSTRINFO_HEADER | |
| namespace llvm { | |
| struct PPCGenInstrInfo : public TargetInstrInfo { | |
| explicit PPCGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1); | |
| ~PPCGenInstrInfo() override = default; | |
| }; | |
| } // end namespace llvm | |
| #endif // GET_INSTRINFO_HEADER | |
| #ifdef GET_INSTRINFO_HELPER_DECLS | |
| #undef GET_INSTRINFO_HELPER_DECLS | |
| #endif // GET_INSTRINFO_HELPER_DECLS | |
| #ifdef GET_INSTRINFO_HELPERS | |
| #undef GET_INSTRINFO_HELPERS | |
| #endif // GET_INSTRINFO_HELPERS | |
| #ifdef GET_INSTRINFO_CTOR_DTOR | |
| #undef GET_INSTRINFO_CTOR_DTOR | |
| namespace llvm { | |
| extern const MCInstrDesc PPCInsts[]; | |
| extern const unsigned PPCInstrNameIndices[]; | |
| extern const char PPCInstrNameData[]; | |
| PPCGenInstrInfo::PPCGenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode) | |
| : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) { | |
| InitMCInstrInfo(PPCInsts, PPCInstrNameIndices, PPCInstrNameData, 2288); | |
| } | |
| } // end namespace llvm | |
| #endif // GET_INSTRINFO_CTOR_DTOR | |
| #ifdef GET_INSTRINFO_OPERAND_ENUM | |
| #undef GET_INSTRINFO_OPERAND_ENUM | |
| namespace llvm { | |
| namespace PPC { | |
| namespace OpName { | |
| enum { | |
| OPERAND_LAST | |
| }; | |
| } // end namespace OpName | |
| } // end namespace PPC | |
| } // end namespace llvm | |
| #endif //GET_INSTRINFO_OPERAND_ENUM | |
| #ifdef GET_INSTRINFO_NAMED_OPS | |
| #undef GET_INSTRINFO_NAMED_OPS | |
| namespace llvm { | |
| namespace PPC { | |
| LLVM_READONLY | |
| int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) { | |
| return -1; | |
| } | |
| } // end namespace PPC | |
| } // end namespace llvm | |
| #endif //GET_INSTRINFO_NAMED_OPS | |
| #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM | |
| #undef GET_INSTRINFO_OPERAND_TYPES_ENUM | |
| namespace llvm { | |
| namespace PPC { | |
| namespace OpTypes { | |
| enum OperandType { | |
| abscalltarget = 0, | |
| abscondbrtarget = 1, | |
| absdirectbrtarget = 2, | |
| atimm = 3, | |
| calltarget = 4, | |
| condbrtarget = 5, | |
| crbitm = 6, | |
| directbrtarget = 7, | |
| dispRI = 8, | |
| dispRIX = 9, | |
| dispRIX16 = 10, | |
| dispSPE2 = 11, | |
| dispSPE4 = 12, | |
| dispSPE8 = 13, | |
| f32imm = 14, | |
| f64imm = 15, | |
| i16imm = 16, | |
| i1imm = 17, | |
| i32imm = 18, | |
| i64imm = 19, | |
| i8imm = 20, | |
| imm32SExt16 = 21, | |
| imm64SExt16 = 22, | |
| imm64ZExt32 = 23, | |
| memr = 24, | |
| memri = 25, | |
| memrix = 26, | |
| memrix16 = 27, | |
| memrr = 28, | |
| pred = 29, | |
| ptr_rc_idx = 30, | |
| ptr_rc_nor0 = 31, | |
| ptype0 = 32, | |
| ptype1 = 33, | |
| ptype2 = 34, | |
| ptype3 = 35, | |
| ptype4 = 36, | |
| ptype5 = 37, | |
| s16imm = 38, | |
| s16imm64 = 39, | |
| s17imm = 40, | |
| s17imm64 = 41, | |
| s5imm = 42, | |
| spe2dis = 43, | |
| spe4dis = 44, | |
| spe8dis = 45, | |
| tlscall = 46, | |
| tlscall32 = 47, | |
| tlsgd = 48, | |
| tlsgd32 = 49, | |
| tlsreg = 50, | |
| tlsreg32 = 51, | |
| tocentry = 52, | |
| tocentry32 = 53, | |
| type0 = 54, | |
| type1 = 55, | |
| type2 = 56, | |
| type3 = 57, | |
| type4 = 58, | |
| type5 = 59, | |
| u10imm = 60, | |
| u12imm = 61, | |
| u16imm = 62, | |
| u16imm64 = 63, | |
| u1imm = 64, | |
| u2imm = 65, | |
| u3imm = 66, | |
| u4imm = 67, | |
| u5imm = 68, | |
| u6imm = 69, | |
| u7imm = 70, | |
| u8imm = 71, | |
| untyped_imm_0 = 72, | |
| crbitrc = 73, | |
| crrc = 74, | |
| f4rc = 75, | |
| f8rc = 76, | |
| g8rc = 77, | |
| g8rc_nox0 = 78, | |
| gprc = 79, | |
| gprc_nor0 = 80, | |
| qbrc = 81, | |
| qfrc = 82, | |
| qsrc = 83, | |
| spe4rc = 84, | |
| sperc = 85, | |
| spilltovsrrc = 86, | |
| vfrc = 87, | |
| vrrc = 88, | |
| vsfrc = 89, | |
| vsrc = 90, | |
| vssrc = 91, | |
| CARRYRC = 92, | |
| CRBITRC = 93, | |
| CRRC = 94, | |
| CTRRC = 95, | |
| CTRRC8 = 96, | |
| F4RC = 97, | |
| F8RC = 98, | |
| G8RC = 99, | |
| G8RC_NOX0 = 100, | |
| GPRC = 101, | |
| GPRC_NOR0 = 102, | |
| QBRC = 103, | |
| QFRC = 104, | |
| QSRC = 105, | |
| SPERC = 106, | |
| SPILLTOVSRRC = 107, | |
| VFRC = 108, | |
| VRRC = 109, | |
| VRSAVERC = 110, | |
| VSFRC = 111, | |
| VSLRC = 112, | |
| VSRC = 113, | |
| VSSRC = 114, | |
| OPERAND_TYPE_LIST_END | |
| }; | |
| } // end namespace OpTypes | |
| } // end namespace PPC | |
| } // end namespace llvm | |
| #endif // GET_INSTRINFO_OPERAND_TYPES_ENUM | |
| #ifdef GET_INSTRINFO_OPERAND_TYPE | |
| #undef GET_INSTRINFO_OPERAND_TYPE | |
| namespace llvm { | |
| namespace PPC { | |
| LLVM_READONLY | |
| static int getOperandType(uint16_t Opcode, uint16_t OpIdx) { | |
| const int Offsets[] = { | |
| 0, | |
| 1, | |
| 1, | |
| 1, | |
| 2, | |
| 3, | |
| 4, | |
| 5, | |
| 5, | |
| 8, | |
| 12, | |
| 13, | |
| 17, | |
| 20, | |
| 20, | |
| 21, | |
| 23, | |
| 25, | |
| 25, | |
| 26, | |
| 27, | |
| 29, | |
| 29, | |
| 35, | |
| 36, | |
| 36, | |
| 38, | |
| 39, | |
| 39, | |
| 39, | |
| 39, | |
| 39, | |
| 39, | |
| 41, | |
| 44, | |
| 44, | |
| 47, | |
| 50, | |
| 53, | |
| 56, | |
| 59, | |
| 62, | |
| 65, | |
| 68, | |
| 71, | |
| 74, | |
| 75, | |
| 76, | |
| 78, | |
| 80, | |
| 83, | |
| 85, | |
| 89, | |
| 91, | |
| 93, | |
| 95, | |
| 97, | |
| 99, | |
| 101, | |
| 103, | |
| 105, | |
| 107, | |
| 108, | |
| 110, | |
| 112, | |
| 114, | |
| 119, | |
| 124, | |
| 129, | |
| 131, | |
| 136, | |
| 141, | |
| 145, | |
| 148, | |
| 151, | |
| 154, | |
| 157, | |
| 160, | |
| 163, | |
| 166, | |
| 169, | |
| 172, | |
| 175, | |
| 178, | |
| 181, | |
| 184, | |
| 186, | |
| 188, | |
| 189, | |
| 190, | |
| 191, | |
| 193, | |
| 195, | |
| 197, | |
| 199, | |
| 200, | |
| 203, | |
| 205, | |
| 208, | |
| 210, | |
| 213, | |
| 216, | |
| 219, | |
| 223, | |
| 227, | |
| 231, | |
| 235, | |
| 240, | |
| 244, | |
| 249, | |
| 253, | |
| 258, | |
| 262, | |
| 267, | |
| 271, | |
| 275, | |
| 278, | |
| 281, | |
| 284, | |
| 287, | |
| 290, | |
| 294, | |
| 298, | |
| 301, | |
| 304, | |
| 307, | |
| 309, | |
| 311, | |
| 313, | |
| 315, | |
| 317, | |
| 319, | |
| 321, | |
| 323, | |
| 325, | |
| 327, | |
| 329, | |
| 331, | |
| 333, | |
| 336, | |
| 338, | |
| 341, | |
| 344, | |
| 347, | |
| 350, | |
| 353, | |
| 356, | |
| 359, | |
| 362, | |
| 365, | |
| 368, | |
| 371, | |
| 374, | |
| 375, | |
| 378, | |
| 382, | |
| 385, | |
| 389, | |
| 391, | |
| 393, | |
| 395, | |
| 397, | |
| 399, | |
| 401, | |
| 403, | |
| 405, | |
| 407, | |
| 409, | |
| 411, | |
| 413, | |
| 415, | |
| 417, | |
| 419, | |
| 421, | |
| 423, | |
| 426, | |
| 428, | |
| 430, | |
| 431, | |
| 435, | |
| 439, | |
| 443, | |
| 447, | |
| 450, | |
| 453, | |
| 456, | |
| 459, | |
| 461, | |
| 463, | |
| 465, | |
| 467, | |
| 469, | |
| 471, | |
| 473, | |
| 476, | |
| 479, | |
| 482, | |
| 485, | |
| 487, | |
| 489, | |
| 491, | |
| 493, | |
| 496, | |
| 499, | |
| 502, | |
| 505, | |
| 509, | |
| 513, | |
| 517, | |
| 521, | |
| 525, | |
| 529, | |
| 533, | |
| 537, | |
| 541, | |
| 545, | |
| 549, | |
| 553, | |
| 557, | |
| 561, | |
| 564, | |
| 567, | |
| 570, | |
| 574, | |
| 578, | |
| 582, | |
| 586, | |
| 590, | |
| 594, | |
| 597, | |
| 600, | |
| 603, | |
| 606, | |
| 609, | |
| 612, | |
| 615, | |
| 618, | |
| 621, | |
| 624, | |
| 627, | |
| 630, | |
| 633, | |
| 636, | |
| 639, | |
| 642, | |
| 645, | |
| 648, | |
| 651, | |
| 654, | |
| 657, | |
| 659, | |
| 662, | |
| 665, | |
| 668, | |
| 671, | |
| 674, | |
| 677, | |
| 680, | |
| 683, | |
| 686, | |
| 689, | |
| 692, | |
| 695, | |
| 698, | |
| 701, | |
| 704, | |
| 707, | |
| 710, | |
| 713, | |
| 716, | |
| 719, | |
| 722, | |
| 725, | |
| 728, | |
| 731, | |
| 734, | |
| 737, | |
| 740, | |
| 743, | |
| 746, | |
| 749, | |
| 752, | |
| 755, | |
| 758, | |
| 761, | |
| 764, | |
| 767, | |
| 770, | |
| 773, | |
| 776, | |
| 779, | |
| 782, | |
| 785, | |
| 788, | |
| 791, | |
| 794, | |
| 797, | |
| 800, | |
| 803, | |
| 806, | |
| 810, | |
| 814, | |
| 817, | |
| 820, | |
| 824, | |
| 828, | |
| 831, | |
| 833, | |
| 835, | |
| 837, | |
| 839, | |
| 841, | |
| 843, | |
| 845, | |
| 847, | |
| 849, | |
| 851, | |
| 853, | |
| 855, | |
| 857, | |
| 859, | |
| 861, | |
| 863, | |
| 865, | |
| 867, | |
| 869, | |
| 872, | |
| 875, | |
| 878, | |
| 881, | |
| 884, | |
| 887, | |
| 890, | |
| 893, | |
| 896, | |
| 899, | |
| 902, | |
| 904, | |
| 906, | |
| 908, | |
| 910, | |
| 913, | |
| 918, | |
| 923, | |
| 928, | |
| 933, | |
| 937, | |
| 941, | |
| 945, | |
| 949, | |
| 953, | |
| 957, | |
| 961, | |
| 965, | |
| 969, | |
| 973, | |
| 977, | |
| 981, | |
| 985, | |
| 989, | |
| 993, | |
| 997, | |
| 1001, | |
| 1005, | |
| 1009, | |
| 1013, | |
| 1017, | |
| 1021, | |
| 1025, | |
| 1029, | |
| 1033, | |
| 1037, | |
| 1041, | |
| 1045, | |
| 1049, | |
| 1053, | |
| 1057, | |
| 1061, | |
| 1065, | |
| 1069, | |
| 1073, | |
| 1077, | |
| 1081, | |
| 1085, | |
| 1089, | |
| 1093, | |
| 1097, | |
| 1101, | |
| 1105, | |
| 1109, | |
| 1109, | |
| 1110, | |
| 1111, | |
| 1113, | |
| 1116, | |
| 1119, | |
| 1121, | |
| 1123, | |
| 1125, | |
| 1127, | |
| 1130, | |
| 1133, | |
| 1135, | |
| 1137, | |
| 1138, | |
| 1139, | |
| 1140, | |
| 1141, | |
| 1142, | |
| 1143, | |
| 1144, | |
| 1145, | |
| 1148, | |
| 1151, | |
| 1154, | |
| 1157, | |
| 1159, | |
| 1161, | |
| 1164, | |
| 1167, | |
| 1171, | |
| 1175, | |
| 1179, | |
| 1182, | |
| 1185, | |
| 1187, | |
| 1188, | |
| 1189, | |
| 1190, | |
| 1191, | |
| 1192, | |
| 1194, | |
| 1194, | |
| 1194, | |
| 1194, | |
| 1194, | |
| 1196, | |
| 1198, | |
| 1200, | |
| 1201, | |
| 1202, | |
| 1203, | |
| 1204, | |
| 1205, | |
| 1206, | |
| 1207, | |
| 1208, | |
| 1209, | |
| 1209, | |
| 1209, | |
| 1209, | |
| 1209, | |
| 1209, | |
| 1209, | |
| 1209, | |
| 1210, | |
| 1211, | |
| 1212, | |
| 1213, | |
| 1214, | |
| 1215, | |
| 1216, | |
| 1217, | |
| 1218, | |
| 1219, | |
| 1220, | |
| 1221, | |
| 1222, | |
| 1222, | |
| 1222, | |
| 1222, | |
| 1222, | |
| 1222, | |
| 1222, | |
| 1222, | |
| 1223, | |
| 1224, | |
| 1225, | |
| 1226, | |
| 1227, | |
| 1228, | |
| 1229, | |
| 1231, | |
| 1233, | |
| 1235, | |
| 1236, | |
| 1237, | |
| 1238, | |
| 1238, | |
| 1238, | |
| 1238, | |
| 1239, | |
| 1241, | |
| 1244, | |
| 1247, | |
| 1247, | |
| 1250, | |
| 1253, | |
| 1256, | |
| 1259, | |
| 1262, | |
| 1265, | |
| 1268, | |
| 1271, | |
| 1274, | |
| 1278, | |
| 1282, | |
| 1285, | |
| 1288, | |
| 1290, | |
| 1292, | |
| 1294, | |
| 1296, | |
| 1298, | |
| 1300, | |
| 1302, | |
| 1304, | |
| 1306, | |
| 1308, | |
| 1310, | |
| 1312, | |
| 1312, | |
| 1315, | |
| 1318, | |
| 1321, | |
| 1324, | |
| 1327, | |
| 1330, | |
| 1330, | |
| 1330, | |
| 1333, | |
| 1336, | |
| 1339, | |
| 1342, | |
| 1345, | |
| 1348, | |
| 1351, | |
| 1352, | |
| 1353, | |
| 1356, | |
| 1359, | |
| 1361, | |
| 1363, | |
| 1366, | |
| 1368, | |
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| 4237, | |
| 4240, | |
| 4243, | |
| 4246, | |
| 4249, | |
| 4253, | |
| 4257, | |
| 4260, | |
| 4263, | |
| 4266, | |
| 4270, | |
| 4274, | |
| 4277, | |
| 4280, | |
| 4283, | |
| 4286, | |
| 4289, | |
| 4292, | |
| 4295, | |
| 4299, | |
| 4303, | |
| 4307, | |
| 4311, | |
| 4314, | |
| 4317, | |
| 4320, | |
| 4323, | |
| 4326, | |
| 4329, | |
| 4329, | |
| 4332, | |
| 4335, | |
| 4338, | |
| 4341, | |
| 4344, | |
| 4347, | |
| 4350, | |
| 4353, | |
| 4356, | |
| 4359, | |
| 4362, | |
| 4365, | |
| 4368, | |
| 4372, | |
| 4376, | |
| 4380, | |
| 4384, | |
| 4387, | |
| 4390, | |
| 4393, | |
| 4396, | |
| 4399, | |
| 4402, | |
| 4405, | |
| 4408, | |
| 4411, | |
| 4414, | |
| 4417, | |
| 4420, | |
| 4423, | |
| 4426, | |
| 4429, | |
| 4432, | |
| 4435, | |
| 4438, | |
| 4441, | |
| 4444, | |
| 4447, | |
| 4450, | |
| 4453, | |
| 4456, | |
| 4459, | |
| 4462, | |
| 4465, | |
| 4468, | |
| 4471, | |
| 4474, | |
| 4477, | |
| 4480, | |
| 4483, | |
| 4486, | |
| 4489, | |
| 4492, | |
| 4495, | |
| 4498, | |
| 4501, | |
| 4504, | |
| 4507, | |
| 4510, | |
| 4513, | |
| 4516, | |
| 4519, | |
| 4521, | |
| 4523, | |
| 4525, | |
| 4527, | |
| 4529, | |
| 4531, | |
| 4533, | |
| 4535, | |
| 4538, | |
| 4541, | |
| 4543, | |
| 4545, | |
| 4547, | |
| 4549, | |
| 4551, | |
| 4553, | |
| 4555, | |
| 4557, | |
| 4560, | |
| 4561, | |
| 4562, | |
| 4565, | |
| 4568, | |
| 4571, | |
| 4574, | |
| 4575, | |
| 4576, | |
| 4577, | |
| 4578, | |
| 4578, | |
| 4578, | |
| 4579, | |
| 4581, | |
| 4582, | |
| 4583, | |
| 4585, | |
| 4587, | |
| 4589, | |
| 4591, | |
| 4593, | |
| 4595, | |
| 4598, | |
| 4601, | |
| 4602, | |
| 4602, | |
| 4604, | |
| 4605, | |
| 4607, | |
| 4608, | |
| 4609, | |
| 4609, | |
| 4612, | |
| 4614, | |
| 4617, | |
| 4620, | |
| 4620, | |
| 4620, | |
| 4623, | |
| 4623, | |
| 4623, | |
| 4624, | |
| 4625, | |
| 4628, | |
| 4631, | |
| 4631, | |
| 4633, | |
| 4636, | |
| 4639, | |
| 4642, | |
| 4645, | |
| 4648, | |
| 4651, | |
| 4655, | |
| 4659, | |
| 4662, | |
| 4665, | |
| 4668, | |
| 4671, | |
| 4674, | |
| 4677, | |
| 4680, | |
| 4683, | |
| 4686, | |
| 4689, | |
| 4692, | |
| 4695, | |
| 4698, | |
| 4701, | |
| 4704, | |
| 4707, | |
| 4710, | |
| 4713, | |
| 4716, | |
| 4719, | |
| 4722, | |
| 4725, | |
| 4728, | |
| 4730, | |
| 4733, | |
| 4735, | |
| 4738, | |
| 4741, | |
| 4743, | |
| 4745, | |
| 4747, | |
| 4749, | |
| 4751, | |
| 4754, | |
| 4757, | |
| 4760, | |
| 4763, | |
| 4766, | |
| 4769, | |
| 4772, | |
| 4775, | |
| 4778, | |
| 4781, | |
| 4784, | |
| 4787, | |
| 4790, | |
| 4793, | |
| 4796, | |
| 4799, | |
| 4802, | |
| 4805, | |
| 4808, | |
| 4811, | |
| 4814, | |
| 4817, | |
| 4820, | |
| 4823, | |
| 4826, | |
| 4829, | |
| 4832, | |
| 4835, | |
| 4838, | |
| 4841, | |
| 4844, | |
| 4847, | |
| 4850, | |
| 4853, | |
| 4856, | |
| 4859, | |
| 4862, | |
| 4865, | |
| 4868, | |
| 4871, | |
| 4874, | |
| 4877, | |
| 4880, | |
| 4883, | |
| 4886, | |
| 4888, | |
| 4891, | |
| 4893, | |
| 4895, | |
| 4897, | |
| 4899, | |
| 4901, | |
| 4903, | |
| 4906, | |
| 4908, | |
| 4911, | |
| 4914, | |
| 4917, | |
| 4920, | |
| 4922, | |
| 4924, | |
| 4926, | |
| 4928, | |
| 4930, | |
| 4932, | |
| 4934, | |
| 4936, | |
| 4938, | |
| 4940, | |
| 4943, | |
| 4946, | |
| 4949, | |
| 4952, | |
| 4955, | |
| 4958, | |
| 4960, | |
| 4964, | |
| 4967, | |
| 4971, | |
| 4974, | |
| 4976, | |
| 4980, | |
| 4983, | |
| 4986, | |
| 4989, | |
| 4992, | |
| 4995, | |
| 4998, | |
| 5001, | |
| 5004, | |
| 5007, | |
| 5011, | |
| 5015, | |
| 5018, | |
| 5021, | |
| 5024, | |
| 5027, | |
| 5030, | |
| 5033, | |
| 5036, | |
| 5039, | |
| 5042, | |
| 5046, | |
| 5049, | |
| 5052, | |
| 5055, | |
| 5058, | |
| 5061, | |
| 5064, | |
| 5067, | |
| 5070, | |
| 5074, | |
| 5078, | |
| 5082, | |
| 5086, | |
| 5090, | |
| 5094, | |
| 5096, | |
| 5099, | |
| 5102, | |
| 5104, | |
| 5107, | |
| 5110, | |
| 5113, | |
| 5116, | |
| 5119, | |
| 5122, | |
| 5125, | |
| 5128, | |
| 5131, | |
| 5134, | |
| 5137, | |
| 5140, | |
| 5143, | |
| 5146, | |
| 5149, | |
| 5152, | |
| 5154, | |
| 5156, | |
| 5160, | |
| 5163, | |
| 5166, | |
| 5169, | |
| 5173, | |
| 5177, | |
| 5181, | |
| 5184, | |
| 5187, | |
| 5190, | |
| 5193, | |
| 5196, | |
| 5199, | |
| 5202, | |
| 5205, | |
| 5208, | |
| 5211, | |
| 5214, | |
| 5217, | |
| 5220, | |
| 5223, | |
| 5226, | |
| 5229, | |
| 5232, | |
| 5234, | |
| 5236, | |
| 5238, | |
| 5240, | |
| 5242, | |
| 5244, | |
| 5246, | |
| 5248, | |
| 5250, | |
| 5252, | |
| 5254, | |
| 5256, | |
| 5259, | |
| 5262, | |
| 5266, | |
| 5269, | |
| 5272, | |
| 5275, | |
| 5279, | |
| 5282, | |
| 5284, | |
| 5286, | |
| 5290, | |
| 5294, | |
| 5298, | |
| 5301, | |
| 5304, | |
| 5307, | |
| 5311, | |
| 5314, | |
| 5317, | |
| 5320, | |
| 5323, | |
| 5326, | |
| 5329, | |
| 5332, | |
| 5335, | |
| 5337, | |
| 5339, | |
| 5341, | |
| 5344, | |
| 5347, | |
| 5350, | |
| 5353, | |
| 5356, | |
| 5359, | |
| 5362, | |
| 5365, | |
| 5368, | |
| 5371, | |
| 5374, | |
| 5377, | |
| 5380, | |
| 5383, | |
| 5387, | |
| 5391, | |
| 5394, | |
| 5397, | |
| 5400, | |
| 5403, | |
| 5406, | |
| 5409, | |
| 5412, | |
| 5415, | |
| 5418, | |
| 5421, | |
| 5424, | |
| 5427, | |
| 5430, | |
| 5433, | |
| 5436, | |
| 5439, | |
| 5442, | |
| 5444, | |
| 5446, | |
| 5448, | |
| 5450, | |
| 5452, | |
| 5454, | |
| 5456, | |
| 5458, | |
| 5461, | |
| 5462, | |
| 5463, | |
| 5464, | |
| 5465, | |
| 5466, | |
| 5467, | |
| 5468, | |
| 5469, | |
| 5470, | |
| 5473, | |
| 5476, | |
| 5479, | |
| 5482, | |
| 5485, | |
| 5488, | |
| 5491, | |
| 5494, | |
| 5496, | |
| 5498, | |
| 5501, | |
| 5504, | |
| 5507, | |
| 5510, | |
| 5513, | |
| 5516, | |
| 5519, | |
| 5522, | |
| 5525, | |
| 5528, | |
| 5531, | |
| 5534, | |
| 5537, | |
| 5540, | |
| 5543, | |
| 5545, | |
| 5547, | |
| 5549, | |
| 5551, | |
| 5553, | |
| 5555, | |
| 5557, | |
| 5559, | |
| 5561, | |
| 5563, | |
| 5565, | |
| 5567, | |
| 5569, | |
| 5571, | |
| 5573, | |
| 5575, | |
| 5577, | |
| 5579, | |
| 5581, | |
| 5583, | |
| 5585, | |
| 5587, | |
| 5589, | |
| 5591, | |
| 5593, | |
| 5595, | |
| 5597, | |
| 5600, | |
| 5603, | |
| 5606, | |
| 5609, | |
| 5612, | |
| 5615, | |
| 5619, | |
| 5623, | |
| 5627, | |
| 5631, | |
| 5635, | |
| 5639, | |
| 5642, | |
| 5645, | |
| 5648, | |
| 5651, | |
| 5654, | |
| 5657, | |
| 5661, | |
| 5665, | |
| 5669, | |
| 5673, | |
| 5677, | |
| 5681, | |
| 5684, | |
| 5687, | |
| 5690, | |
| 5693, | |
| 5695, | |
| 5697, | |
| 5699, | |
| 5701, | |
| 5705, | |
| 5709, | |
| 5713, | |
| 5717, | |
| 5721, | |
| 5725, | |
| 5729, | |
| 5733, | |
| 5737, | |
| 5741, | |
| 5745, | |
| 5749, | |
| 5751, | |
| 5753, | |
| 5755, | |
| 5757, | |
| 5759, | |
| 5761, | |
| 5763, | |
| 5767, | |
| 5771, | |
| 5775, | |
| 5777, | |
| 5779, | |
| 5781, | |
| 5783, | |
| 5785, | |
| 5787, | |
| 5789, | |
| 5792, | |
| 5795, | |
| 5798, | |
| 5801, | |
| 5804, | |
| 5806, | |
| 5809, | |
| 5812, | |
| 5815, | |
| 5817, | |
| 5819, | |
| 5821, | |
| 5823, | |
| 5825, | |
| 5827, | |
| 5830, | |
| 5833, | |
| 5836, | |
| 5839, | |
| 5842, | |
| 5845, | |
| 5848, | |
| 5851, | |
| 5854, | |
| 5857, | |
| 5860, | |
| 5863, | |
| 5866, | |
| 5869, | |
| 5872, | |
| 5875, | |
| 5877, | |
| 5879, | |
| 5881, | |
| 5883, | |
| 5885, | |
| 5887, | |
| 5889, | |
| 5891, | |
| 5893, | |
| 5895, | |
| 5897, | |
| 5899, | |
| 5901, | |
| 5903, | |
| 5905, | |
| 5907, | |
| 5909, | |
| 5911, | |
| 5913, | |
| 5915, | |
| 5918, | |
| 5921, | |
| 5924, | |
| 5927, | |
| 5931, | |
| 5935, | |
| 5939, | |
| 5943, | |
| 5946, | |
| 5949, | |
| 5952, | |
| 5955, | |
| 5959, | |
| 5963, | |
| 5967, | |
| 5971, | |
| 5974, | |
| 5977, | |
| 5979, | |
| 5981, | |
| 5983, | |
| 5985, | |
| 5989, | |
| 5993, | |
| 5997, | |
| 6001, | |
| 6005, | |
| 6009, | |
| 6013, | |
| 6017, | |
| 6019, | |
| 6021, | |
| 6023, | |
| 6025, | |
| 6027, | |
| 6029, | |
| 6031, | |
| 6033, | |
| 6035, | |
| 6037, | |
| 6039, | |
| 6041, | |
| 6043, | |
| 6045, | |
| 6047, | |
| 6049, | |
| 6052, | |
| 6055, | |
| 6058, | |
| 6061, | |
| 6063, | |
| 6065, | |
| 6068, | |
| 6071, | |
| 6073, | |
| 6075, | |
| 6077, | |
| 6079, | |
| 6081, | |
| 6083, | |
| 6085, | |
| 6087, | |
| 6090, | |
| 6094, | |
| 6097, | |
| 6100, | |
| 6103, | |
| 6104, | |
| 6107, | |
| 6110, | |
| 6113, | |
| 6116, | |
| 6119, | |
| 6122, | |
| 6123, | |
| 6124, | |
| 6125, | |
| 6128, | |
| 6131, | |
| 6134, | |
| 6138, | |
| 6141, | |
| 6144, | |
| 6148, | |
| 6152, | |
| 6155, | |
| 6157, | |
| 6160, | |
| 6163, | |
| 6166, | |
| 6169, | |
| 6173, | |
| 6176, | |
| 6179, | |
| 6182, | |
| 6185, | |
| 6189, | |
| 6192, | |
| 6195, | |
| 6199, | |
| }; | |
| const int OpcodeOperandTypes[] = { | |
| -1, | |
| /**/ | |
| /**/ | |
| OpTypes::i32imm, | |
| OpTypes::i32imm, | |
| OpTypes::i32imm, | |
| OpTypes::i32imm, | |
| /**/ | |
| -1, -1, OpTypes::i32imm, | |
| -1, -1, -1, OpTypes::i32imm, | |
| -1, | |
| -1, -1, -1, OpTypes::i32imm, | |
| -1, -1, OpTypes::i32imm, | |
| /**/ | |
| -1, | |
| -1, -1, | |
| -1, -1, | |
| /**/ | |
| OpTypes::i32imm, | |
| OpTypes::i32imm, | |
| OpTypes::i64imm, OpTypes::i32imm, | |
| /**/ | |
| -1, OpTypes::i64imm, OpTypes::i32imm, -1, OpTypes::i32imm, OpTypes::i32imm, | |
| -1, | |
| /**/ | |
| -1, OpTypes::i32imm, | |
| -1, | |
| /**/ | |
| /**/ | |
| /**/ | |
| /**/ | |
| /**/ | |
| -1, -1, | |
| -1, -1, -1, | |
| /**/ | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, | |
| OpTypes::type0, | |
| OpTypes::type0, -1, | |
| OpTypes::type0, -1, | |
| OpTypes::type0, OpTypes::type1, -1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type1, -1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, | |
| OpTypes::type0, OpTypes::ptype1, | |
| OpTypes::type0, OpTypes::ptype1, | |
| OpTypes::type0, OpTypes::ptype1, | |
| OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1, | |
| OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1, | |
| OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1, | |
| OpTypes::type0, OpTypes::ptype1, | |
| OpTypes::ptype0, OpTypes::type1, OpTypes::ptype0, OpTypes::ptype2, -1, | |
| OpTypes::type0, OpTypes::type1, OpTypes::type2, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, | |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, | |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, | |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, | |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, | |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, | |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, | |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, | |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, | |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, | |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, | |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, | |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, | |
| OpTypes::i32imm, OpTypes::i32imm, | |
| OpTypes::type0, -1, | |
| OpTypes::type0, | |
| -1, | |
| -1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, -1, | |
| OpTypes::type0, -1, | |
| OpTypes::type0, | |
| OpTypes::type0, OpTypes::type1, -1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type0, OpTypes::untyped_imm_0, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, -1, OpTypes::type1, OpTypes::type1, | |
| OpTypes::type0, -1, OpTypes::type1, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type0, -1, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, | |
| -1, | |
| OpTypes::ptype0, -1, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type0, OpTypes::type1, OpTypes::type2, | |
| OpTypes::type0, OpTypes::type1, OpTypes::type2, | |
| OpTypes::type0, OpTypes::type1, OpTypes::type1, -1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type0, | |
| OpTypes::type0, OpTypes::type1, | |
| OpTypes::type0, -1, | |
| OpTypes::type0, -1, | |
| OpTypes::ptype0, OpTypes::type1, OpTypes::i32imm, | |
| OpTypes::type0, -1, | |
| -1, OpTypes::type0, | |
| OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, OpTypes::u6imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::u5imm, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::u5imm, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::u5imm, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::u5imm, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vssrc, OpTypes::dispRIX, OpTypes::ptr_rc_nor0, | |
| OpTypes::vsfrc, OpTypes::dispRIX, OpTypes::ptr_rc_nor0, | |
| OpTypes::vssrc, OpTypes::dispRIX, OpTypes::ptr_rc_nor0, | |
| OpTypes::vsfrc, OpTypes::dispRIX, OpTypes::ptr_rc_nor0, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, OpTypes::u6imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, OpTypes::u6imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, OpTypes::u6imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::vsfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u5imm, OpTypes::i32imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u5imm, OpTypes::i32imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u5imm, OpTypes::i32imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u5imm, OpTypes::i32imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u5imm, OpTypes::i32imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u5imm, OpTypes::i32imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, | |
| OpTypes::spilltovsrrc, OpTypes::dispRIX, OpTypes::ptr_rc_nor0, | |
| OpTypes::spilltovsrrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::spilltovsrrc, OpTypes::dispRIX, OpTypes::ptr_rc_nor0, | |
| OpTypes::spilltovsrrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, | |
| OpTypes::vsfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::s16imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::s16imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::s16imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::s16imm, | |
| OpTypes::g8rc, OpTypes::s16imm, | |
| OpTypes::vssrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vssrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::tlsreg32, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc_nox0, OpTypes::tlsreg, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::tlsreg, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc_nor0, OpTypes::s16imm, | |
| OpTypes::g8rc, OpTypes::g8rc_nox0, OpTypes::s16imm64, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::s16imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::s16imm64, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::s16imm, | |
| OpTypes::gprc, OpTypes::gprc_nor0, OpTypes::s17imm, | |
| OpTypes::g8rc, OpTypes::g8rc_nox0, OpTypes::s17imm64, | |
| OpTypes::g8rc, OpTypes::g8rc_nox0, OpTypes::s16imm64, | |
| OpTypes::gprc, OpTypes::gprc_nor0, OpTypes::s16imm, | |
| OpTypes::g8rc, OpTypes::g8rc_nox0, OpTypes::s16imm64, | |
| OpTypes::g8rc, OpTypes::g8rc_nox0, OpTypes::s16imm64, | |
| OpTypes::g8rc, OpTypes::g8rc_nox0, OpTypes::s16imm64, | |
| OpTypes::gprc, OpTypes::gprc_nor0, OpTypes::i32imm, | |
| OpTypes::g8rc, OpTypes::g8rc_nox0, OpTypes::i64imm, | |
| OpTypes::g8rc, OpTypes::g8rc_nox0, OpTypes::s16imm64, | |
| OpTypes::gprc, OpTypes::gprc_nor0, OpTypes::s16imm, | |
| OpTypes::g8rc, OpTypes::g8rc_nox0, OpTypes::s16imm64, | |
| OpTypes::gprc, OpTypes::gprc_nor0, OpTypes::s16imm, | |
| OpTypes::g8rc, OpTypes::g8rc_nox0, OpTypes::s16imm64, OpTypes::tlsgd, | |
| OpTypes::gprc, OpTypes::gprc_nor0, OpTypes::s16imm, OpTypes::tlsgd32, | |
| OpTypes::g8rc, OpTypes::g8rc_nox0, OpTypes::s16imm64, | |
| OpTypes::gprc, OpTypes::gprc_nor0, OpTypes::s16imm, | |
| OpTypes::g8rc, OpTypes::g8rc_nox0, OpTypes::s16imm64, OpTypes::tlsgd, | |
| OpTypes::gprc, OpTypes::gprc_nor0, OpTypes::s16imm, OpTypes::tlsgd32, | |
| OpTypes::g8rc, OpTypes::g8rc_nox0, OpTypes::i64imm, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::i32imm, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::u16imm, OpTypes::u16imm, | |
| OpTypes::u16imm, OpTypes::u16imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u16imm64, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u16imm64, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u16imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u16imm, | |
| OpTypes::crbitrc, OpTypes::gprc, | |
| OpTypes::crbitrc, OpTypes::g8rc, | |
| OpTypes::crbitrc, OpTypes::gprc, | |
| OpTypes::crbitrc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::gprc, | |
| /**/ | |
| OpTypes::directbrtarget, | |
| OpTypes::absdirectbrtarget, | |
| OpTypes::crbitrc, OpTypes::condbrtarget, | |
| OpTypes::i32imm, OpTypes::crrc, OpTypes::condbrtarget, | |
| OpTypes::i32imm, OpTypes::crrc, OpTypes::abscondbrtarget, | |
| OpTypes::i32imm, OpTypes::crrc, | |
| OpTypes::i32imm, OpTypes::crrc, | |
| OpTypes::i32imm, OpTypes::crrc, | |
| OpTypes::i32imm, OpTypes::crrc, | |
| OpTypes::i32imm, OpTypes::crrc, OpTypes::condbrtarget, | |
| OpTypes::i32imm, OpTypes::crrc, OpTypes::abscondbrtarget, | |
| OpTypes::i32imm, OpTypes::crrc, | |
| OpTypes::i32imm, OpTypes::crrc, | |
| OpTypes::crbitrc, | |
| OpTypes::crbitrc, | |
| OpTypes::crbitrc, | |
| OpTypes::crbitrc, | |
| OpTypes::crbitrc, | |
| OpTypes::crbitrc, | |
| OpTypes::crbitrc, | |
| OpTypes::crbitrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::u1imm, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::u1imm, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::u1imm, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::u1imm, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::u1imm, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::u1imm, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::u1imm, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::u1imm, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::crbitrc, OpTypes::condbrtarget, | |
| OpTypes::crbitrc, | |
| OpTypes::crbitrc, | |
| OpTypes::crbitrc, | |
| OpTypes::crbitrc, | |
| OpTypes::condbrtarget, | |
| OpTypes::crbitrc, OpTypes::condbrtarget, | |
| /**/ | |
| /**/ | |
| /**/ | |
| /**/ | |
| OpTypes::dispRIX, OpTypes::ptr_rc_nor0, | |
| OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::crbitrc, OpTypes::condbrtarget, | |
| OpTypes::condbrtarget, | |
| OpTypes::condbrtarget, | |
| OpTypes::abscondbrtarget, | |
| OpTypes::abscondbrtarget, | |
| OpTypes::abscondbrtarget, | |
| OpTypes::condbrtarget, | |
| OpTypes::abscondbrtarget, | |
| OpTypes::abscondbrtarget, | |
| OpTypes::abscondbrtarget, | |
| /**/ | |
| /**/ | |
| /**/ | |
| /**/ | |
| /**/ | |
| /**/ | |
| /**/ | |
| OpTypes::condbrtarget, | |
| OpTypes::condbrtarget, | |
| OpTypes::condbrtarget, | |
| OpTypes::condbrtarget, | |
| OpTypes::condbrtarget, | |
| OpTypes::condbrtarget, | |
| OpTypes::abscondbrtarget, | |
| OpTypes::abscondbrtarget, | |
| OpTypes::abscondbrtarget, | |
| OpTypes::condbrtarget, | |
| OpTypes::abscondbrtarget, | |
| OpTypes::abscondbrtarget, | |
| OpTypes::abscondbrtarget, | |
| /**/ | |
| /**/ | |
| /**/ | |
| /**/ | |
| /**/ | |
| /**/ | |
| /**/ | |
| OpTypes::condbrtarget, | |
| OpTypes::condbrtarget, | |
| OpTypes::condbrtarget, | |
| OpTypes::condbrtarget, | |
| OpTypes::calltarget, | |
| OpTypes::calltarget, | |
| OpTypes::calltarget, | |
| OpTypes::calltarget, OpTypes::tlsgd, | |
| OpTypes::calltarget, OpTypes::tlsgd, | |
| OpTypes::calltarget, OpTypes::tlsgd, | |
| OpTypes::abscalltarget, | |
| OpTypes::abscalltarget, | |
| OpTypes::abscalltarget, | |
| /**/ | |
| /**/ | |
| /**/ | |
| OpTypes::calltarget, | |
| OpTypes::calltarget, OpTypes::tlsgd32, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| /**/ | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::crrc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::crrc, OpTypes::g8rc, OpTypes::s16imm64, | |
| OpTypes::crbitrc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::crrc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::crrc, OpTypes::g8rc, OpTypes::u16imm64, | |
| OpTypes::crrc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::crrc, OpTypes::gprc, OpTypes::u16imm, | |
| OpTypes::crbitrc, OpTypes::u1imm, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::crbitrc, OpTypes::u1imm, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::crrc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::crrc, OpTypes::gprc, OpTypes::s16imm, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| /**/ | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u1imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u1imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u1imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u1imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u1imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u1imm, | |
| /**/ | |
| /**/ | |
| OpTypes::crbitrc, OpTypes::crbitrc, OpTypes::crbitrc, | |
| OpTypes::crbitrc, OpTypes::crbitrc, OpTypes::crbitrc, | |
| OpTypes::crbitrc, OpTypes::crbitrc, OpTypes::crbitrc, | |
| OpTypes::crbitrc, OpTypes::crbitrc, OpTypes::crbitrc, | |
| OpTypes::crbitrc, OpTypes::crbitrc, OpTypes::crbitrc, | |
| OpTypes::crbitrc, OpTypes::crbitrc, OpTypes::crbitrc, | |
| OpTypes::crbitrc, OpTypes::crbitrc, OpTypes::crbitrc, | |
| OpTypes::crbitrc, | |
| OpTypes::crbitrc, | |
| OpTypes::crbitrc, OpTypes::crbitrc, OpTypes::crbitrc, | |
| OpTypes::i32imm, OpTypes::crrc, OpTypes::condbrtarget, | |
| OpTypes::g8rc, OpTypes::i32imm, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::u5imm, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::u5imm, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::u5imm, | |
| OpTypes::u5imm, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, OpTypes::u5imm, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::u5imm, | |
| /**/ | |
| OpTypes::u5imm, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::u5imm, OpTypes::g8rc, OpTypes::gprc, | |
| OpTypes::u5imm, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::u5imm, OpTypes::g8rc, OpTypes::gprc, | |
| OpTypes::u5imm, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::u5imm, OpTypes::g8rc, OpTypes::gprc, | |
| OpTypes::u5imm, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::u5imm, OpTypes::g8rc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::i32imm, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::i64imm, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::spe4rc, | |
| OpTypes::sperc, OpTypes::spe4rc, | |
| OpTypes::sperc, OpTypes::gprc, | |
| OpTypes::sperc, OpTypes::gprc, | |
| OpTypes::sperc, OpTypes::spe4rc, | |
| OpTypes::sperc, OpTypes::gprc, | |
| OpTypes::sperc, OpTypes::gprc, | |
| OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::spe4rc, | |
| OpTypes::gprc, OpTypes::sperc, | |
| OpTypes::gprc, OpTypes::sperc, | |
| OpTypes::gprc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::spe4rc, | |
| OpTypes::gprc, OpTypes::sperc, | |
| OpTypes::gprc, OpTypes::sperc, | |
| OpTypes::gprc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::spe4rc, OpTypes::spe4rc, | |
| OpTypes::spe4rc, OpTypes::spe4rc, OpTypes::spe4rc, | |
| OpTypes::spe4rc, OpTypes::sperc, | |
| OpTypes::spe4rc, OpTypes::spe4rc, | |
| OpTypes::spe4rc, OpTypes::gprc, | |
| OpTypes::spe4rc, OpTypes::spe4rc, | |
| OpTypes::spe4rc, OpTypes::gprc, | |
| OpTypes::crrc, OpTypes::spe4rc, OpTypes::spe4rc, | |
| OpTypes::crrc, OpTypes::spe4rc, OpTypes::spe4rc, | |
| OpTypes::crrc, OpTypes::spe4rc, OpTypes::spe4rc, | |
| OpTypes::spe4rc, OpTypes::spe4rc, | |
| OpTypes::gprc, OpTypes::spe4rc, | |
| OpTypes::gprc, OpTypes::spe4rc, | |
| OpTypes::sperc, OpTypes::spe4rc, | |
| OpTypes::gprc, OpTypes::spe4rc, | |
| OpTypes::gprc, OpTypes::spe4rc, | |
| OpTypes::spe4rc, OpTypes::spe4rc, OpTypes::spe4rc, | |
| OpTypes::spe4rc, OpTypes::spe4rc, OpTypes::spe4rc, | |
| OpTypes::spe4rc, OpTypes::spe4rc, | |
| OpTypes::spe4rc, OpTypes::spe4rc, | |
| OpTypes::spe4rc, OpTypes::spe4rc, OpTypes::spe4rc, | |
| OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::ptr_rc_nor0, | |
| OpTypes::ptr_rc_nor0, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, | |
| OpTypes::directbrtarget, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::u5imm, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::dispSPE8, OpTypes::ptr_rc_nor0, | |
| OpTypes::sperc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::sperc, OpTypes::dispSPE8, OpTypes::ptr_rc_nor0, | |
| OpTypes::sperc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::sperc, OpTypes::dispSPE8, OpTypes::ptr_rc_nor0, | |
| OpTypes::sperc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::sperc, OpTypes::dispSPE2, OpTypes::ptr_rc_nor0, | |
| OpTypes::sperc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::sperc, OpTypes::dispSPE2, OpTypes::ptr_rc_nor0, | |
| OpTypes::sperc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::sperc, OpTypes::dispSPE2, OpTypes::ptr_rc_nor0, | |
| OpTypes::sperc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::sperc, OpTypes::dispSPE4, OpTypes::ptr_rc_nor0, | |
| OpTypes::sperc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::sperc, OpTypes::dispSPE4, OpTypes::ptr_rc_nor0, | |
| OpTypes::sperc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::sperc, OpTypes::dispSPE4, OpTypes::ptr_rc_nor0, | |
| OpTypes::sperc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::sperc, OpTypes::dispSPE4, OpTypes::ptr_rc_nor0, | |
| OpTypes::sperc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::sperc, OpTypes::dispSPE4, OpTypes::ptr_rc_nor0, | |
| OpTypes::sperc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::u5imm, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, OpTypes::crrc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::u5imm, | |
| OpTypes::sperc, OpTypes::s5imm, | |
| OpTypes::sperc, OpTypes::s5imm, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::u5imm, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::u5imm, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::dispSPE8, OpTypes::ptr_rc_nor0, | |
| OpTypes::sperc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::sperc, OpTypes::dispSPE8, OpTypes::ptr_rc_nor0, | |
| OpTypes::sperc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::sperc, OpTypes::dispSPE8, OpTypes::ptr_rc_nor0, | |
| OpTypes::sperc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::sperc, OpTypes::dispSPE4, OpTypes::ptr_rc_nor0, | |
| OpTypes::sperc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::sperc, OpTypes::dispSPE4, OpTypes::ptr_rc_nor0, | |
| OpTypes::sperc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::sperc, OpTypes::dispSPE4, OpTypes::ptr_rc_nor0, | |
| OpTypes::sperc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::sperc, OpTypes::dispSPE4, OpTypes::ptr_rc_nor0, | |
| OpTypes::sperc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::u5imm, OpTypes::sperc, | |
| OpTypes::sperc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::gprc, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::gprc, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| /**/ | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::crrc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::crrc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f8rc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f8rc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f4rc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::crrc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::crrc, OpTypes::f8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::tlsgd, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::tlsgd32, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::tlsgd, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::tlsgd32, | |
| /**/ | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::u4imm, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::u4imm, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::u4imm, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::u4imm, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc_nor0, OpTypes::gprc, OpTypes::crbitrc, | |
| OpTypes::g8rc, OpTypes::g8rc_nox0, OpTypes::g8rc, OpTypes::crbitrc, | |
| /**/ | |
| OpTypes::gprc, OpTypes::gprc_nor0, OpTypes::s16imm, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::g8rc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::g8rc, OpTypes::dispRIX, OpTypes::ptr_rc_nor0, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u5imm, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::dispRIX, OpTypes::ptr_rc_nor0, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::g8rc, OpTypes::s16imm64, OpTypes::g8rc_nox0, | |
| OpTypes::gprc, OpTypes::s16imm, OpTypes::gprc_nor0, | |
| OpTypes::g8rc, OpTypes::i64imm, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::i64imm, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::i64imm, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::i64imm, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::i64imm, OpTypes::g8rc_nox0, | |
| OpTypes::f8rc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::f8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::f8rc, OpTypes::ptr_rc_nor0, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::f8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::f8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::f8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::f8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::f4rc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::f4rc, OpTypes::ptr_rc_nor0, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::f4rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::f4rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::g8rc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::g8rc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::gprc, OpTypes::s16imm, | |
| OpTypes::g8rc, OpTypes::s16imm64, | |
| OpTypes::gprc, OpTypes::s17imm, | |
| OpTypes::g8rc, OpTypes::s17imm64, | |
| OpTypes::gprc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, | |
| OpTypes::vrrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vrrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vrrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vrrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vrrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vrrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vrrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::dispRIX, OpTypes::ptr_rc_nor0, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::dispRIX, OpTypes::ptr_rc_nor0, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::g8rc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::gprc, OpTypes::i32imm, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::i32imm, OpTypes::gprc_nor0, | |
| OpTypes::vfrc, OpTypes::dispRIX, OpTypes::ptr_rc_nor0, | |
| OpTypes::vsfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vfrc, OpTypes::dispRIX, OpTypes::ptr_rc_nor0, | |
| OpTypes::vssrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsrc, OpTypes::dispRIX16, OpTypes::ptr_rc_nor0, | |
| OpTypes::vsrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsrc, OpTypes::ptr_rc_nor0, OpTypes::g8rc, | |
| OpTypes::vsrc, OpTypes::ptr_rc_nor0, OpTypes::g8rc, | |
| OpTypes::vsrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::u5imm, | |
| OpTypes::crrc, OpTypes::crrc, | |
| OpTypes::crrc, OpTypes::crrc, | |
| OpTypes::crrc, | |
| OpTypes::gprc, OpTypes::u10imm, OpTypes::u10imm, | |
| OpTypes::gprc, | |
| OpTypes::g8rc, | |
| OpTypes::gprc, | |
| OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::i32imm, | |
| OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::u3imm, | |
| OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::f8rc, OpTypes::u2imm, | |
| OpTypes::f8rc, | |
| OpTypes::f8rc, | |
| OpTypes::gprc, | |
| OpTypes::g8rc, | |
| OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::crbitm, | |
| OpTypes::g8rc, OpTypes::crbitm, | |
| OpTypes::gprc, OpTypes::i32imm, | |
| OpTypes::gprc, OpTypes::i32imm, | |
| OpTypes::g8rc, OpTypes::i32imm, | |
| OpTypes::gprc, OpTypes::u4imm, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::i32imm, | |
| OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::vsrc, | |
| OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::VRSAVERC, | |
| OpTypes::gprc, OpTypes::vsrc, | |
| OpTypes::vrrc, | |
| OpTypes::g8rc, OpTypes::vsfrc, | |
| OpTypes::g8rc, OpTypes::vsrc, | |
| OpTypes::gprc, OpTypes::vsfrc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| /**/ | |
| /**/ | |
| OpTypes::i32imm, OpTypes::gprc, | |
| OpTypes::i32imm, OpTypes::g8rc, | |
| OpTypes::gprc, | |
| OpTypes::g8rc, | |
| OpTypes::g8rc, | |
| OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::i32imm, | |
| OpTypes::u5imm, | |
| OpTypes::u5imm, | |
| OpTypes::i32imm, OpTypes::f8rc, OpTypes::i32imm, OpTypes::i32imm, | |
| OpTypes::crrc, OpTypes::i32imm, OpTypes::i32imm, | |
| OpTypes::crrc, OpTypes::i32imm, OpTypes::i32imm, | |
| OpTypes::i32imm, OpTypes::f8rc, OpTypes::i32imm, OpTypes::i32imm, | |
| OpTypes::i32imm, OpTypes::f8rc, | |
| OpTypes::gprc, | |
| OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::i32imm, | |
| OpTypes::gprc, OpTypes::i32imm, | |
| OpTypes::crbitm, OpTypes::gprc, | |
| OpTypes::crbitm, OpTypes::g8rc, | |
| OpTypes::i32imm, OpTypes::gprc, | |
| OpTypes::i32imm, OpTypes::gprc, | |
| OpTypes::i32imm, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::u4imm, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::vsrc, OpTypes::g8rc, | |
| OpTypes::gprc, | |
| OpTypes::VRSAVERC, OpTypes::gprc, | |
| OpTypes::vsrc, OpTypes::gprc, | |
| OpTypes::vsrc, OpTypes::gprc, | |
| OpTypes::vrrc, | |
| OpTypes::vsfrc, OpTypes::g8rc, | |
| OpTypes::vsrc, OpTypes::g8rc_nox0, OpTypes::g8rc, | |
| OpTypes::vsfrc, OpTypes::gprc, | |
| OpTypes::vsrc, OpTypes::gprc, | |
| OpTypes::vsfrc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::s16imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::s16imm64, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| /**/ | |
| /**/ | |
| /**/ | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| /**/ | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| /**/ | |
| /**/ | |
| /**/ | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u16imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u16imm64, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u16imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u16imm64, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::u2imm, | |
| OpTypes::qbrc, OpTypes::qbrc, OpTypes::qbrc, OpTypes::u2imm, | |
| OpTypes::qsrc, OpTypes::qsrc, OpTypes::qsrc, OpTypes::u2imm, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::u2imm, | |
| OpTypes::qbrc, OpTypes::qbrc, OpTypes::u2imm, | |
| OpTypes::qsrc, OpTypes::qsrc, OpTypes::u2imm, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qsrc, OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qbrc, OpTypes::qbrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qbrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qbrc, OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qbrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qbrc, OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qbrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qbrc, OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qsrc, OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qbrc, OpTypes::qbrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::u12imm, | |
| OpTypes::qbrc, OpTypes::qbrc, OpTypes::qbrc, OpTypes::u12imm, | |
| OpTypes::qbrc, OpTypes::qbrc, OpTypes::qbrc, OpTypes::u12imm, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qsrc, OpTypes::qsrc, OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qbrc, OpTypes::qbrc, | |
| OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qsrc, OpTypes::qsrc, OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qsrc, OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qsrc, OpTypes::qsrc, OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qsrc, OpTypes::qsrc, OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qsrc, OpTypes::qsrc, OpTypes::qsrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qsrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qbrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qbrc, OpTypes::qbrc, OpTypes::qbrc, OpTypes::qbrc, | |
| OpTypes::qsrc, OpTypes::qbrc, OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qsrc, OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qbrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qbrc, OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qfrc, OpTypes::u12imm, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qsrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qbrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qsrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qbrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qsrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::G8RC, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qsrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qbrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::qsrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::qsrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::crrc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::crbitrc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::VRSAVERC, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| /**/ | |
| /**/ | |
| OpTypes::u1imm, | |
| /**/ | |
| /**/ | |
| /**/ | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::gprc, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::gprc, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::gprc, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::gprc, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, OpTypes::u6imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u6imm, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::gprc, OpTypes::u6imm, OpTypes::u6imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u6imm, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, OpTypes::u6imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u6imm, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, OpTypes::u6imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, OpTypes::u5imm, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, OpTypes::u5imm, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u5imm, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u5imm, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::i32imm, | |
| OpTypes::vrrc, OpTypes::crrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::i32imm, | |
| OpTypes::f4rc, OpTypes::crrc, OpTypes::f4rc, OpTypes::f4rc, OpTypes::i32imm, | |
| OpTypes::f8rc, OpTypes::crrc, OpTypes::f8rc, OpTypes::f8rc, OpTypes::i32imm, | |
| OpTypes::gprc, OpTypes::crrc, OpTypes::gprc_nor0, OpTypes::gprc_nor0, OpTypes::i32imm, | |
| OpTypes::g8rc, OpTypes::crrc, OpTypes::g8rc_nox0, OpTypes::g8rc_nox0, OpTypes::i32imm, | |
| OpTypes::qbrc, OpTypes::crrc, OpTypes::qbrc, OpTypes::qbrc, OpTypes::i32imm, | |
| OpTypes::qfrc, OpTypes::crrc, OpTypes::qfrc, OpTypes::qfrc, OpTypes::i32imm, | |
| OpTypes::qsrc, OpTypes::crrc, OpTypes::qsrc, OpTypes::qsrc, OpTypes::i32imm, | |
| OpTypes::sperc, OpTypes::crrc, OpTypes::sperc, OpTypes::sperc, OpTypes::i32imm, | |
| OpTypes::spe4rc, OpTypes::crrc, OpTypes::spe4rc, OpTypes::spe4rc, OpTypes::i32imm, | |
| OpTypes::vrrc, OpTypes::crrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::i32imm, | |
| OpTypes::f8rc, OpTypes::crrc, OpTypes::f8rc, OpTypes::f8rc, OpTypes::i32imm, | |
| OpTypes::vsrc, OpTypes::crrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::i32imm, | |
| OpTypes::f4rc, OpTypes::crrc, OpTypes::f4rc, OpTypes::f4rc, OpTypes::i32imm, | |
| OpTypes::vrrc, OpTypes::crbitrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::f4rc, OpTypes::crbitrc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::f8rc, OpTypes::crbitrc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::gprc, OpTypes::crbitrc, OpTypes::gprc_nor0, OpTypes::gprc_nor0, | |
| OpTypes::g8rc, OpTypes::crbitrc, OpTypes::g8rc_nox0, OpTypes::g8rc_nox0, | |
| OpTypes::qbrc, OpTypes::crbitrc, OpTypes::qbrc, OpTypes::qbrc, | |
| OpTypes::qfrc, OpTypes::crbitrc, OpTypes::qfrc, OpTypes::qfrc, | |
| OpTypes::qsrc, OpTypes::crbitrc, OpTypes::qsrc, OpTypes::qsrc, | |
| OpTypes::sperc, OpTypes::crbitrc, OpTypes::sperc, OpTypes::sperc, | |
| OpTypes::spe4rc, OpTypes::crbitrc, OpTypes::spe4rc, OpTypes::spe4rc, | |
| OpTypes::vrrc, OpTypes::crbitrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::f8rc, OpTypes::crbitrc, OpTypes::f8rc, OpTypes::f8rc, | |
| OpTypes::vsrc, OpTypes::crbitrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::f4rc, OpTypes::crbitrc, OpTypes::f4rc, OpTypes::f4rc, | |
| OpTypes::gprc, OpTypes::crrc, | |
| OpTypes::g8rc, OpTypes::crrc, | |
| OpTypes::f8rc, OpTypes::gprc, | |
| OpTypes::f8rc, OpTypes::u2imm, | |
| OpTypes::gprc, OpTypes::gprc, | |
| /**/ | |
| OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| /**/ | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::spe4rc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::spe4rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::spe4rc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::spe4rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::crrc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::crbitrc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::VRSAVERC, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u6imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::g8rc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::gprc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::ptr_rc_nor0, OpTypes::g8rc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::ptr_rc_nor0, OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::g8rc, OpTypes::dispRIX, OpTypes::ptr_rc_nor0, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u5imm, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::g8rc, OpTypes::dispRIX, OpTypes::ptr_rc_nor0, | |
| OpTypes::ptr_rc_nor0, OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::f8rc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::f8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::f8rc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::ptr_rc_nor0, OpTypes::f8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::f8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::f8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::f4rc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::ptr_rc_nor0, OpTypes::f4rc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::ptr_rc_nor0, OpTypes::f4rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::f4rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::g8rc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::gprc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::ptr_rc_nor0, OpTypes::g8rc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::ptr_rc_nor0, OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::gprc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| /**/ | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, | |
| OpTypes::vrrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vrrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vrrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vrrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vrrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::g8rc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u5imm, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::gprc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::ptr_rc_nor0, OpTypes::g8rc, OpTypes::dispRI, OpTypes::ptr_rc_nor0, | |
| OpTypes::ptr_rc_nor0, OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::ptr_rc_nor0, OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::g8rc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::gprc, OpTypes::ptr_rc_nor0, OpTypes::tlsreg, | |
| OpTypes::vfrc, OpTypes::dispRIX, OpTypes::ptr_rc_nor0, | |
| OpTypes::vsfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsfrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vfrc, OpTypes::dispRIX, OpTypes::ptr_rc_nor0, | |
| OpTypes::vssrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsrc, OpTypes::dispRIX16, OpTypes::ptr_rc_nor0, | |
| OpTypes::vsrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsrc, OpTypes::ptr_rc_nor0, OpTypes::g8rc, | |
| OpTypes::vsrc, OpTypes::ptr_rc_nor0, OpTypes::g8rc, | |
| OpTypes::vsrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::vsrc, OpTypes::ptr_rc_nor0, OpTypes::ptr_rc_idx, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::s16imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::s16imm64, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::i32imm, | |
| OpTypes::gprc, | |
| OpTypes::u5imm, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::u5imm, OpTypes::gprc, OpTypes::u5imm, | |
| OpTypes::u5imm, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::u5imm, OpTypes::gprc, OpTypes::u5imm, | |
| OpTypes::calltarget, | |
| OpTypes::calltarget, | |
| OpTypes::abscalltarget, | |
| OpTypes::abscalltarget, | |
| /**/ | |
| /**/ | |
| OpTypes::u1imm, | |
| OpTypes::gprc, OpTypes::u1imm, | |
| OpTypes::crrc, | |
| OpTypes::gprc, | |
| OpTypes::abscalltarget, OpTypes::i32imm, | |
| OpTypes::abscalltarget, OpTypes::i32imm, | |
| OpTypes::calltarget, OpTypes::i32imm, | |
| OpTypes::calltarget, OpTypes::i32imm, | |
| OpTypes::CTRRC, OpTypes::i32imm, | |
| OpTypes::CTRRC8, OpTypes::i32imm, | |
| OpTypes::u5imm, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::u5imm, OpTypes::g8rc, OpTypes::s16imm, | |
| OpTypes::u1imm, | |
| /**/ | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, | |
| OpTypes::gprc, | |
| /**/ | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::i1imm, | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| /**/ | |
| /**/ | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::i1imm, | |
| /**/ | |
| /**/ | |
| OpTypes::gprc, | |
| OpTypes::u1imm, | |
| OpTypes::u5imm, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::u5imm, OpTypes::gprc, OpTypes::s16imm, | |
| /**/ | |
| OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::u5imm, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::u5imm, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::gprc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::u5imm, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::u5imm, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::gprc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::u4imm, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::u4imm, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::u4imm, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::u4imm, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vfrc, OpTypes::vfrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vfrc, OpTypes::vfrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vfrc, OpTypes::vfrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vfrc, OpTypes::vfrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vfrc, OpTypes::vfrc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::vrrc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::vrrc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::vrrc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::vrrc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::vrrc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::u4imm, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::u4imm, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::u4imm, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::u4imm, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::u1imm, OpTypes::u4imm, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::u1imm, OpTypes::u4imm, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::u4imm, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::u5imm, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::u5imm, OpTypes::vfrc, | |
| OpTypes::vrrc, OpTypes::u5imm, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::u5imm, OpTypes::vfrc, | |
| OpTypes::vrrc, OpTypes::s5imm, | |
| OpTypes::vrrc, OpTypes::s5imm, | |
| OpTypes::vrrc, OpTypes::s5imm, | |
| OpTypes::vrrc, OpTypes::u5imm, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, | |
| OpTypes::vrrc, | |
| OpTypes::vrrc, | |
| OpTypes::vrrc, | |
| OpTypes::vrrc, | |
| OpTypes::vrrc, | |
| OpTypes::i32imm, | |
| OpTypes::gprc, | |
| OpTypes::i1imm, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u16imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u16imm64, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::u16imm, | |
| OpTypes::g8rc, OpTypes::g8rc, OpTypes::u16imm64, | |
| OpTypes::gprc, OpTypes::gprc, OpTypes::gprc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vssrc, OpTypes::vssrc, OpTypes::vssrc, | |
| OpTypes::vsrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::crrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::crrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vsrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vsrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::crrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::crrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::crrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::crrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vrrc, OpTypes::vfrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vsrc, OpTypes::vssrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vssrc, OpTypes::vssrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vssrc, OpTypes::vssrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vssrc, OpTypes::vssrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vssrc, OpTypes::vssrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vfrc, OpTypes::vrrc, | |
| OpTypes::vfrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vfrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vssrc, OpTypes::vsrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vssrc, OpTypes::vsfrc, | |
| OpTypes::vrrc, OpTypes::vfrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vssrc, OpTypes::vsfrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vssrc, OpTypes::vssrc, OpTypes::vssrc, | |
| OpTypes::vsrc, OpTypes::g8rc, OpTypes::g8rc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vsfrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vssrc, OpTypes::vssrc, OpTypes::vssrc, OpTypes::vssrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vssrc, OpTypes::vssrc, OpTypes::vssrc, OpTypes::vssrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vsrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vsrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vssrc, OpTypes::vssrc, OpTypes::vssrc, OpTypes::vssrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vssrc, OpTypes::vssrc, OpTypes::vssrc, OpTypes::vssrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vssrc, OpTypes::vssrc, OpTypes::vssrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vssrc, OpTypes::vssrc, OpTypes::vssrc, OpTypes::vssrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vssrc, OpTypes::vssrc, OpTypes::vssrc, OpTypes::vssrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vssrc, OpTypes::vssrc, OpTypes::vssrc, OpTypes::vssrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vssrc, OpTypes::vssrc, OpTypes::vssrc, OpTypes::vssrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vssrc, OpTypes::vssrc, | |
| OpTypes::vrrc, OpTypes::u1imm, OpTypes::vrrc, OpTypes::u2imm, | |
| OpTypes::vrrc, OpTypes::u1imm, OpTypes::vrrc, OpTypes::u2imm, | |
| OpTypes::vrrc, OpTypes::u1imm, OpTypes::vrrc, OpTypes::u2imm, | |
| OpTypes::vssrc, OpTypes::vsfrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vssrc, OpTypes::vssrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vssrc, OpTypes::vssrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vrrc, OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vssrc, OpTypes::vssrc, OpTypes::vssrc, | |
| OpTypes::crrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::crrc, OpTypes::vsfrc, | |
| OpTypes::crrc, OpTypes::u7imm, OpTypes::vsfrc, | |
| OpTypes::crrc, OpTypes::u7imm, OpTypes::vrrc, | |
| OpTypes::crrc, OpTypes::u7imm, OpTypes::vsfrc, | |
| OpTypes::g8rc, OpTypes::vsfrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::g8rc, OpTypes::vsfrc, | |
| OpTypes::vrrc, OpTypes::vrrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::crrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::crrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::crrc, OpTypes::vsrc, | |
| OpTypes::crrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::u7imm, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::u7imm, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsfrc, OpTypes::vsrc, OpTypes::u4imm, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::u4imm, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsfrc, OpTypes::vsfrc, OpTypes::vsfrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsfrc, | |
| OpTypes::vssrc, | |
| OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::u2imm, | |
| OpTypes::vsrc, OpTypes::vsfrc, OpTypes::u2imm, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::vsrc, OpTypes::u2imm, | |
| OpTypes::vsrc, OpTypes::vsfrc, OpTypes::u2imm, | |
| OpTypes::vsrc, OpTypes::u8imm, | |
| OpTypes::vsrc, OpTypes::vsrc, OpTypes::u2imm, | |
| OpTypes::vsrc, OpTypes::vsfrc, OpTypes::u2imm, | |
| OpTypes::u5imm, OpTypes::crbitrc, OpTypes::condbrtarget, | |
| OpTypes::u5imm, OpTypes::crbitrc, OpTypes::abscondbrtarget, | |
| OpTypes::u5imm, OpTypes::atimm, OpTypes::crbitrc, OpTypes::abscondbrtarget, | |
| OpTypes::u5imm, OpTypes::crbitrc, OpTypes::i32imm, | |
| OpTypes::u5imm, OpTypes::crbitrc, OpTypes::i32imm, | |
| OpTypes::u5imm, OpTypes::crbitrc, OpTypes::condbrtarget, | |
| OpTypes::u5imm, OpTypes::crbitrc, OpTypes::abscondbrtarget, | |
| OpTypes::u5imm, OpTypes::atimm, OpTypes::crbitrc, OpTypes::abscondbrtarget, | |
| OpTypes::u5imm, OpTypes::crbitrc, OpTypes::i32imm, | |
| OpTypes::u5imm, OpTypes::crbitrc, OpTypes::i32imm, | |
| OpTypes::u5imm, OpTypes::atimm, OpTypes::crbitrc, OpTypes::condbrtarget, | |
| OpTypes::u5imm, OpTypes::atimm, OpTypes::crbitrc, OpTypes::condbrtarget, | |
| }; | |
| return OpcodeOperandTypes[Offsets[Opcode] + OpIdx]; | |
| } | |
| } // end namespace PPC | |
| } // end namespace llvm | |
| #endif // GET_INSTRINFO_OPERAND_TYPE | |
| #ifdef GET_INSTRMAP_INFO | |
| #undef GET_INSTRMAP_INFO | |
| namespace llvm { | |
| namespace PPC { | |
| enum IsVSXFMAAlt { | |
| IsVSXFMAAlt_1 | |
| }; | |
| enum RC { | |
| RC_0, | |
| RC_1 | |
| }; | |
| // getAltVSXFMAOpcode | |
| LLVM_READONLY | |
| int getAltVSXFMAOpcode(uint16_t Opcode) { | |
| static const uint16_t getAltVSXFMAOpcodeTable[][2] = { | |
| { PPC::XSMADDADP, PPC::XSMADDMDP }, | |
| { PPC::XSMADDASP, PPC::XSMADDMSP }, | |
| { PPC::XSMSUBADP, PPC::XSMSUBMDP }, | |
| { PPC::XSMSUBASP, PPC::XSMSUBMSP }, | |
| { PPC::XSNMADDADP, PPC::XSNMADDMDP }, | |
| { PPC::XSNMADDASP, PPC::XSNMADDMSP }, | |
| { PPC::XSNMSUBADP, PPC::XSNMSUBMDP }, | |
| { PPC::XSNMSUBASP, PPC::XSNMSUBMSP }, | |
| { PPC::XVMADDADP, PPC::XVMADDMDP }, | |
| { PPC::XVMADDASP, PPC::XVMADDMSP }, | |
| { PPC::XVMSUBADP, PPC::XVMSUBMDP }, | |
| { PPC::XVMSUBASP, PPC::XVMSUBMSP }, | |
| { PPC::XVNMADDADP, PPC::XVNMADDMDP }, | |
| { PPC::XVNMADDASP, PPC::XVNMADDMSP }, | |
| { PPC::XVNMSUBADP, PPC::XVNMSUBMDP }, | |
| { PPC::XVNMSUBASP, PPC::XVNMSUBMSP }, | |
| }; // End of getAltVSXFMAOpcodeTable | |
| unsigned mid; | |
| unsigned start = 0; | |
| unsigned end = 16; | |
| while (start < end) { | |
| mid = start + (end - start)/2; | |
| if (Opcode == getAltVSXFMAOpcodeTable[mid][0]) { | |
| break; | |
| } | |
| if (Opcode < getAltVSXFMAOpcodeTable[mid][0]) | |
| end = mid; | |
| else | |
| start = mid + 1; | |
| } | |
| if (start == end) | |
| return -1; // Instruction doesn't exist in this table. | |
| return getAltVSXFMAOpcodeTable[mid][1]; | |
| } | |
| // getNonRecordFormOpcode | |
| LLVM_READONLY | |
| int getNonRecordFormOpcode(uint16_t Opcode) { | |
| static const uint16_t getNonRecordFormOpcodeTable[][2] = { | |
| { PPC::ADD4O_rec, PPC::ADD4O }, | |
| { PPC::ADD4_rec, PPC::ADD4 }, | |
| { PPC::ADD8O_rec, PPC::ADD8O }, | |
| { PPC::ADD8_rec, PPC::ADD8 }, | |
| { PPC::ADDC8O_rec, PPC::ADDC8O }, | |
| { PPC::ADDC8_rec, PPC::ADDC8 }, | |
| { PPC::ADDCO_rec, PPC::ADDCO }, | |
| { PPC::ADDC_rec, PPC::ADDC }, | |
| { PPC::ADDE8O_rec, PPC::ADDE8O }, | |
| { PPC::ADDE8_rec, PPC::ADDE8 }, | |
| { PPC::ADDEO_rec, PPC::ADDEO }, | |
| { PPC::ADDE_rec, PPC::ADDE }, | |
| { PPC::ADDIC_rec, PPC::ADDIC }, | |
| { PPC::ADDME8O_rec, PPC::ADDME8O }, | |
| { PPC::ADDME8_rec, PPC::ADDME8 }, | |
| { PPC::ADDMEO_rec, PPC::ADDMEO }, | |
| { PPC::ADDME_rec, PPC::ADDME }, | |
| { PPC::ADDZE8O_rec, PPC::ADDZE8O }, | |
| { PPC::ADDZE8_rec, PPC::ADDZE8 }, | |
| { PPC::ADDZEO_rec, PPC::ADDZEO }, | |
| { PPC::ADDZE_rec, PPC::ADDZE }, | |
| { PPC::AND8_rec, PPC::AND8 }, | |
| { PPC::ANDC8_rec, PPC::ANDC8 }, | |
| { PPC::ANDC_rec, PPC::ANDC }, | |
| { PPC::AND_rec, PPC::AND }, | |
| { PPC::CNTLZD_rec, PPC::CNTLZD }, | |
| { PPC::CNTLZW8_rec, PPC::CNTLZW8 }, | |
| { PPC::CNTLZW_rec, PPC::CNTLZW }, | |
| { PPC::CNTTZD_rec, PPC::CNTTZD }, | |
| { PPC::CNTTZW8_rec, PPC::CNTTZW8 }, | |
| { PPC::CNTTZW_rec, PPC::CNTTZW }, | |
| { PPC::DIVDEO_rec, PPC::DIVDEO }, | |
| { PPC::DIVDEUO_rec, PPC::DIVDEUO }, | |
| { PPC::DIVDEU_rec, PPC::DIVDEU }, | |
| { PPC::DIVDE_rec, PPC::DIVDE }, | |
| { PPC::DIVDO_rec, PPC::DIVDO }, | |
| { PPC::DIVDUO_rec, PPC::DIVDUO }, | |
| { PPC::DIVDU_rec, PPC::DIVDU }, | |
| { PPC::DIVD_rec, PPC::DIVD }, | |
| { PPC::DIVWEO_rec, PPC::DIVWEO }, | |
| { PPC::DIVWEUO_rec, PPC::DIVWEUO }, | |
| { PPC::DIVWEU_rec, PPC::DIVWEU }, | |
| { PPC::DIVWE_rec, PPC::DIVWE }, | |
| { PPC::DIVWO_rec, PPC::DIVWO }, | |
| { PPC::DIVWUO_rec, PPC::DIVWUO }, | |
| { PPC::DIVWU_rec, PPC::DIVWU }, | |
| { PPC::DIVW_rec, PPC::DIVW }, | |
| { PPC::EQV8_rec, PPC::EQV8 }, | |
| { PPC::EQV_rec, PPC::EQV }, | |
| { PPC::EXTSB8_rec, PPC::EXTSB8 }, | |
| { PPC::EXTSB_rec, PPC::EXTSB }, | |
| { PPC::EXTSH8_rec, PPC::EXTSH8 }, | |
| { PPC::EXTSH_rec, PPC::EXTSH }, | |
| { PPC::EXTSWSLI_32_64_rec, PPC::EXTSWSLI_32_64 }, | |
| { PPC::EXTSWSLI_rec, PPC::EXTSWSLI }, | |
| { PPC::EXTSW_32_64_rec, PPC::EXTSW_32_64 }, | |
| { PPC::EXTSW_rec, PPC::EXTSW }, | |
| { PPC::FABSD_rec, PPC::FABSD }, | |
| { PPC::FABSS_rec, PPC::FABSS }, | |
| { PPC::FADDS_rec, PPC::FADDS }, | |
| { PPC::FADD_rec, PPC::FADD }, | |
| { PPC::FCFIDS_rec, PPC::FCFIDS }, | |
| { PPC::FCFIDUS_rec, PPC::FCFIDUS }, | |
| { PPC::FCFIDU_rec, PPC::FCFIDU }, | |
| { PPC::FCFID_rec, PPC::FCFID }, | |
| { PPC::FCPSGND_rec, PPC::FCPSGND }, | |
| { PPC::FCPSGNS_rec, PPC::FCPSGNS }, | |
| { PPC::FCTIDUZ_rec, PPC::FCTIDUZ }, | |
| { PPC::FCTIDU_rec, PPC::FCTIDU }, | |
| { PPC::FCTIDZ_rec, PPC::FCTIDZ }, | |
| { PPC::FCTID_rec, PPC::FCTID }, | |
| { PPC::FCTIWUZ_rec, PPC::FCTIWUZ }, | |
| { PPC::FCTIWU_rec, PPC::FCTIWU }, | |
| { PPC::FCTIWZ_rec, PPC::FCTIWZ }, | |
| { PPC::FCTIW_rec, PPC::FCTIW }, | |
| { PPC::FDIVS_rec, PPC::FDIVS }, | |
| { PPC::FDIV_rec, PPC::FDIV }, | |
| { PPC::FMADDS_rec, PPC::FMADDS }, | |
| { PPC::FMADD_rec, PPC::FMADD }, | |
| { PPC::FMR_rec, PPC::FMR }, | |
| { PPC::FMSUBS_rec, PPC::FMSUBS }, | |
| { PPC::FMSUB_rec, PPC::FMSUB }, | |
| { PPC::FMULS_rec, PPC::FMULS }, | |
| { PPC::FMUL_rec, PPC::FMUL }, | |
| { PPC::FNABSD_rec, PPC::FNABSD }, | |
| { PPC::FNABSS_rec, PPC::FNABSS }, | |
| { PPC::FNEGD_rec, PPC::FNEGD }, | |
| { PPC::FNEGS_rec, PPC::FNEGS }, | |
| { PPC::FNMADDS_rec, PPC::FNMADDS }, | |
| { PPC::FNMADD_rec, PPC::FNMADD }, | |
| { PPC::FNMSUBS_rec, PPC::FNMSUBS }, | |
| { PPC::FNMSUB_rec, PPC::FNMSUB }, | |
| { PPC::FRES_rec, PPC::FRES }, | |
| { PPC::FRE_rec, PPC::FRE }, | |
| { PPC::FRIMD_rec, PPC::FRIMD }, | |
| { PPC::FRIMS_rec, PPC::FRIMS }, | |
| { PPC::FRIND_rec, PPC::FRIND }, | |
| { PPC::FRINS_rec, PPC::FRINS }, | |
| { PPC::FRIPD_rec, PPC::FRIPD }, | |
| { PPC::FRIPS_rec, PPC::FRIPS }, | |
| { PPC::FRIZD_rec, PPC::FRIZD }, | |
| { PPC::FRIZS_rec, PPC::FRIZS }, | |
| { PPC::FRSP_rec, PPC::FRSP }, | |
| { PPC::FRSQRTES_rec, PPC::FRSQRTES }, | |
| { PPC::FRSQRTE_rec, PPC::FRSQRTE }, | |
| { PPC::FSELD_rec, PPC::FSELD }, | |
| { PPC::FSELS_rec, PPC::FSELS }, | |
| { PPC::FSQRTS_rec, PPC::FSQRTS }, | |
| { PPC::FSQRT_rec, PPC::FSQRT }, | |
| { PPC::FSUBS_rec, PPC::FSUBS }, | |
| { PPC::FSUB_rec, PPC::FSUB }, | |
| { PPC::MULHDU_rec, PPC::MULHDU }, | |
| { PPC::MULHD_rec, PPC::MULHD }, | |
| { PPC::MULHWU_rec, PPC::MULHWU }, | |
| { PPC::MULHW_rec, PPC::MULHW }, | |
| { PPC::MULLDO_rec, PPC::MULLDO }, | |
| { PPC::MULLD_rec, PPC::MULLD }, | |
| { PPC::MULLWO_rec, PPC::MULLWO }, | |
| { PPC::MULLW_rec, PPC::MULLW }, | |
| { PPC::NAND8_rec, PPC::NAND8 }, | |
| { PPC::NAND_rec, PPC::NAND }, | |
| { PPC::NEG8O_rec, PPC::NEG8O }, | |
| { PPC::NEG8_rec, PPC::NEG8 }, | |
| { PPC::NEGO_rec, PPC::NEGO }, | |
| { PPC::NEG_rec, PPC::NEG }, | |
| { PPC::NOR8_rec, PPC::NOR8 }, | |
| { PPC::NOR_rec, PPC::NOR }, | |
| { PPC::OR8_rec, PPC::OR8 }, | |
| { PPC::ORC8_rec, PPC::ORC8 }, | |
| { PPC::ORC_rec, PPC::ORC }, | |
| { PPC::OR_rec, PPC::OR }, | |
| { PPC::RLDCL_rec, PPC::RLDCL }, | |
| { PPC::RLDCR_rec, PPC::RLDCR }, | |
| { PPC::RLDICL_32_rec, PPC::RLDICL_32 }, | |
| { PPC::RLDICL_rec, PPC::RLDICL }, | |
| { PPC::RLDICR_rec, PPC::RLDICR }, | |
| { PPC::RLDIC_rec, PPC::RLDIC }, | |
| { PPC::RLDIMI_rec, PPC::RLDIMI }, | |
| { PPC::RLWIMI8_rec, PPC::RLWIMI8 }, | |
| { PPC::RLWIMI_rec, PPC::RLWIMI }, | |
| { PPC::RLWINM8_rec, PPC::RLWINM8 }, | |
| { PPC::RLWINM_rec, PPC::RLWINM }, | |
| { PPC::RLWNM8_rec, PPC::RLWNM8 }, | |
| { PPC::RLWNM_rec, PPC::RLWNM }, | |
| { PPC::SLD_rec, PPC::SLD }, | |
| { PPC::SLW8_rec, PPC::SLW8 }, | |
| { PPC::SLW_rec, PPC::SLW }, | |
| { PPC::SRADI_rec, PPC::SRADI }, | |
| { PPC::SRAD_rec, PPC::SRAD }, | |
| { PPC::SRAWI_rec, PPC::SRAWI }, | |
| { PPC::SRAW_rec, PPC::SRAW }, | |
| { PPC::SRD_rec, PPC::SRD }, | |
| { PPC::SRW8_rec, PPC::SRW8 }, | |
| { PPC::SRW_rec, PPC::SRW }, | |
| { PPC::SUBF8O_rec, PPC::SUBF8O }, | |
| { PPC::SUBF8_rec, PPC::SUBF8 }, | |
| { PPC::SUBFC8O_rec, PPC::SUBFC8O }, | |
| { PPC::SUBFC8_rec, PPC::SUBFC8 }, | |
| { PPC::SUBFCO_rec, PPC::SUBFCO }, | |
| { PPC::SUBFC_rec, PPC::SUBFC }, | |
| { PPC::SUBFE8O_rec, PPC::SUBFE8O }, | |
| { PPC::SUBFE8_rec, PPC::SUBFE8 }, | |
| { PPC::SUBFEO_rec, PPC::SUBFEO }, | |
| { PPC::SUBFE_rec, PPC::SUBFE }, | |
| { PPC::SUBFME8O_rec, PPC::SUBFME8O }, | |
| { PPC::SUBFME8_rec, PPC::SUBFME8 }, | |
| { PPC::SUBFMEO_rec, PPC::SUBFMEO }, | |
| { PPC::SUBFME_rec, PPC::SUBFME }, | |
| { PPC::SUBFO_rec, PPC::SUBFO }, | |
| { PPC::SUBFZE8O_rec, PPC::SUBFZE8O }, | |
| { PPC::SUBFZE8_rec, PPC::SUBFZE8 }, | |
| { PPC::SUBFZEO_rec, PPC::SUBFZEO }, | |
| { PPC::SUBFZE_rec, PPC::SUBFZE }, | |
| { PPC::SUBF_rec, PPC::SUBF }, | |
| { PPC::XOR8_rec, PPC::XOR8 }, | |
| { PPC::XOR_rec, PPC::XOR }, | |
| }; // End of getNonRecordFormOpcodeTable | |
| unsigned mid; | |
| unsigned start = 0; | |
| unsigned end = 176; | |
| while (start < end) { | |
| mid = start + (end - start)/2; | |
| if (Opcode == getNonRecordFormOpcodeTable[mid][0]) { | |
| break; | |
| } | |
| if (Opcode < getNonRecordFormOpcodeTable[mid][0]) | |
| end = mid; | |
| else | |
| start = mid + 1; | |
| } | |
| if (start == end) | |
| return -1; // Instruction doesn't exist in this table. | |
| return getNonRecordFormOpcodeTable[mid][1]; | |
| } | |
| // getRecordFormOpcode | |
| LLVM_READONLY | |
| int getRecordFormOpcode(uint16_t Opcode) { | |
| static const uint16_t getRecordFormOpcodeTable[][2] = { | |
| { PPC::ADD4, PPC::ADD4_rec }, | |
| { PPC::ADD4O, PPC::ADD4O_rec }, | |
| { PPC::ADD8, PPC::ADD8_rec }, | |
| { PPC::ADD8O, PPC::ADD8O_rec }, | |
| { PPC::ADDC, PPC::ADDC_rec }, | |
| { PPC::ADDC8, PPC::ADDC8_rec }, | |
| { PPC::ADDC8O, PPC::ADDC8O_rec }, | |
| { PPC::ADDCO, PPC::ADDCO_rec }, | |
| { PPC::ADDE, PPC::ADDE_rec }, | |
| { PPC::ADDE8, PPC::ADDE8_rec }, | |
| { PPC::ADDE8O, PPC::ADDE8O_rec }, | |
| { PPC::ADDEO, PPC::ADDEO_rec }, | |
| { PPC::ADDIC, PPC::ADDIC_rec }, | |
| { PPC::ADDME, PPC::ADDME_rec }, | |
| { PPC::ADDME8, PPC::ADDME8_rec }, | |
| { PPC::ADDME8O, PPC::ADDME8O_rec }, | |
| { PPC::ADDMEO, PPC::ADDMEO_rec }, | |
| { PPC::ADDZE, PPC::ADDZE_rec }, | |
| { PPC::ADDZE8, PPC::ADDZE8_rec }, | |
| { PPC::ADDZE8O, PPC::ADDZE8O_rec }, | |
| { PPC::ADDZEO, PPC::ADDZEO_rec }, | |
| { PPC::AND, PPC::AND_rec }, | |
| { PPC::AND8, PPC::AND8_rec }, | |
| { PPC::ANDC, PPC::ANDC_rec }, | |
| { PPC::ANDC8, PPC::ANDC8_rec }, | |
| { PPC::CNTLZD, PPC::CNTLZD_rec }, | |
| { PPC::CNTLZW, PPC::CNTLZW_rec }, | |
| { PPC::CNTLZW8, PPC::CNTLZW8_rec }, | |
| { PPC::CNTTZD, PPC::CNTTZD_rec }, | |
| { PPC::CNTTZW, PPC::CNTTZW_rec }, | |
| { PPC::CNTTZW8, PPC::CNTTZW8_rec }, | |
| { PPC::DIVD, PPC::DIVD_rec }, | |
| { PPC::DIVDE, PPC::DIVDE_rec }, | |
| { PPC::DIVDEO, PPC::DIVDEO_rec }, | |
| { PPC::DIVDEU, PPC::DIVDEU_rec }, | |
| { PPC::DIVDEUO, PPC::DIVDEUO_rec }, | |
| { PPC::DIVDO, PPC::DIVDO_rec }, | |
| { PPC::DIVDU, PPC::DIVDU_rec }, | |
| { PPC::DIVDUO, PPC::DIVDUO_rec }, | |
| { PPC::DIVW, PPC::DIVW_rec }, | |
| { PPC::DIVWE, PPC::DIVWE_rec }, | |
| { PPC::DIVWEO, PPC::DIVWEO_rec }, | |
| { PPC::DIVWEU, PPC::DIVWEU_rec }, | |
| { PPC::DIVWEUO, PPC::DIVWEUO_rec }, | |
| { PPC::DIVWO, PPC::DIVWO_rec }, | |
| { PPC::DIVWU, PPC::DIVWU_rec }, | |
| { PPC::DIVWUO, PPC::DIVWUO_rec }, | |
| { PPC::EQV, PPC::EQV_rec }, | |
| { PPC::EQV8, PPC::EQV8_rec }, | |
| { PPC::EXTSB, PPC::EXTSB_rec }, | |
| { PPC::EXTSB8, PPC::EXTSB8_rec }, | |
| { PPC::EXTSH, PPC::EXTSH_rec }, | |
| { PPC::EXTSH8, PPC::EXTSH8_rec }, | |
| { PPC::EXTSW, PPC::EXTSW_rec }, | |
| { PPC::EXTSWSLI, PPC::EXTSWSLI_rec }, | |
| { PPC::EXTSWSLI_32_64, PPC::EXTSWSLI_32_64_rec }, | |
| { PPC::EXTSW_32_64, PPC::EXTSW_32_64_rec }, | |
| { PPC::FABSD, PPC::FABSD_rec }, | |
| { PPC::FABSS, PPC::FABSS_rec }, | |
| { PPC::FADD, PPC::FADD_rec }, | |
| { PPC::FADDS, PPC::FADDS_rec }, | |
| { PPC::FCFID, PPC::FCFID_rec }, | |
| { PPC::FCFIDS, PPC::FCFIDS_rec }, | |
| { PPC::FCFIDU, PPC::FCFIDU_rec }, | |
| { PPC::FCFIDUS, PPC::FCFIDUS_rec }, | |
| { PPC::FCPSGND, PPC::FCPSGND_rec }, | |
| { PPC::FCPSGNS, PPC::FCPSGNS_rec }, | |
| { PPC::FCTID, PPC::FCTID_rec }, | |
| { PPC::FCTIDU, PPC::FCTIDU_rec }, | |
| { PPC::FCTIDUZ, PPC::FCTIDUZ_rec }, | |
| { PPC::FCTIDZ, PPC::FCTIDZ_rec }, | |
| { PPC::FCTIW, PPC::FCTIW_rec }, | |
| { PPC::FCTIWU, PPC::FCTIWU_rec }, | |
| { PPC::FCTIWUZ, PPC::FCTIWUZ_rec }, | |
| { PPC::FCTIWZ, PPC::FCTIWZ_rec }, | |
| { PPC::FDIV, PPC::FDIV_rec }, | |
| { PPC::FDIVS, PPC::FDIVS_rec }, | |
| { PPC::FMADD, PPC::FMADD_rec }, | |
| { PPC::FMADDS, PPC::FMADDS_rec }, | |
| { PPC::FMR, PPC::FMR_rec }, | |
| { PPC::FMSUB, PPC::FMSUB_rec }, | |
| { PPC::FMSUBS, PPC::FMSUBS_rec }, | |
| { PPC::FMUL, PPC::FMUL_rec }, | |
| { PPC::FMULS, PPC::FMULS_rec }, | |
| { PPC::FNABSD, PPC::FNABSD_rec }, | |
| { PPC::FNABSS, PPC::FNABSS_rec }, | |
| { PPC::FNEGD, PPC::FNEGD_rec }, | |
| { PPC::FNEGS, PPC::FNEGS_rec }, | |
| { PPC::FNMADD, PPC::FNMADD_rec }, | |
| { PPC::FNMADDS, PPC::FNMADDS_rec }, | |
| { PPC::FNMSUB, PPC::FNMSUB_rec }, | |
| { PPC::FNMSUBS, PPC::FNMSUBS_rec }, | |
| { PPC::FRE, PPC::FRE_rec }, | |
| { PPC::FRES, PPC::FRES_rec }, | |
| { PPC::FRIMD, PPC::FRIMD_rec }, | |
| { PPC::FRIMS, PPC::FRIMS_rec }, | |
| { PPC::FRIND, PPC::FRIND_rec }, | |
| { PPC::FRINS, PPC::FRINS_rec }, | |
| { PPC::FRIPD, PPC::FRIPD_rec }, | |
| { PPC::FRIPS, PPC::FRIPS_rec }, | |
| { PPC::FRIZD, PPC::FRIZD_rec }, | |
| { PPC::FRIZS, PPC::FRIZS_rec }, | |
| { PPC::FRSP, PPC::FRSP_rec }, | |
| { PPC::FRSQRTE, PPC::FRSQRTE_rec }, | |
| { PPC::FRSQRTES, PPC::FRSQRTES_rec }, | |
| { PPC::FSELD, PPC::FSELD_rec }, | |
| { PPC::FSELS, PPC::FSELS_rec }, | |
| { PPC::FSQRT, PPC::FSQRT_rec }, | |
| { PPC::FSQRTS, PPC::FSQRTS_rec }, | |
| { PPC::FSUB, PPC::FSUB_rec }, | |
| { PPC::FSUBS, PPC::FSUBS_rec }, | |
| { PPC::MULHD, PPC::MULHD_rec }, | |
| { PPC::MULHDU, PPC::MULHDU_rec }, | |
| { PPC::MULHW, PPC::MULHW_rec }, | |
| { PPC::MULHWU, PPC::MULHWU_rec }, | |
| { PPC::MULLD, PPC::MULLD_rec }, | |
| { PPC::MULLDO, PPC::MULLDO_rec }, | |
| { PPC::MULLW, PPC::MULLW_rec }, | |
| { PPC::MULLWO, PPC::MULLWO_rec }, | |
| { PPC::NAND, PPC::NAND_rec }, | |
| { PPC::NAND8, PPC::NAND8_rec }, | |
| { PPC::NEG, PPC::NEG_rec }, | |
| { PPC::NEG8, PPC::NEG8_rec }, | |
| { PPC::NEG8O, PPC::NEG8O_rec }, | |
| { PPC::NEGO, PPC::NEGO_rec }, | |
| { PPC::NOR, PPC::NOR_rec }, | |
| { PPC::NOR8, PPC::NOR8_rec }, | |
| { PPC::OR, PPC::OR_rec }, | |
| { PPC::OR8, PPC::OR8_rec }, | |
| { PPC::ORC, PPC::ORC_rec }, | |
| { PPC::ORC8, PPC::ORC8_rec }, | |
| { PPC::RLDCL, PPC::RLDCL_rec }, | |
| { PPC::RLDCR, PPC::RLDCR_rec }, | |
| { PPC::RLDIC, PPC::RLDIC_rec }, | |
| { PPC::RLDICL, PPC::RLDICL_rec }, | |
| { PPC::RLDICL_32, PPC::RLDICL_32_rec }, | |
| { PPC::RLDICR, PPC::RLDICR_rec }, | |
| { PPC::RLDIMI, PPC::RLDIMI_rec }, | |
| { PPC::RLWIMI, PPC::RLWIMI_rec }, | |
| { PPC::RLWIMI8, PPC::RLWIMI8_rec }, | |
| { PPC::RLWINM, PPC::RLWINM_rec }, | |
| { PPC::RLWINM8, PPC::RLWINM8_rec }, | |
| { PPC::RLWNM, PPC::RLWNM_rec }, | |
| { PPC::RLWNM8, PPC::RLWNM8_rec }, | |
| { PPC::SLD, PPC::SLD_rec }, | |
| { PPC::SLW, PPC::SLW_rec }, | |
| { PPC::SLW8, PPC::SLW8_rec }, | |
| { PPC::SRAD, PPC::SRAD_rec }, | |
| { PPC::SRADI, PPC::SRADI_rec }, | |
| { PPC::SRAW, PPC::SRAW_rec }, | |
| { PPC::SRAWI, PPC::SRAWI_rec }, | |
| { PPC::SRD, PPC::SRD_rec }, | |
| { PPC::SRW, PPC::SRW_rec }, | |
| { PPC::SRW8, PPC::SRW8_rec }, | |
| { PPC::SUBF, PPC::SUBF_rec }, | |
| { PPC::SUBF8, PPC::SUBF8_rec }, | |
| { PPC::SUBF8O, PPC::SUBF8O_rec }, | |
| { PPC::SUBFC, PPC::SUBFC_rec }, | |
| { PPC::SUBFC8, PPC::SUBFC8_rec }, | |
| { PPC::SUBFC8O, PPC::SUBFC8O_rec }, | |
| { PPC::SUBFCO, PPC::SUBFCO_rec }, | |
| { PPC::SUBFE, PPC::SUBFE_rec }, | |
| { PPC::SUBFE8, PPC::SUBFE8_rec }, | |
| { PPC::SUBFE8O, PPC::SUBFE8O_rec }, | |
| { PPC::SUBFEO, PPC::SUBFEO_rec }, | |
| { PPC::SUBFME, PPC::SUBFME_rec }, | |
| { PPC::SUBFME8, PPC::SUBFME8_rec }, | |
| { PPC::SUBFME8O, PPC::SUBFME8O_rec }, | |
| { PPC::SUBFMEO, PPC::SUBFMEO_rec }, | |
| { PPC::SUBFO, PPC::SUBFO_rec }, | |
| { PPC::SUBFZE, PPC::SUBFZE_rec }, | |
| { PPC::SUBFZE8, PPC::SUBFZE8_rec }, | |
| { PPC::SUBFZE8O, PPC::SUBFZE8O_rec }, | |
| { PPC::SUBFZEO, PPC::SUBFZEO_rec }, | |
| { PPC::XOR, PPC::XOR_rec }, | |
| { PPC::XOR8, PPC::XOR8_rec }, | |
| }; // End of getRecordFormOpcodeTable | |
| unsigned mid; | |
| unsigned start = 0; | |
| unsigned end = 176; | |
| while (start < end) { | |
| mid = start + (end - start)/2; | |
| if (Opcode == getRecordFormOpcodeTable[mid][0]) { | |
| break; | |
| } | |
| if (Opcode < getRecordFormOpcodeTable[mid][0]) | |
| end = mid; | |
| else | |
| start = mid + 1; | |
| } | |
| if (start == end) | |
| return -1; // Instruction doesn't exist in this table. | |
| return getRecordFormOpcodeTable[mid][1]; | |
| } | |
| } // end namespace PPC | |
| } // end namespace llvm | |
| #endif // GET_INSTRMAP_INFO | |