| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Assembly Writer Source Fragment *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| /// getMnemonic - This method is automatically generated by tablegen |
| /// from the instruction set description. |
| std::pair<const char *, uint64_t> AArch64AppleInstPrinter::getMnemonic(const MCInst *MI) { |
| |
| #ifdef __GNUC__ |
| #pragma GCC diagnostic push |
| #pragma GCC diagnostic ignored "-Woverlength-strings" |
| #endif |
| static const char AsmStrs[] = { |
| /* 0 */ "st64bv0\t\0" |
| /* 9 */ "ld1\t\0" |
| /* 14 */ "stl1\t\0" |
| /* 20 */ "trn1\t\0" |
| /* 26 */ "ldap1\t\0" |
| /* 33 */ "zip1\t\0" |
| /* 39 */ "uzp1\t\0" |
| /* 45 */ "zipq1\t\0" |
| /* 52 */ "uzpq1\t\0" |
| /* 59 */ "dcps1\t\0" |
| /* 66 */ "st1\t\0" |
| /* 71 */ "rax1\t\0" |
| /* 77 */ "rev32\t\0" |
| /* 84 */ "ld2\t\0" |
| /* 89 */ "luti2\t\0" |
| /* 96 */ "fmlal2\t\0" |
| /* 104 */ "fmlsl2\t\0" |
| /* 112 */ "fcvtl2\t\0" |
| /* 120 */ "trn2\t\0" |
| /* 126 */ "fcvtn2\t\0" |
| /* 134 */ "fcvtxn2\t\0" |
| /* 143 */ "zip2\t\0" |
| /* 149 */ "uzp2\t\0" |
| /* 155 */ "zipq2\t\0" |
| /* 162 */ "uzpq2\t\0" |
| /* 169 */ "dcps2\t\0" |
| /* 176 */ "st2\t\0" |
| /* 181 */ "ld3\t\0" |
| /* 186 */ "eor3\t\0" |
| /* 192 */ "dcps3\t\0" |
| /* 199 */ "st3\t\0" |
| /* 204 */ "ld4\t\0" |
| /* 209 */ "luti4\t\0" |
| /* 216 */ "st4\t\0" |
| /* 221 */ "rev16\t\0" |
| /* 228 */ "braa\t\0" |
| /* 234 */ "ldraa\t\0" |
| /* 241 */ "blraa\t\0" |
| /* 248 */ "saba\t\0" |
| /* 254 */ "uaba\t\0" |
| /* 260 */ "pacda\t\0" |
| /* 267 */ "ldadda\t\0" |
| /* 275 */ "fadda\t\0" |
| /* 282 */ "autda\t\0" |
| /* 289 */ "pacga\t\0" |
| /* 296 */ "addha\t\0" |
| /* 303 */ "pacia\t\0" |
| /* 310 */ "autia\t\0" |
| /* 317 */ "brka\t\0" |
| /* 323 */ "fcmla\t\0" |
| /* 330 */ "bfmla\t\0" |
| /* 337 */ "bfmmla\t\0" |
| /* 345 */ "usmmla\t\0" |
| /* 353 */ "ummla\t\0" |
| /* 360 */ "fnmla\t\0" |
| /* 367 */ "ldsmina\t\0" |
| /* 376 */ "ldumina\t\0" |
| /* 385 */ "brkpa\t\0" |
| /* 392 */ "bmopa\t\0" |
| /* 399 */ "bfmopa\t\0" |
| /* 407 */ "usmopa\t\0" |
| /* 415 */ "sumopa\t\0" |
| /* 423 */ "rcwsswppa\t\0" |
| /* 434 */ "rcwswppa\t\0" |
| /* 444 */ "ldclrpa\t\0" |
| /* 453 */ "rcwsclrpa\t\0" |
| /* 464 */ "rcwclrpa\t\0" |
| /* 474 */ "rcwscaspa\t\0" |
| /* 485 */ "rcwcaspa\t\0" |
| /* 495 */ "ldsetpa\t\0" |
| /* 504 */ "rcwssetpa\t\0" |
| /* 515 */ "rcwsetpa\t\0" |
| /* 525 */ "rcwsswpa\t\0" |
| /* 535 */ "rcwswpa\t\0" |
| /* 544 */ "fexpa\t\0" |
| /* 551 */ "ldclra\t\0" |
| /* 559 */ "rcwsclra\t\0" |
| /* 569 */ "rcwclra\t\0" |
| /* 578 */ "ldeora\t\0" |
| /* 586 */ "srsra\t\0" |
| /* 593 */ "ursra\t\0" |
| /* 600 */ "ssra\t\0" |
| /* 606 */ "usra\t\0" |
| /* 612 */ "rcwscasa\t\0" |
| /* 622 */ "rcwcasa\t\0" |
| /* 631 */ "ldseta\t\0" |
| /* 639 */ "rcwsseta\t\0" |
| /* 649 */ "rcwseta\t\0" |
| /* 658 */ "frinta\t\0" |
| /* 666 */ "clasta\t\0" |
| /* 674 */ "addva\t\0" |
| /* 681 */ "mova\t\0" |
| /* 687 */ "ldsmaxa\t\0" |
| /* 696 */ "ldumaxa\t\0" |
| /* 705 */ "pacdza\t\0" |
| /* 713 */ "autdza\t\0" |
| /* 721 */ "paciza\t\0" |
| /* 729 */ "autiza\t\0" |
| /* 737 */ "ins.b\t\0" |
| /* 744 */ "smov.b\t\0" |
| /* 752 */ "umov.b\t\0" |
| /* 760 */ "ld1b\t\0" |
| /* 766 */ "ldff1b\t\0" |
| /* 774 */ "ldnf1b\t\0" |
| /* 782 */ "ldnt1b\t\0" |
| /* 790 */ "stnt1b\t\0" |
| /* 798 */ "st1b\t\0" |
| /* 804 */ "crc32b\t\0" |
| /* 812 */ "ld2b\t\0" |
| /* 818 */ "st2b\t\0" |
| /* 824 */ "ld3b\t\0" |
| /* 830 */ "st3b\t\0" |
| /* 836 */ "ld64b\t\0" |
| /* 843 */ "st64b\t\0" |
| /* 850 */ "ld4b\t\0" |
| /* 856 */ "st4b\t\0" |
| /* 862 */ "trn1.16b\t\0" |
| /* 872 */ "zip1.16b\t\0" |
| /* 882 */ "uzp1.16b\t\0" |
| /* 892 */ "rev32.16b\t\0" |
| /* 903 */ "rsubhn2.16b\t\0" |
| /* 916 */ "raddhn2.16b\t\0" |
| /* 929 */ "sqshrn2.16b\t\0" |
| /* 942 */ "uqshrn2.16b\t\0" |
| /* 955 */ "sqrshrn2.16b\t\0" |
| /* 969 */ "uqrshrn2.16b\t\0" |
| /* 983 */ "trn2.16b\t\0" |
| /* 993 */ "sqxtn2.16b\t\0" |
| /* 1005 */ "uqxtn2.16b\t\0" |
| /* 1017 */ "sqshrun2.16b\t\0" |
| /* 1031 */ "sqrshrun2.16b\t\0" |
| /* 1046 */ "sqxtun2.16b\t\0" |
| /* 1059 */ "zip2.16b\t\0" |
| /* 1069 */ "uzp2.16b\t\0" |
| /* 1079 */ "eor3.16b\t\0" |
| /* 1089 */ "rev64.16b\t\0" |
| /* 1100 */ "rev16.16b\t\0" |
| /* 1111 */ "saba.16b\t\0" |
| /* 1121 */ "uaba.16b\t\0" |
| /* 1131 */ "mla.16b\t\0" |
| /* 1140 */ "srsra.16b\t\0" |
| /* 1151 */ "ursra.16b\t\0" |
| /* 1162 */ "ssra.16b\t\0" |
| /* 1172 */ "usra.16b\t\0" |
| /* 1182 */ "shsub.16b\t\0" |
| /* 1193 */ "uhsub.16b\t\0" |
| /* 1204 */ "sqsub.16b\t\0" |
| /* 1215 */ "uqsub.16b\t\0" |
| /* 1226 */ "bic.16b\t\0" |
| /* 1235 */ "aesimc.16b\t\0" |
| /* 1247 */ "aesmc.16b\t\0" |
| /* 1258 */ "sabd.16b\t\0" |
| /* 1268 */ "uabd.16b\t\0" |
| /* 1278 */ "srhadd.16b\t\0" |
| /* 1290 */ "urhadd.16b\t\0" |
| /* 1302 */ "shadd.16b\t\0" |
| /* 1313 */ "uhadd.16b\t\0" |
| /* 1324 */ "usqadd.16b\t\0" |
| /* 1336 */ "suqadd.16b\t\0" |
| /* 1348 */ "and.16b\t\0" |
| /* 1357 */ "aesd.16b\t\0" |
| /* 1367 */ "cmge.16b\t\0" |
| /* 1377 */ "cmle.16b\t\0" |
| /* 1387 */ "aese.16b\t\0" |
| /* 1397 */ "bif.16b\t\0" |
| /* 1406 */ "sqneg.16b\t\0" |
| /* 1417 */ "cmhi.16b\t\0" |
| /* 1427 */ "sli.16b\t\0" |
| /* 1436 */ "sri.16b\t\0" |
| /* 1445 */ "movi.16b\t\0" |
| /* 1455 */ "sqshl.16b\t\0" |
| /* 1466 */ "uqshl.16b\t\0" |
| /* 1477 */ "sqrshl.16b\t\0" |
| /* 1489 */ "uqrshl.16b\t\0" |
| /* 1501 */ "srshl.16b\t\0" |
| /* 1512 */ "urshl.16b\t\0" |
| /* 1523 */ "sshl.16b\t\0" |
| /* 1533 */ "ushl.16b\t\0" |
| /* 1543 */ "bsl.16b\t\0" |
| /* 1552 */ "pmul.16b\t\0" |
| /* 1562 */ "smin.16b\t\0" |
| /* 1572 */ "umin.16b\t\0" |
| /* 1582 */ "orn.16b\t\0" |
| /* 1591 */ "addp.16b\t\0" |
| /* 1601 */ "sminp.16b\t\0" |
| /* 1612 */ "uminp.16b\t\0" |
| /* 1623 */ "dup.16b\t\0" |
| /* 1632 */ "smaxp.16b\t\0" |
| /* 1643 */ "umaxp.16b\t\0" |
| /* 1654 */ "cmeq.16b\t\0" |
| /* 1664 */ "srshr.16b\t\0" |
| /* 1675 */ "urshr.16b\t\0" |
| /* 1686 */ "sshr.16b\t\0" |
| /* 1696 */ "ushr.16b\t\0" |
| /* 1706 */ "eor.16b\t\0" |
| /* 1715 */ "orr.16b\t\0" |
| /* 1724 */ "sqabs.16b\t\0" |
| /* 1735 */ "cmhs.16b\t\0" |
| /* 1745 */ "cls.16b\t\0" |
| /* 1754 */ "mls.16b\t\0" |
| /* 1763 */ "cmgt.16b\t\0" |
| /* 1773 */ "rbit.16b\t\0" |
| /* 1783 */ "cmlt.16b\t\0" |
| /* 1793 */ "cnt.16b\t\0" |
| /* 1802 */ "not.16b\t\0" |
| /* 1811 */ "cmtst.16b\t\0" |
| /* 1822 */ "ext.16b\t\0" |
| /* 1831 */ "sqshlu.16b\t\0" |
| /* 1843 */ "addv.16b\t\0" |
| /* 1853 */ "saddlv.16b\t\0" |
| /* 1865 */ "uaddlv.16b\t\0" |
| /* 1877 */ "sminv.16b\t\0" |
| /* 1888 */ "uminv.16b\t\0" |
| /* 1899 */ "smaxv.16b\t\0" |
| /* 1910 */ "umaxv.16b\t\0" |
| /* 1921 */ "bcax.16b\t\0" |
| /* 1931 */ "smax.16b\t\0" |
| /* 1941 */ "umax.16b\t\0" |
| /* 1951 */ "clz.16b\t\0" |
| /* 1960 */ "trn1.8b\t\0" |
| /* 1969 */ "zip1.8b\t\0" |
| /* 1978 */ "uzp1.8b\t\0" |
| /* 1987 */ "rev32.8b\t\0" |
| /* 1997 */ "trn2.8b\t\0" |
| /* 2006 */ "zip2.8b\t\0" |
| /* 2015 */ "uzp2.8b\t\0" |
| /* 2024 */ "rev64.8b\t\0" |
| /* 2034 */ "rev16.8b\t\0" |
| /* 2044 */ "saba.8b\t\0" |
| /* 2053 */ "uaba.8b\t\0" |
| /* 2062 */ "mla.8b\t\0" |
| /* 2070 */ "srsra.8b\t\0" |
| /* 2080 */ "ursra.8b\t\0" |
| /* 2090 */ "ssra.8b\t\0" |
| /* 2099 */ "usra.8b\t\0" |
| /* 2108 */ "shsub.8b\t\0" |
| /* 2118 */ "uhsub.8b\t\0" |
| /* 2128 */ "sqsub.8b\t\0" |
| /* 2138 */ "uqsub.8b\t\0" |
| /* 2148 */ "bic.8b\t\0" |
| /* 2156 */ "sabd.8b\t\0" |
| /* 2165 */ "uabd.8b\t\0" |
| /* 2174 */ "srhadd.8b\t\0" |
| /* 2185 */ "urhadd.8b\t\0" |
| /* 2196 */ "shadd.8b\t\0" |
| /* 2206 */ "uhadd.8b\t\0" |
| /* 2216 */ "usqadd.8b\t\0" |
| /* 2227 */ "suqadd.8b\t\0" |
| /* 2238 */ "and.8b\t\0" |
| /* 2246 */ "cmge.8b\t\0" |
| /* 2255 */ "cmle.8b\t\0" |
| /* 2264 */ "bif.8b\t\0" |
| /* 2272 */ "sqneg.8b\t\0" |
| /* 2282 */ "cmhi.8b\t\0" |
| /* 2291 */ "sli.8b\t\0" |
| /* 2299 */ "sri.8b\t\0" |
| /* 2307 */ "movi.8b\t\0" |
| /* 2316 */ "sqshl.8b\t\0" |
| /* 2326 */ "uqshl.8b\t\0" |
| /* 2336 */ "sqrshl.8b\t\0" |
| /* 2347 */ "uqrshl.8b\t\0" |
| /* 2358 */ "srshl.8b\t\0" |
| /* 2368 */ "urshl.8b\t\0" |
| /* 2378 */ "sshl.8b\t\0" |
| /* 2387 */ "ushl.8b\t\0" |
| /* 2396 */ "bsl.8b\t\0" |
| /* 2404 */ "pmul.8b\t\0" |
| /* 2413 */ "rsubhn.8b\t\0" |
| /* 2424 */ "raddhn.8b\t\0" |
| /* 2435 */ "smin.8b\t\0" |
| /* 2444 */ "umin.8b\t\0" |
| /* 2453 */ "sqshrn.8b\t\0" |
| /* 2464 */ "uqshrn.8b\t\0" |
| /* 2475 */ "sqrshrn.8b\t\0" |
| /* 2487 */ "uqrshrn.8b\t\0" |
| /* 2499 */ "orn.8b\t\0" |
| /* 2507 */ "sqxtn.8b\t\0" |
| /* 2517 */ "uqxtn.8b\t\0" |
| /* 2527 */ "sqshrun.8b\t\0" |
| /* 2539 */ "sqrshrun.8b\t\0" |
| /* 2552 */ "sqxtun.8b\t\0" |
| /* 2563 */ "addp.8b\t\0" |
| /* 2572 */ "sminp.8b\t\0" |
| /* 2582 */ "uminp.8b\t\0" |
| /* 2592 */ "dup.8b\t\0" |
| /* 2600 */ "smaxp.8b\t\0" |
| /* 2610 */ "umaxp.8b\t\0" |
| /* 2620 */ "cmeq.8b\t\0" |
| /* 2629 */ "srshr.8b\t\0" |
| /* 2639 */ "urshr.8b\t\0" |
| /* 2649 */ "sshr.8b\t\0" |
| /* 2658 */ "ushr.8b\t\0" |
| /* 2667 */ "eor.8b\t\0" |
| /* 2675 */ "orr.8b\t\0" |
| /* 2683 */ "sqabs.8b\t\0" |
| /* 2693 */ "cmhs.8b\t\0" |
| /* 2702 */ "cls.8b\t\0" |
| /* 2710 */ "mls.8b\t\0" |
| /* 2718 */ "cmgt.8b\t\0" |
| /* 2727 */ "rbit.8b\t\0" |
| /* 2736 */ "cmlt.8b\t\0" |
| /* 2745 */ "cnt.8b\t\0" |
| /* 2753 */ "not.8b\t\0" |
| /* 2761 */ "cmtst.8b\t\0" |
| /* 2771 */ "ext.8b\t\0" |
| /* 2779 */ "sqshlu.8b\t\0" |
| /* 2790 */ "addv.8b\t\0" |
| /* 2799 */ "saddlv.8b\t\0" |
| /* 2810 */ "uaddlv.8b\t\0" |
| /* 2821 */ "sminv.8b\t\0" |
| /* 2831 */ "uminv.8b\t\0" |
| /* 2841 */ "smaxv.8b\t\0" |
| /* 2851 */ "umaxv.8b\t\0" |
| /* 2861 */ "smax.8b\t\0" |
| /* 2870 */ "umax.8b\t\0" |
| /* 2879 */ "clz.8b\t\0" |
| /* 2887 */ "ldaddab\t\0" |
| /* 2896 */ "ldsminab\t\0" |
| /* 2906 */ "lduminab\t\0" |
| /* 2916 */ "swpab\t\0" |
| /* 2923 */ "brab\t\0" |
| /* 2929 */ "ldrab\t\0" |
| /* 2936 */ "blrab\t\0" |
| /* 2943 */ "ldclrab\t\0" |
| /* 2952 */ "ldeorab\t\0" |
| /* 2961 */ "casab\t\0" |
| /* 2968 */ "ldsetab\t\0" |
| /* 2977 */ "ldsmaxab\t\0" |
| /* 2987 */ "ldumaxab\t\0" |
| /* 2997 */ "crc32cb\t\0" |
| /* 3006 */ "sqdecb\t\0" |
| /* 3014 */ "uqdecb\t\0" |
| /* 3022 */ "sqincb\t\0" |
| /* 3030 */ "uqincb\t\0" |
| /* 3038 */ "pacdb\t\0" |
| /* 3045 */ "ldaddb\t\0" |
| /* 3053 */ "autdb\t\0" |
| /* 3060 */ "prfb\t\0" |
| /* 3066 */ "flogb\t\0" |
| /* 3073 */ "pacib\t\0" |
| /* 3080 */ "autib\t\0" |
| /* 3087 */ "brkb\t\0" |
| /* 3093 */ "sabalb\t\0" |
| /* 3101 */ "uabalb\t\0" |
| /* 3109 */ "ldaddalb\t\0" |
| /* 3119 */ "sqdmlalb\t\0" |
| /* 3129 */ "bfmlalb\t\0" |
| /* 3138 */ "smlalb\t\0" |
| /* 3146 */ "umlalb\t\0" |
| /* 3154 */ "ldsminalb\t\0" |
| /* 3165 */ "lduminalb\t\0" |
| /* 3176 */ "swpalb\t\0" |
| /* 3184 */ "ldclralb\t\0" |
| /* 3194 */ "ldeoralb\t\0" |
| /* 3204 */ "casalb\t\0" |
| /* 3212 */ "ldsetalb\t\0" |
| /* 3222 */ "ldsmaxalb\t\0" |
| /* 3233 */ "ldumaxalb\t\0" |
| /* 3244 */ "ssublb\t\0" |
| /* 3252 */ "usublb\t\0" |
| /* 3260 */ "sbclb\t\0" |
| /* 3267 */ "adclb\t\0" |
| /* 3274 */ "sabdlb\t\0" |
| /* 3282 */ "uabdlb\t\0" |
| /* 3290 */ "ldaddlb\t\0" |
| /* 3299 */ "saddlb\t\0" |
| /* 3307 */ "uaddlb\t\0" |
| /* 3315 */ "sshllb\t\0" |
| /* 3323 */ "ushllb\t\0" |
| /* 3331 */ "sqdmullb\t\0" |
| /* 3341 */ "pmullb\t\0" |
| /* 3349 */ "smullb\t\0" |
| /* 3357 */ "umullb\t\0" |
| /* 3365 */ "ldsminlb\t\0" |
| /* 3375 */ "lduminlb\t\0" |
| /* 3385 */ "swplb\t\0" |
| /* 3392 */ "ldclrlb\t\0" |
| /* 3401 */ "ldeorlb\t\0" |
| /* 3410 */ "caslb\t\0" |
| /* 3417 */ "sqdmlslb\t\0" |
| /* 3427 */ "bfmlslb\t\0" |
| /* 3436 */ "smlslb\t\0" |
| /* 3444 */ "umlslb\t\0" |
| /* 3452 */ "ldsetlb\t\0" |
| /* 3461 */ "ldsmaxlb\t\0" |
| /* 3471 */ "ldumaxlb\t\0" |
| /* 3481 */ "dmb\t\0" |
| /* 3486 */ "rsubhnb\t\0" |
| /* 3495 */ "raddhnb\t\0" |
| /* 3504 */ "ldsminb\t\0" |
| /* 3513 */ "lduminb\t\0" |
| /* 3522 */ "sqshrnb\t\0" |
| /* 3531 */ "uqshrnb\t\0" |
| /* 3540 */ "sqrshrnb\t\0" |
| /* 3550 */ "uqrshrnb\t\0" |
| /* 3560 */ "sqxtnb\t\0" |
| /* 3568 */ "uqxtnb\t\0" |
| /* 3576 */ "sqshrunb\t\0" |
| /* 3586 */ "sqrshrunb\t\0" |
| /* 3597 */ "sqxtunb\t\0" |
| /* 3606 */ "ld1rob\t\0" |
| /* 3614 */ "brkpb\t\0" |
| /* 3621 */ "swpb\t\0" |
| /* 3627 */ "ld1rqb\t\0" |
| /* 3635 */ "ld1rb\t\0" |
| /* 3642 */ "ldarb\t\0" |
| /* 3649 */ "ldlarb\t\0" |
| /* 3657 */ "ldrb\t\0" |
| /* 3663 */ "ldclrb\t\0" |
| /* 3671 */ "stllrb\t\0" |
| /* 3679 */ "stlrb\t\0" |
| /* 3686 */ "ldeorb\t\0" |
| /* 3694 */ "ldaprb\t\0" |
| /* 3702 */ "ldtrb\t\0" |
| /* 3709 */ "strb\t\0" |
| /* 3715 */ "sttrb\t\0" |
| /* 3722 */ "ldurb\t\0" |
| /* 3729 */ "stlurb\t\0" |
| /* 3737 */ "ldapurb\t\0" |
| /* 3746 */ "sturb\t\0" |
| /* 3753 */ "ldaxrb\t\0" |
| /* 3761 */ "ldxrb\t\0" |
| /* 3768 */ "stlxrb\t\0" |
| /* 3776 */ "stxrb\t\0" |
| /* 3783 */ "ld1sb\t\0" |
| /* 3790 */ "ldff1sb\t\0" |
| /* 3799 */ "ldnf1sb\t\0" |
| /* 3808 */ "ldnt1sb\t\0" |
| /* 3817 */ "casb\t\0" |
| /* 3823 */ "dsb\t\0" |
| /* 3828 */ "isb\t\0" |
| /* 3833 */ "fmsb\t\0" |
| /* 3839 */ "fnmsb\t\0" |
| /* 3846 */ "ld1rsb\t\0" |
| /* 3854 */ "ldrsb\t\0" |
| /* 3861 */ "ldtrsb\t\0" |
| /* 3869 */ "ldursb\t\0" |
| /* 3877 */ "ldapursb\t\0" |
| /* 3887 */ "tsb\t\0" |
| /* 3892 */ "ldsetb\t\0" |
| /* 3900 */ "ssubltb\t\0" |
| /* 3909 */ "cntb\t\0" |
| /* 3915 */ "eortb\t\0" |
| /* 3922 */ "clastb\t\0" |
| /* 3930 */ "sxtb\t\0" |
| /* 3936 */ "uxtb\t\0" |
| /* 3942 */ "bfsub\t\0" |
| /* 3949 */ "shsub\t\0" |
| /* 3956 */ "uhsub\t\0" |
| /* 3963 */ "fmsub\t\0" |
| /* 3970 */ "fnmsub\t\0" |
| /* 3978 */ "sqsub\t\0" |
| /* 3985 */ "uqsub\t\0" |
| /* 3992 */ "revb\t\0" |
| /* 3998 */ "ssubwb\t\0" |
| /* 4006 */ "usubwb\t\0" |
| /* 4014 */ "saddwb\t\0" |
| /* 4022 */ "uaddwb\t\0" |
| /* 4030 */ "ldsmaxb\t\0" |
| /* 4039 */ "ldumaxb\t\0" |
| /* 4048 */ "pacdzb\t\0" |
| /* 4056 */ "autdzb\t\0" |
| /* 4064 */ "pacizb\t\0" |
| /* 4072 */ "autizb\t\0" |
| /* 4080 */ "sbc\t\0" |
| /* 4085 */ "adc\t\0" |
| /* 4090 */ "bic\t\0" |
| /* 4095 */ "aesimc\t\0" |
| /* 4103 */ "aesmc\t\0" |
| /* 4110 */ "csinc\t\0" |
| /* 4117 */ "hvc\t\0" |
| /* 4122 */ "svc\t\0" |
| /* 4127 */ "fmla.d\t\0" |
| /* 4135 */ "fmul.d\t\0" |
| /* 4143 */ "fmls.d\t\0" |
| /* 4151 */ "ins.d\t\0" |
| /* 4158 */ "fmov.d\t\0" |
| /* 4166 */ "umov.d\t\0" |
| /* 4174 */ "fmulx.d\t\0" |
| /* 4183 */ "sadalp.1d\t\0" |
| /* 4194 */ "uadalp.1d\t\0" |
| /* 4205 */ "saddlp.1d\t\0" |
| /* 4216 */ "uaddlp.1d\t\0" |
| /* 4227 */ "ld1d\t\0" |
| /* 4233 */ "ldff1d\t\0" |
| /* 4241 */ "ldnf1d\t\0" |
| /* 4249 */ "ldnt1d\t\0" |
| /* 4257 */ "stnt1d\t\0" |
| /* 4265 */ "st1d\t\0" |
| /* 4271 */ "sha512su0.2d\t\0" |
| /* 4285 */ "trn1.2d\t\0" |
| /* 4294 */ "zip1.2d\t\0" |
| /* 4303 */ "uzp1.2d\t\0" |
| /* 4312 */ "sha512su1.2d\t\0" |
| /* 4326 */ "rax1.2d\t\0" |
| /* 4335 */ "sha512h2.2d\t\0" |
| /* 4348 */ "sabal2.2d\t\0" |
| /* 4359 */ "uabal2.2d\t\0" |
| /* 4370 */ "sqdmlal2.2d\t\0" |
| /* 4383 */ "smlal2.2d\t\0" |
| /* 4394 */ "umlal2.2d\t\0" |
| /* 4405 */ "ssubl2.2d\t\0" |
| /* 4416 */ "usubl2.2d\t\0" |
| /* 4427 */ "sabdl2.2d\t\0" |
| /* 4438 */ "uabdl2.2d\t\0" |
| /* 4449 */ "saddl2.2d\t\0" |
| /* 4460 */ "uaddl2.2d\t\0" |
| /* 4471 */ "sshll2.2d\t\0" |
| /* 4482 */ "ushll2.2d\t\0" |
| /* 4493 */ "sqdmull2.2d\t\0" |
| /* 4506 */ "smull2.2d\t\0" |
| /* 4517 */ "umull2.2d\t\0" |
| /* 4528 */ "sqdmlsl2.2d\t\0" |
| /* 4541 */ "smlsl2.2d\t\0" |
| /* 4552 */ "umlsl2.2d\t\0" |
| /* 4563 */ "trn2.2d\t\0" |
| /* 4572 */ "zip2.2d\t\0" |
| /* 4581 */ "uzp2.2d\t\0" |
| /* 4590 */ "ssubw2.2d\t\0" |
| /* 4601 */ "usubw2.2d\t\0" |
| /* 4612 */ "saddw2.2d\t\0" |
| /* 4623 */ "uaddw2.2d\t\0" |
| /* 4634 */ "fcmla.2d\t\0" |
| /* 4644 */ "fmla.2d\t\0" |
| /* 4653 */ "srsra.2d\t\0" |
| /* 4663 */ "ursra.2d\t\0" |
| /* 4673 */ "ssra.2d\t\0" |
| /* 4682 */ "usra.2d\t\0" |
| /* 4691 */ "frinta.2d\t\0" |
| /* 4702 */ "fsub.2d\t\0" |
| /* 4711 */ "sqsub.2d\t\0" |
| /* 4721 */ "uqsub.2d\t\0" |
| /* 4731 */ "fabd.2d\t\0" |
| /* 4740 */ "fcadd.2d\t\0" |
| /* 4750 */ "fadd.2d\t\0" |
| /* 4759 */ "usqadd.2d\t\0" |
| /* 4770 */ "suqadd.2d\t\0" |
| /* 4781 */ "facge.2d\t\0" |
| /* 4791 */ "fcmge.2d\t\0" |
| /* 4801 */ "fcmle.2d\t\0" |
| /* 4811 */ "frecpe.2d\t\0" |
| /* 4822 */ "frsqrte.2d\t\0" |
| /* 4834 */ "scvtf.2d\t\0" |
| /* 4844 */ "ucvtf.2d\t\0" |
| /* 4854 */ "fneg.2d\t\0" |
| /* 4863 */ "sqneg.2d\t\0" |
| /* 4873 */ "sha512h.2d\t\0" |
| /* 4885 */ "cmhi.2d\t\0" |
| /* 4894 */ "sli.2d\t\0" |
| /* 4902 */ "sri.2d\t\0" |
| /* 4910 */ "frinti.2d\t\0" |
| /* 4921 */ "movi.2d\t\0" |
| /* 4930 */ "sabal.2d\t\0" |
| /* 4940 */ "uabal.2d\t\0" |
| /* 4950 */ "sqdmlal.2d\t\0" |
| /* 4962 */ "smlal.2d\t\0" |
| /* 4972 */ "umlal.2d\t\0" |
| /* 4982 */ "ssubl.2d\t\0" |
| /* 4992 */ "usubl.2d\t\0" |
| /* 5002 */ "sabdl.2d\t\0" |
| /* 5012 */ "uabdl.2d\t\0" |
| /* 5022 */ "saddl.2d\t\0" |
| /* 5032 */ "uaddl.2d\t\0" |
| /* 5042 */ "sqshl.2d\t\0" |
| /* 5052 */ "uqshl.2d\t\0" |
| /* 5062 */ "sqrshl.2d\t\0" |
| /* 5073 */ "uqrshl.2d\t\0" |
| /* 5084 */ "srshl.2d\t\0" |
| /* 5094 */ "urshl.2d\t\0" |
| /* 5104 */ "sshl.2d\t\0" |
| /* 5113 */ "ushl.2d\t\0" |
| /* 5122 */ "sshll.2d\t\0" |
| /* 5132 */ "ushll.2d\t\0" |
| /* 5142 */ "sqdmull.2d\t\0" |
| /* 5154 */ "smull.2d\t\0" |
| /* 5164 */ "umull.2d\t\0" |
| /* 5174 */ "sqdmlsl.2d\t\0" |
| /* 5186 */ "smlsl.2d\t\0" |
| /* 5196 */ "umlsl.2d\t\0" |
| /* 5206 */ "fmul.2d\t\0" |
| /* 5215 */ "fminnm.2d\t\0" |
| /* 5226 */ "fmaxnm.2d\t\0" |
| /* 5237 */ "frintm.2d\t\0" |
| /* 5248 */ "fmin.2d\t\0" |
| /* 5257 */ "frintn.2d\t\0" |
| /* 5268 */ "faddp.2d\t\0" |
| /* 5278 */ "sadalp.2d\t\0" |
| /* 5289 */ "uadalp.2d\t\0" |
| /* 5300 */ "saddlp.2d\t\0" |
| /* 5311 */ "uaddlp.2d\t\0" |
| /* 5322 */ "fminnmp.2d\t\0" |
| /* 5334 */ "fmaxnmp.2d\t\0" |
| /* 5346 */ "fminp.2d\t\0" |
| /* 5356 */ "frintp.2d\t\0" |
| /* 5367 */ "dup.2d\t\0" |
| /* 5375 */ "fmaxp.2d\t\0" |
| /* 5385 */ "fcmeq.2d\t\0" |
| /* 5395 */ "xar.2d\t\0" |
| /* 5403 */ "srshr.2d\t\0" |
| /* 5413 */ "urshr.2d\t\0" |
| /* 5423 */ "sshr.2d\t\0" |
| /* 5432 */ "ushr.2d\t\0" |
| /* 5441 */ "fcvtas.2d\t\0" |
| /* 5452 */ "fabs.2d\t\0" |
| /* 5461 */ "sqabs.2d\t\0" |
| /* 5471 */ "cmhs.2d\t\0" |
| /* 5480 */ "fmls.2d\t\0" |
| /* 5489 */ "fcvtms.2d\t\0" |
| /* 5500 */ "fcvtns.2d\t\0" |
| /* 5511 */ "frecps.2d\t\0" |
| /* 5522 */ "fcvtps.2d\t\0" |
| /* 5533 */ "frsqrts.2d\t\0" |
| /* 5545 */ "fcvtzs.2d\t\0" |
| /* 5556 */ "facgt.2d\t\0" |
| /* 5566 */ "fcmgt.2d\t\0" |
| /* 5576 */ "fcmlt.2d\t\0" |
| /* 5586 */ "fsqrt.2d\t\0" |
| /* 5596 */ "cmtst.2d\t\0" |
| /* 5606 */ "fcvtau.2d\t\0" |
| /* 5617 */ "sqshlu.2d\t\0" |
| /* 5628 */ "fcvtmu.2d\t\0" |
| /* 5639 */ "fcvtnu.2d\t\0" |
| /* 5650 */ "fcvtpu.2d\t\0" |
| /* 5661 */ "fcvtzu.2d\t\0" |
| /* 5672 */ "fdiv.2d\t\0" |
| /* 5681 */ "fmov.2d\t\0" |
| /* 5690 */ "ssubw.2d\t\0" |
| /* 5700 */ "usubw.2d\t\0" |
| /* 5710 */ "saddw.2d\t\0" |
| /* 5720 */ "uaddw.2d\t\0" |
| /* 5730 */ "frint32x.2d\t\0" |
| /* 5743 */ "frint64x.2d\t\0" |
| /* 5756 */ "fmax.2d\t\0" |
| /* 5765 */ "fmulx.2d\t\0" |
| /* 5775 */ "frintx.2d\t\0" |
| /* 5786 */ "frint32z.2d\t\0" |
| /* 5799 */ "frint64z.2d\t\0" |
| /* 5812 */ "frintz.2d\t\0" |
| /* 5823 */ "ld2d\t\0" |
| /* 5829 */ "st2d\t\0" |
| /* 5835 */ "ld3d\t\0" |
| /* 5841 */ "st3d\t\0" |
| /* 5847 */ "ld4d\t\0" |
| /* 5853 */ "st4d\t\0" |
| /* 5859 */ "fmad\t\0" |
| /* 5865 */ "fnmad\t\0" |
| /* 5872 */ "ftmad\t\0" |
| /* 5879 */ "fabd\t\0" |
| /* 5885 */ "sabd\t\0" |
| /* 5891 */ "uabd\t\0" |
| /* 5897 */ "xpacd\t\0" |
| /* 5904 */ "sqdecd\t\0" |
| /* 5912 */ "uqdecd\t\0" |
| /* 5920 */ "sqincd\t\0" |
| /* 5928 */ "uqincd\t\0" |
| /* 5936 */ "fcadd\t\0" |
| /* 5943 */ "sqcadd\t\0" |
| /* 5951 */ "ldadd\t\0" |
| /* 5958 */ "bfadd\t\0" |
| /* 5965 */ "srhadd\t\0" |
| /* 5973 */ "urhadd\t\0" |
| /* 5981 */ "shadd\t\0" |
| /* 5988 */ "uhadd\t\0" |
| /* 5995 */ "fmadd\t\0" |
| /* 6002 */ "fnmadd\t\0" |
| /* 6010 */ "usqadd\t\0" |
| /* 6018 */ "suqadd\t\0" |
| /* 6026 */ "prfd\t\0" |
| /* 6032 */ "nand\t\0" |
| /* 6038 */ "ld1rod\t\0" |
| /* 6046 */ "ld1rqd\t\0" |
| /* 6054 */ "ld1rd\t\0" |
| /* 6061 */ "asrd\t\0" |
| /* 6067 */ "aesd\t\0" |
| /* 6073 */ "cntd\t\0" |
| /* 6079 */ "revd\t\0" |
| /* 6085 */ "sm4e\t\0" |
| /* 6091 */ "splice\t\0" |
| /* 6099 */ "facge\t\0" |
| /* 6106 */ "whilege\t\0" |
| /* 6115 */ "fcmge\t\0" |
| /* 6122 */ "cmpge\t\0" |
| /* 6129 */ "fscale\t\0" |
| /* 6137 */ "whilele\t\0" |
| /* 6146 */ "fcmle\t\0" |
| /* 6153 */ "cmple\t\0" |
| /* 6160 */ "fcmne\t\0" |
| /* 6167 */ "ctermne\t\0" |
| /* 6176 */ "cmpne\t\0" |
| /* 6183 */ "frecpe\t\0" |
| /* 6191 */ "urecpe\t\0" |
| /* 6199 */ "fccmpe\t\0" |
| /* 6207 */ "fcmpe\t\0" |
| /* 6214 */ "aese\t\0" |
| /* 6220 */ "pfalse\t\0" |
| /* 6228 */ "frsqrte\t\0" |
| /* 6237 */ "ursqrte\t\0" |
| /* 6246 */ "ptrue\t\0" |
| /* 6253 */ "udf\t\0" |
| /* 6258 */ "scvtf\t\0" |
| /* 6265 */ "ucvtf\t\0" |
| /* 6272 */ "st2g\t\0" |
| /* 6278 */ "stz2g\t\0" |
| /* 6285 */ "subg\t\0" |
| /* 6291 */ "addg\t\0" |
| /* 6297 */ "ldg\t\0" |
| /* 6302 */ "fneg\t\0" |
| /* 6308 */ "sqneg\t\0" |
| /* 6315 */ "csneg\t\0" |
| /* 6322 */ "histseg\t\0" |
| /* 6331 */ "irg\t\0" |
| /* 6336 */ "stg\t\0" |
| /* 6341 */ "stzg\t\0" |
| /* 6347 */ "fmla.h\t\0" |
| /* 6355 */ "sqrdmlah.h\t\0" |
| /* 6367 */ "sqdmulh.h\t\0" |
| /* 6378 */ "sqrdmulh.h\t\0" |
| /* 6390 */ "sqrdmlsh.h\t\0" |
| /* 6402 */ "sqdmlal.h\t\0" |
| /* 6413 */ "sqdmull.h\t\0" |
| /* 6424 */ "sqdmlsl.h\t\0" |
| /* 6435 */ "fmul.h\t\0" |
| /* 6443 */ "fmls.h\t\0" |
| /* 6451 */ "ins.h\t\0" |
| /* 6458 */ "smov.h\t\0" |
| /* 6466 */ "umov.h\t\0" |
| /* 6474 */ "fmulx.h\t\0" |
| /* 6483 */ "sha1h\t\0" |
| /* 6490 */ "ld1h\t\0" |
| /* 6496 */ "ldff1h\t\0" |
| /* 6504 */ "ldnf1h\t\0" |
| /* 6512 */ "ldnt1h\t\0" |
| /* 6520 */ "stnt1h\t\0" |
| /* 6528 */ "st1h\t\0" |
| /* 6534 */ "faddp.2h\t\0" |
| /* 6544 */ "fminnmp.2h\t\0" |
| /* 6556 */ "fmaxnmp.2h\t\0" |
| /* 6568 */ "fminp.2h\t\0" |
| /* 6578 */ "fmaxp.2h\t\0" |
| /* 6588 */ "crc32h\t\0" |
| /* 6596 */ "ld2h\t\0" |
| /* 6602 */ "st2h\t\0" |
| /* 6608 */ "ld3h\t\0" |
| /* 6614 */ "st3h\t\0" |
| /* 6620 */ "trn1.4h\t\0" |
| /* 6629 */ "zip1.4h\t\0" |
| /* 6638 */ "uzp1.4h\t\0" |
| /* 6647 */ "rev32.4h\t\0" |
| /* 6657 */ "trn2.4h\t\0" |
| /* 6666 */ "zip2.4h\t\0" |
| /* 6675 */ "uzp2.4h\t\0" |
| /* 6684 */ "rev64.4h\t\0" |
| /* 6694 */ "saba.4h\t\0" |
| /* 6703 */ "uaba.4h\t\0" |
| /* 6712 */ "fcmla.4h\t\0" |
| /* 6722 */ "fmla.4h\t\0" |
| /* 6731 */ "srsra.4h\t\0" |
| /* 6741 */ "ursra.4h\t\0" |
| /* 6751 */ "ssra.4h\t\0" |
| /* 6760 */ "usra.4h\t\0" |
| /* 6769 */ "frinta.4h\t\0" |
| /* 6780 */ "fsub.4h\t\0" |
| /* 6789 */ "shsub.4h\t\0" |
| /* 6799 */ "uhsub.4h\t\0" |
| /* 6809 */ "sqsub.4h\t\0" |
| /* 6819 */ "uqsub.4h\t\0" |
| /* 6829 */ "bic.4h\t\0" |
| /* 6837 */ "fabd.4h\t\0" |
| /* 6846 */ "sabd.4h\t\0" |
| /* 6855 */ "uabd.4h\t\0" |
| /* 6864 */ "fcadd.4h\t\0" |
| /* 6874 */ "fadd.4h\t\0" |
| /* 6883 */ "srhadd.4h\t\0" |
| /* 6894 */ "urhadd.4h\t\0" |
| /* 6905 */ "shadd.4h\t\0" |
| /* 6915 */ "uhadd.4h\t\0" |
| /* 6925 */ "usqadd.4h\t\0" |
| /* 6936 */ "suqadd.4h\t\0" |
| /* 6947 */ "facge.4h\t\0" |
| /* 6957 */ "fcmge.4h\t\0" |
| /* 6967 */ "fcmle.4h\t\0" |
| /* 6977 */ "frecpe.4h\t\0" |
| /* 6988 */ "frsqrte.4h\t\0" |
| /* 7000 */ "scvtf.4h\t\0" |
| /* 7010 */ "ucvtf.4h\t\0" |
| /* 7020 */ "fneg.4h\t\0" |
| /* 7029 */ "sqneg.4h\t\0" |
| /* 7039 */ "sqrdmlah.4h\t\0" |
| /* 7052 */ "sqdmulh.4h\t\0" |
| /* 7064 */ "sqrdmulh.4h\t\0" |
| /* 7077 */ "sqrdmlsh.4h\t\0" |
| /* 7090 */ "cmhi.4h\t\0" |
| /* 7099 */ "sli.4h\t\0" |
| /* 7107 */ "mvni.4h\t\0" |
| /* 7116 */ "sri.4h\t\0" |
| /* 7124 */ "frinti.4h\t\0" |
| /* 7135 */ "movi.4h\t\0" |
| /* 7144 */ "sqshl.4h\t\0" |
| /* 7154 */ "uqshl.4h\t\0" |
| /* 7164 */ "sqrshl.4h\t\0" |
| /* 7175 */ "uqrshl.4h\t\0" |
| /* 7186 */ "srshl.4h\t\0" |
| /* 7196 */ "urshl.4h\t\0" |
| /* 7206 */ "sshl.4h\t\0" |
| /* 7215 */ "ushl.4h\t\0" |
| /* 7224 */ "fmul.4h\t\0" |
| /* 7233 */ "fminnm.4h\t\0" |
| /* 7244 */ "fmaxnm.4h\t\0" |
| /* 7255 */ "frintm.4h\t\0" |
| /* 7266 */ "rsubhn.4h\t\0" |
| /* 7277 */ "raddhn.4h\t\0" |
| /* 7288 */ "fmin.4h\t\0" |
| /* 7297 */ "smin.4h\t\0" |
| /* 7306 */ "umin.4h\t\0" |
| /* 7315 */ "sqshrn.4h\t\0" |
| /* 7326 */ "uqshrn.4h\t\0" |
| /* 7337 */ "sqrshrn.4h\t\0" |
| /* 7349 */ "uqrshrn.4h\t\0" |
| /* 7361 */ "frintn.4h\t\0" |
| /* 7372 */ "bfcvtn.4h\t\0" |
| /* 7383 */ "sqxtn.4h\t\0" |
| /* 7393 */ "uqxtn.4h\t\0" |
| /* 7403 */ "sqshrun.4h\t\0" |
| /* 7415 */ "sqrshrun.4h\t\0" |
| /* 7428 */ "sqxtun.4h\t\0" |
| /* 7439 */ "faddp.4h\t\0" |
| /* 7449 */ "sadalp.4h\t\0" |
| /* 7460 */ "uadalp.4h\t\0" |
| /* 7471 */ "saddlp.4h\t\0" |
| /* 7482 */ "uaddlp.4h\t\0" |
| /* 7493 */ "fminnmp.4h\t\0" |
| /* 7505 */ "fmaxnmp.4h\t\0" |
| /* 7517 */ "fminp.4h\t\0" |
| /* 7527 */ "sminp.4h\t\0" |
| /* 7537 */ "uminp.4h\t\0" |
| /* 7547 */ "frintp.4h\t\0" |
| /* 7558 */ "dup.4h\t\0" |
| /* 7566 */ "fmaxp.4h\t\0" |
| /* 7576 */ "smaxp.4h\t\0" |
| /* 7586 */ "umaxp.4h\t\0" |
| /* 7596 */ "fcmeq.4h\t\0" |
| /* 7606 */ "srshr.4h\t\0" |
| /* 7616 */ "urshr.4h\t\0" |
| /* 7626 */ "sshr.4h\t\0" |
| /* 7635 */ "ushr.4h\t\0" |
| /* 7644 */ "orr.4h\t\0" |
| /* 7652 */ "fcvtas.4h\t\0" |
| /* 7663 */ "fabs.4h\t\0" |
| /* 7672 */ "sqabs.4h\t\0" |
| /* 7682 */ "cmhs.4h\t\0" |
| /* 7691 */ "cls.4h\t\0" |
| /* 7699 */ "fmls.4h\t\0" |
| /* 7708 */ "fcvtms.4h\t\0" |
| /* 7719 */ "fcvtns.4h\t\0" |
| /* 7730 */ "frecps.4h\t\0" |
| /* 7741 */ "fcvtps.4h\t\0" |
| /* 7752 */ "frsqrts.4h\t\0" |
| /* 7764 */ "fcvtzs.4h\t\0" |
| /* 7775 */ "facgt.4h\t\0" |
| /* 7785 */ "fcmgt.4h\t\0" |
| /* 7795 */ "fcmlt.4h\t\0" |
| /* 7805 */ "fsqrt.4h\t\0" |
| /* 7815 */ "cmtst.4h\t\0" |
| /* 7825 */ "fcvtau.4h\t\0" |
| /* 7836 */ "sqshlu.4h\t\0" |
| /* 7847 */ "fcvtmu.4h\t\0" |
| /* 7858 */ "fcvtnu.4h\t\0" |
| /* 7869 */ "fcvtpu.4h\t\0" |
| /* 7880 */ "fcvtzu.4h\t\0" |
| /* 7891 */ "addv.4h\t\0" |
| /* 7900 */ "fdiv.4h\t\0" |
| /* 7909 */ "saddlv.4h\t\0" |
| /* 7920 */ "uaddlv.4h\t\0" |
| /* 7931 */ "fminnmv.4h\t\0" |
| /* 7943 */ "fmaxnmv.4h\t\0" |
| /* 7955 */ "fminv.4h\t\0" |
| /* 7965 */ "sminv.4h\t\0" |
| /* 7975 */ "uminv.4h\t\0" |
| /* 7985 */ "fmov.4h\t\0" |
| /* 7994 */ "fmaxv.4h\t\0" |
| /* 8004 */ "smaxv.4h\t\0" |
| /* 8014 */ "umaxv.4h\t\0" |
| /* 8024 */ "fmax.4h\t\0" |
| /* 8033 */ "smax.4h\t\0" |
| /* 8042 */ "umax.4h\t\0" |
| /* 8051 */ "fmulx.4h\t\0" |
| /* 8061 */ "frintx.4h\t\0" |
| /* 8072 */ "clz.4h\t\0" |
| /* 8080 */ "frintz.4h\t\0" |
| /* 8091 */ "ld4h\t\0" |
| /* 8097 */ "st4h\t\0" |
| /* 8103 */ "trn1.8h\t\0" |
| /* 8112 */ "zip1.8h\t\0" |
| /* 8121 */ "uzp1.8h\t\0" |
| /* 8130 */ "rev32.8h\t\0" |
| /* 8140 */ "sabal2.8h\t\0" |
| /* 8151 */ "uabal2.8h\t\0" |
| /* 8162 */ "smlal2.8h\t\0" |
| /* 8173 */ "umlal2.8h\t\0" |
| /* 8184 */ "ssubl2.8h\t\0" |
| /* 8195 */ "usubl2.8h\t\0" |
| /* 8206 */ "sabdl2.8h\t\0" |
| /* 8217 */ "uabdl2.8h\t\0" |
| /* 8228 */ "saddl2.8h\t\0" |
| /* 8239 */ "uaddl2.8h\t\0" |
| /* 8250 */ "sshll2.8h\t\0" |
| /* 8261 */ "ushll2.8h\t\0" |
| /* 8272 */ "pmull2.8h\t\0" |
| /* 8283 */ "smull2.8h\t\0" |
| /* 8294 */ "umull2.8h\t\0" |
| /* 8305 */ "smlsl2.8h\t\0" |
| /* 8316 */ "umlsl2.8h\t\0" |
| /* 8327 */ "rsubhn2.8h\t\0" |
| /* 8339 */ "raddhn2.8h\t\0" |
| /* 8351 */ "sqshrn2.8h\t\0" |
| /* 8363 */ "uqshrn2.8h\t\0" |
| /* 8375 */ "sqrshrn2.8h\t\0" |
| /* 8388 */ "uqrshrn2.8h\t\0" |
| /* 8401 */ "trn2.8h\t\0" |
| /* 8410 */ "bfcvtn2.8h\t\0" |
| /* 8422 */ "sqxtn2.8h\t\0" |
| /* 8433 */ "uqxtn2.8h\t\0" |
| /* 8444 */ "sqshrun2.8h\t\0" |
| /* 8457 */ "sqrshrun2.8h\t\0" |
| /* 8471 */ "sqxtun2.8h\t\0" |
| /* 8483 */ "zip2.8h\t\0" |
| /* 8492 */ "uzp2.8h\t\0" |
| /* 8501 */ "ssubw2.8h\t\0" |
| /* 8512 */ "usubw2.8h\t\0" |
| /* 8523 */ "saddw2.8h\t\0" |
| /* 8534 */ "uaddw2.8h\t\0" |
| /* 8545 */ "rev64.8h\t\0" |
| /* 8555 */ "saba.8h\t\0" |
| /* 8564 */ "uaba.8h\t\0" |
| /* 8573 */ "fcmla.8h\t\0" |
| /* 8583 */ "fmla.8h\t\0" |
| /* 8592 */ "srsra.8h\t\0" |
| /* 8602 */ "ursra.8h\t\0" |
| /* 8612 */ "ssra.8h\t\0" |
| /* 8621 */ "usra.8h\t\0" |
| /* 8630 */ "frinta.8h\t\0" |
| /* 8641 */ "fsub.8h\t\0" |
| /* 8650 */ "shsub.8h\t\0" |
| /* 8660 */ "uhsub.8h\t\0" |
| /* 8670 */ "sqsub.8h\t\0" |
| /* 8680 */ "uqsub.8h\t\0" |
| /* 8690 */ "bic.8h\t\0" |
| /* 8698 */ "fabd.8h\t\0" |
| /* 8707 */ "sabd.8h\t\0" |
| /* 8716 */ "uabd.8h\t\0" |
| /* 8725 */ "fcadd.8h\t\0" |
| /* 8735 */ "fadd.8h\t\0" |
| /* 8744 */ "srhadd.8h\t\0" |
| /* 8755 */ "urhadd.8h\t\0" |
| /* 8766 */ "shadd.8h\t\0" |
| /* 8776 */ "uhadd.8h\t\0" |
| /* 8786 */ "usqadd.8h\t\0" |
| /* 8797 */ "suqadd.8h\t\0" |
| /* 8808 */ "facge.8h\t\0" |
| /* 8818 */ "fcmge.8h\t\0" |
| /* 8828 */ "fcmle.8h\t\0" |
| /* 8838 */ "frecpe.8h\t\0" |
| /* 8849 */ "frsqrte.8h\t\0" |
| /* 8861 */ "scvtf.8h\t\0" |
| /* 8871 */ "ucvtf.8h\t\0" |
| /* 8881 */ "fneg.8h\t\0" |
| /* 8890 */ "sqneg.8h\t\0" |
| /* 8900 */ "sqrdmlah.8h\t\0" |
| /* 8913 */ "sqdmulh.8h\t\0" |
| /* 8925 */ "sqrdmulh.8h\t\0" |
| /* 8938 */ "sqrdmlsh.8h\t\0" |
| /* 8951 */ "cmhi.8h\t\0" |
| /* 8960 */ "sli.8h\t\0" |
| /* 8968 */ "mvni.8h\t\0" |
| /* 8977 */ "sri.8h\t\0" |
| /* 8985 */ "frinti.8h\t\0" |
| /* 8996 */ "movi.8h\t\0" |
| /* 9005 */ "sabal.8h\t\0" |
| /* 9015 */ "uabal.8h\t\0" |
| /* 9025 */ "smlal.8h\t\0" |
| /* 9035 */ "umlal.8h\t\0" |
| /* 9045 */ "ssubl.8h\t\0" |
| /* 9055 */ "usubl.8h\t\0" |
| /* 9065 */ "sabdl.8h\t\0" |
| /* 9075 */ "uabdl.8h\t\0" |
| /* 9085 */ "saddl.8h\t\0" |
| /* 9095 */ "uaddl.8h\t\0" |
| /* 9105 */ "sqshl.8h\t\0" |
| /* 9115 */ "uqshl.8h\t\0" |
| /* 9125 */ "sqrshl.8h\t\0" |
| /* 9136 */ "uqrshl.8h\t\0" |
| /* 9147 */ "srshl.8h\t\0" |
| /* 9157 */ "urshl.8h\t\0" |
| /* 9167 */ "sshl.8h\t\0" |
| /* 9176 */ "ushl.8h\t\0" |
| /* 9185 */ "sshll.8h\t\0" |
| /* 9195 */ "ushll.8h\t\0" |
| /* 9205 */ "pmull.8h\t\0" |
| /* 9215 */ "smull.8h\t\0" |
| /* 9225 */ "umull.8h\t\0" |
| /* 9235 */ "smlsl.8h\t\0" |
| /* 9245 */ "umlsl.8h\t\0" |
| /* 9255 */ "fmul.8h\t\0" |
| /* 9264 */ "fminnm.8h\t\0" |
| /* 9275 */ "fmaxnm.8h\t\0" |
| /* 9286 */ "frintm.8h\t\0" |
| /* 9297 */ "fmin.8h\t\0" |
| /* 9306 */ "smin.8h\t\0" |
| /* 9315 */ "umin.8h\t\0" |
| /* 9324 */ "frintn.8h\t\0" |
| /* 9335 */ "faddp.8h\t\0" |
| /* 9345 */ "sadalp.8h\t\0" |
| /* 9356 */ "uadalp.8h\t\0" |
| /* 9367 */ "saddlp.8h\t\0" |
| /* 9378 */ "uaddlp.8h\t\0" |
| /* 9389 */ "fminnmp.8h\t\0" |
| /* 9401 */ "fmaxnmp.8h\t\0" |
| /* 9413 */ "fminp.8h\t\0" |
| /* 9423 */ "sminp.8h\t\0" |
| /* 9433 */ "uminp.8h\t\0" |
| /* 9443 */ "frintp.8h\t\0" |
| /* 9454 */ "dup.8h\t\0" |
| /* 9462 */ "fmaxp.8h\t\0" |
| /* 9472 */ "smaxp.8h\t\0" |
| /* 9482 */ "umaxp.8h\t\0" |
| /* 9492 */ "fcmeq.8h\t\0" |
| /* 9502 */ "srshr.8h\t\0" |
| /* 9512 */ "urshr.8h\t\0" |
| /* 9522 */ "sshr.8h\t\0" |
| /* 9531 */ "ushr.8h\t\0" |
| /* 9540 */ "orr.8h\t\0" |
| /* 9548 */ "fcvtas.8h\t\0" |
| /* 9559 */ "fabs.8h\t\0" |
| /* 9568 */ "sqabs.8h\t\0" |
| /* 9578 */ "cmhs.8h\t\0" |
| /* 9587 */ "cls.8h\t\0" |
| /* 9595 */ "fmls.8h\t\0" |
| /* 9604 */ "fcvtms.8h\t\0" |
| /* 9615 */ "fcvtns.8h\t\0" |
| /* 9626 */ "frecps.8h\t\0" |
| /* 9637 */ "fcvtps.8h\t\0" |
| /* 9648 */ "frsqrts.8h\t\0" |
| /* 9660 */ "fcvtzs.8h\t\0" |
| /* 9671 */ "facgt.8h\t\0" |
| /* 9681 */ "fcmgt.8h\t\0" |
| /* 9691 */ "fcmlt.8h\t\0" |
| /* 9701 */ "fsqrt.8h\t\0" |
| /* 9711 */ "cmtst.8h\t\0" |
| /* 9721 */ "fcvtau.8h\t\0" |
| /* 9732 */ "sqshlu.8h\t\0" |
| /* 9743 */ "fcvtmu.8h\t\0" |
| /* 9754 */ "fcvtnu.8h\t\0" |
| /* 9765 */ "fcvtpu.8h\t\0" |
| /* 9776 */ "fcvtzu.8h\t\0" |
| /* 9787 */ "addv.8h\t\0" |
| /* 9796 */ "fdiv.8h\t\0" |
| /* 9805 */ "saddlv.8h\t\0" |
| /* 9816 */ "uaddlv.8h\t\0" |
| /* 9827 */ "fminnmv.8h\t\0" |
| /* 9839 */ "fmaxnmv.8h\t\0" |
| /* 9851 */ "fminv.8h\t\0" |
| /* 9861 */ "sminv.8h\t\0" |
| /* 9871 */ "uminv.8h\t\0" |
| /* 9881 */ "fmov.8h\t\0" |
| /* 9890 */ "fmaxv.8h\t\0" |
| /* 9900 */ "smaxv.8h\t\0" |
| /* 9910 */ "umaxv.8h\t\0" |
| /* 9920 */ "ssubw.8h\t\0" |
| /* 9930 */ "usubw.8h\t\0" |
| /* 9940 */ "saddw.8h\t\0" |
| /* 9950 */ "uaddw.8h\t\0" |
| /* 9960 */ "fmax.8h\t\0" |
| /* 9969 */ "smax.8h\t\0" |
| /* 9978 */ "umax.8h\t\0" |
| /* 9987 */ "fmulx.8h\t\0" |
| /* 9997 */ "frintx.8h\t\0" |
| /* 10008 */ "clz.8h\t\0" |
| /* 10016 */ "frintz.8h\t\0" |
| /* 10027 */ "ldaddah\t\0" |
| /* 10036 */ "sqrdcmlah\t\0" |
| /* 10047 */ "sqrdmlah\t\0" |
| /* 10057 */ "ldsminah\t\0" |
| /* 10067 */ "lduminah\t\0" |
| /* 10077 */ "swpah\t\0" |
| /* 10084 */ "ldclrah\t\0" |
| /* 10093 */ "ldeorah\t\0" |
| /* 10102 */ "casah\t\0" |
| /* 10109 */ "ldsetah\t\0" |
| /* 10118 */ "ldsmaxah\t\0" |
| /* 10128 */ "ldumaxah\t\0" |
| /* 10138 */ "crc32ch\t\0" |
| /* 10147 */ "sqdech\t\0" |
| /* 10155 */ "uqdech\t\0" |
| /* 10163 */ "sqinch\t\0" |
| /* 10171 */ "uqinch\t\0" |
| /* 10179 */ "nmatch\t\0" |
| /* 10187 */ "ldaddh\t\0" |
| /* 10195 */ "prfh\t\0" |
| /* 10201 */ "ldaddalh\t\0" |
| /* 10211 */ "ldsminalh\t\0" |
| /* 10222 */ "lduminalh\t\0" |
| /* 10233 */ "swpalh\t\0" |
| /* 10241 */ "ldclralh\t\0" |
| /* 10251 */ "ldeoralh\t\0" |
| /* 10261 */ "casalh\t\0" |
| /* 10269 */ "ldsetalh\t\0" |
| /* 10279 */ "ldsmaxalh\t\0" |
| /* 10290 */ "ldumaxalh\t\0" |
| /* 10301 */ "ldaddlh\t\0" |
| /* 10310 */ "ldsminlh\t\0" |
| /* 10320 */ "lduminlh\t\0" |
| /* 10330 */ "swplh\t\0" |
| /* 10337 */ "ldclrlh\t\0" |
| /* 10346 */ "ldeorlh\t\0" |
| /* 10355 */ "caslh\t\0" |
| /* 10362 */ "ldsetlh\t\0" |
| /* 10371 */ "sqdmulh\t\0" |
| /* 10380 */ "sqrdmulh\t\0" |
| /* 10390 */ "smulh\t\0" |
| /* 10397 */ "umulh\t\0" |
| /* 10404 */ "ldsmaxlh\t\0" |
| /* 10414 */ "ldumaxlh\t\0" |
| /* 10424 */ "ldsminh\t\0" |
| /* 10433 */ "lduminh\t\0" |
| /* 10442 */ "ld1roh\t\0" |
| /* 10450 */ "swph\t\0" |
| /* 10456 */ "ld1rqh\t\0" |
| /* 10464 */ "ld1rh\t\0" |
| /* 10471 */ "ldarh\t\0" |
| /* 10478 */ "ldlarh\t\0" |
| /* 10486 */ "ldrh\t\0" |
| /* 10492 */ "ldclrh\t\0" |
| /* 10500 */ "stllrh\t\0" |
| /* 10508 */ "stlrh\t\0" |
| /* 10515 */ "ldeorh\t\0" |
| /* 10523 */ "ldaprh\t\0" |
| /* 10531 */ "ldtrh\t\0" |
| /* 10538 */ "strh\t\0" |
| /* 10544 */ "sttrh\t\0" |
| /* 10551 */ "ldurh\t\0" |
| /* 10558 */ "stlurh\t\0" |
| /* 10566 */ "ldapurh\t\0" |
| /* 10575 */ "sturh\t\0" |
| /* 10582 */ "ldaxrh\t\0" |
| /* 10590 */ "ldxrh\t\0" |
| /* 10597 */ "stlxrh\t\0" |
| /* 10605 */ "stxrh\t\0" |
| /* 10612 */ "ld1sh\t\0" |
| /* 10619 */ "ldff1sh\t\0" |
| /* 10628 */ "ldnf1sh\t\0" |
| /* 10637 */ "ldnt1sh\t\0" |
| /* 10646 */ "cash\t\0" |
| /* 10652 */ "sqrdmlsh\t\0" |
| /* 10662 */ "ld1rsh\t\0" |
| /* 10670 */ "ldrsh\t\0" |
| /* 10677 */ "ldtrsh\t\0" |
| /* 10685 */ "ldursh\t\0" |
| /* 10693 */ "ldapursh\t\0" |
| /* 10703 */ "ldseth\t\0" |
| /* 10711 */ "cnth\t\0" |
| /* 10717 */ "sxth\t\0" |
| /* 10723 */ "uxth\t\0" |
| /* 10729 */ "revh\t\0" |
| /* 10735 */ "ldsmaxh\t\0" |
| /* 10744 */ "ldumaxh\t\0" |
| /* 10753 */ "xpaci\t\0" |
| /* 10760 */ "whilehi\t\0" |
| /* 10769 */ "punpkhi\t\0" |
| /* 10778 */ "sunpkhi\t\0" |
| /* 10787 */ "uunpkhi\t\0" |
| /* 10796 */ "cmhi\t\0" |
| /* 10802 */ "cmphi\t\0" |
| /* 10809 */ "sli\t\0" |
| /* 10814 */ "gmi\t\0" |
| /* 10819 */ "sri\t\0" |
| /* 10824 */ "frinti\t\0" |
| /* 10832 */ "movi\t\0" |
| /* 10838 */ "sunpk\t\0" |
| /* 10845 */ "uunpk\t\0" |
| /* 10852 */ "brk\t\0" |
| /* 10857 */ "movk\t\0" |
| /* 10863 */ "ldaddal\t\0" |
| /* 10872 */ "sqdmlal\t\0" |
| /* 10881 */ "bfmlal\t\0" |
| /* 10889 */ "smlal\t\0" |
| /* 10896 */ "umlal\t\0" |
| /* 10903 */ "ldsminal\t\0" |
| /* 10913 */ "lduminal\t\0" |
| /* 10923 */ "rcwsswppal\t\0" |
| /* 10935 */ "rcwswppal\t\0" |
| /* 10946 */ "ldclrpal\t\0" |
| /* 10956 */ "rcwsclrpal\t\0" |
| /* 10968 */ "rcwclrpal\t\0" |
| /* 10979 */ "rcwscaspal\t\0" |
| /* 10991 */ "rcwcaspal\t\0" |
| /* 11002 */ "ldsetpal\t\0" |
| /* 11012 */ "rcwssetpal\t\0" |
| /* 11024 */ "rcwsetpal\t\0" |
| /* 11035 */ "rcwsswpal\t\0" |
| /* 11046 */ "rcwswpal\t\0" |
| /* 11056 */ "ldclral\t\0" |
| /* 11065 */ "rcwsclral\t\0" |
| /* 11076 */ "rcwclral\t\0" |
| /* 11086 */ "ldeoral\t\0" |
| /* 11095 */ "rcwscasal\t\0" |
| /* 11106 */ "rcwcasal\t\0" |
| /* 11116 */ "ldsetal\t\0" |
| /* 11125 */ "rcwssetal\t\0" |
| /* 11136 */ "rcwsetal\t\0" |
| /* 11146 */ "ldsmaxal\t\0" |
| /* 11156 */ "ldumaxal\t\0" |
| /* 11166 */ "tbl\t\0" |
| /* 11171 */ "smsubl\t\0" |
| /* 11179 */ "umsubl\t\0" |
| /* 11187 */ "ldaddl\t\0" |
| /* 11195 */ "smaddl\t\0" |
| /* 11203 */ "umaddl\t\0" |
| /* 11211 */ "tcancel\t\0" |
| /* 11220 */ "fcsel\t\0" |
| /* 11227 */ "psel\t\0" |
| /* 11233 */ "ftssel\t\0" |
| /* 11241 */ "sqshl\t\0" |
| /* 11248 */ "uqshl\t\0" |
| /* 11255 */ "sqrshl\t\0" |
| /* 11263 */ "uqrshl\t\0" |
| /* 11271 */ "srshl\t\0" |
| /* 11278 */ "urshl\t\0" |
| /* 11285 */ "sshl\t\0" |
| /* 11291 */ "ushl\t\0" |
| /* 11297 */ "usmlall\t\0" |
| /* 11306 */ "sumlall\t\0" |
| /* 11315 */ "smlsll\t\0" |
| /* 11323 */ "umlsll\t\0" |
| /* 11331 */ "sqdmull\t\0" |
| /* 11340 */ "ldsminl\t\0" |
| /* 11349 */ "lduminl\t\0" |
| /* 11358 */ "addpl\t\0" |
| /* 11365 */ "rcwsswppl\t\0" |
| /* 11376 */ "rcwswppl\t\0" |
| /* 11386 */ "ldclrpl\t\0" |
| /* 11395 */ "rcwsclrpl\t\0" |
| /* 11406 */ "rcwclrpl\t\0" |
| /* 11416 */ "rcwscaspl\t\0" |
| /* 11427 */ "rcwcaspl\t\0" |
| /* 11437 */ "addspl\t\0" |
| /* 11445 */ "ldsetpl\t\0" |
| /* 11454 */ "rcwssetpl\t\0" |
| /* 11465 */ "rcwsetpl\t\0" |
| /* 11475 */ "rcwsswpl\t\0" |
| /* 11485 */ "rcwswpl\t\0" |
| /* 11494 */ "ldclrl\t\0" |
| /* 11502 */ "rcwsclrl\t\0" |
| /* 11512 */ "rcwclrl\t\0" |
| /* 11521 */ "ldeorl\t\0" |
| /* 11529 */ "rcwscasl\t\0" |
| /* 11539 */ "rcwcasl\t\0" |
| /* 11548 */ "nbsl\t\0" |
| /* 11554 */ "sqdmlsl\t\0" |
| /* 11563 */ "bfmlsl\t\0" |
| /* 11571 */ "smlsl\t\0" |
| /* 11578 */ "umlsl\t\0" |
| /* 11585 */ "sysl\t\0" |
| /* 11591 */ "ldsetl\t\0" |
| /* 11599 */ "rcwssetl\t\0" |
| /* 11609 */ "rcwsetl\t\0" |
| /* 11618 */ "fcvtl\t\0" |
| /* 11625 */ "bfmul\t\0" |
| /* 11632 */ "fnmul\t\0" |
| /* 11639 */ "pmul\t\0" |
| /* 11645 */ "ftsmul\t\0" |
| /* 11653 */ "addvl\t\0" |
| /* 11660 */ "rdvl\t\0" |
| /* 11666 */ "addsvl\t\0" |
| /* 11674 */ "rdsvl\t\0" |
| /* 11681 */ "ldsmaxl\t\0" |
| /* 11690 */ "ldumaxl\t\0" |
| /* 11699 */ "sbfm\t\0" |
| /* 11705 */ "ubfm\t\0" |
| /* 11711 */ "rprfm\t\0" |
| /* 11718 */ "ldgm\t\0" |
| /* 11724 */ "stgm\t\0" |
| /* 11730 */ "stzgm\t\0" |
| /* 11737 */ "bfminnm\t\0" |
| /* 11746 */ "bfmaxnm\t\0" |
| /* 11755 */ "dupm\t\0" |
| /* 11761 */ "frintm\t\0" |
| /* 11769 */ "prfum\t\0" |
| /* 11776 */ "bsl1n\t\0" |
| /* 11783 */ "bsl2n\t\0" |
| /* 11790 */ "bfmin\t\0" |
| /* 11797 */ "ldsmin\t\0" |
| /* 11805 */ "ldumin\t\0" |
| /* 11813 */ "brkn\t\0" |
| /* 11819 */ "ccmn\t\0" |
| /* 11825 */ "eon\t\0" |
| /* 11830 */ "sqshrn\t\0" |
| /* 11838 */ "uqshrn\t\0" |
| /* 11846 */ "sqrshrn\t\0" |
| /* 11855 */ "uqrshrn\t\0" |
| /* 11864 */ "orn\t\0" |
| /* 11869 */ "frintn\t\0" |
| /* 11877 */ "bfcvtn\t\0" |
| /* 11885 */ "sqcvtn\t\0" |
| /* 11893 */ "uqcvtn\t\0" |
| /* 11901 */ "sqxtn\t\0" |
| /* 11908 */ "uqxtn\t\0" |
| /* 11915 */ "sqshrun\t\0" |
| /* 11924 */ "sqrshrun\t\0" |
| /* 11934 */ "sqcvtun\t\0" |
| /* 11943 */ "sqxtun\t\0" |
| /* 11951 */ "movn\t\0" |
| /* 11957 */ "fcvtxn\t\0" |
| /* 11965 */ "whilelo\t\0" |
| /* 11974 */ "punpklo\t\0" |
| /* 11983 */ "sunpklo\t\0" |
| /* 11992 */ "uunpklo\t\0" |
| /* 12001 */ "cmplo\t\0" |
| /* 12008 */ "zero\t\0" |
| /* 12014 */ "fcmuo\t\0" |
| /* 12021 */ "subp\t\0" |
| /* 12027 */ "sqdecp\t\0" |
| /* 12035 */ "uqdecp\t\0" |
| /* 12043 */ "sqincp\t\0" |
| /* 12051 */ "uqincp\t\0" |
| /* 12059 */ "faddp\t\0" |
| /* 12066 */ "ldp\t\0" |
| /* 12071 */ "bdep\t\0" |
| /* 12077 */ "stgp\t\0" |
| /* 12083 */ "zip\t\0" |
| /* 12088 */ "sadalp\t\0" |
| /* 12096 */ "uadalp\t\0" |
| /* 12104 */ "stilp\t\0" |
| /* 12111 */ "bfclamp\t\0" |
| /* 12120 */ "sclamp\t\0" |
| /* 12128 */ "uclamp\t\0" |
| /* 12136 */ "fccmp\t\0" |
| /* 12143 */ "fcmp\t\0" |
| /* 12149 */ "fminnmp\t\0" |
| /* 12158 */ "fmaxnmp\t\0" |
| /* 12167 */ "ldnp\t\0" |
| /* 12173 */ "fminp\t\0" |
| /* 12180 */ "sminp\t\0" |
| /* 12187 */ "uminp\t\0" |
| /* 12194 */ "stnp\t\0" |
| /* 12200 */ "ldiapp\t\0" |
| /* 12208 */ "rcwsswpp\t\0" |
| /* 12218 */ "rcwswpp\t\0" |
| /* 12227 */ "adrp\t\0" |
| /* 12233 */ "bgrp\t\0" |
| /* 12239 */ "ldclrp\t\0" |
| /* 12247 */ "rcwsclrp\t\0" |
| /* 12257 */ "rcwclrp\t\0" |
| /* 12266 */ "rcwscasp\t\0" |
| /* 12276 */ "rcwcasp\t\0" |
| /* 12285 */ "sysp\t\0" |
| /* 12291 */ "ldsetp\t\0" |
| /* 12299 */ "rcwssetp\t\0" |
| /* 12309 */ "rcwsetp\t\0" |
| /* 12318 */ "cntp\t\0" |
| /* 12324 */ "frintp\t\0" |
| /* 12332 */ "stp\t\0" |
| /* 12337 */ "fdup\t\0" |
| /* 12343 */ "rcwsswp\t\0" |
| /* 12352 */ "rcwswp\t\0" |
| /* 12360 */ "ldaxp\t\0" |
| /* 12367 */ "fmaxp\t\0" |
| /* 12374 */ "smaxp\t\0" |
| /* 12381 */ "umaxp\t\0" |
| /* 12388 */ "ldxp\t\0" |
| /* 12394 */ "stlxp\t\0" |
| /* 12401 */ "stxp\t\0" |
| /* 12407 */ "uzp\t\0" |
| /* 12412 */ "pmull2.1q\t\0" |
| /* 12423 */ "pmull.1q\t\0" |
| /* 12433 */ "ld1q\t\0" |
| /* 12439 */ "st1q\t\0" |
| /* 12445 */ "ld2q\t\0" |
| /* 12451 */ "st2q\t\0" |
| /* 12457 */ "ld3q\t\0" |
| /* 12463 */ "st3q\t\0" |
| /* 12469 */ "ld4q\t\0" |
| /* 12475 */ "st4q\t\0" |
| /* 12481 */ "fcmeq\t\0" |
| /* 12488 */ "ctermeq\t\0" |
| /* 12497 */ "cmpeq\t\0" |
| /* 12504 */ "tblq\t\0" |
| /* 12510 */ "dupq\t\0" |
| /* 12516 */ "extq\t\0" |
| /* 12522 */ "tbxq\t\0" |
| /* 12528 */ "ld1r\t\0" |
| /* 12534 */ "ld2r\t\0" |
| /* 12540 */ "ld3r\t\0" |
| /* 12546 */ "ld4r\t\0" |
| /* 12552 */ "ldar\t\0" |
| /* 12558 */ "ldlar\t\0" |
| /* 12565 */ "xar\t\0" |
| /* 12570 */ "fsubr\t\0" |
| /* 12577 */ "shsubr\t\0" |
| /* 12585 */ "uhsubr\t\0" |
| /* 12593 */ "sqsubr\t\0" |
| /* 12601 */ "uqsubr\t\0" |
| /* 12609 */ "adr\t\0" |
| /* 12614 */ "ldr\t\0" |
| /* 12619 */ "rdffr\t\0" |
| /* 12626 */ "wrffr\t\0" |
| /* 12633 */ "sqrshr\t\0" |
| /* 12641 */ "uqrshr\t\0" |
| /* 12649 */ "srshr\t\0" |
| /* 12656 */ "urshr\t\0" |
| /* 12663 */ "sshr\t\0" |
| /* 12669 */ "ushr\t\0" |
| /* 12675 */ "blr\t\0" |
| /* 12680 */ "ldclr\t\0" |
| /* 12687 */ "rcwsclr\t\0" |
| /* 12696 */ "rcwclr\t\0" |
| /* 12704 */ "sqshlr\t\0" |
| /* 12712 */ "uqshlr\t\0" |
| /* 12720 */ "sqrshlr\t\0" |
| /* 12729 */ "uqrshlr\t\0" |
| /* 12738 */ "srshlr\t\0" |
| /* 12746 */ "urshlr\t\0" |
| /* 12754 */ "stllr\t\0" |
| /* 12761 */ "lslr\t\0" |
| /* 12767 */ "stlr\t\0" |
| /* 12773 */ "ldeor\t\0" |
| /* 12780 */ "nor\t\0" |
| /* 12785 */ "ror\t\0" |
| /* 12790 */ "ldapr\t\0" |
| /* 12797 */ "orr\t\0" |
| /* 12802 */ "asrr\t\0" |
| /* 12808 */ "lsrr\t\0" |
| /* 12814 */ "msrr\t\0" |
| /* 12820 */ "asr\t\0" |
| /* 12825 */ "lsr\t\0" |
| /* 12830 */ "msr\t\0" |
| /* 12835 */ "insr\t\0" |
| /* 12841 */ "ldtr\t\0" |
| /* 12847 */ "str\t\0" |
| /* 12852 */ "sttr\t\0" |
| /* 12858 */ "extr\t\0" |
| /* 12864 */ "ldur\t\0" |
| /* 12870 */ "stlur\t\0" |
| /* 12877 */ "ldapur\t\0" |
| /* 12885 */ "stur\t\0" |
| /* 12891 */ "fdivr\t\0" |
| /* 12898 */ "sdivr\t\0" |
| /* 12905 */ "udivr\t\0" |
| /* 12912 */ "whilewr\t\0" |
| /* 12921 */ "ldaxr\t\0" |
| /* 12928 */ "ldxr\t\0" |
| /* 12934 */ "stlxr\t\0" |
| /* 12941 */ "stxr\t\0" |
| /* 12947 */ "fmla.s\t\0" |
| /* 12955 */ "sqrdmlah.s\t\0" |
| /* 12967 */ "sqdmulh.s\t\0" |
| /* 12978 */ "sqrdmulh.s\t\0" |
| /* 12990 */ "sqrdmlsh.s\t\0" |
| /* 13002 */ "sqdmlal.s\t\0" |
| /* 13013 */ "sqdmull.s\t\0" |
| /* 13024 */ "sqdmlsl.s\t\0" |
| /* 13035 */ "fmul.s\t\0" |
| /* 13043 */ "fmls.s\t\0" |
| /* 13051 */ "ins.s\t\0" |
| /* 13058 */ "smov.s\t\0" |
| /* 13066 */ "umov.s\t\0" |
| /* 13074 */ "fmulx.s\t\0" |
| /* 13083 */ "trn1.2s\t\0" |
| /* 13092 */ "zip1.2s\t\0" |
| /* 13101 */ "uzp1.2s\t\0" |
| /* 13110 */ "trn2.2s\t\0" |
| /* 13119 */ "zip2.2s\t\0" |
| /* 13128 */ "uzp2.2s\t\0" |
| /* 13137 */ "rev64.2s\t\0" |
| /* 13147 */ "saba.2s\t\0" |
| /* 13156 */ "uaba.2s\t\0" |
| /* 13165 */ "fcmla.2s\t\0" |
| /* 13175 */ "fmla.2s\t\0" |
| /* 13184 */ "srsra.2s\t\0" |
| /* 13194 */ "ursra.2s\t\0" |
| /* 13204 */ "ssra.2s\t\0" |
| /* 13213 */ "usra.2s\t\0" |
| /* 13222 */ "frinta.2s\t\0" |
| /* 13233 */ "fsub.2s\t\0" |
| /* 13242 */ "shsub.2s\t\0" |
| /* 13252 */ "uhsub.2s\t\0" |
| /* 13262 */ "sqsub.2s\t\0" |
| /* 13272 */ "uqsub.2s\t\0" |
| /* 13282 */ "bic.2s\t\0" |
| /* 13290 */ "fabd.2s\t\0" |
| /* 13299 */ "sabd.2s\t\0" |
| /* 13308 */ "uabd.2s\t\0" |
| /* 13317 */ "fcadd.2s\t\0" |
| /* 13327 */ "fadd.2s\t\0" |
| /* 13336 */ "srhadd.2s\t\0" |
| /* 13347 */ "urhadd.2s\t\0" |
| /* 13358 */ "shadd.2s\t\0" |
| /* 13368 */ "uhadd.2s\t\0" |
| /* 13378 */ "usqadd.2s\t\0" |
| /* 13389 */ "suqadd.2s\t\0" |
| /* 13400 */ "facge.2s\t\0" |
| /* 13410 */ "fcmge.2s\t\0" |
| /* 13420 */ "fcmle.2s\t\0" |
| /* 13430 */ "frecpe.2s\t\0" |
| /* 13441 */ "urecpe.2s\t\0" |
| /* 13452 */ "frsqrte.2s\t\0" |
| /* 13464 */ "ursqrte.2s\t\0" |
| /* 13476 */ "scvtf.2s\t\0" |
| /* 13486 */ "ucvtf.2s\t\0" |
| /* 13496 */ "fneg.2s\t\0" |
| /* 13505 */ "sqneg.2s\t\0" |
| /* 13515 */ "sqrdmlah.2s\t\0" |
| /* 13528 */ "sqdmulh.2s\t\0" |
| /* 13540 */ "sqrdmulh.2s\t\0" |
| /* 13553 */ "sqrdmlsh.2s\t\0" |
| /* 13566 */ "cmhi.2s\t\0" |
| /* 13575 */ "sli.2s\t\0" |
| /* 13583 */ "mvni.2s\t\0" |
| /* 13592 */ "sri.2s\t\0" |
| /* 13600 */ "frinti.2s\t\0" |
| /* 13611 */ "movi.2s\t\0" |
| /* 13620 */ "sqshl.2s\t\0" |
| /* 13630 */ "uqshl.2s\t\0" |
| /* 13640 */ "sqrshl.2s\t\0" |
| /* 13651 */ "uqrshl.2s\t\0" |
| /* 13662 */ "srshl.2s\t\0" |
| /* 13672 */ "urshl.2s\t\0" |
| /* 13682 */ "sshl.2s\t\0" |
| /* 13691 */ "ushl.2s\t\0" |
| /* 13700 */ "fmul.2s\t\0" |
| /* 13709 */ "fminnm.2s\t\0" |
| /* 13720 */ "fmaxnm.2s\t\0" |
| /* 13731 */ "frintm.2s\t\0" |
| /* 13742 */ "rsubhn.2s\t\0" |
| /* 13753 */ "raddhn.2s\t\0" |
| /* 13764 */ "fmin.2s\t\0" |
| /* 13773 */ "smin.2s\t\0" |
| /* 13782 */ "umin.2s\t\0" |
| /* 13791 */ "sqshrn.2s\t\0" |
| /* 13802 */ "uqshrn.2s\t\0" |
| /* 13813 */ "sqrshrn.2s\t\0" |
| /* 13825 */ "uqrshrn.2s\t\0" |
| /* 13837 */ "frintn.2s\t\0" |
| /* 13848 */ "sqxtn.2s\t\0" |
| /* 13858 */ "uqxtn.2s\t\0" |
| /* 13868 */ "sqshrun.2s\t\0" |
| /* 13880 */ "sqrshrun.2s\t\0" |
| /* 13893 */ "sqxtun.2s\t\0" |
| /* 13904 */ "faddp.2s\t\0" |
| /* 13914 */ "sadalp.2s\t\0" |
| /* 13925 */ "uadalp.2s\t\0" |
| /* 13936 */ "saddlp.2s\t\0" |
| /* 13947 */ "uaddlp.2s\t\0" |
| /* 13958 */ "fminnmp.2s\t\0" |
| /* 13970 */ "fmaxnmp.2s\t\0" |
| /* 13982 */ "fminp.2s\t\0" |
| /* 13992 */ "sminp.2s\t\0" |
| /* 14002 */ "uminp.2s\t\0" |
| /* 14012 */ "frintp.2s\t\0" |
| /* 14023 */ "dup.2s\t\0" |
| /* 14031 */ "fmaxp.2s\t\0" |
| /* 14041 */ "smaxp.2s\t\0" |
| /* 14051 */ "umaxp.2s\t\0" |
| /* 14061 */ "fcmeq.2s\t\0" |
| /* 14071 */ "srshr.2s\t\0" |
| /* 14081 */ "urshr.2s\t\0" |
| /* 14091 */ "sshr.2s\t\0" |
| /* 14100 */ "ushr.2s\t\0" |
| /* 14109 */ "orr.2s\t\0" |
| /* 14117 */ "fcvtas.2s\t\0" |
| /* 14128 */ "fabs.2s\t\0" |
| /* 14137 */ "sqabs.2s\t\0" |
| /* 14147 */ "cmhs.2s\t\0" |
| /* 14156 */ "cls.2s\t\0" |
| /* 14164 */ "fmls.2s\t\0" |
| /* 14173 */ "fcvtms.2s\t\0" |
| /* 14184 */ "fcvtns.2s\t\0" |
| /* 14195 */ "frecps.2s\t\0" |
| /* 14206 */ "fcvtps.2s\t\0" |
| /* 14217 */ "frsqrts.2s\t\0" |
| /* 14229 */ "fcvtzs.2s\t\0" |
| /* 14240 */ "facgt.2s\t\0" |
| /* 14250 */ "fcmgt.2s\t\0" |
| /* 14260 */ "fcmlt.2s\t\0" |
| /* 14270 */ "fsqrt.2s\t\0" |
| /* 14280 */ "cmtst.2s\t\0" |
| /* 14290 */ "fcvtau.2s\t\0" |
| /* 14301 */ "sqshlu.2s\t\0" |
| /* 14312 */ "fcvtmu.2s\t\0" |
| /* 14323 */ "fcvtnu.2s\t\0" |
| /* 14334 */ "fcvtpu.2s\t\0" |
| /* 14345 */ "fcvtzu.2s\t\0" |
| /* 14356 */ "fdiv.2s\t\0" |
| /* 14365 */ "fmov.2s\t\0" |
| /* 14374 */ "frint32x.2s\t\0" |
| /* 14387 */ "frint64x.2s\t\0" |
| /* 14400 */ "fmax.2s\t\0" |
| /* 14409 */ "smax.2s\t\0" |
| /* 14418 */ "umax.2s\t\0" |
| /* 14427 */ "fmulx.2s\t\0" |
| /* 14437 */ "frintx.2s\t\0" |
| /* 14448 */ "frint32z.2s\t\0" |
| /* 14461 */ "frint64z.2s\t\0" |
| /* 14474 */ "clz.2s\t\0" |
| /* 14482 */ "frintz.2s\t\0" |
| /* 14493 */ "sha1su0.4s\t\0" |
| /* 14505 */ "sha256su0.4s\t\0" |
| /* 14519 */ "trn1.4s\t\0" |
| /* 14528 */ "zip1.4s\t\0" |
| /* 14537 */ "uzp1.4s\t\0" |
| /* 14546 */ "sm3ss1.4s\t\0" |
| /* 14557 */ "sha1su1.4s\t\0" |
| /* 14569 */ "sha256su1.4s\t\0" |
| /* 14583 */ "sm3partw1.4s\t\0" |
| /* 14597 */ "sha256h2.4s\t\0" |
| /* 14610 */ "sabal2.4s\t\0" |
| /* 14621 */ "uabal2.4s\t\0" |
| /* 14632 */ "sqdmlal2.4s\t\0" |
| /* 14645 */ "smlal2.4s\t\0" |
| /* 14656 */ "umlal2.4s\t\0" |
| /* 14667 */ "ssubl2.4s\t\0" |
| /* 14678 */ "usubl2.4s\t\0" |
| /* 14689 */ "sabdl2.4s\t\0" |
| /* 14700 */ "uabdl2.4s\t\0" |
| /* 14711 */ "saddl2.4s\t\0" |
| /* 14722 */ "uaddl2.4s\t\0" |
| /* 14733 */ "sshll2.4s\t\0" |
| /* 14744 */ "ushll2.4s\t\0" |
| /* 14755 */ "sqdmull2.4s\t\0" |
| /* 14768 */ "smull2.4s\t\0" |
| /* 14779 */ "umull2.4s\t\0" |
| /* 14790 */ "sqdmlsl2.4s\t\0" |
| /* 14803 */ "smlsl2.4s\t\0" |
| /* 14814 */ "umlsl2.4s\t\0" |
| /* 14825 */ "rsubhn2.4s\t\0" |
| /* 14837 */ "raddhn2.4s\t\0" |
| /* 14849 */ "sqshrn2.4s\t\0" |
| /* 14861 */ "uqshrn2.4s\t\0" |
| /* 14873 */ "sqrshrn2.4s\t\0" |
| /* 14886 */ "uqrshrn2.4s\t\0" |
| /* 14899 */ "trn2.4s\t\0" |
| /* 14908 */ "sqxtn2.4s\t\0" |
| /* 14919 */ "uqxtn2.4s\t\0" |
| /* 14930 */ "sqshrun2.4s\t\0" |
| /* 14943 */ "sqrshrun2.4s\t\0" |
| /* 14957 */ "sqxtun2.4s\t\0" |
| /* 14969 */ "zip2.4s\t\0" |
| /* 14978 */ "uzp2.4s\t\0" |
| /* 14987 */ "ssubw2.4s\t\0" |
| /* 14998 */ "usubw2.4s\t\0" |
| /* 15009 */ "saddw2.4s\t\0" |
| /* 15020 */ "uaddw2.4s\t\0" |
| /* 15031 */ "sm3partw2.4s\t\0" |
| /* 15045 */ "rev64.4s\t\0" |
| /* 15055 */ "sm3tt1a.4s\t\0" |
| /* 15067 */ "sm3tt2a.4s\t\0" |
| /* 15079 */ "saba.4s\t\0" |
| /* 15088 */ "uaba.4s\t\0" |
| /* 15097 */ "fcmla.4s\t\0" |
| /* 15107 */ "fmla.4s\t\0" |
| /* 15116 */ "srsra.4s\t\0" |
| /* 15126 */ "ursra.4s\t\0" |
| /* 15136 */ "ssra.4s\t\0" |
| /* 15145 */ "usra.4s\t\0" |
| /* 15154 */ "frinta.4s\t\0" |
| /* 15165 */ "sm3tt1b.4s\t\0" |
| /* 15177 */ "sm3tt2b.4s\t\0" |
| /* 15189 */ "fsub.4s\t\0" |
| /* 15198 */ "shsub.4s\t\0" |
| /* 15208 */ "uhsub.4s\t\0" |
| /* 15218 */ "sqsub.4s\t\0" |
| /* 15228 */ "uqsub.4s\t\0" |
| /* 15238 */ "sha1c.4s\t\0" |
| /* 15248 */ "bic.4s\t\0" |
| /* 15256 */ "fabd.4s\t\0" |
| /* 15265 */ "sabd.4s\t\0" |
| /* 15274 */ "uabd.4s\t\0" |
| /* 15283 */ "fcadd.4s\t\0" |
| /* 15293 */ "fadd.4s\t\0" |
| /* 15302 */ "srhadd.4s\t\0" |
| /* 15313 */ "urhadd.4s\t\0" |
| /* 15324 */ "shadd.4s\t\0" |
| /* 15334 */ "uhadd.4s\t\0" |
| /* 15344 */ "usqadd.4s\t\0" |
| /* 15355 */ "suqadd.4s\t\0" |
| /* 15366 */ "sm4e.4s\t\0" |
| /* 15375 */ "facge.4s\t\0" |
| /* 15385 */ "fcmge.4s\t\0" |
| /* 15395 */ "fcmle.4s\t\0" |
| /* 15405 */ "frecpe.4s\t\0" |
| /* 15416 */ "urecpe.4s\t\0" |
| /* 15427 */ "frsqrte.4s\t\0" |
| /* 15439 */ "ursqrte.4s\t\0" |
| /* 15451 */ "scvtf.4s\t\0" |
| /* 15461 */ "ucvtf.4s\t\0" |
| /* 15471 */ "fneg.4s\t\0" |
| /* 15480 */ "sqneg.4s\t\0" |
| /* 15490 */ "sha256h.4s\t\0" |
| /* 15502 */ "sqrdmlah.4s\t\0" |
| /* 15515 */ "sqdmulh.4s\t\0" |
| /* 15527 */ "sqrdmulh.4s\t\0" |
| /* 15540 */ "sqrdmlsh.4s\t\0" |
| /* 15553 */ "cmhi.4s\t\0" |
| /* 15562 */ "sli.4s\t\0" |
| /* 15570 */ "mvni.4s\t\0" |
| /* 15579 */ "sri.4s\t\0" |
| /* 15587 */ "frinti.4s\t\0" |
| /* 15598 */ "movi.4s\t\0" |
| /* 15607 */ "sabal.4s\t\0" |
| /* 15617 */ "uabal.4s\t\0" |
| /* 15627 */ "sqdmlal.4s\t\0" |
| /* 15639 */ "smlal.4s\t\0" |
| /* 15649 */ "umlal.4s\t\0" |
| /* 15659 */ "ssubl.4s\t\0" |
| /* 15669 */ "usubl.4s\t\0" |
| /* 15679 */ "sabdl.4s\t\0" |
| /* 15689 */ "uabdl.4s\t\0" |
| /* 15699 */ "saddl.4s\t\0" |
| /* 15709 */ "uaddl.4s\t\0" |
| /* 15719 */ "sqshl.4s\t\0" |
| /* 15729 */ "uqshl.4s\t\0" |
| /* 15739 */ "sqrshl.4s\t\0" |
| /* 15750 */ "uqrshl.4s\t\0" |
| /* 15761 */ "srshl.4s\t\0" |
| /* 15771 */ "urshl.4s\t\0" |
| /* 15781 */ "sshl.4s\t\0" |
| /* 15790 */ "ushl.4s\t\0" |
| /* 15799 */ "sshll.4s\t\0" |
| /* 15809 */ "ushll.4s\t\0" |
| /* 15819 */ "sqdmull.4s\t\0" |
| /* 15831 */ "smull.4s\t\0" |
| /* 15841 */ "umull.4s\t\0" |
| /* 15851 */ "sqdmlsl.4s\t\0" |
| /* 15863 */ "smlsl.4s\t\0" |
| /* 15873 */ "umlsl.4s\t\0" |
| /* 15883 */ "fmul.4s\t\0" |
| /* 15892 */ "sha1m.4s\t\0" |
| /* 15902 */ "fminnm.4s\t\0" |
| /* 15913 */ "fmaxnm.4s\t\0" |
| /* 15924 */ "frintm.4s\t\0" |
| /* 15935 */ "fmin.4s\t\0" |
| /* 15944 */ "smin.4s\t\0" |
| /* 15953 */ "umin.4s\t\0" |
| /* 15962 */ "frintn.4s\t\0" |
| /* 15973 */ "sha1p.4s\t\0" |
| /* 15983 */ "faddp.4s\t\0" |
| /* 15993 */ "sadalp.4s\t\0" |
| /* 16004 */ "uadalp.4s\t\0" |
| /* 16015 */ "saddlp.4s\t\0" |
| /* 16026 */ "uaddlp.4s\t\0" |
| /* 16037 */ "fminnmp.4s\t\0" |
| /* 16049 */ "fmaxnmp.4s\t\0" |
| /* 16061 */ "fminp.4s\t\0" |
| /* 16071 */ "sminp.4s\t\0" |
| /* 16081 */ "uminp.4s\t\0" |
| /* 16091 */ "frintp.4s\t\0" |
| /* 16102 */ "dup.4s\t\0" |
| /* 16110 */ "fmaxp.4s\t\0" |
| /* 16120 */ "smaxp.4s\t\0" |
| /* 16130 */ "umaxp.4s\t\0" |
| /* 16140 */ "fcmeq.4s\t\0" |
| /* 16150 */ "srshr.4s\t\0" |
| /* 16160 */ "urshr.4s\t\0" |
| /* 16170 */ "sshr.4s\t\0" |
| /* 16179 */ "ushr.4s\t\0" |
| /* 16188 */ "orr.4s\t\0" |
| /* 16196 */ "fcvtas.4s\t\0" |
| /* 16207 */ "fabs.4s\t\0" |
| /* 16216 */ "sqabs.4s\t\0" |
| /* 16226 */ "cmhs.4s\t\0" |
| /* 16235 */ "cls.4s\t\0" |
| /* 16243 */ "fmls.4s\t\0" |
| /* 16252 */ "fcvtms.4s\t\0" |
| /* 16263 */ "fcvtns.4s\t\0" |
| /* 16274 */ "frecps.4s\t\0" |
| /* 16285 */ "fcvtps.4s\t\0" |
| /* 16296 */ "frsqrts.4s\t\0" |
| /* 16308 */ "fcvtzs.4s\t\0" |
| /* 16319 */ "facgt.4s\t\0" |
| /* 16329 */ "fcmgt.4s\t\0" |
| /* 16339 */ "fcmlt.4s\t\0" |
| /* 16349 */ "fsqrt.4s\t\0" |
| /* 16359 */ "cmtst.4s\t\0" |
| /* 16369 */ "fcvtau.4s\t\0" |
| /* 16380 */ "sqshlu.4s\t\0" |
| /* 16391 */ "fcvtmu.4s\t\0" |
| /* 16402 */ "fcvtnu.4s\t\0" |
| /* 16413 */ "fcvtpu.4s\t\0" |
| /* 16424 */ "fcvtzu.4s\t\0" |
| /* 16435 */ "addv.4s\t\0" |
| /* 16444 */ "fdiv.4s\t\0" |
| /* 16453 */ "saddlv.4s\t\0" |
| /* 16464 */ "uaddlv.4s\t\0" |
| /* 16475 */ "fminnmv.4s\t\0" |
| /* 16487 */ "fmaxnmv.4s\t\0" |
| /* 16499 */ "fminv.4s\t\0" |
| /* 16509 */ "sminv.4s\t\0" |
| /* 16519 */ "uminv.4s\t\0" |
| /* 16529 */ "fmov.4s\t\0" |
| /* 16538 */ "fmaxv.4s\t\0" |
| /* 16548 */ "smaxv.4s\t\0" |
| /* 16558 */ "umaxv.4s\t\0" |
| /* 16568 */ "ssubw.4s\t\0" |
| /* 16578 */ "usubw.4s\t\0" |
| /* 16588 */ "saddw.4s\t\0" |
| /* 16598 */ "uaddw.4s\t\0" |
| /* 16608 */ "frint32x.4s\t\0" |
| /* 16621 */ "frint64x.4s\t\0" |
| /* 16634 */ "fmax.4s\t\0" |
| /* 16643 */ "smax.4s\t\0" |
| /* 16652 */ "umax.4s\t\0" |
| /* 16661 */ "fmulx.4s\t\0" |
| /* 16671 */ "frintx.4s\t\0" |
| /* 16682 */ "sm4ekey.4s\t\0" |
| /* 16694 */ "frint32z.4s\t\0" |
| /* 16707 */ "frint64z.4s\t\0" |
| /* 16720 */ "clz.4s\t\0" |
| /* 16728 */ "frintz.4s\t\0" |
| /* 16739 */ "rcwscas\t\0" |
| /* 16748 */ "rcwcas\t\0" |
| /* 16756 */ "brkas\t\0" |
| /* 16763 */ "brkpas\t\0" |
| /* 16771 */ "fcvtas\t\0" |
| /* 16779 */ "fabs\t\0" |
| /* 16785 */ "sqabs\t\0" |
| /* 16792 */ "brkbs\t\0" |
| /* 16799 */ "brkpbs\t\0" |
| /* 16807 */ "subs\t\0" |
| /* 16813 */ "sbcs\t\0" |
| /* 16819 */ "adcs\t\0" |
| /* 16825 */ "bics\t\0" |
| /* 16831 */ "adds\t\0" |
| /* 16837 */ "nands\t\0" |
| /* 16844 */ "ptrues\t\0" |
| /* 16852 */ "whilehs\t\0" |
| /* 16861 */ "cmhs\t\0" |
| /* 16867 */ "cmphs\t\0" |
| /* 16874 */ "cls\t\0" |
| /* 16879 */ "whilels\t\0" |
| /* 16888 */ "bfmls\t\0" |
| /* 16895 */ "fnmls\t\0" |
| /* 16902 */ "cmpls\t\0" |
| /* 16909 */ "fcvtms\t\0" |
| /* 16917 */ "brkns\t\0" |
| /* 16924 */ "orns\t\0" |
| /* 16930 */ "fcvtns\t\0" |
| /* 16938 */ "subps\t\0" |
| /* 16945 */ "frecps\t\0" |
| /* 16953 */ "bmops\t\0" |
| /* 16960 */ "bfmops\t\0" |
| /* 16968 */ "usmops\t\0" |
| /* 16976 */ "sumops\t\0" |
| /* 16984 */ "fcvtps\t\0" |
| /* 16992 */ "rdffrs\t\0" |
| /* 17000 */ "mrs\t\0" |
| /* 17005 */ "eors\t\0" |
| /* 17011 */ "nors\t\0" |
| /* 17017 */ "mrrs\t\0" |
| /* 17023 */ "orrs\t\0" |
| /* 17029 */ "frsqrts\t\0" |
| /* 17038 */ "sys\t\0" |
| /* 17043 */ "fcvtzs\t\0" |
| /* 17051 */ "fjcvtzs\t\0" |
| /* 17060 */ "sqdmlalbt\t\0" |
| /* 17071 */ "ssublbt\t\0" |
| /* 17080 */ "saddlbt\t\0" |
| /* 17089 */ "sqdmlslbt\t\0" |
| /* 17100 */ "eorbt\t\0" |
| /* 17107 */ "compact\t\0" |
| /* 17116 */ "wfet\t\0" |
| /* 17122 */ "ret\t\0" |
| /* 17127 */ "ldset\t\0" |
| /* 17134 */ "rcwsset\t\0" |
| /* 17143 */ "rcwset\t\0" |
| /* 17151 */ "facgt\t\0" |
| /* 17158 */ "whilegt\t\0" |
| /* 17167 */ "fcmgt\t\0" |
| /* 17174 */ "cmpgt\t\0" |
| /* 17181 */ "rbit\t\0" |
| /* 17187 */ "trcit\t\0" |
| /* 17194 */ "wfit\t\0" |
| /* 17200 */ "sabalt\t\0" |
| /* 17208 */ "uabalt\t\0" |
| /* 17216 */ "sqdmlalt\t\0" |
| /* 17226 */ "bfmlalt\t\0" |
| /* 17235 */ "smlalt\t\0" |
| /* 17243 */ "umlalt\t\0" |
| /* 17251 */ "ssublt\t\0" |
| /* 17259 */ "usublt\t\0" |
| /* 17267 */ "sbclt\t\0" |
| /* 17274 */ "adclt\t\0" |
| /* 17281 */ "sabdlt\t\0" |
| /* 17289 */ "uabdlt\t\0" |
| /* 17297 */ "saddlt\t\0" |
| /* 17305 */ "uaddlt\t\0" |
| /* 17313 */ "whilelt\t\0" |
| /* 17322 */ "hlt\t\0" |
| /* 17327 */ "sshllt\t\0" |
| /* 17335 */ "ushllt\t\0" |
| /* 17343 */ "sqdmullt\t\0" |
| /* 17353 */ "pmullt\t\0" |
| /* 17361 */ "smullt\t\0" |
| /* 17369 */ "umullt\t\0" |
| /* 17377 */ "fcmlt\t\0" |
| /* 17384 */ "cmplt\t\0" |
| /* 17391 */ "sqdmlslt\t\0" |
| /* 17401 */ "bfmlslt\t\0" |
| /* 17410 */ "smlslt\t\0" |
| /* 17418 */ "umlslt\t\0" |
| /* 17426 */ "fcvtlt\t\0" |
| /* 17434 */ "histcnt\t\0" |
| /* 17443 */ "rsubhnt\t\0" |
| /* 17452 */ "raddhnt\t\0" |
| /* 17461 */ "hint\t\0" |
| /* 17467 */ "sqshrnt\t\0" |
| /* 17476 */ "uqshrnt\t\0" |
| /* 17485 */ "sqrshrnt\t\0" |
| /* 17495 */ "uqrshrnt\t\0" |
| /* 17505 */ "bfcvtnt\t\0" |
| /* 17514 */ "sqxtnt\t\0" |
| /* 17522 */ "uqxtnt\t\0" |
| /* 17530 */ "sqshrunt\t\0" |
| /* 17540 */ "sqrshrunt\t\0" |
| /* 17551 */ "sqxtunt\t\0" |
| /* 17560 */ "fcvtxnt\t\0" |
| /* 17569 */ "cdot\t\0" |
| /* 17575 */ "bfdot\t\0" |
| /* 17582 */ "usdot\t\0" |
| /* 17589 */ "sudot\t\0" |
| /* 17596 */ "bfvdot\t\0" |
| /* 17604 */ "usvdot\t\0" |
| /* 17612 */ "suvdot\t\0" |
| /* 17620 */ "cnot\t\0" |
| /* 17626 */ "tstart\t\0" |
| /* 17634 */ "fsqrt\t\0" |
| /* 17641 */ "ptest\t\0" |
| /* 17648 */ "ttest\t\0" |
| /* 17655 */ "pfirst\t\0" |
| /* 17663 */ "cmtst\t\0" |
| /* 17670 */ "bfcvt\t\0" |
| /* 17677 */ "sqcvt\t\0" |
| /* 17684 */ "uqcvt\t\0" |
| /* 17691 */ "movt\t\0" |
| /* 17697 */ "ssubwt\t\0" |
| /* 17705 */ "usubwt\t\0" |
| /* 17713 */ "saddwt\t\0" |
| /* 17721 */ "uaddwt\t\0" |
| /* 17729 */ "bext\t\0" |
| /* 17735 */ "pnext\t\0" |
| /* 17742 */ "pext\t\0" |
| /* 17748 */ "fcvtau\t\0" |
| /* 17756 */ "sqshlu\t\0" |
| /* 17764 */ "fcvtmu\t\0" |
| /* 17772 */ "fcvtnu\t\0" |
| /* 17780 */ "fcvtpu\t\0" |
| /* 17788 */ "sqrshru\t\0" |
| /* 17797 */ "sqcvtu\t\0" |
| /* 17805 */ "fcvtzu\t\0" |
| /* 17813 */ "st64bv\t\0" |
| /* 17821 */ "faddv\t\0" |
| /* 17828 */ "saddv\t\0" |
| /* 17835 */ "uaddv\t\0" |
| /* 17842 */ "andv\t\0" |
| /* 17848 */ "rev\t\0" |
| /* 17853 */ "fdiv\t\0" |
| /* 17859 */ "sdiv\t\0" |
| /* 17865 */ "udiv\t\0" |
| /* 17871 */ "fminnmv\t\0" |
| /* 17880 */ "fmaxnmv\t\0" |
| /* 17889 */ "fminv\t\0" |
| /* 17896 */ "sminv\t\0" |
| /* 17903 */ "uminv\t\0" |
| /* 17910 */ "csinv\t\0" |
| /* 17917 */ "fmov\t\0" |
| /* 17923 */ "pmov\t\0" |
| /* 17929 */ "faddqv\t\0" |
| /* 17937 */ "andqv\t\0" |
| /* 17944 */ "fminnmqv\t\0" |
| /* 17954 */ "fmaxnmqv\t\0" |
| /* 17964 */ "fminqv\t\0" |
| /* 17972 */ "sminqv\t\0" |
| /* 17980 */ "uminqv\t\0" |
| /* 17988 */ "eorqv\t\0" |
| /* 17995 */ "fmaxqv\t\0" |
| /* 18003 */ "smaxqv\t\0" |
| /* 18011 */ "umaxqv\t\0" |
| /* 18019 */ "eorv\t\0" |
| /* 18025 */ "fmaxv\t\0" |
| /* 18032 */ "smaxv\t\0" |
| /* 18039 */ "umaxv\t\0" |
| /* 18046 */ "ld1w\t\0" |
| /* 18052 */ "ldff1w\t\0" |
| /* 18060 */ "ldnf1w\t\0" |
| /* 18068 */ "ldnt1w\t\0" |
| /* 18076 */ "stnt1w\t\0" |
| /* 18084 */ "st1w\t\0" |
| /* 18090 */ "crc32w\t\0" |
| /* 18098 */ "ld2w\t\0" |
| /* 18104 */ "st2w\t\0" |
| /* 18110 */ "ld3w\t\0" |
| /* 18116 */ "st3w\t\0" |
| /* 18122 */ "ld4w\t\0" |
| /* 18128 */ "st4w\t\0" |
| /* 18134 */ "crc32cw\t\0" |
| /* 18143 */ "sqdecw\t\0" |
| /* 18151 */ "uqdecw\t\0" |
| /* 18159 */ "sqincw\t\0" |
| /* 18167 */ "uqincw\t\0" |
| /* 18175 */ "prfw\t\0" |
| /* 18181 */ "ld1row\t\0" |
| /* 18189 */ "ld1rqw\t\0" |
| /* 18197 */ "ld1rw\t\0" |
| /* 18204 */ "whilerw\t\0" |
| /* 18213 */ "ld1sw\t\0" |
| /* 18220 */ "ldff1sw\t\0" |
| /* 18229 */ "ldnf1sw\t\0" |
| /* 18238 */ "ldnt1sw\t\0" |
| /* 18247 */ "ldpsw\t\0" |
| /* 18254 */ "ld1rsw\t\0" |
| /* 18262 */ "ldrsw\t\0" |
| /* 18269 */ "ldtrsw\t\0" |
| /* 18277 */ "ldursw\t\0" |
| /* 18285 */ "ldapursw\t\0" |
| /* 18295 */ "cntw\t\0" |
| /* 18301 */ "sxtw\t\0" |
| /* 18307 */ "uxtw\t\0" |
| /* 18313 */ "revw\t\0" |
| /* 18319 */ "crc32x\t\0" |
| /* 18327 */ "frint32x\t\0" |
| /* 18337 */ "frint64x\t\0" |
| /* 18347 */ "bcax\t\0" |
| /* 18353 */ "bfmax\t\0" |
| /* 18360 */ "ldsmax\t\0" |
| /* 18368 */ "ldumax\t\0" |
| /* 18376 */ "tbx\t\0" |
| /* 18381 */ "crc32cx\t\0" |
| /* 18390 */ "index\t\0" |
| /* 18397 */ "clrex\t\0" |
| /* 18404 */ "movprfx\t\0" |
| /* 18413 */ "fmulx\t\0" |
| /* 18420 */ "frecpx\t\0" |
| /* 18428 */ "frintx\t\0" |
| /* 18436 */ "fcvtx\t\0" |
| /* 18443 */ "sm4ekey\t\0" |
| /* 18452 */ "fcpy\t\0" |
| /* 18458 */ "frint32z\t\0" |
| /* 18468 */ "frint64z\t\0" |
| /* 18478 */ "braaz\t\0" |
| /* 18485 */ "blraaz\t\0" |
| /* 18493 */ "movaz\t\0" |
| /* 18500 */ "brabz\t\0" |
| /* 18507 */ "blrabz\t\0" |
| /* 18515 */ "cbz\t\0" |
| /* 18520 */ "tbz\t\0" |
| /* 18525 */ "clz\t\0" |
| /* 18530 */ "cbnz\t\0" |
| /* 18536 */ "tbnz\t\0" |
| /* 18542 */ "ctz\t\0" |
| /* 18547 */ "frintz\t\0" |
| /* 18555 */ "movz\t\0" |
| /* 18561 */ ".tlsdesccall \0" |
| /* 18575 */ "zero\t{ \0" |
| /* 18583 */ "# XRay Function Patchable RET.\0" |
| /* 18614 */ "b.\0" |
| /* 18617 */ "bc.\0" |
| /* 18621 */ "# XRay Typed Event Log.\0" |
| /* 18645 */ "# XRay Custom Event Log.\0" |
| /* 18670 */ "# XRay Function Enter.\0" |
| /* 18693 */ "# XRay Tail Call Exit.\0" |
| /* 18716 */ "# XRay Function Exit.\0" |
| /* 18738 */ "hint\t#10\0" |
| /* 18747 */ "hint\t#30\0" |
| /* 18756 */ "hint\t#31\0" |
| /* 18765 */ "hint\t#12\0" |
| /* 18774 */ "fmlal2\0" |
| /* 18781 */ "fmlsl2\0" |
| /* 18788 */ "hint\t#14\0" |
| /* 18797 */ "hint\t#24\0" |
| /* 18806 */ "hint\t#25\0" |
| /* 18815 */ "setf16\0" |
| /* 18822 */ "hint\t#26\0" |
| /* 18831 */ "hint\t#7\0" |
| /* 18839 */ "hint\t#27\0" |
| /* 18848 */ "hint\t#8\0" |
| /* 18856 */ "hint\t#28\0" |
| /* 18865 */ "setf8\0" |
| /* 18871 */ "hint\t#29\0" |
| /* 18880 */ "LIFETIME_END\0" |
| /* 18893 */ "PSEUDO_PROBE\0" |
| /* 18906 */ "BUNDLE\0" |
| /* 18913 */ "DBG_VALUE\0" |
| /* 18923 */ "DBG_INSTR_REF\0" |
| /* 18937 */ "DBG_PHI\0" |
| /* 18945 */ "DBG_LABEL\0" |
| /* 18955 */ "LIFETIME_START\0" |
| /* 18970 */ "DBG_VALUE_LIST\0" |
| /* 18985 */ "cpyfe\t[\0" |
| /* 18993 */ "setge\t[\0" |
| /* 19001 */ "sete\t[\0" |
| /* 19008 */ "cpye\t[\0" |
| /* 19015 */ "cpyfm\t[\0" |
| /* 19023 */ "setgm\t[\0" |
| /* 19031 */ "setm\t[\0" |
| /* 19038 */ "cpym\t[\0" |
| /* 19045 */ "cpyfen\t[\0" |
| /* 19054 */ "setgen\t[\0" |
| /* 19063 */ "seten\t[\0" |
| /* 19071 */ "cpyen\t[\0" |
| /* 19079 */ "cpyfmn\t[\0" |
| /* 19088 */ "setgmn\t[\0" |
| /* 19097 */ "setmn\t[\0" |
| /* 19105 */ "cpymn\t[\0" |
| /* 19113 */ "cpyfpn\t[\0" |
| /* 19122 */ "setgpn\t[\0" |
| /* 19131 */ "setpn\t[\0" |
| /* 19139 */ "cpypn\t[\0" |
| /* 19147 */ "cpyfern\t[\0" |
| /* 19157 */ "cpyern\t[\0" |
| /* 19166 */ "cpyfmrn\t[\0" |
| /* 19176 */ "cpymrn\t[\0" |
| /* 19185 */ "cpyfprn\t[\0" |
| /* 19195 */ "cpyprn\t[\0" |
| /* 19204 */ "cpyfetrn\t[\0" |
| /* 19215 */ "cpyetrn\t[\0" |
| /* 19225 */ "cpyfmtrn\t[\0" |
| /* 19236 */ "cpymtrn\t[\0" |
| /* 19246 */ "cpyfptrn\t[\0" |
| /* 19257 */ "cpyptrn\t[\0" |
| /* 19267 */ "cpyfertrn\t[\0" |
| /* 19279 */ "cpyertrn\t[\0" |
| /* 19290 */ "cpyfmrtrn\t[\0" |
| /* 19302 */ "cpymrtrn\t[\0" |
| /* 19313 */ "cpyfprtrn\t[\0" |
| /* 19325 */ "cpyprtrn\t[\0" |
| /* 19336 */ "cpyfewtrn\t[\0" |
| /* 19348 */ "cpyewtrn\t[\0" |
| /* 19359 */ "cpyfmwtrn\t[\0" |
| /* 19371 */ "cpymwtrn\t[\0" |
| /* 19382 */ "cpyfpwtrn\t[\0" |
| /* 19394 */ "cpypwtrn\t[\0" |
| /* 19405 */ "cpyfetn\t[\0" |
| /* 19415 */ "setgetn\t[\0" |
| /* 19425 */ "setetn\t[\0" |
| /* 19434 */ "cpyetn\t[\0" |
| /* 19443 */ "cpyfmtn\t[\0" |
| /* 19453 */ "setgmtn\t[\0" |
| /* 19463 */ "setmtn\t[\0" |
| /* 19472 */ "cpymtn\t[\0" |
| /* 19481 */ "cpyfptn\t[\0" |
| /* 19491 */ "setgptn\t[\0" |
| /* 19501 */ "setptn\t[\0" |
| /* 19510 */ "cpyptn\t[\0" |
| /* 19519 */ "cpyfertn\t[\0" |
| /* 19530 */ "cpyertn\t[\0" |
| /* 19540 */ "cpyfmrtn\t[\0" |
| /* 19551 */ "cpymrtn\t[\0" |
| /* 19561 */ "cpyfprtn\t[\0" |
| /* 19572 */ "cpyprtn\t[\0" |
| /* 19582 */ "cpyfewtn\t[\0" |
| /* 19593 */ "cpyewtn\t[\0" |
| /* 19603 */ "cpyfmwtn\t[\0" |
| /* 19614 */ "cpymwtn\t[\0" |
| /* 19624 */ "cpyfpwtn\t[\0" |
| /* 19635 */ "cpypwtn\t[\0" |
| /* 19645 */ "cpyfewn\t[\0" |
| /* 19655 */ "cpyewn\t[\0" |
| /* 19664 */ "cpyfmwn\t[\0" |
| /* 19674 */ "cpymwn\t[\0" |
| /* 19683 */ "cpyfpwn\t[\0" |
| /* 19693 */ "cpypwn\t[\0" |
| /* 19702 */ "cpyfetwn\t[\0" |
| /* 19713 */ "cpyetwn\t[\0" |
| /* 19723 */ "cpyfmtwn\t[\0" |
| /* 19734 */ "cpymtwn\t[\0" |
| /* 19744 */ "cpyfptwn\t[\0" |
| /* 19755 */ "cpyptwn\t[\0" |
| /* 19765 */ "cpyfertwn\t[\0" |
| /* 19777 */ "cpyertwn\t[\0" |
| /* 19788 */ "cpyfmrtwn\t[\0" |
| /* 19800 */ "cpymrtwn\t[\0" |
| /* 19811 */ "cpyfprtwn\t[\0" |
| /* 19823 */ "cpyprtwn\t[\0" |
| /* 19834 */ "cpyfewtwn\t[\0" |
| /* 19846 */ "cpyewtwn\t[\0" |
| /* 19857 */ "cpyfmwtwn\t[\0" |
| /* 19869 */ "cpymwtwn\t[\0" |
| /* 19880 */ "cpyfpwtwn\t[\0" |
| /* 19892 */ "cpypwtwn\t[\0" |
| /* 19903 */ "cpyfp\t[\0" |
| /* 19911 */ "setgp\t[\0" |
| /* 19919 */ "setp\t[\0" |
| /* 19926 */ "cpyp\t[\0" |
| /* 19933 */ "cpyfet\t[\0" |
| /* 19942 */ "setget\t[\0" |
| /* 19951 */ "setet\t[\0" |
| /* 19959 */ "cpyet\t[\0" |
| /* 19967 */ "cpyfmt\t[\0" |
| /* 19976 */ "setgmt\t[\0" |
| /* 19985 */ "setmt\t[\0" |
| /* 19993 */ "cpymt\t[\0" |
| /* 20001 */ "cpyfpt\t[\0" |
| /* 20010 */ "setgpt\t[\0" |
| /* 20019 */ "setpt\t[\0" |
| /* 20027 */ "cpypt\t[\0" |
| /* 20035 */ "cpyfert\t[\0" |
| /* 20045 */ "cpyert\t[\0" |
| /* 20054 */ "cpyfmrt\t[\0" |
| /* 20064 */ "cpymrt\t[\0" |
| /* 20073 */ "cpyfprt\t[\0" |
| /* 20083 */ "cpyprt\t[\0" |
| /* 20092 */ "cpyfewt\t[\0" |
| /* 20102 */ "cpyewt\t[\0" |
| /* 20111 */ "cpyfmwt\t[\0" |
| /* 20121 */ "cpymwt\t[\0" |
| /* 20130 */ "cpyfpwt\t[\0" |
| /* 20140 */ "cpypwt\t[\0" |
| /* 20149 */ "eretaa\0" |
| /* 20156 */ "bfmmla\0" |
| /* 20163 */ "usmmla\0" |
| /* 20170 */ "ummla\0" |
| /* 20176 */ "eretab\0" |
| /* 20183 */ "bfmlalb\0" |
| /* 20191 */ "sb\0" |
| /* 20194 */ "rmif\0" |
| /* 20199 */ "xaflag\0" |
| /* 20206 */ "axflag\0" |
| /* 20213 */ "brb\tinj\0" |
| /* 20221 */ "fmlal\0" |
| /* 20227 */ "# FEntry call\0" |
| /* 20241 */ "brb\tiall\0" |
| /* 20250 */ "fmlsl\0" |
| /* 20256 */ "setffr\0" |
| /* 20263 */ "drps\0" |
| /* 20268 */ "eret\0" |
| /* 20273 */ "tcommit\0" |
| /* 20281 */ "bfmlalt\0" |
| /* 20289 */ "bfdot\0" |
| /* 20295 */ "usdot\0" |
| /* 20301 */ "udot\0" |
| /* 20306 */ "cfinv\0" |
| /* 20312 */ "ld1b\t{\0" |
| /* 20319 */ "st1b\t{\0" |
| /* 20326 */ "ld1d\t{\0" |
| /* 20333 */ "st1d\t{\0" |
| /* 20340 */ "ld1h\t{\0" |
| /* 20347 */ "st1h\t{\0" |
| /* 20354 */ "ld1q\t{\0" |
| /* 20361 */ "st1q\t{\0" |
| /* 20368 */ "ld1w\t{\0" |
| /* 20375 */ "st1w\t{\0" |
| }; |
| #ifdef __GNUC__ |
| #pragma GCC diagnostic pop |
| #endif |
| |
| static const uint32_t OpInfo0[] = { |
| 0U, // PHI |
| 0U, // INLINEASM |
| 0U, // INLINEASM_BR |
| 0U, // CFI_INSTRUCTION |
| 0U, // EH_LABEL |
| 0U, // GC_LABEL |
| 0U, // ANNOTATION_LABEL |
| 0U, // KILL |
| 0U, // EXTRACT_SUBREG |
| 0U, // INSERT_SUBREG |
| 0U, // IMPLICIT_DEF |
| 0U, // SUBREG_TO_REG |
| 0U, // COPY_TO_REGCLASS |
| 18914U, // DBG_VALUE |
| 18971U, // DBG_VALUE_LIST |
| 18924U, // DBG_INSTR_REF |
| 18938U, // DBG_PHI |
| 18946U, // DBG_LABEL |
| 0U, // REG_SEQUENCE |
| 0U, // COPY |
| 18907U, // BUNDLE |
| 18956U, // LIFETIME_START |
| 18881U, // LIFETIME_END |
| 18894U, // PSEUDO_PROBE |
| 0U, // ARITH_FENCE |
| 0U, // STACKMAP |
| 20228U, // FENTRY_CALL |
| 0U, // PATCHPOINT |
| 0U, // LOAD_STACK_GUARD |
| 0U, // PREALLOCATED_SETUP |
| 0U, // PREALLOCATED_ARG |
| 0U, // STATEPOINT |
| 0U, // LOCAL_ESCAPE |
| 0U, // FAULTING_OP |
| 0U, // PATCHABLE_OP |
| 18671U, // PATCHABLE_FUNCTION_ENTER |
| 18584U, // PATCHABLE_RET |
| 18717U, // PATCHABLE_FUNCTION_EXIT |
| 18694U, // PATCHABLE_TAIL_CALL |
| 18646U, // PATCHABLE_EVENT_CALL |
| 18622U, // PATCHABLE_TYPED_EVENT_CALL |
| 0U, // ICALL_BRANCH_FUNNEL |
| 0U, // MEMBARRIER |
| 0U, // G_ASSERT_SEXT |
| 0U, // G_ASSERT_ZEXT |
| 0U, // G_ASSERT_ALIGN |
| 0U, // G_ADD |
| 0U, // G_SUB |
| 0U, // G_MUL |
| 0U, // G_SDIV |
| 0U, // G_UDIV |
| 0U, // G_SREM |
| 0U, // G_UREM |
| 0U, // G_SDIVREM |
| 0U, // G_UDIVREM |
| 0U, // G_AND |
| 0U, // G_OR |
| 0U, // G_XOR |
| 0U, // G_IMPLICIT_DEF |
| 0U, // G_PHI |
| 0U, // G_FRAME_INDEX |
| 0U, // G_GLOBAL_VALUE |
| 0U, // G_EXTRACT |
| 0U, // G_UNMERGE_VALUES |
| 0U, // G_INSERT |
| 0U, // G_MERGE_VALUES |
| 0U, // G_BUILD_VECTOR |
| 0U, // G_BUILD_VECTOR_TRUNC |
| 0U, // G_CONCAT_VECTORS |
| 0U, // G_PTRTOINT |
| 0U, // G_INTTOPTR |
| 0U, // G_BITCAST |
| 0U, // G_FREEZE |
| 0U, // G_INTRINSIC_FPTRUNC_ROUND |
| 0U, // G_INTRINSIC_TRUNC |
| 0U, // G_INTRINSIC_ROUND |
| 0U, // G_INTRINSIC_LRINT |
| 0U, // G_INTRINSIC_ROUNDEVEN |
| 0U, // G_READCYCLECOUNTER |
| 0U, // G_LOAD |
| 0U, // G_SEXTLOAD |
| 0U, // G_ZEXTLOAD |
| 0U, // G_INDEXED_LOAD |
| 0U, // G_INDEXED_SEXTLOAD |
| 0U, // G_INDEXED_ZEXTLOAD |
| 0U, // G_STORE |
| 0U, // G_INDEXED_STORE |
| 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 0U, // G_ATOMIC_CMPXCHG |
| 0U, // G_ATOMICRMW_XCHG |
| 0U, // G_ATOMICRMW_ADD |
| 0U, // G_ATOMICRMW_SUB |
| 0U, // G_ATOMICRMW_AND |
| 0U, // G_ATOMICRMW_NAND |
| 0U, // G_ATOMICRMW_OR |
| 0U, // G_ATOMICRMW_XOR |
| 0U, // G_ATOMICRMW_MAX |
| 0U, // G_ATOMICRMW_MIN |
| 0U, // G_ATOMICRMW_UMAX |
| 0U, // G_ATOMICRMW_UMIN |
| 0U, // G_ATOMICRMW_FADD |
| 0U, // G_ATOMICRMW_FSUB |
| 0U, // G_ATOMICRMW_FMAX |
| 0U, // G_ATOMICRMW_FMIN |
| 0U, // G_ATOMICRMW_UINC_WRAP |
| 0U, // G_ATOMICRMW_UDEC_WRAP |
| 0U, // G_FENCE |
| 0U, // G_BRCOND |
| 0U, // G_BRINDIRECT |
| 0U, // G_INVOKE_REGION_START |
| 0U, // G_INTRINSIC |
| 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 0U, // G_ANYEXT |
| 0U, // G_TRUNC |
| 0U, // G_CONSTANT |
| 0U, // G_FCONSTANT |
| 0U, // G_VASTART |
| 0U, // G_VAARG |
| 0U, // G_SEXT |
| 0U, // G_SEXT_INREG |
| 0U, // G_ZEXT |
| 0U, // G_SHL |
| 0U, // G_LSHR |
| 0U, // G_ASHR |
| 0U, // G_FSHL |
| 0U, // G_FSHR |
| 0U, // G_ROTR |
| 0U, // G_ROTL |
| 0U, // G_ICMP |
| 0U, // G_FCMP |
| 0U, // G_SELECT |
| 0U, // G_UADDO |
| 0U, // G_UADDE |
| 0U, // G_USUBO |
| 0U, // G_USUBE |
| 0U, // G_SADDO |
| 0U, // G_SADDE |
| 0U, // G_SSUBO |
| 0U, // G_SSUBE |
| 0U, // G_UMULO |
| 0U, // G_SMULO |
| 0U, // G_UMULH |
| 0U, // G_SMULH |
| 0U, // G_UADDSAT |
| 0U, // G_SADDSAT |
| 0U, // G_USUBSAT |
| 0U, // G_SSUBSAT |
| 0U, // G_USHLSAT |
| 0U, // G_SSHLSAT |
| 0U, // G_SMULFIX |
| 0U, // G_UMULFIX |
| 0U, // G_SMULFIXSAT |
| 0U, // G_UMULFIXSAT |
| 0U, // G_SDIVFIX |
| 0U, // G_UDIVFIX |
| 0U, // G_SDIVFIXSAT |
| 0U, // G_UDIVFIXSAT |
| 0U, // G_FADD |
| 0U, // G_FSUB |
| 0U, // G_FMUL |
| 0U, // G_FMA |
| 0U, // G_FMAD |
| 0U, // G_FDIV |
| 0U, // G_FREM |
| 0U, // G_FPOW |
| 0U, // G_FPOWI |
| 0U, // G_FEXP |
| 0U, // G_FEXP2 |
| 0U, // G_FLOG |
| 0U, // G_FLOG2 |
| 0U, // G_FLOG10 |
| 0U, // G_FNEG |
| 0U, // G_FPEXT |
| 0U, // G_FPTRUNC |
| 0U, // G_FPTOSI |
| 0U, // G_FPTOUI |
| 0U, // G_SITOFP |
| 0U, // G_UITOFP |
| 0U, // G_FABS |
| 0U, // G_FCOPYSIGN |
| 0U, // G_IS_FPCLASS |
| 0U, // G_FCANONICALIZE |
| 0U, // G_FMINNUM |
| 0U, // G_FMAXNUM |
| 0U, // G_FMINNUM_IEEE |
| 0U, // G_FMAXNUM_IEEE |
| 0U, // G_FMINIMUM |
| 0U, // G_FMAXIMUM |
| 0U, // G_PTR_ADD |
| 0U, // G_PTRMASK |
| 0U, // G_SMIN |
| 0U, // G_SMAX |
| 0U, // G_UMIN |
| 0U, // G_UMAX |
| 0U, // G_ABS |
| 0U, // G_LROUND |
| 0U, // G_LLROUND |
| 0U, // G_BR |
| 0U, // G_BRJT |
| 0U, // G_INSERT_VECTOR_ELT |
| 0U, // G_EXTRACT_VECTOR_ELT |
| 0U, // G_SHUFFLE_VECTOR |
| 0U, // G_CTTZ |
| 0U, // G_CTTZ_ZERO_UNDEF |
| 0U, // G_CTLZ |
| 0U, // G_CTLZ_ZERO_UNDEF |
| 0U, // G_CTPOP |
| 0U, // G_BSWAP |
| 0U, // G_BITREVERSE |
| 0U, // G_FCEIL |
| 0U, // G_FCOS |
| 0U, // G_FSIN |
| 0U, // G_FSQRT |
| 0U, // G_FFLOOR |
| 0U, // G_FRINT |
| 0U, // G_FNEARBYINT |
| 0U, // G_ADDRSPACE_CAST |
| 0U, // G_BLOCK_ADDR |
| 0U, // G_JUMP_TABLE |
| 0U, // G_DYN_STACKALLOC |
| 0U, // G_STRICT_FADD |
| 0U, // G_STRICT_FSUB |
| 0U, // G_STRICT_FMUL |
| 0U, // G_STRICT_FDIV |
| 0U, // G_STRICT_FREM |
| 0U, // G_STRICT_FMA |
| 0U, // G_STRICT_FSQRT |
| 0U, // G_READ_REGISTER |
| 0U, // G_WRITE_REGISTER |
| 0U, // G_MEMCPY |
| 0U, // G_MEMCPY_INLINE |
| 0U, // G_MEMMOVE |
| 0U, // G_MEMSET |
| 0U, // G_BZERO |
| 0U, // G_VECREDUCE_SEQ_FADD |
| 0U, // G_VECREDUCE_SEQ_FMUL |
| 0U, // G_VECREDUCE_FADD |
| 0U, // G_VECREDUCE_FMUL |
| 0U, // G_VECREDUCE_FMAX |
| 0U, // G_VECREDUCE_FMIN |
| 0U, // G_VECREDUCE_ADD |
| 0U, // G_VECREDUCE_MUL |
| 0U, // G_VECREDUCE_AND |
| 0U, // G_VECREDUCE_OR |
| 0U, // G_VECREDUCE_XOR |
| 0U, // G_VECREDUCE_SMAX |
| 0U, // G_VECREDUCE_SMIN |
| 0U, // G_VECREDUCE_UMAX |
| 0U, // G_VECREDUCE_UMIN |
| 0U, // G_SBFX |
| 0U, // G_UBFX |
| 0U, // ABS_ZPmZ_UNDEF_B |
| 0U, // ABS_ZPmZ_UNDEF_D |
| 0U, // ABS_ZPmZ_UNDEF_H |
| 0U, // ABS_ZPmZ_UNDEF_S |
| 0U, // ADDHA_MPPZ_D_PSEUDO_D |
| 0U, // ADDHA_MPPZ_S_PSEUDO_S |
| 0U, // ADDSWrr |
| 0U, // ADDSXrr |
| 0U, // ADDVA_MPPZ_D_PSEUDO_D |
| 0U, // ADDVA_MPPZ_S_PSEUDO_S |
| 0U, // ADDWrr |
| 0U, // ADDXrr |
| 0U, // ADD_VG2_M2Z2Z_D_PSEUDO |
| 0U, // ADD_VG2_M2Z2Z_S_PSEUDO |
| 0U, // ADD_VG2_M2ZZ_D_PSEUDO |
| 0U, // ADD_VG2_M2ZZ_S_PSEUDO |
| 0U, // ADD_VG4_M4Z4Z_D_PSEUDO |
| 0U, // ADD_VG4_M4Z4Z_S_PSEUDO |
| 0U, // ADD_VG4_M4ZZ_D_PSEUDO |
| 0U, // ADD_VG4_M4ZZ_S_PSEUDO |
| 0U, // ADD_ZPZZ_ZERO_B |
| 0U, // ADD_ZPZZ_ZERO_D |
| 0U, // ADD_ZPZZ_ZERO_H |
| 0U, // ADD_ZPZZ_ZERO_S |
| 0U, // ADDlowTLS |
| 0U, // ADJCALLSTACKDOWN |
| 0U, // ADJCALLSTACKUP |
| 0U, // AESIMCrrTied |
| 0U, // AESMCrrTied |
| 0U, // ANDSWrr |
| 0U, // ANDSXrr |
| 0U, // ANDWrr |
| 0U, // ANDXrr |
| 0U, // AND_ZPZZ_ZERO_B |
| 0U, // AND_ZPZZ_ZERO_D |
| 0U, // AND_ZPZZ_ZERO_H |
| 0U, // AND_ZPZZ_ZERO_S |
| 0U, // ASRD_ZPZI_ZERO_B |
| 0U, // ASRD_ZPZI_ZERO_D |
| 0U, // ASRD_ZPZI_ZERO_H |
| 0U, // ASRD_ZPZI_ZERO_S |
| 0U, // ASR_ZPZI_UNDEF_B |
| 0U, // ASR_ZPZI_UNDEF_D |
| 0U, // ASR_ZPZI_UNDEF_H |
| 0U, // ASR_ZPZI_UNDEF_S |
| 0U, // ASR_ZPZZ_UNDEF_B |
| 0U, // ASR_ZPZZ_UNDEF_D |
| 0U, // ASR_ZPZZ_UNDEF_H |
| 0U, // ASR_ZPZZ_UNDEF_S |
| 0U, // ASR_ZPZZ_ZERO_B |
| 0U, // ASR_ZPZZ_ZERO_D |
| 0U, // ASR_ZPZZ_ZERO_H |
| 0U, // ASR_ZPZZ_ZERO_S |
| 0U, // BFDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 0U, // BFDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 0U, // BFDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 0U, // BFDOT_VG4_M4ZZI_HtoS_PSEUDO |
| 0U, // BFMLAL_MZZI_S_PSEUDO |
| 0U, // BFMLAL_MZZ_S_PSEUDO |
| 0U, // BFMLAL_VG2_M2Z2Z_S_PSEUDO |
| 0U, // BFMLAL_VG2_M2ZZI_S_PSEUDO |
| 0U, // BFMLAL_VG2_M2ZZ_S_PSEUDO |
| 0U, // BFMLAL_VG4_M4Z4Z_S_PSEUDO |
| 0U, // BFMLAL_VG4_M4ZZI_S_PSEUDO |
| 0U, // BFMLAL_VG4_M4ZZ_S_PSEUDO |
| 0U, // BFMLA_VG2_M2Z2Z_PSEUDO |
| 0U, // BFMLA_VG4_M4Z4Z_PSEUDO |
| 0U, // BFMLSL_MZZI_S_PSEUDO |
| 0U, // BFMLSL_MZZ_S_PSEUDO |
| 0U, // BFMLSL_VG2_M2Z2Z_S_PSEUDO |
| 0U, // BFMLSL_VG2_M2ZZI_S_PSEUDO |
| 0U, // BFMLSL_VG2_M2ZZ_S_PSEUDO |
| 0U, // BFMLSL_VG4_M4Z4Z_S_PSEUDO |
| 0U, // BFMLSL_VG4_M4ZZI_S_PSEUDO |
| 0U, // BFMLSL_VG4_M4ZZ_S_PSEUDO |
| 0U, // BFMLS_VG2_M2Z2Z_PSEUDO |
| 0U, // BFMLS_VG4_M4Z4Z_PSEUDO |
| 0U, // BFMOPA_MPPZZ_PSEUDO |
| 0U, // BFMOPS_MPPZZ_PSEUDO |
| 0U, // BFVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 0U, // BICSWrr |
| 0U, // BICSXrr |
| 0U, // BICWrr |
| 0U, // BICXrr |
| 0U, // BIC_ZPZZ_ZERO_B |
| 0U, // BIC_ZPZZ_ZERO_D |
| 0U, // BIC_ZPZZ_ZERO_H |
| 0U, // BIC_ZPZZ_ZERO_S |
| 0U, // BLRNoIP |
| 0U, // BLR_BTI |
| 0U, // BLR_RVMARKER |
| 0U, // BSPv16i8 |
| 0U, // BSPv8i8 |
| 0U, // CATCHRET |
| 0U, // CLEANUPRET |
| 0U, // CLS_ZPmZ_UNDEF_B |
| 0U, // CLS_ZPmZ_UNDEF_D |
| 0U, // CLS_ZPmZ_UNDEF_H |
| 0U, // CLS_ZPmZ_UNDEF_S |
| 0U, // CLZ_ZPmZ_UNDEF_B |
| 0U, // CLZ_ZPmZ_UNDEF_D |
| 0U, // CLZ_ZPmZ_UNDEF_H |
| 0U, // CLZ_ZPmZ_UNDEF_S |
| 0U, // CMP_SWAP_128 |
| 0U, // CMP_SWAP_128_ACQUIRE |
| 0U, // CMP_SWAP_128_MONOTONIC |
| 0U, // CMP_SWAP_128_RELEASE |
| 0U, // CMP_SWAP_16 |
| 0U, // CMP_SWAP_32 |
| 0U, // CMP_SWAP_64 |
| 0U, // CMP_SWAP_8 |
| 0U, // CNOT_ZPmZ_UNDEF_B |
| 0U, // CNOT_ZPmZ_UNDEF_D |
| 0U, // CNOT_ZPmZ_UNDEF_H |
| 0U, // CNOT_ZPmZ_UNDEF_S |
| 0U, // CNT_ZPmZ_UNDEF_B |
| 0U, // CNT_ZPmZ_UNDEF_D |
| 0U, // CNT_ZPmZ_UNDEF_H |
| 0U, // CNT_ZPmZ_UNDEF_S |
| 0U, // EMITBKEY |
| 0U, // EMITMTETAGGED |
| 0U, // EONWrr |
| 0U, // EONXrr |
| 0U, // EORWrr |
| 0U, // EORXrr |
| 0U, // EOR_ZPZZ_ZERO_B |
| 0U, // EOR_ZPZZ_ZERO_D |
| 0U, // EOR_ZPZZ_ZERO_H |
| 0U, // EOR_ZPZZ_ZERO_S |
| 0U, // F128CSEL |
| 0U, // FABD_ZPZZ_UNDEF_D |
| 0U, // FABD_ZPZZ_UNDEF_H |
| 0U, // FABD_ZPZZ_UNDEF_S |
| 0U, // FABD_ZPZZ_ZERO_D |
| 0U, // FABD_ZPZZ_ZERO_H |
| 0U, // FABD_ZPZZ_ZERO_S |
| 0U, // FABS_ZPmZ_UNDEF_D |
| 0U, // FABS_ZPmZ_UNDEF_H |
| 0U, // FABS_ZPmZ_UNDEF_S |
| 0U, // FADD_ZPZI_UNDEF_D |
| 0U, // FADD_ZPZI_UNDEF_H |
| 0U, // FADD_ZPZI_UNDEF_S |
| 0U, // FADD_ZPZI_ZERO_D |
| 0U, // FADD_ZPZI_ZERO_H |
| 0U, // FADD_ZPZI_ZERO_S |
| 0U, // FADD_ZPZZ_UNDEF_D |
| 0U, // FADD_ZPZZ_UNDEF_H |
| 0U, // FADD_ZPZZ_UNDEF_S |
| 0U, // FADD_ZPZZ_ZERO_D |
| 0U, // FADD_ZPZZ_ZERO_H |
| 0U, // FADD_ZPZZ_ZERO_S |
| 0U, // FCVTZS_ZPmZ_DtoD_UNDEF |
| 0U, // FCVTZS_ZPmZ_DtoS_UNDEF |
| 0U, // FCVTZS_ZPmZ_HtoD_UNDEF |
| 0U, // FCVTZS_ZPmZ_HtoH_UNDEF |
| 0U, // FCVTZS_ZPmZ_HtoS_UNDEF |
| 0U, // FCVTZS_ZPmZ_StoD_UNDEF |
| 0U, // FCVTZS_ZPmZ_StoS_UNDEF |
| 0U, // FCVTZU_ZPmZ_DtoD_UNDEF |
| 0U, // FCVTZU_ZPmZ_DtoS_UNDEF |
| 0U, // FCVTZU_ZPmZ_HtoD_UNDEF |
| 0U, // FCVTZU_ZPmZ_HtoH_UNDEF |
| 0U, // FCVTZU_ZPmZ_HtoS_UNDEF |
| 0U, // FCVTZU_ZPmZ_StoD_UNDEF |
| 0U, // FCVTZU_ZPmZ_StoS_UNDEF |
| 0U, // FCVT_ZPmZ_DtoH_UNDEF |
| 0U, // FCVT_ZPmZ_DtoS_UNDEF |
| 0U, // FCVT_ZPmZ_HtoD_UNDEF |
| 0U, // FCVT_ZPmZ_HtoS_UNDEF |
| 0U, // FCVT_ZPmZ_StoD_UNDEF |
| 0U, // FCVT_ZPmZ_StoH_UNDEF |
| 0U, // FDIVR_ZPZZ_ZERO_D |
| 0U, // FDIVR_ZPZZ_ZERO_H |
| 0U, // FDIVR_ZPZZ_ZERO_S |
| 0U, // FDIV_ZPZZ_UNDEF_D |
| 0U, // FDIV_ZPZZ_UNDEF_H |
| 0U, // FDIV_ZPZZ_UNDEF_S |
| 0U, // FDIV_ZPZZ_ZERO_D |
| 0U, // FDIV_ZPZZ_ZERO_H |
| 0U, // FDIV_ZPZZ_ZERO_S |
| 0U, // FDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 0U, // FDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 0U, // FDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 0U, // FDOT_VG4_M4ZZI_HtoS_PSEUDO |
| 0U, // FMAXNM_ZPZI_UNDEF_D |
| 0U, // FMAXNM_ZPZI_UNDEF_H |
| 0U, // FMAXNM_ZPZI_UNDEF_S |
| 0U, // FMAXNM_ZPZI_ZERO_D |
| 0U, // FMAXNM_ZPZI_ZERO_H |
| 0U, // FMAXNM_ZPZI_ZERO_S |
| 0U, // FMAXNM_ZPZZ_UNDEF_D |
| 0U, // FMAXNM_ZPZZ_UNDEF_H |
| 0U, // FMAXNM_ZPZZ_UNDEF_S |
| 0U, // FMAXNM_ZPZZ_ZERO_D |
| 0U, // FMAXNM_ZPZZ_ZERO_H |
| 0U, // FMAXNM_ZPZZ_ZERO_S |
| 0U, // FMAX_ZPZI_UNDEF_D |
| 0U, // FMAX_ZPZI_UNDEF_H |
| 0U, // FMAX_ZPZI_UNDEF_S |
| 0U, // FMAX_ZPZI_ZERO_D |
| 0U, // FMAX_ZPZI_ZERO_H |
| 0U, // FMAX_ZPZI_ZERO_S |
| 0U, // FMAX_ZPZZ_UNDEF_D |
| 0U, // FMAX_ZPZZ_UNDEF_H |
| 0U, // FMAX_ZPZZ_UNDEF_S |
| 0U, // FMAX_ZPZZ_ZERO_D |
| 0U, // FMAX_ZPZZ_ZERO_H |
| 0U, // FMAX_ZPZZ_ZERO_S |
| 0U, // FMINNM_ZPZI_UNDEF_D |
| 0U, // FMINNM_ZPZI_UNDEF_H |
| 0U, // FMINNM_ZPZI_UNDEF_S |
| 0U, // FMINNM_ZPZI_ZERO_D |
| 0U, // FMINNM_ZPZI_ZERO_H |
| 0U, // FMINNM_ZPZI_ZERO_S |
| 0U, // FMINNM_ZPZZ_UNDEF_D |
| 0U, // FMINNM_ZPZZ_UNDEF_H |
| 0U, // FMINNM_ZPZZ_UNDEF_S |
| 0U, // FMINNM_ZPZZ_ZERO_D |
| 0U, // FMINNM_ZPZZ_ZERO_H |
| 0U, // FMINNM_ZPZZ_ZERO_S |
| 0U, // FMIN_ZPZI_UNDEF_D |
| 0U, // FMIN_ZPZI_UNDEF_H |
| 0U, // FMIN_ZPZI_UNDEF_S |
| 0U, // FMIN_ZPZI_ZERO_D |
| 0U, // FMIN_ZPZI_ZERO_H |
| 0U, // FMIN_ZPZI_ZERO_S |
| 0U, // FMIN_ZPZZ_UNDEF_D |
| 0U, // FMIN_ZPZZ_UNDEF_H |
| 0U, // FMIN_ZPZZ_UNDEF_S |
| 0U, // FMIN_ZPZZ_ZERO_D |
| 0U, // FMIN_ZPZZ_ZERO_H |
| 0U, // FMIN_ZPZZ_ZERO_S |
| 0U, // FMLAL_MZZI_S_PSEUDO |
| 0U, // FMLAL_MZZ_S_PSEUDO |
| 0U, // FMLAL_VG2_M2Z2Z_S_PSEUDO |
| 0U, // FMLAL_VG2_M2ZZI_S_PSEUDO |
| 0U, // FMLAL_VG2_M2ZZ_S_PSEUDO |
| 0U, // FMLAL_VG4_M4Z4Z_S_PSEUDO |
| 0U, // FMLAL_VG4_M4ZZI_S_PSEUDO |
| 0U, // FMLAL_VG4_M4ZZ_S_PSEUDO |
| 0U, // FMLA_VG2_M2Z2Z_D_PSEUDO |
| 0U, // FMLA_VG2_M2Z2Z_S_PSEUDO |
| 0U, // FMLA_VG2_M2Z4Z_H_PSEUDO |
| 0U, // FMLA_VG2_M2ZZI_D_PSEUDO |
| 0U, // FMLA_VG2_M2ZZI_S_PSEUDO |
| 0U, // FMLA_VG2_M2ZZ_D_PSEUDO |
| 0U, // FMLA_VG2_M2ZZ_S_PSEUDO |
| 0U, // FMLA_VG4_M4Z4Z_D_PSEUDO |
| 0U, // FMLA_VG4_M4Z4Z_H_PSEUDO |
| 0U, // FMLA_VG4_M4Z4Z_S_PSEUDO |
| 0U, // FMLA_VG4_M4ZZI_D_PSEUDO |
| 0U, // FMLA_VG4_M4ZZI_S_PSEUDO |
| 0U, // FMLA_VG4_M4ZZ_D_PSEUDO |
| 0U, // FMLA_VG4_M4ZZ_S_PSEUDO |
| 0U, // FMLA_ZPZZZ_UNDEF_D |
| 0U, // FMLA_ZPZZZ_UNDEF_H |
| 0U, // FMLA_ZPZZZ_UNDEF_S |
| 0U, // FMLSL_MZZI_S_PSEUDO |
| 0U, // FMLSL_MZZ_S_PSEUDO |
| 0U, // FMLSL_VG2_M2Z2Z_S_PSEUDO |
| 0U, // FMLSL_VG2_M2ZZI_S_PSEUDO |
| 0U, // FMLSL_VG2_M2ZZ_S_PSEUDO |
| 0U, // FMLSL_VG4_M4Z4Z_S_PSEUDO |
| 0U, // FMLSL_VG4_M4ZZI_S_PSEUDO |
| 0U, // FMLSL_VG4_M4ZZ_S_PSEUDO |
| 0U, // FMLS_VG2_M2Z2Z_D_PSEUDO |
| 0U, // FMLS_VG2_M2Z2Z_H_PSEUDO |
| 0U, // FMLS_VG2_M2Z2Z_S_PSEUDO |
| 0U, // FMLS_VG2_M2ZZI_D_PSEUDO |
| 0U, // FMLS_VG2_M2ZZI_S_PSEUDO |
| 0U, // FMLS_VG2_M2ZZ_D_PSEUDO |
| 0U, // FMLS_VG2_M2ZZ_S_PSEUDO |
| 0U, // FMLS_VG4_M4Z2Z_H_PSEUDO |
| 0U, // FMLS_VG4_M4Z4Z_D_PSEUDO |
| 0U, // FMLS_VG4_M4Z4Z_S_PSEUDO |
| 0U, // FMLS_VG4_M4ZZI_D_PSEUDO |
| 0U, // FMLS_VG4_M4ZZI_S_PSEUDO |
| 0U, // FMLS_VG4_M4ZZ_D_PSEUDO |
| 0U, // FMLS_VG4_M4ZZ_S_PSEUDO |
| 0U, // FMLS_ZPZZZ_UNDEF_D |
| 0U, // FMLS_ZPZZZ_UNDEF_H |
| 0U, // FMLS_ZPZZZ_UNDEF_S |
| 0U, // FMOPAL_MPPZZ_PSEUDO |
| 0U, // FMOPA_MPPZZ_D_PSEUDO |
| 0U, // FMOPA_MPPZZ_S_PSEUDO |
| 0U, // FMOPSL_MPPZZ_PSEUDO |
| 0U, // FMOPS_MPPZZ_D_PSEUDO |
| 0U, // FMOPS_MPPZZ_S_PSEUDO |
| 0U, // FMOVD0 |
| 0U, // FMOVH0 |
| 0U, // FMOVS0 |
| 0U, // FMULX_ZPZZ_ZERO_D |
| 0U, // FMULX_ZPZZ_ZERO_H |
| 0U, // FMULX_ZPZZ_ZERO_S |
| 0U, // FMUL_ZPZI_UNDEF_D |
| 0U, // FMUL_ZPZI_UNDEF_H |
| 0U, // FMUL_ZPZI_UNDEF_S |
| 0U, // FMUL_ZPZI_ZERO_D |
| 0U, // FMUL_ZPZI_ZERO_H |
| 0U, // FMUL_ZPZI_ZERO_S |
| 0U, // FMUL_ZPZZ_UNDEF_D |
| 0U, // FMUL_ZPZZ_UNDEF_H |
| 0U, // FMUL_ZPZZ_UNDEF_S |
| 0U, // FMUL_ZPZZ_ZERO_D |
| 0U, // FMUL_ZPZZ_ZERO_H |
| 0U, // FMUL_ZPZZ_ZERO_S |
| 0U, // FNEG_ZPmZ_UNDEF_D |
| 0U, // FNEG_ZPmZ_UNDEF_H |
| 0U, // FNEG_ZPmZ_UNDEF_S |
| 0U, // FNMLA_ZPZZZ_UNDEF_D |
| 0U, // FNMLA_ZPZZZ_UNDEF_H |
| 0U, // FNMLA_ZPZZZ_UNDEF_S |
| 0U, // FNMLS_ZPZZZ_UNDEF_D |
| 0U, // FNMLS_ZPZZZ_UNDEF_H |
| 0U, // FNMLS_ZPZZZ_UNDEF_S |
| 0U, // FRECPX_ZPmZ_UNDEF_D |
| 0U, // FRECPX_ZPmZ_UNDEF_H |
| 0U, // FRECPX_ZPmZ_UNDEF_S |
| 0U, // FRINTA_ZPmZ_UNDEF_D |
| 0U, // FRINTA_ZPmZ_UNDEF_H |
| 0U, // FRINTA_ZPmZ_UNDEF_S |
| 0U, // FRINTI_ZPmZ_UNDEF_D |
| 0U, // FRINTI_ZPmZ_UNDEF_H |
| 0U, // FRINTI_ZPmZ_UNDEF_S |
| 0U, // FRINTM_ZPmZ_UNDEF_D |
| 0U, // FRINTM_ZPmZ_UNDEF_H |
| 0U, // FRINTM_ZPmZ_UNDEF_S |
| 0U, // FRINTN_ZPmZ_UNDEF_D |
| 0U, // FRINTN_ZPmZ_UNDEF_H |
| 0U, // FRINTN_ZPmZ_UNDEF_S |
| 0U, // FRINTP_ZPmZ_UNDEF_D |
| 0U, // FRINTP_ZPmZ_UNDEF_H |
| 0U, // FRINTP_ZPmZ_UNDEF_S |
| 0U, // FRINTX_ZPmZ_UNDEF_D |
| 0U, // FRINTX_ZPmZ_UNDEF_H |
| 0U, // FRINTX_ZPmZ_UNDEF_S |
| 0U, // FRINTZ_ZPmZ_UNDEF_D |
| 0U, // FRINTZ_ZPmZ_UNDEF_H |
| 0U, // FRINTZ_ZPmZ_UNDEF_S |
| 0U, // FSQRT_ZPmZ_UNDEF_D |
| 0U, // FSQRT_ZPmZ_UNDEF_H |
| 0U, // FSQRT_ZPmZ_UNDEF_S |
| 0U, // FSUBR_ZPZI_UNDEF_D |
| 0U, // FSUBR_ZPZI_UNDEF_H |
| 0U, // FSUBR_ZPZI_UNDEF_S |
| 0U, // FSUBR_ZPZI_ZERO_D |
| 0U, // FSUBR_ZPZI_ZERO_H |
| 0U, // FSUBR_ZPZI_ZERO_S |
| 0U, // FSUBR_ZPZZ_ZERO_D |
| 0U, // FSUBR_ZPZZ_ZERO_H |
| 0U, // FSUBR_ZPZZ_ZERO_S |
| 0U, // FSUB_ZPZI_UNDEF_D |
| 0U, // FSUB_ZPZI_UNDEF_H |
| 0U, // FSUB_ZPZI_UNDEF_S |
| 0U, // FSUB_ZPZI_ZERO_D |
| 0U, // FSUB_ZPZI_ZERO_H |
| 0U, // FSUB_ZPZI_ZERO_S |
| 0U, // FSUB_ZPZZ_UNDEF_D |
| 0U, // FSUB_ZPZZ_UNDEF_H |
| 0U, // FSUB_ZPZZ_UNDEF_S |
| 0U, // FSUB_ZPZZ_ZERO_D |
| 0U, // FSUB_ZPZZ_ZERO_H |
| 0U, // FSUB_ZPZZ_ZERO_S |
| 0U, // FVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 0U, // GLD1B_D |
| 0U, // GLD1B_D_IMM |
| 0U, // GLD1B_D_SXTW |
| 0U, // GLD1B_D_UXTW |
| 0U, // GLD1B_S_IMM |
| 0U, // GLD1B_S_SXTW |
| 0U, // GLD1B_S_UXTW |
| 0U, // GLD1D |
| 0U, // GLD1D_IMM |
| 0U, // GLD1D_SCALED |
| 0U, // GLD1D_SXTW |
| 0U, // GLD1D_SXTW_SCALED |
| 0U, // GLD1D_UXTW |
| 0U, // GLD1D_UXTW_SCALED |
| 0U, // GLD1H_D |
| 0U, // GLD1H_D_IMM |
| 0U, // GLD1H_D_SCALED |
| 0U, // GLD1H_D_SXTW |
| 0U, // GLD1H_D_SXTW_SCALED |
| 0U, // GLD1H_D_UXTW |
| 0U, // GLD1H_D_UXTW_SCALED |
| 0U, // GLD1H_S_IMM |
| 0U, // GLD1H_S_SXTW |
| 0U, // GLD1H_S_SXTW_SCALED |
| 0U, // GLD1H_S_UXTW |
| 0U, // GLD1H_S_UXTW_SCALED |
| 0U, // GLD1SB_D |
| 0U, // GLD1SB_D_IMM |
| 0U, // GLD1SB_D_SXTW |
| 0U, // GLD1SB_D_UXTW |
| 0U, // GLD1SB_S_IMM |
| 0U, // GLD1SB_S_SXTW |
| 0U, // GLD1SB_S_UXTW |
| 0U, // GLD1SH_D |
| 0U, // GLD1SH_D_IMM |
| 0U, // GLD1SH_D_SCALED |
| 0U, // GLD1SH_D_SXTW |
| 0U, // GLD1SH_D_SXTW_SCALED |
| 0U, // GLD1SH_D_UXTW |
| 0U, // GLD1SH_D_UXTW_SCALED |
| 0U, // GLD1SH_S_IMM |
| 0U, // GLD1SH_S_SXTW |
| 0U, // GLD1SH_S_SXTW_SCALED |
| 0U, // GLD1SH_S_UXTW |
| 0U, // GLD1SH_S_UXTW_SCALED |
| 0U, // GLD1SW_D |
| 0U, // GLD1SW_D_IMM |
| 0U, // GLD1SW_D_SCALED |
| 0U, // GLD1SW_D_SXTW |
| 0U, // GLD1SW_D_SXTW_SCALED |
| 0U, // GLD1SW_D_UXTW |
| 0U, // GLD1SW_D_UXTW_SCALED |
| 0U, // GLD1W_D |
| 0U, // GLD1W_D_IMM |
| 0U, // GLD1W_D_SCALED |
| 0U, // GLD1W_D_SXTW |
| 0U, // GLD1W_D_SXTW_SCALED |
| 0U, // GLD1W_D_UXTW |
| 0U, // GLD1W_D_UXTW_SCALED |
| 0U, // GLD1W_IMM |
| 0U, // GLD1W_SXTW |
| 0U, // GLD1W_SXTW_SCALED |
| 0U, // GLD1W_UXTW |
| 0U, // GLD1W_UXTW_SCALED |
| 0U, // GLDFF1B_D |
| 0U, // GLDFF1B_D_IMM |
| 0U, // GLDFF1B_D_SXTW |
| 0U, // GLDFF1B_D_UXTW |
| 0U, // GLDFF1B_S_IMM |
| 0U, // GLDFF1B_S_SXTW |
| 0U, // GLDFF1B_S_UXTW |
| 0U, // GLDFF1D |
| 0U, // GLDFF1D_IMM |
| 0U, // GLDFF1D_SCALED |
| 0U, // GLDFF1D_SXTW |
| 0U, // GLDFF1D_SXTW_SCALED |
| 0U, // GLDFF1D_UXTW |
| 0U, // GLDFF1D_UXTW_SCALED |
| 0U, // GLDFF1H_D |
| 0U, // GLDFF1H_D_IMM |
| 0U, // GLDFF1H_D_SCALED |
| 0U, // GLDFF1H_D_SXTW |
| 0U, // GLDFF1H_D_SXTW_SCALED |
| 0U, // GLDFF1H_D_UXTW |
| 0U, // GLDFF1H_D_UXTW_SCALED |
| 0U, // GLDFF1H_S_IMM |
| 0U, // GLDFF1H_S_SXTW |
| 0U, // GLDFF1H_S_SXTW_SCALED |
| 0U, // GLDFF1H_S_UXTW |
| 0U, // GLDFF1H_S_UXTW_SCALED |
| 0U, // GLDFF1SB_D |
| 0U, // GLDFF1SB_D_IMM |
| 0U, // GLDFF1SB_D_SXTW |
| 0U, // GLDFF1SB_D_UXTW |
| 0U, // GLDFF1SB_S_IMM |
| 0U, // GLDFF1SB_S_SXTW |
| 0U, // GLDFF1SB_S_UXTW |
| 0U, // GLDFF1SH_D |
| 0U, // GLDFF1SH_D_IMM |
| 0U, // GLDFF1SH_D_SCALED |
| 0U, // GLDFF1SH_D_SXTW |
| 0U, // GLDFF1SH_D_SXTW_SCALED |
| 0U, // GLDFF1SH_D_UXTW |
| 0U, // GLDFF1SH_D_UXTW_SCALED |
| 0U, // GLDFF1SH_S_IMM |
| 0U, // GLDFF1SH_S_SXTW |
| 0U, // GLDFF1SH_S_SXTW_SCALED |
| 0U, // GLDFF1SH_S_UXTW |
| 0U, // GLDFF1SH_S_UXTW_SCALED |
| 0U, // GLDFF1SW_D |
| 0U, // GLDFF1SW_D_IMM |
| 0U, // GLDFF1SW_D_SCALED |
| 0U, // GLDFF1SW_D_SXTW |
| 0U, // GLDFF1SW_D_SXTW_SCALED |
| 0U, // GLDFF1SW_D_UXTW |
| 0U, // GLDFF1SW_D_UXTW_SCALED |
| 0U, // GLDFF1W_D |
| 0U, // GLDFF1W_D_IMM |
| 0U, // GLDFF1W_D_SCALED |
| 0U, // GLDFF1W_D_SXTW |
| 0U, // GLDFF1W_D_SXTW_SCALED |
| 0U, // GLDFF1W_D_UXTW |
| 0U, // GLDFF1W_D_UXTW_SCALED |
| 0U, // GLDFF1W_IMM |
| 0U, // GLDFF1W_SXTW |
| 0U, // GLDFF1W_SXTW_SCALED |
| 0U, // GLDFF1W_UXTW |
| 0U, // GLDFF1W_UXTW_SCALED |
| 0U, // G_ADD_LOW |
| 0U, // G_BIT |
| 0U, // G_DUP |
| 0U, // G_DUPLANE16 |
| 0U, // G_DUPLANE32 |
| 0U, // G_DUPLANE64 |
| 0U, // G_DUPLANE8 |
| 0U, // G_EXT |
| 0U, // G_FCMEQ |
| 0U, // G_FCMEQZ |
| 0U, // G_FCMGE |
| 0U, // G_FCMGEZ |
| 0U, // G_FCMGT |
| 0U, // G_FCMGTZ |
| 0U, // G_FCMLEZ |
| 0U, // G_FCMLTZ |
| 0U, // G_PREFETCH |
| 0U, // G_REV16 |
| 0U, // G_REV32 |
| 0U, // G_REV64 |
| 0U, // G_SITOF |
| 0U, // G_TRN1 |
| 0U, // G_TRN2 |
| 0U, // G_UITOF |
| 0U, // G_UZP1 |
| 0U, // G_UZP2 |
| 0U, // G_VASHR |
| 0U, // G_VLSHR |
| 0U, // G_ZIP1 |
| 0U, // G_ZIP2 |
| 0U, // HOM_Epilog |
| 0U, // HOM_Prolog |
| 0U, // HWASAN_CHECK_MEMACCESS |
| 0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES |
| 0U, // INSERT_MXIPZ_H_PSEUDO_B |
| 0U, // INSERT_MXIPZ_H_PSEUDO_D |
| 0U, // INSERT_MXIPZ_H_PSEUDO_H |
| 0U, // INSERT_MXIPZ_H_PSEUDO_Q |
| 0U, // INSERT_MXIPZ_H_PSEUDO_S |
| 0U, // INSERT_MXIPZ_V_PSEUDO_B |
| 0U, // INSERT_MXIPZ_V_PSEUDO_D |
| 0U, // INSERT_MXIPZ_V_PSEUDO_H |
| 0U, // INSERT_MXIPZ_V_PSEUDO_Q |
| 0U, // INSERT_MXIPZ_V_PSEUDO_S |
| 0U, // IRGstack |
| 0U, // JumpTableDest16 |
| 0U, // JumpTableDest32 |
| 0U, // JumpTableDest8 |
| 0U, // KCFI_CHECK |
| 0U, // LD1B_D_IMM |
| 0U, // LD1B_H_IMM |
| 0U, // LD1B_IMM |
| 0U, // LD1B_S_IMM |
| 0U, // LD1D_IMM |
| 0U, // LD1H_D_IMM |
| 0U, // LD1H_IMM |
| 0U, // LD1H_S_IMM |
| 0U, // LD1SB_D_IMM |
| 0U, // LD1SB_H_IMM |
| 0U, // LD1SB_S_IMM |
| 0U, // LD1SH_D_IMM |
| 0U, // LD1SH_S_IMM |
| 0U, // LD1SW_D_IMM |
| 0U, // LD1W_D_IMM |
| 0U, // LD1W_IMM |
| 0U, // LD1_MXIPXX_H_PSEUDO_B |
| 0U, // LD1_MXIPXX_H_PSEUDO_D |
| 0U, // LD1_MXIPXX_H_PSEUDO_H |
| 0U, // LD1_MXIPXX_H_PSEUDO_Q |
| 0U, // LD1_MXIPXX_H_PSEUDO_S |
| 0U, // LD1_MXIPXX_V_PSEUDO_B |
| 0U, // LD1_MXIPXX_V_PSEUDO_D |
| 0U, // LD1_MXIPXX_V_PSEUDO_H |
| 0U, // LD1_MXIPXX_V_PSEUDO_Q |
| 0U, // LD1_MXIPXX_V_PSEUDO_S |
| 0U, // LDFF1B |
| 0U, // LDFF1B_D |
| 0U, // LDFF1B_H |
| 0U, // LDFF1B_S |
| 0U, // LDFF1D |
| 0U, // LDFF1H |
| 0U, // LDFF1H_D |
| 0U, // LDFF1H_S |
| 0U, // LDFF1SB_D |
| 0U, // LDFF1SB_H |
| 0U, // LDFF1SB_S |
| 0U, // LDFF1SH_D |
| 0U, // LDFF1SH_S |
| 0U, // LDFF1SW_D |
| 0U, // LDFF1W |
| 0U, // LDFF1W_D |
| 0U, // LDNF1B_D_IMM |
| 0U, // LDNF1B_H_IMM |
| 0U, // LDNF1B_IMM |
| 0U, // LDNF1B_S_IMM |
| 0U, // LDNF1D_IMM |
| 0U, // LDNF1H_D_IMM |
| 0U, // LDNF1H_IMM |
| 0U, // LDNF1H_S_IMM |
| 0U, // LDNF1SB_D_IMM |
| 0U, // LDNF1SB_H_IMM |
| 0U, // LDNF1SB_S_IMM |
| 0U, // LDNF1SH_D_IMM |
| 0U, // LDNF1SH_S_IMM |
| 0U, // LDNF1SW_D_IMM |
| 0U, // LDNF1W_D_IMM |
| 0U, // LDNF1W_IMM |
| 0U, // LDR_ZA_PSEUDO |
| 0U, // LDR_ZZXI |
| 0U, // LDR_ZZZXI |
| 0U, // LDR_ZZZZXI |
| 0U, // LOADgot |
| 0U, // LSL_ZPZI_UNDEF_B |
| 0U, // LSL_ZPZI_UNDEF_D |
| 0U, // LSL_ZPZI_UNDEF_H |
| 0U, // LSL_ZPZI_UNDEF_S |
| 0U, // LSL_ZPZZ_UNDEF_B |
| 0U, // LSL_ZPZZ_UNDEF_D |
| 0U, // LSL_ZPZZ_UNDEF_H |
| 0U, // LSL_ZPZZ_UNDEF_S |
| 0U, // LSL_ZPZZ_ZERO_B |
| 0U, // LSL_ZPZZ_ZERO_D |
| 0U, // LSL_ZPZZ_ZERO_H |
| 0U, // LSL_ZPZZ_ZERO_S |
| 0U, // LSR_ZPZI_UNDEF_B |
| 0U, // LSR_ZPZI_UNDEF_D |
| 0U, // LSR_ZPZI_UNDEF_H |
| 0U, // LSR_ZPZI_UNDEF_S |
| 0U, // LSR_ZPZZ_UNDEF_B |
| 0U, // LSR_ZPZZ_UNDEF_D |
| 0U, // LSR_ZPZZ_UNDEF_H |
| 0U, // LSR_ZPZZ_UNDEF_S |
| 0U, // LSR_ZPZZ_ZERO_B |
| 0U, // LSR_ZPZZ_ZERO_D |
| 0U, // LSR_ZPZZ_ZERO_H |
| 0U, // LSR_ZPZZ_ZERO_S |
| 0U, // MOPSMemoryCopyPseudo |
| 0U, // MOPSMemoryMovePseudo |
| 0U, // MOPSMemorySetPseudo |
| 0U, // MOPSMemorySetTaggingPseudo |
| 0U, // MOVMCSym |
| 0U, // MOVaddr |
| 0U, // MOVaddrBA |
| 0U, // MOVaddrCP |
| 0U, // MOVaddrEXT |
| 0U, // MOVaddrJT |
| 0U, // MOVaddrTLS |
| 0U, // MOVbaseTLS |
| 0U, // MOVi32imm |
| 0U, // MOVi64imm |
| 0U, // MRS_FPCR |
| 0U, // MSR_FPCR |
| 0U, // MSRpstatePseudo |
| 0U, // MUL_ZPZZ_UNDEF_B |
| 0U, // MUL_ZPZZ_UNDEF_D |
| 0U, // MUL_ZPZZ_UNDEF_H |
| 0U, // MUL_ZPZZ_UNDEF_S |
| 0U, // NEG_ZPmZ_UNDEF_B |
| 0U, // NEG_ZPmZ_UNDEF_D |
| 0U, // NEG_ZPmZ_UNDEF_H |
| 0U, // NEG_ZPmZ_UNDEF_S |
| 0U, // NOT_ZPmZ_UNDEF_B |
| 0U, // NOT_ZPmZ_UNDEF_D |
| 0U, // NOT_ZPmZ_UNDEF_H |
| 0U, // NOT_ZPmZ_UNDEF_S |
| 0U, // OBSCURE_COPY |
| 0U, // ORNWrr |
| 0U, // ORNXrr |
| 0U, // ORRWrr |
| 0U, // ORRXrr |
| 0U, // ORR_ZPZZ_ZERO_B |
| 0U, // ORR_ZPZZ_ZERO_D |
| 0U, // ORR_ZPZZ_ZERO_H |
| 0U, // ORR_ZPZZ_ZERO_S |
| 0U, // PTEST_PP_ANY |
| 0U, // RDFFR_P |
| 0U, // RDFFR_PPz |
| 0U, // RET_ReallyLR |
| 0U, // RestoreZAPseudo |
| 0U, // SABD_ZPZZ_UNDEF_B |
| 0U, // SABD_ZPZZ_UNDEF_D |
| 0U, // SABD_ZPZZ_UNDEF_H |
| 0U, // SABD_ZPZZ_UNDEF_S |
| 0U, // SCVTF_ZPmZ_DtoD_UNDEF |
| 0U, // SCVTF_ZPmZ_DtoH_UNDEF |
| 0U, // SCVTF_ZPmZ_DtoS_UNDEF |
| 0U, // SCVTF_ZPmZ_HtoH_UNDEF |
| 0U, // SCVTF_ZPmZ_StoD_UNDEF |
| 0U, // SCVTF_ZPmZ_StoH_UNDEF |
| 0U, // SCVTF_ZPmZ_StoS_UNDEF |
| 0U, // SDIV_ZPZZ_UNDEF_D |
| 0U, // SDIV_ZPZZ_UNDEF_S |
| 0U, // SDOT_VG2_M2Z2Z_BtoS_PSEUDO |
| 0U, // SDOT_VG2_M2Z2Z_HtoD_PSEUDO |
| 0U, // SDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 0U, // SDOT_VG2_M2ZZI_BToS_PSEUDO |
| 0U, // SDOT_VG2_M2ZZI_HToS_PSEUDO |
| 0U, // SDOT_VG2_M2ZZI_HtoD_PSEUDO |
| 0U, // SDOT_VG4_M4Z4Z_BtoS_PSEUDO |
| 0U, // SDOT_VG4_M4Z4Z_HtoD_PSEUDO |
| 0U, // SDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 0U, // SDOT_VG4_M4ZZI_BToS_PSEUDO |
| 0U, // SDOT_VG4_M4ZZI_HToS_PSEUDO |
| 0U, // SDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 0U, // SEH_AddFP |
| 0U, // SEH_EpilogEnd |
| 0U, // SEH_EpilogStart |
| 0U, // SEH_Nop |
| 0U, // SEH_PACSignLR |
| 0U, // SEH_PrologEnd |
| 0U, // SEH_SaveFPLR |
| 0U, // SEH_SaveFPLR_X |
| 0U, // SEH_SaveFReg |
| 0U, // SEH_SaveFRegP |
| 0U, // SEH_SaveFRegP_X |
| 0U, // SEH_SaveFReg_X |
| 0U, // SEH_SaveReg |
| 0U, // SEH_SaveRegP |
| 0U, // SEH_SaveRegP_X |
| 0U, // SEH_SaveReg_X |
| 0U, // SEH_SetFP |
| 0U, // SEH_StackAlloc |
| 0U, // SMAX_ZPZZ_UNDEF_B |
| 0U, // SMAX_ZPZZ_UNDEF_D |
| 0U, // SMAX_ZPZZ_UNDEF_H |
| 0U, // SMAX_ZPZZ_UNDEF_S |
| 0U, // SMIN_ZPZZ_UNDEF_B |
| 0U, // SMIN_ZPZZ_UNDEF_D |
| 0U, // SMIN_ZPZZ_UNDEF_H |
| 0U, // SMIN_ZPZZ_UNDEF_S |
| 0U, // SMLAL_MZZI_S_PSEUDO |
| 0U, // SMLAL_MZZ_S_PSEUDO |
| 0U, // SMLAL_VG2_M2Z2Z_S_PSEUDO |
| 0U, // SMLAL_VG2_M2ZZI_S_PSEUDO |
| 0U, // SMLAL_VG2_M2ZZ_S_PSEUDO |
| 0U, // SMLAL_VG4_M4Z4Z_S_PSEUDO |
| 0U, // SMLAL_VG4_M4ZZI_S_PSEUDO |
| 0U, // SMLAL_VG4_M4ZZ_S_PSEUDO |
| 0U, // SMLSL_MZZI_S_PSEUDO |
| 0U, // SMLSL_MZZ_S_PSEUDO |
| 0U, // SMLSL_VG2_M2Z2Z_S_PSEUDO |
| 0U, // SMLSL_VG2_M2ZZI_S_PSEUDO |
| 0U, // SMLSL_VG2_M2ZZ_S_PSEUDO |
| 0U, // SMLSL_VG4_M4Z4Z_S_PSEUDO |
| 0U, // SMLSL_VG4_M4ZZI_S_PSEUDO |
| 0U, // SMLSL_VG4_M4ZZ_S_PSEUDO |
| 0U, // SMOPA_MPPZZ_D_PSEUDO |
| 0U, // SMOPA_MPPZZ_S_PSEUDO |
| 0U, // SMOPS_MPPZZ_D_PSEUDO |
| 0U, // SMOPS_MPPZZ_S_PSEUDO |
| 0U, // SMULH_ZPZZ_UNDEF_B |
| 0U, // SMULH_ZPZZ_UNDEF_D |
| 0U, // SMULH_ZPZZ_UNDEF_H |
| 0U, // SMULH_ZPZZ_UNDEF_S |
| 0U, // SPACE |
| 0U, // SQABS_ZPmZ_UNDEF_B |
| 0U, // SQABS_ZPmZ_UNDEF_D |
| 0U, // SQABS_ZPmZ_UNDEF_H |
| 0U, // SQABS_ZPmZ_UNDEF_S |
| 0U, // SQNEG_ZPmZ_UNDEF_B |
| 0U, // SQNEG_ZPmZ_UNDEF_D |
| 0U, // SQNEG_ZPmZ_UNDEF_H |
| 0U, // SQNEG_ZPmZ_UNDEF_S |
| 0U, // SQRSHL_ZPZZ_UNDEF_B |
| 0U, // SQRSHL_ZPZZ_UNDEF_D |
| 0U, // SQRSHL_ZPZZ_UNDEF_H |
| 0U, // SQRSHL_ZPZZ_UNDEF_S |
| 0U, // SQSHLU_ZPZI_ZERO_B |
| 0U, // SQSHLU_ZPZI_ZERO_D |
| 0U, // SQSHLU_ZPZI_ZERO_H |
| 0U, // SQSHLU_ZPZI_ZERO_S |
| 0U, // SQSHL_ZPZI_ZERO_B |
| 0U, // SQSHL_ZPZI_ZERO_D |
| 0U, // SQSHL_ZPZI_ZERO_H |
| 0U, // SQSHL_ZPZI_ZERO_S |
| 0U, // SQSHL_ZPZZ_UNDEF_B |
| 0U, // SQSHL_ZPZZ_UNDEF_D |
| 0U, // SQSHL_ZPZZ_UNDEF_H |
| 0U, // SQSHL_ZPZZ_UNDEF_S |
| 0U, // SRSHL_ZPZZ_UNDEF_B |
| 0U, // SRSHL_ZPZZ_UNDEF_D |
| 0U, // SRSHL_ZPZZ_UNDEF_H |
| 0U, // SRSHL_ZPZZ_UNDEF_S |
| 0U, // SRSHR_ZPZI_ZERO_B |
| 0U, // SRSHR_ZPZI_ZERO_D |
| 0U, // SRSHR_ZPZI_ZERO_H |
| 0U, // SRSHR_ZPZI_ZERO_S |
| 0U, // STGloop |
| 0U, // STGloop_wback |
| 0U, // STR_ZZXI |
| 0U, // STR_ZZZXI |
| 0U, // STR_ZZZZXI |
| 0U, // STZGloop |
| 0U, // STZGloop_wback |
| 0U, // SUBR_ZPZZ_ZERO_B |
| 0U, // SUBR_ZPZZ_ZERO_D |
| 0U, // SUBR_ZPZZ_ZERO_H |
| 0U, // SUBR_ZPZZ_ZERO_S |
| 0U, // SUBSWrr |
| 0U, // SUBSXrr |
| 0U, // SUBWrr |
| 0U, // SUBXrr |
| 0U, // SUB_VG2_M2Z2Z_D_PSEUDO |
| 0U, // SUB_VG2_M2Z2Z_S_PSEUDO |
| 0U, // SUB_VG2_M2ZZ_D_PSEUDO |
| 0U, // SUB_VG2_M2ZZ_S_PSEUDO |
| 0U, // SUB_VG4_M4Z4Z_D_PSEUDO |
| 0U, // SUB_VG4_M4Z4Z_S_PSEUDO |
| 0U, // SUB_VG4_M4ZZ_D_PSEUDO |
| 0U, // SUB_VG4_M4ZZ_S_PSEUDO |
| 0U, // SUB_ZPZZ_ZERO_B |
| 0U, // SUB_ZPZZ_ZERO_D |
| 0U, // SUB_ZPZZ_ZERO_H |
| 0U, // SUB_ZPZZ_ZERO_S |
| 0U, // SUDOT_VG2_M2ZZI_BToS_PSEUDO |
| 0U, // SUDOT_VG4_M4ZZI_BToS_PSEUDO |
| 0U, // SUMOPA_MPPZZ_D_PSEUDO |
| 0U, // SUMOPA_MPPZZ_S_PSEUDO |
| 0U, // SUMOPS_MPPZZ_D_PSEUDO |
| 0U, // SUMOPS_MPPZZ_S_PSEUDO |
| 0U, // SUVDOT_VG4_M4ZZI_BToS_PSEUDO |
| 0U, // SVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 0U, // SVDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 0U, // SVDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 0U, // SXTB_ZPmZ_UNDEF_D |
| 0U, // SXTB_ZPmZ_UNDEF_H |
| 0U, // SXTB_ZPmZ_UNDEF_S |
| 0U, // SXTH_ZPmZ_UNDEF_D |
| 0U, // SXTH_ZPmZ_UNDEF_S |
| 0U, // SXTW_ZPmZ_UNDEF_D |
| 0U, // SpeculationBarrierISBDSBEndBB |
| 0U, // SpeculationBarrierSBEndBB |
| 0U, // SpeculationSafeValueW |
| 0U, // SpeculationSafeValueX |
| 0U, // StoreSwiftAsyncContext |
| 0U, // TAGPstack |
| 0U, // TCRETURNdi |
| 0U, // TCRETURNri |
| 0U, // TCRETURNriALL |
| 0U, // TCRETURNriBTI |
| 51330U, // TLSDESCCALL |
| 0U, // TLSDESC_CALLSEQ |
| 0U, // UABD_ZPZZ_UNDEF_B |
| 0U, // UABD_ZPZZ_UNDEF_D |
| 0U, // UABD_ZPZZ_UNDEF_H |
| 0U, // UABD_ZPZZ_UNDEF_S |
| 0U, // UCVTF_ZPmZ_DtoD_UNDEF |
| 0U, // UCVTF_ZPmZ_DtoH_UNDEF |
| 0U, // UCVTF_ZPmZ_DtoS_UNDEF |
| 0U, // UCVTF_ZPmZ_HtoH_UNDEF |
| 0U, // UCVTF_ZPmZ_StoD_UNDEF |
| 0U, // UCVTF_ZPmZ_StoH_UNDEF |
| 0U, // UCVTF_ZPmZ_StoS_UNDEF |
| 0U, // UDIV_ZPZZ_UNDEF_D |
| 0U, // UDIV_ZPZZ_UNDEF_S |
| 0U, // UDOT_VG2_M2Z2Z_BtoS_PSEUDO |
| 0U, // UDOT_VG2_M2Z2Z_HtoD_PSEUDO |
| 0U, // UDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 0U, // UDOT_VG2_M2ZZI_BToS_PSEUDO |
| 0U, // UDOT_VG2_M2ZZI_HToS_PSEUDO |
| 0U, // UDOT_VG2_M2ZZI_HtoD_PSEUDO |
| 0U, // UDOT_VG4_M4Z4Z_BtoS_PSEUDO |
| 0U, // UDOT_VG4_M4Z4Z_HtoD_PSEUDO |
| 0U, // UDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 0U, // UDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 0U, // UDOT_VG4_M4ZZI_HToS_PSEUDO |
| 0U, // UDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 0U, // UMAX_ZPZZ_UNDEF_B |
| 0U, // UMAX_ZPZZ_UNDEF_D |
| 0U, // UMAX_ZPZZ_UNDEF_H |
| 0U, // UMAX_ZPZZ_UNDEF_S |
| 0U, // UMIN_ZPZZ_UNDEF_B |
| 0U, // UMIN_ZPZZ_UNDEF_D |
| 0U, // UMIN_ZPZZ_UNDEF_H |
| 0U, // UMIN_ZPZZ_UNDEF_S |
| 0U, // UMLAL_MZZI_S_PSEUDO |
| 0U, // UMLAL_MZZ_S_PSEUDO |
| 0U, // UMLAL_VG2_M2Z2Z_S_PSEUDO |
| 0U, // UMLAL_VG2_M2ZZI_S_PSEUDO |
| 0U, // UMLAL_VG2_M2ZZ_S_PSEUDO |
| 0U, // UMLAL_VG4_M4Z4Z_S_PSEUDO |
| 0U, // UMLAL_VG4_M4ZZI_S_PSEUDO |
| 0U, // UMLAL_VG4_M4ZZ_S_PSEUDO |
| 0U, // UMLSL_MZZI_S_PSEUDO |
| 0U, // UMLSL_MZZ_S_PSEUDO |
| 0U, // UMLSL_VG2_M2Z2Z_S_PSEUDO |
| 0U, // UMLSL_VG2_M2ZZI_S_PSEUDO |
| 0U, // UMLSL_VG2_M2ZZ_S_PSEUDO |
| 0U, // UMLSL_VG4_M4Z4Z_S_PSEUDO |
| 0U, // UMLSL_VG4_M4ZZI_S_PSEUDO |
| 0U, // UMLSL_VG4_M4ZZ_S_PSEUDO |
| 0U, // UMOPA_MPPZZ_D_PSEUDO |
| 0U, // UMOPA_MPPZZ_S_PSEUDO |
| 0U, // UMOPS_MPPZZ_D_PSEUDO |
| 0U, // UMOPS_MPPZZ_S_PSEUDO |
| 0U, // UMULH_ZPZZ_UNDEF_B |
| 0U, // UMULH_ZPZZ_UNDEF_D |
| 0U, // UMULH_ZPZZ_UNDEF_H |
| 0U, // UMULH_ZPZZ_UNDEF_S |
| 0U, // UQRSHL_ZPZZ_UNDEF_B |
| 0U, // UQRSHL_ZPZZ_UNDEF_D |
| 0U, // UQRSHL_ZPZZ_UNDEF_H |
| 0U, // UQRSHL_ZPZZ_UNDEF_S |
| 0U, // UQSHL_ZPZI_ZERO_B |
| 0U, // UQSHL_ZPZI_ZERO_D |
| 0U, // UQSHL_ZPZI_ZERO_H |
| 0U, // UQSHL_ZPZI_ZERO_S |
| 0U, // UQSHL_ZPZZ_UNDEF_B |
| 0U, // UQSHL_ZPZZ_UNDEF_D |
| 0U, // UQSHL_ZPZZ_UNDEF_H |
| 0U, // UQSHL_ZPZZ_UNDEF_S |
| 0U, // URECPE_ZPmZ_UNDEF_S |
| 0U, // URSHL_ZPZZ_UNDEF_B |
| 0U, // URSHL_ZPZZ_UNDEF_D |
| 0U, // URSHL_ZPZZ_UNDEF_H |
| 0U, // URSHL_ZPZZ_UNDEF_S |
| 0U, // URSHR_ZPZI_ZERO_B |
| 0U, // URSHR_ZPZI_ZERO_D |
| 0U, // URSHR_ZPZI_ZERO_H |
| 0U, // URSHR_ZPZI_ZERO_S |
| 0U, // URSQRTE_ZPmZ_UNDEF_S |
| 0U, // USDOT_VG2_M2Z2Z_BToS_PSEUDO |
| 0U, // USDOT_VG2_M2ZZI_BToS_PSEUDO |
| 0U, // USDOT_VG4_M4Z4Z_BToS_PSEUDO |
| 0U, // USDOT_VG4_M4ZZI_BToS_PSEUDO |
| 0U, // USMOPA_MPPZZ_D_PSEUDO |
| 0U, // USMOPA_MPPZZ_S_PSEUDO |
| 0U, // USMOPS_MPPZZ_D_PSEUDO |
| 0U, // USMOPS_MPPZZ_S_PSEUDO |
| 0U, // USVDOT_VG4_M4ZZI_BToS_PSEUDO |
| 0U, // UVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 0U, // UVDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 0U, // UVDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 0U, // UXTB_ZPmZ_UNDEF_D |
| 0U, // UXTB_ZPmZ_UNDEF_H |
| 0U, // UXTB_ZPmZ_UNDEF_S |
| 0U, // UXTH_ZPmZ_UNDEF_D |
| 0U, // UXTH_ZPmZ_UNDEF_S |
| 0U, // UXTW_ZPmZ_UNDEF_D |
| 0U, // ZERO_M_PSEUDO |
| 4243853U, // ABSWr |
| 4243853U, // ABSXr |
| 541147533U, // ABS_ZPmZ_B |
| 541180301U, // ABS_ZPmZ_D |
| 1082278285U, // ABS_ZPmZ_H |
| 541245837U, // ABS_ZPmZ_S |
| 1615005375U, // ABSv16i8 |
| 4243853U, // ABSv1i64 |
| 1615017778U, // ABSv2i32 |
| 1615009102U, // ABSv2i64 |
| 1615011313U, // ABSv4i16 |
| 1615019857U, // ABSv4i32 |
| 1615013209U, // ABSv8i16 |
| 1615006334U, // ABSv8i8 |
| 2151779524U, // ADCLB_ZZZ_D |
| 2688715972U, // ADCLB_ZZZ_S |
| 2151793531U, // ADCLT_ZZZ_D |
| 2688729979U, // ADCLT_ZZZ_S |
| 4243892U, // ADCSWr |
| 4243892U, // ADCSXr |
| 4231158U, // ADCWr |
| 4231158U, // ADCXr |
| 4233364U, // ADDG |
| 3234038057U, // ADDHA_MPPZ_D |
| 3238232361U, // ADDHA_MPPZ_S |
| 3762359721U, // ADDHNB_ZZZ_B |
| 21106089U, // ADDHNB_ZZZ_H |
| 541232553U, // ADDHNB_ZZZ_S |
| 1078019118U, // ADDHNT_ZZZ_B |
| 25314350U, // ADDHNT_ZZZ_H |
| 2151859246U, // ADDHNT_ZZZ_S |
| 1615017403U, // ADDHNv2i64_v2i32 |
| 1615084023U, // ADDHNv2i64_v4i32 |
| 1615010927U, // ADDHNv4i32_v4i16 |
| 1615077525U, // ADDHNv4i32_v8i16 |
| 1615070102U, // ADDHNv8i16_v16i8 |
| 1615006074U, // ADDHNv8i16_v8i8 |
| 4238431U, // ADDPL_XXI |
| 2151755549U, // ADDP_ZPmZ_B |
| 2151788317U, // ADDP_ZPmZ_D |
| 2713857821U, // ADDP_ZPmZ_H |
| 2151853853U, // ADDP_ZPmZ_S |
| 1615005240U, // ADDPv16i8 |
| 1615017554U, // ADDPv2i32 |
| 1615008918U, // ADDPv2i64 |
| 1614845078U, // ADDPv2i64p |
| 1615011089U, // ADDPv4i16 |
| 1615019633U, // ADDPv4i32 |
| 1615012985U, // ADDPv8i16 |
| 1615006212U, // ADDPv8i8 |
| 2181252619U, // ADDQV_VPZ_B |
| 2185446923U, // ADDQV_VPZ_D |
| 2189641227U, // ADDQV_VPZ_H |
| 2193835531U, // ADDQV_VPZ_S |
| 4238510U, // ADDSPL_XXI |
| 4238739U, // ADDSVL_XXI |
| 4243904U, // ADDSWri |
| 4243904U, // ADDSWrs |
| 4243904U, // ADDSWrx |
| 4243904U, // ADDSXri |
| 4243904U, // ADDSXrs |
| 4243904U, // ADDSXrx |
| 4243904U, // ADDSXrx64 |
| 3234038435U, // ADDVA_MPPZ_D |
| 3238232739U, // ADDVA_MPPZ_S |
| 4238726U, // ADDVL_XXI |
| 1614841652U, // ADDVv16i8v |
| 1614847700U, // ADDVv4i16v |
| 1614856244U, // ADDVv4i32v |
| 1614849596U, // ADDVv8i16v |
| 1614842599U, // ADDVv8i8v |
| 4233011U, // ADDWri |
| 4233011U, // ADDWrs |
| 4233011U, // ADDWrx |
| 4233011U, // ADDXri |
| 4233011U, // ADDXrs |
| 4233011U, // ADDXrx |
| 4233011U, // ADDXrx64 |
| 50632499U, // ADD_VG2_2ZZ_B |
| 54859571U, // ADD_VG2_2ZZ_D |
| 59086643U, // ADD_VG2_2ZZ_H |
| 63313715U, // ADD_VG2_2ZZ_S |
| 3288766259U, // ADD_VG2_M2Z2Z_D |
| 3288799027U, // ADD_VG2_M2Z2Z_S |
| 3288766259U, // ADD_VG2_M2ZZ_D |
| 3288799027U, // ADD_VG2_M2ZZ_S |
| 3288766259U, // ADD_VG2_M2Z_D |
| 3288799027U, // ADD_VG2_M2Z_S |
| 50632499U, // ADD_VG4_4ZZ_B |
| 54859571U, // ADD_VG4_4ZZ_D |
| 59086643U, // ADD_VG4_4ZZ_H |
| 63313715U, // ADD_VG4_4ZZ_S |
| 3825637171U, // ADD_VG4_M4Z4Z_D |
| 3825669939U, // ADD_VG4_M4Z4Z_S |
| 3825637171U, // ADD_VG4_M4ZZ_D |
| 3825669939U, // ADD_VG4_M4ZZ_S |
| 3825637171U, // ADD_VG4_M4Z_D |
| 3825669939U, // ADD_VG4_M4Z_S |
| 4265779U, // ADD_ZI_B |
| 541169459U, // ADD_ZI_D |
| 71440179U, // ADD_ZI_H |
| 541234995U, // ADD_ZI_S |
| 2151749427U, // ADD_ZPmZ_B |
| 2151782195U, // ADD_ZPmZ_D |
| 2713851699U, // ADD_ZPmZ_H |
| 2151847731U, // ADD_ZPmZ_S |
| 4265779U, // ADD_ZZZ_B |
| 541169459U, // ADD_ZZZ_D |
| 71440179U, // ADD_ZZZ_H |
| 541234995U, // ADD_ZZZ_S |
| 1615004930U, // ADDv16i8 |
| 4233011U, // ADDv1i64 |
| 1615016968U, // ADDv2i32 |
| 1615008391U, // ADDv2i64 |
| 1615010515U, // ADDv4i16 |
| 1615018934U, // ADDv4i32 |
| 1615012376U, // ADDv8i16 |
| 1615005826U, // ADDv8i8 |
| 4239682U, // ADR |
| 1077981124U, // ADRP |
| 612479298U, // ADR_LSL_ZZZ_D_0 |
| 612479298U, // ADR_LSL_ZZZ_D_1 |
| 612479298U, // ADR_LSL_ZZZ_D_2 |
| 612479298U, // ADR_LSL_ZZZ_D_3 |
| 612544834U, // ADR_LSL_ZZZ_S_0 |
| 612544834U, // ADR_LSL_ZZZ_S_1 |
| 612544834U, // ADR_LSL_ZZZ_S_2 |
| 612544834U, // ADR_LSL_ZZZ_S_3 |
| 612479298U, // ADR_SXTW_ZZZ_D_0 |
| 612479298U, // ADR_SXTW_ZZZ_D_1 |
| 612479298U, // ADR_SXTW_ZZZ_D_2 |
| 612479298U, // ADR_SXTW_ZZZ_D_3 |
| 612479298U, // ADR_UXTW_ZZZ_D_0 |
| 612479298U, // ADR_UXTW_ZZZ_D_1 |
| 612479298U, // ADR_UXTW_ZZZ_D_2 |
| 612479298U, // ADR_UXTW_ZZZ_D_3 |
| 4265908U, // AESD_ZZZ_B |
| 1615070542U, // AESDrr |
| 4266055U, // AESE_ZZZ_B |
| 1615070572U, // AESErr |
| 4263936U, // AESIMC_ZZ_B |
| 1615004884U, // AESIMCrr |
| 4263944U, // AESMC_ZZ_B |
| 1615004896U, // AESMCrr |
| 2181252626U, // ANDQV_VPZ_B |
| 2185446930U, // ANDQV_VPZ_D |
| 2189641234U, // ANDQV_VPZ_H |
| 2193835538U, // ANDQV_VPZ_S |
| 4243911U, // ANDSWri |
| 4243911U, // ANDSWrs |
| 4243911U, // ANDSXri |
| 4243911U, // ANDSXrs |
| 2151760327U, // ANDS_PPzPP |
| 509363U, // ANDV_VPZ_B |
| 3301459379U, // ANDV_VPZ_D |
| 3305686451U, // ANDV_VPZ_H |
| 3246998963U, // ANDV_VPZ_S |
| 4233106U, // ANDWri |
| 4233106U, // ANDWrs |
| 4233106U, // ANDXri |
| 4233106U, // ANDXrs |
| 2151749522U, // AND_PPzPP |
| 541169554U, // AND_ZI |
| 2151749522U, // AND_ZPmZ_B |
| 2151782290U, // AND_ZPmZ_D |
| 2713851794U, // AND_ZPmZ_H |
| 2151847826U, // AND_ZPmZ_S |
| 541169554U, // AND_ZZZ |
| 1615004997U, // ANDv16i8 |
| 1615005887U, // ANDv8i8 |
| 2151749550U, // ASRD_ZPmI_B |
| 2151782318U, // ASRD_ZPmI_D |
| 2713851822U, // ASRD_ZPmI_H |
| 2151847854U, // ASRD_ZPmI_S |
| 2151756291U, // ASRR_ZPmZ_B |
| 2151789059U, // ASRR_ZPmZ_D |
| 2713858563U, // ASRR_ZPmZ_H |
| 2151854595U, // ASRR_ZPmZ_S |
| 4239893U, // ASRVWr |
| 4239893U, // ASRVXr |
| 2151756309U, // ASR_WIDE_ZPmZ_B |
| 2713858581U, // ASR_WIDE_ZPmZ_H |
| 2151854613U, // ASR_WIDE_ZPmZ_S |
| 4272661U, // ASR_WIDE_ZZZ_B |
| 71447061U, // ASR_WIDE_ZZZ_H |
| 541241877U, // ASR_WIDE_ZZZ_S |
| 2151756309U, // ASR_ZPmI_B |
| 2151789077U, // ASR_ZPmI_D |
| 2713858581U, // ASR_ZPmI_H |
| 2151854613U, // ASR_ZPmI_S |
| 2151756309U, // ASR_ZPmZ_B |
| 2151789077U, // ASR_ZPmZ_D |
| 2713858581U, // ASR_ZPmZ_H |
| 2151854613U, // ASR_ZPmZ_S |
| 4272661U, // ASR_ZZI_B |
| 541176341U, // ASR_ZZI_D |
| 71447061U, // ASR_ZZI_H |
| 541241877U, // ASR_ZZI_S |
| 1615429915U, // AUTDA |
| 1615432686U, // AUTDB |
| 623306U, // AUTDZA |
| 626649U, // AUTDZB |
| 1615429943U, // AUTIA |
| 18766U, // AUTIA1716 |
| 18872U, // AUTIASP |
| 18857U, // AUTIAZ |
| 1615432713U, // AUTIB |
| 18789U, // AUTIB1716 |
| 18757U, // AUTIBSP |
| 18748U, // AUTIBZ |
| 623322U, // AUTIZA |
| 626665U, // AUTIZB |
| 20207U, // AXFLAG |
| 656102U, // B |
| 1615005570U, // BCAX |
| 541181868U, // BCAX_ZZZZ |
| 706746U, // BCcc |
| 4271912U, // BDEP_ZZZ_B |
| 541175592U, // BDEP_ZZZ_D |
| 71446312U, // BDEP_ZZZ_H |
| 541241128U, // BDEP_ZZZ_S |
| 4277570U, // BEXT_ZZZ_B |
| 541181250U, // BEXT_ZZZ_D |
| 71451970U, // BEXT_ZZZ_H |
| 541246786U, // BEXT_ZZZ_S |
| 1615086760U, // BF16DOTlanev4bf16 |
| 1615086760U, // BF16DOTlanev8bf16 |
| 3310032711U, // BFADD_VG2_M2Z_H |
| 3314227015U, // BFADD_VG4_M4Z_H |
| 2713851719U, // BFADD_ZPZmZ |
| 71440199U, // BFADD_ZZZ |
| 84258640U, // BFCLAMP_VG2_2ZZZ_H |
| 84258640U, // BFCLAMP_VG4_4ZZZ_H |
| 84029264U, // BFCLAMP_ZZZ |
| 4244743U, // BFCVT |
| 1615011021U, // BFCVTN |
| 1615077595U, // BFCVTN2 |
| 2156020834U, // BFCVTNT_ZPmZ |
| 3284282982U, // BFCVTN_Z2Z_StoH |
| 3284288775U, // BFCVT_Z2Z_StoH |
| 2156020999U, // BFCVT_ZPmZ |
| 3288810664U, // BFDOT_VG2_M2Z2Z_HtoS |
| 3288810664U, // BFDOT_VG2_M2ZZI_HtoS |
| 3288810664U, // BFDOT_VG2_M2ZZ_HtoS |
| 3825681576U, // BFDOT_VG4_M4Z4Z_HtoS |
| 3825681576U, // BFDOT_VG4_M4ZZI_HtoS |
| 3825681576U, // BFDOT_VG4_M4ZZ_HtoS |
| 1078117544U, // BFDOT_ZZI |
| 1078117544U, // BFDOT_ZZZ |
| 20290U, // BFDOTv4bf16 |
| 20290U, // BFDOTv8bf16 |
| 59092451U, // BFMAXNM_VG2_2Z2Z_H |
| 59092451U, // BFMAXNM_VG2_2ZZ_H |
| 59092451U, // BFMAXNM_VG4_4Z2Z_H |
| 59092451U, // BFMAXNM_VG4_4ZZ_H |
| 2713857507U, // BFMAXNM_ZPZmZ |
| 59099058U, // BFMAX_VG2_2Z2Z_H |
| 59099058U, // BFMAX_VG2_2ZZ_H |
| 59099058U, // BFMAX_VG4_4Z2Z_H |
| 59099058U, // BFMAX_VG4_4ZZ_H |
| 2713864114U, // BFMAX_ZPZmZ |
| 59092442U, // BFMINNM_VG2_2Z2Z_H |
| 59092442U, // BFMINNM_VG2_2ZZ_H |
| 59092442U, // BFMINNM_VG4_4Z2Z_H |
| 59092442U, // BFMINNM_VG4_4ZZ_H |
| 2713857498U, // BFMINNM_ZPZmZ |
| 59092495U, // BFMIN_VG2_2Z2Z_H |
| 59092495U, // BFMIN_VG2_2ZZ_H |
| 59092495U, // BFMIN_VG4_4Z2Z_H |
| 59092495U, // BFMIN_VG4_4ZZ_H |
| 2713857551U, // BFMIN_ZPZmZ |
| 20184U, // BFMLALB |
| 20184U, // BFMLALBIdx |
| 1078103098U, // BFMLALB_ZZZ |
| 1078103098U, // BFMLALB_ZZZI |
| 20282U, // BFMLALT |
| 20282U, // BFMLALTIdx |
| 1078117195U, // BFMLALT_ZZZ |
| 1078117195U, // BFMLALT_ZZZI |
| 2781293186U, // BFMLAL_MZZI_S |
| 2781293186U, // BFMLAL_MZZ_S |
| 3318164098U, // BFMLAL_VG2_M2Z2Z_S |
| 3318164098U, // BFMLAL_VG2_M2ZZI_S |
| 3318164098U, // BFMLAL_VG2_M2ZZ_S |
| 3855035010U, // BFMLAL_VG4_M4Z4Z_S |
| 3855035010U, // BFMLAL_VG4_M4ZZI_S |
| 3855035010U, // BFMLAL_VG4_M4ZZ_S |
| 88801611U, // BFMLA_VG2_M2Z2Z |
| 88801611U, // BFMLA_VG2_M2ZZ |
| 88801611U, // BFMLA_VG2_M2ZZI |
| 92995915U, // BFMLA_VG4_M4Z4Z |
| 92995915U, // BFMLA_VG4_M4ZZ |
| 92995915U, // BFMLA_VG4_M4ZZI |
| 2713846091U, // BFMLA_ZPmZZ |
| 84017483U, // BFMLA_ZZZI |
| 1078103396U, // BFMLSLB_ZZZI_S |
| 1078103396U, // BFMLSLB_ZZZ_S |
| 1078117370U, // BFMLSLT_ZZZI_S |
| 1078117370U, // BFMLSLT_ZZZ_S |
| 2781293868U, // BFMLSL_MZZI_S |
| 2781293868U, // BFMLSL_MZZ_S |
| 3318164780U, // BFMLSL_VG2_M2Z2Z_S |
| 3318164780U, // BFMLSL_VG2_M2ZZI_S |
| 3318164780U, // BFMLSL_VG2_M2ZZ_S |
| 3855035692U, // BFMLSL_VG4_M4Z4Z_S |
| 3855035692U, // BFMLSL_VG4_M4ZZI_S |
| 3855035692U, // BFMLSL_VG4_M4ZZ_S |
| 88818169U, // BFMLS_VG2_M2Z2Z |
| 88818169U, // BFMLS_VG2_M2ZZ |
| 88818169U, // BFMLS_VG2_M2ZZI |
| 93012473U, // BFMLS_VG4_M4Z4Z |
| 93012473U, // BFMLS_VG4_M4ZZ |
| 93012473U, // BFMLS_VG4_M4ZZI |
| 2713862649U, // BFMLS_ZPmZZ |
| 84034041U, // BFMLS_ZZZI |
| 20157U, // BFMMLA |
| 1078100306U, // BFMMLA_ZZZ |
| 100893072U, // BFMOPA_MPPZZ |
| 100893072U, // BFMOPA_MPPZZ_H |
| 100909633U, // BFMOPS_MPPZZ |
| 100909633U, // BFMOPS_MPPZZ_H |
| 2713857386U, // BFMUL_ZPZmZ |
| 71445866U, // BFMUL_ZZZ |
| 71445866U, // BFMUL_ZZZI |
| 1614851509U, // BFMWri |
| 1614851509U, // BFMXri |
| 3310030695U, // BFSUB_VG2_M2Z_H |
| 3314224999U, // BFSUB_VG4_M4Z_H |
| 2713849703U, // BFSUB_ZPZmZ |
| 71438183U, // BFSUB_ZZZ |
| 3288810685U, // BFVDOT_VG2_M2ZZI_HtoS |
| 4272074U, // BGRP_ZZZ_B |
| 541175754U, // BGRP_ZZZ_D |
| 71446474U, // BGRP_ZZZ_H |
| 541241290U, // BGRP_ZZZ_S |
| 4243898U, // BICSWrs |
| 4243898U, // BICSXrs |
| 2151760314U, // BICS_PPzPP |
| 4231163U, // BICWrs |
| 4231163U, // BICXrs |
| 2151747579U, // BIC_PPzPP |
| 2151747579U, // BIC_ZPmZ_B |
| 2151780347U, // BIC_ZPmZ_D |
| 2713849851U, // BIC_ZPmZ_H |
| 2151845883U, // BIC_ZPmZ_S |
| 541167611U, // BIC_ZZZ |
| 1615004875U, // BICv16i8 |
| 3225695203U, // BICv2i32 |
| 3225688750U, // BICv4i16 |
| 3225697169U, // BICv4i32 |
| 3225690611U, // BICv8i16 |
| 1615005797U, // BICv8i8 |
| 1615070582U, // BIFv16i8 |
| 1615071449U, // BIFv8i8 |
| 1615070959U, // BITv16i8 |
| 1615071913U, // BITv8i8 |
| 666528U, // BL |
| 45444U, // BLR |
| 4227314U, // BLRAA |
| 51254U, // BLRAAZ |
| 4230009U, // BLRAB |
| 51276U, // BLRABZ |
| 17006985U, // BMOPA_MPPZZ_S |
| 17023546U, // BMOPS_MPPZZ_S |
| 45342U, // BR |
| 4227301U, // BRAA |
| 51247U, // BRAAZ |
| 4229996U, // BRAB |
| 51269U, // BRABZ |
| 20242U, // BRB_IALL |
| 20214U, // BRB_INJ |
| 764517U, // BRK |
| 2151760245U, // BRKAS_PPzP |
| 541131070U, // BRKA_PPmP |
| 2151743806U, // BRKA_PPzP |
| 2151760281U, // BRKBS_PPzP |
| 541133840U, // BRKB_PPmP |
| 2151746576U, // BRKB_PPzP |
| 2151760406U, // BRKNS_PPzP |
| 2151755302U, // BRKN_PPzP |
| 2151760252U, // BRKPAS_PPzPP |
| 2151743874U, // BRKPA_PPzPP |
| 2151760288U, // BRKPBS_PPzPP |
| 2151747103U, // BRKPB_PPzPP |
| 541175297U, // BSL1N_ZZZZ |
| 541175304U, // BSL2N_ZZZZ |
| 541175070U, // BSL_ZZZZ |
| 1615070728U, // BSLv16i8 |
| 1615071581U, // BSLv8i8 |
| 706743U, // Bcc |
| 4265778U, // CADD_ZZI_B |
| 541169458U, // CADD_ZZI_D |
| 71440178U, // CADD_ZZI_H |
| 541234994U, // CADD_ZZI_S |
| 1615432594U, // CASAB |
| 1615439735U, // CASAH |
| 1615432837U, // CASALB |
| 1615439894U, // CASALH |
| 1615440732U, // CASALW |
| 1615440732U, // CASALX |
| 1615430249U, // CASAW |
| 1615430249U, // CASAX |
| 1615433450U, // CASB |
| 1615440279U, // CASH |
| 1615433043U, // CASLB |
| 1615439988U, // CASLH |
| 1615441166U, // CASLW |
| 1615441166U, // CASLX |
| 797416U, // CASPALW |
| 830184U, // CASPALX |
| 786911U, // CASPAW |
| 819679U, // CASPAX |
| 797853U, // CASPLW |
| 830621U, // CASPLX |
| 798703U, // CASPW |
| 831471U, // CASPX |
| 1615446376U, // CASW |
| 1615446376U, // CASX |
| 3762341987U, // CBNZW |
| 3762341987U, // CBNZX |
| 3762341972U, // CBZW |
| 3762341972U, // CBZX |
| 4238892U, // CCMNWi |
| 4238892U, // CCMNWr |
| 4238892U, // CCMNXi |
| 4238892U, // CCMNXr |
| 4239210U, // CCMPWi |
| 4239210U, // CCMPWr |
| 4239210U, // CCMPXi |
| 4239210U, // CCMPXr |
| 1078052002U, // CDOT_ZZZI_D |
| 4375714U, // CDOT_ZZZI_S |
| 1078052002U, // CDOT_ZZZ_D |
| 4375714U, // CDOT_ZZZ_S |
| 20307U, // CFINV |
| 2151711387U, // CLASTA_RPZ_B |
| 2151711387U, // CLASTA_RPZ_D |
| 2151711387U, // CLASTA_RPZ_H |
| 2151711387U, // CLASTA_RPZ_S |
| 2151711387U, // CLASTA_VPZ_B |
| 2151711387U, // CLASTA_VPZ_D |
| 2151711387U, // CLASTA_VPZ_H |
| 2151711387U, // CLASTA_VPZ_S |
| 2151744155U, // CLASTA_ZPZ_B |
| 2151776923U, // CLASTA_ZPZ_D |
| 29491867U, // CLASTA_ZPZ_H |
| 2151842459U, // CLASTA_ZPZ_S |
| 2151714643U, // CLASTB_RPZ_B |
| 2151714643U, // CLASTB_RPZ_D |
| 2151714643U, // CLASTB_RPZ_H |
| 2151714643U, // CLASTB_RPZ_S |
| 2151714643U, // CLASTB_VPZ_B |
| 2151714643U, // CLASTB_VPZ_D |
| 2151714643U, // CLASTB_VPZ_H |
| 2151714643U, // CLASTB_VPZ_S |
| 2151747411U, // CLASTB_ZPZ_B |
| 2151780179U, // CLASTB_ZPZ_D |
| 29495123U, // CLASTB_ZPZ_H |
| 2151845715U, // CLASTB_ZPZ_S |
| 51166U, // CLREX |
| 4243947U, // CLSWr |
| 4243947U, // CLSXr |
| 541147627U, // CLS_ZPmZ_B |
| 541180395U, // CLS_ZPmZ_D |
| 1082278379U, // CLS_ZPmZ_H |
| 541245931U, // CLS_ZPmZ_S |
| 1615005394U, // CLSv16i8 |
| 1615017805U, // CLSv2i32 |
| 1615011340U, // CLSv4i16 |
| 1615019884U, // CLSv4i32 |
| 1615013236U, // CLSv8i16 |
| 1615006351U, // CLSv8i8 |
| 4245598U, // CLZWr |
| 4245598U, // CLZXr |
| 541149278U, // CLZ_ZPmZ_B |
| 541182046U, // CLZ_ZPmZ_D |
| 1082280030U, // CLZ_ZPmZ_H |
| 541247582U, // CLZ_ZPmZ_S |
| 1615005600U, // CLZv16i8 |
| 1615018123U, // CLZv2i32 |
| 1615011721U, // CLZv4i16 |
| 1615020369U, // CLZv4i32 |
| 1615013657U, // CLZv8i16 |
| 1615006528U, // CLZv8i8 |
| 1615005303U, // CMEQv16i8 |
| 1615005303U, // CMEQv16i8rz |
| 4239555U, // CMEQv1i64 |
| 4239555U, // CMEQv1i64rz |
| 1615017711U, // CMEQv2i32 |
| 1615017711U, // CMEQv2i32rz |
| 1615009035U, // CMEQv2i64 |
| 1615009035U, // CMEQv2i64rz |
| 1615011246U, // CMEQv4i16 |
| 1615011246U, // CMEQv4i16rz |
| 1615019790U, // CMEQv4i32 |
| 1615019790U, // CMEQv4i32rz |
| 1615013142U, // CMEQv8i16 |
| 1615013142U, // CMEQv8i16rz |
| 1615006269U, // CMEQv8i8 |
| 1615006269U, // CMEQv8i8rz |
| 1615005016U, // CMGEv16i8 |
| 1615005016U, // CMGEv16i8rz |
| 4233189U, // CMGEv1i64 |
| 4233189U, // CMGEv1i64rz |
| 1615017060U, // CMGEv2i32 |
| 1615017060U, // CMGEv2i32rz |
| 1615008441U, // CMGEv2i64 |
| 1615008441U, // CMGEv2i64rz |
| 1615010607U, // CMGEv4i16 |
| 1615010607U, // CMGEv4i16rz |
| 1615019035U, // CMGEv4i32 |
| 1615019035U, // CMGEv4i32rz |
| 1615012468U, // CMGEv8i16 |
| 1615012468U, // CMGEv8i16rz |
| 1615005895U, // CMGEv8i8 |
| 1615005895U, // CMGEv8i8rz |
| 1615005412U, // CMGTv16i8 |
| 1615005412U, // CMGTv16i8rz |
| 4244241U, // CMGTv1i64 |
| 4244241U, // CMGTv1i64rz |
| 1615017900U, // CMGTv2i32 |
| 1615017900U, // CMGTv2i32rz |
| 1615009216U, // CMGTv2i64 |
| 1615009216U, // CMGTv2i64rz |
| 1615011435U, // CMGTv4i16 |
| 1615011435U, // CMGTv4i16rz |
| 1615019979U, // CMGTv4i32 |
| 1615019979U, // CMGTv4i32rz |
| 1615013331U, // CMGTv8i16 |
| 1615013331U, // CMGTv8i16rz |
| 1615006367U, // CMGTv8i8 |
| 1615006367U, // CMGTv8i8rz |
| 1615005066U, // CMHIv16i8 |
| 4237869U, // CMHIv1i64 |
| 1615017215U, // CMHIv2i32 |
| 1615008534U, // CMHIv2i64 |
| 1615010739U, // CMHIv4i16 |
| 1615019202U, // CMHIv4i32 |
| 1615012600U, // CMHIv8i16 |
| 1615005931U, // CMHIv8i8 |
| 1615005384U, // CMHSv16i8 |
| 4243934U, // CMHSv1i64 |
| 1615017796U, // CMHSv2i32 |
| 1615009120U, // CMHSv2i64 |
| 1615011331U, // CMHSv4i16 |
| 1615019875U, // CMHSv4i32 |
| 1615013227U, // CMHSv8i16 |
| 1615006342U, // CMHSv8i8 |
| 84017477U, // CMLA_ZZZI_H |
| 2688713029U, // CMLA_ZZZI_S |
| 4260165U, // CMLA_ZZZ_B |
| 2151776581U, // CMLA_ZZZ_D |
| 84017477U, // CMLA_ZZZ_H |
| 2688713029U, // CMLA_ZZZ_S |
| 1615005026U, // CMLEv16i8rz |
| 4233220U, // CMLEv1i64rz |
| 1615017070U, // CMLEv2i32rz |
| 1615008451U, // CMLEv2i64rz |
| 1615010617U, // CMLEv4i16rz |
| 1615019045U, // CMLEv4i32rz |
| 1615012478U, // CMLEv8i16rz |
| 1615005904U, // CMLEv8i8rz |
| 1615005432U, // CMLTv16i8rz |
| 4244451U, // CMLTv1i64rz |
| 1615017910U, // CMLTv2i32rz |
| 1615009226U, // CMLTv2i64rz |
| 1615011445U, // CMLTv4i16rz |
| 1615019989U, // CMLTv4i32rz |
| 1615013341U, // CMLTv8i16rz |
| 1615006385U, // CMLTv8i8rz |
| 2151755986U, // CMPEQ_PPzZI_B |
| 2151788754U, // CMPEQ_PPzZI_D |
| 566374610U, // CMPEQ_PPzZI_H |
| 2151854290U, // CMPEQ_PPzZI_S |
| 2151755986U, // CMPEQ_PPzZZ_B |
| 2151788754U, // CMPEQ_PPzZZ_D |
| 566374610U, // CMPEQ_PPzZZ_H |
| 2151854290U, // CMPEQ_PPzZZ_S |
| 2151755986U, // CMPEQ_WIDE_PPzZZ_B |
| 566374610U, // CMPEQ_WIDE_PPzZZ_H |
| 2151854290U, // CMPEQ_WIDE_PPzZZ_S |
| 2151749611U, // CMPGE_PPzZI_B |
| 2151782379U, // CMPGE_PPzZI_D |
| 566368235U, // CMPGE_PPzZI_H |
| 2151847915U, // CMPGE_PPzZI_S |
| 2151749611U, // CMPGE_PPzZZ_B |
| 2151782379U, // CMPGE_PPzZZ_D |
| 566368235U, // CMPGE_PPzZZ_H |
| 2151847915U, // CMPGE_PPzZZ_S |
| 2151749611U, // CMPGE_WIDE_PPzZZ_B |
| 566368235U, // CMPGE_WIDE_PPzZZ_H |
| 2151847915U, // CMPGE_WIDE_PPzZZ_S |
| 2151760663U, // CMPGT_PPzZI_B |
| 2151793431U, // CMPGT_PPzZI_D |
| 566379287U, // CMPGT_PPzZI_H |
| 2151858967U, // CMPGT_PPzZI_S |
| 2151760663U, // CMPGT_PPzZZ_B |
| 2151793431U, // CMPGT_PPzZZ_D |
| 566379287U, // CMPGT_PPzZZ_H |
| 2151858967U, // CMPGT_PPzZZ_S |
| 2151760663U, // CMPGT_WIDE_PPzZZ_B |
| 566379287U, // CMPGT_WIDE_PPzZZ_H |
| 2151858967U, // CMPGT_WIDE_PPzZZ_S |
| 2151754291U, // CMPHI_PPzZI_B |
| 2151787059U, // CMPHI_PPzZI_D |
| 566372915U, // CMPHI_PPzZI_H |
| 2151852595U, // CMPHI_PPzZI_S |
| 2151754291U, // CMPHI_PPzZZ_B |
| 2151787059U, // CMPHI_PPzZZ_D |
| 566372915U, // CMPHI_PPzZZ_H |
| 2151852595U, // CMPHI_PPzZZ_S |
| 2151754291U, // CMPHI_WIDE_PPzZZ_B |
| 566372915U, // CMPHI_WIDE_PPzZZ_H |
| 2151852595U, // CMPHI_WIDE_PPzZZ_S |
| 2151760356U, // CMPHS_PPzZI_B |
| 2151793124U, // CMPHS_PPzZI_D |
| 566378980U, // CMPHS_PPzZI_H |
| 2151858660U, // CMPHS_PPzZI_S |
| 2151760356U, // CMPHS_PPzZZ_B |
| 2151793124U, // CMPHS_PPzZZ_D |
| 566378980U, // CMPHS_PPzZZ_H |
| 2151858660U, // CMPHS_PPzZZ_S |
| 2151760356U, // CMPHS_WIDE_PPzZZ_B |
| 566378980U, // CMPHS_WIDE_PPzZZ_H |
| 2151858660U, // CMPHS_WIDE_PPzZZ_S |
| 2151749642U, // CMPLE_PPzZI_B |
| 2151782410U, // CMPLE_PPzZI_D |
| 566368266U, // CMPLE_PPzZI_H |
| 2151847946U, // CMPLE_PPzZI_S |
| 2151749642U, // CMPLE_WIDE_PPzZZ_B |
| 566368266U, // CMPLE_WIDE_PPzZZ_H |
| 2151847946U, // CMPLE_WIDE_PPzZZ_S |
| 2151755490U, // CMPLO_PPzZI_B |
| 2151788258U, // CMPLO_PPzZI_D |
| 566374114U, // CMPLO_PPzZI_H |
| 2151853794U, // CMPLO_PPzZI_S |
| 2151755490U, // CMPLO_WIDE_PPzZZ_B |
| 566374114U, // CMPLO_WIDE_PPzZZ_H |
| 2151853794U, // CMPLO_WIDE_PPzZZ_S |
| 2151760391U, // CMPLS_PPzZI_B |
| 2151793159U, // CMPLS_PPzZI_D |
| 566379015U, // CMPLS_PPzZI_H |
| 2151858695U, // CMPLS_PPzZI_S |
| 2151760391U, // CMPLS_WIDE_PPzZZ_B |
| 566379015U, // CMPLS_WIDE_PPzZZ_H |
| 2151858695U, // CMPLS_WIDE_PPzZZ_S |
| 2151760873U, // CMPLT_PPzZI_B |
| 2151793641U, // CMPLT_PPzZI_D |
| 566379497U, // CMPLT_PPzZI_H |
| 2151859177U, // CMPLT_PPzZI_S |
| 2151760873U, // CMPLT_WIDE_PPzZZ_B |
| 566379497U, // CMPLT_WIDE_PPzZZ_H |
| 2151859177U, // CMPLT_WIDE_PPzZZ_S |
| 2151749665U, // CMPNE_PPzZI_B |
| 2151782433U, // CMPNE_PPzZI_D |
| 566368289U, // CMPNE_PPzZI_H |
| 2151847969U, // CMPNE_PPzZI_S |
| 2151749665U, // CMPNE_PPzZZ_B |
| 2151782433U, // CMPNE_PPzZZ_D |
| 566368289U, // CMPNE_PPzZZ_H |
| 2151847969U, // CMPNE_PPzZZ_S |
| 2151749665U, // CMPNE_WIDE_PPzZZ_B |
| 566368289U, // CMPNE_WIDE_PPzZZ_H |
| 2151847969U, // CMPNE_WIDE_PPzZZ_S |
| 1615005460U, // CMTSTv16i8 |
| 4244736U, // CMTSTv1i64 |
| 1615017929U, // CMTSTv2i32 |
| 1615009245U, // CMTSTv2i64 |
| 1615011464U, // CMTSTv4i16 |
| 1615020008U, // CMTSTv4i32 |
| 1615013360U, // CMTSTv8i16 |
| 1615006410U, // CMTSTv8i8 |
| 541148373U, // CNOT_ZPmZ_B |
| 541181141U, // CNOT_ZPmZ_D |
| 1082279125U, // CNOT_ZPmZ_H |
| 541246677U, // CNOT_ZPmZ_S |
| 1077972806U, // CNTB_XPiI |
| 1077974970U, // CNTD_XPiI |
| 1077979608U, // CNTH_XPiI |
| 1614852127U, // CNTP_XCI_B |
| 2151723039U, // CNTP_XCI_D |
| 2688593951U, // CNTP_XCI_H |
| 3225464863U, // CNTP_XCI_S |
| 2151723039U, // CNTP_XPP_B |
| 2151723039U, // CNTP_XPP_D |
| 2151723039U, // CNTP_XPP_H |
| 2151723039U, // CNTP_XPP_S |
| 1077987192U, // CNTW_XPiI |
| 4244511U, // CNTWr |
| 4244511U, // CNTXr |
| 541148191U, // CNT_ZPmZ_B |
| 541180959U, // CNT_ZPmZ_D |
| 1082278943U, // CNT_ZPmZ_H |
| 541246495U, // CNT_ZPmZ_S |
| 1615005442U, // CNTv16i8 |
| 1615006394U, // CNTv8i8 |
| 2151793364U, // COMPACT_ZPZ_D |
| 2151858900U, // COMPACT_ZPZ_S |
| 870977U, // CPYE |
| 871040U, // CPYEN |
| 871126U, // CPYERN |
| 872014U, // CPYERT |
| 871499U, // CPYERTN |
| 871248U, // CPYERTRN |
| 871746U, // CPYERTWN |
| 871928U, // CPYET |
| 871403U, // CPYETN |
| 871184U, // CPYETRN |
| 871682U, // CPYETWN |
| 871624U, // CPYEWN |
| 872071U, // CPYEWT |
| 871562U, // CPYEWTN |
| 871317U, // CPYEWTRN |
| 871815U, // CPYEWTWN |
| 870954U, // CPYFE |
| 871014U, // CPYFEN |
| 871116U, // CPYFERN |
| 872004U, // CPYFERT |
| 871488U, // CPYFERTN |
| 871236U, // CPYFERTRN |
| 871734U, // CPYFERTWN |
| 871902U, // CPYFET |
| 871374U, // CPYFETN |
| 871173U, // CPYFETRN |
| 871671U, // CPYFETWN |
| 871614U, // CPYFEWN |
| 872061U, // CPYFEWT |
| 871551U, // CPYFEWTN |
| 871305U, // CPYFEWTRN |
| 871803U, // CPYFEWTWN |
| 870984U, // CPYFM |
| 871048U, // CPYFMN |
| 871135U, // CPYFMRN |
| 872023U, // CPYFMRT |
| 871509U, // CPYFMRTN |
| 871259U, // CPYFMRTRN |
| 871757U, // CPYFMRTWN |
| 871936U, // CPYFMT |
| 871412U, // CPYFMTN |
| 871194U, // CPYFMTRN |
| 871692U, // CPYFMTWN |
| 871633U, // CPYFMWN |
| 872080U, // CPYFMWT |
| 871572U, // CPYFMWTN |
| 871328U, // CPYFMWTRN |
| 871826U, // CPYFMWTWN |
| 871872U, // CPYFP |
| 871082U, // CPYFPN |
| 871154U, // CPYFPRN |
| 872042U, // CPYFPRT |
| 871530U, // CPYFPRTN |
| 871282U, // CPYFPRTRN |
| 871780U, // CPYFPRTWN |
| 871970U, // CPYFPT |
| 871450U, // CPYFPTN |
| 871215U, // CPYFPTRN |
| 871713U, // CPYFPTWN |
| 871652U, // CPYFPWN |
| 872099U, // CPYFPWT |
| 871593U, // CPYFPWTN |
| 871351U, // CPYFPWTRN |
| 871849U, // CPYFPWTWN |
| 871007U, // CPYM |
| 871074U, // CPYMN |
| 871145U, // CPYMRN |
| 872033U, // CPYMRT |
| 871520U, // CPYMRTN |
| 871271U, // CPYMRTRN |
| 871769U, // CPYMRTWN |
| 871962U, // CPYMT |
| 871441U, // CPYMTN |
| 871205U, // CPYMTRN |
| 871703U, // CPYMTWN |
| 871643U, // CPYMWN |
| 872090U, // CPYMWT |
| 871583U, // CPYMWTN |
| 871340U, // CPYMWTRN |
| 871838U, // CPYMWTWN |
| 871895U, // CPYP |
| 871108U, // CPYPN |
| 871164U, // CPYPRN |
| 872052U, // CPYPRT |
| 871541U, // CPYPRTN |
| 871294U, // CPYPRTRN |
| 871792U, // CPYPRTWN |
| 871996U, // CPYPT |
| 871479U, // CPYPTN |
| 871226U, // CPYPTRN |
| 871724U, // CPYPTWN |
| 871662U, // CPYPWN |
| 872109U, // CPYPWT |
| 871604U, // CPYPWTN |
| 871363U, // CPYPWTRN |
| 871861U, // CPYPWTWN |
| 541149206U, // CPY_ZPmI_B |
| 541181974U, // CPY_ZPmI_D |
| 3766634518U, // CPY_ZPmI_H |
| 541247510U, // CPY_ZPmI_S |
| 541149206U, // CPY_ZPmR_B |
| 541181974U, // CPY_ZPmR_D |
| 8538134U, // CPY_ZPmR_H |
| 541247510U, // CPY_ZPmR_S |
| 541149206U, // CPY_ZPmV_B |
| 541181974U, // CPY_ZPmV_D |
| 8538134U, // CPY_ZPmV_H |
| 541247510U, // CPY_ZPmV_S |
| 2151761942U, // CPY_ZPzI_B |
| 2151794710U, // CPY_ZPzI_D |
| 566380566U, // CPY_ZPzI_H |
| 2151860246U, // CPY_ZPzI_S |
| 4227877U, // CRC32Brr |
| 4230070U, // CRC32CBrr |
| 4237211U, // CRC32CHrr |
| 4245207U, // CRC32CWrr |
| 4245454U, // CRC32CXrr |
| 4233661U, // CRC32Hrr |
| 4245163U, // CRC32Wrr |
| 4245392U, // CRC32Xrr |
| 4238294U, // CSELWr |
| 4238294U, // CSELXr |
| 4231183U, // CSINCWr |
| 4231183U, // CSINCXr |
| 4244983U, // CSINVWr |
| 4244983U, // CSINVXr |
| 4233388U, // CSNEGWr |
| 4233388U, // CSNEGXr |
| 4239561U, // CTERMEQ_WW |
| 4239561U, // CTERMEQ_XX |
| 4233240U, // CTERMNE_WW |
| 4233240U, // CTERMNE_XX |
| 4245615U, // CTZWr |
| 4245615U, // CTZXr |
| 753724U, // DCPS1 |
| 753834U, // DCPS2 |
| 753857U, // DCPS3 |
| 541100993U, // DECB_XPiI |
| 541103891U, // DECD_XPiI |
| 541169427U, // DECD_ZPiI |
| 541108134U, // DECH_XPiI |
| 104998822U, // DECH_ZPiI |
| 4239102U, // DECP_XP_B |
| 541110014U, // DECP_XP_D |
| 3762335486U, // DECP_XP_H |
| 541110014U, // DECP_XP_S |
| 2151788286U, // DECP_ZP_D |
| 3305254654U, // DECP_ZP_H |
| 2688724734U, // DECP_ZP_S |
| 541116130U, // DECW_XPiI |
| 541247202U, // DECW_ZPiI |
| 888218U, // DMB |
| 20264U, // DRPS |
| 888560U, // DSB |
| 921328U, // DSBnXS |
| 1078046188U, // DUPM_ZI |
| 4272351U, // DUPQ_ZZI_B |
| 541176031U, // DUPQ_ZZI_D |
| 1682059487U, // DUPQ_ZZI_H |
| 541241567U, // DUPQ_ZZI_S |
| 2151755827U, // DUP_ZI_B |
| 2688659507U, // DUP_ZI_D |
| 109195315U, // DUP_ZI_H |
| 3225595955U, // DUP_ZI_S |
| 4272179U, // DUP_ZR_B |
| 4304947U, // DUP_ZR_D |
| 3334615091U, // DUP_ZR_H |
| 4370483U, // DUP_ZR_S |
| 4272179U, // DUP_ZZI_B |
| 541175859U, // DUP_ZZI_D |
| 1682059315U, // DUP_ZZI_H |
| 1729015859U, // DUP_ZZI_Q |
| 541241395U, // DUP_ZZI_S |
| 1614857727U, // DUPi16 |
| 1614857727U, // DUPi32 |
| 1614857727U, // DUPi64 |
| 1614857727U, // DUPi8 |
| 4392536U, // DUPv16i8gpr |
| 1615005272U, // DUPv16i8lane |
| 4404936U, // DUPv2i32gpr |
| 1615017672U, // DUPv2i32lane |
| 4396280U, // DUPv2i64gpr |
| 1615009016U, // DUPv2i64lane |
| 4398471U, // DUPv4i16gpr |
| 1615011207U, // DUPv4i16lane |
| 4407015U, // DUPv4i32gpr |
| 1615019751U, // DUPv4i32lane |
| 4400367U, // DUPv8i16gpr |
| 1615013103U, // DUPv8i16lane |
| 4393505U, // DUPv8i8gpr |
| 1615006241U, // DUPv8i8lane |
| 4238898U, // EONWrs |
| 4238898U, // EONXrs |
| 1615004728U, // EOR3 |
| 541163707U, // EOR3_ZZZZ |
| 4276941U, // EORBT_ZZZ_B |
| 2151793357U, // EORBT_ZZZ_D |
| 84034253U, // EORBT_ZZZ_H |
| 2688729805U, // EORBT_ZZZ_S |
| 2181252677U, // EORQV_VPZ_B |
| 2185446981U, // EORQV_VPZ_D |
| 2189641285U, // EORQV_VPZ_H |
| 2193835589U, // EORQV_VPZ_S |
| 2151760494U, // EORS_PPzPP |
| 4263756U, // EORTB_ZZZ_B |
| 2151780172U, // EORTB_ZZZ_D |
| 84021068U, // EORTB_ZZZ_H |
| 2688716620U, // EORTB_ZZZ_S |
| 509540U, // EORV_VPZ_B |
| 3301459556U, // EORV_VPZ_D |
| 3305686628U, // EORV_VPZ_H |
| 3246999140U, // EORV_VPZ_S |
| 4239848U, // EORWri |
| 4239848U, // EORWrs |
| 4239848U, // EORXri |
| 4239848U, // EORXrs |
| 2151756264U, // EOR_PPzPP |
| 541176296U, // EOR_ZI |
| 2151756264U, // EOR_ZPmZ_B |
| 2151789032U, // EOR_ZPmZ_D |
| 2713858536U, // EOR_ZPmZ_H |
| 2151854568U, // EOR_ZPmZ_S |
| 541176296U, // EOR_ZZZ |
| 1615005355U, // EORv16i8 |
| 1615006316U, // EORv8i8 |
| 20269U, // ERET |
| 20150U, // ERETAA |
| 20177U, // ERETAB |
| 4272357U, // EXTQ_ZZI |
| 541131434U, // EXTRACT_ZPMXI_H_B |
| 541164202U, // EXTRACT_ZPMXI_H_D |
| 3766616746U, // EXTRACT_ZPMXI_H_H |
| 3767435946U, // EXTRACT_ZPMXI_H_Q |
| 541229738U, // EXTRACT_ZPMXI_H_S |
| 541131434U, // EXTRACT_ZPMXI_V_B |
| 541164202U, // EXTRACT_ZPMXI_V_D |
| 8520362U, // EXTRACT_ZPMXI_V_H |
| 9339562U, // EXTRACT_ZPMXI_V_Q |
| 541229738U, // EXTRACT_ZPMXI_V_S |
| 4239931U, // EXTRWrri |
| 4239931U, // EXTRXrri |
| 4277571U, // EXT_ZZI |
| 541148483U, // EXT_ZZI_B |
| 1615005471U, // EXTv16i8 |
| 1615006420U, // EXTv8i8 |
| 4232952U, // FABD16 |
| 4232952U, // FABD32 |
| 4232952U, // FABD64 |
| 2151782136U, // FABD_ZPmZ_D |
| 2713851640U, // FABD_ZPmZ_H |
| 2151847672U, // FABD_ZPmZ_S |
| 1615016939U, // FABDv2f32 |
| 1615008380U, // FABDv2f64 |
| 1615010486U, // FABDv4f16 |
| 1615018905U, // FABDv4f32 |
| 1615012347U, // FABDv8f16 |
| 4243852U, // FABSDr |
| 4243852U, // FABSHr |
| 4243852U, // FABSSr |
| 541180300U, // FABS_ZPmZ_D |
| 1082278284U, // FABS_ZPmZ_H |
| 541245836U, // FABS_ZPmZ_S |
| 1615017777U, // FABSv2f32 |
| 1615009101U, // FABSv2f64 |
| 1615011312U, // FABSv4f16 |
| 1615019856U, // FABSv4f32 |
| 1615013208U, // FABSv8f16 |
| 4233172U, // FACGE16 |
| 4233172U, // FACGE32 |
| 4233172U, // FACGE64 |
| 2151782356U, // FACGE_PPzZZ_D |
| 566368212U, // FACGE_PPzZZ_H |
| 2151847892U, // FACGE_PPzZZ_S |
| 1615017049U, // FACGEv2f32 |
| 1615008430U, // FACGEv2f64 |
| 1615010596U, // FACGEv4f16 |
| 1615019024U, // FACGEv4f32 |
| 1615012457U, // FACGEv8f16 |
| 4244224U, // FACGT16 |
| 4244224U, // FACGT32 |
| 4244224U, // FACGT64 |
| 2151793408U, // FACGT_PPzZZ_D |
| 566379264U, // FACGT_PPzZZ_H |
| 2151858944U, // FACGT_PPzZZ_S |
| 1615017889U, // FACGTv2f32 |
| 1615009205U, // FACGTv2f64 |
| 1615011424U, // FACGTv4f16 |
| 1615019968U, // FACGTv4f32 |
| 1615013320U, // FACGTv8f16 |
| 122159380U, // FADDA_VPZ_D |
| 126386452U, // FADDA_VPZ_H |
| 130613524U, // FADDA_VPZ_S |
| 4233032U, // FADDDrr |
| 4233032U, // FADDHrr |
| 2151788316U, // FADDP_ZPmZZ_D |
| 2713857820U, // FADDP_ZPmZZ_H |
| 2151853852U, // FADDP_ZPmZZ_S |
| 1615017553U, // FADDPv2f32 |
| 1615008917U, // FADDPv2f64 |
| 1614846343U, // FADDPv2i16p |
| 1614853713U, // FADDPv2i32p |
| 1614845077U, // FADDPv2i64p |
| 1615011088U, // FADDPv4f16 |
| 1615019632U, // FADDPv4f32 |
| 1615012984U, // FADDPv8f16 |
| 2185446922U, // FADDQV_D |
| 2189641226U, // FADDQV_H |
| 2193835530U, // FADDQV_S |
| 4233032U, // FADDSrr |
| 3301459358U, // FADDV_VPZ_D |
| 3305686430U, // FADDV_VPZ_H |
| 3246998942U, // FADDV_VPZ_S |
| 3288766280U, // FADD_VG2_M2Z_D |
| 3310032712U, // FADD_VG2_M2Z_H |
| 3288799048U, // FADD_VG2_M2Z_S |
| 3825637192U, // FADD_VG4_M4Z_D |
| 3314227016U, // FADD_VG4_M4Z_H |
| 3825669960U, // FADD_VG4_M4Z_S |
| 2151782216U, // FADD_ZPmI_D |
| 2713851720U, // FADD_ZPmI_H |
| 2151847752U, // FADD_ZPmI_S |
| 2151782216U, // FADD_ZPmZ_D |
| 2713851720U, // FADD_ZPmZ_H |
| 2151847752U, // FADD_ZPmZ_S |
| 541169480U, // FADD_ZZZ_D |
| 71440200U, // FADD_ZZZ_H |
| 541235016U, // FADD_ZZZ_S |
| 1615016976U, // FADDv2f32 |
| 1615008399U, // FADDv2f64 |
| 1615010523U, // FADDv4f16 |
| 1615018942U, // FADDv4f32 |
| 1615012384U, // FADDv8f16 |
| 2151782193U, // FCADD_ZPmZ_D |
| 2713851697U, // FCADD_ZPmZ_H |
| 2151847729U, // FCADD_ZPmZ_S |
| 1615016966U, // FCADDv2f32 |
| 1615008389U, // FCADDv2f64 |
| 1615010513U, // FCADDv4f16 |
| 1615018932U, // FCADDv4f32 |
| 1615012374U, // FCADDv8f16 |
| 4239209U, // FCCMPDrr |
| 4233272U, // FCCMPEDrr |
| 4233272U, // FCCMPEHrr |
| 4233272U, // FCCMPESrr |
| 4239209U, // FCCMPHrr |
| 4239209U, // FCCMPSrr |
| 80031569U, // FCLAMP_VG2_2Z2Z_D |
| 84258641U, // FCLAMP_VG2_2Z2Z_H |
| 25571153U, // FCLAMP_VG2_2Z2Z_S |
| 80031569U, // FCLAMP_VG4_4Z4Z_D |
| 84258641U, // FCLAMP_VG4_4Z4Z_H |
| 25571153U, // FCLAMP_VG4_4Z4Z_S |
| 2151788369U, // FCLAMP_ZZZ_D |
| 84029265U, // FCLAMP_ZZZ_H |
| 2688724817U, // FCLAMP_ZZZ_S |
| 4239554U, // FCMEQ16 |
| 4239554U, // FCMEQ32 |
| 4239554U, // FCMEQ64 |
| 2151788738U, // FCMEQ_PPzZ0_D |
| 566374594U, // FCMEQ_PPzZ0_H |
| 2151854274U, // FCMEQ_PPzZ0_S |
| 2151788738U, // FCMEQ_PPzZZ_D |
| 566374594U, // FCMEQ_PPzZZ_H |
| 2151854274U, // FCMEQ_PPzZZ_S |
| 4239554U, // FCMEQv1i16rz |
| 4239554U, // FCMEQv1i32rz |
| 4239554U, // FCMEQv1i64rz |
| 1615017710U, // FCMEQv2f32 |
| 1615009034U, // FCMEQv2f64 |
| 1615017710U, // FCMEQv2i32rz |
| 1615009034U, // FCMEQv2i64rz |
| 1615011245U, // FCMEQv4f16 |
| 1615019789U, // FCMEQv4f32 |
| 1615011245U, // FCMEQv4i16rz |
| 1615019789U, // FCMEQv4i32rz |
| 1615013141U, // FCMEQv8f16 |
| 1615013141U, // FCMEQv8i16rz |
| 4233188U, // FCMGE16 |
| 4233188U, // FCMGE32 |
| 4233188U, // FCMGE64 |
| 2151782372U, // FCMGE_PPzZ0_D |
| 566368228U, // FCMGE_PPzZ0_H |
| 2151847908U, // FCMGE_PPzZ0_S |
| 2151782372U, // FCMGE_PPzZZ_D |
| 566368228U, // FCMGE_PPzZZ_H |
| 2151847908U, // FCMGE_PPzZZ_S |
| 4233188U, // FCMGEv1i16rz |
| 4233188U, // FCMGEv1i32rz |
| 4233188U, // FCMGEv1i64rz |
| 1615017059U, // FCMGEv2f32 |
| 1615008440U, // FCMGEv2f64 |
| 1615017059U, // FCMGEv2i32rz |
| 1615008440U, // FCMGEv2i64rz |
| 1615010606U, // FCMGEv4f16 |
| 1615019034U, // FCMGEv4f32 |
| 1615010606U, // FCMGEv4i16rz |
| 1615019034U, // FCMGEv4i32rz |
| 1615012467U, // FCMGEv8f16 |
| 1615012467U, // FCMGEv8i16rz |
| 4244240U, // FCMGT16 |
| 4244240U, // FCMGT32 |
| 4244240U, // FCMGT64 |
| 2151793424U, // FCMGT_PPzZ0_D |
| 566379280U, // FCMGT_PPzZ0_H |
| 2151858960U, // FCMGT_PPzZ0_S |
| 2151793424U, // FCMGT_PPzZZ_D |
| 566379280U, // FCMGT_PPzZZ_H |
| 2151858960U, // FCMGT_PPzZZ_S |
| 4244240U, // FCMGTv1i16rz |
| 4244240U, // FCMGTv1i32rz |
| 4244240U, // FCMGTv1i64rz |
| 1615017899U, // FCMGTv2f32 |
| 1615009215U, // FCMGTv2f64 |
| 1615017899U, // FCMGTv2i32rz |
| 1615009215U, // FCMGTv2i64rz |
| 1615011434U, // FCMGTv4f16 |
| 1615019978U, // FCMGTv4f32 |
| 1615011434U, // FCMGTv4i16rz |
| 1615019978U, // FCMGTv4i32rz |
| 1615013330U, // FCMGTv8f16 |
| 1615013330U, // FCMGTv8i16rz |
| 2151776580U, // FCMLA_ZPmZZ_D |
| 2713846084U, // FCMLA_ZPmZZ_H |
| 2151842116U, // FCMLA_ZPmZZ_S |
| 84017476U, // FCMLA_ZZZI_H |
| 2688713028U, // FCMLA_ZZZI_S |
| 1615082350U, // FCMLAv2f32 |
| 1615073819U, // FCMLAv2f64 |
| 1615075897U, // FCMLAv4f16 |
| 1615075897U, // FCMLAv4f16_indexed |
| 1615084282U, // FCMLAv4f32 |
| 1615084282U, // FCMLAv4f32_indexed |
| 1615077758U, // FCMLAv8f16 |
| 1615077758U, // FCMLAv8f16_indexed |
| 2151782403U, // FCMLE_PPzZ0_D |
| 566368259U, // FCMLE_PPzZ0_H |
| 2151847939U, // FCMLE_PPzZ0_S |
| 4233219U, // FCMLEv1i16rz |
| 4233219U, // FCMLEv1i32rz |
| 4233219U, // FCMLEv1i64rz |
| 1615017069U, // FCMLEv2i32rz |
| 1615008450U, // FCMLEv2i64rz |
| 1615010616U, // FCMLEv4i16rz |
| 1615019044U, // FCMLEv4i32rz |
| 1615012477U, // FCMLEv8i16rz |
| 2151793634U, // FCMLT_PPzZ0_D |
| 566379490U, // FCMLT_PPzZ0_H |
| 2151859170U, // FCMLT_PPzZ0_S |
| 4244450U, // FCMLTv1i16rz |
| 4244450U, // FCMLTv1i32rz |
| 4244450U, // FCMLTv1i64rz |
| 1615017909U, // FCMLTv2i32rz |
| 1615009225U, // FCMLTv2i64rz |
| 1615011444U, // FCMLTv4i16rz |
| 1615019988U, // FCMLTv4i32rz |
| 1615013340U, // FCMLTv8i16rz |
| 2151782417U, // FCMNE_PPzZ0_D |
| 566368273U, // FCMNE_PPzZ0_H |
| 2151847953U, // FCMNE_PPzZ0_S |
| 2151782417U, // FCMNE_PPzZZ_D |
| 566368273U, // FCMNE_PPzZZ_H |
| 2151847953U, // FCMNE_PPzZZ_S |
| 134262640U, // FCMPDri |
| 4239216U, // FCMPDrr |
| 134256704U, // FCMPEDri |
| 4233280U, // FCMPEDrr |
| 134256704U, // FCMPEHri |
| 4233280U, // FCMPEHrr |
| 134256704U, // FCMPESri |
| 4233280U, // FCMPESrr |
| 134262640U, // FCMPHri |
| 4239216U, // FCMPHrr |
| 134262640U, // FCMPSri |
| 4239216U, // FCMPSrr |
| 2151788271U, // FCMUO_PPzZZ_D |
| 566374127U, // FCMUO_PPzZZ_H |
| 2151853807U, // FCMUO_PPzZZ_S |
| 541181973U, // FCPY_ZPmI_D |
| 1082279957U, // FCPY_ZPmI_H |
| 541247509U, // FCPY_ZPmI_S |
| 4238293U, // FCSELDrrr |
| 4238293U, // FCSELHrrr |
| 4238293U, // FCSELSrrr |
| 4243844U, // FCVTASUWDr |
| 4243844U, // FCVTASUWHr |
| 4243844U, // FCVTASUWSr |
| 4243844U, // FCVTASUXDr |
| 4243844U, // FCVTASUXHr |
| 4243844U, // FCVTASUXSr |
| 4243844U, // FCVTASv1f16 |
| 4243844U, // FCVTASv1i32 |
| 4243844U, // FCVTASv1i64 |
| 1615017766U, // FCVTASv2f32 |
| 1615009090U, // FCVTASv2f64 |
| 1615011301U, // FCVTASv4f16 |
| 1615019845U, // FCVTASv4f32 |
| 1615013197U, // FCVTASv8f16 |
| 4244821U, // FCVTAUUWDr |
| 4244821U, // FCVTAUUWHr |
| 4244821U, // FCVTAUUWSr |
| 4244821U, // FCVTAUUXDr |
| 4244821U, // FCVTAUUXHr |
| 4244821U, // FCVTAUUXSr |
| 4244821U, // FCVTAUv1f16 |
| 4244821U, // FCVTAUv1i32 |
| 4244821U, // FCVTAUv1i64 |
| 1615017939U, // FCVTAUv2f32 |
| 1615009255U, // FCVTAUv2f64 |
| 1615011474U, // FCVTAUv4f16 |
| 1615020018U, // FCVTAUv4f32 |
| 1615013370U, // FCVTAUv8f16 |
| 4244744U, // FCVTDHr |
| 4244744U, // FCVTDSr |
| 4244744U, // FCVTHDr |
| 4244744U, // FCVTHSr |
| 541246483U, // FCVTLT_ZPmZ_HtoS |
| 541180947U, // FCVTLT_ZPmZ_StoD |
| 3292933475U, // FCVTL_2ZZ_H_S |
| 1648569699U, // FCVTLv2i32 |
| 1656958307U, // FCVTLv4i16 |
| 1648558193U, // FCVTLv4i32 |
| 1656946801U, // FCVTLv8i16 |
| 4243982U, // FCVTMSUWDr |
| 4243982U, // FCVTMSUWHr |
| 4243982U, // FCVTMSUWSr |
| 4243982U, // FCVTMSUXDr |
| 4243982U, // FCVTMSUXHr |
| 4243982U, // FCVTMSUXSr |
| 4243982U, // FCVTMSv1f16 |
| 4243982U, // FCVTMSv1i32 |
| 4243982U, // FCVTMSv1i64 |
| 1615017822U, // FCVTMSv2f32 |
| 1615009138U, // FCVTMSv2f64 |
| 1615011357U, // FCVTMSv4f16 |
| 1615019901U, // FCVTMSv4f32 |
| 1615013253U, // FCVTMSv8f16 |
| 4244837U, // FCVTMUUWDr |
| 4244837U, // FCVTMUUWHr |
| 4244837U, // FCVTMUUWSr |
| 4244837U, // FCVTMUUXDr |
| 4244837U, // FCVTMUUXHr |
| 4244837U, // FCVTMUUXSr |
| 4244837U, // FCVTMUv1f16 |
| 4244837U, // FCVTMUv1i32 |
| 4244837U, // FCVTMUv1i64 |
| 1615017961U, // FCVTMUv2f32 |
| 1615009277U, // FCVTMUv2f64 |
| 1615011496U, // FCVTMUv4f16 |
| 1615020040U, // FCVTMUv4f32 |
| 1615013392U, // FCVTMUv8f16 |
| 4244003U, // FCVTNSUWDr |
| 4244003U, // FCVTNSUWHr |
| 4244003U, // FCVTNSUWSr |
| 4244003U, // FCVTNSUXDr |
| 4244003U, // FCVTNSUXHr |
| 4244003U, // FCVTNSUXSr |
| 4244003U, // FCVTNSv1f16 |
| 4244003U, // FCVTNSv1i32 |
| 4244003U, // FCVTNSv1i64 |
| 1615017833U, // FCVTNSv2f32 |
| 1615009149U, // FCVTNSv2f64 |
| 1615011368U, // FCVTNSv4f16 |
| 1615019912U, // FCVTNSv4f32 |
| 1615013264U, // FCVTNSv8f16 |
| 541246563U, // FCVTNT_ZPmZ_DtoS |
| 2156020835U, // FCVTNT_ZPmZ_StoH |
| 4244845U, // FCVTNUUWDr |
| 4244845U, // FCVTNUUWHr |
| 4244845U, // FCVTNUUWSr |
| 4244845U, // FCVTNUUXDr |
| 4244845U, // FCVTNUUXHr |
| 4244845U, // FCVTNUUXSr |
| 4244845U, // FCVTNUv1f16 |
| 4244845U, // FCVTNUv1i32 |
| 4244845U, // FCVTNUv1i64 |
| 1615017972U, // FCVTNUv2f32 |
| 1615009288U, // FCVTNUv2f64 |
| 1615011507U, // FCVTNUv4f16 |
| 1615020051U, // FCVTNUv4f32 |
| 1615013403U, // FCVTNUv8f16 |
| 3284282983U, // FCVTN_Z2Z_StoH |
| 138620519U, // FCVTNv2i32 |
| 142814823U, // FCVTNv4i16 |
| 1657012351U, // FCVTNv4i32 |
| 1652818047U, // FCVTNv8i16 |
| 4244057U, // FCVTPSUWDr |
| 4244057U, // FCVTPSUWHr |
| 4244057U, // FCVTPSUWSr |
| 4244057U, // FCVTPSUXDr |
| 4244057U, // FCVTPSUXHr |
| 4244057U, // FCVTPSUXSr |
| 4244057U, // FCVTPSv1f16 |
| 4244057U, // FCVTPSv1i32 |
| 4244057U, // FCVTPSv1i64 |
| 1615017855U, // FCVTPSv2f32 |
| 1615009171U, // FCVTPSv2f64 |
| 1615011390U, // FCVTPSv4f16 |
| 1615019934U, // FCVTPSv4f32 |
| 1615013286U, // FCVTPSv8f16 |
| 4244853U, // FCVTPUUWDr |
| 4244853U, // FCVTPUUWHr |
| 4244853U, // FCVTPUUWSr |
| 4244853U, // FCVTPUUXDr |
| 4244853U, // FCVTPUUXHr |
| 4244853U, // FCVTPUUXSr |
| 4244853U, // FCVTPUv1f16 |
| 4244853U, // FCVTPUv1i32 |
| 4244853U, // FCVTPUv1i64 |
| 1615017983U, // FCVTPUv2f32 |
| 1615009299U, // FCVTPUv2f64 |
| 1615011518U, // FCVTPUv4f16 |
| 1615020062U, // FCVTPUv4f32 |
| 1615013414U, // FCVTPUv8f16 |
| 4244744U, // FCVTSDr |
| 4244744U, // FCVTSHr |
| 541246617U, // FCVTXNT_ZPmZ_DtoS |
| 4239030U, // FCVTXNv1i64 |
| 138620598U, // FCVTXNv2f32 |
| 1657012359U, // FCVTXNv4f32 |
| 541247493U, // FCVTX_ZPmZ_DtoS |
| 4244116U, // FCVTZSSWDri |
| 4244116U, // FCVTZSSWHri |
| 4244116U, // FCVTZSSWSri |
| 4244116U, // FCVTZSSXDri |
| 4244116U, // FCVTZSSXHri |
| 4244116U, // FCVTZSSXSri |
| 4244116U, // FCVTZSUWDr |
| 4244116U, // FCVTZSUWHr |
| 4244116U, // FCVTZSUWSr |
| 4244116U, // FCVTZSUXDr |
| 4244116U, // FCVTZSUXHr |
| 4244116U, // FCVTZSUXSr |
| 3284550292U, // FCVTZS_2Z2Z_StoS |
| 3284550292U, // FCVTZS_4Z4Z_StoS |
| 541180564U, // FCVTZS_ZPmZ_DtoD |
| 541246100U, // FCVTZS_ZPmZ_DtoS |
| 541180564U, // FCVTZS_ZPmZ_HtoD |
| 1082278548U, // FCVTZS_ZPmZ_HtoH |
| 541246100U, // FCVTZS_ZPmZ_HtoS |
| 541180564U, // FCVTZS_ZPmZ_StoD |
| 541246100U, // FCVTZS_ZPmZ_StoS |
| 4244116U, // FCVTZSd |
| 4244116U, // FCVTZSh |
| 4244116U, // FCVTZSs |
| 4244116U, // FCVTZSv1f16 |
| 4244116U, // FCVTZSv1i32 |
| 4244116U, // FCVTZSv1i64 |
| 1615017878U, // FCVTZSv2f32 |
| 1615009194U, // FCVTZSv2f64 |
| 1615017878U, // FCVTZSv2i32_shift |
| 1615009194U, // FCVTZSv2i64_shift |
| 1615011413U, // FCVTZSv4f16 |
| 1615019957U, // FCVTZSv4f32 |
| 1615011413U, // FCVTZSv4i16_shift |
| 1615019957U, // FCVTZSv4i32_shift |
| 1615013309U, // FCVTZSv8f16 |
| 1615013309U, // FCVTZSv8i16_shift |
| 4244878U, // FCVTZUSWDri |
| 4244878U, // FCVTZUSWHri |
| 4244878U, // FCVTZUSWSri |
| 4244878U, // FCVTZUSXDri |
| 4244878U, // FCVTZUSXHri |
| 4244878U, // FCVTZUSXSri |
| 4244878U, // FCVTZUUWDr |
| 4244878U, // FCVTZUUWHr |
| 4244878U, // FCVTZUUWSr |
| 4244878U, // FCVTZUUXDr |
| 4244878U, // FCVTZUUXHr |
| 4244878U, // FCVTZUUXSr |
| 3284551054U, // FCVTZU_2Z2Z_StoS |
| 3284551054U, // FCVTZU_4Z4Z_StoS |
| 541181326U, // FCVTZU_ZPmZ_DtoD |
| 541246862U, // FCVTZU_ZPmZ_DtoS |
| 541181326U, // FCVTZU_ZPmZ_HtoD |
| 1082279310U, // FCVTZU_ZPmZ_HtoH |
| 541246862U, // FCVTZU_ZPmZ_HtoS |
| 541181326U, // FCVTZU_ZPmZ_StoD |
| 541246862U, // FCVTZU_ZPmZ_StoS |
| 4244878U, // FCVTZUd |
| 4244878U, // FCVTZUh |
| 4244878U, // FCVTZUs |
| 4244878U, // FCVTZUv1f16 |
| 4244878U, // FCVTZUv1i32 |
| 4244878U, // FCVTZUv1i64 |
| 1615017994U, // FCVTZUv2f32 |
| 1615009310U, // FCVTZUv2f64 |
| 1615017994U, // FCVTZUv2i32_shift |
| 1615009310U, // FCVTZUv2i64_shift |
| 1615011529U, // FCVTZUv4f16 |
| 1615020073U, // FCVTZUv4f32 |
| 1615011529U, // FCVTZUv4i16_shift |
| 1615020073U, // FCVTZUv4i32_shift |
| 1615013425U, // FCVTZUv8f16 |
| 1615013425U, // FCVTZUv8i16_shift |
| 3292939528U, // FCVT_2ZZ_H_S |
| 3284288776U, // FCVT_Z2Z_StoH |
| 1619150088U, // FCVT_ZPmZ_DtoH |
| 541246728U, // FCVT_ZPmZ_DtoS |
| 541181192U, // FCVT_ZPmZ_HtoD |
| 541246728U, // FCVT_ZPmZ_HtoS |
| 541181192U, // FCVT_ZPmZ_StoD |
| 2156021000U, // FCVT_ZPmZ_StoH |
| 4244926U, // FDIVDrr |
| 4244926U, // FDIVHrr |
| 2151789148U, // FDIVR_ZPmZ_D |
| 2713858652U, // FDIVR_ZPmZ_H |
| 2151854684U, // FDIVR_ZPmZ_S |
| 4244926U, // FDIVSrr |
| 2151794110U, // FDIV_ZPmZ_D |
| 2713863614U, // FDIV_ZPmZ_H |
| 2151859646U, // FDIV_ZPmZ_S |
| 1615018005U, // FDIVv2f32 |
| 1615009321U, // FDIVv2f64 |
| 1615011549U, // FDIVv4f16 |
| 1615020093U, // FDIVv4f32 |
| 1615013445U, // FDIVv8f16 |
| 3288810665U, // FDOT_VG2_M2Z2Z_HtoS |
| 3288810665U, // FDOT_VG2_M2ZZI_HtoS |
| 3288810665U, // FDOT_VG2_M2ZZ_HtoS |
| 3825681577U, // FDOT_VG4_M4Z4Z_HtoS |
| 3825681577U, // FDOT_VG4_M4ZZI_HtoS |
| 3825681577U, // FDOT_VG4_M4ZZ_HtoS |
| 1078117545U, // FDOT_ZZZI_S |
| 1078117545U, // FDOT_ZZZ_S |
| 2151788594U, // FDUP_ZI_D |
| 146944050U, // FDUP_ZI_H |
| 2151854130U, // FDUP_ZI_S |
| 541164065U, // FEXPA_ZZ_D |
| 3292660257U, // FEXPA_ZZ_H |
| 541229601U, // FEXPA_ZZ_S |
| 4244124U, // FJCVTZS |
| 541166587U, // FLOGB_ZPmZ_D |
| 1082264571U, // FLOGB_ZPmZ_H |
| 541232123U, // FLOGB_ZPmZ_S |
| 4233068U, // FMADDDrrr |
| 4233068U, // FMADDHrrr |
| 4233068U, // FMADDSrrr |
| 2151782116U, // FMAD_ZPmZZ_D |
| 2713851620U, // FMAD_ZPmZZ_H |
| 2151847652U, // FMAD_ZPmZZ_S |
| 4245427U, // FMAXDrr |
| 4245427U, // FMAXHrr |
| 4238820U, // FMAXNMDrr |
| 4238820U, // FMAXNMHrr |
| 2151788415U, // FMAXNMP_ZPmZZ_D |
| 2713857919U, // FMAXNMP_ZPmZZ_H |
| 2151853951U, // FMAXNMP_ZPmZZ_S |
| 1615017619U, // FMAXNMPv2f32 |
| 1615008983U, // FMAXNMPv2f64 |
| 1614846365U, // FMAXNMPv2i16p |
| 1614853779U, // FMAXNMPv2i32p |
| 1614845143U, // FMAXNMPv2i64p |
| 1615011154U, // FMAXNMPv4f16 |
| 1615019698U, // FMAXNMPv4f32 |
| 1615013050U, // FMAXNMPv8f16 |
| 2185446947U, // FMAXNMQV_D |
| 2189641251U, // FMAXNMQV_H |
| 2193835555U, // FMAXNMQV_S |
| 4238820U, // FMAXNMSrr |
| 3301459417U, // FMAXNMV_VPZ_D |
| 3305686489U, // FMAXNMV_VPZ_H |
| 3246999001U, // FMAXNMV_VPZ_S |
| 1614847752U, // FMAXNMVv4i16v |
| 1614856296U, // FMAXNMVv4i32v |
| 1614849648U, // FMAXNMVv8i16v |
| 54865380U, // FMAXNM_VG2_2Z2Z_D |
| 59092452U, // FMAXNM_VG2_2Z2Z_H |
| 63319524U, // FMAXNM_VG2_2Z2Z_S |
| 54865380U, // FMAXNM_VG2_2ZZ_D |
| 59092452U, // FMAXNM_VG2_2ZZ_H |
| 63319524U, // FMAXNM_VG2_2ZZ_S |
| 54865380U, // FMAXNM_VG4_4Z4Z_D |
| 59092452U, // FMAXNM_VG4_4Z4Z_H |
| 63319524U, // FMAXNM_VG4_4Z4Z_S |
| 54865380U, // FMAXNM_VG4_4ZZ_D |
| 59092452U, // FMAXNM_VG4_4ZZ_H |
| 63319524U, // FMAXNM_VG4_4ZZ_S |
| 2151788004U, // FMAXNM_ZPmI_D |
| 2713857508U, // FMAXNM_ZPmI_H |
| 2151853540U, // FMAXNM_ZPmI_S |
| 2151788004U, // FMAXNM_ZPmZ_D |
| 2713857508U, // FMAXNM_ZPmZ_H |
| 2151853540U, // FMAXNM_ZPmZ_S |
| 1615017369U, // FMAXNMv2f32 |
| 1615008875U, // FMAXNMv2f64 |
| 1615010893U, // FMAXNMv4f16 |
| 1615019562U, // FMAXNMv4f32 |
| 1615012924U, // FMAXNMv8f16 |
| 2151788624U, // FMAXP_ZPmZZ_D |
| 2713858128U, // FMAXP_ZPmZZ_H |
| 2151854160U, // FMAXP_ZPmZZ_S |
| 1615017680U, // FMAXPv2f32 |
| 1615009024U, // FMAXPv2f64 |
| 1614846387U, // FMAXPv2i16p |
| 1614853840U, // FMAXPv2i32p |
| 1614845184U, // FMAXPv2i64p |
| 1615011215U, // FMAXPv4f16 |
| 1615019759U, // FMAXPv4f32 |
| 1615013111U, // FMAXPv8f16 |
| 2185446988U, // FMAXQV_D |
| 2189641292U, // FMAXQV_H |
| 2193835596U, // FMAXQV_S |
| 4245427U, // FMAXSrr |
| 3301459562U, // FMAXV_VPZ_D |
| 3305686634U, // FMAXV_VPZ_H |
| 3246999146U, // FMAXV_VPZ_S |
| 1614847803U, // FMAXVv4i16v |
| 1614856347U, // FMAXVv4i32v |
| 1614849699U, // FMAXVv8i16v |
| 54871987U, // FMAX_VG2_2Z2Z_D |
| 59099059U, // FMAX_VG2_2Z2Z_H |
| 63326131U, // FMAX_VG2_2Z2Z_S |
| 54871987U, // FMAX_VG2_2ZZ_D |
| 59099059U, // FMAX_VG2_2ZZ_H |
| 63326131U, // FMAX_VG2_2ZZ_S |
| 54871987U, // FMAX_VG4_4Z4Z_D |
| 59099059U, // FMAX_VG4_4Z4Z_H |
| 63326131U, // FMAX_VG4_4Z4Z_S |
| 54871987U, // FMAX_VG4_4ZZ_D |
| 59099059U, // FMAX_VG4_4ZZ_H |
| 63326131U, // FMAX_VG4_4ZZ_S |
| 2151794611U, // FMAX_ZPmI_D |
| 2713864115U, // FMAX_ZPmI_H |
| 2151860147U, // FMAX_ZPmI_S |
| 2151794611U, // FMAX_ZPmZ_D |
| 2713864115U, // FMAX_ZPmZ_H |
| 2151860147U, // FMAX_ZPmZ_S |
| 1615018049U, // FMAXv2f32 |
| 1615009405U, // FMAXv2f64 |
| 1615011673U, // FMAXv4f16 |
| 1615020283U, // FMAXv4f32 |
| 1615013609U, // FMAXv8f16 |
| 4238864U, // FMINDrr |
| 4238864U, // FMINHrr |
| 4238811U, // FMINNMDrr |
| 4238811U, // FMINNMHrr |
| 2151788406U, // FMINNMP_ZPmZZ_D |
| 2713857910U, // FMINNMP_ZPmZZ_H |
| 2151853942U, // FMINNMP_ZPmZZ_S |
| 1615017607U, // FMINNMPv2f32 |
| 1615008971U, // FMINNMPv2f64 |
| 1614846353U, // FMINNMPv2i16p |
| 1614853767U, // FMINNMPv2i32p |
| 1614845131U, // FMINNMPv2i64p |
| 1615011142U, // FMINNMPv4f16 |
| 1615019686U, // FMINNMPv4f32 |
| 1615013038U, // FMINNMPv8f16 |
| 2185446937U, // FMINNMQV_D |
| 2189641241U, // FMINNMQV_H |
| 2193835545U, // FMINNMQV_S |
| 4238811U, // FMINNMSrr |
| 3301459408U, // FMINNMV_VPZ_D |
| 3305686480U, // FMINNMV_VPZ_H |
| 3246998992U, // FMINNMV_VPZ_S |
| 1614847740U, // FMINNMVv4i16v |
| 1614856284U, // FMINNMVv4i32v |
| 1614849636U, // FMINNMVv8i16v |
| 54865371U, // FMINNM_VG2_2Z2Z_D |
| 59092443U, // FMINNM_VG2_2Z2Z_H |
| 63319515U, // FMINNM_VG2_2Z2Z_S |
| 54865371U, // FMINNM_VG2_2ZZ_D |
| 59092443U, // FMINNM_VG2_2ZZ_H |
| 63319515U, // FMINNM_VG2_2ZZ_S |
| 54865371U, // FMINNM_VG4_4Z4Z_D |
| 59092443U, // FMINNM_VG4_4Z4Z_H |
| 63319515U, // FMINNM_VG4_4Z4Z_S |
| 54865371U, // FMINNM_VG4_4ZZ_D |
| 59092443U, // FMINNM_VG4_4ZZ_H |
| 63319515U, // FMINNM_VG4_4ZZ_S |
| 2151787995U, // FMINNM_ZPmI_D |
| 2713857499U, // FMINNM_ZPmI_H |
| 2151853531U, // FMINNM_ZPmI_S |
| 2151787995U, // FMINNM_ZPmZ_D |
| 2713857499U, // FMINNM_ZPmZ_H |
| 2151853531U, // FMINNM_ZPmZ_S |
| 1615017358U, // FMINNMv2f32 |
| 1615008864U, // FMINNMv2f64 |
| 1615010882U, // FMINNMv4f16 |
| 1615019551U, // FMINNMv4f32 |
| 1615012913U, // FMINNMv8f16 |
| 2151788430U, // FMINP_ZPmZZ_D |
| 2713857934U, // FMINP_ZPmZZ_H |
| 2151853966U, // FMINP_ZPmZZ_S |
| 1615017631U, // FMINPv2f32 |
| 1615008995U, // FMINPv2f64 |
| 1614846377U, // FMINPv2i16p |
| 1614853791U, // FMINPv2i32p |
| 1614845155U, // FMINPv2i64p |
| 1615011166U, // FMINPv4f16 |
| 1615019710U, // FMINPv4f32 |
| 1615013062U, // FMINPv8f16 |
| 2185446957U, // FMINQV_D |
| 2189641261U, // FMINQV_H |
| 2193835565U, // FMINQV_S |
| 4238864U, // FMINSrr |
| 3301459426U, // FMINV_VPZ_D |
| 3305686498U, // FMINV_VPZ_H |
| 3246999010U, // FMINV_VPZ_S |
| 1614847764U, // FMINVv4i16v |
| 1614856308U, // FMINVv4i32v |
| 1614849660U, // FMINVv8i16v |
| 54865424U, // FMIN_VG2_2Z2Z_D |
| 59092496U, // FMIN_VG2_2Z2Z_H |
| 63319568U, // FMIN_VG2_2Z2Z_S |
| 54865424U, // FMIN_VG2_2ZZ_D |
| 59092496U, // FMIN_VG2_2ZZ_H |
| 63319568U, // FMIN_VG2_2ZZ_S |
| 54865424U, // FMIN_VG4_4Z4Z_D |
| 59092496U, // FMIN_VG4_4Z4Z_H |
| 63319568U, // FMIN_VG4_4Z4Z_S |
| 54865424U, // FMIN_VG4_4ZZ_D |
| 59092496U, // FMIN_VG4_4ZZ_H |
| 63319568U, // FMIN_VG4_4ZZ_S |
| 2151788048U, // FMIN_ZPmI_D |
| 2713857552U, // FMIN_ZPmI_H |
| 2151853584U, // FMIN_ZPmI_S |
| 2151788048U, // FMIN_ZPmZ_D |
| 2713857552U, // FMIN_ZPmZ_H |
| 2151853584U, // FMIN_ZPmZ_S |
| 1615017413U, // FMINv2f32 |
| 1615008897U, // FMINv2f64 |
| 1615010937U, // FMINv4f16 |
| 1615019584U, // FMINv4f32 |
| 1615012946U, // FMINv8f16 |
| 1615069281U, // FMLAL2lanev4f16 |
| 1615069281U, // FMLAL2lanev8f16 |
| 18775U, // FMLAL2v4f16 |
| 18775U, // FMLAL2v8f16 |
| 1078103099U, // FMLALB_ZZZI_SHH |
| 1078103099U, // FMLALB_ZZZ_SHH |
| 1078117196U, // FMLALT_ZZZI_SHH |
| 1078117196U, // FMLALT_ZZZ_SHH |
| 2781293187U, // FMLAL_MZZI_S |
| 2781293187U, // FMLAL_MZZ_S |
| 3318164099U, // FMLAL_VG2_M2Z2Z_S |
| 3318164099U, // FMLAL_VG2_M2ZZI_S |
| 3318164099U, // FMLAL_VG2_M2ZZ_S |
| 3855035011U, // FMLAL_VG4_M4Z4Z_S |
| 3855035011U, // FMLAL_VG4_M4ZZI_S |
| 3855035011U, // FMLAL_VG4_M4ZZ_S |
| 1615080067U, // FMLALlanev4f16 |
| 1615080067U, // FMLALlanev8f16 |
| 20222U, // FMLALv4f16 |
| 20222U, // FMLALv8f16 |
| 3288760652U, // FMLA_VG2_M2Z2Z_D |
| 3288793420U, // FMLA_VG2_M2Z2Z_S |
| 88801612U, // FMLA_VG2_M2Z4Z_H |
| 3288760652U, // FMLA_VG2_M2ZZI_D |
| 88801612U, // FMLA_VG2_M2ZZI_H |
| 3288793420U, // FMLA_VG2_M2ZZI_S |
| 3288760652U, // FMLA_VG2_M2ZZ_D |
| 88801612U, // FMLA_VG2_M2ZZ_H |
| 3288793420U, // FMLA_VG2_M2ZZ_S |
| 3825631564U, // FMLA_VG4_M4Z4Z_D |
| 92995916U, // FMLA_VG4_M4Z4Z_H |
| 3825664332U, // FMLA_VG4_M4Z4Z_S |
| 3825631564U, // FMLA_VG4_M4ZZI_D |
| 92995916U, // FMLA_VG4_M4ZZI_H |
| 3825664332U, // FMLA_VG4_M4ZZI_S |
| 3825631564U, // FMLA_VG4_M4ZZ_D |
| 92995916U, // FMLA_VG4_M4ZZ_H |
| 3825664332U, // FMLA_VG4_M4ZZ_S |
| 2151776588U, // FMLA_ZPmZZ_D |
| 2713846092U, // FMLA_ZPmZZ_H |
| 2151842124U, // FMLA_ZPmZZ_S |
| 2151776588U, // FMLA_ZZZI_D |
| 84017484U, // FMLA_ZZZI_H |
| 2688713036U, // FMLA_ZZZI_S |
| 1615435980U, // FMLAv1i16_indexed |
| 1615442580U, // FMLAv1i32_indexed |
| 1615433760U, // FMLAv1i64_indexed |
| 1615082360U, // FMLAv2f32 |
| 1615073829U, // FMLAv2f64 |
| 1615082360U, // FMLAv2i32_indexed |
| 1615073829U, // FMLAv2i64_indexed |
| 1615075907U, // FMLAv4f16 |
| 1615084292U, // FMLAv4f32 |
| 1615075907U, // FMLAv4i16_indexed |
| 1615084292U, // FMLAv4i32_indexed |
| 1615077768U, // FMLAv8f16 |
| 1615077768U, // FMLAv8i16_indexed |
| 1615069289U, // FMLSL2lanev4f16 |
| 1615069289U, // FMLSL2lanev8f16 |
| 18782U, // FMLSL2v4f16 |
| 18782U, // FMLSL2v8f16 |
| 1078103397U, // FMLSLB_ZZZI_SHH |
| 1078103397U, // FMLSLB_ZZZ_SHH |
| 1078117371U, // FMLSLT_ZZZI_SHH |
| 1078117371U, // FMLSLT_ZZZ_SHH |
| 2781293869U, // FMLSL_MZZI_S |
| 2781293869U, // FMLSL_MZZ_S |
| 3318164781U, // FMLSL_VG2_M2Z2Z_S |
| 3318164781U, // FMLSL_VG2_M2ZZI_S |
| 3318164781U, // FMLSL_VG2_M2ZZ_S |
| 3855035693U, // FMLSL_VG4_M4Z4Z_S |
| 3855035693U, // FMLSL_VG4_M4ZZI_S |
| 3855035693U, // FMLSL_VG4_M4ZZ_S |
| 1615080749U, // FMLSLlanev4f16 |
| 1615080749U, // FMLSLlanev8f16 |
| 20251U, // FMLSLv4f16 |
| 20251U, // FMLSLv8f16 |
| 3288777210U, // FMLS_VG2_M2Z2Z_D |
| 88818170U, // FMLS_VG2_M2Z2Z_H |
| 3288809978U, // FMLS_VG2_M2Z2Z_S |
| 3288777210U, // FMLS_VG2_M2ZZI_D |
| 88818170U, // FMLS_VG2_M2ZZI_H |
| 3288809978U, // FMLS_VG2_M2ZZI_S |
| 3288777210U, // FMLS_VG2_M2ZZ_D |
| 88818170U, // FMLS_VG2_M2ZZ_H |
| 3288809978U, // FMLS_VG2_M2ZZ_S |
| 93012474U, // FMLS_VG4_M4Z2Z_H |
| 3825648122U, // FMLS_VG4_M4Z4Z_D |
| 3825680890U, // FMLS_VG4_M4Z4Z_S |
| 3825648122U, // FMLS_VG4_M4ZZI_D |
| 93012474U, // FMLS_VG4_M4ZZI_H |
| 3825680890U, // FMLS_VG4_M4ZZI_S |
| 3825648122U, // FMLS_VG4_M4ZZ_D |
| 93012474U, // FMLS_VG4_M4ZZ_H |
| 3825680890U, // FMLS_VG4_M4ZZ_S |
| 2151793146U, // FMLS_ZPmZZ_D |
| 2713862650U, // FMLS_ZPmZZ_H |
| 2151858682U, // FMLS_ZPmZZ_S |
| 2151793146U, // FMLS_ZZZI_D |
| 84034042U, // FMLS_ZZZI_H |
| 2688729594U, // FMLS_ZZZI_S |
| 1615436076U, // FMLSv1i16_indexed |
| 1615442676U, // FMLSv1i32_indexed |
| 1615433776U, // FMLSv1i64_indexed |
| 1615083349U, // FMLSv2f32 |
| 1615074665U, // FMLSv2f64 |
| 1615083349U, // FMLSv2i32_indexed |
| 1615074665U, // FMLSv2i64_indexed |
| 1615076884U, // FMLSv4f16 |
| 1615085428U, // FMLSv4f32 |
| 1615076884U, // FMLSv4i16_indexed |
| 1615085428U, // FMLSv4i32_indexed |
| 1615078780U, // FMLSv8f16 |
| 1615078780U, // FMLSv8i16_indexed |
| 2151776595U, // FMMLA_ZZZ_D |
| 2688713043U, // FMMLA_ZZZ_S |
| 100893073U, // FMOPAL_MPPZZ |
| 12812689U, // FMOPA_MPPZZ_D |
| 100893073U, // FMOPA_MPPZZ_H |
| 17006993U, // FMOPA_MPPZZ_S |
| 100909634U, // FMOPSL_MPPZZ |
| 12829250U, // FMOPS_MPPZZ_D |
| 100909634U, // FMOPS_MPPZZ_H |
| 17023554U, // FMOPS_MPPZZ_S |
| 1614843967U, // FMOVDXHighr |
| 4244990U, // FMOVDXr |
| 2151728638U, // FMOVDi |
| 4244990U, // FMOVDr |
| 4244990U, // FMOVHWr |
| 4244990U, // FMOVHXr |
| 2151728638U, // FMOVHi |
| 4244990U, // FMOVHr |
| 4244990U, // FMOVSWr |
| 2151728638U, // FMOVSi |
| 4244990U, // FMOVSr |
| 4244990U, // FMOVWHr |
| 4244990U, // FMOVWSr |
| 151195711U, // FMOVXDHighr |
| 4244990U, // FMOVXDr |
| 4244990U, // FMOVXHr |
| 2151888926U, // FMOVv2f32_ns |
| 2151880242U, // FMOVv2f64_ns |
| 2151882546U, // FMOVv4f16_ns |
| 2151891090U, // FMOVv4f32_ns |
| 2151884442U, // FMOVv8f16_ns |
| 2151780090U, // FMSB_ZPmZZ_D |
| 2713849594U, // FMSB_ZPmZZ_H |
| 2151845626U, // FMSB_ZPmZZ_S |
| 4231036U, // FMSUBDrrr |
| 4231036U, // FMSUBHrrr |
| 4231036U, // FMSUBSrrr |
| 4238699U, // FMULDrr |
| 4238699U, // FMULHrr |
| 4238699U, // FMULSrr |
| 4245486U, // FMULX16 |
| 4245486U, // FMULX32 |
| 4245486U, // FMULX64 |
| 2151794670U, // FMULX_ZPmZ_D |
| 2713864174U, // FMULX_ZPmZ_H |
| 2151860206U, // FMULX_ZPmZ_S |
| 4233547U, // FMULXv1i16_indexed |
| 4240147U, // FMULXv1i32_indexed |
| 4231247U, // FMULXv1i64_indexed |
| 1615018076U, // FMULXv2f32 |
| 1615009414U, // FMULXv2f64 |
| 1615018076U, // FMULXv2i32_indexed |
| 1615009414U, // FMULXv2i64_indexed |
| 1615011700U, // FMULXv4f16 |
| 1615020310U, // FMULXv4f32 |
| 1615011700U, // FMULXv4i16_indexed |
| 1615020310U, // FMULXv4i32_indexed |
| 1615013636U, // FMULXv8f16 |
| 1615013636U, // FMULXv8i16_indexed |
| 2151787883U, // FMUL_ZPmI_D |
| 2713857387U, // FMUL_ZPmI_H |
| 2151853419U, // FMUL_ZPmI_S |
| 2151787883U, // FMUL_ZPmZ_D |
| 2713857387U, // FMUL_ZPmZ_H |
| 2151853419U, // FMUL_ZPmZ_S |
| 541175147U, // FMUL_ZZZI_D |
| 71445867U, // FMUL_ZZZI_H |
| 541240683U, // FMUL_ZZZI_S |
| 541175147U, // FMUL_ZZZ_D |
| 71445867U, // FMUL_ZZZ_H |
| 541240683U, // FMUL_ZZZ_S |
| 4233508U, // FMULv1i16_indexed |
| 4240108U, // FMULv1i32_indexed |
| 4231208U, // FMULv1i64_indexed |
| 1615017349U, // FMULv2f32 |
| 1615008855U, // FMULv2f64 |
| 1615017349U, // FMULv2i32_indexed |
| 1615008855U, // FMULv2i64_indexed |
| 1615010873U, // FMULv4f16 |
| 1615019532U, // FMULv4f32 |
| 1615010873U, // FMULv4i16_indexed |
| 1615019532U, // FMULv4i32_indexed |
| 1615012904U, // FMULv8f16 |
| 1615012904U, // FMULv8i16_indexed |
| 4233375U, // FNEGDr |
| 4233375U, // FNEGHr |
| 4233375U, // FNEGSr |
| 541169823U, // FNEG_ZPmZ_D |
| 1082267807U, // FNEG_ZPmZ_H |
| 541235359U, // FNEG_ZPmZ_S |
| 1615017145U, // FNEGv2f32 |
| 1615008503U, // FNEGv2f64 |
| 1615010669U, // FNEGv4f16 |
| 1615019120U, // FNEGv4f32 |
| 1615012530U, // FNEGv8f16 |
| 4233075U, // FNMADDDrrr |
| 4233075U, // FNMADDHrrr |
| 4233075U, // FNMADDSrrr |
| 2151782122U, // FNMAD_ZPmZZ_D |
| 2713851626U, // FNMAD_ZPmZZ_H |
| 2151847658U, // FNMAD_ZPmZZ_S |
| 2151776617U, // FNMLA_ZPmZZ_D |
| 2713846121U, // FNMLA_ZPmZZ_H |
| 2151842153U, // FNMLA_ZPmZZ_S |
| 2151793152U, // FNMLS_ZPmZZ_D |
| 2713862656U, // FNMLS_ZPmZZ_H |
| 2151858688U, // FNMLS_ZPmZZ_S |
| 2151780096U, // FNMSB_ZPmZZ_D |
| 2713849600U, // FNMSB_ZPmZZ_H |
| 2151845632U, // FNMSB_ZPmZZ_S |
| 4231043U, // FNMSUBDrrr |
| 4231043U, // FNMSUBHrrr |
| 4231043U, // FNMSUBSrrr |
| 4238705U, // FNMULDrr |
| 4238705U, // FNMULHrr |
| 4238705U, // FNMULSrr |
| 541169704U, // FRECPE_ZZ_D |
| 3292665896U, // FRECPE_ZZ_H |
| 541235240U, // FRECPE_ZZ_S |
| 4233256U, // FRECPEv1f16 |
| 4233256U, // FRECPEv1i32 |
| 4233256U, // FRECPEv1i64 |
| 1615017079U, // FRECPEv2f32 |
| 1615008460U, // FRECPEv2f64 |
| 1615010626U, // FRECPEv4f16 |
| 1615019054U, // FRECPEv4f32 |
| 1615012487U, // FRECPEv8f16 |
| 4244018U, // FRECPS16 |
| 4244018U, // FRECPS32 |
| 4244018U, // FRECPS64 |
| 541180466U, // FRECPS_ZZZ_D |
| 71451186U, // FRECPS_ZZZ_H |
| 541246002U, // FRECPS_ZZZ_S |
| 1615017844U, // FRECPSv2f32 |
| 1615009160U, // FRECPSv2f64 |
| 1615011379U, // FRECPSv4f16 |
| 1615019923U, // FRECPSv4f32 |
| 1615013275U, // FRECPSv8f16 |
| 541181941U, // FRECPX_ZPmZ_D |
| 1082279925U, // FRECPX_ZPmZ_H |
| 541247477U, // FRECPX_ZPmZ_S |
| 4245493U, // FRECPXv1f16 |
| 4245493U, // FRECPXv1i32 |
| 4245493U, // FRECPXv1i64 |
| 4245400U, // FRINT32XDr |
| 4245400U, // FRINT32XSr |
| 1615018023U, // FRINT32Xv2f32 |
| 1615009379U, // FRINT32Xv2f64 |
| 1615020257U, // FRINT32Xv4f32 |
| 4245531U, // FRINT32ZDr |
| 4245531U, // FRINT32ZSr |
| 1615018097U, // FRINT32Zv2f32 |
| 1615009435U, // FRINT32Zv2f64 |
| 1615020343U, // FRINT32Zv4f32 |
| 4245410U, // FRINT64XDr |
| 4245410U, // FRINT64XSr |
| 1615018036U, // FRINT64Xv2f32 |
| 1615009392U, // FRINT64Xv2f64 |
| 1615020270U, // FRINT64Xv4f32 |
| 4245541U, // FRINT64ZDr |
| 4245541U, // FRINT64ZSr |
| 1615018110U, // FRINT64Zv2f32 |
| 1615009448U, // FRINT64Zv2f64 |
| 1615020356U, // FRINT64Zv4f32 |
| 4227731U, // FRINTADr |
| 4227731U, // FRINTAHr |
| 4227731U, // FRINTASr |
| 3284533907U, // FRINTA_2Z2Z_S |
| 3284533907U, // FRINTA_4Z4Z_S |
| 541164179U, // FRINTA_ZPmZ_D |
| 1082262163U, // FRINTA_ZPmZ_H |
| 541229715U, // FRINTA_ZPmZ_S |
| 1615016871U, // FRINTAv2f32 |
| 1615008340U, // FRINTAv2f64 |
| 1615010418U, // FRINTAv4f16 |
| 1615018803U, // FRINTAv4f32 |
| 1615012279U, // FRINTAv8f16 |
| 4237897U, // FRINTIDr |
| 4237897U, // FRINTIHr |
| 4237897U, // FRINTISr |
| 541174345U, // FRINTI_ZPmZ_D |
| 1082272329U, // FRINTI_ZPmZ_H |
| 541239881U, // FRINTI_ZPmZ_S |
| 1615017249U, // FRINTIv2f32 |
| 1615008559U, // FRINTIv2f64 |
| 1615010773U, // FRINTIv4f16 |
| 1615019236U, // FRINTIv4f32 |
| 1615012634U, // FRINTIv8f16 |
| 4238834U, // FRINTMDr |
| 4238834U, // FRINTMHr |
| 4238834U, // FRINTMSr |
| 3284545010U, // FRINTM_2Z2Z_S |
| 3284545010U, // FRINTM_4Z4Z_S |
| 541175282U, // FRINTM_ZPmZ_D |
| 1082273266U, // FRINTM_ZPmZ_H |
| 541240818U, // FRINTM_ZPmZ_S |
| 1615017380U, // FRINTMv2f32 |
| 1615008886U, // FRINTMv2f64 |
| 1615010904U, // FRINTMv4f16 |
| 1615019573U, // FRINTMv4f32 |
| 1615012935U, // FRINTMv8f16 |
| 4238942U, // FRINTNDr |
| 4238942U, // FRINTNHr |
| 4238942U, // FRINTNSr |
| 3284545118U, // FRINTN_2Z2Z_S |
| 3284545118U, // FRINTN_4Z4Z_S |
| 541175390U, // FRINTN_ZPmZ_D |
| 1082273374U, // FRINTN_ZPmZ_H |
| 541240926U, // FRINTN_ZPmZ_S |
| 1615017486U, // FRINTNv2f32 |
| 1615008906U, // FRINTNv2f64 |
| 1615011010U, // FRINTNv4f16 |
| 1615019611U, // FRINTNv4f32 |
| 1615012973U, // FRINTNv8f16 |
| 4239397U, // FRINTPDr |
| 4239397U, // FRINTPHr |
| 4239397U, // FRINTPSr |
| 3284545573U, // FRINTP_2Z2Z_S |
| 3284545573U, // FRINTP_4Z4Z_S |
| 541175845U, // FRINTP_ZPmZ_D |
| 1082273829U, // FRINTP_ZPmZ_H |
| 541241381U, // FRINTP_ZPmZ_S |
| 1615017661U, // FRINTPv2f32 |
| 1615009005U, // FRINTPv2f64 |
| 1615011196U, // FRINTPv4f16 |
| 1615019740U, // FRINTPv4f32 |
| 1615013092U, // FRINTPv8f16 |
| 4245501U, // FRINTXDr |
| 4245501U, // FRINTXHr |
| 4245501U, // FRINTXSr |
| 541181949U, // FRINTX_ZPmZ_D |
| 1082279933U, // FRINTX_ZPmZ_H |
| 541247485U, // FRINTX_ZPmZ_S |
| 1615018086U, // FRINTXv2f32 |
| 1615009424U, // FRINTXv2f64 |
| 1615011710U, // FRINTXv4f16 |
| 1615020320U, // FRINTXv4f32 |
| 1615013646U, // FRINTXv8f16 |
| 4245620U, // FRINTZDr |
| 4245620U, // FRINTZHr |
| 4245620U, // FRINTZSr |
| 541182068U, // FRINTZ_ZPmZ_D |
| 1082280052U, // FRINTZ_ZPmZ_H |
| 541247604U, // FRINTZ_ZPmZ_S |
| 1615018131U, // FRINTZv2f32 |
| 1615009461U, // FRINTZv2f64 |
| 1615011729U, // FRINTZv4f16 |
| 1615020377U, // FRINTZv4f32 |
| 1615013665U, // FRINTZv8f16 |
| 541169749U, // FRSQRTE_ZZ_D |
| 3292665941U, // FRSQRTE_ZZ_H |
| 541235285U, // FRSQRTE_ZZ_S |
| 4233301U, // FRSQRTEv1f16 |
| 4233301U, // FRSQRTEv1i32 |
| 4233301U, // FRSQRTEv1i64 |
| 1615017101U, // FRSQRTEv2f32 |
| 1615008471U, // FRSQRTEv2f64 |
| 1615010637U, // FRSQRTEv4f16 |
| 1615019076U, // FRSQRTEv4f32 |
| 1615012498U, // FRSQRTEv8f16 |
| 4244102U, // FRSQRTS16 |
| 4244102U, // FRSQRTS32 |
| 4244102U, // FRSQRTS64 |
| 541180550U, // FRSQRTS_ZZZ_D |
| 71451270U, // FRSQRTS_ZZZ_H |
| 541246086U, // FRSQRTS_ZZZ_S |
| 1615017866U, // FRSQRTSv2f32 |
| 1615009182U, // FRSQRTSv2f64 |
| 1615011401U, // FRSQRTSv4f16 |
| 1615019945U, // FRSQRTSv4f32 |
| 1615013297U, // FRSQRTSv8f16 |
| 2151782386U, // FSCALE_ZPmZ_D |
| 2713851890U, // FSCALE_ZPmZ_H |
| 2151847922U, // FSCALE_ZPmZ_S |
| 4244707U, // FSQRTDr |
| 4244707U, // FSQRTHr |
| 4244707U, // FSQRTSr |
| 541181155U, // FSQRT_ZPmZ_D |
| 1082279139U, // FSQRT_ZPmZ_H |
| 541246691U, // FSQRT_ZPmZ_S |
| 1615017919U, // FSQRTv2f32 |
| 1615009235U, // FSQRTv2f64 |
| 1615011454U, // FSQRTv4f16 |
| 1615019998U, // FSQRTv4f32 |
| 1615013350U, // FSQRTv8f16 |
| 4231016U, // FSUBDrr |
| 4231016U, // FSUBHrr |
| 2151788827U, // FSUBR_ZPmI_D |
| 2713858331U, // FSUBR_ZPmI_H |
| 2151854363U, // FSUBR_ZPmI_S |
| 2151788827U, // FSUBR_ZPmZ_D |
| 2713858331U, // FSUBR_ZPmZ_H |
| 2151854363U, // FSUBR_ZPmZ_S |
| 4231016U, // FSUBSrr |
| 3288764264U, // FSUB_VG2_M2Z_D |
| 3310030696U, // FSUB_VG2_M2Z_H |
| 3288797032U, // FSUB_VG2_M2Z_S |
| 3825635176U, // FSUB_VG4_M4Z_D |
| 3314225000U, // FSUB_VG4_M4Z_H |
| 3825667944U, // FSUB_VG4_M4Z_S |
| 2151780200U, // FSUB_ZPmI_D |
| 2713849704U, // FSUB_ZPmI_H |
| 2151845736U, // FSUB_ZPmI_S |
| 2151780200U, // FSUB_ZPmZ_D |
| 2713849704U, // FSUB_ZPmZ_H |
| 2151845736U, // FSUB_ZPmZ_S |
| 541167464U, // FSUB_ZZZ_D |
| 71438184U, // FSUB_ZZZ_H |
| 541233000U, // FSUB_ZZZ_S |
| 1615016882U, // FSUBv2f32 |
| 1615008351U, // FSUBv2f64 |
| 1615010429U, // FSUBv4f16 |
| 1615018838U, // FSUBv4f32 |
| 1615012290U, // FSUBv8f16 |
| 541169393U, // FTMAD_ZZI_D |
| 71440113U, // FTMAD_ZZI_H |
| 541234929U, // FTMAD_ZZI_S |
| 541175166U, // FTSMUL_ZZZ_D |
| 71445886U, // FTSMUL_ZZZ_H |
| 541240702U, // FTSMUL_ZZZ_S |
| 541174754U, // FTSSEL_ZZZ_D |
| 71445474U, // FTSSEL_ZZZ_H |
| 541240290U, // FTSSEL_ZZZ_S |
| 3288810686U, // FVDOT_VG2_M2ZZI_HtoS |
| 2714043129U, // GLD1B_D_IMM_REAL |
| 2714043129U, // GLD1B_D_REAL |
| 2714043129U, // GLD1B_D_SXTW_REAL |
| 2714043129U, // GLD1B_D_UXTW_REAL |
| 2714108665U, // GLD1B_S_IMM_REAL |
| 2714108665U, // GLD1B_S_SXTW_REAL |
| 2714108665U, // GLD1B_S_UXTW_REAL |
| 2714046596U, // GLD1D_IMM_REAL |
| 2714046596U, // GLD1D_REAL |
| 2714046596U, // GLD1D_SCALED_REAL |
| 2714046596U, // GLD1D_SXTW_REAL |
| 2714046596U, // GLD1D_SXTW_SCALED_REAL |
| 2714046596U, // GLD1D_UXTW_REAL |
| 2714046596U, // GLD1D_UXTW_SCALED_REAL |
| 2714048859U, // GLD1H_D_IMM_REAL |
| 2714048859U, // GLD1H_D_REAL |
| 2714048859U, // GLD1H_D_SCALED_REAL |
| 2714048859U, // GLD1H_D_SXTW_REAL |
| 2714048859U, // GLD1H_D_SXTW_SCALED_REAL |
| 2714048859U, // GLD1H_D_UXTW_REAL |
| 2714048859U, // GLD1H_D_UXTW_SCALED_REAL |
| 2714114395U, // GLD1H_S_IMM_REAL |
| 2714114395U, // GLD1H_S_SXTW_REAL |
| 2714114395U, // GLD1H_S_SXTW_SCALED_REAL |
| 2714114395U, // GLD1H_S_UXTW_REAL |
| 2714114395U, // GLD1H_S_UXTW_SCALED_REAL |
| 2714710162U, // GLD1Q |
| 2714046152U, // GLD1SB_D_IMM_REAL |
| 2714046152U, // GLD1SB_D_REAL |
| 2714046152U, // GLD1SB_D_SXTW_REAL |
| 2714046152U, // GLD1SB_D_UXTW_REAL |
| 2714111688U, // GLD1SB_S_IMM_REAL |
| 2714111688U, // GLD1SB_S_SXTW_REAL |
| 2714111688U, // GLD1SB_S_UXTW_REAL |
| 2714052981U, // GLD1SH_D_IMM_REAL |
| 2714052981U, // GLD1SH_D_REAL |
| 2714052981U, // GLD1SH_D_SCALED_REAL |
| 2714052981U, // GLD1SH_D_SXTW_REAL |
| 2714052981U, // GLD1SH_D_SXTW_SCALED_REAL |
| 2714052981U, // GLD1SH_D_UXTW_REAL |
| 2714052981U, // GLD1SH_D_UXTW_SCALED_REAL |
| 2714118517U, // GLD1SH_S_IMM_REAL |
| 2714118517U, // GLD1SH_S_SXTW_REAL |
| 2714118517U, // GLD1SH_S_SXTW_SCALED_REAL |
| 2714118517U, // GLD1SH_S_UXTW_REAL |
| 2714118517U, // GLD1SH_S_UXTW_SCALED_REAL |
| 2714060582U, // GLD1SW_D_IMM_REAL |
| 2714060582U, // GLD1SW_D_REAL |
| 2714060582U, // GLD1SW_D_SCALED_REAL |
| 2714060582U, // GLD1SW_D_SXTW_REAL |
| 2714060582U, // GLD1SW_D_SXTW_SCALED_REAL |
| 2714060582U, // GLD1SW_D_UXTW_REAL |
| 2714060582U, // GLD1SW_D_UXTW_SCALED_REAL |
| 2714060415U, // GLD1W_D_IMM_REAL |
| 2714060415U, // GLD1W_D_REAL |
| 2714060415U, // GLD1W_D_SCALED_REAL |
| 2714060415U, // GLD1W_D_SXTW_REAL |
| 2714060415U, // GLD1W_D_SXTW_SCALED_REAL |
| 2714060415U, // GLD1W_D_UXTW_REAL |
| 2714060415U, // GLD1W_D_UXTW_SCALED_REAL |
| 2714125951U, // GLD1W_IMM_REAL |
| 2714125951U, // GLD1W_SXTW_REAL |
| 2714125951U, // GLD1W_SXTW_SCALED_REAL |
| 2714125951U, // GLD1W_UXTW_REAL |
| 2714125951U, // GLD1W_UXTW_SCALED_REAL |
| 2714043135U, // GLDFF1B_D_IMM_REAL |
| 2714043135U, // GLDFF1B_D_REAL |
| 2714043135U, // GLDFF1B_D_SXTW_REAL |
| 2714043135U, // GLDFF1B_D_UXTW_REAL |
| 2714108671U, // GLDFF1B_S_IMM_REAL |
| 2714108671U, // GLDFF1B_S_SXTW_REAL |
| 2714108671U, // GLDFF1B_S_UXTW_REAL |
| 2714046602U, // GLDFF1D_IMM_REAL |
| 2714046602U, // GLDFF1D_REAL |
| 2714046602U, // GLDFF1D_SCALED_REAL |
| 2714046602U, // GLDFF1D_SXTW_REAL |
| 2714046602U, // GLDFF1D_SXTW_SCALED_REAL |
| 2714046602U, // GLDFF1D_UXTW_REAL |
| 2714046602U, // GLDFF1D_UXTW_SCALED_REAL |
| 2714048865U, // GLDFF1H_D_IMM_REAL |
| 2714048865U, // GLDFF1H_D_REAL |
| 2714048865U, // GLDFF1H_D_SCALED_REAL |
| 2714048865U, // GLDFF1H_D_SXTW_REAL |
| 2714048865U, // GLDFF1H_D_SXTW_SCALED_REAL |
| 2714048865U, // GLDFF1H_D_UXTW_REAL |
| 2714048865U, // GLDFF1H_D_UXTW_SCALED_REAL |
| 2714114401U, // GLDFF1H_S_IMM_REAL |
| 2714114401U, // GLDFF1H_S_SXTW_REAL |
| 2714114401U, // GLDFF1H_S_SXTW_SCALED_REAL |
| 2714114401U, // GLDFF1H_S_UXTW_REAL |
| 2714114401U, // GLDFF1H_S_UXTW_SCALED_REAL |
| 2714046159U, // GLDFF1SB_D_IMM_REAL |
| 2714046159U, // GLDFF1SB_D_REAL |
| 2714046159U, // GLDFF1SB_D_SXTW_REAL |
| 2714046159U, // GLDFF1SB_D_UXTW_REAL |
| 2714111695U, // GLDFF1SB_S_IMM_REAL |
| 2714111695U, // GLDFF1SB_S_SXTW_REAL |
| 2714111695U, // GLDFF1SB_S_UXTW_REAL |
| 2714052988U, // GLDFF1SH_D_IMM_REAL |
| 2714052988U, // GLDFF1SH_D_REAL |
| 2714052988U, // GLDFF1SH_D_SCALED_REAL |
| 2714052988U, // GLDFF1SH_D_SXTW_REAL |
| 2714052988U, // GLDFF1SH_D_SXTW_SCALED_REAL |
| 2714052988U, // GLDFF1SH_D_UXTW_REAL |
| 2714052988U, // GLDFF1SH_D_UXTW_SCALED_REAL |
| 2714118524U, // GLDFF1SH_S_IMM_REAL |
| 2714118524U, // GLDFF1SH_S_SXTW_REAL |
| 2714118524U, // GLDFF1SH_S_SXTW_SCALED_REAL |
| 2714118524U, // GLDFF1SH_S_UXTW_REAL |
| 2714118524U, // GLDFF1SH_S_UXTW_SCALED_REAL |
| 2714060589U, // GLDFF1SW_D_IMM_REAL |
| 2714060589U, // GLDFF1SW_D_REAL |
| 2714060589U, // GLDFF1SW_D_SCALED_REAL |
| 2714060589U, // GLDFF1SW_D_SXTW_REAL |
| 2714060589U, // GLDFF1SW_D_SXTW_SCALED_REAL |
| 2714060589U, // GLDFF1SW_D_UXTW_REAL |
| 2714060589U, // GLDFF1SW_D_UXTW_SCALED_REAL |
| 2714060421U, // GLDFF1W_D_IMM_REAL |
| 2714060421U, // GLDFF1W_D_REAL |
| 2714060421U, // GLDFF1W_D_SCALED_REAL |
| 2714060421U, // GLDFF1W_D_SXTW_REAL |
| 2714060421U, // GLDFF1W_D_SXTW_SCALED_REAL |
| 2714060421U, // GLDFF1W_D_UXTW_REAL |
| 2714060421U, // GLDFF1W_D_UXTW_SCALED_REAL |
| 2714125957U, // GLDFF1W_IMM_REAL |
| 2714125957U, // GLDFF1W_SXTW_REAL |
| 2714125957U, // GLDFF1W_SXTW_SCALED_REAL |
| 2714125957U, // GLDFF1W_UXTW_REAL |
| 2714125957U, // GLDFF1W_UXTW_SCALED_REAL |
| 4237887U, // GMI |
| 1033270U, // HINT |
| 2151793691U, // HISTCNT_ZPzZZ_D |
| 2151859227U, // HISTCNT_ZPzZZ_S |
| 4266163U, // HISTSEG_ZZZ |
| 770987U, // HLT |
| 757782U, // HVC |
| 541101009U, // INCB_XPiI |
| 541103907U, // INCD_XPiI |
| 541169443U, // INCD_ZPiI |
| 541108150U, // INCH_XPiI |
| 104998838U, // INCH_ZPiI |
| 4239118U, // INCP_XP_B |
| 541110030U, // INCP_XP_D |
| 3762335502U, // INCP_XP_H |
| 541110030U, // INCP_XP_S |
| 2151788302U, // INCP_ZP_D |
| 3305254670U, // INCP_ZP_H |
| 2688724750U, // INCP_ZP_S |
| 541116146U, // INCW_XPiI |
| 541247218U, // INCW_ZPiI |
| 3225503703U, // INDEX_II_B |
| 4310999U, // INDEX_II_D |
| 3913435095U, // INDEX_II_H |
| 4376535U, // INDEX_II_S |
| 3225503703U, // INDEX_IR_B |
| 4310999U, // INDEX_IR_D |
| 1765951447U, // INDEX_IR_H |
| 4376535U, // INDEX_IR_S |
| 4278231U, // INDEX_RI_B |
| 4310999U, // INDEX_RI_D |
| 113395671U, // INDEX_RI_H |
| 4376535U, // INDEX_RI_S |
| 4278231U, // INDEX_RR_B |
| 4310999U, // INDEX_RR_D |
| 113395671U, // INDEX_RR_H |
| 4376535U, // INDEX_RR_S |
| 160432810U, // INSERT_MXIPZ_H_B |
| 160432810U, // INSERT_MXIPZ_H_D |
| 160432810U, // INSERT_MXIPZ_H_H |
| 160432810U, // INSERT_MXIPZ_H_Q |
| 160432810U, // INSERT_MXIPZ_H_S |
| 160465578U, // INSERT_MXIPZ_V_B |
| 160465578U, // INSERT_MXIPZ_V_D |
| 160465578U, // INSERT_MXIPZ_V_H |
| 160465578U, // INSERT_MXIPZ_V_Q |
| 160465578U, // INSERT_MXIPZ_V_S |
| 1614885412U, // INSR_ZR_B |
| 1614918180U, // INSR_ZR_D |
| 3380752932U, // INSR_ZR_H |
| 1614983716U, // INSR_ZR_S |
| 4272676U, // INSR_ZV_B |
| 541176356U, // INSR_ZV_D |
| 3347198500U, // INSR_ZV_H |
| 1078112804U, // INSR_ZV_S |
| 151263540U, // INSvi16gpr |
| 1761876276U, // INSvi16lane |
| 151270140U, // INSvi32gpr |
| 1761882876U, // INSvi32lane |
| 151261240U, // INSvi64gpr |
| 1761873976U, // INSvi64lane |
| 151257826U, // INSvi8gpr |
| 1761870562U, // INSvi8lane |
| 4233404U, // IRG |
| 888565U, // ISB |
| 2151711388U, // LASTA_RPZ_B |
| 2151711388U, // LASTA_RPZ_D |
| 2151711388U, // LASTA_RPZ_H |
| 2151711388U, // LASTA_RPZ_S |
| 2151711388U, // LASTA_VPZ_B |
| 2151711388U, // LASTA_VPZ_D |
| 2151711388U, // LASTA_VPZ_H |
| 2151711388U, // LASTA_VPZ_S |
| 2151714644U, // LASTB_RPZ_B |
| 2151714644U, // LASTB_RPZ_D |
| 2151714644U, // LASTB_RPZ_H |
| 2151714644U, // LASTB_RPZ_S |
| 2151714644U, // LASTB_VPZ_B |
| 2151714644U, // LASTB_VPZ_D |
| 2151714644U, // LASTB_VPZ_H |
| 2151714644U, // LASTB_VPZ_S |
| 2714010361U, // LD1B |
| 2848228089U, // LD1B_2Z |
| 2848228089U, // LD1B_2Z_IMM |
| 2848228089U, // LD1B_4Z |
| 2848228089U, // LD1B_4Z_IMM |
| 2714043129U, // LD1B_D |
| 2714043129U, // LD1B_D_IMM_REAL |
| 2714075897U, // LD1B_H |
| 2714075897U, // LD1B_H_IMM_REAL |
| 2714010361U, // LD1B_IMM_REAL |
| 2714108665U, // LD1B_S |
| 2714108665U, // LD1B_S_IMM_REAL |
| 2152792825U, // LD1B_VG2_M2ZPXI |
| 2152792825U, // LD1B_VG2_M2ZPXX |
| 2848228089U, // LD1B_VG4_M4ZPXI |
| 2848228089U, // LD1B_VG4_M4ZPXX |
| 2714046596U, // LD1D |
| 2848264324U, // LD1D_2Z |
| 2848264324U, // LD1D_2Z_IMM |
| 2848264324U, // LD1D_4Z |
| 2848264324U, // LD1D_4Z_IMM |
| 2714046596U, // LD1D_IMM_REAL |
| 2714701956U, // LD1D_Q |
| 2714701956U, // LD1D_Q_IMM |
| 2848264324U, // LD1D_VG2_M2ZPXI |
| 2848264324U, // LD1D_VG2_M2ZPXX |
| 2848264324U, // LD1D_VG4_M4ZPXI |
| 2848264324U, // LD1D_VG4_M4ZPXX |
| 1146890U, // LD1Fourv16b |
| 168951818U, // LD1Fourv16b_POST |
| 1212426U, // LD1Fourv1d |
| 173211658U, // LD1Fourv1d_POST |
| 1277962U, // LD1Fourv2d |
| 169082890U, // LD1Fourv2d_POST |
| 1343498U, // LD1Fourv2s |
| 173342730U, // LD1Fourv2s_POST |
| 1409034U, // LD1Fourv4h |
| 173408266U, // LD1Fourv4h_POST |
| 1474570U, // LD1Fourv4s |
| 169279498U, // LD1Fourv4s_POST |
| 1540106U, // LD1Fourv8b |
| 173539338U, // LD1Fourv8b_POST |
| 1605642U, // LD1Fourv8h |
| 169410570U, // LD1Fourv8h_POST |
| 2714081627U, // LD1H |
| 2848299355U, // LD1H_2Z |
| 2848299355U, // LD1H_2Z_IMM |
| 2848299355U, // LD1H_4Z |
| 2848299355U, // LD1H_4Z_IMM |
| 2714048859U, // LD1H_D |
| 2714048859U, // LD1H_D_IMM_REAL |
| 2714081627U, // LD1H_IMM_REAL |
| 2714114395U, // LD1H_S |
| 2714114395U, // LD1H_S_IMM_REAL |
| 2153355611U, // LD1H_VG2_M2ZPXI |
| 2153355611U, // LD1H_VG2_M2ZPXX |
| 2848299355U, // LD1H_VG4_M4ZPXI |
| 2848299355U, // LD1H_VG4_M4ZPXX |
| 1146890U, // LD1Onev16b |
| 177340426U, // LD1Onev16b_POST |
| 1212426U, // LD1Onev1d |
| 181600266U, // LD1Onev1d_POST |
| 1277962U, // LD1Onev2d |
| 177471498U, // LD1Onev2d_POST |
| 1343498U, // LD1Onev2s |
| 181731338U, // LD1Onev2s_POST |
| 1409034U, // LD1Onev4h |
| 181796874U, // LD1Onev4h_POST |
| 1474570U, // LD1Onev4s |
| 177668106U, // LD1Onev4s_POST |
| 1540106U, // LD1Onev8b |
| 181927946U, // LD1Onev8b_POST |
| 1605642U, // LD1Onev8h |
| 177799178U, // LD1Onev8h_POST |
| 2714046004U, // LD1RB_D_IMM |
| 2714078772U, // LD1RB_H_IMM |
| 2714013236U, // LD1RB_IMM |
| 2714111540U, // LD1RB_S_IMM |
| 2714048423U, // LD1RD_IMM |
| 2714052833U, // LD1RH_D_IMM |
| 2714085601U, // LD1RH_IMM |
| 2714118369U, // LD1RH_S_IMM |
| 2714013207U, // LD1RO_B |
| 2714013207U, // LD1RO_B_IMM |
| 2714048407U, // LD1RO_D |
| 2714048407U, // LD1RO_D_IMM |
| 2714085579U, // LD1RO_H |
| 2714085579U, // LD1RO_H_IMM |
| 2714126086U, // LD1RO_W |
| 2714126086U, // LD1RO_W_IMM |
| 2714013228U, // LD1RQ_B |
| 2714013228U, // LD1RQ_B_IMM |
| 2714048415U, // LD1RQ_D |
| 2714048415U, // LD1RQ_D_IMM |
| 2714085593U, // LD1RQ_H |
| 2714085593U, // LD1RQ_H_IMM |
| 2714126094U, // LD1RQ_W |
| 2714126094U, // LD1RQ_W_IMM |
| 2714046215U, // LD1RSB_D_IMM |
| 2714078983U, // LD1RSB_H_IMM |
| 2714111751U, // LD1RSB_S_IMM |
| 2714053031U, // LD1RSH_D_IMM |
| 2714118567U, // LD1RSH_S_IMM |
| 2714060623U, // LD1RSW_IMM |
| 2714060566U, // LD1RW_D_IMM |
| 2714126102U, // LD1RW_IMM |
| 1159409U, // LD1Rv16b |
| 185741553U, // LD1Rv16b_POST |
| 1224945U, // LD1Rv1d |
| 181612785U, // LD1Rv1d_POST |
| 1290481U, // LD1Rv2d |
| 181678321U, // LD1Rv2d_POST |
| 1356017U, // LD1Rv2s |
| 190132465U, // LD1Rv2s_POST |
| 1421553U, // LD1Rv4h |
| 194392305U, // LD1Rv4h_POST |
| 1487089U, // LD1Rv4s |
| 190263537U, // LD1Rv4s_POST |
| 1552625U, // LD1Rv8b |
| 186134769U, // LD1Rv8b_POST |
| 1618161U, // LD1Rv8h |
| 194588913U, // LD1Rv8h_POST |
| 2714046152U, // LD1SB_D |
| 2714046152U, // LD1SB_D_IMM_REAL |
| 2714078920U, // LD1SB_H |
| 2714078920U, // LD1SB_H_IMM_REAL |
| 2714111688U, // LD1SB_S |
| 2714111688U, // LD1SB_S_IMM_REAL |
| 2714052981U, // LD1SH_D |
| 2714052981U, // LD1SH_D_IMM_REAL |
| 2714118517U, // LD1SH_S |
| 2714118517U, // LD1SH_S_IMM_REAL |
| 2714060582U, // LD1SW_D |
| 2714060582U, // LD1SW_D_IMM_REAL |
| 1146890U, // LD1Threev16b |
| 198311946U, // LD1Threev16b_POST |
| 1212426U, // LD1Threev1d |
| 202571786U, // LD1Threev1d_POST |
| 1277962U, // LD1Threev2d |
| 198443018U, // LD1Threev2d_POST |
| 1343498U, // LD1Threev2s |
| 202702858U, // LD1Threev2s_POST |
| 1409034U, // LD1Threev4h |
| 202768394U, // LD1Threev4h_POST |
| 1474570U, // LD1Threev4s |
| 198639626U, // LD1Threev4s_POST |
| 1540106U, // LD1Threev8b |
| 202899466U, // LD1Threev8b_POST |
| 1605642U, // LD1Threev8h |
| 198770698U, // LD1Threev8h_POST |
| 1146890U, // LD1Twov16b |
| 173146122U, // LD1Twov16b_POST |
| 1212426U, // LD1Twov1d |
| 177405962U, // LD1Twov1d_POST |
| 1277962U, // LD1Twov2d |
| 173277194U, // LD1Twov2d_POST |
| 1343498U, // LD1Twov2s |
| 177537034U, // LD1Twov2s_POST |
| 1409034U, // LD1Twov4h |
| 177602570U, // LD1Twov4h_POST |
| 1474570U, // LD1Twov4s |
| 173473802U, // LD1Twov4s_POST |
| 1540106U, // LD1Twov8b |
| 177733642U, // LD1Twov8b_POST |
| 1605642U, // LD1Twov8h |
| 173604874U, // LD1Twov8h_POST |
| 2714125951U, // LD1W |
| 2848343679U, // LD1W_2Z |
| 2848343679U, // LD1W_2Z_IMM |
| 2848343679U, // LD1W_4Z |
| 2848343679U, // LD1W_4Z_IMM |
| 2714060415U, // LD1W_D |
| 2714060415U, // LD1W_D_IMM_REAL |
| 2714125951U, // LD1W_IMM_REAL |
| 2714715775U, // LD1W_Q |
| 2714715775U, // LD1W_Q_IMM |
| 2848343679U, // LD1W_VG2_M2ZPXI |
| 2848343679U, // LD1W_VG2_M2ZPXX |
| 2848343679U, // LD1W_VG4_M4ZPXI |
| 2848343679U, // LD1W_VG4_M4ZPXX |
| 114315097U, // LD1_MXIPXX_H_B |
| 114315111U, // LD1_MXIPXX_H_D |
| 114315125U, // LD1_MXIPXX_H_H |
| 114315139U, // LD1_MXIPXX_H_Q |
| 114315153U, // LD1_MXIPXX_H_S |
| 114347865U, // LD1_MXIPXX_V_B |
| 114347879U, // LD1_MXIPXX_V_D |
| 114347893U, // LD1_MXIPXX_V_H |
| 114347907U, // LD1_MXIPXX_V_Q |
| 114347921U, // LD1_MXIPXX_V_S |
| 207224842U, // LD1i16 |
| 211451914U, // LD1i16_POST |
| 207290378U, // LD1i32 |
| 215711754U, // LD1i32_POST |
| 207355914U, // LD1i64 |
| 219971594U, // LD1i64_POST |
| 207421450U, // LD1i8 |
| 224231434U, // LD1i8_POST |
| 2714010413U, // LD2B |
| 2714010413U, // LD2B_IMM |
| 2714048192U, // LD2D |
| 2714048192U, // LD2D_IMM |
| 2714081733U, // LD2H |
| 2714081733U, // LD2H_IMM |
| 2714710174U, // LD2Q |
| 2714710174U, // LD2Q_IMM |
| 1159415U, // LD2Rv16b |
| 194130167U, // LD2Rv16b_POST |
| 1224951U, // LD2Rv1d |
| 177418487U, // LD2Rv1d_POST |
| 1290487U, // LD2Rv2d |
| 177484023U, // LD2Rv2d_POST |
| 1356023U, // LD2Rv2s |
| 181743863U, // LD2Rv2s_POST |
| 1421559U, // LD2Rv4h |
| 190198007U, // LD2Rv4h_POST |
| 1487095U, // LD2Rv4s |
| 181874935U, // LD2Rv4s_POST |
| 1552631U, // LD2Rv8b |
| 194523383U, // LD2Rv8b_POST |
| 1618167U, // LD2Rv8h |
| 190394615U, // LD2Rv8h_POST |
| 1146965U, // LD2Twov16b |
| 173146197U, // LD2Twov16b_POST |
| 1278037U, // LD2Twov2d |
| 173277269U, // LD2Twov2d_POST |
| 1343573U, // LD2Twov2s |
| 177537109U, // LD2Twov2s_POST |
| 1409109U, // LD2Twov4h |
| 177602645U, // LD2Twov4h_POST |
| 1474645U, // LD2Twov4s |
| 173473877U, // LD2Twov4s_POST |
| 1540181U, // LD2Twov8b |
| 177733717U, // LD2Twov8b_POST |
| 1605717U, // LD2Twov8h |
| 173604949U, // LD2Twov8h_POST |
| 2714126003U, // LD2W |
| 2714126003U, // LD2W_IMM |
| 207224917U, // LD2i16 |
| 215646293U, // LD2i16_POST |
| 207290453U, // LD2i32 |
| 219906133U, // LD2i32_POST |
| 207355989U, // LD2i64 |
| 228360277U, // LD2i64_POST |
| 207421525U, // LD2i8 |
| 211648597U, // LD2i8_POST |
| 2714010425U, // LD3B |
| 2714010425U, // LD3B_IMM |
| 2714048204U, // LD3D |
| 2714048204U, // LD3D_IMM |
| 2714081745U, // LD3H |
| 2714081745U, // LD3H_IMM |
| 2714710186U, // LD3Q |
| 2714710186U, // LD3Q_IMM |
| 1159421U, // LD3Rv16b |
| 231878909U, // LD3Rv16b_POST |
| 1224957U, // LD3Rv1d |
| 202584317U, // LD3Rv1d_POST |
| 1290493U, // LD3Rv2d |
| 202649853U, // LD3Rv2d_POST |
| 1356029U, // LD3Rv2s |
| 236269821U, // LD3Rv2s_POST |
| 1421565U, // LD3Rv4h |
| 240529661U, // LD3Rv4h_POST |
| 1487101U, // LD3Rv4s |
| 236400893U, // LD3Rv4s_POST |
| 1552637U, // LD3Rv8b |
| 232272125U, // LD3Rv8b_POST |
| 1618173U, // LD3Rv8h |
| 240726269U, // LD3Rv8h_POST |
| 1147062U, // LD3Threev16b |
| 198312118U, // LD3Threev16b_POST |
| 1278134U, // LD3Threev2d |
| 198443190U, // LD3Threev2d_POST |
| 1343670U, // LD3Threev2s |
| 202703030U, // LD3Threev2s_POST |
| 1409206U, // LD3Threev4h |
| 202768566U, // LD3Threev4h_POST |
| 1474742U, // LD3Threev4s |
| 198639798U, // LD3Threev4s_POST |
| 1540278U, // LD3Threev8b |
| 202899638U, // LD3Threev8b_POST |
| 1605814U, // LD3Threev8h |
| 198770870U, // LD3Threev8h_POST |
| 2714126015U, // LD3W |
| 2714126015U, // LD3W_IMM |
| 207225014U, // LD3i16 |
| 245006518U, // LD3i16_POST |
| 207290550U, // LD3i32 |
| 249266358U, // LD3i32_POST |
| 207356086U, // LD3i64 |
| 253526198U, // LD3i64_POST |
| 207421622U, // LD3i8 |
| 257786038U, // LD3i8_POST |
| 2714010451U, // LD4B |
| 2714010451U, // LD4B_IMM |
| 2714048216U, // LD4D |
| 2714048216U, // LD4D_IMM |
| 1147085U, // LD4Fourv16b |
| 168952013U, // LD4Fourv16b_POST |
| 1278157U, // LD4Fourv2d |
| 169083085U, // LD4Fourv2d_POST |
| 1343693U, // LD4Fourv2s |
| 173342925U, // LD4Fourv2s_POST |
| 1409229U, // LD4Fourv4h |
| 173408461U, // LD4Fourv4h_POST |
| 1474765U, // LD4Fourv4s |
| 169279693U, // LD4Fourv4s_POST |
| 1540301U, // LD4Fourv8b |
| 173539533U, // LD4Fourv8b_POST |
| 1605837U, // LD4Fourv8h |
| 169410765U, // LD4Fourv8h_POST |
| 2714083228U, // LD4H |
| 2714083228U, // LD4H_IMM |
| 2714710198U, // LD4Q |
| 2714710198U, // LD4Q_IMM |
| 1159427U, // LD4Rv16b |
| 189935875U, // LD4Rv16b_POST |
| 1224963U, // LD4Rv1d |
| 173224195U, // LD4Rv1d_POST |
| 1290499U, // LD4Rv2d |
| 173289731U, // LD4Rv2d_POST |
| 1356035U, // LD4Rv2s |
| 177549571U, // LD4Rv2s_POST |
| 1421571U, // LD4Rv4h |
| 181809411U, // LD4Rv4h_POST |
| 1487107U, // LD4Rv4s |
| 177680643U, // LD4Rv4s_POST |
| 1552643U, // LD4Rv8b |
| 190329091U, // LD4Rv8b_POST |
| 1618179U, // LD4Rv8h |
| 182006019U, // LD4Rv8h_POST |
| 2714126027U, // LD4W |
| 2714126027U, // LD4W_IMM |
| 207225037U, // LD4i16 |
| 219840717U, // LD4i16_POST |
| 207290573U, // LD4i32 |
| 228294861U, // LD4i32_POST |
| 207356109U, // LD4i64 |
| 261914829U, // LD4i64_POST |
| 207421645U, // LD4i8 |
| 215843021U, // LD4i8_POST |
| 1966917U, // LD64B |
| 2689174344U, // LDADDAB |
| 2689181484U, // LDADDAH |
| 2689174566U, // LDADDALB |
| 2689181658U, // LDADDALH |
| 2689182320U, // LDADDALW |
| 2689182320U, // LDADDALX |
| 2689171724U, // LDADDAW |
| 2689171724U, // LDADDAX |
| 2689174502U, // LDADDB |
| 2689181644U, // LDADDH |
| 2689174747U, // LDADDLB |
| 2689181758U, // LDADDLH |
| 2689182644U, // LDADDLW |
| 2689182644U, // LDADDLX |
| 2689177408U, // LDADDW |
| 2689177408U, // LDADDX |
| 207355931U, // LDAP1 |
| 75533935U, // LDAPRB |
| 75540764U, // LDAPRH |
| 75543031U, // LDAPRW |
| 1686745591U, // LDAPRWpre |
| 75543031U, // LDAPRX |
| 1686745591U, // LDAPRXpre |
| 75533978U, // LDAPURBi |
| 75540807U, // LDAPURHi |
| 75534118U, // LDAPURSBWi |
| 75534118U, // LDAPURSBXi |
| 75540934U, // LDAPURSHWi |
| 75540934U, // LDAPURSHXi |
| 75548526U, // LDAPURSWi |
| 75543118U, // LDAPURXi |
| 75543118U, // LDAPURbi |
| 75543118U, // LDAPURdi |
| 75543118U, // LDAPURhi |
| 75543118U, // LDAPURi |
| 75543118U, // LDAPURqi |
| 75543118U, // LDAPURsi |
| 75533883U, // LDARB |
| 75540712U, // LDARH |
| 75542793U, // LDARW |
| 75542793U, // LDARX |
| 4239433U, // LDAXPW |
| 4239433U, // LDAXPX |
| 75533994U, // LDAXRB |
| 75540823U, // LDAXRH |
| 75543162U, // LDAXRW |
| 75543162U, // LDAXRX |
| 2689174400U, // LDCLRAB |
| 2689181541U, // LDCLRAH |
| 2689174641U, // LDCLRALB |
| 2689181698U, // LDCLRALH |
| 2689182513U, // LDCLRALW |
| 2689182513U, // LDCLRALX |
| 2689172008U, // LDCLRAW |
| 2689172008U, // LDCLRAX |
| 2689175120U, // LDCLRB |
| 2689181949U, // LDCLRH |
| 2689174849U, // LDCLRLB |
| 2689181794U, // LDCLRLH |
| 2689182951U, // LDCLRLW |
| 2689182951U, // LDCLRLX |
| 6205392U, // LDCLRP |
| 6193597U, // LDCLRPA |
| 6204099U, // LDCLRPAL |
| 6204539U, // LDCLRPL |
| 2689184137U, // LDCLRW |
| 2689184137U, // LDCLRX |
| 2689174409U, // LDEORAB |
| 2689181550U, // LDEORAH |
| 2689174651U, // LDEORALB |
| 2689181708U, // LDEORALH |
| 2689182543U, // LDEORALW |
| 2689182543U, // LDEORALX |
| 2689172035U, // LDEORAW |
| 2689172035U, // LDEORAX |
| 2689175143U, // LDEORB |
| 2689181972U, // LDEORH |
| 2689174858U, // LDEORLB |
| 2689181803U, // LDEORLH |
| 2689182978U, // LDEORLW |
| 2689182978U, // LDEORLX |
| 2689184230U, // LDEORW |
| 2689184230U, // LDEORX |
| 2714043135U, // LDFF1B_D_REAL |
| 2714075903U, // LDFF1B_H_REAL |
| 2714010367U, // LDFF1B_REAL |
| 2714108671U, // LDFF1B_S_REAL |
| 2714046602U, // LDFF1D_REAL |
| 2714048865U, // LDFF1H_D_REAL |
| 2714081633U, // LDFF1H_REAL |
| 2714114401U, // LDFF1H_S_REAL |
| 2714046159U, // LDFF1SB_D_REAL |
| 2714078927U, // LDFF1SB_H_REAL |
| 2714111695U, // LDFF1SB_S_REAL |
| 2714052988U, // LDFF1SH_D_REAL |
| 2714118524U, // LDFF1SH_S_REAL |
| 2714060589U, // LDFF1SW_D_REAL |
| 2714060421U, // LDFF1W_D_REAL |
| 2714125957U, // LDFF1W_REAL |
| 1686739098U, // LDG |
| 75541959U, // LDGM |
| 4239273U, // LDIAPPW |
| 1615441833U, // LDIAPPWpre |
| 4239273U, // LDIAPPX |
| 1615441833U, // LDIAPPXpre |
| 75533890U, // LDLARB |
| 75540719U, // LDLARH |
| 75542799U, // LDLARW |
| 75542799U, // LDLARX |
| 2714043143U, // LDNF1B_D_IMM_REAL |
| 2714075911U, // LDNF1B_H_IMM_REAL |
| 2714010375U, // LDNF1B_IMM_REAL |
| 2714108679U, // LDNF1B_S_IMM_REAL |
| 2714046610U, // LDNF1D_IMM_REAL |
| 2714048873U, // LDNF1H_D_IMM_REAL |
| 2714081641U, // LDNF1H_IMM_REAL |
| 2714114409U, // LDNF1H_S_IMM_REAL |
| 2714046168U, // LDNF1SB_D_IMM_REAL |
| 2714078936U, // LDNF1SB_H_IMM_REAL |
| 2714111704U, // LDNF1SB_S_IMM_REAL |
| 2714052997U, // LDNF1SH_D_IMM_REAL |
| 2714118533U, // LDNF1SH_S_IMM_REAL |
| 2714060598U, // LDNF1SW_D_IMM_REAL |
| 2714060429U, // LDNF1W_D_IMM_REAL |
| 2714125965U, // LDNF1W_IMM_REAL |
| 4239240U, // LDNPDi |
| 4239240U, // LDNPQi |
| 4239240U, // LDNPSi |
| 4239240U, // LDNPWi |
| 4239240U, // LDNPXi |
| 2848228111U, // LDNT1B_2Z |
| 2848228111U, // LDNT1B_2Z_IMM |
| 2848228111U, // LDNT1B_4Z |
| 2848228111U, // LDNT1B_4Z_IMM |
| 2152792847U, // LDNT1B_VG2_M2ZPXI |
| 2152792847U, // LDNT1B_VG2_M2ZPXX |
| 2848228111U, // LDNT1B_VG4_M4ZPXI |
| 2848228111U, // LDNT1B_VG4_M4ZPXX |
| 2714010383U, // LDNT1B_ZRI |
| 2714010383U, // LDNT1B_ZRR |
| 2714043151U, // LDNT1B_ZZR_D_REAL |
| 2714108687U, // LDNT1B_ZZR_S_REAL |
| 2848264346U, // LDNT1D_2Z |
| 2848264346U, // LDNT1D_2Z_IMM |
| 2848264346U, // LDNT1D_4Z |
| 2848264346U, // LDNT1D_4Z_IMM |
| 2848264346U, // LDNT1D_VG2_M2ZPXI |
| 2848264346U, // LDNT1D_VG2_M2ZPXX |
| 2848264346U, // LDNT1D_VG4_M4ZPXI |
| 2848264346U, // LDNT1D_VG4_M4ZPXX |
| 2714046618U, // LDNT1D_ZRI |
| 2714046618U, // LDNT1D_ZRR |
| 2714046618U, // LDNT1D_ZZR_D_REAL |
| 2848299377U, // LDNT1H_2Z |
| 2848299377U, // LDNT1H_2Z_IMM |
| 2848299377U, // LDNT1H_4Z |
| 2848299377U, // LDNT1H_4Z_IMM |
| 2153355633U, // LDNT1H_VG2_M2ZPXI |
| 2153355633U, // LDNT1H_VG2_M2ZPXX |
| 2848299377U, // LDNT1H_VG4_M4ZPXI |
| 2848299377U, // LDNT1H_VG4_M4ZPXX |
| 2714081649U, // LDNT1H_ZRI |
| 2714081649U, // LDNT1H_ZRR |
| 2714048881U, // LDNT1H_ZZR_D_REAL |
| 2714114417U, // LDNT1H_ZZR_S_REAL |
| 2714046177U, // LDNT1SB_ZZR_D_REAL |
| 2714111713U, // LDNT1SB_ZZR_S_REAL |
| 2714053006U, // LDNT1SH_ZZR_D_REAL |
| 2714118542U, // LDNT1SH_ZZR_S_REAL |
| 2714060607U, // LDNT1SW_ZZR_D_REAL |
| 2848343701U, // LDNT1W_2Z |
| 2848343701U, // LDNT1W_2Z_IMM |
| 2848343701U, // LDNT1W_4Z |
| 2848343701U, // LDNT1W_4Z_IMM |
| 2848343701U, // LDNT1W_VG2_M2ZPXI |
| 2848343701U, // LDNT1W_VG2_M2ZPXX |
| 2848343701U, // LDNT1W_VG4_M4ZPXI |
| 2848343701U, // LDNT1W_VG4_M4ZPXX |
| 2714125973U, // LDNT1W_ZRI |
| 2714125973U, // LDNT1W_ZRR |
| 2714060437U, // LDNT1W_ZZR_D_REAL |
| 2714125973U, // LDNT1W_ZZR_S_REAL |
| 4239139U, // LDPDi |
| 1615441699U, // LDPDpost |
| 1615441699U, // LDPDpre |
| 4239139U, // LDPQi |
| 1615441699U, // LDPQpost |
| 1615441699U, // LDPQpre |
| 4245320U, // LDPSWi |
| 1615447880U, // LDPSWpost |
| 1615447880U, // LDPSWpre |
| 4239139U, // LDPSi |
| 1615441699U, // LDPSpost |
| 1615441699U, // LDPSpre |
| 4239139U, // LDPWi |
| 1615441699U, // LDPWpost |
| 1615441699U, // LDPWpre |
| 4239139U, // LDPXi |
| 1615441699U, // LDPXpost |
| 1615441699U, // LDPXpre |
| 75530475U, // LDRAAindexed |
| 1686733035U, // LDRAAwriteback |
| 75533170U, // LDRABindexed |
| 1686735730U, // LDRABwriteback |
| 1686736458U, // LDRBBpost |
| 1686736458U, // LDRBBpre |
| 75533898U, // LDRBBroW |
| 75533898U, // LDRBBroX |
| 75533898U, // LDRBBui |
| 1686745415U, // LDRBpost |
| 1686745415U, // LDRBpre |
| 75542855U, // LDRBroW |
| 75542855U, // LDRBroX |
| 75542855U, // LDRBui |
| 3762336071U, // LDRDl |
| 1686745415U, // LDRDpost |
| 1686745415U, // LDRDpre |
| 75542855U, // LDRDroW |
| 75542855U, // LDRDroX |
| 75542855U, // LDRDui |
| 1686743287U, // LDRHHpost |
| 1686743287U, // LDRHHpre |
| 75540727U, // LDRHHroW |
| 75540727U, // LDRHHroX |
| 75540727U, // LDRHHui |
| 1686745415U, // LDRHpost |
| 1686745415U, // LDRHpre |
| 75542855U, // LDRHroW |
| 75542855U, // LDRHroX |
| 75542855U, // LDRHui |
| 3762336071U, // LDRQl |
| 1686745415U, // LDRQpost |
| 1686745415U, // LDRQpre |
| 75542855U, // LDRQroW |
| 75542855U, // LDRQroX |
| 75542855U, // LDRQui |
| 1686736655U, // LDRSBWpost |
| 1686736655U, // LDRSBWpre |
| 75534095U, // LDRSBWroW |
| 75534095U, // LDRSBWroX |
| 75534095U, // LDRSBWui |
| 1686736655U, // LDRSBXpost |
| 1686736655U, // LDRSBXpre |
| 75534095U, // LDRSBXroW |
| 75534095U, // LDRSBXroX |
| 75534095U, // LDRSBXui |
| 1686743471U, // LDRSHWpost |
| 1686743471U, // LDRSHWpre |
| 75540911U, // LDRSHWroW |
| 75540911U, // LDRSHWroX |
| 75540911U, // LDRSHWui |
| 1686743471U, // LDRSHXpost |
| 1686743471U, // LDRSHXpre |
| 75540911U, // LDRSHXroW |
| 75540911U, // LDRSHXroX |
| 75540911U, // LDRSHXui |
| 3762341719U, // LDRSWl |
| 1686751063U, // LDRSWpost |
| 1686751063U, // LDRSWpre |
| 75548503U, // LDRSWroW |
| 75548503U, // LDRSWroX |
| 75548503U, // LDRSWui |
| 3762336071U, // LDRSl |
| 1686745415U, // LDRSpost |
| 1686745415U, // LDRSpre |
| 75542855U, // LDRSroW |
| 75542855U, // LDRSroX |
| 75542855U, // LDRSui |
| 3762336071U, // LDRWl |
| 1686745415U, // LDRWpost |
| 1686745415U, // LDRWpre |
| 75542855U, // LDRWroW |
| 75542855U, // LDRWroX |
| 75542855U, // LDRWui |
| 3762336071U, // LDRXl |
| 1686745415U, // LDRXpost |
| 1686745415U, // LDRXpre |
| 75542855U, // LDRXroW |
| 75542855U, // LDRXroX |
| 75542855U, // LDRXui |
| 77541703U, // LDR_PXI |
| 75542855U, // LDR_TX |
| 2076999U, // LDR_ZA |
| 77541703U, // LDR_ZXI |
| 2689174425U, // LDSETAB |
| 2689181566U, // LDSETAH |
| 2689174669U, // LDSETALB |
| 2689181726U, // LDSETALH |
| 2689182573U, // LDSETALW |
| 2689182573U, // LDSETALX |
| 2689172088U, // LDSETAW |
| 2689172088U, // LDSETAX |
| 2689175349U, // LDSETB |
| 2689182160U, // LDSETH |
| 2689174909U, // LDSETLB |
| 2689181819U, // LDSETLH |
| 2689183048U, // LDSETLW |
| 2689183048U, // LDSETLX |
| 6205444U, // LDSETP |
| 6193648U, // LDSETPA |
| 6204155U, // LDSETPAL |
| 6204598U, // LDSETPL |
| 2689188584U, // LDSETW |
| 2689188584U, // LDSETX |
| 2689174434U, // LDSMAXAB |
| 2689181575U, // LDSMAXAH |
| 2689174679U, // LDSMAXALB |
| 2689181736U, // LDSMAXALH |
| 2689182603U, // LDSMAXALW |
| 2689182603U, // LDSMAXALX |
| 2689172144U, // LDSMAXAW |
| 2689172144U, // LDSMAXAX |
| 2689175487U, // LDSMAXB |
| 2689182192U, // LDSMAXH |
| 2689174918U, // LDSMAXLB |
| 2689181861U, // LDSMAXLH |
| 2689183138U, // LDSMAXLW |
| 2689183138U, // LDSMAXLX |
| 2689189817U, // LDSMAXW |
| 2689189817U, // LDSMAXX |
| 2689174353U, // LDSMINAB |
| 2689181514U, // LDSMINAH |
| 2689174611U, // LDSMINALB |
| 2689181668U, // LDSMINALH |
| 2689182360U, // LDSMINALW |
| 2689182360U, // LDSMINALX |
| 2689171824U, // LDSMINAW |
| 2689171824U, // LDSMINAX |
| 2689174961U, // LDSMINB |
| 2689181881U, // LDSMINH |
| 2689174822U, // LDSMINLB |
| 2689181767U, // LDSMINLH |
| 2689182797U, // LDSMINLW |
| 2689182797U, // LDSMINLX |
| 2689183254U, // LDSMINW |
| 2689183254U, // LDSMINX |
| 75533943U, // LDTRBi |
| 75540772U, // LDTRHi |
| 75534102U, // LDTRSBWi |
| 75534102U, // LDTRSBXi |
| 75540918U, // LDTRSHWi |
| 75540918U, // LDTRSHXi |
| 75548510U, // LDTRSWi |
| 75543082U, // LDTRWi |
| 75543082U, // LDTRXi |
| 2689174444U, // LDUMAXAB |
| 2689181585U, // LDUMAXAH |
| 2689174690U, // LDUMAXALB |
| 2689181747U, // LDUMAXALH |
| 2689182613U, // LDUMAXALW |
| 2689182613U, // LDUMAXALX |
| 2689172153U, // LDUMAXAW |
| 2689172153U, // LDUMAXAX |
| 2689175496U, // LDUMAXB |
| 2689182201U, // LDUMAXH |
| 2689174928U, // LDUMAXLB |
| 2689181871U, // LDUMAXLH |
| 2689183147U, // LDUMAXLW |
| 2689183147U, // LDUMAXLX |
| 2689189825U, // LDUMAXW |
| 2689189825U, // LDUMAXX |
| 2689174363U, // LDUMINAB |
| 2689181524U, // LDUMINAH |
| 2689174622U, // LDUMINALB |
| 2689181679U, // LDUMINALH |
| 2689182370U, // LDUMINALW |
| 2689182370U, // LDUMINALX |
| 2689171833U, // LDUMINAW |
| 2689171833U, // LDUMINAX |
| 2689174970U, // LDUMINB |
| 2689181890U, // LDUMINH |
| 2689174832U, // LDUMINLB |
| 2689181777U, // LDUMINLH |
| 2689182806U, // LDUMINLW |
| 2689182806U, // LDUMINLX |
| 2689183262U, // LDUMINW |
| 2689183262U, // LDUMINX |
| 75533963U, // LDURBBi |
| 75543105U, // LDURBi |
| 75543105U, // LDURDi |
| 75540792U, // LDURHHi |
| 75543105U, // LDURHi |
| 75543105U, // LDURQi |
| 75534110U, // LDURSBWi |
| 75534110U, // LDURSBXi |
| 75540926U, // LDURSHWi |
| 75540926U, // LDURSHXi |
| 75548518U, // LDURSWi |
| 75543105U, // LDURSi |
| 75543105U, // LDURWi |
| 75543105U, // LDURXi |
| 4239461U, // LDXPW |
| 4239461U, // LDXPX |
| 75534002U, // LDXRB |
| 75540831U, // LDXRH |
| 75543169U, // LDXRW |
| 75543169U, // LDXRX |
| 2151756250U, // LSLR_ZPmZ_B |
| 2151789018U, // LSLR_ZPmZ_D |
| 2713858522U, // LSLR_ZPmZ_H |
| 2151854554U, // LSLR_ZPmZ_S |
| 4238631U, // LSLVWr |
| 4238631U, // LSLVXr |
| 2151755047U, // LSL_WIDE_ZPmZ_B |
| 2713857319U, // LSL_WIDE_ZPmZ_H |
| 2151853351U, // LSL_WIDE_ZPmZ_S |
| 4271399U, // LSL_WIDE_ZZZ_B |
| 71445799U, // LSL_WIDE_ZZZ_H |
| 541240615U, // LSL_WIDE_ZZZ_S |
| 2151755047U, // LSL_ZPmI_B |
| 2151787815U, // LSL_ZPmI_D |
| 2713857319U, // LSL_ZPmI_H |
| 2151853351U, // LSL_ZPmI_S |
| 2151755047U, // LSL_ZPmZ_B |
| 2151787815U, // LSL_ZPmZ_D |
| 2713857319U, // LSL_ZPmZ_H |
| 2151853351U, // LSL_ZPmZ_S |
| 4271399U, // LSL_ZZI_B |
| 541175079U, // LSL_ZZI_D |
| 71445799U, // LSL_ZZI_H |
| 541240615U, // LSL_ZZI_S |
| 2151756297U, // LSRR_ZPmZ_B |
| 2151789065U, // LSRR_ZPmZ_D |
| 2713858569U, // LSRR_ZPmZ_H |
| 2151854601U, // LSRR_ZPmZ_S |
| 4239898U, // LSRVWr |
| 4239898U, // LSRVXr |
| 2151756314U, // LSR_WIDE_ZPmZ_B |
| 2713858586U, // LSR_WIDE_ZPmZ_H |
| 2151854618U, // LSR_WIDE_ZPmZ_S |
| 4272666U, // LSR_WIDE_ZZZ_B |
| 71447066U, // LSR_WIDE_ZZZ_H |
| 541241882U, // LSR_WIDE_ZZZ_S |
| 2151756314U, // LSR_ZPmI_B |
| 2151789082U, // LSR_ZPmI_D |
| 2713858586U, // LSR_ZPmI_H |
| 2151854618U, // LSR_ZPmI_S |
| 2151756314U, // LSR_ZPmZ_B |
| 2151789082U, // LSR_ZPmZ_D |
| 2713858586U, // LSR_ZPmZ_H |
| 2151854618U, // LSR_ZPmZ_S |
| 4272666U, // LSR_ZZI_B |
| 541176346U, // LSR_ZZI_D |
| 71447066U, // LSR_ZZI_H |
| 541241882U, // LSR_ZZI_S |
| 113541210U, // LUTI2_2ZTZI_B |
| 113606746U, // LUTI2_2ZTZI_H |
| 113639514U, // LUTI2_2ZTZI_S |
| 113541210U, // LUTI2_4ZTZI_B |
| 113606746U, // LUTI2_4ZTZI_H |
| 113639514U, // LUTI2_4ZTZI_S |
| 5308506U, // LUTI2_S_2ZTZI_B |
| 5865562U, // LUTI2_S_2ZTZI_H |
| 113541210U, // LUTI2_S_4ZTZI_B |
| 113606746U, // LUTI2_S_4ZTZI_H |
| 4259930U, // LUTI2_ZTZI_B |
| 113377370U, // LUTI2_ZTZI_H |
| 4358234U, // LUTI2_ZTZI_S |
| 113541330U, // LUTI4_2ZTZI_B |
| 113606866U, // LUTI4_2ZTZI_H |
| 113639634U, // LUTI4_2ZTZI_S |
| 113606866U, // LUTI4_4ZTZI_H |
| 113639634U, // LUTI4_4ZTZI_S |
| 5308626U, // LUTI4_S_2ZTZI_B |
| 5865682U, // LUTI4_S_2ZTZI_H |
| 113606866U, // LUTI4_S_4ZTZI_H |
| 4260050U, // LUTI4_ZTZI_B |
| 113377490U, // LUTI4_ZTZI_H |
| 4358354U, // LUTI4_ZTZI_S |
| 4233069U, // MADDWrrr |
| 4233069U, // MADDXrrr |
| 2151749349U, // MAD_ZPmZZ_B |
| 2151782117U, // MAD_ZPmZZ_D |
| 2713851621U, // MAD_ZPmZZ_H |
| 2151847653U, // MAD_ZPmZZ_S |
| 2151753669U, // MATCH_PPzZZ_B |
| 566372293U, // MATCH_PPzZZ_H |
| 2151743814U, // MLA_ZPmZZ_B |
| 2151776582U, // MLA_ZPmZZ_D |
| 2713846086U, // MLA_ZPmZZ_H |
| 2151842118U, // MLA_ZPmZZ_S |
| 2151776582U, // MLA_ZZZI_D |
| 84017478U, // MLA_ZZZI_H |
| 2688713030U, // MLA_ZZZI_S |
| 1615070316U, // MLAv16i8 |
| 1615082352U, // MLAv2i32 |
| 1615082352U, // MLAv2i32_indexed |
| 1615075899U, // MLAv4i16 |
| 1615075899U, // MLAv4i16_indexed |
| 1615084284U, // MLAv4i32 |
| 1615084284U, // MLAv4i32_indexed |
| 1615077760U, // MLAv8i16 |
| 1615077760U, // MLAv8i16_indexed |
| 1615071247U, // MLAv8i8 |
| 2151760379U, // MLS_ZPmZZ_B |
| 2151793147U, // MLS_ZPmZZ_D |
| 2713862651U, // MLS_ZPmZZ_H |
| 2151858683U, // MLS_ZPmZZ_S |
| 2151793147U, // MLS_ZZZI_D |
| 84034043U, // MLS_ZZZI_H |
| 2688729595U, // MLS_ZZZI_S |
| 1615070939U, // MLSv16i8 |
| 1615083350U, // MLSv2i32 |
| 1615083350U, // MLSv2i32_indexed |
| 1615076885U, // MLSv4i16 |
| 1615076885U, // MLSv4i16_indexed |
| 1615085429U, // MLSv4i32 |
| 1615085429U, // MLSv4i32_indexed |
| 1615078781U, // MLSv8i16 |
| 1615078781U, // MLSv8i16_indexed |
| 1615071895U, // MLSv8i8 |
| 266258994U, // MOPSSETGE |
| 266259055U, // MOPSSETGEN |
| 266259943U, // MOPSSETGET |
| 266259416U, // MOPSSETGETN |
| 3489974334U, // MOVAZ_2ZMI_H_B |
| 3490007102U, // MOVAZ_2ZMI_H_D |
| 3490039870U, // MOVAZ_2ZMI_H_H |
| 3490072638U, // MOVAZ_2ZMI_H_S |
| 3494168638U, // MOVAZ_2ZMI_V_B |
| 3494201406U, // MOVAZ_2ZMI_V_D |
| 3494234174U, // MOVAZ_2ZMI_V_H |
| 3494266942U, // MOVAZ_2ZMI_V_S |
| 4026845246U, // MOVAZ_4ZMI_H_B |
| 4026878014U, // MOVAZ_4ZMI_H_D |
| 4026910782U, // MOVAZ_4ZMI_H_H |
| 4026943550U, // MOVAZ_4ZMI_H_S |
| 4031039550U, // MOVAZ_4ZMI_V_B |
| 4031072318U, // MOVAZ_4ZMI_V_D |
| 4031105086U, // MOVAZ_4ZMI_V_H |
| 4031137854U, // MOVAZ_4ZMI_V_S |
| 277170238U, // MOVAZ_VG2_2ZM |
| 814041150U, // MOVAZ_VG4_4ZM |
| 1078020158U, // MOVAZ_ZMI_H_B |
| 1078052926U, // MOVAZ_ZMI_H_D |
| 281167934U, // MOVAZ_ZMI_H_H |
| 281987134U, // MOVAZ_ZMI_H_Q |
| 1078118462U, // MOVAZ_ZMI_H_S |
| 1614891070U, // MOVAZ_ZMI_V_B |
| 1614923838U, // MOVAZ_ZMI_V_D |
| 285362238U, // MOVAZ_ZMI_V_H |
| 286181438U, // MOVAZ_ZMI_V_Q |
| 1614989374U, // MOVAZ_ZMI_V_S |
| 1891926698U, // MOVA_2ZMXI_H_B |
| 1891959466U, // MOVA_2ZMXI_H_D |
| 1891992234U, // MOVA_2ZMXI_H_H |
| 1892025002U, // MOVA_2ZMXI_H_S |
| 1896121002U, // MOVA_2ZMXI_V_B |
| 1896153770U, // MOVA_2ZMXI_V_D |
| 1896186538U, // MOVA_2ZMXI_V_H |
| 1896219306U, // MOVA_2ZMXI_V_S |
| 1891926698U, // MOVA_4ZMXI_H_B |
| 1891959466U, // MOVA_4ZMXI_H_D |
| 1891992234U, // MOVA_4ZMXI_H_H |
| 1892025002U, // MOVA_4ZMXI_H_S |
| 1896121002U, // MOVA_4ZMXI_V_B |
| 1896153770U, // MOVA_4ZMXI_V_D |
| 1896186538U, // MOVA_4ZMXI_V_H |
| 1896219306U, // MOVA_4ZMXI_V_S |
| 160432810U, // MOVA_MXI2Z_H_B |
| 160432810U, // MOVA_MXI2Z_H_D |
| 160432810U, // MOVA_MXI2Z_H_H |
| 160432810U, // MOVA_MXI2Z_H_S |
| 160465578U, // MOVA_MXI2Z_V_B |
| 160465578U, // MOVA_MXI2Z_V_D |
| 160465578U, // MOVA_MXI2Z_V_H |
| 160465578U, // MOVA_MXI2Z_V_S |
| 160432810U, // MOVA_MXI4Z_H_B |
| 160432810U, // MOVA_MXI4Z_H_D |
| 160432810U, // MOVA_MXI4Z_H_H |
| 160432810U, // MOVA_MXI4Z_H_S |
| 160465578U, // MOVA_MXI4Z_V_B |
| 160465578U, // MOVA_MXI4Z_V_D |
| 160465578U, // MOVA_MXI4Z_V_H |
| 160465578U, // MOVA_MXI4Z_V_S |
| 289735338U, // MOVA_VG2_2ZMXI |
| 3288761002U, // MOVA_VG2_MXI2Z |
| 826606250U, // MOVA_VG4_4ZMXI |
| 3825631914U, // MOVA_VG4_MXI4Z |
| 2151721553U, // MOVID |
| 2688746918U, // MOVIv16b_ns |
| 2151879482U, // MOVIv2d_ns |
| 2688759084U, // MOVIv2i32 |
| 2688759084U, // MOVIv2s_msl |
| 2688752608U, // MOVIv4i16 |
| 2688761071U, // MOVIv4i32 |
| 2688761071U, // MOVIv4s_msl |
| 2688747780U, // MOVIv8b_ns |
| 2688754469U, // MOVIv8i16 |
| 3225463402U, // MOVKWi |
| 3225463402U, // MOVKXi |
| 2688593584U, // MOVNWi |
| 2688593584U, // MOVNXi |
| 541149157U, // MOVPRFX_ZPmZ_B |
| 541181925U, // MOVPRFX_ZPmZ_D |
| 1082279909U, // MOVPRFX_ZPmZ_H |
| 541247461U, // MOVPRFX_ZPmZ_S |
| 2151761893U, // MOVPRFX_ZPzZ_B |
| 2151794661U, // MOVPRFX_ZPzZ_D |
| 566380517U, // MOVPRFX_ZPzZ_H |
| 2151860197U, // MOVPRFX_ZPzZ_S |
| 2153727973U, // MOVPRFX_ZZ |
| 293651740U, // MOVT_TIX |
| 4244764U, // MOVT_XTI |
| 2688600188U, // MOVZWi |
| 2688600188U, // MOVZXi |
| 2114170U, // MRRS |
| 3225469545U, // MRS |
| 2151747323U, // MSB_ZPmZZ_B |
| 2151780091U, // MSB_ZPmZZ_D |
| 2713849595U, // MSB_ZPmZZ_H |
| 2151845627U, // MSB_ZPmZZ_S |
| 3336614431U, // MSR |
| 299938319U, // MSRR |
| 2175519U, // MSRpstateImm1 |
| 2175519U, // MSRpstateImm4 |
| 2208287U, // MSRpstatesvcrImm1 |
| 4231037U, // MSUBWrrr |
| 4231037U, // MSUBXrrr |
| 4271468U, // MUL_ZI_B |
| 541175148U, // MUL_ZI_D |
| 71445868U, // MUL_ZI_H |
| 541240684U, // MUL_ZI_S |
| 2151755116U, // MUL_ZPmZ_B |
| 2151787884U, // MUL_ZPmZ_D |
| 2713857388U, // MUL_ZPmZ_H |
| 2151853420U, // MUL_ZPmZ_S |
| 541175148U, // MUL_ZZZI_D |
| 71445868U, // MUL_ZZZI_H |
| 541240684U, // MUL_ZZZI_S |
| 4271468U, // MUL_ZZZ_B |
| 541175148U, // MUL_ZZZ_D |
| 71445868U, // MUL_ZZZ_H |
| 541240684U, // MUL_ZZZ_S |
| 1615005202U, // MULv16i8 |
| 1615017350U, // MULv2i32 |
| 1615017350U, // MULv2i32_indexed |
| 1615010874U, // MULv4i16 |
| 1615010874U, // MULv4i16_indexed |
| 1615019533U, // MULv4i32 |
| 1615019533U, // MULv4i32_indexed |
| 1615012905U, // MULv8i16 |
| 1615012905U, // MULv8i16_indexed |
| 1615006054U, // MULv8i8 |
| 2688759056U, // MVNIv2i32 |
| 2688759056U, // MVNIv2s_msl |
| 2688752580U, // MVNIv4i16 |
| 2688761043U, // MVNIv4i32 |
| 2688761043U, // MVNIv4s_msl |
| 2688754441U, // MVNIv8i16 |
| 2151760326U, // NANDS_PPzPP |
| 2151749521U, // NAND_PPzPP |
| 541175069U, // NBSL_ZZZZ |
| 541137056U, // NEG_ZPmZ_B |
| 541169824U, // NEG_ZPmZ_D |
| 1082267808U, // NEG_ZPmZ_H |
| 541235360U, // NEG_ZPmZ_S |
| 1615005057U, // NEGv16i8 |
| 4233376U, // NEGv1i64 |
| 1615017146U, // NEGv2i32 |
| 1615008504U, // NEGv2i64 |
| 1615010670U, // NEGv4i16 |
| 1615019121U, // NEGv4i32 |
| 1615012531U, // NEGv8i16 |
| 1615005923U, // NEGv8i8 |
| 2151753668U, // NMATCH_PPzZZ_B |
| 566372292U, // NMATCH_PPzZZ_H |
| 2151760500U, // NORS_PPzPP |
| 2151756269U, // NOR_PPzPP |
| 541148374U, // NOT_ZPmZ_B |
| 541181142U, // NOT_ZPmZ_D |
| 1082279126U, // NOT_ZPmZ_H |
| 541246678U, // NOT_ZPmZ_S |
| 1615005451U, // NOTv16i8 |
| 1615006402U, // NOTv8i8 |
| 2151760413U, // ORNS_PPzPP |
| 4238937U, // ORNWrs |
| 4238937U, // ORNXrs |
| 2151755353U, // ORN_PPzPP |
| 1615005231U, // ORNv16i8 |
| 1615006148U, // ORNv8i8 |
| 2181252678U, // ORQV_VPZ_B |
| 2185446982U, // ORQV_VPZ_D |
| 2189641286U, // ORQV_VPZ_H |
| 2193835590U, // ORQV_VPZ_S |
| 2151760512U, // ORRS_PPzPP |
| 4239870U, // ORRWri |
| 4239870U, // ORRWrs |
| 4239870U, // ORRXri |
| 4239870U, // ORRXrs |
| 2151756286U, // ORR_PPzPP |
| 541176318U, // ORR_ZI |
| 2151756286U, // ORR_ZPmZ_B |
| 2151789054U, // ORR_ZPmZ_D |
| 2713858558U, // ORR_ZPmZ_H |
| 2151854590U, // ORR_ZPmZ_S |
| 541176318U, // ORR_ZZZ |
| 1615005364U, // ORRv16i8 |
| 3225696030U, // ORRv2i32 |
| 3225689565U, // ORRv4i16 |
| 3225698109U, // ORRv4i32 |
| 3225691461U, // ORRv8i16 |
| 1615006324U, // ORRv8i8 |
| 509541U, // ORV_VPZ_B |
| 3301459557U, // ORV_VPZ_D |
| 3305686629U, // ORV_VPZ_H |
| 3246999141U, // ORV_VPZ_S |
| 1615429893U, // PACDA |
| 1615432671U, // PACDB |
| 623298U, // PACDZA |
| 626641U, // PACDZB |
| 4227362U, // PACGA |
| 1615429936U, // PACIA |
| 18849U, // PACIA1716 |
| 18807U, // PACIASP |
| 18798U, // PACIAZ |
| 1615432706U, // PACIB |
| 18739U, // PACIB1716 |
| 18840U, // PACIBSP |
| 18823U, // PACIBZ |
| 623314U, // PACIZA |
| 626657U, // PACIZB |
| 1774503247U, // PEXT_2PCI_B |
| 1774536015U, // PEXT_2PCI_D |
| 1774568783U, // PEXT_2PCI_H |
| 1774601551U, // PEXT_2PCI_S |
| 2151761231U, // PEXT_PCI_B |
| 2151793999U, // PEXT_PCI_D |
| 1774339407U, // PEXT_PCI_H |
| 2151859535U, // PEXT_PCI_S |
| 71757U, // PFALSE |
| 2151761144U, // PFIRST_B |
| 2151761412U, // PMOV_PZI_B |
| 2151794180U, // PMOV_PZI_D |
| 1640121860U, // PMOV_PZI_H |
| 2151859716U, // PMOV_PZI_S |
| 3911140868U, // PMOV_ZIP_B |
| 1763657220U, // PMOV_ZIP_D |
| 1226786308U, // PMOV_ZIP_H |
| 2300528132U, // PMOV_ZIP_S |
| 541166862U, // PMULLB_ZZZ_D |
| 302124302U, // PMULLB_ZZZ_H |
| 307137806U, // PMULLB_ZZZ_Q |
| 541180874U, // PMULLT_ZZZ_D |
| 302138314U, // PMULLT_ZZZ_H |
| 307151818U, // PMULLT_ZZZ_Q |
| 1615011921U, // PMULLv16i8 |
| 1615016072U, // PMULLv1i64 |
| 1615016061U, // PMULLv2i64 |
| 1615012854U, // PMULLv8i8 |
| 4271480U, // PMUL_ZZZ_B |
| 1615005201U, // PMULv16i8 |
| 1615006053U, // PMULv8i8 |
| 2151761224U, // PNEXT_B |
| 2151793992U, // PNEXT_D |
| 29508936U, // PNEXT_H |
| 2151859528U, // PNEXT_S |
| 81923061U, // PRFB_D_PZI |
| 161614837U, // PRFB_D_SCALED |
| 161614837U, // PRFB_D_SXTW_SCALED |
| 161614837U, // PRFB_D_UXTW_SCALED |
| 161614837U, // PRFB_PRI |
| 161614837U, // PRFB_PRR |
| 27397109U, // PRFB_S_PZI |
| 161614837U, // PRFB_S_SXTW_SCALED |
| 161614837U, // PRFB_S_UXTW_SCALED |
| 81926027U, // PRFD_D_PZI |
| 161617803U, // PRFD_D_SCALED |
| 161617803U, // PRFD_D_SXTW_SCALED |
| 161617803U, // PRFD_D_UXTW_SCALED |
| 161617803U, // PRFD_PRI |
| 161617803U, // PRFD_PRR |
| 27400075U, // PRFD_S_PZI |
| 161617803U, // PRFD_S_SXTW_SCALED |
| 161617803U, // PRFD_S_UXTW_SCALED |
| 81930196U, // PRFH_D_PZI |
| 161621972U, // PRFH_D_SCALED |
| 161621972U, // PRFH_D_SXTW_SCALED |
| 161621972U, // PRFH_D_UXTW_SCALED |
| 161621972U, // PRFH_PRI |
| 161621972U, // PRFH_PRR |
| 27404244U, // PRFH_S_PZI |
| 161621972U, // PRFH_S_SXTW_SCALED |
| 161621972U, // PRFH_S_UXTW_SCALED |
| 3764563393U, // PRFMl |
| 77770177U, // PRFMroW |
| 77770177U, // PRFMroX |
| 77770177U, // PRFMui |
| 77770234U, // PRFUMi |
| 81938176U, // PRFW_D_PZI |
| 161629952U, // PRFW_D_SCALED |
| 161629952U, // PRFW_D_SXTW_SCALED |
| 161629952U, // PRFW_D_UXTW_SCALED |
| 161629952U, // PRFW_PRI |
| 161629952U, // PRFW_PRR |
| 27412224U, // PRFW_S_PZI |
| 161629952U, // PRFW_S_SXTW_SCALED |
| 161629952U, // PRFW_S_UXTW_SCALED |
| 2153720796U, // PSEL_PPPRI_B |
| 2153720796U, // PSEL_PPPRI_D |
| 2153720796U, // PSEL_PPPRI_H |
| 2153720796U, // PSEL_PPPRI_S |
| 6243562U, // PTEST_PP |
| 1078018509U, // PTRUES_B |
| 1078051277U, // PTRUES_D |
| 310526413U, // PTRUES_H |
| 1078116813U, // PTRUES_S |
| 1078007911U, // PTRUE_B |
| 2300007U, // PTRUE_C_B |
| 2332775U, // PTRUE_C_D |
| 2365543U, // PTRUE_C_H |
| 2398311U, // PTRUE_C_S |
| 1078040679U, // PTRUE_D |
| 310515815U, // PTRUE_H |
| 1078106215U, // PTRUE_S |
| 3523357202U, // PUNPKHI_PP |
| 3523358407U, // PUNPKLO_PP |
| 3762359720U, // RADDHNB_ZZZ_B |
| 21106088U, // RADDHNB_ZZZ_H |
| 541232552U, // RADDHNB_ZZZ_S |
| 1078019117U, // RADDHNT_ZZZ_B |
| 25314349U, // RADDHNT_ZZZ_H |
| 2151859245U, // RADDHNT_ZZZ_S |
| 1615017402U, // RADDHNv2i64_v2i32 |
| 1615084022U, // RADDHNv2i64_v4i32 |
| 1615010926U, // RADDHNv4i32_v4i16 |
| 1615077524U, // RADDHNv4i32_v8i16 |
| 1615070101U, // RADDHNv8i16_v16i8 |
| 1615006073U, // RADDHNv8i16_v8i8 |
| 1615007975U, // RAX1 |
| 541163592U, // RAX1_ZZZ_D |
| 4244254U, // RBITWr |
| 4244254U, // RBITXr |
| 541147934U, // RBIT_ZPmZ_B |
| 541180702U, // RBIT_ZPmZ_D |
| 1082278686U, // RBIT_ZPmZ_H |
| 541246238U, // RBIT_ZPmZ_S |
| 1615005422U, // RBITv16i8 |
| 1615006376U, // RBITv8i8 |
| 1615446381U, // RCWCAS |
| 1615430255U, // RCWCASA |
| 1615440739U, // RCWCASAL |
| 1615441172U, // RCWCASL |
| 831477U, // RCWCASP |
| 819686U, // RCWCASPA |
| 830192U, // RCWCASPAL |
| 830628U, // RCWCASPL |
| 2689184153U, // RCWCLR |
| 2689172026U, // RCWCLRA |
| 2689182533U, // RCWCLRAL |
| 2689182969U, // RCWCLRL |
| 6205410U, // RCWCLRP |
| 6193617U, // RCWCLRPA |
| 6204121U, // RCWCLRPAL |
| 6204559U, // RCWCLRPL |
| 2689184144U, // RCWCLRS |
| 2689172016U, // RCWCLRSA |
| 2689182522U, // RCWCLRSAL |
| 2689182959U, // RCWCLRSL |
| 6205400U, // RCWCLRSP |
| 6193606U, // RCWCLRSPA |
| 6204109U, // RCWCLRSPAL |
| 6204548U, // RCWCLRSPL |
| 1615446372U, // RCWSCAS |
| 1615430245U, // RCWSCASA |
| 1615440728U, // RCWSCASAL |
| 1615441162U, // RCWSCASL |
| 831467U, // RCWSCASP |
| 819675U, // RCWSCASPA |
| 830180U, // RCWSCASPAL |
| 830617U, // RCWSCASPL |
| 2689188600U, // RCWSET |
| 2689172106U, // RCWSETA |
| 2689182593U, // RCWSETAL |
| 2689183066U, // RCWSETL |
| 6205462U, // RCWSETP |
| 6193668U, // RCWSETPA |
| 6204177U, // RCWSETPAL |
| 6204618U, // RCWSETPL |
| 2689188591U, // RCWSETS |
| 2689172096U, // RCWSETSA |
| 2689182582U, // RCWSETSAL |
| 2689183056U, // RCWSETSL |
| 6205452U, // RCWSETSP |
| 6193657U, // RCWSETSPA |
| 6204165U, // RCWSETSPAL |
| 6204607U, // RCWSETSPL |
| 2689183809U, // RCWSWP |
| 2689171992U, // RCWSWPA |
| 2689182503U, // RCWSWPAL |
| 2689182942U, // RCWSWPL |
| 6205371U, // RCWSWPP |
| 6193587U, // RCWSWPPA |
| 6204088U, // RCWSWPPAL |
| 6204529U, // RCWSWPPL |
| 2689183800U, // RCWSWPS |
| 2689171982U, // RCWSWPSA |
| 2689182492U, // RCWSWPSAL |
| 2689182932U, // RCWSWPSL |
| 6205361U, // RCWSWPSP |
| 6193576U, // RCWSWPSPA |
| 6204076U, // RCWSWPSPAL |
| 6204518U, // RCWSWPSPL |
| 2151760481U, // RDFFRS_PPz |
| 2151756108U, // RDFFR_PPz_REAL |
| 78156U, // RDFFR_P_REAL |
| 4238747U, // RDSVLI_XI |
| 4238733U, // RDVLI_XI |
| 49891U, // RET |
| 20151U, // RETAA |
| 20178U, // RETAB |
| 4227294U, // REV16Wr |
| 4227294U, // REV16Xr |
| 1615004749U, // REV16v16i8 |
| 1615005683U, // REV16v8i8 |
| 4227150U, // REV32Xr |
| 1615004541U, // REV32v16i8 |
| 1615010296U, // REV32v4i16 |
| 1615011779U, // REV32v8i16 |
| 1615005636U, // REV32v8i8 |
| 1615004738U, // REV64v16i8 |
| 1615016786U, // REV64v2i32 |
| 1615010333U, // REV64v4i16 |
| 1615018694U, // REV64v4i32 |
| 1615012194U, // REV64v8i16 |
| 1615005673U, // REV64v8i8 |
| 541167513U, // REVB_ZPmZ_D |
| 1082265497U, // REVB_ZPmZ_H |
| 541233049U, // REVB_ZPmZ_S |
| 9344960U, // REVD_ZPmZ |
| 541174250U, // REVH_ZPmZ_D |
| 541239786U, // REVH_ZPmZ_S |
| 541181834U, // REVW_ZPmZ_D |
| 4244921U, // REVWr |
| 4244921U, // REVXr |
| 4277689U, // REV_PP_B |
| 541181369U, // REV_PP_D |
| 3292677561U, // REV_PP_H |
| 541246905U, // REV_PP_S |
| 4277689U, // REV_ZZ_B |
| 541181369U, // REV_ZZ_D |
| 3292677561U, // REV_ZZ_H |
| 541246905U, // REV_ZZ_S |
| 20195U, // RMIF |
| 4239858U, // RORVWr |
| 4239858U, // RORVXr |
| 2436544U, // RPRFM |
| 3762359767U, // RSHRNB_ZZI_B |
| 21106135U, // RSHRNB_ZZI_H |
| 541232599U, // RSHRNB_ZZI_S |
| 1078019152U, // RSHRNT_ZZI_B |
| 25314384U, // RSHRNT_ZZI_H |
| 2151859280U, // RSHRNT_ZZI_S |
| 1615070142U, // RSHRNv16i8_shift |
| 1615017464U, // RSHRNv2i32_shift |
| 1615010988U, // RSHRNv4i16_shift |
| 1615084060U, // RSHRNv4i32_shift |
| 1615077562U, // RSHRNv8i16_shift |
| 1615006126U, // RSHRNv8i8_shift |
| 3762359711U, // RSUBHNB_ZZZ_B |
| 21106079U, // RSUBHNB_ZZZ_H |
| 541232543U, // RSUBHNB_ZZZ_S |
| 1078019108U, // RSUBHNT_ZZZ_B |
| 25314340U, // RSUBHNT_ZZZ_H |
| 2151859236U, // RSUBHNT_ZZZ_S |
| 1615017391U, // RSUBHNv2i64_v2i32 |
| 1615084010U, // RSUBHNv2i64_v4i32 |
| 1615010915U, // RSUBHNv4i32_v4i16 |
| 1615077512U, // RSUBHNv4i32_v8i16 |
| 1615070088U, // RSUBHNv8i16_v16i8 |
| 1615006062U, // RSUBHNv8i16_v8i8 |
| 2688650262U, // SABALB_ZZZ_D |
| 314706966U, // SABALB_ZZZ_H |
| 1078103062U, // SABALB_ZZZ_S |
| 2688664369U, // SABALT_ZZZ_D |
| 314721073U, // SABALT_ZZZ_H |
| 1078117169U, // SABALT_ZZZ_S |
| 1615077325U, // SABALv16i8_v8i16 |
| 1615074115U, // SABALv2i32_v2i64 |
| 1615084792U, // SABALv4i16_v4i32 |
| 1615073533U, // SABALv4i32_v2i64 |
| 1615083795U, // SABALv8i16_v4i32 |
| 1615078190U, // SABALv8i8_v8i16 |
| 4260089U, // SABA_ZZZ_B |
| 2151776505U, // SABA_ZZZ_D |
| 84017401U, // SABA_ZZZ_H |
| 2688712953U, // SABA_ZZZ_S |
| 1615070296U, // SABAv16i8 |
| 1615082332U, // SABAv2i32 |
| 1615075879U, // SABAv4i16 |
| 1615084264U, // SABAv4i32 |
| 1615077740U, // SABAv8i16 |
| 1615071229U, // SABAv8i8 |
| 541166795U, // SABDLB_ZZZ_D |
| 302124235U, // SABDLB_ZZZ_H |
| 3762457803U, // SABDLB_ZZZ_S |
| 541180802U, // SABDLT_ZZZ_D |
| 302138242U, // SABDLT_ZZZ_H |
| 3762471810U, // SABDLT_ZZZ_S |
| 1615011855U, // SABDLv16i8_v8i16 |
| 1615008651U, // SABDLv2i32_v2i64 |
| 1615019328U, // SABDLv4i16_v4i32 |
| 1615008076U, // SABDLv4i32_v2i64 |
| 1615018338U, // SABDLv8i16_v4i32 |
| 1615012714U, // SABDLv8i8_v8i16 |
| 2151749374U, // SABD_ZPmZ_B |
| 2151782142U, // SABD_ZPmZ_D |
| 2713851646U, // SABD_ZPmZ_H |
| 2151847678U, // SABD_ZPmZ_S |
| 1615004907U, // SABDv16i8 |
| 1615016948U, // SABDv2i32 |
| 1615010495U, // SABDv4i16 |
| 1615018914U, // SABDv4i32 |
| 1615012356U, // SABDv8i16 |
| 1615005805U, // SABDv8i8 |
| 2151788345U, // SADALP_ZPmZ_D |
| 2713857849U, // SADALP_ZPmZ_H |
| 2151853881U, // SADALP_ZPmZ_S |
| 1615078530U, // SADALPv16i8_v8i16 |
| 1615073368U, // SADALPv2i32_v1i64 |
| 1615083099U, // SADALPv4i16_v2i32 |
| 1615074463U, // SADALPv4i32_v2i64 |
| 1615085178U, // SADALPv8i16_v4i32 |
| 1615076634U, // SADALPv8i8_v4i16 |
| 541180601U, // SADDLBT_ZZZ_D |
| 302138041U, // SADDLBT_ZZZ_H |
| 3762471609U, // SADDLBT_ZZZ_S |
| 541166820U, // SADDLB_ZZZ_D |
| 302124260U, // SADDLB_ZZZ_H |
| 3762457828U, // SADDLB_ZZZ_S |
| 1615013016U, // SADDLPv16i8_v8i16 |
| 1615007854U, // SADDLPv2i32_v1i64 |
| 1615017585U, // SADDLPv4i16_v2i32 |
| 1615008949U, // SADDLPv4i32_v2i64 |
| 1615019664U, // SADDLPv8i16_v4i32 |
| 1615011120U, // SADDLPv8i8_v4i16 |
| 541180818U, // SADDLT_ZZZ_D |
| 302138258U, // SADDLT_ZZZ_H |
| 3762471826U, // SADDLT_ZZZ_S |
| 1614841662U, // SADDLVv16i8v |
| 1614847718U, // SADDLVv4i16v |
| 1614856262U, // SADDLVv4i32v |
| 1614849614U, // SADDLVv8i16v |
| 1614842608U, // SADDLVv8i8v |
| 1615011877U, // SADDLv16i8_v8i16 |
| 1615008671U, // SADDLv2i32_v2i64 |
| 1615019348U, // SADDLv4i16_v4i32 |
| 1615008098U, // SADDLv4i32_v2i64 |
| 1615018360U, // SADDLv8i16_v4i32 |
| 1615012734U, // SADDLv8i8_v8i16 |
| 3536340389U, // SADDV_VPZ_B |
| 3305653669U, // SADDV_VPZ_H |
| 3246933413U, // SADDV_VPZ_S |
| 541167535U, // SADDWB_ZZZ_D |
| 71438255U, // SADDWB_ZZZ_H |
| 541233071U, // SADDWB_ZZZ_S |
| 541181234U, // SADDWT_ZZZ_D |
| 71451954U, // SADDWT_ZZZ_H |
| 541246770U, // SADDWT_ZZZ_S |
| 1615012172U, // SADDWv16i8_v8i16 |
| 1615009359U, // SADDWv2i32_v2i64 |
| 1615020237U, // SADDWv4i16_v4i32 |
| 1615008261U, // SADDWv4i32_v2i64 |
| 1615018658U, // SADDWv8i16_v4i32 |
| 1615013589U, // SADDWv8i8_v8i16 |
| 20192U, // SB |
| 2151779517U, // SBCLB_ZZZ_D |
| 2688715965U, // SBCLB_ZZZ_S |
| 2151793524U, // SBCLT_ZZZ_D |
| 2688729972U, // SBCLT_ZZZ_S |
| 4243886U, // SBCSWr |
| 4243886U, // SBCSXr |
| 4231153U, // SBCWr |
| 4231153U, // SBCXr |
| 4238772U, // SBFMWri |
| 4238772U, // SBFMXri |
| 314879833U, // SCLAMP_VG2_2Z2Z_B |
| 80031577U, // SCLAMP_VG2_2Z2Z_D |
| 84258649U, // SCLAMP_VG2_2Z2Z_H |
| 25571161U, // SCLAMP_VG2_2Z2Z_S |
| 314879833U, // SCLAMP_VG4_4Z4Z_B |
| 80031577U, // SCLAMP_VG4_4Z4Z_D |
| 84258649U, // SCLAMP_VG4_4Z4Z_H |
| 25571161U, // SCLAMP_VG4_4Z4Z_S |
| 4271961U, // SCLAMP_ZZZ_B |
| 541175641U, // SCLAMP_ZZZ_D |
| 71446361U, // SCLAMP_ZZZ_H |
| 541241177U, // SCLAMP_ZZZ_S |
| 4233331U, // SCVTFSWDri |
| 4233331U, // SCVTFSWHri |
| 4233331U, // SCVTFSWSri |
| 4233331U, // SCVTFSXDri |
| 4233331U, // SCVTFSXHri |
| 4233331U, // SCVTFSXSri |
| 4233331U, // SCVTFUWDri |
| 4233331U, // SCVTFUWHri |
| 4233331U, // SCVTFUWSri |
| 4233331U, // SCVTFUXDri |
| 4233331U, // SCVTFUXHri |
| 4233331U, // SCVTFUXSri |
| 3284539507U, // SCVTF_2Z2Z_StoS |
| 3284539507U, // SCVTF_4Z4Z_StoS |
| 541169779U, // SCVTF_ZPmZ_DtoD |
| 1619138675U, // SCVTF_ZPmZ_DtoH |
| 541235315U, // SCVTF_ZPmZ_DtoS |
| 1082267763U, // SCVTF_ZPmZ_HtoH |
| 541169779U, // SCVTF_ZPmZ_StoD |
| 2156009587U, // SCVTF_ZPmZ_StoH |
| 541235315U, // SCVTF_ZPmZ_StoS |
| 4233331U, // SCVTFd |
| 4233331U, // SCVTFh |
| 4233331U, // SCVTFs |
| 4233331U, // SCVTFv1i16 |
| 4233331U, // SCVTFv1i32 |
| 4233331U, // SCVTFv1i64 |
| 1615017125U, // SCVTFv2f32 |
| 1615008483U, // SCVTFv2f64 |
| 1615017125U, // SCVTFv2i32_shift |
| 1615008483U, // SCVTFv2i64_shift |
| 1615010649U, // SCVTFv4f16 |
| 1615019100U, // SCVTFv4f32 |
| 1615010649U, // SCVTFv4i16_shift |
| 1615019100U, // SCVTFv4i32_shift |
| 1615012510U, // SCVTFv8f16 |
| 1615012510U, // SCVTFv8i16_shift |
| 2151789155U, // SDIVR_ZPmZ_D |
| 2151854691U, // SDIVR_ZPmZ_S |
| 4244932U, // SDIVWr |
| 4244932U, // SDIVXr |
| 2151794116U, // SDIV_ZPmZ_D |
| 2151859652U, // SDIV_ZPmZ_S |
| 3288810672U, // SDOT_VG2_M2Z2Z_BtoS |
| 3288777904U, // SDOT_VG2_M2Z2Z_HtoD |
| 3288810672U, // SDOT_VG2_M2Z2Z_HtoS |
| 3288810672U, // SDOT_VG2_M2ZZI_BToS |
| 3288810672U, // SDOT_VG2_M2ZZI_HToS |
| 3288777904U, // SDOT_VG2_M2ZZI_HtoD |
| 3288810672U, // SDOT_VG2_M2ZZ_BtoS |
| 3288777904U, // SDOT_VG2_M2ZZ_HtoD |
| 3288810672U, // SDOT_VG2_M2ZZ_HtoS |
| 3825681584U, // SDOT_VG4_M4Z4Z_BtoS |
| 3825648816U, // SDOT_VG4_M4Z4Z_HtoD |
| 3825681584U, // SDOT_VG4_M4Z4Z_HtoS |
| 3825681584U, // SDOT_VG4_M4ZZI_BToS |
| 3825681584U, // SDOT_VG4_M4ZZI_HToS |
| 3825648816U, // SDOT_VG4_M4ZZI_HtoD |
| 3825681584U, // SDOT_VG4_M4ZZ_BtoS |
| 3825648816U, // SDOT_VG4_M4ZZ_HtoD |
| 3825681584U, // SDOT_VG4_M4ZZ_HtoS |
| 1078052016U, // SDOT_ZZZI_D |
| 1078117552U, // SDOT_ZZZI_HtoS |
| 4375728U, // SDOT_ZZZI_S |
| 1078052016U, // SDOT_ZZZ_D |
| 1078117552U, // SDOT_ZZZ_HtoS |
| 4375728U, // SDOT_ZZZ_S |
| 1615086768U, // SDOTlanev16i8 |
| 1615086768U, // SDOTlanev8i8 |
| 20297U, // SDOTv16i8 |
| 20297U, // SDOTv8i8 |
| 2151754711U, // SEL_PPPP |
| 163883991U, // SEL_VG2_2ZP2Z2Z_B |
| 163916759U, // SEL_VG2_2ZP2Z2Z_D |
| 163949527U, // SEL_VG2_2ZP2Z2Z_H |
| 163982295U, // SEL_VG2_2ZP2Z2Z_S |
| 163883991U, // SEL_VG4_4ZP4Z4Z_B |
| 163916759U, // SEL_VG4_4ZP4Z4Z_D |
| 163949527U, // SEL_VG4_4ZP4Z4Z_H |
| 163982295U, // SEL_VG4_4ZP4Z4Z_S |
| 2151754711U, // SEL_ZPZZ_B |
| 2151787479U, // SEL_ZPZZ_D |
| 29502423U, // SEL_ZPZZ_H |
| 2151853015U, // SEL_ZPZZ_S |
| 266259002U, // SETE |
| 266259064U, // SETEN |
| 266259952U, // SETET |
| 266259426U, // SETETN |
| 18816U, // SETF16 |
| 18866U, // SETF8 |
| 20257U, // SETFFR |
| 266259024U, // SETGM |
| 266259089U, // SETGMN |
| 266259977U, // SETGMT |
| 266259454U, // SETGMTN |
| 266259912U, // SETGP |
| 266259123U, // SETGPN |
| 266260011U, // SETGPT |
| 266259492U, // SETGPTN |
| 266259032U, // SETM |
| 266259098U, // SETMN |
| 266259986U, // SETMT |
| 266259464U, // SETMTN |
| 266259920U, // SETP |
| 266259132U, // SETPN |
| 266260020U, // SETPT |
| 266259502U, // SETPTN |
| 1615444871U, // SHA1Crrr |
| 4233556U, // SHA1Hrr |
| 1615445525U, // SHA1Mrrr |
| 1615445606U, // SHA1Prrr |
| 1615083678U, // SHA1SU0rrr |
| 1615083742U, // SHA1SU1rr |
| 1615444230U, // SHA256H2rrr |
| 1615445123U, // SHA256Hrrr |
| 1615083690U, // SHA256SU0rr |
| 1615083754U, // SHA256SU1rrr |
| 1615434506U, // SHA512H |
| 1615433968U, // SHA512H2 |
| 1615073456U, // SHA512SU0 |
| 1615073497U, // SHA512SU1 |
| 2151749470U, // SHADD_ZPmZ_B |
| 2151782238U, // SHADD_ZPmZ_D |
| 2713851742U, // SHADD_ZPmZ_H |
| 2151847774U, // SHADD_ZPmZ_S |
| 1615004951U, // SHADDv16i8 |
| 1615017007U, // SHADDv2i32 |
| 1615010554U, // SHADDv4i16 |
| 1615018973U, // SHADDv4i32 |
| 1615012415U, // SHADDv8i16 |
| 1615005845U, // SHADDv8i8 |
| 1615011900U, // SHLLv16i8 |
| 1615008772U, // SHLLv2i32 |
| 1615019449U, // SHLLv4i16 |
| 1615008121U, // SHLLv4i32 |
| 1615018383U, // SHLLv8i16 |
| 1615012835U, // SHLLv8i8 |
| 4238316U, // SHLd |
| 1615005106U, // SHLv16i8_shift |
| 1615017271U, // SHLv2i32_shift |
| 1615008693U, // SHLv2i64_shift |
| 1615010795U, // SHLv4i16_shift |
| 1615019370U, // SHLv4i32_shift |
| 1615012756U, // SHLv8i16_shift |
| 1615005967U, // SHLv8i8_shift |
| 3762359749U, // SHRNB_ZZI_B |
| 21106117U, // SHRNB_ZZI_H |
| 541232581U, // SHRNB_ZZI_S |
| 1078019134U, // SHRNT_ZZI_B |
| 25314366U, // SHRNT_ZZI_H |
| 2151859262U, // SHRNT_ZZI_S |
| 1615070116U, // SHRNv16i8_shift |
| 1615017442U, // SHRNv2i32_shift |
| 1615010966U, // SHRNv4i16_shift |
| 1615084036U, // SHRNv4i32_shift |
| 1615077538U, // SHRNv8i16_shift |
| 1615006104U, // SHRNv8i8_shift |
| 2151756066U, // SHSUBR_ZPmZ_B |
| 2151788834U, // SHSUBR_ZPmZ_D |
| 2713858338U, // SHSUBR_ZPmZ_H |
| 2151854370U, // SHSUBR_ZPmZ_S |
| 2151747438U, // SHSUB_ZPmZ_B |
| 2151780206U, // SHSUB_ZPmZ_D |
| 2713849710U, // SHSUB_ZPmZ_H |
| 2151845742U, // SHSUB_ZPmZ_S |
| 1615004831U, // SHSUBv16i8 |
| 1615016891U, // SHSUBv2i32 |
| 1615010438U, // SHSUBv4i16 |
| 1615018847U, // SHSUBv4i32 |
| 1615012299U, // SHSUBv8i16 |
| 1615005757U, // SHSUBv8i8 |
| 4270650U, // SLI_ZZI_B |
| 2151787066U, // SLI_ZZI_D |
| 84027962U, // SLI_ZZI_H |
| 2688723514U, // SLI_ZZI_S |
| 1615440442U, // SLId |
| 1615070612U, // SLIv16i8_shift |
| 1615082760U, // SLIv2i32_shift |
| 1615074079U, // SLIv2i64_shift |
| 1615076284U, // SLIv4i16_shift |
| 1615084747U, // SLIv4i32_shift |
| 1615078145U, // SLIv8i16_shift |
| 1615071476U, // SLIv8i8_shift |
| 1615083768U, // SM3PARTW1 |
| 1615084216U, // SM3PARTW2 |
| 1615018195U, // SM3SS1 |
| 1615084240U, // SM3TT1A |
| 1615084350U, // SM3TT1B |
| 1615084252U, // SM3TT2A |
| 1615084362U, // SM3TT2B |
| 1615084551U, // SM4E |
| 541247500U, // SM4EKEY_ZZZ_S |
| 1615020331U, // SM4ENCKEY |
| 541235142U, // SM4E_ZZZ_S |
| 4238268U, // SMADDLrrr |
| 2151755863U, // SMAXP_ZPmZ_B |
| 2151788631U, // SMAXP_ZPmZ_D |
| 2713858135U, // SMAXP_ZPmZ_H |
| 2151854167U, // SMAXP_ZPmZ_S |
| 1615005281U, // SMAXPv16i8 |
| 1615017690U, // SMAXPv2i32 |
| 1615011225U, // SMAXPv4i16 |
| 1615019769U, // SMAXPv4i32 |
| 1615013121U, // SMAXPv8i16 |
| 1615006249U, // SMAXPv8i8 |
| 2181252692U, // SMAXQV_VPZ_B |
| 2185446996U, // SMAXQV_VPZ_D |
| 2189641300U, // SMAXQV_VPZ_H |
| 2193835604U, // SMAXQV_VPZ_S |
| 509553U, // SMAXV_VPZ_B |
| 3301459569U, // SMAXV_VPZ_D |
| 3305686641U, // SMAXV_VPZ_H |
| 3246999153U, // SMAXV_VPZ_S |
| 1614841708U, // SMAXVv16i8v |
| 1614847813U, // SMAXVv4i16v |
| 1614856357U, // SMAXVv4i32v |
| 1614849709U, // SMAXVv8i16v |
| 1614842650U, // SMAXVv8i8v |
| 4245435U, // SMAXWri |
| 4245435U, // SMAXWrr |
| 4245435U, // SMAXXri |
| 4245435U, // SMAXXrr |
| 50644923U, // SMAX_VG2_2Z2Z_B |
| 54871995U, // SMAX_VG2_2Z2Z_D |
| 59099067U, // SMAX_VG2_2Z2Z_H |
| 63326139U, // SMAX_VG2_2Z2Z_S |
| 50644923U, // SMAX_VG2_2ZZ_B |
| 54871995U, // SMAX_VG2_2ZZ_D |
| 59099067U, // SMAX_VG2_2ZZ_H |
| 63326139U, // SMAX_VG2_2ZZ_S |
| 50644923U, // SMAX_VG4_4Z4Z_B |
| 54871995U, // SMAX_VG4_4Z4Z_D |
| 59099067U, // SMAX_VG4_4Z4Z_H |
| 63326139U, // SMAX_VG4_4Z4Z_S |
| 50644923U, // SMAX_VG4_4ZZ_B |
| 54871995U, // SMAX_VG4_4ZZ_D |
| 59099067U, // SMAX_VG4_4ZZ_H |
| 63326139U, // SMAX_VG4_4ZZ_S |
| 4278203U, // SMAX_ZI_B |
| 541181883U, // SMAX_ZI_D |
| 71452603U, // SMAX_ZI_H |
| 541247419U, // SMAX_ZI_S |
| 2151761851U, // SMAX_ZPmZ_B |
| 2151794619U, // SMAX_ZPmZ_D |
| 2713864123U, // SMAX_ZPmZ_H |
| 2151860155U, // SMAX_ZPmZ_S |
| 1615005580U, // SMAXv16i8 |
| 1615018058U, // SMAXv2i32 |
| 1615011682U, // SMAXv4i16 |
| 1615020292U, // SMAXv4i32 |
| 1615013618U, // SMAXv8i16 |
| 1615006510U, // SMAXv8i8 |
| 757770U, // SMC |
| 2151755669U, // SMINP_ZPmZ_B |
| 2151788437U, // SMINP_ZPmZ_D |
| 2713857941U, // SMINP_ZPmZ_H |
| 2151853973U, // SMINP_ZPmZ_S |
| 1615005250U, // SMINPv16i8 |
| 1615017641U, // SMINPv2i32 |
| 1615011176U, // SMINPv4i16 |
| 1615019720U, // SMINPv4i32 |
| 1615013072U, // SMINPv8i16 |
| 1615006221U, // SMINPv8i8 |
| 2181252661U, // SMINQV_VPZ_B |
| 2185446965U, // SMINQV_VPZ_D |
| 2189641269U, // SMINQV_VPZ_H |
| 2193835573U, // SMINQV_VPZ_S |
| 509417U, // SMINV_VPZ_B |
| 3301459433U, // SMINV_VPZ_D |
| 3305686505U, // SMINV_VPZ_H |
| 3246999017U, // SMINV_VPZ_S |
| 1614841686U, // SMINVv16i8v |
| 1614847774U, // SMINVv4i16v |
| 1614856318U, // SMINVv4i32v |
| 1614849670U, // SMINVv8i16v |
| 1614842630U, // SMINVv8i8v |
| 4238872U, // SMINWri |
| 4238872U, // SMINWrr |
| 4238872U, // SMINXri |
| 4238872U, // SMINXrr |
| 50638360U, // SMIN_VG2_2Z2Z_B |
| 54865432U, // SMIN_VG2_2Z2Z_D |
| 59092504U, // SMIN_VG2_2Z2Z_H |
| 63319576U, // SMIN_VG2_2Z2Z_S |
| 50638360U, // SMIN_VG2_2ZZ_B |
| 54865432U, // SMIN_VG2_2ZZ_D |
| 59092504U, // SMIN_VG2_2ZZ_H |
| 63319576U, // SMIN_VG2_2ZZ_S |
| 50638360U, // SMIN_VG4_4Z4Z_B |
| 54865432U, // SMIN_VG4_4Z4Z_D |
| 59092504U, // SMIN_VG4_4Z4Z_H |
| 63319576U, // SMIN_VG4_4Z4Z_S |
| 50638360U, // SMIN_VG4_4ZZ_B |
| 54865432U, // SMIN_VG4_4ZZ_D |
| 59092504U, // SMIN_VG4_4ZZ_H |
| 63319576U, // SMIN_VG4_4ZZ_S |
| 4271640U, // SMIN_ZI_B |
| 541175320U, // SMIN_ZI_D |
| 71446040U, // SMIN_ZI_H |
| 541240856U, // SMIN_ZI_S |
| 2151755288U, // SMIN_ZPmZ_B |
| 2151788056U, // SMIN_ZPmZ_D |
| 2713857560U, // SMIN_ZPmZ_H |
| 2151853592U, // SMIN_ZPmZ_S |
| 1615005211U, // SMINv16i8 |
| 1615017422U, // SMINv2i32 |
| 1615010946U, // SMINv4i16 |
| 1615019593U, // SMINv4i32 |
| 1615012955U, // SMINv8i16 |
| 1615006084U, // SMINv8i8 |
| 2688650307U, // SMLALB_ZZZI_D |
| 1078103107U, // SMLALB_ZZZI_S |
| 2688650307U, // SMLALB_ZZZ_D |
| 314707011U, // SMLALB_ZZZ_H |
| 1078103107U, // SMLALB_ZZZ_S |
| 3003591715U, // SMLALL_MZZI_BtoS |
| 3003558947U, // SMLALL_MZZI_HtoD |
| 3003591715U, // SMLALL_MZZ_BtoS |
| 3003558947U, // SMLALL_MZZ_HtoD |
| 3540462627U, // SMLALL_VG2_M2Z2Z_BtoS |
| 3540429859U, // SMLALL_VG2_M2Z2Z_HtoD |
| 3540462627U, // SMLALL_VG2_M2ZZI_BtoS |
| 3540429859U, // SMLALL_VG2_M2ZZI_HtoD |
| 856108067U, // SMLALL_VG2_M2ZZ_BtoS |
| 856075299U, // SMLALL_VG2_M2ZZ_HtoD |
| 4077333539U, // SMLALL_VG4_M4Z4Z_BtoS |
| 4077300771U, // SMLALL_VG4_M4Z4Z_HtoD |
| 4077333539U, // SMLALL_VG4_M4ZZI_BtoS |
| 4077300771U, // SMLALL_VG4_M4ZZI_HtoD |
| 1392978979U, // SMLALL_VG4_M4ZZ_BtoS |
| 1392946211U, // SMLALL_VG4_M4ZZ_HtoD |
| 2688664404U, // SMLALT_ZZZI_D |
| 1078117204U, // SMLALT_ZZZI_S |
| 2688664404U, // SMLALT_ZZZ_D |
| 314721108U, // SMLALT_ZZZ_H |
| 1078117204U, // SMLALT_ZZZ_S |
| 2781293194U, // SMLAL_MZZI_S |
| 2781293194U, // SMLAL_MZZ_S |
| 3318164106U, // SMLAL_VG2_M2Z2Z_S |
| 3318164106U, // SMLAL_VG2_M2ZZI_S |
| 3318164106U, // SMLAL_VG2_M2ZZ_S |
| 3855035018U, // SMLAL_VG4_M4Z4Z_S |
| 3855035018U, // SMLAL_VG4_M4ZZI_S |
| 3855035018U, // SMLAL_VG4_M4ZZ_S |
| 1615077347U, // SMLALv16i8_v8i16 |
| 1615074147U, // SMLALv2i32_indexed |
| 1615074147U, // SMLALv2i32_v2i64 |
| 1615084824U, // SMLALv4i16_indexed |
| 1615084824U, // SMLALv4i16_v4i32 |
| 1615073568U, // SMLALv4i32_indexed |
| 1615073568U, // SMLALv4i32_v2i64 |
| 1615083830U, // SMLALv8i16_indexed |
| 1615083830U, // SMLALv8i16_v4i32 |
| 1615078210U, // SMLALv8i8_v8i16 |
| 2688650605U, // SMLSLB_ZZZI_D |
| 1078103405U, // SMLSLB_ZZZI_S |
| 2688650605U, // SMLSLB_ZZZ_D |
| 314707309U, // SMLSLB_ZZZ_H |
| 1078103405U, // SMLSLB_ZZZ_S |
| 3003591732U, // SMLSLL_MZZI_BtoS |
| 3003558964U, // SMLSLL_MZZI_HtoD |
| 3003591732U, // SMLSLL_MZZ_BtoS |
| 3003558964U, // SMLSLL_MZZ_HtoD |
| 3540462644U, // SMLSLL_VG2_M2Z2Z_BtoS |
| 3540429876U, // SMLSLL_VG2_M2Z2Z_HtoD |
| 3540462644U, // SMLSLL_VG2_M2ZZI_BtoS |
| 3540429876U, // SMLSLL_VG2_M2ZZI_HtoD |
| 856108084U, // SMLSLL_VG2_M2ZZ_BtoS |
| 856075316U, // SMLSLL_VG2_M2ZZ_HtoD |
| 4077333556U, // SMLSLL_VG4_M4Z4Z_BtoS |
| 4077300788U, // SMLSLL_VG4_M4Z4Z_HtoD |
| 4077333556U, // SMLSLL_VG4_M4ZZI_BtoS |
| 4077300788U, // SMLSLL_VG4_M4ZZI_HtoD |
| 1392978996U, // SMLSLL_VG4_M4ZZ_BtoS |
| 1392946228U, // SMLSLL_VG4_M4ZZ_HtoD |
| 2688664579U, // SMLSLT_ZZZI_D |
| 1078117379U, // SMLSLT_ZZZI_S |
| 2688664579U, // SMLSLT_ZZZ_D |
| 314721283U, // SMLSLT_ZZZ_H |
| 1078117379U, // SMLSLT_ZZZ_S |
| 2781293876U, // SMLSL_MZZI_S |
| 2781293876U, // SMLSL_MZZ_S |
| 3318164788U, // SMLSL_VG2_M2Z2Z_S |
| 3318164788U, // SMLSL_VG2_M2ZZI_S |
| 3318164788U, // SMLSL_VG2_M2ZZ_S |
| 3855035700U, // SMLSL_VG4_M4Z4Z_S |
| 3855035700U, // SMLSL_VG4_M4ZZI_S |
| 3855035700U, // SMLSL_VG4_M4ZZ_S |
| 1615077490U, // SMLSLv16i8_v8i16 |
| 1615074371U, // SMLSLv2i32_indexed |
| 1615074371U, // SMLSLv2i32_v2i64 |
| 1615085048U, // SMLSLv4i16_indexed |
| 1615085048U, // SMLSLv4i16_v4i32 |
| 1615073726U, // SMLSLv4i32_indexed |
| 1615073726U, // SMLSLv4i32_v2i64 |
| 1615083988U, // SMLSLv8i16_indexed |
| 1615083988U, // SMLSLv8i16_v4i32 |
| 1615078420U, // SMLSLv8i8_v8i16 |
| 20165U, // SMMLA |
| 4358491U, // SMMLA_ZZZ |
| 100893081U, // SMOPA_MPPZZ_D |
| 100893081U, // SMOPA_MPPZZ_HtoS |
| 323191193U, // SMOPA_MPPZZ_S |
| 100909642U, // SMOPS_MPPZZ_D |
| 100909642U, // SMOPS_MPPZZ_HtoS |
| 323207754U, // SMOPS_MPPZZ_S |
| 1614846267U, // SMOVvi16to32 |
| 1614846267U, // SMOVvi16to32_idx0 |
| 1614846267U, // SMOVvi16to64 |
| 1614846267U, // SMOVvi16to64_idx0 |
| 1614852867U, // SMOVvi32to64 |
| 1614852867U, // SMOVvi32to64_idx0 |
| 1614840553U, // SMOVvi8to32 |
| 1614840553U, // SMOVvi8to32_idx0 |
| 1614840553U, // SMOVvi8to64 |
| 1614840553U, // SMOVvi8to64_idx0 |
| 4238244U, // SMSUBLrrr |
| 2151753879U, // SMULH_ZPmZ_B |
| 2151786647U, // SMULH_ZPmZ_D |
| 2713856151U, // SMULH_ZPmZ_H |
| 2151852183U, // SMULH_ZPmZ_S |
| 4270231U, // SMULH_ZZZ_B |
| 541173911U, // SMULH_ZZZ_D |
| 71444631U, // SMULH_ZZZ_H |
| 541239447U, // SMULH_ZZZ_S |
| 4237463U, // SMULHrr |
| 541166870U, // SMULLB_ZZZI_D |
| 3762457878U, // SMULLB_ZZZI_S |
| 541166870U, // SMULLB_ZZZ_D |
| 302124310U, // SMULLB_ZZZ_H |
| 3762457878U, // SMULLB_ZZZ_S |
| 541180882U, // SMULLT_ZZZI_D |
| 3762471890U, // SMULLT_ZZZI_S |
| 541180882U, // SMULLT_ZZZ_D |
| 302138322U, // SMULLT_ZZZ_H |
| 3762471890U, // SMULLT_ZZZ_S |
| 1615011932U, // SMULLv16i8_v8i16 |
| 1615008803U, // SMULLv2i32_indexed |
| 1615008803U, // SMULLv2i32_v2i64 |
| 1615019480U, // SMULLv4i16_indexed |
| 1615019480U, // SMULLv4i16_v4i32 |
| 1615008155U, // SMULLv4i32_indexed |
| 1615008155U, // SMULLv4i32_v2i64 |
| 1615018417U, // SMULLv8i16_indexed |
| 1615018417U, // SMULLv8i16_v4i32 |
| 1615012864U, // SMULLv8i8_v8i16 |
| 2151749580U, // SPLICE_ZPZZ_B |
| 2151782348U, // SPLICE_ZPZZ_D |
| 29497292U, // SPLICE_ZPZZ_H |
| 2151847884U, // SPLICE_ZPZZ_S |
| 2151749580U, // SPLICE_ZPZ_B |
| 2151782348U, // SPLICE_ZPZ_D |
| 29497292U, // SPLICE_ZPZ_H |
| 2151847884U, // SPLICE_ZPZ_S |
| 541147538U, // SQABS_ZPmZ_B |
| 541180306U, // SQABS_ZPmZ_D |
| 1082278290U, // SQABS_ZPmZ_H |
| 541245842U, // SQABS_ZPmZ_S |
| 1615005373U, // SQABSv16i8 |
| 4243858U, // SQABSv1i16 |
| 4243858U, // SQABSv1i32 |
| 4243858U, // SQABSv1i64 |
| 4243858U, // SQABSv1i8 |
| 1615017786U, // SQABSv2i32 |
| 1615009110U, // SQABSv2i64 |
| 1615011321U, // SQABSv4i16 |
| 1615019865U, // SQABSv4i32 |
| 1615013217U, // SQABSv8i16 |
| 1615006332U, // SQABSv8i8 |
| 4265852U, // SQADD_ZI_B |
| 541169532U, // SQADD_ZI_D |
| 71440252U, // SQADD_ZI_H |
| 541235068U, // SQADD_ZI_S |
| 2151749500U, // SQADD_ZPmZ_B |
| 2151782268U, // SQADD_ZPmZ_D |
| 2713851772U, // SQADD_ZPmZ_H |
| 2151847804U, // SQADD_ZPmZ_S |
| 4265852U, // SQADD_ZZZ_B |
| 541169532U, // SQADD_ZZZ_D |
| 71440252U, // SQADD_ZZZ_H |
| 541235068U, // SQADD_ZZZ_S |
| 1615004974U, // SQADDv16i8 |
| 4233084U, // SQADDv1i16 |
| 4233084U, // SQADDv1i32 |
| 4233084U, // SQADDv1i64 |
| 4233084U, // SQADDv1i8 |
| 1615017028U, // SQADDv2i32 |
| 1615008409U, // SQADDv2i64 |
| 1615010575U, // SQADDv4i16 |
| 1615018994U, // SQADDv4i32 |
| 1615012436U, // SQADDv8i16 |
| 1615005866U, // SQADDv8i8 |
| 4265784U, // SQCADD_ZZI_B |
| 541169464U, // SQCADD_ZZI_D |
| 71440184U, // SQCADD_ZZI_H |
| 541235000U, // SQCADD_ZZI_S |
| 3284282990U, // SQCVTN_Z2Z_StoH |
| 3275894382U, // SQCVTN_Z4Z_DtoH |
| 1614884462U, // SQCVTN_Z4Z_StoB |
| 3284283039U, // SQCVTUN_Z2Z_StoH |
| 3275894431U, // SQCVTUN_Z4Z_DtoH |
| 1614884511U, // SQCVTUN_Z4Z_StoB |
| 3284288902U, // SQCVTU_Z2Z_StoH |
| 3275900294U, // SQCVTU_Z4Z_DtoH |
| 1614890374U, // SQCVTU_Z4Z_StoB |
| 3284288782U, // SQCVT_Z2Z_StoH |
| 3275900174U, // SQCVT_Z4Z_DtoH |
| 1614890254U, // SQCVT_Z4Z_StoB |
| 541100991U, // SQDECB_XPiI |
| 2151713727U, // SQDECB_XPiWdI |
| 541103889U, // SQDECD_XPiI |
| 2151716625U, // SQDECD_XPiWdI |
| 541169425U, // SQDECD_ZPiI |
| 541108132U, // SQDECH_XPiI |
| 2151720868U, // SQDECH_XPiWdI |
| 104998820U, // SQDECH_ZPiI |
| 4239100U, // SQDECP_XPWd_B |
| 541110012U, // SQDECP_XPWd_D |
| 3762335484U, // SQDECP_XPWd_H |
| 541110012U, // SQDECP_XPWd_S |
| 4239100U, // SQDECP_XP_B |
| 541110012U, // SQDECP_XP_D |
| 3762335484U, // SQDECP_XP_H |
| 541110012U, // SQDECP_XP_S |
| 2151788284U, // SQDECP_ZP_D |
| 3305254652U, // SQDECP_ZP_H |
| 2688724732U, // SQDECP_ZP_S |
| 541116128U, // SQDECW_XPiI |
| 2151728864U, // SQDECW_XPiWdI |
| 541247200U, // SQDECW_ZPiI |
| 2688664229U, // SQDMLALBT_ZZZ_D |
| 314720933U, // SQDMLALBT_ZZZ_H |
| 1078117029U, // SQDMLALBT_ZZZ_S |
| 2688650288U, // SQDMLALB_ZZZI_D |
| 1078103088U, // SQDMLALB_ZZZI_S |
| 2688650288U, // SQDMLALB_ZZZ_D |
| 314706992U, // SQDMLALB_ZZZ_H |
| 1078103088U, // SQDMLALB_ZZZ_S |
| 2688664385U, // SQDMLALT_ZZZI_D |
| 1078117185U, // SQDMLALT_ZZZI_S |
| 2688664385U, // SQDMLALT_ZZZ_D |
| 314721089U, // SQDMLALT_ZZZ_H |
| 1078117185U, // SQDMLALT_ZZZ_S |
| 1615440505U, // SQDMLALi16 |
| 1615440505U, // SQDMLALi32 |
| 1615436035U, // SQDMLALv1i32_indexed |
| 1615442635U, // SQDMLALv1i64_indexed |
| 1615074135U, // SQDMLALv2i32_indexed |
| 1615074135U, // SQDMLALv2i32_v2i64 |
| 1615084812U, // SQDMLALv4i16_indexed |
| 1615084812U, // SQDMLALv4i16_v4i32 |
| 1615073555U, // SQDMLALv4i32_indexed |
| 1615073555U, // SQDMLALv4i32_v2i64 |
| 1615083817U, // SQDMLALv8i16_indexed |
| 1615083817U, // SQDMLALv8i16_v4i32 |
| 2688664258U, // SQDMLSLBT_ZZZ_D |
| 314720962U, // SQDMLSLBT_ZZZ_H |
| 1078117058U, // SQDMLSLBT_ZZZ_S |
| 2688650586U, // SQDMLSLB_ZZZI_D |
| 1078103386U, // SQDMLSLB_ZZZI_S |
| 2688650586U, // SQDMLSLB_ZZZ_D |
| 314707290U, // SQDMLSLB_ZZZ_H |
| 1078103386U, // SQDMLSLB_ZZZ_S |
| 2688664560U, // SQDMLSLT_ZZZI_D |
| 1078117360U, // SQDMLSLT_ZZZI_S |
| 2688664560U, // SQDMLSLT_ZZZ_D |
| 314721264U, // SQDMLSLT_ZZZ_H |
| 1078117360U, // SQDMLSLT_ZZZ_S |
| 1615441187U, // SQDMLSLi16 |
| 1615441187U, // SQDMLSLi32 |
| 1615436057U, // SQDMLSLv1i32_indexed |
| 1615442657U, // SQDMLSLv1i64_indexed |
| 1615074359U, // SQDMLSLv2i32_indexed |
| 1615074359U, // SQDMLSLv2i32_v2i64 |
| 1615085036U, // SQDMLSLv4i16_indexed |
| 1615085036U, // SQDMLSLv4i16_v4i32 |
| 1615073713U, // SQDMLSLv4i32_indexed |
| 1615073713U, // SQDMLSLv4i32_v2i64 |
| 1615083975U, // SQDMLSLv8i16_indexed |
| 1615083975U, // SQDMLSLv8i16_v4i32 |
| 50636932U, // SQDMULH_VG2_2Z2Z_B |
| 54864004U, // SQDMULH_VG2_2Z2Z_D |
| 59091076U, // SQDMULH_VG2_2Z2Z_H |
| 63318148U, // SQDMULH_VG2_2Z2Z_S |
| 50636932U, // SQDMULH_VG2_2ZZ_B |
| 54864004U, // SQDMULH_VG2_2ZZ_D |
| 59091076U, // SQDMULH_VG2_2ZZ_H |
| 63318148U, // SQDMULH_VG2_2ZZ_S |
| 50636932U, // SQDMULH_VG4_4Z4Z_B |
| 54864004U, // SQDMULH_VG4_4Z4Z_D |
| 59091076U, // SQDMULH_VG4_4Z4Z_H |
| 63318148U, // SQDMULH_VG4_4Z4Z_S |
| 50636932U, // SQDMULH_VG4_4ZZ_B |
| 54864004U, // SQDMULH_VG4_4ZZ_D |
| 59091076U, // SQDMULH_VG4_4ZZ_H |
| 63318148U, // SQDMULH_VG4_4ZZ_S |
| 541173892U, // SQDMULH_ZZZI_D |
| 71444612U, // SQDMULH_ZZZI_H |
| 541239428U, // SQDMULH_ZZZI_S |
| 4270212U, // SQDMULH_ZZZ_B |
| 541173892U, // SQDMULH_ZZZ_D |
| 71444612U, // SQDMULH_ZZZ_H |
| 541239428U, // SQDMULH_ZZZ_S |
| 4237444U, // SQDMULHv1i16 |
| 4233440U, // SQDMULHv1i16_indexed |
| 4237444U, // SQDMULHv1i32 |
| 4240040U, // SQDMULHv1i32_indexed |
| 1615017177U, // SQDMULHv2i32 |
| 1615017177U, // SQDMULHv2i32_indexed |
| 1615010701U, // SQDMULHv4i16 |
| 1615010701U, // SQDMULHv4i16_indexed |
| 1615019164U, // SQDMULHv4i32 |
| 1615019164U, // SQDMULHv4i32_indexed |
| 1615012562U, // SQDMULHv8i16 |
| 1615012562U, // SQDMULHv8i16_indexed |
| 541166852U, // SQDMULLB_ZZZI_D |
| 3762457860U, // SQDMULLB_ZZZI_S |
| 541166852U, // SQDMULLB_ZZZ_D |
| 302124292U, // SQDMULLB_ZZZ_H |
| 3762457860U, // SQDMULLB_ZZZ_S |
| 541180864U, // SQDMULLT_ZZZI_D |
| 3762471872U, // SQDMULLT_ZZZI_S |
| 541180864U, // SQDMULLT_ZZZ_D |
| 302138304U, // SQDMULLT_ZZZ_H |
| 3762471872U, // SQDMULLT_ZZZ_S |
| 4238404U, // SQDMULLi16 |
| 4238404U, // SQDMULLi32 |
| 4233486U, // SQDMULLv1i32_indexed |
| 4240086U, // SQDMULLv1i64_indexed |
| 1615008791U, // SQDMULLv2i32_indexed |
| 1615008791U, // SQDMULLv2i32_v2i64 |
| 1615019468U, // SQDMULLv4i16_indexed |
| 1615019468U, // SQDMULLv4i16_v4i32 |
| 1615008142U, // SQDMULLv4i32_indexed |
| 1615008142U, // SQDMULLv4i32_v2i64 |
| 1615018404U, // SQDMULLv8i16_indexed |
| 1615018404U, // SQDMULLv8i16_v4i32 |
| 541101007U, // SQINCB_XPiI |
| 2151713743U, // SQINCB_XPiWdI |
| 541103905U, // SQINCD_XPiI |
| 2151716641U, // SQINCD_XPiWdI |
| 541169441U, // SQINCD_ZPiI |
| 541108148U, // SQINCH_XPiI |
| 2151720884U, // SQINCH_XPiWdI |
| 104998836U, // SQINCH_ZPiI |
| 4239116U, // SQINCP_XPWd_B |
| 541110028U, // SQINCP_XPWd_D |
| 3762335500U, // SQINCP_XPWd_H |
| 541110028U, // SQINCP_XPWd_S |
| 4239116U, // SQINCP_XP_B |
| 541110028U, // SQINCP_XP_D |
| 3762335500U, // SQINCP_XP_H |
| 541110028U, // SQINCP_XP_S |
| 2151788300U, // SQINCP_ZP_D |
| 3305254668U, // SQINCP_ZP_H |
| 2688724748U, // SQINCP_ZP_S |
| 541116144U, // SQINCW_XPiI |
| 2151728880U, // SQINCW_XPiWdI |
| 541247216U, // SQINCW_ZPiI |
| 541137061U, // SQNEG_ZPmZ_B |
| 541169829U, // SQNEG_ZPmZ_D |
| 1082267813U, // SQNEG_ZPmZ_H |
| 541235365U, // SQNEG_ZPmZ_S |
| 1615005055U, // SQNEGv16i8 |
| 4233381U, // SQNEGv1i16 |
| 4233381U, // SQNEGv1i32 |
| 4233381U, // SQNEGv1i64 |
| 4233381U, // SQNEGv1i8 |
| 1615017154U, // SQNEGv2i32 |
| 1615008512U, // SQNEGv2i64 |
| 1615010678U, // SQNEGv4i16 |
| 1615019129U, // SQNEGv4i32 |
| 1615012539U, // SQNEGv8i16 |
| 1615005921U, // SQNEGv8i8 |
| 84027189U, // SQRDCMLAH_ZZZI_H |
| 2688722741U, // SQRDCMLAH_ZZZI_S |
| 4269877U, // SQRDCMLAH_ZZZ_B |
| 2151786293U, // SQRDCMLAH_ZZZ_D |
| 84027189U, // SQRDCMLAH_ZZZ_H |
| 2688722741U, // SQRDCMLAH_ZZZ_S |
| 2151786304U, // SQRDMLAH_ZZZI_D |
| 84027200U, // SQRDMLAH_ZZZI_H |
| 2688722752U, // SQRDMLAH_ZZZI_S |
| 4269888U, // SQRDMLAH_ZZZ_B |
| 2151786304U, // SQRDMLAH_ZZZ_D |
| 84027200U, // SQRDMLAH_ZZZ_H |
| 2688722752U, // SQRDMLAH_ZZZ_S |
| 1615435988U, // SQRDMLAHi16_indexed |
| 1615442588U, // SQRDMLAHi32_indexed |
| 1615439680U, // SQRDMLAHv1i16 |
| 1615439680U, // SQRDMLAHv1i32 |
| 1615082700U, // SQRDMLAHv2i32 |
| 1615082700U, // SQRDMLAHv2i32_indexed |
| 1615076224U, // SQRDMLAHv4i16 |
| 1615076224U, // SQRDMLAHv4i16_indexed |
| 1615084687U, // SQRDMLAHv4i32 |
| 1615084687U, // SQRDMLAHv4i32_indexed |
| 1615078085U, // SQRDMLAHv8i16 |
| 1615078085U, // SQRDMLAHv8i16_indexed |
| 2151786909U, // SQRDMLSH_ZZZI_D |
| 84027805U, // SQRDMLSH_ZZZI_H |
| 2688723357U, // SQRDMLSH_ZZZI_S |
| 4270493U, // SQRDMLSH_ZZZ_B |
| 2151786909U, // SQRDMLSH_ZZZ_D |
| 84027805U, // SQRDMLSH_ZZZ_H |
| 2688723357U, // SQRDMLSH_ZZZ_S |
| 1615436023U, // SQRDMLSHi16_indexed |
| 1615442623U, // SQRDMLSHi32_indexed |
| 1615440285U, // SQRDMLSHv1i16 |
| 1615440285U, // SQRDMLSHv1i32 |
| 1615082738U, // SQRDMLSHv2i32 |
| 1615082738U, // SQRDMLSHv2i32_indexed |
| 1615076262U, // SQRDMLSHv4i16 |
| 1615076262U, // SQRDMLSHv4i16_indexed |
| 1615084725U, // SQRDMLSHv4i32 |
| 1615084725U, // SQRDMLSHv4i32_indexed |
| 1615078123U, // SQRDMLSHv8i16 |
| 1615078123U, // SQRDMLSHv8i16_indexed |
| 541173901U, // SQRDMULH_ZZZI_D |
| 71444621U, // SQRDMULH_ZZZI_H |
| 541239437U, // SQRDMULH_ZZZI_S |
| 4270221U, // SQRDMULH_ZZZ_B |
| 541173901U, // SQRDMULH_ZZZ_D |
| 71444621U, // SQRDMULH_ZZZ_H |
| 541239437U, // SQRDMULH_ZZZ_S |
| 4237453U, // SQRDMULHv1i16 |
| 4233451U, // SQRDMULHv1i16_indexed |
| 4237453U, // SQRDMULHv1i32 |
| 4240051U, // SQRDMULHv1i32_indexed |
| 1615017189U, // SQRDMULHv2i32 |
| 1615017189U, // SQRDMULHv2i32_indexed |
| 1615010713U, // SQRDMULHv4i16 |
| 1615010713U, // SQRDMULHv4i16_indexed |
| 1615019176U, // SQRDMULHv4i32 |
| 1615019176U, // SQRDMULHv4i32_indexed |
| 1615012574U, // SQRDMULHv8i16 |
| 1615012574U, // SQRDMULHv8i16_indexed |
| 2151756209U, // SQRSHLR_ZPmZ_B |
| 2151788977U, // SQRSHLR_ZPmZ_D |
| 2713858481U, // SQRSHLR_ZPmZ_H |
| 2151854513U, // SQRSHLR_ZPmZ_S |
| 2151754744U, // SQRSHL_ZPmZ_B |
| 2151787512U, // SQRSHL_ZPmZ_D |
| 2713857016U, // SQRSHL_ZPmZ_H |
| 2151853048U, // SQRSHL_ZPmZ_S |
| 1615005126U, // SQRSHLv16i8 |
| 4238328U, // SQRSHLv1i16 |
| 4238328U, // SQRSHLv1i32 |
| 4238328U, // SQRSHLv1i64 |
| 4238328U, // SQRSHLv1i8 |
| 1615017289U, // SQRSHLv2i32 |
| 1615008711U, // SQRSHLv2i64 |
| 1615010813U, // SQRSHLv4i16 |
| 1615019388U, // SQRSHLv4i32 |
| 1615012774U, // SQRSHLv8i16 |
| 1615005985U, // SQRSHLv8i8 |
| 3762359765U, // SQRSHRNB_ZZI_B |
| 21106133U, // SQRSHRNB_ZZI_H |
| 541232597U, // SQRSHRNB_ZZI_S |
| 1078019150U, // SQRSHRNT_ZZI_B |
| 25314382U, // SQRSHRNT_ZZI_H |
| 2151859278U, // SQRSHRNT_ZZI_S |
| 1614884423U, // SQRSHRN_VG4_Z4ZI_B |
| 54668871U, // SQRSHRN_VG4_Z4ZI_H |
| 4238919U, // SQRSHRNb |
| 4238919U, // SQRSHRNh |
| 4238919U, // SQRSHRNs |
| 1615070140U, // SQRSHRNv16i8_shift |
| 1615017462U, // SQRSHRNv2i32_shift |
| 1615010986U, // SQRSHRNv4i16_shift |
| 1615084058U, // SQRSHRNv4i32_shift |
| 1615077560U, // SQRSHRNv8i16_shift |
| 1615006124U, // SQRSHRNv8i8_shift |
| 3762359811U, // SQRSHRUNB_ZZI_B |
| 21106179U, // SQRSHRUNB_ZZI_H |
| 541232643U, // SQRSHRUNB_ZZI_S |
| 1078019205U, // SQRSHRUNT_ZZI_B |
| 25314437U, // SQRSHRUNT_ZZI_H |
| 2151859333U, // SQRSHRUNT_ZZI_S |
| 1614884501U, // SQRSHRUN_VG4_Z4ZI_B |
| 54668949U, // SQRSHRUN_VG4_Z4ZI_H |
| 4238997U, // SQRSHRUNb |
| 4238997U, // SQRSHRUNh |
| 4238997U, // SQRSHRUNs |
| 1615070216U, // SQRSHRUNv16i8_shift |
| 1615017529U, // SQRSHRUNv2i32_shift |
| 1615011064U, // SQRSHRUNv4i16_shift |
| 1615084128U, // SQRSHRUNv4i32_shift |
| 1615077642U, // SQRSHRUNv8i16_shift |
| 1615006188U, // SQRSHRUNv8i8_shift |
| 63063421U, // SQRSHRU_VG2_Z2ZI_H |
| 1614890365U, // SQRSHRU_VG4_Z4ZI_B |
| 54674813U, // SQRSHRU_VG4_Z4ZI_H |
| 63058266U, // SQRSHR_VG2_Z2ZI_H |
| 1614885210U, // SQRSHR_VG4_Z4ZI_B |
| 54669658U, // SQRSHR_VG4_Z4ZI_H |
| 2151756193U, // SQSHLR_ZPmZ_B |
| 2151788961U, // SQSHLR_ZPmZ_D |
| 2713858465U, // SQSHLR_ZPmZ_H |
| 2151854497U, // SQSHLR_ZPmZ_S |
| 2151761245U, // SQSHLU_ZPmI_B |
| 2151794013U, // SQSHLU_ZPmI_D |
| 2713863517U, // SQSHLU_ZPmI_H |
| 2151859549U, // SQSHLU_ZPmI_S |
| 4244829U, // SQSHLUb |
| 4244829U, // SQSHLUd |
| 4244829U, // SQSHLUh |
| 4244829U, // SQSHLUs |
| 1615005480U, // SQSHLUv16i8_shift |
| 1615017950U, // SQSHLUv2i32_shift |
| 1615009266U, // SQSHLUv2i64_shift |
| 1615011485U, // SQSHLUv4i16_shift |
| 1615020029U, // SQSHLUv4i32_shift |
| 1615013381U, // SQSHLUv8i16_shift |
| 1615006428U, // SQSHLUv8i8_shift |
| 2151754730U, // SQSHL_ZPmI_B |
| 2151787498U, // SQSHL_ZPmI_D |
| 2713857002U, // SQSHL_ZPmI_H |
| 2151853034U, // SQSHL_ZPmI_S |
| 2151754730U, // SQSHL_ZPmZ_B |
| 2151787498U, // SQSHL_ZPmZ_D |
| 2713857002U, // SQSHL_ZPmZ_H |
| 2151853034U, // SQSHL_ZPmZ_S |
| 4238314U, // SQSHLb |
| 4238314U, // SQSHLd |
| 4238314U, // SQSHLh |
| 4238314U, // SQSHLs |
| 1615005104U, // SQSHLv16i8 |
| 1615005104U, // SQSHLv16i8_shift |
| 4238314U, // SQSHLv1i16 |
| 4238314U, // SQSHLv1i32 |
| 4238314U, // SQSHLv1i64 |
| 4238314U, // SQSHLv1i8 |
| 1615017269U, // SQSHLv2i32 |
| 1615017269U, // SQSHLv2i32_shift |
| 1615008691U, // SQSHLv2i64 |
| 1615008691U, // SQSHLv2i64_shift |
| 1615010793U, // SQSHLv4i16 |
| 1615010793U, // SQSHLv4i16_shift |
| 1615019368U, // SQSHLv4i32 |
| 1615019368U, // SQSHLv4i32_shift |
| 1615012754U, // SQSHLv8i16 |
| 1615012754U, // SQSHLv8i16_shift |
| 1615005965U, // SQSHLv8i8 |
| 1615005965U, // SQSHLv8i8_shift |
| 3762359747U, // SQSHRNB_ZZI_B |
| 21106115U, // SQSHRNB_ZZI_H |
| 541232579U, // SQSHRNB_ZZI_S |
| 1078019132U, // SQSHRNT_ZZI_B |
| 25314364U, // SQSHRNT_ZZI_H |
| 2151859260U, // SQSHRNT_ZZI_S |
| 4238903U, // SQSHRNb |
| 4238903U, // SQSHRNh |
| 4238903U, // SQSHRNs |
| 1615070114U, // SQSHRNv16i8_shift |
| 1615017440U, // SQSHRNv2i32_shift |
| 1615010964U, // SQSHRNv4i16_shift |
| 1615084034U, // SQSHRNv4i32_shift |
| 1615077536U, // SQSHRNv8i16_shift |
| 1615006102U, // SQSHRNv8i8_shift |
| 3762359801U, // SQSHRUNB_ZZI_B |
| 21106169U, // SQSHRUNB_ZZI_H |
| 541232633U, // SQSHRUNB_ZZI_S |
| 1078019195U, // SQSHRUNT_ZZI_B |
| 25314427U, // SQSHRUNT_ZZI_H |
| 2151859323U, // SQSHRUNT_ZZI_S |
| 4238988U, // SQSHRUNb |
| 4238988U, // SQSHRUNh |
| 4238988U, // SQSHRUNs |
| 1615070202U, // SQSHRUNv16i8_shift |
| 1615017517U, // SQSHRUNv2i32_shift |
| 1615011052U, // SQSHRUNv4i16_shift |
| 1615084115U, // SQSHRUNv4i32_shift |
| 1615077629U, // SQSHRUNv8i16_shift |
| 1615006176U, // SQSHRUNv8i8_shift |
| 2151756082U, // SQSUBR_ZPmZ_B |
| 2151788850U, // SQSUBR_ZPmZ_D |
| 2713858354U, // SQSUBR_ZPmZ_H |
| 2151854386U, // SQSUBR_ZPmZ_S |
| 4263819U, // SQSUB_ZI_B |
| 541167499U, // SQSUB_ZI_D |
| 71438219U, // SQSUB_ZI_H |
| 541233035U, // SQSUB_ZI_S |
| 2151747467U, // SQSUB_ZPmZ_B |
| 2151780235U, // SQSUB_ZPmZ_D |
| 2713849739U, // SQSUB_ZPmZ_H |
| 2151845771U, // SQSUB_ZPmZ_S |
| 4263819U, // SQSUB_ZZZ_B |
| 541167499U, // SQSUB_ZZZ_D |
| 71438219U, // SQSUB_ZZZ_H |
| 541233035U, // SQSUB_ZZZ_S |
| 1615004853U, // SQSUBv16i8 |
| 4231051U, // SQSUBv1i16 |
| 4231051U, // SQSUBv1i32 |
| 4231051U, // SQSUBv1i64 |
| 4231051U, // SQSUBv1i8 |
| 1615016911U, // SQSUBv2i32 |
| 1615008360U, // SQSUBv2i64 |
| 1615010458U, // SQSUBv4i16 |
| 1615018867U, // SQSUBv4i32 |
| 1615012319U, // SQSUBv8i16 |
| 1615005777U, // SQSUBv8i8 |
| 3762359785U, // SQXTNB_ZZ_B |
| 3242331625U, // SQXTNB_ZZ_H |
| 541232617U, // SQXTNB_ZZ_S |
| 1078019179U, // SQXTNT_ZZ_B |
| 3246539883U, // SQXTNT_ZZ_H |
| 2151859307U, // SQXTNT_ZZ_S |
| 1615070178U, // SQXTNv16i8 |
| 4238974U, // SQXTNv1i16 |
| 4238974U, // SQXTNv1i32 |
| 4238974U, // SQXTNv1i8 |
| 1615017497U, // SQXTNv2i32 |
| 1615011032U, // SQXTNv4i16 |
| 1615084093U, // SQXTNv4i32 |
| 1615077607U, // SQXTNv8i16 |
| 1615006156U, // SQXTNv8i8 |
| 3762359822U, // SQXTUNB_ZZ_B |
| 3242331662U, // SQXTUNB_ZZ_H |
| 541232654U, // SQXTUNB_ZZ_S |
| 1078019216U, // SQXTUNT_ZZ_B |
| 3246539920U, // SQXTUNT_ZZ_H |
| 2151859344U, // SQXTUNT_ZZ_S |
| 1615070231U, // SQXTUNv16i8 |
| 4239016U, // SQXTUNv1i16 |
| 4239016U, // SQXTUNv1i32 |
| 4239016U, // SQXTUNv1i8 |
| 1615017542U, // SQXTUNv2i32 |
| 1615011077U, // SQXTUNv4i16 |
| 1615084142U, // SQXTUNv4i32 |
| 1615077656U, // SQXTUNv8i16 |
| 1615006201U, // SQXTUNv8i8 |
| 2151749454U, // SRHADD_ZPmZ_B |
| 2151782222U, // SRHADD_ZPmZ_D |
| 2713851726U, // SRHADD_ZPmZ_H |
| 2151847758U, // SRHADD_ZPmZ_S |
| 1615004927U, // SRHADDv16i8 |
| 1615016985U, // SRHADDv2i32 |
| 1615010532U, // SRHADDv4i16 |
| 1615018951U, // SRHADDv4i32 |
| 1615012393U, // SRHADDv8i16 |
| 1615005823U, // SRHADDv8i8 |
| 4270660U, // SRI_ZZI_B |
| 2151787076U, // SRI_ZZI_D |
| 84027972U, // SRI_ZZI_H |
| 2688723524U, // SRI_ZZI_S |
| 1615440452U, // SRId |
| 1615070621U, // SRIv16i8_shift |
| 1615082777U, // SRIv2i32_shift |
| 1615074087U, // SRIv2i64_shift |
| 1615076301U, // SRIv4i16_shift |
| 1615084764U, // SRIv4i32_shift |
| 1615078162U, // SRIv8i16_shift |
| 1615071484U, // SRIv8i8_shift |
| 2151756227U, // SRSHLR_ZPmZ_B |
| 2151788995U, // SRSHLR_ZPmZ_D |
| 2713858499U, // SRSHLR_ZPmZ_H |
| 2151854531U, // SRSHLR_ZPmZ_S |
| 50637832U, // SRSHL_VG2_2Z2Z_B |
| 54864904U, // SRSHL_VG2_2Z2Z_D |
| 59091976U, // SRSHL_VG2_2Z2Z_H |
| 63319048U, // SRSHL_VG2_2Z2Z_S |
| 50637832U, // SRSHL_VG2_2ZZ_B |
| 54864904U, // SRSHL_VG2_2ZZ_D |
| 59091976U, // SRSHL_VG2_2ZZ_H |
| 63319048U, // SRSHL_VG2_2ZZ_S |
| 50637832U, // SRSHL_VG4_4Z4Z_B |
| 54864904U, // SRSHL_VG4_4Z4Z_D |
| 59091976U, // SRSHL_VG4_4Z4Z_H |
| 63319048U, // SRSHL_VG4_4Z4Z_S |
| 50637832U, // SRSHL_VG4_4ZZ_B |
| 54864904U, // SRSHL_VG4_4ZZ_D |
| 59091976U, // SRSHL_VG4_4ZZ_H |
| 63319048U, // SRSHL_VG4_4ZZ_S |
| 2151754760U, // SRSHL_ZPmZ_B |
| 2151787528U, // SRSHL_ZPmZ_D |
| 2713857032U, // SRSHL_ZPmZ_H |
| 2151853064U, // SRSHL_ZPmZ_S |
| 1615005150U, // SRSHLv16i8 |
| 4238344U, // SRSHLv1i64 |
| 1615017311U, // SRSHLv2i32 |
| 1615008733U, // SRSHLv2i64 |
| 1615010835U, // SRSHLv4i16 |
| 1615019410U, // SRSHLv4i32 |
| 1615012796U, // SRSHLv8i16 |
| 1615006007U, // SRSHLv8i8 |
| 2151756138U, // SRSHR_ZPmI_B |
| 2151788906U, // SRSHR_ZPmI_D |
| 2713858410U, // SRSHR_ZPmI_H |
| 2151854442U, // SRSHR_ZPmI_S |
| 4239722U, // SRSHRd |
| 1615005313U, // SRSHRv16i8_shift |
| 1615017720U, // SRSHRv2i32_shift |
| 1615009052U, // SRSHRv2i64_shift |
| 1615011255U, // SRSHRv4i16_shift |
| 1615019799U, // SRSHRv4i32_shift |
| 1615013151U, // SRSHRv8i16_shift |
| 1615006278U, // SRSHRv8i8_shift |
| 4260427U, // SRSRA_ZZI_B |
| 2151776843U, // SRSRA_ZZI_D |
| 84017739U, // SRSRA_ZZI_H |
| 2688713291U, // SRSRA_ZZI_S |
| 1615430219U, // SRSRAd |
| 1615070325U, // SRSRAv16i8_shift |
| 1615082369U, // SRSRAv2i32_shift |
| 1615073838U, // SRSRAv2i64_shift |
| 1615075916U, // SRSRAv4i16_shift |
| 1615084301U, // SRSRAv4i32_shift |
| 1615077777U, // SRSRAv8i16_shift |
| 1615071255U, // SRSRAv8i8_shift |
| 541166836U, // SSHLLB_ZZI_D |
| 302124276U, // SSHLLB_ZZI_H |
| 3762457844U, // SSHLLB_ZZI_S |
| 541180848U, // SSHLLT_ZZI_D |
| 302138288U, // SSHLLT_ZZI_H |
| 3762471856U, // SSHLLT_ZZI_S |
| 1615011899U, // SSHLLv16i8_shift |
| 1615008771U, // SSHLLv2i32_shift |
| 1615019448U, // SSHLLv4i16_shift |
| 1615008120U, // SSHLLv4i32_shift |
| 1615018382U, // SSHLLv8i16_shift |
| 1615012834U, // SSHLLv8i8_shift |
| 1615005172U, // SSHLv16i8 |
| 4238358U, // SSHLv1i64 |
| 1615017331U, // SSHLv2i32 |
| 1615008753U, // SSHLv2i64 |
| 1615010855U, // SSHLv4i16 |
| 1615019430U, // SSHLv4i32 |
| 1615012816U, // SSHLv8i16 |
| 1615006027U, // SSHLv8i8 |
| 4239736U, // SSHRd |
| 1615005335U, // SSHRv16i8_shift |
| 1615017740U, // SSHRv2i32_shift |
| 1615009072U, // SSHRv2i64_shift |
| 1615011275U, // SSHRv4i16_shift |
| 1615019819U, // SSHRv4i32_shift |
| 1615013171U, // SSHRv8i16_shift |
| 1615006298U, // SSHRv8i8_shift |
| 4260441U, // SSRA_ZZI_B |
| 2151776857U, // SSRA_ZZI_D |
| 84017753U, // SSRA_ZZI_H |
| 2688713305U, // SSRA_ZZI_S |
| 1615430233U, // SSRAd |
| 1615070347U, // SSRAv16i8_shift |
| 1615082389U, // SSRAv2i32_shift |
| 1615073858U, // SSRAv2i64_shift |
| 1615075936U, // SSRAv4i16_shift |
| 1615084321U, // SSRAv4i32_shift |
| 1615077797U, // SSRAv8i16_shift |
| 1615071275U, // SSRAv8i8_shift |
| 2714043167U, // SST1B_D |
| 2714043167U, // SST1B_D_IMM |
| 2714043167U, // SST1B_D_SXTW |
| 2714043167U, // SST1B_D_UXTW |
| 2714108703U, // SST1B_S_IMM |
| 2714108703U, // SST1B_S_SXTW |
| 2714108703U, // SST1B_S_UXTW |
| 2714046634U, // SST1D |
| 2714046634U, // SST1D_IMM |
| 2714046634U, // SST1D_SCALED |
| 2714046634U, // SST1D_SXTW |
| 2714046634U, // SST1D_SXTW_SCALED |
| 2714046634U, // SST1D_UXTW |
| 2714046634U, // SST1D_UXTW_SCALED |
| 2714048897U, // SST1H_D |
| 2714048897U, // SST1H_D_IMM |
| 2714048897U, // SST1H_D_SCALED |
| 2714048897U, // SST1H_D_SXTW |
| 2714048897U, // SST1H_D_SXTW_SCALED |
| 2714048897U, // SST1H_D_UXTW |
| 2714048897U, // SST1H_D_UXTW_SCALED |
| 2714114433U, // SST1H_S_IMM |
| 2714114433U, // SST1H_S_SXTW |
| 2714114433U, // SST1H_S_SXTW_SCALED |
| 2714114433U, // SST1H_S_UXTW |
| 2714114433U, // SST1H_S_UXTW_SCALED |
| 2714710168U, // SST1Q |
| 2714060453U, // SST1W_D |
| 2714060453U, // SST1W_D_IMM |
| 2714060453U, // SST1W_D_SCALED |
| 2714060453U, // SST1W_D_SXTW |
| 2714060453U, // SST1W_D_SXTW_SCALED |
| 2714060453U, // SST1W_D_UXTW |
| 2714060453U, // SST1W_D_UXTW_SCALED |
| 2714125989U, // SST1W_IMM |
| 2714125989U, // SST1W_SXTW |
| 2714125989U, // SST1W_SXTW_SCALED |
| 2714125989U, // SST1W_UXTW |
| 2714125989U, // SST1W_UXTW_SCALED |
| 541180592U, // SSUBLBT_ZZZ_D |
| 302138032U, // SSUBLBT_ZZZ_H |
| 3762471600U, // SSUBLBT_ZZZ_S |
| 541166765U, // SSUBLB_ZZZ_D |
| 302124205U, // SSUBLB_ZZZ_H |
| 3762457773U, // SSUBLB_ZZZ_S |
| 541167421U, // SSUBLTB_ZZZ_D |
| 302124861U, // SSUBLTB_ZZZ_H |
| 3762458429U, // SSUBLTB_ZZZ_S |
| 541180772U, // SSUBLT_ZZZ_D |
| 302138212U, // SSUBLT_ZZZ_H |
| 3762471780U, // SSUBLT_ZZZ_S |
| 1615011833U, // SSUBLv16i8_v8i16 |
| 1615008631U, // SSUBLv2i32_v2i64 |
| 1615019308U, // SSUBLv4i16_v4i32 |
| 1615008054U, // SSUBLv4i32_v2i64 |
| 1615018316U, // SSUBLv8i16_v4i32 |
| 1615012694U, // SSUBLv8i8_v8i16 |
| 541167519U, // SSUBWB_ZZZ_D |
| 71438239U, // SSUBWB_ZZZ_H |
| 541233055U, // SSUBWB_ZZZ_S |
| 541181218U, // SSUBWT_ZZZ_D |
| 71451938U, // SSUBWT_ZZZ_H |
| 541246754U, // SSUBWT_ZZZ_S |
| 1615012150U, // SSUBWv16i8_v8i16 |
| 1615009339U, // SSUBWv2i32_v2i64 |
| 1615020217U, // SSUBWv4i16_v4i32 |
| 1615008239U, // SSUBWv4i32_v2i64 |
| 1615018636U, // SSUBWv8i16_v4i32 |
| 1615013569U, // SSUBWv8i8_v8i16 |
| 2714010399U, // ST1B |
| 2848228127U, // ST1B_2Z |
| 2848228127U, // ST1B_2Z_IMM |
| 2848228127U, // ST1B_4Z |
| 2848228127U, // ST1B_4Z_IMM |
| 2714043167U, // ST1B_D |
| 2714043167U, // ST1B_D_IMM |
| 2714075935U, // ST1B_H |
| 2714075935U, // ST1B_H_IMM |
| 2714010399U, // ST1B_IMM |
| 2714108703U, // ST1B_S |
| 2714108703U, // ST1B_S_IMM |
| 2152792863U, // ST1B_VG2_M2ZPXI |
| 2152792863U, // ST1B_VG2_M2ZPXX |
| 2848228127U, // ST1B_VG4_M4ZPXI |
| 2848228127U, // ST1B_VG4_M4ZPXX |
| 2714046634U, // ST1D |
| 2848264362U, // ST1D_2Z |
| 2848264362U, // ST1D_2Z_IMM |
| 2848264362U, // ST1D_4Z |
| 2848264362U, // ST1D_4Z_IMM |
| 2714046634U, // ST1D_IMM |
| 2714701994U, // ST1D_Q |
| 2714701994U, // ST1D_Q_IMM |
| 2848264362U, // ST1D_VG2_M2ZPXI |
| 2848264362U, // ST1D_VG2_M2ZPXX |
| 2848264362U, // ST1D_VG4_M4ZPXI |
| 2848264362U, // ST1D_VG4_M4ZPXX |
| 1146947U, // ST1Fourv16b |
| 168951875U, // ST1Fourv16b_POST |
| 1212483U, // ST1Fourv1d |
| 173211715U, // ST1Fourv1d_POST |
| 1278019U, // ST1Fourv2d |
| 169082947U, // ST1Fourv2d_POST |
| 1343555U, // ST1Fourv2s |
| 173342787U, // ST1Fourv2s_POST |
| 1409091U, // ST1Fourv4h |
| 173408323U, // ST1Fourv4h_POST |
| 1474627U, // ST1Fourv4s |
| 169279555U, // ST1Fourv4s_POST |
| 1540163U, // ST1Fourv8b |
| 173539395U, // ST1Fourv8b_POST |
| 1605699U, // ST1Fourv8h |
| 169410627U, // ST1Fourv8h_POST |
| 2714081665U, // ST1H |
| 2848299393U, // ST1H_2Z |
| 2848299393U, // ST1H_2Z_IMM |
| 2848299393U, // ST1H_4Z |
| 2848299393U, // ST1H_4Z_IMM |
| 2714048897U, // ST1H_D |
| 2714048897U, // ST1H_D_IMM |
| 2714081665U, // ST1H_IMM |
| 2714114433U, // ST1H_S |
| 2714114433U, // ST1H_S_IMM |
| 2153355649U, // ST1H_VG2_M2ZPXI |
| 2153355649U, // ST1H_VG2_M2ZPXX |
| 2848299393U, // ST1H_VG4_M4ZPXI |
| 2848299393U, // ST1H_VG4_M4ZPXX |
| 1146947U, // ST1Onev16b |
| 177340483U, // ST1Onev16b_POST |
| 1212483U, // ST1Onev1d |
| 181600323U, // ST1Onev1d_POST |
| 1278019U, // ST1Onev2d |
| 177471555U, // ST1Onev2d_POST |
| 1343555U, // ST1Onev2s |
| 181731395U, // ST1Onev2s_POST |
| 1409091U, // ST1Onev4h |
| 181796931U, // ST1Onev4h_POST |
| 1474627U, // ST1Onev4s |
| 177668163U, // ST1Onev4s_POST |
| 1540163U, // ST1Onev8b |
| 181928003U, // ST1Onev8b_POST |
| 1605699U, // ST1Onev8h |
| 177799235U, // ST1Onev8h_POST |
| 1146947U, // ST1Threev16b |
| 198312003U, // ST1Threev16b_POST |
| 1212483U, // ST1Threev1d |
| 202571843U, // ST1Threev1d_POST |
| 1278019U, // ST1Threev2d |
| 198443075U, // ST1Threev2d_POST |
| 1343555U, // ST1Threev2s |
| 202702915U, // ST1Threev2s_POST |
| 1409091U, // ST1Threev4h |
| 202768451U, // ST1Threev4h_POST |
| 1474627U, // ST1Threev4s |
| 198639683U, // ST1Threev4s_POST |
| 1540163U, // ST1Threev8b |
| 202899523U, // ST1Threev8b_POST |
| 1605699U, // ST1Threev8h |
| 198770755U, // ST1Threev8h_POST |
| 1146947U, // ST1Twov16b |
| 173146179U, // ST1Twov16b_POST |
| 1212483U, // ST1Twov1d |
| 177406019U, // ST1Twov1d_POST |
| 1278019U, // ST1Twov2d |
| 173277251U, // ST1Twov2d_POST |
| 1343555U, // ST1Twov2s |
| 177537091U, // ST1Twov2s_POST |
| 1409091U, // ST1Twov4h |
| 177602627U, // ST1Twov4h_POST |
| 1474627U, // ST1Twov4s |
| 173473859U, // ST1Twov4s_POST |
| 1540163U, // ST1Twov8b |
| 177733699U, // ST1Twov8b_POST |
| 1605699U, // ST1Twov8h |
| 173604931U, // ST1Twov8h_POST |
| 2714125989U, // ST1W |
| 2848343717U, // ST1W_2Z |
| 2848343717U, // ST1W_2Z_IMM |
| 2848343717U, // ST1W_4Z |
| 2848343717U, // ST1W_4Z_IMM |
| 2714060453U, // ST1W_D |
| 2714060453U, // ST1W_D_IMM |
| 2714125989U, // ST1W_IMM |
| 2714715813U, // ST1W_Q |
| 2714715813U, // ST1W_Q_IMM |
| 2848343717U, // ST1W_VG2_M2ZPXI |
| 2848343717U, // ST1W_VG2_M2ZPXX |
| 2848343717U, // ST1W_VG4_M4ZPXI |
| 2848343717U, // ST1W_VG4_M4ZPXX |
| 114315104U, // ST1_MXIPXX_H_B |
| 114315118U, // ST1_MXIPXX_H_D |
| 114315132U, // ST1_MXIPXX_H_H |
| 114315146U, // ST1_MXIPXX_H_Q |
| 114315160U, // ST1_MXIPXX_H_S |
| 114347872U, // ST1_MXIPXX_V_B |
| 114347886U, // ST1_MXIPXX_V_D |
| 114347900U, // ST1_MXIPXX_V_H |
| 114347914U, // ST1_MXIPXX_V_Q |
| 114347928U, // ST1_MXIPXX_V_S |
| 328826947U, // ST1i16 |
| 3554279491U, // ST1i16_POST |
| 2457667U, // ST1i32 |
| 4091215939U, // ST1i32_POST |
| 2490435U, // ST1i64 |
| 333185091U, // ST1i64_POST |
| 328269891U, // ST1i8 |
| 870121539U, // ST1i8_POST |
| 2714010419U, // ST2B |
| 2714010419U, // ST2B_IMM |
| 2714048198U, // ST2D |
| 2714048198U, // ST2D_IMM |
| 75536513U, // ST2GOffset |
| 1686739073U, // ST2GPostIndex |
| 1686739073U, // ST2GPreIndex |
| 2714081739U, // ST2H |
| 2714081739U, // ST2H_IMM |
| 2714710180U, // ST2Q |
| 2714710180U, // ST2Q_IMM |
| 1147057U, // ST2Twov16b |
| 173146289U, // ST2Twov16b_POST |
| 1278129U, // ST2Twov2d |
| 173277361U, // ST2Twov2d_POST |
| 1343665U, // ST2Twov2s |
| 177537201U, // ST2Twov2s_POST |
| 1409201U, // ST2Twov4h |
| 177602737U, // ST2Twov4h_POST |
| 1474737U, // ST2Twov4s |
| 173473969U, // ST2Twov4s_POST |
| 1540273U, // ST2Twov8b |
| 177733809U, // ST2Twov8b_POST |
| 1605809U, // ST2Twov8h |
| 173605041U, // ST2Twov8h_POST |
| 2714126009U, // ST2W |
| 2714126009U, // ST2W_IMM |
| 328827057U, // ST2i16 |
| 4091150513U, // ST2i16_POST |
| 2457777U, // ST2i32 |
| 333119665U, // ST2i32_POST |
| 2490545U, // ST2i64 |
| 1406927025U, // ST2i64_POST |
| 328270001U, // ST2i8 |
| 3554476209U, // ST2i8_POST |
| 2714010431U, // ST3B |
| 2714010431U, // ST3B_IMM |
| 2714048210U, // ST3D |
| 2714048210U, // ST3D_IMM |
| 2714081751U, // ST3H |
| 2714081751U, // ST3H_IMM |
| 2714710192U, // ST3Q |
| 2714710192U, // ST3Q_IMM |
| 1147080U, // ST3Threev16b |
| 198312136U, // ST3Threev16b_POST |
| 1278152U, // ST3Threev2d |
| 198443208U, // ST3Threev2d_POST |
| 1343688U, // ST3Threev2s |
| 202703048U, // ST3Threev2s_POST |
| 1409224U, // ST3Threev4h |
| 202768584U, // ST3Threev4h_POST |
| 1474760U, // ST3Threev4s |
| 198639816U, // ST3Threev4s_POST |
| 1540296U, // ST3Threev8b |
| 202899656U, // ST3Threev8b_POST |
| 1605832U, // ST3Threev8h |
| 198770888U, // ST3Threev8h_POST |
| 2714126021U, // ST3W |
| 2714126021U, // ST3W_IMM |
| 328827080U, // ST3i16 |
| 1943666888U, // ST3i16_POST |
| 2457800U, // ST3i32 |
| 2480603336U, // ST3i32_POST |
| 2490568U, // ST3i64 |
| 3017539784U, // ST3i64_POST |
| 328270024U, // ST3i8 |
| 3554476232U, // ST3i8_POST |
| 2714010457U, // ST4B |
| 2714010457U, // ST4B_IMM |
| 2714048222U, // ST4D |
| 2714048222U, // ST4D_IMM |
| 1147097U, // ST4Fourv16b |
| 168952025U, // ST4Fourv16b_POST |
| 1278169U, // ST4Fourv2d |
| 169083097U, // ST4Fourv2d_POST |
| 1343705U, // ST4Fourv2s |
| 173342937U, // ST4Fourv2s_POST |
| 1409241U, // ST4Fourv4h |
| 173408473U, // ST4Fourv4h_POST |
| 1474777U, // ST4Fourv4s |
| 169279705U, // ST4Fourv4s_POST |
| 1540313U, // ST4Fourv8b |
| 173539545U, // ST4Fourv8b_POST |
| 1605849U, // ST4Fourv8h |
| 169410777U, // ST4Fourv8h_POST |
| 2714083234U, // ST4H |
| 2714083234U, // ST4H_IMM |
| 2714710204U, // ST4Q |
| 2714710204U, // ST4Q_IMM |
| 2714126033U, // ST4W |
| 2714126033U, // ST4W_IMM |
| 328827097U, // ST4i16 |
| 333054169U, // ST4i16_POST |
| 2457817U, // ST4i32 |
| 1406861529U, // ST4i32_POST |
| 2490585U, // ST4i64 |
| 4091281625U, // ST4i64_POST |
| 328270041U, // ST4i8 |
| 4091347161U, // ST4i8_POST |
| 1966924U, // ST64B |
| 4244886U, // ST64BV |
| 4227073U, // ST64BV0 |
| 75541965U, // STGM |
| 75536577U, // STGOffset |
| 4239150U, // STGPi |
| 1686739137U, // STGPostIndex |
| 1615441710U, // STGPpost |
| 1615441710U, // STGPpre |
| 1686739137U, // STGPreIndex |
| 4239177U, // STILPW |
| 1615441737U, // STILPWpre |
| 4239177U, // STILPX |
| 1615441737U, // STILPXpre |
| 2490383U, // STL1 |
| 75533912U, // STLLRB |
| 75540741U, // STLLRH |
| 75542995U, // STLLRW |
| 75542995U, // STLLRX |
| 75533920U, // STLRB |
| 75540749U, // STLRH |
| 75543008U, // STLRW |
| 1686745568U, // STLRWpre |
| 75543008U, // STLRX |
| 1686745568U, // STLRXpre |
| 75533970U, // STLURBi |
| 75540799U, // STLURHi |
| 75543111U, // STLURWi |
| 75543111U, // STLURXi |
| 75543111U, // STLURbi |
| 75543111U, // STLURdi |
| 75543111U, // STLURhi |
| 75543111U, // STLURqi |
| 75543111U, // STLURsi |
| 4239467U, // STLXPW |
| 4239467U, // STLXPX |
| 4230841U, // STLXRB |
| 4237670U, // STLXRH |
| 4240007U, // STLXRW |
| 4240007U, // STLXRX |
| 4239267U, // STNPDi |
| 4239267U, // STNPQi |
| 4239267U, // STNPSi |
| 4239267U, // STNPWi |
| 4239267U, // STNPXi |
| 2848228119U, // STNT1B_2Z |
| 2848228119U, // STNT1B_2Z_IMM |
| 2848228119U, // STNT1B_4Z |
| 2848228119U, // STNT1B_4Z_IMM |
| 2152792855U, // STNT1B_VG2_M2ZPXI |
| 2152792855U, // STNT1B_VG2_M2ZPXX |
| 2848228119U, // STNT1B_VG4_M4ZPXI |
| 2848228119U, // STNT1B_VG4_M4ZPXX |
| 2714010391U, // STNT1B_ZRI |
| 2714010391U, // STNT1B_ZRR |
| 2714043159U, // STNT1B_ZZR_D_REAL |
| 2714108695U, // STNT1B_ZZR_S_REAL |
| 2848264354U, // STNT1D_2Z |
| 2848264354U, // STNT1D_2Z_IMM |
| 2848264354U, // STNT1D_4Z |
| 2848264354U, // STNT1D_4Z_IMM |
| 2848264354U, // STNT1D_VG2_M2ZPXI |
| 2848264354U, // STNT1D_VG2_M2ZPXX |
| 2848264354U, // STNT1D_VG4_M4ZPXI |
| 2848264354U, // STNT1D_VG4_M4ZPXX |
| 2714046626U, // STNT1D_ZRI |
| 2714046626U, // STNT1D_ZRR |
| 2714046626U, // STNT1D_ZZR_D_REAL |
| 2848299385U, // STNT1H_2Z |
| 2848299385U, // STNT1H_2Z_IMM |
| 2848299385U, // STNT1H_4Z |
| 2848299385U, // STNT1H_4Z_IMM |
| 2153355641U, // STNT1H_VG2_M2ZPXI |
| 2153355641U, // STNT1H_VG2_M2ZPXX |
| 2848299385U, // STNT1H_VG4_M4ZPXI |
| 2848299385U, // STNT1H_VG4_M4ZPXX |
| 2714081657U, // STNT1H_ZRI |
| 2714081657U, // STNT1H_ZRR |
| 2714048889U, // STNT1H_ZZR_D_REAL |
| 2714114425U, // STNT1H_ZZR_S_REAL |
| 2848343709U, // STNT1W_2Z |
| 2848343709U, // STNT1W_2Z_IMM |
| 2848343709U, // STNT1W_4Z |
| 2848343709U, // STNT1W_4Z_IMM |
| 2848343709U, // STNT1W_VG2_M2ZPXI |
| 2848343709U, // STNT1W_VG2_M2ZPXX |
| 2848343709U, // STNT1W_VG4_M4ZPXI |
| 2848343709U, // STNT1W_VG4_M4ZPXX |
| 2714125981U, // STNT1W_ZRI |
| 2714125981U, // STNT1W_ZRR |
| 2714060445U, // STNT1W_ZZR_D_REAL |
| 2714125981U, // STNT1W_ZZR_S_REAL |
| 4239405U, // STPDi |
| 1615441965U, // STPDpost |
| 1615441965U, // STPDpre |
| 4239405U, // STPQi |
| 1615441965U, // STPQpost |
| 1615441965U, // STPQpre |
| 4239405U, // STPSi |
| 1615441965U, // STPSpost |
| 1615441965U, // STPSpre |
| 4239405U, // STPWi |
| 1615441965U, // STPWpost |
| 1615441965U, // STPWpre |
| 4239405U, // STPXi |
| 1615441965U, // STPXpost |
| 1615441965U, // STPXpre |
| 1686736510U, // STRBBpost |
| 1686736510U, // STRBBpre |
| 75533950U, // STRBBroW |
| 75533950U, // STRBBroX |
| 75533950U, // STRBBui |
| 1686745648U, // STRBpost |
| 1686745648U, // STRBpre |
| 75543088U, // STRBroW |
| 75543088U, // STRBroX |
| 75543088U, // STRBui |
| 1686745648U, // STRDpost |
| 1686745648U, // STRDpre |
| 75543088U, // STRDroW |
| 75543088U, // STRDroX |
| 75543088U, // STRDui |
| 1686743339U, // STRHHpost |
| 1686743339U, // STRHHpre |
| 75540779U, // STRHHroW |
| 75540779U, // STRHHroX |
| 75540779U, // STRHHui |
| 1686745648U, // STRHpost |
| 1686745648U, // STRHpre |
| 75543088U, // STRHroW |
| 75543088U, // STRHroX |
| 75543088U, // STRHui |
| 1686745648U, // STRQpost |
| 1686745648U, // STRQpre |
| 75543088U, // STRQroW |
| 75543088U, // STRQroX |
| 75543088U, // STRQui |
| 1686745648U, // STRSpost |
| 1686745648U, // STRSpre |
| 75543088U, // STRSroW |
| 75543088U, // STRSroX |
| 75543088U, // STRSui |
| 1686745648U, // STRWpost |
| 1686745648U, // STRWpre |
| 75543088U, // STRWroW |
| 75543088U, // STRWroX |
| 75543088U, // STRWui |
| 1686745648U, // STRXpost |
| 1686745648U, // STRXpre |
| 75543088U, // STRXroW |
| 75543088U, // STRXroX |
| 75543088U, // STRXui |
| 77541936U, // STR_PXI |
| 75543088U, // STR_TX |
| 2077232U, // STR_ZA |
| 77541936U, // STR_ZXI |
| 75533956U, // STTRBi |
| 75540785U, // STTRHi |
| 75543093U, // STTRWi |
| 75543093U, // STTRXi |
| 75533987U, // STURBBi |
| 75543126U, // STURBi |
| 75543126U, // STURDi |
| 75540816U, // STURHHi |
| 75543126U, // STURHi |
| 75543126U, // STURQi |
| 75543126U, // STURSi |
| 75543126U, // STURWi |
| 75543126U, // STURXi |
| 4239474U, // STXPW |
| 4239474U, // STXPX |
| 4230849U, // STXRB |
| 4237678U, // STXRH |
| 4240014U, // STXRW |
| 4240014U, // STXRX |
| 75536519U, // STZ2GOffset |
| 1686739079U, // STZ2GPostIndex |
| 1686739079U, // STZ2GPreIndex |
| 75541971U, // STZGM |
| 75536582U, // STZGOffset |
| 1686739142U, // STZGPostIndex |
| 1686739142U, // STZGPreIndex |
| 4233358U, // SUBG |
| 3762359712U, // SUBHNB_ZZZ_B |
| 21106080U, // SUBHNB_ZZZ_H |
| 541232544U, // SUBHNB_ZZZ_S |
| 1078019109U, // SUBHNT_ZZZ_B |
| 25314341U, // SUBHNT_ZZZ_H |
| 2151859237U, // SUBHNT_ZZZ_S |
| 1615017392U, // SUBHNv2i64_v2i32 |
| 1615084011U, // SUBHNv2i64_v4i32 |
| 1615010916U, // SUBHNv4i32_v4i16 |
| 1615077513U, // SUBHNv4i32_v8i16 |
| 1615070089U, // SUBHNv8i16_v16i8 |
| 1615006063U, // SUBHNv8i16_v8i8 |
| 4239094U, // SUBP |
| 4244011U, // SUBPS |
| 4272412U, // SUBR_ZI_B |
| 541176092U, // SUBR_ZI_D |
| 71446812U, // SUBR_ZI_H |
| 541241628U, // SUBR_ZI_S |
| 2151756060U, // SUBR_ZPmZ_B |
| 2151788828U, // SUBR_ZPmZ_D |
| 2713858332U, // SUBR_ZPmZ_H |
| 2151854364U, // SUBR_ZPmZ_S |
| 4243880U, // SUBSWri |
| 4243880U, // SUBSWrs |
| 4243880U, // SUBSWrx |
| 4243880U, // SUBSXri |
| 4243880U, // SUBSXrs |
| 4243880U, // SUBSXrx |
| 4243880U, // SUBSXrx64 |
| 4231017U, // SUBWri |
| 4231017U, // SUBWrs |
| 4231017U, // SUBWrx |
| 4231017U, // SUBXri |
| 4231017U, // SUBXrs |
| 4231017U, // SUBXrx |
| 4231017U, // SUBXrx64 |
| 3288764265U, // SUB_VG2_M2Z2Z_D |
| 3288797033U, // SUB_VG2_M2Z2Z_S |
| 3288764265U, // SUB_VG2_M2ZZ_D |
| 3288797033U, // SUB_VG2_M2ZZ_S |
| 3288764265U, // SUB_VG2_M2Z_D |
| 3288797033U, // SUB_VG2_M2Z_S |
| 3825635177U, // SUB_VG4_M4Z4Z_D |
| 3825667945U, // SUB_VG4_M4Z4Z_S |
| 3825635177U, // SUB_VG4_M4ZZ_D |
| 3825667945U, // SUB_VG4_M4ZZ_S |
| 3825635177U, // SUB_VG4_M4Z_D |
| 3825667945U, // SUB_VG4_M4Z_S |
| 4263785U, // SUB_ZI_B |
| 541167465U, // SUB_ZI_D |
| 71438185U, // SUB_ZI_H |
| 541233001U, // SUB_ZI_S |
| 2151747433U, // SUB_ZPmZ_B |
| 2151780201U, // SUB_ZPmZ_D |
| 2713849705U, // SUB_ZPmZ_H |
| 2151845737U, // SUB_ZPmZ_S |
| 4263785U, // SUB_ZZZ_B |
| 541167465U, // SUB_ZZZ_D |
| 71438185U, // SUB_ZZZ_H |
| 541233001U, // SUB_ZZZ_S |
| 1615004833U, // SUBv16i8 |
| 4231017U, // SUBv1i64 |
| 1615016883U, // SUBv2i32 |
| 1615008352U, // SUBv2i64 |
| 1615010430U, // SUBv4i16 |
| 1615018839U, // SUBv4i32 |
| 1615012291U, // SUBv8i16 |
| 1615005759U, // SUBv8i8 |
| 3288810678U, // SUDOT_VG2_M2ZZI_BToS |
| 3288810678U, // SUDOT_VG2_M2ZZ_BToS |
| 3825681590U, // SUDOT_VG4_M4ZZI_BToS |
| 3825681590U, // SUDOT_VG4_M4ZZ_BToS |
| 4375734U, // SUDOT_ZZZI |
| 1615086774U, // SUDOTlanev16i8 |
| 1615086774U, // SUDOTlanev8i8 |
| 3003591723U, // SUMLALL_MZZI_BtoS |
| 3540462635U, // SUMLALL_VG2_M2ZZI_BtoS |
| 856108075U, // SUMLALL_VG2_M2ZZ_BtoS |
| 4077333547U, // SUMLALL_VG4_M4ZZI_BtoS |
| 1392978987U, // SUMLALL_VG4_M4ZZ_BtoS |
| 100893088U, // SUMOPA_MPPZZ_D |
| 323191200U, // SUMOPA_MPPZZ_S |
| 100909649U, // SUMOPS_MPPZZ_D |
| 323207761U, // SUMOPS_MPPZZ_S |
| 541174299U, // SUNPKHI_ZZ_D |
| 3523357211U, // SUNPKHI_ZZ_H |
| 3762465307U, // SUNPKHI_ZZ_S |
| 541175504U, // SUNPKLO_ZZ_D |
| 3523358416U, // SUNPKLO_ZZ_H |
| 3762466512U, // SUNPKLO_ZZ_S |
| 3242535511U, // SUNPK_VG2_2ZZ_D |
| 3523586647U, // SUNPK_VG2_2ZZ_H |
| 3292932695U, // SUNPK_VG2_2ZZ_S |
| 3284478551U, // SUNPK_VG4_4Z2Z_D |
| 3271928407U, // SUNPK_VG4_4Z2Z_H |
| 3280349783U, // SUNPK_VG4_4Z2Z_S |
| 2151749507U, // SUQADD_ZPmZ_B |
| 2151782275U, // SUQADD_ZPmZ_D |
| 2713851779U, // SUQADD_ZPmZ_H |
| 2151847811U, // SUQADD_ZPmZ_S |
| 1615070521U, // SUQADDv16i8 |
| 1615435651U, // SUQADDv1i16 |
| 1615435651U, // SUQADDv1i32 |
| 1615435651U, // SUQADDv1i64 |
| 1615435651U, // SUQADDv1i8 |
| 1615082574U, // SUQADDv2i32 |
| 1615073955U, // SUQADDv2i64 |
| 1615076121U, // SUQADDv4i16 |
| 1615084540U, // SUQADDv4i32 |
| 1615077982U, // SUQADDv8i16 |
| 1615071412U, // SUQADDv8i8 |
| 3825681613U, // SUVDOT_VG4_M4ZZI_BToS |
| 757787U, // SVC |
| 3288810694U, // SVDOT_VG2_M2ZZI_HtoS |
| 3825681606U, // SVDOT_VG4_M4ZZI_BtoS |
| 3825648838U, // SVDOT_VG4_M4ZZI_HtoD |
| 2689174373U, // SWPAB |
| 2689181534U, // SWPAH |
| 2689174633U, // SWPALB |
| 2689181690U, // SWPALH |
| 2689182496U, // SWPALW |
| 2689182496U, // SWPALX |
| 2689171986U, // SWPAW |
| 2689171986U, // SWPAX |
| 2689175078U, // SWPB |
| 2689181907U, // SWPH |
| 2689174842U, // SWPLB |
| 2689181787U, // SWPLH |
| 2689182936U, // SWPLW |
| 2689182936U, // SWPLX |
| 6205365U, // SWPP |
| 6193580U, // SWPPA |
| 6204080U, // SWPPAL |
| 6204522U, // SWPPL |
| 2689183804U, // SWPW |
| 2689183804U, // SWPX |
| 541167451U, // SXTB_ZPmZ_D |
| 1082265435U, // SXTB_ZPmZ_H |
| 541232987U, // SXTB_ZPmZ_S |
| 541174238U, // SXTH_ZPmZ_D |
| 541239774U, // SXTH_ZPmZ_S |
| 541181822U, // SXTW_ZPmZ_D |
| 4238658U, // SYSLxt |
| 541110270U, // SYSPxt |
| 541110270U, // SYSPxt_XZR |
| 541115023U, // SYSxt |
| 541143257U, // TBLQ_ZZZ_B |
| 1078046937U, // TBLQ_ZZZ_D |
| 58863833U, // TBLQ_ZZZ_H |
| 1614983385U, // TBLQ_ZZZ_S |
| 541141919U, // TBL_ZZZZ_B |
| 1078045599U, // TBL_ZZZZ_D |
| 58862495U, // TBL_ZZZZ_H |
| 1614982047U, // TBL_ZZZZ_S |
| 541141919U, // TBL_ZZZ_B |
| 1078045599U, // TBL_ZZZ_D |
| 58862495U, // TBL_ZZZ_H |
| 1614982047U, // TBL_ZZZ_S |
| 1644374943U, // TBLv16i8Four |
| 1644374943U, // TBLv16i8One |
| 1644374943U, // TBLv16i8Three |
| 1644374943U, // TBLv16i8Two |
| 1946364831U, // TBLv8i8Four |
| 1946364831U, // TBLv8i8One |
| 1946364831U, // TBLv8i8Three |
| 1946364831U, // TBLv8i8Two |
| 4245609U, // TBNZW |
| 4245609U, // TBNZX |
| 4272363U, // TBXQ_ZZZ_B |
| 2151788779U, // TBXQ_ZZZ_D |
| 84029675U, // TBXQ_ZZZ_H |
| 2688725227U, // TBXQ_ZZZ_S |
| 4278217U, // TBX_ZZZ_B |
| 2151794633U, // TBX_ZZZ_D |
| 84035529U, // TBX_ZZZ_H |
| 2688731081U, // TBX_ZZZ_S |
| 2181318601U, // TBXv16i8Four |
| 2181318601U, // TBXv16i8One |
| 2181318601U, // TBXv16i8Three |
| 2181318601U, // TBXv16i8Two |
| 2483308489U, // TBXv8i8Four |
| 2483308489U, // TBXv8i8One |
| 2483308489U, // TBXv8i8Three |
| 2483308489U, // TBXv8i8Two |
| 4245593U, // TBZW |
| 4245593U, // TBZX |
| 764876U, // TCANCEL |
| 20274U, // TCOMMIT |
| 49956U, // TRCIT |
| 4259861U, // TRN1_PPP_B |
| 541163541U, // TRN1_PPP_D |
| 71434261U, // TRN1_PPP_H |
| 541229077U, // TRN1_PPP_S |
| 4259861U, // TRN1_ZZZ_B |
| 541163541U, // TRN1_ZZZ_D |
| 71434261U, // TRN1_ZZZ_H |
| 118390805U, // TRN1_ZZZ_Q |
| 541229077U, // TRN1_ZZZ_S |
| 1615004511U, // TRN1v16i8 |
| 1615016732U, // TRN1v2i32 |
| 1615007934U, // TRN1v2i64 |
| 1615010269U, // TRN1v4i16 |
| 1615018168U, // TRN1v4i32 |
| 1615011752U, // TRN1v8i16 |
| 1615005609U, // TRN1v8i8 |
| 4259961U, // TRN2_PPP_B |
| 541163641U, // TRN2_PPP_D |
| 71434361U, // TRN2_PPP_H |
| 541229177U, // TRN2_PPP_S |
| 4259961U, // TRN2_ZZZ_B |
| 541163641U, // TRN2_ZZZ_D |
| 71434361U, // TRN2_ZZZ_H |
| 118390905U, // TRN2_ZZZ_Q |
| 541229177U, // TRN2_ZZZ_S |
| 1615004632U, // TRN2v16i8 |
| 1615016759U, // TRN2v2i32 |
| 1615008212U, // TRN2v2i64 |
| 1615010306U, // TRN2v4i16 |
| 1615018548U, // TRN2v4i32 |
| 1615012050U, // TRN2v8i16 |
| 1615005646U, // TRN2v8i8 |
| 888624U, // TSB |
| 50395U, // TSTART |
| 50417U, // TTEST |
| 2688650270U, // UABALB_ZZZ_D |
| 314706974U, // UABALB_ZZZ_H |
| 1078103070U, // UABALB_ZZZ_S |
| 2688664377U, // UABALT_ZZZ_D |
| 314721081U, // UABALT_ZZZ_H |
| 1078117177U, // UABALT_ZZZ_S |
| 1615077336U, // UABALv16i8_v8i16 |
| 1615074125U, // UABALv2i32_v2i64 |
| 1615084802U, // UABALv4i16_v4i32 |
| 1615073544U, // UABALv4i32_v2i64 |
| 1615083806U, // UABALv8i16_v4i32 |
| 1615078200U, // UABALv8i8_v8i16 |
| 4260095U, // UABA_ZZZ_B |
| 2151776511U, // UABA_ZZZ_D |
| 84017407U, // UABA_ZZZ_H |
| 2688712959U, // UABA_ZZZ_S |
| 1615070306U, // UABAv16i8 |
| 1615082341U, // UABAv2i32 |
| 1615075888U, // UABAv4i16 |
| 1615084273U, // UABAv4i32 |
| 1615077749U, // UABAv8i16 |
| 1615071238U, // UABAv8i8 |
| 541166803U, // UABDLB_ZZZ_D |
| 302124243U, // UABDLB_ZZZ_H |
| 3762457811U, // UABDLB_ZZZ_S |
| 541180810U, // UABDLT_ZZZ_D |
| 302138250U, // UABDLT_ZZZ_H |
| 3762471818U, // UABDLT_ZZZ_S |
| 1615011866U, // UABDLv16i8_v8i16 |
| 1615008661U, // UABDLv2i32_v2i64 |
| 1615019338U, // UABDLv4i16_v4i32 |
| 1615008087U, // UABDLv4i32_v2i64 |
| 1615018349U, // UABDLv8i16_v4i32 |
| 1615012724U, // UABDLv8i8_v8i16 |
| 2151749380U, // UABD_ZPmZ_B |
| 2151782148U, // UABD_ZPmZ_D |
| 2713851652U, // UABD_ZPmZ_H |
| 2151847684U, // UABD_ZPmZ_S |
| 1615004917U, // UABDv16i8 |
| 1615016957U, // UABDv2i32 |
| 1615010504U, // UABDv4i16 |
| 1615018923U, // UABDv4i32 |
| 1615012365U, // UABDv8i16 |
| 1615005814U, // UABDv8i8 |
| 2151788353U, // UADALP_ZPmZ_D |
| 2713857857U, // UADALP_ZPmZ_H |
| 2151853889U, // UADALP_ZPmZ_S |
| 1615078541U, // UADALPv16i8_v8i16 |
| 1615073379U, // UADALPv2i32_v1i64 |
| 1615083110U, // UADALPv4i16_v2i32 |
| 1615074474U, // UADALPv4i32_v2i64 |
| 1615085189U, // UADALPv8i16_v4i32 |
| 1615076645U, // UADALPv8i8_v4i16 |
| 541166828U, // UADDLB_ZZZ_D |
| 302124268U, // UADDLB_ZZZ_H |
| 3762457836U, // UADDLB_ZZZ_S |
| 1615013027U, // UADDLPv16i8_v8i16 |
| 1615007865U, // UADDLPv2i32_v1i64 |
| 1615017596U, // UADDLPv4i16_v2i32 |
| 1615008960U, // UADDLPv4i32_v2i64 |
| 1615019675U, // UADDLPv8i16_v4i32 |
| 1615011131U, // UADDLPv8i8_v4i16 |
| 541180826U, // UADDLT_ZZZ_D |
| 302138266U, // UADDLT_ZZZ_H |
| 3762471834U, // UADDLT_ZZZ_S |
| 1614841674U, // UADDLVv16i8v |
| 1614847729U, // UADDLVv4i16v |
| 1614856273U, // UADDLVv4i32v |
| 1614849625U, // UADDLVv8i16v |
| 1614842619U, // UADDLVv8i8v |
| 1615011888U, // UADDLv16i8_v8i16 |
| 1615008681U, // UADDLv2i32_v2i64 |
| 1615019358U, // UADDLv4i16_v4i32 |
| 1615008109U, // UADDLv4i32_v2i64 |
| 1615018371U, // UADDLv8i16_v4i32 |
| 1615012744U, // UADDLv8i8_v8i16 |
| 3536340396U, // UADDV_VPZ_B |
| 3301459372U, // UADDV_VPZ_D |
| 3305653676U, // UADDV_VPZ_H |
| 3246933420U, // UADDV_VPZ_S |
| 541167543U, // UADDWB_ZZZ_D |
| 71438263U, // UADDWB_ZZZ_H |
| 541233079U, // UADDWB_ZZZ_S |
| 541181242U, // UADDWT_ZZZ_D |
| 71451962U, // UADDWT_ZZZ_H |
| 541246778U, // UADDWT_ZZZ_S |
| 1615012183U, // UADDWv16i8_v8i16 |
| 1615009369U, // UADDWv2i32_v2i64 |
| 1615020247U, // UADDWv4i16_v4i32 |
| 1615008272U, // UADDWv4i32_v2i64 |
| 1615018669U, // UADDWv8i16_v4i32 |
| 1615013599U, // UADDWv8i8_v8i16 |
| 4238778U, // UBFMWri |
| 4238778U, // UBFMXri |
| 314879841U, // UCLAMP_VG2_2Z2Z_B |
| 80031585U, // UCLAMP_VG2_2Z2Z_D |
| 84258657U, // UCLAMP_VG2_2Z2Z_H |
| 25571169U, // UCLAMP_VG2_2Z2Z_S |
| 314879841U, // UCLAMP_VG4_4Z4Z_B |
| 80031585U, // UCLAMP_VG4_4Z4Z_D |
| 84258657U, // UCLAMP_VG4_4Z4Z_H |
| 25571169U, // UCLAMP_VG4_4Z4Z_S |
| 4271969U, // UCLAMP_ZZZ_B |
| 541175649U, // UCLAMP_ZZZ_D |
| 71446369U, // UCLAMP_ZZZ_H |
| 541241185U, // UCLAMP_ZZZ_S |
| 4233338U, // UCVTFSWDri |
| 4233338U, // UCVTFSWHri |
| 4233338U, // UCVTFSWSri |
| 4233338U, // UCVTFSXDri |
| 4233338U, // UCVTFSXHri |
| 4233338U, // UCVTFSXSri |
| 4233338U, // UCVTFUWDri |
| 4233338U, // UCVTFUWHri |
| 4233338U, // UCVTFUWSri |
| 4233338U, // UCVTFUXDri |
| 4233338U, // UCVTFUXHri |
| 4233338U, // UCVTFUXSri |
| 3284539514U, // UCVTF_2Z2Z_StoS |
| 3284539514U, // UCVTF_4Z4Z_StoS |
| 541169786U, // UCVTF_ZPmZ_DtoD |
| 1619138682U, // UCVTF_ZPmZ_DtoH |
| 541235322U, // UCVTF_ZPmZ_DtoS |
| 1082267770U, // UCVTF_ZPmZ_HtoH |
| 541169786U, // UCVTF_ZPmZ_StoD |
| 2156009594U, // UCVTF_ZPmZ_StoH |
| 541235322U, // UCVTF_ZPmZ_StoS |
| 4233338U, // UCVTFd |
| 4233338U, // UCVTFh |
| 4233338U, // UCVTFs |
| 4233338U, // UCVTFv1i16 |
| 4233338U, // UCVTFv1i32 |
| 4233338U, // UCVTFv1i64 |
| 1615017135U, // UCVTFv2f32 |
| 1615008493U, // UCVTFv2f64 |
| 1615017135U, // UCVTFv2i32_shift |
| 1615008493U, // UCVTFv2i64_shift |
| 1615010659U, // UCVTFv4f16 |
| 1615019110U, // UCVTFv4f32 |
| 1615010659U, // UCVTFv4i16_shift |
| 1615019110U, // UCVTFv4i32_shift |
| 1615012520U, // UCVTFv8f16 |
| 1615012520U, // UCVTFv8i16_shift |
| 39022U, // UDF |
| 2151789162U, // UDIVR_ZPmZ_D |
| 2151854698U, // UDIVR_ZPmZ_S |
| 4244938U, // UDIVWr |
| 4244938U, // UDIVXr |
| 2151794122U, // UDIV_ZPmZ_D |
| 2151859658U, // UDIV_ZPmZ_S |
| 3288810679U, // UDOT_VG2_M2Z2Z_BtoS |
| 3288777911U, // UDOT_VG2_M2Z2Z_HtoD |
| 3288810679U, // UDOT_VG2_M2Z2Z_HtoS |
| 3288810679U, // UDOT_VG2_M2ZZI_BToS |
| 3288810679U, // UDOT_VG2_M2ZZI_HToS |
| 3288777911U, // UDOT_VG2_M2ZZI_HtoD |
| 3288810679U, // UDOT_VG2_M2ZZ_BtoS |
| 3288777911U, // UDOT_VG2_M2ZZ_HtoD |
| 3288810679U, // UDOT_VG2_M2ZZ_HtoS |
| 3825681591U, // UDOT_VG4_M4Z4Z_BtoS |
| 3825648823U, // UDOT_VG4_M4Z4Z_HtoD |
| 3825681591U, // UDOT_VG4_M4Z4Z_HtoS |
| 3825681591U, // UDOT_VG4_M4ZZI_BtoS |
| 3825681591U, // UDOT_VG4_M4ZZI_HToS |
| 3825648823U, // UDOT_VG4_M4ZZI_HtoD |
| 3825681591U, // UDOT_VG4_M4ZZ_BtoS |
| 3825648823U, // UDOT_VG4_M4ZZ_HtoD |
| 3825681591U, // UDOT_VG4_M4ZZ_HtoS |
| 1078052023U, // UDOT_ZZZI_D |
| 1078117559U, // UDOT_ZZZI_HtoS |
| 4375735U, // UDOT_ZZZI_S |
| 1078052023U, // UDOT_ZZZ_D |
| 1078117559U, // UDOT_ZZZ_HtoS |
| 4375735U, // UDOT_ZZZ_S |
| 1615086775U, // UDOTlanev16i8 |
| 1615086775U, // UDOTlanev8i8 |
| 20302U, // UDOTv16i8 |
| 20302U, // UDOTv8i8 |
| 2151749477U, // UHADD_ZPmZ_B |
| 2151782245U, // UHADD_ZPmZ_D |
| 2713851749U, // UHADD_ZPmZ_H |
| 2151847781U, // UHADD_ZPmZ_S |
| 1615004962U, // UHADDv16i8 |
| 1615017017U, // UHADDv2i32 |
| 1615010564U, // UHADDv4i16 |
| 1615018983U, // UHADDv4i32 |
| 1615012425U, // UHADDv8i16 |
| 1615005855U, // UHADDv8i8 |
| 2151756074U, // UHSUBR_ZPmZ_B |
| 2151788842U, // UHSUBR_ZPmZ_D |
| 2713858346U, // UHSUBR_ZPmZ_H |
| 2151854378U, // UHSUBR_ZPmZ_S |
| 2151747445U, // UHSUB_ZPmZ_B |
| 2151780213U, // UHSUB_ZPmZ_D |
| 2713849717U, // UHSUB_ZPmZ_H |
| 2151845749U, // UHSUB_ZPmZ_S |
| 1615004842U, // UHSUBv16i8 |
| 1615016901U, // UHSUBv2i32 |
| 1615010448U, // UHSUBv4i16 |
| 1615018857U, // UHSUBv4i32 |
| 1615012309U, // UHSUBv8i16 |
| 1615005767U, // UHSUBv8i8 |
| 4238276U, // UMADDLrrr |
| 2151755870U, // UMAXP_ZPmZ_B |
| 2151788638U, // UMAXP_ZPmZ_D |
| 2713858142U, // UMAXP_ZPmZ_H |
| 2151854174U, // UMAXP_ZPmZ_S |
| 1615005292U, // UMAXPv16i8 |
| 1615017700U, // UMAXPv2i32 |
| 1615011235U, // UMAXPv4i16 |
| 1615019779U, // UMAXPv4i32 |
| 1615013131U, // UMAXPv8i16 |
| 1615006259U, // UMAXPv8i8 |
| 2181252700U, // UMAXQV_VPZ_B |
| 2185447004U, // UMAXQV_VPZ_D |
| 2189641308U, // UMAXQV_VPZ_H |
| 2193835612U, // UMAXQV_VPZ_S |
| 509560U, // UMAXV_VPZ_B |
| 3301459576U, // UMAXV_VPZ_D |
| 3305686648U, // UMAXV_VPZ_H |
| 3246999160U, // UMAXV_VPZ_S |
| 1614841719U, // UMAXVv16i8v |
| 1614847823U, // UMAXVv4i16v |
| 1614856367U, // UMAXVv4i32v |
| 1614849719U, // UMAXVv8i16v |
| 1614842660U, // UMAXVv8i8v |
| 4245443U, // UMAXWri |
| 4245443U, // UMAXWrr |
| 4245443U, // UMAXXri |
| 4245443U, // UMAXXrr |
| 50644931U, // UMAX_VG2_2Z2Z_B |
| 54872003U, // UMAX_VG2_2Z2Z_D |
| 59099075U, // UMAX_VG2_2Z2Z_H |
| 63326147U, // UMAX_VG2_2Z2Z_S |
| 50644931U, // UMAX_VG2_2ZZ_B |
| 54872003U, // UMAX_VG2_2ZZ_D |
| 59099075U, // UMAX_VG2_2ZZ_H |
| 63326147U, // UMAX_VG2_2ZZ_S |
| 50644931U, // UMAX_VG4_4Z4Z_B |
| 54872003U, // UMAX_VG4_4Z4Z_D |
| 59099075U, // UMAX_VG4_4Z4Z_H |
| 63326147U, // UMAX_VG4_4Z4Z_S |
| 50644931U, // UMAX_VG4_4ZZ_B |
| 54872003U, // UMAX_VG4_4ZZ_D |
| 59099075U, // UMAX_VG4_4ZZ_H |
| 63326147U, // UMAX_VG4_4ZZ_S |
| 4278211U, // UMAX_ZI_B |
| 541181891U, // UMAX_ZI_D |
| 71452611U, // UMAX_ZI_H |
| 541247427U, // UMAX_ZI_S |
| 2151761859U, // UMAX_ZPmZ_B |
| 2151794627U, // UMAX_ZPmZ_D |
| 2713864131U, // UMAX_ZPmZ_H |
| 2151860163U, // UMAX_ZPmZ_S |
| 1615005590U, // UMAXv16i8 |
| 1615018067U, // UMAXv2i32 |
| 1615011691U, // UMAXv4i16 |
| 1615020301U, // UMAXv4i32 |
| 1615013627U, // UMAXv8i16 |
| 1615006519U, // UMAXv8i8 |
| 2151755676U, // UMINP_ZPmZ_B |
| 2151788444U, // UMINP_ZPmZ_D |
| 2713857948U, // UMINP_ZPmZ_H |
| 2151853980U, // UMINP_ZPmZ_S |
| 1615005261U, // UMINPv16i8 |
| 1615017651U, // UMINPv2i32 |
| 1615011186U, // UMINPv4i16 |
| 1615019730U, // UMINPv4i32 |
| 1615013082U, // UMINPv8i16 |
| 1615006231U, // UMINPv8i8 |
| 2181252669U, // UMINQV_VPZ_B |
| 2185446973U, // UMINQV_VPZ_D |
| 2189641277U, // UMINQV_VPZ_H |
| 2193835581U, // UMINQV_VPZ_S |
| 509424U, // UMINV_VPZ_B |
| 3301459440U, // UMINV_VPZ_D |
| 3305686512U, // UMINV_VPZ_H |
| 3246999024U, // UMINV_VPZ_S |
| 1614841697U, // UMINVv16i8v |
| 1614847784U, // UMINVv4i16v |
| 1614856328U, // UMINVv4i32v |
| 1614849680U, // UMINVv8i16v |
| 1614842640U, // UMINVv8i8v |
| 4238880U, // UMINWri |
| 4238880U, // UMINWrr |
| 4238880U, // UMINXri |
| 4238880U, // UMINXrr |
| 50638368U, // UMIN_VG2_2Z2Z_B |
| 54865440U, // UMIN_VG2_2Z2Z_D |
| 59092512U, // UMIN_VG2_2Z2Z_H |
| 63319584U, // UMIN_VG2_2Z2Z_S |
| 50638368U, // UMIN_VG2_2ZZ_B |
| 54865440U, // UMIN_VG2_2ZZ_D |
| 59092512U, // UMIN_VG2_2ZZ_H |
| 63319584U, // UMIN_VG2_2ZZ_S |
| 50638368U, // UMIN_VG4_4Z4Z_B |
| 54865440U, // UMIN_VG4_4Z4Z_D |
| 59092512U, // UMIN_VG4_4Z4Z_H |
| 63319584U, // UMIN_VG4_4Z4Z_S |
| 50638368U, // UMIN_VG4_4ZZ_B |
| 54865440U, // UMIN_VG4_4ZZ_D |
| 59092512U, // UMIN_VG4_4ZZ_H |
| 63319584U, // UMIN_VG4_4ZZ_S |
| 4271648U, // UMIN_ZI_B |
| 541175328U, // UMIN_ZI_D |
| 71446048U, // UMIN_ZI_H |
| 541240864U, // UMIN_ZI_S |
| 2151755296U, // UMIN_ZPmZ_B |
| 2151788064U, // UMIN_ZPmZ_D |
| 2713857568U, // UMIN_ZPmZ_H |
| 2151853600U, // UMIN_ZPmZ_S |
| 1615005221U, // UMINv16i8 |
| 1615017431U, // UMINv2i32 |
| 1615010955U, // UMINv4i16 |
| 1615019602U, // UMINv4i32 |
| 1615012964U, // UMINv8i16 |
| 1615006093U, // UMINv8i8 |
| 2688650315U, // UMLALB_ZZZI_D |
| 1078103115U, // UMLALB_ZZZI_S |
| 2688650315U, // UMLALB_ZZZ_D |
| 314707019U, // UMLALB_ZZZ_H |
| 1078103115U, // UMLALB_ZZZ_S |
| 3003591724U, // UMLALL_MZZI_BtoS |
| 3003558956U, // UMLALL_MZZI_HtoD |
| 3003591724U, // UMLALL_MZZ_BtoS |
| 3003558956U, // UMLALL_MZZ_HtoD |
| 3540462636U, // UMLALL_VG2_M2Z2Z_BtoS |
| 3540429868U, // UMLALL_VG2_M2Z2Z_HtoD |
| 3540462636U, // UMLALL_VG2_M2ZZI_BtoS |
| 3540429868U, // UMLALL_VG2_M2ZZI_HtoD |
| 856108076U, // UMLALL_VG2_M2ZZ_BtoS |
| 856075308U, // UMLALL_VG2_M2ZZ_HtoD |
| 4077333548U, // UMLALL_VG4_M4Z4Z_BtoS |
| 4077300780U, // UMLALL_VG4_M4Z4Z_HtoD |
| 4077333548U, // UMLALL_VG4_M4ZZI_BtoS |
| 4077300780U, // UMLALL_VG4_M4ZZI_HtoD |
| 1392978988U, // UMLALL_VG4_M4ZZ_BtoS |
| 1392946220U, // UMLALL_VG4_M4ZZ_HtoD |
| 2688664412U, // UMLALT_ZZZI_D |
| 1078117212U, // UMLALT_ZZZI_S |
| 2688664412U, // UMLALT_ZZZ_D |
| 314721116U, // UMLALT_ZZZ_H |
| 1078117212U, // UMLALT_ZZZ_S |
| 2781293201U, // UMLAL_MZZI_S |
| 2781293201U, // UMLAL_MZZ_S |
| 3318164113U, // UMLAL_VG2_M2Z2Z_S |
| 3318164113U, // UMLAL_VG2_M2ZZI_S |
| 3318164113U, // UMLAL_VG2_M2ZZ_S |
| 3855035025U, // UMLAL_VG4_M4Z4Z_S |
| 3855035025U, // UMLAL_VG4_M4ZZI_S |
| 3855035025U, // UMLAL_VG4_M4ZZ_S |
| 1615077358U, // UMLALv16i8_v8i16 |
| 1615074157U, // UMLALv2i32_indexed |
| 1615074157U, // UMLALv2i32_v2i64 |
| 1615084834U, // UMLALv4i16_indexed |
| 1615084834U, // UMLALv4i16_v4i32 |
| 1615073579U, // UMLALv4i32_indexed |
| 1615073579U, // UMLALv4i32_v2i64 |
| 1615083841U, // UMLALv8i16_indexed |
| 1615083841U, // UMLALv8i16_v4i32 |
| 1615078220U, // UMLALv8i8_v8i16 |
| 2688650613U, // UMLSLB_ZZZI_D |
| 1078103413U, // UMLSLB_ZZZI_S |
| 2688650613U, // UMLSLB_ZZZ_D |
| 314707317U, // UMLSLB_ZZZ_H |
| 1078103413U, // UMLSLB_ZZZ_S |
| 3003591740U, // UMLSLL_MZZI_BtoS |
| 3003558972U, // UMLSLL_MZZI_HtoD |
| 3003591740U, // UMLSLL_MZZ_BtoS |
| 3003558972U, // UMLSLL_MZZ_HtoD |
| 3540462652U, // UMLSLL_VG2_M2Z2Z_BtoS |
| 3540429884U, // UMLSLL_VG2_M2Z2Z_HtoD |
| 3540462652U, // UMLSLL_VG2_M2ZZI_BtoS |
| 3540429884U, // UMLSLL_VG2_M2ZZI_HtoD |
| 856108092U, // UMLSLL_VG2_M2ZZ_BtoS |
| 856075324U, // UMLSLL_VG2_M2ZZ_HtoD |
| 4077333564U, // UMLSLL_VG4_M4Z4Z_BtoS |
| 4077300796U, // UMLSLL_VG4_M4Z4Z_HtoD |
| 4077333564U, // UMLSLL_VG4_M4ZZI_BtoS |
| 4077300796U, // UMLSLL_VG4_M4ZZI_HtoD |
| 1392979004U, // UMLSLL_VG4_M4ZZ_BtoS |
| 1392946236U, // UMLSLL_VG4_M4ZZ_HtoD |
| 2688664587U, // UMLSLT_ZZZI_D |
| 1078117387U, // UMLSLT_ZZZI_S |
| 2688664587U, // UMLSLT_ZZZ_D |
| 314721291U, // UMLSLT_ZZZ_H |
| 1078117387U, // UMLSLT_ZZZ_S |
| 2781293883U, // UMLSL_MZZI_S |
| 2781293883U, // UMLSL_MZZ_S |
| 3318164795U, // UMLSL_VG2_M2Z2Z_S |
| 3318164795U, // UMLSL_VG2_M2ZZI_S |
| 3318164795U, // UMLSL_VG2_M2ZZ_S |
| 3855035707U, // UMLSL_VG4_M4Z4Z_S |
| 3855035707U, // UMLSL_VG4_M4ZZI_S |
| 3855035707U, // UMLSL_VG4_M4ZZ_S |
| 1615077501U, // UMLSLv16i8_v8i16 |
| 1615074381U, // UMLSLv2i32_indexed |
| 1615074381U, // UMLSLv2i32_v2i64 |
| 1615085058U, // UMLSLv4i16_indexed |
| 1615085058U, // UMLSLv4i16_v4i32 |
| 1615073737U, // UMLSLv4i32_indexed |
| 1615073737U, // UMLSLv4i32_v2i64 |
| 1615083999U, // UMLSLv8i16_indexed |
| 1615083999U, // UMLSLv8i16_v4i32 |
| 1615078430U, // UMLSLv8i8_v8i16 |
| 20171U, // UMMLA |
| 4358498U, // UMMLA_ZZZ |
| 100893089U, // UMOPA_MPPZZ_D |
| 100893089U, // UMOPA_MPPZZ_HtoS |
| 323191201U, // UMOPA_MPPZZ_S |
| 100909650U, // UMOPS_MPPZZ_D |
| 100909650U, // UMOPS_MPPZZ_HtoS |
| 323207762U, // UMOPS_MPPZZ_S |
| 1614846275U, // UMOVvi16 |
| 1614846275U, // UMOVvi16_idx0 |
| 1614852875U, // UMOVvi32 |
| 1614852875U, // UMOVvi32_idx0 |
| 1614843975U, // UMOVvi64 |
| 1614843975U, // UMOVvi64_idx0 |
| 1614840561U, // UMOVvi8 |
| 1614840561U, // UMOVvi8_idx0 |
| 4238252U, // UMSUBLrrr |
| 2151753886U, // UMULH_ZPmZ_B |
| 2151786654U, // UMULH_ZPmZ_D |
| 2713856158U, // UMULH_ZPmZ_H |
| 2151852190U, // UMULH_ZPmZ_S |
| 4270238U, // UMULH_ZZZ_B |
| 541173918U, // UMULH_ZZZ_D |
| 71444638U, // UMULH_ZZZ_H |
| 541239454U, // UMULH_ZZZ_S |
| 4237470U, // UMULHrr |
| 541166878U, // UMULLB_ZZZI_D |
| 3762457886U, // UMULLB_ZZZI_S |
| 541166878U, // UMULLB_ZZZ_D |
| 302124318U, // UMULLB_ZZZ_H |
| 3762457886U, // UMULLB_ZZZ_S |
| 541180890U, // UMULLT_ZZZI_D |
| 3762471898U, // UMULLT_ZZZI_S |
| 541180890U, // UMULLT_ZZZ_D |
| 302138330U, // UMULLT_ZZZ_H |
| 3762471898U, // UMULLT_ZZZ_S |
| 1615011943U, // UMULLv16i8_v8i16 |
| 1615008813U, // UMULLv2i32_indexed |
| 1615008813U, // UMULLv2i32_v2i64 |
| 1615019490U, // UMULLv4i16_indexed |
| 1615019490U, // UMULLv4i16_v4i32 |
| 1615008166U, // UMULLv4i32_indexed |
| 1615008166U, // UMULLv4i32_v2i64 |
| 1615018428U, // UMULLv8i16_indexed |
| 1615018428U, // UMULLv8i16_v4i32 |
| 1615012874U, // UMULLv8i8_v8i16 |
| 4265860U, // UQADD_ZI_B |
| 541169540U, // UQADD_ZI_D |
| 71440260U, // UQADD_ZI_H |
| 541235076U, // UQADD_ZI_S |
| 2151749508U, // UQADD_ZPmZ_B |
| 2151782276U, // UQADD_ZPmZ_D |
| 2713851780U, // UQADD_ZPmZ_H |
| 2151847812U, // UQADD_ZPmZ_S |
| 4265860U, // UQADD_ZZZ_B |
| 541169540U, // UQADD_ZZZ_D |
| 71440260U, // UQADD_ZZZ_H |
| 541235076U, // UQADD_ZZZ_S |
| 1615004986U, // UQADDv16i8 |
| 4233092U, // UQADDv1i16 |
| 4233092U, // UQADDv1i32 |
| 4233092U, // UQADDv1i64 |
| 4233092U, // UQADDv1i8 |
| 1615017039U, // UQADDv2i32 |
| 1615008420U, // UQADDv2i64 |
| 1615010586U, // UQADDv4i16 |
| 1615019005U, // UQADDv4i32 |
| 1615012447U, // UQADDv8i16 |
| 1615005877U, // UQADDv8i8 |
| 3284282998U, // UQCVTN_Z2Z_StoH |
| 3275894390U, // UQCVTN_Z4Z_DtoH |
| 1614884470U, // UQCVTN_Z4Z_StoB |
| 3284288789U, // UQCVT_Z2Z_StoH |
| 3275900181U, // UQCVT_Z4Z_DtoH |
| 1614890261U, // UQCVT_Z4Z_StoB |
| 541100999U, // UQDECB_WPiI |
| 541100999U, // UQDECB_XPiI |
| 541103897U, // UQDECD_WPiI |
| 541103897U, // UQDECD_XPiI |
| 541169433U, // UQDECD_ZPiI |
| 541108140U, // UQDECH_WPiI |
| 541108140U, // UQDECH_XPiI |
| 104998828U, // UQDECH_ZPiI |
| 4239108U, // UQDECP_WP_B |
| 541110020U, // UQDECP_WP_D |
| 3762335492U, // UQDECP_WP_H |
| 541110020U, // UQDECP_WP_S |
| 4239108U, // UQDECP_XP_B |
| 541110020U, // UQDECP_XP_D |
| 3762335492U, // UQDECP_XP_H |
| 541110020U, // UQDECP_XP_S |
| 2151788292U, // UQDECP_ZP_D |
| 3305254660U, // UQDECP_ZP_H |
| 2688724740U, // UQDECP_ZP_S |
| 541116136U, // UQDECW_WPiI |
| 541116136U, // UQDECW_XPiI |
| 541247208U, // UQDECW_ZPiI |
| 541101015U, // UQINCB_WPiI |
| 541101015U, // UQINCB_XPiI |
| 541103913U, // UQINCD_WPiI |
| 541103913U, // UQINCD_XPiI |
| 541169449U, // UQINCD_ZPiI |
| 541108156U, // UQINCH_WPiI |
| 541108156U, // UQINCH_XPiI |
| 104998844U, // UQINCH_ZPiI |
| 4239124U, // UQINCP_WP_B |
| 541110036U, // UQINCP_WP_D |
| 3762335508U, // UQINCP_WP_H |
| 541110036U, // UQINCP_WP_S |
| 4239124U, // UQINCP_XP_B |
| 541110036U, // UQINCP_XP_D |
| 3762335508U, // UQINCP_XP_H |
| 541110036U, // UQINCP_XP_S |
| 2151788308U, // UQINCP_ZP_D |
| 3305254676U, // UQINCP_ZP_H |
| 2688724756U, // UQINCP_ZP_S |
| 541116152U, // UQINCW_WPiI |
| 541116152U, // UQINCW_XPiI |
| 541247224U, // UQINCW_ZPiI |
| 2151756218U, // UQRSHLR_ZPmZ_B |
| 2151788986U, // UQRSHLR_ZPmZ_D |
| 2713858490U, // UQRSHLR_ZPmZ_H |
| 2151854522U, // UQRSHLR_ZPmZ_S |
| 2151754752U, // UQRSHL_ZPmZ_B |
| 2151787520U, // UQRSHL_ZPmZ_D |
| 2713857024U, // UQRSHL_ZPmZ_H |
| 2151853056U, // UQRSHL_ZPmZ_S |
| 1615005138U, // UQRSHLv16i8 |
| 4238336U, // UQRSHLv1i16 |
| 4238336U, // UQRSHLv1i32 |
| 4238336U, // UQRSHLv1i64 |
| 4238336U, // UQRSHLv1i8 |
| 1615017300U, // UQRSHLv2i32 |
| 1615008722U, // UQRSHLv2i64 |
| 1615010824U, // UQRSHLv4i16 |
| 1615019399U, // UQRSHLv4i32 |
| 1615012785U, // UQRSHLv8i16 |
| 1615005996U, // UQRSHLv8i8 |
| 3762359775U, // UQRSHRNB_ZZI_B |
| 21106143U, // UQRSHRNB_ZZI_H |
| 541232607U, // UQRSHRNB_ZZI_S |
| 1078019160U, // UQRSHRNT_ZZI_B |
| 25314392U, // UQRSHRNT_ZZI_H |
| 2151859288U, // UQRSHRNT_ZZI_S |
| 1614884432U, // UQRSHRN_VG4_Z4ZI_B |
| 54668880U, // UQRSHRN_VG4_Z4ZI_H |
| 4238928U, // UQRSHRNb |
| 4238928U, // UQRSHRNh |
| 4238928U, // UQRSHRNs |
| 1615070154U, // UQRSHRNv16i8_shift |
| 1615017474U, // UQRSHRNv2i32_shift |
| 1615010998U, // UQRSHRNv4i16_shift |
| 1615084071U, // UQRSHRNv4i32_shift |
| 1615077573U, // UQRSHRNv8i16_shift |
| 1615006136U, // UQRSHRNv8i8_shift |
| 63058274U, // UQRSHR_VG2_Z2ZI_H |
| 1614885218U, // UQRSHR_VG4_Z4ZI_B |
| 54669666U, // UQRSHR_VG4_Z4ZI_H |
| 2151756201U, // UQSHLR_ZPmZ_B |
| 2151788969U, // UQSHLR_ZPmZ_D |
| 2713858473U, // UQSHLR_ZPmZ_H |
| 2151854505U, // UQSHLR_ZPmZ_S |
| 2151754737U, // UQSHL_ZPmI_B |
| 2151787505U, // UQSHL_ZPmI_D |
| 2713857009U, // UQSHL_ZPmI_H |
| 2151853041U, // UQSHL_ZPmI_S |
| 2151754737U, // UQSHL_ZPmZ_B |
| 2151787505U, // UQSHL_ZPmZ_D |
| 2713857009U, // UQSHL_ZPmZ_H |
| 2151853041U, // UQSHL_ZPmZ_S |
| 4238321U, // UQSHLb |
| 4238321U, // UQSHLd |
| 4238321U, // UQSHLh |
| 4238321U, // UQSHLs |
| 1615005115U, // UQSHLv16i8 |
| 1615005115U, // UQSHLv16i8_shift |
| 4238321U, // UQSHLv1i16 |
| 4238321U, // UQSHLv1i32 |
| 4238321U, // UQSHLv1i64 |
| 4238321U, // UQSHLv1i8 |
| 1615017279U, // UQSHLv2i32 |
| 1615017279U, // UQSHLv2i32_shift |
| 1615008701U, // UQSHLv2i64 |
| 1615008701U, // UQSHLv2i64_shift |
| 1615010803U, // UQSHLv4i16 |
| 1615010803U, // UQSHLv4i16_shift |
| 1615019378U, // UQSHLv4i32 |
| 1615019378U, // UQSHLv4i32_shift |
| 1615012764U, // UQSHLv8i16 |
| 1615012764U, // UQSHLv8i16_shift |
| 1615005975U, // UQSHLv8i8 |
| 1615005975U, // UQSHLv8i8_shift |
| 3762359756U, // UQSHRNB_ZZI_B |
| 21106124U, // UQSHRNB_ZZI_H |
| 541232588U, // UQSHRNB_ZZI_S |
| 1078019141U, // UQSHRNT_ZZI_B |
| 25314373U, // UQSHRNT_ZZI_H |
| 2151859269U, // UQSHRNT_ZZI_S |
| 4238911U, // UQSHRNb |
| 4238911U, // UQSHRNh |
| 4238911U, // UQSHRNs |
| 1615070127U, // UQSHRNv16i8_shift |
| 1615017451U, // UQSHRNv2i32_shift |
| 1615010975U, // UQSHRNv4i16_shift |
| 1615084046U, // UQSHRNv4i32_shift |
| 1615077548U, // UQSHRNv8i16_shift |
| 1615006113U, // UQSHRNv8i8_shift |
| 2151756090U, // UQSUBR_ZPmZ_B |
| 2151788858U, // UQSUBR_ZPmZ_D |
| 2713858362U, // UQSUBR_ZPmZ_H |
| 2151854394U, // UQSUBR_ZPmZ_S |
| 4263826U, // UQSUB_ZI_B |
| 541167506U, // UQSUB_ZI_D |
| 71438226U, // UQSUB_ZI_H |
| 541233042U, // UQSUB_ZI_S |
| 2151747474U, // UQSUB_ZPmZ_B |
| 2151780242U, // UQSUB_ZPmZ_D |
| 2713849746U, // UQSUB_ZPmZ_H |
| 2151845778U, // UQSUB_ZPmZ_S |
| 4263826U, // UQSUB_ZZZ_B |
| 541167506U, // UQSUB_ZZZ_D |
| 71438226U, // UQSUB_ZZZ_H |
| 541233042U, // UQSUB_ZZZ_S |
| 1615004864U, // UQSUBv16i8 |
| 4231058U, // UQSUBv1i16 |
| 4231058U, // UQSUBv1i32 |
| 4231058U, // UQSUBv1i64 |
| 4231058U, // UQSUBv1i8 |
| 1615016921U, // UQSUBv2i32 |
| 1615008370U, // UQSUBv2i64 |
| 1615010468U, // UQSUBv4i16 |
| 1615018877U, // UQSUBv4i32 |
| 1615012329U, // UQSUBv8i16 |
| 1615005787U, // UQSUBv8i8 |
| 3762359793U, // UQXTNB_ZZ_B |
| 3242331633U, // UQXTNB_ZZ_H |
| 541232625U, // UQXTNB_ZZ_S |
| 1078019187U, // UQXTNT_ZZ_B |
| 3246539891U, // UQXTNT_ZZ_H |
| 2151859315U, // UQXTNT_ZZ_S |
| 1615070190U, // UQXTNv16i8 |
| 4238981U, // UQXTNv1i16 |
| 4238981U, // UQXTNv1i32 |
| 4238981U, // UQXTNv1i8 |
| 1615017507U, // UQXTNv2i32 |
| 1615011042U, // UQXTNv4i16 |
| 1615084104U, // UQXTNv4i32 |
| 1615077618U, // UQXTNv8i16 |
| 1615006166U, // UQXTNv8i8 |
| 541235248U, // URECPE_ZPmZ_S |
| 1615017090U, // URECPEv2i32 |
| 1615019065U, // URECPEv4i32 |
| 2151749462U, // URHADD_ZPmZ_B |
| 2151782230U, // URHADD_ZPmZ_D |
| 2713851734U, // URHADD_ZPmZ_H |
| 2151847766U, // URHADD_ZPmZ_S |
| 1615004939U, // URHADDv16i8 |
| 1615016996U, // URHADDv2i32 |
| 1615010543U, // URHADDv4i16 |
| 1615018962U, // URHADDv4i32 |
| 1615012404U, // URHADDv8i16 |
| 1615005834U, // URHADDv8i8 |
| 2151756235U, // URSHLR_ZPmZ_B |
| 2151789003U, // URSHLR_ZPmZ_D |
| 2713858507U, // URSHLR_ZPmZ_H |
| 2151854539U, // URSHLR_ZPmZ_S |
| 50637839U, // URSHL_VG2_2Z2Z_B |
| 54864911U, // URSHL_VG2_2Z2Z_D |
| 59091983U, // URSHL_VG2_2Z2Z_H |
| 63319055U, // URSHL_VG2_2Z2Z_S |
| 50637839U, // URSHL_VG2_2ZZ_B |
| 54864911U, // URSHL_VG2_2ZZ_D |
| 59091983U, // URSHL_VG2_2ZZ_H |
| 63319055U, // URSHL_VG2_2ZZ_S |
| 50637839U, // URSHL_VG4_4Z4Z_B |
| 54864911U, // URSHL_VG4_4Z4Z_D |
| 59091983U, // URSHL_VG4_4Z4Z_H |
| 63319055U, // URSHL_VG4_4Z4Z_S |
| 50637839U, // URSHL_VG4_4ZZ_B |
| 54864911U, // URSHL_VG4_4ZZ_D |
| 59091983U, // URSHL_VG4_4ZZ_H |
| 63319055U, // URSHL_VG4_4ZZ_S |
| 2151754767U, // URSHL_ZPmZ_B |
| 2151787535U, // URSHL_ZPmZ_D |
| 2713857039U, // URSHL_ZPmZ_H |
| 2151853071U, // URSHL_ZPmZ_S |
| 1615005161U, // URSHLv16i8 |
| 4238351U, // URSHLv1i64 |
| 1615017321U, // URSHLv2i32 |
| 1615008743U, // URSHLv2i64 |
| 1615010845U, // URSHLv4i16 |
| 1615019420U, // URSHLv4i32 |
| 1615012806U, // URSHLv8i16 |
| 1615006017U, // URSHLv8i8 |
| 2151756145U, // URSHR_ZPmI_B |
| 2151788913U, // URSHR_ZPmI_D |
| 2713858417U, // URSHR_ZPmI_H |
| 2151854449U, // URSHR_ZPmI_S |
| 4239729U, // URSHRd |
| 1615005324U, // URSHRv16i8_shift |
| 1615017730U, // URSHRv2i32_shift |
| 1615009062U, // URSHRv2i64_shift |
| 1615011265U, // URSHRv4i16_shift |
| 1615019809U, // URSHRv4i32_shift |
| 1615013161U, // URSHRv8i16_shift |
| 1615006288U, // URSHRv8i8_shift |
| 541235294U, // URSQRTE_ZPmZ_S |
| 1615017113U, // URSQRTEv2i32 |
| 1615019088U, // URSQRTEv4i32 |
| 4260434U, // URSRA_ZZI_B |
| 2151776850U, // URSRA_ZZI_D |
| 84017746U, // URSRA_ZZI_H |
| 2688713298U, // URSRA_ZZI_S |
| 1615430226U, // URSRAd |
| 1615070336U, // URSRAv16i8_shift |
| 1615082379U, // URSRAv2i32_shift |
| 1615073848U, // URSRAv2i64_shift |
| 1615075926U, // URSRAv4i16_shift |
| 1615084311U, // URSRAv4i32_shift |
| 1615077787U, // URSRAv8i16_shift |
| 1615071265U, // URSRAv8i8_shift |
| 3288810671U, // USDOT_VG2_M2Z2Z_BToS |
| 3288810671U, // USDOT_VG2_M2ZZI_BToS |
| 3288810671U, // USDOT_VG2_M2ZZ_BToS |
| 3825681583U, // USDOT_VG4_M4Z4Z_BToS |
| 3825681583U, // USDOT_VG4_M4ZZI_BToS |
| 3825681583U, // USDOT_VG4_M4ZZ_BToS |
| 4375727U, // USDOT_ZZZ |
| 4375727U, // USDOT_ZZZI |
| 1615086767U, // USDOTlanev16i8 |
| 1615086767U, // USDOTlanev8i8 |
| 20296U, // USDOTv16i8 |
| 20296U, // USDOTv8i8 |
| 541166844U, // USHLLB_ZZI_D |
| 302124284U, // USHLLB_ZZI_H |
| 3762457852U, // USHLLB_ZZI_S |
| 541180856U, // USHLLT_ZZI_D |
| 302138296U, // USHLLT_ZZI_H |
| 3762471864U, // USHLLT_ZZI_S |
| 1615011910U, // USHLLv16i8_shift |
| 1615008781U, // USHLLv2i32_shift |
| 1615019458U, // USHLLv4i16_shift |
| 1615008131U, // USHLLv4i32_shift |
| 1615018393U, // USHLLv8i16_shift |
| 1615012844U, // USHLLv8i8_shift |
| 1615005182U, // USHLv16i8 |
| 4238364U, // USHLv1i64 |
| 1615017340U, // USHLv2i32 |
| 1615008762U, // USHLv2i64 |
| 1615010864U, // USHLv4i16 |
| 1615019439U, // USHLv4i32 |
| 1615012825U, // USHLv8i16 |
| 1615006036U, // USHLv8i8 |
| 4239742U, // USHRd |
| 1615005345U, // USHRv16i8_shift |
| 1615017749U, // USHRv2i32_shift |
| 1615009081U, // USHRv2i64_shift |
| 1615011284U, // USHRv4i16_shift |
| 1615019828U, // USHRv4i32_shift |
| 1615013180U, // USHRv8i16_shift |
| 1615006307U, // USHRv8i8_shift |
| 3003591714U, // USMLALL_MZZI_BtoS |
| 3003591714U, // USMLALL_MZZ_BtoS |
| 3540462626U, // USMLALL_VG2_M2Z2Z_BtoS |
| 3540462626U, // USMLALL_VG2_M2ZZI_BtoS |
| 856108066U, // USMLALL_VG2_M2ZZ_BtoS |
| 4077333538U, // USMLALL_VG4_M4Z4Z_BtoS |
| 4077333538U, // USMLALL_VG4_M4ZZI_BtoS |
| 1392978978U, // USMLALL_VG4_M4ZZ_BtoS |
| 20164U, // USMMLA |
| 4358490U, // USMMLA_ZZZ |
| 100893080U, // USMOPA_MPPZZ_D |
| 323191192U, // USMOPA_MPPZZ_S |
| 100909641U, // USMOPS_MPPZZ_D |
| 323207753U, // USMOPS_MPPZZ_S |
| 2151749499U, // USQADD_ZPmZ_B |
| 2151782267U, // USQADD_ZPmZ_D |
| 2713851771U, // USQADD_ZPmZ_H |
| 2151847803U, // USQADD_ZPmZ_S |
| 1615070509U, // USQADDv16i8 |
| 1615435643U, // USQADDv1i16 |
| 1615435643U, // USQADDv1i32 |
| 1615435643U, // USQADDv1i64 |
| 1615435643U, // USQADDv1i8 |
| 1615082563U, // USQADDv2i32 |
| 1615073944U, // USQADDv2i64 |
| 1615076110U, // USQADDv4i16 |
| 1615084529U, // USQADDv4i32 |
| 1615077971U, // USQADDv8i16 |
| 1615071401U, // USQADDv8i8 |
| 4260447U, // USRA_ZZI_B |
| 2151776863U, // USRA_ZZI_D |
| 84017759U, // USRA_ZZI_H |
| 2688713311U, // USRA_ZZI_S |
| 1615430239U, // USRAd |
| 1615070357U, // USRAv16i8_shift |
| 1615082398U, // USRAv2i32_shift |
| 1615073867U, // USRAv2i64_shift |
| 1615075945U, // USRAv4i16_shift |
| 1615084330U, // USRAv4i32_shift |
| 1615077806U, // USRAv8i16_shift |
| 1615071284U, // USRAv8i8_shift |
| 541166773U, // USUBLB_ZZZ_D |
| 302124213U, // USUBLB_ZZZ_H |
| 3762457781U, // USUBLB_ZZZ_S |
| 541180780U, // USUBLT_ZZZ_D |
| 302138220U, // USUBLT_ZZZ_H |
| 3762471788U, // USUBLT_ZZZ_S |
| 1615011844U, // USUBLv16i8_v8i16 |
| 1615008641U, // USUBLv2i32_v2i64 |
| 1615019318U, // USUBLv4i16_v4i32 |
| 1615008065U, // USUBLv4i32_v2i64 |
| 1615018327U, // USUBLv8i16_v4i32 |
| 1615012704U, // USUBLv8i8_v8i16 |
| 541167527U, // USUBWB_ZZZ_D |
| 71438247U, // USUBWB_ZZZ_H |
| 541233063U, // USUBWB_ZZZ_S |
| 541181226U, // USUBWT_ZZZ_D |
| 71451946U, // USUBWT_ZZZ_H |
| 541246762U, // USUBWT_ZZZ_S |
| 1615012161U, // USUBWv16i8_v8i16 |
| 1615009349U, // USUBWv2i32_v2i64 |
| 1615020227U, // USUBWv4i16_v4i32 |
| 1615008250U, // USUBWv4i32_v2i64 |
| 1615018647U, // USUBWv8i16_v4i32 |
| 1615013579U, // USUBWv8i8_v8i16 |
| 3825681605U, // USVDOT_VG4_M4ZZI_BToS |
| 541174308U, // UUNPKHI_ZZ_D |
| 3523357220U, // UUNPKHI_ZZ_H |
| 3762465316U, // UUNPKHI_ZZ_S |
| 541175513U, // UUNPKLO_ZZ_D |
| 3523358425U, // UUNPKLO_ZZ_H |
| 3762466521U, // UUNPKLO_ZZ_S |
| 3242535518U, // UUNPK_VG2_2ZZ_D |
| 3523586654U, // UUNPK_VG2_2ZZ_H |
| 3292932702U, // UUNPK_VG2_2ZZ_S |
| 3284478558U, // UUNPK_VG4_4Z2Z_D |
| 3271928414U, // UUNPK_VG4_4Z2Z_H |
| 3280349790U, // UUNPK_VG4_4Z2Z_S |
| 3288810702U, // UVDOT_VG2_M2ZZI_HtoS |
| 3825681614U, // UVDOT_VG4_M4ZZI_BtoS |
| 3825648846U, // UVDOT_VG4_M4ZZI_HtoD |
| 541167457U, // UXTB_ZPmZ_D |
| 1082265441U, // UXTB_ZPmZ_H |
| 541232993U, // UXTB_ZPmZ_S |
| 541174244U, // UXTH_ZPmZ_D |
| 541239780U, // UXTH_ZPmZ_S |
| 541181828U, // UXTW_ZPmZ_D |
| 4259880U, // UZP1_PPP_B |
| 541163560U, // UZP1_PPP_D |
| 71434280U, // UZP1_PPP_H |
| 541229096U, // UZP1_PPP_S |
| 4259880U, // UZP1_ZZZ_B |
| 541163560U, // UZP1_ZZZ_D |
| 71434280U, // UZP1_ZZZ_H |
| 118390824U, // UZP1_ZZZ_Q |
| 541229096U, // UZP1_ZZZ_S |
| 1615004531U, // UZP1v16i8 |
| 1615016750U, // UZP1v2i32 |
| 1615007952U, // UZP1v2i64 |
| 1615010287U, // UZP1v4i16 |
| 1615018186U, // UZP1v4i32 |
| 1615011770U, // UZP1v8i16 |
| 1615005627U, // UZP1v8i8 |
| 4259990U, // UZP2_PPP_B |
| 541163670U, // UZP2_PPP_D |
| 71434390U, // UZP2_PPP_H |
| 541229206U, // UZP2_PPP_S |
| 4259990U, // UZP2_ZZZ_B |
| 541163670U, // UZP2_ZZZ_D |
| 71434390U, // UZP2_ZZZ_H |
| 118390934U, // UZP2_ZZZ_Q |
| 541229206U, // UZP2_ZZZ_S |
| 1615004718U, // UZP2v16i8 |
| 1615016777U, // UZP2v2i32 |
| 1615008230U, // UZP2v2i64 |
| 1615010324U, // UZP2v4i16 |
| 1615018627U, // UZP2v4i32 |
| 1615012141U, // UZP2v8i16 |
| 1615005664U, // UZP2v8i8 |
| 4259893U, // UZPQ1_ZZZ_B |
| 541163573U, // UZPQ1_ZZZ_D |
| 71434293U, // UZPQ1_ZZZ_H |
| 541229109U, // UZPQ1_ZZZ_S |
| 4260003U, // UZPQ2_ZZZ_B |
| 541163683U, // UZPQ2_ZZZ_D |
| 71434403U, // UZPQ2_ZZZ_H |
| 541229219U, // UZPQ2_ZZZ_S |
| 302297208U, // UZP_VG2_2ZZZ_B |
| 306524280U, // UZP_VG2_2ZZZ_D |
| 71676024U, // UZP_VG2_2ZZZ_H |
| 118435960U, // UZP_VG2_2ZZZ_Q |
| 21377144U, // UZP_VG2_2ZZZ_S |
| 3271864440U, // UZP_VG4_4Z4Z_B |
| 3276091512U, // UZP_VG4_4Z4Z_D |
| 3280318584U, // UZP_VG4_4Z4Z_H |
| 340734072U, // UZP_VG4_4Z4Z_Q |
| 3284545656U, // UZP_VG4_4Z4Z_S |
| 49885U, // WFET |
| 49963U, // WFIT |
| 113547227U, // WHILEGE_2PXX_B |
| 113579995U, // WHILEGE_2PXX_D |
| 113612763U, // WHILEGE_2PXX_H |
| 113645531U, // WHILEGE_2PXX_S |
| 6494171U, // WHILEGE_CXX_B |
| 6526939U, // WHILEGE_CXX_D |
| 6559707U, // WHILEGE_CXX_H |
| 6592475U, // WHILEGE_CXX_S |
| 4265947U, // WHILEGE_PWW_B |
| 4298715U, // WHILEGE_PWW_D |
| 113383387U, // WHILEGE_PWW_H |
| 4364251U, // WHILEGE_PWW_S |
| 4265947U, // WHILEGE_PXX_B |
| 4298715U, // WHILEGE_PXX_D |
| 113383387U, // WHILEGE_PXX_H |
| 4364251U, // WHILEGE_PXX_S |
| 113558279U, // WHILEGT_2PXX_B |
| 113591047U, // WHILEGT_2PXX_D |
| 113623815U, // WHILEGT_2PXX_H |
| 113656583U, // WHILEGT_2PXX_S |
| 6505223U, // WHILEGT_CXX_B |
| 6537991U, // WHILEGT_CXX_D |
| 6570759U, // WHILEGT_CXX_H |
| 6603527U, // WHILEGT_CXX_S |
| 4276999U, // WHILEGT_PWW_B |
| 4309767U, // WHILEGT_PWW_D |
| 113394439U, // WHILEGT_PWW_H |
| 4375303U, // WHILEGT_PWW_S |
| 4276999U, // WHILEGT_PXX_B |
| 4309767U, // WHILEGT_PXX_D |
| 113394439U, // WHILEGT_PXX_H |
| 4375303U, // WHILEGT_PXX_S |
| 113551881U, // WHILEHI_2PXX_B |
| 113584649U, // WHILEHI_2PXX_D |
| 113617417U, // WHILEHI_2PXX_H |
| 113650185U, // WHILEHI_2PXX_S |
| 6498825U, // WHILEHI_CXX_B |
| 6531593U, // WHILEHI_CXX_D |
| 6564361U, // WHILEHI_CXX_H |
| 6597129U, // WHILEHI_CXX_S |
| 4270601U, // WHILEHI_PWW_B |
| 4303369U, // WHILEHI_PWW_D |
| 113388041U, // WHILEHI_PWW_H |
| 4368905U, // WHILEHI_PWW_S |
| 4270601U, // WHILEHI_PXX_B |
| 4303369U, // WHILEHI_PXX_D |
| 113388041U, // WHILEHI_PXX_H |
| 4368905U, // WHILEHI_PXX_S |
| 113557973U, // WHILEHS_2PXX_B |
| 113590741U, // WHILEHS_2PXX_D |
| 113623509U, // WHILEHS_2PXX_H |
| 113656277U, // WHILEHS_2PXX_S |
| 6504917U, // WHILEHS_CXX_B |
| 6537685U, // WHILEHS_CXX_D |
| 6570453U, // WHILEHS_CXX_H |
| 6603221U, // WHILEHS_CXX_S |
| 4276693U, // WHILEHS_PWW_B |
| 4309461U, // WHILEHS_PWW_D |
| 113394133U, // WHILEHS_PWW_H |
| 4374997U, // WHILEHS_PWW_S |
| 4276693U, // WHILEHS_PXX_B |
| 4309461U, // WHILEHS_PXX_D |
| 113394133U, // WHILEHS_PXX_H |
| 4374997U, // WHILEHS_PXX_S |
| 113547258U, // WHILELE_2PXX_B |
| 113580026U, // WHILELE_2PXX_D |
| 113612794U, // WHILELE_2PXX_H |
| 113645562U, // WHILELE_2PXX_S |
| 6494202U, // WHILELE_CXX_B |
| 6526970U, // WHILELE_CXX_D |
| 6559738U, // WHILELE_CXX_H |
| 6592506U, // WHILELE_CXX_S |
| 4265978U, // WHILELE_PWW_B |
| 4298746U, // WHILELE_PWW_D |
| 113383418U, // WHILELE_PWW_H |
| 4364282U, // WHILELE_PWW_S |
| 4265978U, // WHILELE_PXX_B |
| 4298746U, // WHILELE_PXX_D |
| 113383418U, // WHILELE_PXX_H |
| 4364282U, // WHILELE_PXX_S |
| 113553086U, // WHILELO_2PXX_B |
| 113585854U, // WHILELO_2PXX_D |
| 113618622U, // WHILELO_2PXX_H |
| 113651390U, // WHILELO_2PXX_S |
| 6500030U, // WHILELO_CXX_B |
| 6532798U, // WHILELO_CXX_D |
| 6565566U, // WHILELO_CXX_H |
| 6598334U, // WHILELO_CXX_S |
| 4271806U, // WHILELO_PWW_B |
| 4304574U, // WHILELO_PWW_D |
| 113389246U, // WHILELO_PWW_H |
| 4370110U, // WHILELO_PWW_S |
| 4271806U, // WHILELO_PXX_B |
| 4304574U, // WHILELO_PXX_D |
| 113389246U, // WHILELO_PXX_H |
| 4370110U, // WHILELO_PXX_S |
| 113558000U, // WHILELS_2PXX_B |
| 113590768U, // WHILELS_2PXX_D |
| 113623536U, // WHILELS_2PXX_H |
| 113656304U, // WHILELS_2PXX_S |
| 6504944U, // WHILELS_CXX_B |
| 6537712U, // WHILELS_CXX_D |
| 6570480U, // WHILELS_CXX_H |
| 6603248U, // WHILELS_CXX_S |
| 4276720U, // WHILELS_PWW_B |
| 4309488U, // WHILELS_PWW_D |
| 113394160U, // WHILELS_PWW_H |
| 4375024U, // WHILELS_PWW_S |
| 4276720U, // WHILELS_PXX_B |
| 4309488U, // WHILELS_PXX_D |
| 113394160U, // WHILELS_PXX_H |
| 4375024U, // WHILELS_PXX_S |
| 113558434U, // WHILELT_2PXX_B |
| 113591202U, // WHILELT_2PXX_D |
| 113623970U, // WHILELT_2PXX_H |
| 113656738U, // WHILELT_2PXX_S |
| 6505378U, // WHILELT_CXX_B |
| 6538146U, // WHILELT_CXX_D |
| 6570914U, // WHILELT_CXX_H |
| 6603682U, // WHILELT_CXX_S |
| 4277154U, // WHILELT_PWW_B |
| 4309922U, // WHILELT_PWW_D |
| 113394594U, // WHILELT_PWW_H |
| 4375458U, // WHILELT_PWW_S |
| 4277154U, // WHILELT_PXX_B |
| 4309922U, // WHILELT_PXX_D |
| 113394594U, // WHILELT_PXX_H |
| 4375458U, // WHILELT_PXX_S |
| 4278045U, // WHILERW_PXX_B |
| 4310813U, // WHILERW_PXX_D |
| 113395485U, // WHILERW_PXX_H |
| 4376349U, // WHILERW_PXX_S |
| 4272753U, // WHILEWR_PXX_B |
| 4305521U, // WHILEWR_PXX_D |
| 113390193U, // WHILEWR_PXX_H |
| 4371057U, // WHILEWR_PXX_S |
| 78163U, // WRFFR |
| 20200U, // XAFLAG |
| 1615009044U, // XAR |
| 4272406U, // XAR_ZZZI_B |
| 541176086U, // XAR_ZZZI_D |
| 71446806U, // XAR_ZZZI_H |
| 541241622U, // XAR_ZZZI_S |
| 38666U, // XPACD |
| 43522U, // XPACI |
| 18832U, // XPACLRI |
| 1615070180U, // XTNv16i8 |
| 1615017499U, // XTNv2i32 |
| 1615011034U, // XTNv4i16 |
| 1615084095U, // XTNv4i32 |
| 1615077609U, // XTNv8i16 |
| 1615006158U, // XTNv8i8 |
| 2535145U, // ZERO_M |
| 2781261545U, // ZERO_MXI_2Z |
| 3003559657U, // ZERO_MXI_4Z |
| 96906985U, // ZERO_MXI_VG2_2Z |
| 319205097U, // ZERO_MXI_VG2_4Z |
| 67546857U, // ZERO_MXI_VG2_Z |
| 633777897U, // ZERO_MXI_VG4_2Z |
| 856076009U, // ZERO_MXI_VG4_4Z |
| 604417769U, // ZERO_MXI_VG4_Z |
| 343984272U, // ZERO_T |
| 4259874U, // ZIP1_PPP_B |
| 541163554U, // ZIP1_PPP_D |
| 71434274U, // ZIP1_PPP_H |
| 541229090U, // ZIP1_PPP_S |
| 4259874U, // ZIP1_ZZZ_B |
| 541163554U, // ZIP1_ZZZ_D |
| 71434274U, // ZIP1_ZZZ_H |
| 118390818U, // ZIP1_ZZZ_Q |
| 541229090U, // ZIP1_ZZZ_S |
| 1615004521U, // ZIP1v16i8 |
| 1615016741U, // ZIP1v2i32 |
| 1615007943U, // ZIP1v2i64 |
| 1615010278U, // ZIP1v4i16 |
| 1615018177U, // ZIP1v4i32 |
| 1615011761U, // ZIP1v8i16 |
| 1615005618U, // ZIP1v8i8 |
| 4259984U, // ZIP2_PPP_B |
| 541163664U, // ZIP2_PPP_D |
| 71434384U, // ZIP2_PPP_H |
| 541229200U, // ZIP2_PPP_S |
| 4259984U, // ZIP2_ZZZ_B |
| 541163664U, // ZIP2_ZZZ_D |
| 71434384U, // ZIP2_ZZZ_H |
| 118390928U, // ZIP2_ZZZ_Q |
| 541229200U, // ZIP2_ZZZ_S |
| 1615004708U, // ZIP2v16i8 |
| 1615016768U, // ZIP2v2i32 |
| 1615008221U, // ZIP2v2i64 |
| 1615010315U, // ZIP2v4i16 |
| 1615018618U, // ZIP2v4i32 |
| 1615012132U, // ZIP2v8i16 |
| 1615005655U, // ZIP2v8i8 |
| 4259886U, // ZIPQ1_ZZZ_B |
| 541163566U, // ZIPQ1_ZZZ_D |
| 71434286U, // ZIPQ1_ZZZ_H |
| 541229102U, // ZIPQ1_ZZZ_S |
| 4259996U, // ZIPQ2_ZZZ_B |
| 541163676U, // ZIPQ2_ZZZ_D |
| 71434396U, // ZIPQ2_ZZZ_H |
| 541229212U, // ZIPQ2_ZZZ_S |
| 302296884U, // ZIP_VG2_2ZZZ_B |
| 306523956U, // ZIP_VG2_2ZZZ_D |
| 71675700U, // ZIP_VG2_2ZZZ_H |
| 118435636U, // ZIP_VG2_2ZZZ_Q |
| 21376820U, // ZIP_VG2_2ZZZ_S |
| 3271864116U, // ZIP_VG4_4Z4Z_B |
| 3276091188U, // ZIP_VG4_4Z4Z_D |
| 3280318260U, // ZIP_VG4_4Z4Z_H |
| 340733748U, // ZIP_VG4_4Z4Z_Q |
| 3284545332U, // ZIP_VG4_4Z4Z_S |
| 63057488U, // anonymous_15148 |
| 63057557U, // anonymous_15149 |
| 63057479U, // anonymous_5481 |
| }; |
| |
| static const uint32_t OpInfo1[] = { |
| 0U, // PHI |
| 0U, // INLINEASM |
| 0U, // INLINEASM_BR |
| 0U, // CFI_INSTRUCTION |
| 0U, // EH_LABEL |
| 0U, // GC_LABEL |
| 0U, // ANNOTATION_LABEL |
| 0U, // KILL |
| 0U, // EXTRACT_SUBREG |
| 0U, // INSERT_SUBREG |
| 0U, // IMPLICIT_DEF |
| 0U, // SUBREG_TO_REG |
| 0U, // COPY_TO_REGCLASS |
| 0U, // DBG_VALUE |
| 0U, // DBG_VALUE_LIST |
| 0U, // DBG_INSTR_REF |
| 0U, // DBG_PHI |
| 0U, // DBG_LABEL |
| 0U, // REG_SEQUENCE |
| 0U, // COPY |
| 0U, // BUNDLE |
| 0U, // LIFETIME_START |
| 0U, // LIFETIME_END |
| 0U, // PSEUDO_PROBE |
| 0U, // ARITH_FENCE |
| 0U, // STACKMAP |
| 0U, // FENTRY_CALL |
| 0U, // PATCHPOINT |
| 0U, // LOAD_STACK_GUARD |
| 0U, // PREALLOCATED_SETUP |
| 0U, // PREALLOCATED_ARG |
| 0U, // STATEPOINT |
| 0U, // LOCAL_ESCAPE |
| 0U, // FAULTING_OP |
| 0U, // PATCHABLE_OP |
| 0U, // PATCHABLE_FUNCTION_ENTER |
| 0U, // PATCHABLE_RET |
| 0U, // PATCHABLE_FUNCTION_EXIT |
| 0U, // PATCHABLE_TAIL_CALL |
| 0U, // PATCHABLE_EVENT_CALL |
| 0U, // PATCHABLE_TYPED_EVENT_CALL |
| 0U, // ICALL_BRANCH_FUNNEL |
| 0U, // MEMBARRIER |
| 0U, // G_ASSERT_SEXT |
| 0U, // G_ASSERT_ZEXT |
| 0U, // G_ASSERT_ALIGN |
| 0U, // G_ADD |
| 0U, // G_SUB |
| 0U, // G_MUL |
| 0U, // G_SDIV |
| 0U, // G_UDIV |
| 0U, // G_SREM |
| 0U, // G_UREM |
| 0U, // G_SDIVREM |
| 0U, // G_UDIVREM |
| 0U, // G_AND |
| 0U, // G_OR |
| 0U, // G_XOR |
| 0U, // G_IMPLICIT_DEF |
| 0U, // G_PHI |
| 0U, // G_FRAME_INDEX |
| 0U, // G_GLOBAL_VALUE |
| 0U, // G_EXTRACT |
| 0U, // G_UNMERGE_VALUES |
| 0U, // G_INSERT |
| 0U, // G_MERGE_VALUES |
| 0U, // G_BUILD_VECTOR |
| 0U, // G_BUILD_VECTOR_TRUNC |
| 0U, // G_CONCAT_VECTORS |
| 0U, // G_PTRTOINT |
| 0U, // G_INTTOPTR |
| 0U, // G_BITCAST |
| 0U, // G_FREEZE |
| 0U, // G_INTRINSIC_FPTRUNC_ROUND |
| 0U, // G_INTRINSIC_TRUNC |
| 0U, // G_INTRINSIC_ROUND |
| 0U, // G_INTRINSIC_LRINT |
| 0U, // G_INTRINSIC_ROUNDEVEN |
| 0U, // G_READCYCLECOUNTER |
| 0U, // G_LOAD |
| 0U, // G_SEXTLOAD |
| 0U, // G_ZEXTLOAD |
| 0U, // G_INDEXED_LOAD |
| 0U, // G_INDEXED_SEXTLOAD |
| 0U, // G_INDEXED_ZEXTLOAD |
| 0U, // G_STORE |
| 0U, // G_INDEXED_STORE |
| 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 0U, // G_ATOMIC_CMPXCHG |
| 0U, // G_ATOMICRMW_XCHG |
| 0U, // G_ATOMICRMW_ADD |
| 0U, // G_ATOMICRMW_SUB |
| 0U, // G_ATOMICRMW_AND |
| 0U, // G_ATOMICRMW_NAND |
| 0U, // G_ATOMICRMW_OR |
| 0U, // G_ATOMICRMW_XOR |
| 0U, // G_ATOMICRMW_MAX |
| 0U, // G_ATOMICRMW_MIN |
| 0U, // G_ATOMICRMW_UMAX |
| 0U, // G_ATOMICRMW_UMIN |
| 0U, // G_ATOMICRMW_FADD |
| 0U, // G_ATOMICRMW_FSUB |
| 0U, // G_ATOMICRMW_FMAX |
| 0U, // G_ATOMICRMW_FMIN |
| 0U, // G_ATOMICRMW_UINC_WRAP |
| 0U, // G_ATOMICRMW_UDEC_WRAP |
| 0U, // G_FENCE |
| 0U, // G_BRCOND |
| 0U, // G_BRINDIRECT |
| 0U, // G_INVOKE_REGION_START |
| 0U, // G_INTRINSIC |
| 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 0U, // G_ANYEXT |
| 0U, // G_TRUNC |
| 0U, // G_CONSTANT |
| 0U, // G_FCONSTANT |
| 0U, // G_VASTART |
| 0U, // G_VAARG |
| 0U, // G_SEXT |
| 0U, // G_SEXT_INREG |
| 0U, // G_ZEXT |
| 0U, // G_SHL |
| 0U, // G_LSHR |
| 0U, // G_ASHR |
| 0U, // G_FSHL |
| 0U, // G_FSHR |
| 0U, // G_ROTR |
| 0U, // G_ROTL |
| 0U, // G_ICMP |
| 0U, // G_FCMP |
| 0U, // G_SELECT |
| 0U, // G_UADDO |
| 0U, // G_UADDE |
| 0U, // G_USUBO |
| 0U, // G_USUBE |
| 0U, // G_SADDO |
| 0U, // G_SADDE |
| 0U, // G_SSUBO |
| 0U, // G_SSUBE |
| 0U, // G_UMULO |
| 0U, // G_SMULO |
| 0U, // G_UMULH |
| 0U, // G_SMULH |
| 0U, // G_UADDSAT |
| 0U, // G_SADDSAT |
| 0U, // G_USUBSAT |
| 0U, // G_SSUBSAT |
| 0U, // G_USHLSAT |
| 0U, // G_SSHLSAT |
| 0U, // G_SMULFIX |
| 0U, // G_UMULFIX |
| 0U, // G_SMULFIXSAT |
| 0U, // G_UMULFIXSAT |
| 0U, // G_SDIVFIX |
| 0U, // G_UDIVFIX |
| 0U, // G_SDIVFIXSAT |
| 0U, // G_UDIVFIXSAT |
| 0U, // G_FADD |
| 0U, // G_FSUB |
| 0U, // G_FMUL |
| 0U, // G_FMA |
| 0U, // G_FMAD |
| 0U, // G_FDIV |
| 0U, // G_FREM |
| 0U, // G_FPOW |
| 0U, // G_FPOWI |
| 0U, // G_FEXP |
| 0U, // G_FEXP2 |
| 0U, // G_FLOG |
| 0U, // G_FLOG2 |
| 0U, // G_FLOG10 |
| 0U, // G_FNEG |
| 0U, // G_FPEXT |
| 0U, // G_FPTRUNC |
| 0U, // G_FPTOSI |
| 0U, // G_FPTOUI |
| 0U, // G_SITOFP |
| 0U, // G_UITOFP |
| 0U, // G_FABS |
| 0U, // G_FCOPYSIGN |
| 0U, // G_IS_FPCLASS |
| 0U, // G_FCANONICALIZE |
| 0U, // G_FMINNUM |
| 0U, // G_FMAXNUM |
| 0U, // G_FMINNUM_IEEE |
| 0U, // G_FMAXNUM_IEEE |
| 0U, // G_FMINIMUM |
| 0U, // G_FMAXIMUM |
| 0U, // G_PTR_ADD |
| 0U, // G_PTRMASK |
| 0U, // G_SMIN |
| 0U, // G_SMAX |
| 0U, // G_UMIN |
| 0U, // G_UMAX |
| 0U, // G_ABS |
| 0U, // G_LROUND |
| 0U, // G_LLROUND |
| 0U, // G_BR |
| 0U, // G_BRJT |
| 0U, // G_INSERT_VECTOR_ELT |
| 0U, // G_EXTRACT_VECTOR_ELT |
| 0U, // G_SHUFFLE_VECTOR |
| 0U, // G_CTTZ |
| 0U, // G_CTTZ_ZERO_UNDEF |
| 0U, // G_CTLZ |
| 0U, // G_CTLZ_ZERO_UNDEF |
| 0U, // G_CTPOP |
| 0U, // G_BSWAP |
| 0U, // G_BITREVERSE |
| 0U, // G_FCEIL |
| 0U, // G_FCOS |
| 0U, // G_FSIN |
| 0U, // G_FSQRT |
| 0U, // G_FFLOOR |
| 0U, // G_FRINT |
| 0U, // G_FNEARBYINT |
| 0U, // G_ADDRSPACE_CAST |
| 0U, // G_BLOCK_ADDR |
| 0U, // G_JUMP_TABLE |
| 0U, // G_DYN_STACKALLOC |
| 0U, // G_STRICT_FADD |
| 0U, // G_STRICT_FSUB |
| 0U, // G_STRICT_FMUL |
| 0U, // G_STRICT_FDIV |
| 0U, // G_STRICT_FREM |
| 0U, // G_STRICT_FMA |
| 0U, // G_STRICT_FSQRT |
| 0U, // G_READ_REGISTER |
| 0U, // G_WRITE_REGISTER |
| 0U, // G_MEMCPY |
| 0U, // G_MEMCPY_INLINE |
| 0U, // G_MEMMOVE |
| 0U, // G_MEMSET |
| 0U, // G_BZERO |
| 0U, // G_VECREDUCE_SEQ_FADD |
| 0U, // G_VECREDUCE_SEQ_FMUL |
| 0U, // G_VECREDUCE_FADD |
| 0U, // G_VECREDUCE_FMUL |
| 0U, // G_VECREDUCE_FMAX |
| 0U, // G_VECREDUCE_FMIN |
| 0U, // G_VECREDUCE_ADD |
| 0U, // G_VECREDUCE_MUL |
| 0U, // G_VECREDUCE_AND |
| 0U, // G_VECREDUCE_OR |
| 0U, // G_VECREDUCE_XOR |
| 0U, // G_VECREDUCE_SMAX |
| 0U, // G_VECREDUCE_SMIN |
| 0U, // G_VECREDUCE_UMAX |
| 0U, // G_VECREDUCE_UMIN |
| 0U, // G_SBFX |
| 0U, // G_UBFX |
| 0U, // ABS_ZPmZ_UNDEF_B |
| 0U, // ABS_ZPmZ_UNDEF_D |
| 0U, // ABS_ZPmZ_UNDEF_H |
| 0U, // ABS_ZPmZ_UNDEF_S |
| 0U, // ADDHA_MPPZ_D_PSEUDO_D |
| 0U, // ADDHA_MPPZ_S_PSEUDO_S |
| 0U, // ADDSWrr |
| 0U, // ADDSXrr |
| 0U, // ADDVA_MPPZ_D_PSEUDO_D |
| 0U, // ADDVA_MPPZ_S_PSEUDO_S |
| 0U, // ADDWrr |
| 0U, // ADDXrr |
| 0U, // ADD_VG2_M2Z2Z_D_PSEUDO |
| 0U, // ADD_VG2_M2Z2Z_S_PSEUDO |
| 0U, // ADD_VG2_M2ZZ_D_PSEUDO |
| 0U, // ADD_VG2_M2ZZ_S_PSEUDO |
| 0U, // ADD_VG4_M4Z4Z_D_PSEUDO |
| 0U, // ADD_VG4_M4Z4Z_S_PSEUDO |
| 0U, // ADD_VG4_M4ZZ_D_PSEUDO |
| 0U, // ADD_VG4_M4ZZ_S_PSEUDO |
| 0U, // ADD_ZPZZ_ZERO_B |
| 0U, // ADD_ZPZZ_ZERO_D |
| 0U, // ADD_ZPZZ_ZERO_H |
| 0U, // ADD_ZPZZ_ZERO_S |
| 0U, // ADDlowTLS |
| 0U, // ADJCALLSTACKDOWN |
| 0U, // ADJCALLSTACKUP |
| 0U, // AESIMCrrTied |
| 0U, // AESMCrrTied |
| 0U, // ANDSWrr |
| 0U, // ANDSXrr |
| 0U, // ANDWrr |
| 0U, // ANDXrr |
| 0U, // AND_ZPZZ_ZERO_B |
| 0U, // AND_ZPZZ_ZERO_D |
| 0U, // AND_ZPZZ_ZERO_H |
| 0U, // AND_ZPZZ_ZERO_S |
| 0U, // ASRD_ZPZI_ZERO_B |
| 0U, // ASRD_ZPZI_ZERO_D |
| 0U, // ASRD_ZPZI_ZERO_H |
| 0U, // ASRD_ZPZI_ZERO_S |
| 0U, // ASR_ZPZI_UNDEF_B |
| 0U, // ASR_ZPZI_UNDEF_D |
| 0U, // ASR_ZPZI_UNDEF_H |
| 0U, // ASR_ZPZI_UNDEF_S |
| 0U, // ASR_ZPZZ_UNDEF_B |
| 0U, // ASR_ZPZZ_UNDEF_D |
| 0U, // ASR_ZPZZ_UNDEF_H |
| 0U, // ASR_ZPZZ_UNDEF_S |
| 0U, // ASR_ZPZZ_ZERO_B |
| 0U, // ASR_ZPZZ_ZERO_D |
| 0U, // ASR_ZPZZ_ZERO_H |
| 0U, // ASR_ZPZZ_ZERO_S |
| 0U, // BFDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 0U, // BFDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 0U, // BFDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 0U, // BFDOT_VG4_M4ZZI_HtoS_PSEUDO |
| 0U, // BFMLAL_MZZI_S_PSEUDO |
| 0U, // BFMLAL_MZZ_S_PSEUDO |
| 0U, // BFMLAL_VG2_M2Z2Z_S_PSEUDO |
| 0U, // BFMLAL_VG2_M2ZZI_S_PSEUDO |
| 0U, // BFMLAL_VG2_M2ZZ_S_PSEUDO |
| 0U, // BFMLAL_VG4_M4Z4Z_S_PSEUDO |
| 0U, // BFMLAL_VG4_M4ZZI_S_PSEUDO |
| 0U, // BFMLAL_VG4_M4ZZ_S_PSEUDO |
| 0U, // BFMLA_VG2_M2Z2Z_PSEUDO |
| 0U, // BFMLA_VG4_M4Z4Z_PSEUDO |
| 0U, // BFMLSL_MZZI_S_PSEUDO |
| 0U, // BFMLSL_MZZ_S_PSEUDO |
| 0U, // BFMLSL_VG2_M2Z2Z_S_PSEUDO |
| 0U, // BFMLSL_VG2_M2ZZI_S_PSEUDO |
| 0U, // BFMLSL_VG2_M2ZZ_S_PSEUDO |
| 0U, // BFMLSL_VG4_M4Z4Z_S_PSEUDO |
| 0U, // BFMLSL_VG4_M4ZZI_S_PSEUDO |
| 0U, // BFMLSL_VG4_M4ZZ_S_PSEUDO |
| 0U, // BFMLS_VG2_M2Z2Z_PSEUDO |
| 0U, // BFMLS_VG4_M4Z4Z_PSEUDO |
| 0U, // BFMOPA_MPPZZ_PSEUDO |
| 0U, // BFMOPS_MPPZZ_PSEUDO |
| 0U, // BFVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 0U, // BICSWrr |
| 0U, // BICSXrr |
| 0U, // BICWrr |
| 0U, // BICXrr |
| 0U, // BIC_ZPZZ_ZERO_B |
| 0U, // BIC_ZPZZ_ZERO_D |
| 0U, // BIC_ZPZZ_ZERO_H |
| 0U, // BIC_ZPZZ_ZERO_S |
| 0U, // BLRNoIP |
| 0U, // BLR_BTI |
| 0U, // BLR_RVMARKER |
| 0U, // BSPv16i8 |
| 0U, // BSPv8i8 |
| 0U, // CATCHRET |
| 0U, // CLEANUPRET |
| 0U, // CLS_ZPmZ_UNDEF_B |
| 0U, // CLS_ZPmZ_UNDEF_D |
| 0U, // CLS_ZPmZ_UNDEF_H |
| 0U, // CLS_ZPmZ_UNDEF_S |
| 0U, // CLZ_ZPmZ_UNDEF_B |
| 0U, // CLZ_ZPmZ_UNDEF_D |
| 0U, // CLZ_ZPmZ_UNDEF_H |
| 0U, // CLZ_ZPmZ_UNDEF_S |
| 0U, // CMP_SWAP_128 |
| 0U, // CMP_SWAP_128_ACQUIRE |
| 0U, // CMP_SWAP_128_MONOTONIC |
| 0U, // CMP_SWAP_128_RELEASE |
| 0U, // CMP_SWAP_16 |
| 0U, // CMP_SWAP_32 |
| 0U, // CMP_SWAP_64 |
| 0U, // CMP_SWAP_8 |
| 0U, // CNOT_ZPmZ_UNDEF_B |
| 0U, // CNOT_ZPmZ_UNDEF_D |
| 0U, // CNOT_ZPmZ_UNDEF_H |
| 0U, // CNOT_ZPmZ_UNDEF_S |
| 0U, // CNT_ZPmZ_UNDEF_B |
| 0U, // CNT_ZPmZ_UNDEF_D |
| 0U, // CNT_ZPmZ_UNDEF_H |
| 0U, // CNT_ZPmZ_UNDEF_S |
| 0U, // EMITBKEY |
| 0U, // EMITMTETAGGED |
| 0U, // EONWrr |
| 0U, // EONXrr |
| 0U, // EORWrr |
| 0U, // EORXrr |
| 0U, // EOR_ZPZZ_ZERO_B |
| 0U, // EOR_ZPZZ_ZERO_D |
| 0U, // EOR_ZPZZ_ZERO_H |
| 0U, // EOR_ZPZZ_ZERO_S |
| 0U, // F128CSEL |
| 0U, // FABD_ZPZZ_UNDEF_D |
| 0U, // FABD_ZPZZ_UNDEF_H |
| 0U, // FABD_ZPZZ_UNDEF_S |
| 0U, // FABD_ZPZZ_ZERO_D |
| 0U, // FABD_ZPZZ_ZERO_H |
| 0U, // FABD_ZPZZ_ZERO_S |
| 0U, // FABS_ZPmZ_UNDEF_D |
| 0U, // FABS_ZPmZ_UNDEF_H |
| 0U, // FABS_ZPmZ_UNDEF_S |
| 0U, // FADD_ZPZI_UNDEF_D |
| 0U, // FADD_ZPZI_UNDEF_H |
| 0U, // FADD_ZPZI_UNDEF_S |
| 0U, // FADD_ZPZI_ZERO_D |
| 0U, // FADD_ZPZI_ZERO_H |
| 0U, // FADD_ZPZI_ZERO_S |
| 0U, // FADD_ZPZZ_UNDEF_D |
| 0U, // FADD_ZPZZ_UNDEF_H |
| 0U, // FADD_ZPZZ_UNDEF_S |
| 0U, // FADD_ZPZZ_ZERO_D |
| 0U, // FADD_ZPZZ_ZERO_H |
| 0U, // FADD_ZPZZ_ZERO_S |
| 0U, // FCVTZS_ZPmZ_DtoD_UNDEF |
| 0U, // FCVTZS_ZPmZ_DtoS_UNDEF |
| 0U, // FCVTZS_ZPmZ_HtoD_UNDEF |
| 0U, // FCVTZS_ZPmZ_HtoH_UNDEF |
| 0U, // FCVTZS_ZPmZ_HtoS_UNDEF |
| 0U, // FCVTZS_ZPmZ_StoD_UNDEF |
| 0U, // FCVTZS_ZPmZ_StoS_UNDEF |
| 0U, // FCVTZU_ZPmZ_DtoD_UNDEF |
| 0U, // FCVTZU_ZPmZ_DtoS_UNDEF |
| 0U, // FCVTZU_ZPmZ_HtoD_UNDEF |
| 0U, // FCVTZU_ZPmZ_HtoH_UNDEF |
| 0U, // FCVTZU_ZPmZ_HtoS_UNDEF |
| 0U, // FCVTZU_ZPmZ_StoD_UNDEF |
| 0U, // FCVTZU_ZPmZ_StoS_UNDEF |
| 0U, // FCVT_ZPmZ_DtoH_UNDEF |
| 0U, // FCVT_ZPmZ_DtoS_UNDEF |
| 0U, // FCVT_ZPmZ_HtoD_UNDEF |
| 0U, // FCVT_ZPmZ_HtoS_UNDEF |
| 0U, // FCVT_ZPmZ_StoD_UNDEF |
| 0U, // FCVT_ZPmZ_StoH_UNDEF |
| 0U, // FDIVR_ZPZZ_ZERO_D |
| 0U, // FDIVR_ZPZZ_ZERO_H |
| 0U, // FDIVR_ZPZZ_ZERO_S |
| 0U, // FDIV_ZPZZ_UNDEF_D |
| 0U, // FDIV_ZPZZ_UNDEF_H |
| 0U, // FDIV_ZPZZ_UNDEF_S |
| 0U, // FDIV_ZPZZ_ZERO_D |
| 0U, // FDIV_ZPZZ_ZERO_H |
| 0U, // FDIV_ZPZZ_ZERO_S |
| 0U, // FDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 0U, // FDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 0U, // FDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 0U, // FDOT_VG4_M4ZZI_HtoS_PSEUDO |
| 0U, // FMAXNM_ZPZI_UNDEF_D |
| 0U, // FMAXNM_ZPZI_UNDEF_H |
| 0U, // FMAXNM_ZPZI_UNDEF_S |
| 0U, // FMAXNM_ZPZI_ZERO_D |
| 0U, // FMAXNM_ZPZI_ZERO_H |
| 0U, // FMAXNM_ZPZI_ZERO_S |
| 0U, // FMAXNM_ZPZZ_UNDEF_D |
| 0U, // FMAXNM_ZPZZ_UNDEF_H |
| 0U, // FMAXNM_ZPZZ_UNDEF_S |
| 0U, // FMAXNM_ZPZZ_ZERO_D |
| 0U, // FMAXNM_ZPZZ_ZERO_H |
| 0U, // FMAXNM_ZPZZ_ZERO_S |
| 0U, // FMAX_ZPZI_UNDEF_D |
| 0U, // FMAX_ZPZI_UNDEF_H |
| 0U, // FMAX_ZPZI_UNDEF_S |
| 0U, // FMAX_ZPZI_ZERO_D |
| 0U, // FMAX_ZPZI_ZERO_H |
| 0U, // FMAX_ZPZI_ZERO_S |
| 0U, // FMAX_ZPZZ_UNDEF_D |
| 0U, // FMAX_ZPZZ_UNDEF_H |
| 0U, // FMAX_ZPZZ_UNDEF_S |
| 0U, // FMAX_ZPZZ_ZERO_D |
| 0U, // FMAX_ZPZZ_ZERO_H |
| 0U, // FMAX_ZPZZ_ZERO_S |
| 0U, // FMINNM_ZPZI_UNDEF_D |
| 0U, // FMINNM_ZPZI_UNDEF_H |
| 0U, // FMINNM_ZPZI_UNDEF_S |
| 0U, // FMINNM_ZPZI_ZERO_D |
| 0U, // FMINNM_ZPZI_ZERO_H |
| 0U, // FMINNM_ZPZI_ZERO_S |
| 0U, // FMINNM_ZPZZ_UNDEF_D |
| 0U, // FMINNM_ZPZZ_UNDEF_H |
| 0U, // FMINNM_ZPZZ_UNDEF_S |
| 0U, // FMINNM_ZPZZ_ZERO_D |
| 0U, // FMINNM_ZPZZ_ZERO_H |
| 0U, // FMINNM_ZPZZ_ZERO_S |
| 0U, // FMIN_ZPZI_UNDEF_D |
| 0U, // FMIN_ZPZI_UNDEF_H |
| 0U, // FMIN_ZPZI_UNDEF_S |
| 0U, // FMIN_ZPZI_ZERO_D |
| 0U, // FMIN_ZPZI_ZERO_H |
| 0U, // FMIN_ZPZI_ZERO_S |
| 0U, // FMIN_ZPZZ_UNDEF_D |
| 0U, // FMIN_ZPZZ_UNDEF_H |
| 0U, // FMIN_ZPZZ_UNDEF_S |
| 0U, // FMIN_ZPZZ_ZERO_D |
| 0U, // FMIN_ZPZZ_ZERO_H |
| 0U, // FMIN_ZPZZ_ZERO_S |
| 0U, // FMLAL_MZZI_S_PSEUDO |
| 0U, // FMLAL_MZZ_S_PSEUDO |
| 0U, // FMLAL_VG2_M2Z2Z_S_PSEUDO |
| 0U, // FMLAL_VG2_M2ZZI_S_PSEUDO |
| 0U, // FMLAL_VG2_M2ZZ_S_PSEUDO |
| 0U, // FMLAL_VG4_M4Z4Z_S_PSEUDO |
| 0U, // FMLAL_VG4_M4ZZI_S_PSEUDO |
| 0U, // FMLAL_VG4_M4ZZ_S_PSEUDO |
| 0U, // FMLA_VG2_M2Z2Z_D_PSEUDO |
| 0U, // FMLA_VG2_M2Z2Z_S_PSEUDO |
| 0U, // FMLA_VG2_M2Z4Z_H_PSEUDO |
| 0U, // FMLA_VG2_M2ZZI_D_PSEUDO |
| 0U, // FMLA_VG2_M2ZZI_S_PSEUDO |
| 0U, // FMLA_VG2_M2ZZ_D_PSEUDO |
| 0U, // FMLA_VG2_M2ZZ_S_PSEUDO |
| 0U, // FMLA_VG4_M4Z4Z_D_PSEUDO |
| 0U, // FMLA_VG4_M4Z4Z_H_PSEUDO |
| 0U, // FMLA_VG4_M4Z4Z_S_PSEUDO |
| 0U, // FMLA_VG4_M4ZZI_D_PSEUDO |
| 0U, // FMLA_VG4_M4ZZI_S_PSEUDO |
| 0U, // FMLA_VG4_M4ZZ_D_PSEUDO |
| 0U, // FMLA_VG4_M4ZZ_S_PSEUDO |
| 0U, // FMLA_ZPZZZ_UNDEF_D |
| 0U, // FMLA_ZPZZZ_UNDEF_H |
| 0U, // FMLA_ZPZZZ_UNDEF_S |
| 0U, // FMLSL_MZZI_S_PSEUDO |
| 0U, // FMLSL_MZZ_S_PSEUDO |
| 0U, // FMLSL_VG2_M2Z2Z_S_PSEUDO |
| 0U, // FMLSL_VG2_M2ZZI_S_PSEUDO |
| 0U, // FMLSL_VG2_M2ZZ_S_PSEUDO |
| 0U, // FMLSL_VG4_M4Z4Z_S_PSEUDO |
| 0U, // FMLSL_VG4_M4ZZI_S_PSEUDO |
| 0U, // FMLSL_VG4_M4ZZ_S_PSEUDO |
| 0U, // FMLS_VG2_M2Z2Z_D_PSEUDO |
| 0U, // FMLS_VG2_M2Z2Z_H_PSEUDO |
| 0U, // FMLS_VG2_M2Z2Z_S_PSEUDO |
| 0U, // FMLS_VG2_M2ZZI_D_PSEUDO |
| 0U, // FMLS_VG2_M2ZZI_S_PSEUDO |
| 0U, // FMLS_VG2_M2ZZ_D_PSEUDO |
| 0U, // FMLS_VG2_M2ZZ_S_PSEUDO |
| 0U, // FMLS_VG4_M4Z2Z_H_PSEUDO |
| 0U, // FMLS_VG4_M4Z4Z_D_PSEUDO |
| 0U, // FMLS_VG4_M4Z4Z_S_PSEUDO |
| 0U, // FMLS_VG4_M4ZZI_D_PSEUDO |
| 0U, // FMLS_VG4_M4ZZI_S_PSEUDO |
| 0U, // FMLS_VG4_M4ZZ_D_PSEUDO |
| 0U, // FMLS_VG4_M4ZZ_S_PSEUDO |
| 0U, // FMLS_ZPZZZ_UNDEF_D |
| 0U, // FMLS_ZPZZZ_UNDEF_H |
| 0U, // FMLS_ZPZZZ_UNDEF_S |
| 0U, // FMOPAL_MPPZZ_PSEUDO |
| 0U, // FMOPA_MPPZZ_D_PSEUDO |
| 0U, // FMOPA_MPPZZ_S_PSEUDO |
| 0U, // FMOPSL_MPPZZ_PSEUDO |
| 0U, // FMOPS_MPPZZ_D_PSEUDO |
| 0U, // FMOPS_MPPZZ_S_PSEUDO |
| 0U, // FMOVD0 |
| 0U, // FMOVH0 |
| 0U, // FMOVS0 |
| 0U, // FMULX_ZPZZ_ZERO_D |
| 0U, // FMULX_ZPZZ_ZERO_H |
| 0U, // FMULX_ZPZZ_ZERO_S |
| 0U, // FMUL_ZPZI_UNDEF_D |
| 0U, // FMUL_ZPZI_UNDEF_H |
| 0U, // FMUL_ZPZI_UNDEF_S |
| 0U, // FMUL_ZPZI_ZERO_D |
| 0U, // FMUL_ZPZI_ZERO_H |
| 0U, // FMUL_ZPZI_ZERO_S |
| 0U, // FMUL_ZPZZ_UNDEF_D |
| 0U, // FMUL_ZPZZ_UNDEF_H |
| 0U, // FMUL_ZPZZ_UNDEF_S |
| 0U, // FMUL_ZPZZ_ZERO_D |
| 0U, // FMUL_ZPZZ_ZERO_H |
| 0U, // FMUL_ZPZZ_ZERO_S |
| 0U, // FNEG_ZPmZ_UNDEF_D |
| 0U, // FNEG_ZPmZ_UNDEF_H |
| 0U, // FNEG_ZPmZ_UNDEF_S |
| 0U, // FNMLA_ZPZZZ_UNDEF_D |
| 0U, // FNMLA_ZPZZZ_UNDEF_H |
| 0U, // FNMLA_ZPZZZ_UNDEF_S |
| 0U, // FNMLS_ZPZZZ_UNDEF_D |
| 0U, // FNMLS_ZPZZZ_UNDEF_H |
| 0U, // FNMLS_ZPZZZ_UNDEF_S |
| 0U, // FRECPX_ZPmZ_UNDEF_D |
| 0U, // FRECPX_ZPmZ_UNDEF_H |
| 0U, // FRECPX_ZPmZ_UNDEF_S |
| 0U, // FRINTA_ZPmZ_UNDEF_D |
| 0U, // FRINTA_ZPmZ_UNDEF_H |
| 0U, // FRINTA_ZPmZ_UNDEF_S |
| 0U, // FRINTI_ZPmZ_UNDEF_D |
| 0U, // FRINTI_ZPmZ_UNDEF_H |
| 0U, // FRINTI_ZPmZ_UNDEF_S |
| 0U, // FRINTM_ZPmZ_UNDEF_D |
| 0U, // FRINTM_ZPmZ_UNDEF_H |
| 0U, // FRINTM_ZPmZ_UNDEF_S |
| 0U, // FRINTN_ZPmZ_UNDEF_D |
| 0U, // FRINTN_ZPmZ_UNDEF_H |
| 0U, // FRINTN_ZPmZ_UNDEF_S |
| 0U, // FRINTP_ZPmZ_UNDEF_D |
| 0U, // FRINTP_ZPmZ_UNDEF_H |
| 0U, // FRINTP_ZPmZ_UNDEF_S |
| 0U, // FRINTX_ZPmZ_UNDEF_D |
| 0U, // FRINTX_ZPmZ_UNDEF_H |
| 0U, // FRINTX_ZPmZ_UNDEF_S |
| 0U, // FRINTZ_ZPmZ_UNDEF_D |
| 0U, // FRINTZ_ZPmZ_UNDEF_H |
| 0U, // FRINTZ_ZPmZ_UNDEF_S |
| 0U, // FSQRT_ZPmZ_UNDEF_D |
| 0U, // FSQRT_ZPmZ_UNDEF_H |
| 0U, // FSQRT_ZPmZ_UNDEF_S |
| 0U, // FSUBR_ZPZI_UNDEF_D |
| 0U, // FSUBR_ZPZI_UNDEF_H |
| 0U, // FSUBR_ZPZI_UNDEF_S |
| 0U, // FSUBR_ZPZI_ZERO_D |
| 0U, // FSUBR_ZPZI_ZERO_H |
| 0U, // FSUBR_ZPZI_ZERO_S |
| 0U, // FSUBR_ZPZZ_ZERO_D |
| 0U, // FSUBR_ZPZZ_ZERO_H |
| 0U, // FSUBR_ZPZZ_ZERO_S |
| 0U, // FSUB_ZPZI_UNDEF_D |
| 0U, // FSUB_ZPZI_UNDEF_H |
| 0U, // FSUB_ZPZI_UNDEF_S |
| 0U, // FSUB_ZPZI_ZERO_D |
| 0U, // FSUB_ZPZI_ZERO_H |
| 0U, // FSUB_ZPZI_ZERO_S |
| 0U, // FSUB_ZPZZ_UNDEF_D |
| 0U, // FSUB_ZPZZ_UNDEF_H |
| 0U, // FSUB_ZPZZ_UNDEF_S |
| 0U, // FSUB_ZPZZ_ZERO_D |
| 0U, // FSUB_ZPZZ_ZERO_H |
| 0U, // FSUB_ZPZZ_ZERO_S |
| 0U, // FVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 0U, // GLD1B_D |
| 0U, // GLD1B_D_IMM |
| 0U, // GLD1B_D_SXTW |
| 0U, // GLD1B_D_UXTW |
| 0U, // GLD1B_S_IMM |
| 0U, // GLD1B_S_SXTW |
| 0U, // GLD1B_S_UXTW |
| 0U, // GLD1D |
| 0U, // GLD1D_IMM |
| 0U, // GLD1D_SCALED |
| 0U, // GLD1D_SXTW |
| 0U, // GLD1D_SXTW_SCALED |
| 0U, // GLD1D_UXTW |
| 0U, // GLD1D_UXTW_SCALED |
| 0U, // GLD1H_D |
| 0U, // GLD1H_D_IMM |
| 0U, // GLD1H_D_SCALED |
| 0U, // GLD1H_D_SXTW |
| 0U, // GLD1H_D_SXTW_SCALED |
| 0U, // GLD1H_D_UXTW |
| 0U, // GLD1H_D_UXTW_SCALED |
| 0U, // GLD1H_S_IMM |
| 0U, // GLD1H_S_SXTW |
| 0U, // GLD1H_S_SXTW_SCALED |
| 0U, // GLD1H_S_UXTW |
| 0U, // GLD1H_S_UXTW_SCALED |
| 0U, // GLD1SB_D |
| 0U, // GLD1SB_D_IMM |
| 0U, // GLD1SB_D_SXTW |
| 0U, // GLD1SB_D_UXTW |
| 0U, // GLD1SB_S_IMM |
| 0U, // GLD1SB_S_SXTW |
| 0U, // GLD1SB_S_UXTW |
| 0U, // GLD1SH_D |
| 0U, // GLD1SH_D_IMM |
| 0U, // GLD1SH_D_SCALED |
| 0U, // GLD1SH_D_SXTW |
| 0U, // GLD1SH_D_SXTW_SCALED |
| 0U, // GLD1SH_D_UXTW |
| 0U, // GLD1SH_D_UXTW_SCALED |
| 0U, // GLD1SH_S_IMM |
| 0U, // GLD1SH_S_SXTW |
| 0U, // GLD1SH_S_SXTW_SCALED |
| 0U, // GLD1SH_S_UXTW |
| 0U, // GLD1SH_S_UXTW_SCALED |
| 0U, // GLD1SW_D |
| 0U, // GLD1SW_D_IMM |
| 0U, // GLD1SW_D_SCALED |
| 0U, // GLD1SW_D_SXTW |
| 0U, // GLD1SW_D_SXTW_SCALED |
| 0U, // GLD1SW_D_UXTW |
| 0U, // GLD1SW_D_UXTW_SCALED |
| 0U, // GLD1W_D |
| 0U, // GLD1W_D_IMM |
| 0U, // GLD1W_D_SCALED |
| 0U, // GLD1W_D_SXTW |
| 0U, // GLD1W_D_SXTW_SCALED |
| 0U, // GLD1W_D_UXTW |
| 0U, // GLD1W_D_UXTW_SCALED |
| 0U, // GLD1W_IMM |
| 0U, // GLD1W_SXTW |
| 0U, // GLD1W_SXTW_SCALED |
| 0U, // GLD1W_UXTW |
| 0U, // GLD1W_UXTW_SCALED |
| 0U, // GLDFF1B_D |
| 0U, // GLDFF1B_D_IMM |
| 0U, // GLDFF1B_D_SXTW |
| 0U, // GLDFF1B_D_UXTW |
| 0U, // GLDFF1B_S_IMM |
| 0U, // GLDFF1B_S_SXTW |
| 0U, // GLDFF1B_S_UXTW |
| 0U, // GLDFF1D |
| 0U, // GLDFF1D_IMM |
| 0U, // GLDFF1D_SCALED |
| 0U, // GLDFF1D_SXTW |
| 0U, // GLDFF1D_SXTW_SCALED |
| 0U, // GLDFF1D_UXTW |
| 0U, // GLDFF1D_UXTW_SCALED |
| 0U, // GLDFF1H_D |
| 0U, // GLDFF1H_D_IMM |
| 0U, // GLDFF1H_D_SCALED |
| 0U, // GLDFF1H_D_SXTW |
| 0U, // GLDFF1H_D_SXTW_SCALED |
| 0U, // GLDFF1H_D_UXTW |
| 0U, // GLDFF1H_D_UXTW_SCALED |
| 0U, // GLDFF1H_S_IMM |
| 0U, // GLDFF1H_S_SXTW |
| 0U, // GLDFF1H_S_SXTW_SCALED |
| 0U, // GLDFF1H_S_UXTW |
| 0U, // GLDFF1H_S_UXTW_SCALED |
| 0U, // GLDFF1SB_D |
| 0U, // GLDFF1SB_D_IMM |
| 0U, // GLDFF1SB_D_SXTW |
| 0U, // GLDFF1SB_D_UXTW |
| 0U, // GLDFF1SB_S_IMM |
| 0U, // GLDFF1SB_S_SXTW |
| 0U, // GLDFF1SB_S_UXTW |
| 0U, // GLDFF1SH_D |
| 0U, // GLDFF1SH_D_IMM |
| 0U, // GLDFF1SH_D_SCALED |
| 0U, // GLDFF1SH_D_SXTW |
| 0U, // GLDFF1SH_D_SXTW_SCALED |
| 0U, // GLDFF1SH_D_UXTW |
| 0U, // GLDFF1SH_D_UXTW_SCALED |
| 0U, // GLDFF1SH_S_IMM |
| 0U, // GLDFF1SH_S_SXTW |
| 0U, // GLDFF1SH_S_SXTW_SCALED |
| 0U, // GLDFF1SH_S_UXTW |
| 0U, // GLDFF1SH_S_UXTW_SCALED |
| 0U, // GLDFF1SW_D |
| 0U, // GLDFF1SW_D_IMM |
| 0U, // GLDFF1SW_D_SCALED |
| 0U, // GLDFF1SW_D_SXTW |
| 0U, // GLDFF1SW_D_SXTW_SCALED |
| 0U, // GLDFF1SW_D_UXTW |
| 0U, // GLDFF1SW_D_UXTW_SCALED |
| 0U, // GLDFF1W_D |
| 0U, // GLDFF1W_D_IMM |
| 0U, // GLDFF1W_D_SCALED |
| 0U, // GLDFF1W_D_SXTW |
| 0U, // GLDFF1W_D_SXTW_SCALED |
| 0U, // GLDFF1W_D_UXTW |
| 0U, // GLDFF1W_D_UXTW_SCALED |
| 0U, // GLDFF1W_IMM |
| 0U, // GLDFF1W_SXTW |
| 0U, // GLDFF1W_SXTW_SCALED |
| 0U, // GLDFF1W_UXTW |
| 0U, // GLDFF1W_UXTW_SCALED |
| 0U, // G_ADD_LOW |
| 0U, // G_BIT |
| 0U, // G_DUP |
| 0U, // G_DUPLANE16 |
| 0U, // G_DUPLANE32 |
| 0U, // G_DUPLANE64 |
| 0U, // G_DUPLANE8 |
| 0U, // G_EXT |
| 0U, // G_FCMEQ |
| 0U, // G_FCMEQZ |
| 0U, // G_FCMGE |
| 0U, // G_FCMGEZ |
| 0U, // G_FCMGT |
| 0U, // G_FCMGTZ |
| 0U, // G_FCMLEZ |
| 0U, // G_FCMLTZ |
| 0U, // G_PREFETCH |
| 0U, // G_REV16 |
| 0U, // G_REV32 |
| 0U, // G_REV64 |
| 0U, // G_SITOF |
| 0U, // G_TRN1 |
| 0U, // G_TRN2 |
| 0U, // G_UITOF |
| 0U, // G_UZP1 |
| 0U, // G_UZP2 |
| 0U, // G_VASHR |
| 0U, // G_VLSHR |
| 0U, // G_ZIP1 |
| 0U, // G_ZIP2 |
| 0U, // HOM_Epilog |
| 0U, // HOM_Prolog |
| 0U, // HWASAN_CHECK_MEMACCESS |
| 0U, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES |
| 0U, // INSERT_MXIPZ_H_PSEUDO_B |
| 0U, // INSERT_MXIPZ_H_PSEUDO_D |
| 0U, // INSERT_MXIPZ_H_PSEUDO_H |
| 0U, // INSERT_MXIPZ_H_PSEUDO_Q |
| 0U, // INSERT_MXIPZ_H_PSEUDO_S |
| 0U, // INSERT_MXIPZ_V_PSEUDO_B |
| 0U, // INSERT_MXIPZ_V_PSEUDO_D |
| 0U, // INSERT_MXIPZ_V_PSEUDO_H |
| 0U, // INSERT_MXIPZ_V_PSEUDO_Q |
| 0U, // INSERT_MXIPZ_V_PSEUDO_S |
| 0U, // IRGstack |
| 0U, // JumpTableDest16 |
| 0U, // JumpTableDest32 |
| 0U, // JumpTableDest8 |
| 0U, // KCFI_CHECK |
| 0U, // LD1B_D_IMM |
| 0U, // LD1B_H_IMM |
| 0U, // LD1B_IMM |
| 0U, // LD1B_S_IMM |
| 0U, // LD1D_IMM |
| 0U, // LD1H_D_IMM |
| 0U, // LD1H_IMM |
| 0U, // LD1H_S_IMM |
| 0U, // LD1SB_D_IMM |
| 0U, // LD1SB_H_IMM |
| 0U, // LD1SB_S_IMM |
| 0U, // LD1SH_D_IMM |
| 0U, // LD1SH_S_IMM |
| 0U, // LD1SW_D_IMM |
| 0U, // LD1W_D_IMM |
| 0U, // LD1W_IMM |
| 0U, // LD1_MXIPXX_H_PSEUDO_B |
| 0U, // LD1_MXIPXX_H_PSEUDO_D |
| 0U, // LD1_MXIPXX_H_PSEUDO_H |
| 0U, // LD1_MXIPXX_H_PSEUDO_Q |
| 0U, // LD1_MXIPXX_H_PSEUDO_S |
| 0U, // LD1_MXIPXX_V_PSEUDO_B |
| 0U, // LD1_MXIPXX_V_PSEUDO_D |
| 0U, // LD1_MXIPXX_V_PSEUDO_H |
| 0U, // LD1_MXIPXX_V_PSEUDO_Q |
| 0U, // LD1_MXIPXX_V_PSEUDO_S |
| 0U, // LDFF1B |
| 0U, // LDFF1B_D |
| 0U, // LDFF1B_H |
| 0U, // LDFF1B_S |
| 0U, // LDFF1D |
| 0U, // LDFF1H |
| 0U, // LDFF1H_D |
| 0U, // LDFF1H_S |
| 0U, // LDFF1SB_D |
| 0U, // LDFF1SB_H |
| 0U, // LDFF1SB_S |
| 0U, // LDFF1SH_D |
| 0U, // LDFF1SH_S |
| 0U, // LDFF1SW_D |
| 0U, // LDFF1W |
| 0U, // LDFF1W_D |
| 0U, // LDNF1B_D_IMM |
| 0U, // LDNF1B_H_IMM |
| 0U, // LDNF1B_IMM |
| 0U, // LDNF1B_S_IMM |
| 0U, // LDNF1D_IMM |
| 0U, // LDNF1H_D_IMM |
| 0U, // LDNF1H_IMM |
| 0U, // LDNF1H_S_IMM |
| 0U, // LDNF1SB_D_IMM |
| 0U, // LDNF1SB_H_IMM |
| 0U, // LDNF1SB_S_IMM |
| 0U, // LDNF1SH_D_IMM |
| 0U, // LDNF1SH_S_IMM |
| 0U, // LDNF1SW_D_IMM |
| 0U, // LDNF1W_D_IMM |
| 0U, // LDNF1W_IMM |
| 0U, // LDR_ZA_PSEUDO |
| 0U, // LDR_ZZXI |
| 0U, // LDR_ZZZXI |
| 0U, // LDR_ZZZZXI |
| 0U, // LOADgot |
| 0U, // LSL_ZPZI_UNDEF_B |
| 0U, // LSL_ZPZI_UNDEF_D |
| 0U, // LSL_ZPZI_UNDEF_H |
| 0U, // LSL_ZPZI_UNDEF_S |
| 0U, // LSL_ZPZZ_UNDEF_B |
| 0U, // LSL_ZPZZ_UNDEF_D |
| 0U, // LSL_ZPZZ_UNDEF_H |
| 0U, // LSL_ZPZZ_UNDEF_S |
| 0U, // LSL_ZPZZ_ZERO_B |
| 0U, // LSL_ZPZZ_ZERO_D |
| 0U, // LSL_ZPZZ_ZERO_H |
| 0U, // LSL_ZPZZ_ZERO_S |
| 0U, // LSR_ZPZI_UNDEF_B |
| 0U, // LSR_ZPZI_UNDEF_D |
| 0U, // LSR_ZPZI_UNDEF_H |
| 0U, // LSR_ZPZI_UNDEF_S |
| 0U, // LSR_ZPZZ_UNDEF_B |
| 0U, // LSR_ZPZZ_UNDEF_D |
| 0U, // LSR_ZPZZ_UNDEF_H |
| 0U, // LSR_ZPZZ_UNDEF_S |
| 0U, // LSR_ZPZZ_ZERO_B |
| 0U, // LSR_ZPZZ_ZERO_D |
| 0U, // LSR_ZPZZ_ZERO_H |
| 0U, // LSR_ZPZZ_ZERO_S |
| 0U, // MOPSMemoryCopyPseudo |
| 0U, // MOPSMemoryMovePseudo |
| 0U, // MOPSMemorySetPseudo |
| 0U, // MOPSMemorySetTaggingPseudo |
| 0U, // MOVMCSym |
| 0U, // MOVaddr |
| 0U, // MOVaddrBA |
| 0U, // MOVaddrCP |
| 0U, // MOVaddrEXT |
| 0U, // MOVaddrJT |
| 0U, // MOVaddrTLS |
| 0U, // MOVbaseTLS |
| 0U, // MOVi32imm |
| 0U, // MOVi64imm |
| 0U, // MRS_FPCR |
| 0U, // MSR_FPCR |
| 0U, // MSRpstatePseudo |
| 0U, // MUL_ZPZZ_UNDEF_B |
| 0U, // MUL_ZPZZ_UNDEF_D |
| 0U, // MUL_ZPZZ_UNDEF_H |
| 0U, // MUL_ZPZZ_UNDEF_S |
| 0U, // NEG_ZPmZ_UNDEF_B |
| 0U, // NEG_ZPmZ_UNDEF_D |
| 0U, // NEG_ZPmZ_UNDEF_H |
| 0U, // NEG_ZPmZ_UNDEF_S |
| 0U, // NOT_ZPmZ_UNDEF_B |
| 0U, // NOT_ZPmZ_UNDEF_D |
| 0U, // NOT_ZPmZ_UNDEF_H |
| 0U, // NOT_ZPmZ_UNDEF_S |
| 0U, // OBSCURE_COPY |
| 0U, // ORNWrr |
| 0U, // ORNXrr |
| 0U, // ORRWrr |
| 0U, // ORRXrr |
| 0U, // ORR_ZPZZ_ZERO_B |
| 0U, // ORR_ZPZZ_ZERO_D |
| 0U, // ORR_ZPZZ_ZERO_H |
| 0U, // ORR_ZPZZ_ZERO_S |
| 0U, // PTEST_PP_ANY |
| 0U, // RDFFR_P |
| 0U, // RDFFR_PPz |
| 0U, // RET_ReallyLR |
| 0U, // RestoreZAPseudo |
| 0U, // SABD_ZPZZ_UNDEF_B |
| 0U, // SABD_ZPZZ_UNDEF_D |
| 0U, // SABD_ZPZZ_UNDEF_H |
| 0U, // SABD_ZPZZ_UNDEF_S |
| 0U, // SCVTF_ZPmZ_DtoD_UNDEF |
| 0U, // SCVTF_ZPmZ_DtoH_UNDEF |
| 0U, // SCVTF_ZPmZ_DtoS_UNDEF |
| 0U, // SCVTF_ZPmZ_HtoH_UNDEF |
| 0U, // SCVTF_ZPmZ_StoD_UNDEF |
| 0U, // SCVTF_ZPmZ_StoH_UNDEF |
| 0U, // SCVTF_ZPmZ_StoS_UNDEF |
| 0U, // SDIV_ZPZZ_UNDEF_D |
| 0U, // SDIV_ZPZZ_UNDEF_S |
| 0U, // SDOT_VG2_M2Z2Z_BtoS_PSEUDO |
| 0U, // SDOT_VG2_M2Z2Z_HtoD_PSEUDO |
| 0U, // SDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 0U, // SDOT_VG2_M2ZZI_BToS_PSEUDO |
| 0U, // SDOT_VG2_M2ZZI_HToS_PSEUDO |
| 0U, // SDOT_VG2_M2ZZI_HtoD_PSEUDO |
| 0U, // SDOT_VG4_M4Z4Z_BtoS_PSEUDO |
| 0U, // SDOT_VG4_M4Z4Z_HtoD_PSEUDO |
| 0U, // SDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 0U, // SDOT_VG4_M4ZZI_BToS_PSEUDO |
| 0U, // SDOT_VG4_M4ZZI_HToS_PSEUDO |
| 0U, // SDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 0U, // SEH_AddFP |
| 0U, // SEH_EpilogEnd |
| 0U, // SEH_EpilogStart |
| 0U, // SEH_Nop |
| 0U, // SEH_PACSignLR |
| 0U, // SEH_PrologEnd |
| 0U, // SEH_SaveFPLR |
| 0U, // SEH_SaveFPLR_X |
| 0U, // SEH_SaveFReg |
| 0U, // SEH_SaveFRegP |
| 0U, // SEH_SaveFRegP_X |
| 0U, // SEH_SaveFReg_X |
| 0U, // SEH_SaveReg |
| 0U, // SEH_SaveRegP |
| 0U, // SEH_SaveRegP_X |
| 0U, // SEH_SaveReg_X |
| 0U, // SEH_SetFP |
| 0U, // SEH_StackAlloc |
| 0U, // SMAX_ZPZZ_UNDEF_B |
| 0U, // SMAX_ZPZZ_UNDEF_D |
| 0U, // SMAX_ZPZZ_UNDEF_H |
| 0U, // SMAX_ZPZZ_UNDEF_S |
| 0U, // SMIN_ZPZZ_UNDEF_B |
| 0U, // SMIN_ZPZZ_UNDEF_D |
| 0U, // SMIN_ZPZZ_UNDEF_H |
| 0U, // SMIN_ZPZZ_UNDEF_S |
| 0U, // SMLAL_MZZI_S_PSEUDO |
| 0U, // SMLAL_MZZ_S_PSEUDO |
| 0U, // SMLAL_VG2_M2Z2Z_S_PSEUDO |
| 0U, // SMLAL_VG2_M2ZZI_S_PSEUDO |
| 0U, // SMLAL_VG2_M2ZZ_S_PSEUDO |
| 0U, // SMLAL_VG4_M4Z4Z_S_PSEUDO |
| 0U, // SMLAL_VG4_M4ZZI_S_PSEUDO |
| 0U, // SMLAL_VG4_M4ZZ_S_PSEUDO |
| 0U, // SMLSL_MZZI_S_PSEUDO |
| 0U, // SMLSL_MZZ_S_PSEUDO |
| 0U, // SMLSL_VG2_M2Z2Z_S_PSEUDO |
| 0U, // SMLSL_VG2_M2ZZI_S_PSEUDO |
| 0U, // SMLSL_VG2_M2ZZ_S_PSEUDO |
| 0U, // SMLSL_VG4_M4Z4Z_S_PSEUDO |
| 0U, // SMLSL_VG4_M4ZZI_S_PSEUDO |
| 0U, // SMLSL_VG4_M4ZZ_S_PSEUDO |
| 0U, // SMOPA_MPPZZ_D_PSEUDO |
| 0U, // SMOPA_MPPZZ_S_PSEUDO |
| 0U, // SMOPS_MPPZZ_D_PSEUDO |
| 0U, // SMOPS_MPPZZ_S_PSEUDO |
| 0U, // SMULH_ZPZZ_UNDEF_B |
| 0U, // SMULH_ZPZZ_UNDEF_D |
| 0U, // SMULH_ZPZZ_UNDEF_H |
| 0U, // SMULH_ZPZZ_UNDEF_S |
| 0U, // SPACE |
| 0U, // SQABS_ZPmZ_UNDEF_B |
| 0U, // SQABS_ZPmZ_UNDEF_D |
| 0U, // SQABS_ZPmZ_UNDEF_H |
| 0U, // SQABS_ZPmZ_UNDEF_S |
| 0U, // SQNEG_ZPmZ_UNDEF_B |
| 0U, // SQNEG_ZPmZ_UNDEF_D |
| 0U, // SQNEG_ZPmZ_UNDEF_H |
| 0U, // SQNEG_ZPmZ_UNDEF_S |
| 0U, // SQRSHL_ZPZZ_UNDEF_B |
| 0U, // SQRSHL_ZPZZ_UNDEF_D |
| 0U, // SQRSHL_ZPZZ_UNDEF_H |
| 0U, // SQRSHL_ZPZZ_UNDEF_S |
| 0U, // SQSHLU_ZPZI_ZERO_B |
| 0U, // SQSHLU_ZPZI_ZERO_D |
| 0U, // SQSHLU_ZPZI_ZERO_H |
| 0U, // SQSHLU_ZPZI_ZERO_S |
| 0U, // SQSHL_ZPZI_ZERO_B |
| 0U, // SQSHL_ZPZI_ZERO_D |
| 0U, // SQSHL_ZPZI_ZERO_H |
| 0U, // SQSHL_ZPZI_ZERO_S |
| 0U, // SQSHL_ZPZZ_UNDEF_B |
| 0U, // SQSHL_ZPZZ_UNDEF_D |
| 0U, // SQSHL_ZPZZ_UNDEF_H |
| 0U, // SQSHL_ZPZZ_UNDEF_S |
| 0U, // SRSHL_ZPZZ_UNDEF_B |
| 0U, // SRSHL_ZPZZ_UNDEF_D |
| 0U, // SRSHL_ZPZZ_UNDEF_H |
| 0U, // SRSHL_ZPZZ_UNDEF_S |
| 0U, // SRSHR_ZPZI_ZERO_B |
| 0U, // SRSHR_ZPZI_ZERO_D |
| 0U, // SRSHR_ZPZI_ZERO_H |
| 0U, // SRSHR_ZPZI_ZERO_S |
| 0U, // STGloop |
| 0U, // STGloop_wback |
| 0U, // STR_ZZXI |
| 0U, // STR_ZZZXI |
| 0U, // STR_ZZZZXI |
| 0U, // STZGloop |
| 0U, // STZGloop_wback |
| 0U, // SUBR_ZPZZ_ZERO_B |
| 0U, // SUBR_ZPZZ_ZERO_D |
| 0U, // SUBR_ZPZZ_ZERO_H |
| 0U, // SUBR_ZPZZ_ZERO_S |
| 0U, // SUBSWrr |
| 0U, // SUBSXrr |
| 0U, // SUBWrr |
| 0U, // SUBXrr |
| 0U, // SUB_VG2_M2Z2Z_D_PSEUDO |
| 0U, // SUB_VG2_M2Z2Z_S_PSEUDO |
| 0U, // SUB_VG2_M2ZZ_D_PSEUDO |
| 0U, // SUB_VG2_M2ZZ_S_PSEUDO |
| 0U, // SUB_VG4_M4Z4Z_D_PSEUDO |
| 0U, // SUB_VG4_M4Z4Z_S_PSEUDO |
| 0U, // SUB_VG4_M4ZZ_D_PSEUDO |
| 0U, // SUB_VG4_M4ZZ_S_PSEUDO |
| 0U, // SUB_ZPZZ_ZERO_B |
| 0U, // SUB_ZPZZ_ZERO_D |
| 0U, // SUB_ZPZZ_ZERO_H |
| 0U, // SUB_ZPZZ_ZERO_S |
| 0U, // SUDOT_VG2_M2ZZI_BToS_PSEUDO |
| 0U, // SUDOT_VG4_M4ZZI_BToS_PSEUDO |
| 0U, // SUMOPA_MPPZZ_D_PSEUDO |
| 0U, // SUMOPA_MPPZZ_S_PSEUDO |
| 0U, // SUMOPS_MPPZZ_D_PSEUDO |
| 0U, // SUMOPS_MPPZZ_S_PSEUDO |
| 0U, // SUVDOT_VG4_M4ZZI_BToS_PSEUDO |
| 0U, // SVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 0U, // SVDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 0U, // SVDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 0U, // SXTB_ZPmZ_UNDEF_D |
| 0U, // SXTB_ZPmZ_UNDEF_H |
| 0U, // SXTB_ZPmZ_UNDEF_S |
| 0U, // SXTH_ZPmZ_UNDEF_D |
| 0U, // SXTH_ZPmZ_UNDEF_S |
| 0U, // SXTW_ZPmZ_UNDEF_D |
| 0U, // SpeculationBarrierISBDSBEndBB |
| 0U, // SpeculationBarrierSBEndBB |
| 0U, // SpeculationSafeValueW |
| 0U, // SpeculationSafeValueX |
| 0U, // StoreSwiftAsyncContext |
| 0U, // TAGPstack |
| 0U, // TCRETURNdi |
| 0U, // TCRETURNri |
| 0U, // TCRETURNriALL |
| 0U, // TCRETURNriBTI |
| 0U, // TLSDESCCALL |
| 0U, // TLSDESC_CALLSEQ |
| 0U, // UABD_ZPZZ_UNDEF_B |
| 0U, // UABD_ZPZZ_UNDEF_D |
| 0U, // UABD_ZPZZ_UNDEF_H |
| 0U, // UABD_ZPZZ_UNDEF_S |
| 0U, // UCVTF_ZPmZ_DtoD_UNDEF |
| 0U, // UCVTF_ZPmZ_DtoH_UNDEF |
| 0U, // UCVTF_ZPmZ_DtoS_UNDEF |
| 0U, // UCVTF_ZPmZ_HtoH_UNDEF |
| 0U, // UCVTF_ZPmZ_StoD_UNDEF |
| 0U, // UCVTF_ZPmZ_StoH_UNDEF |
| 0U, // UCVTF_ZPmZ_StoS_UNDEF |
| 0U, // UDIV_ZPZZ_UNDEF_D |
| 0U, // UDIV_ZPZZ_UNDEF_S |
| 0U, // UDOT_VG2_M2Z2Z_BtoS_PSEUDO |
| 0U, // UDOT_VG2_M2Z2Z_HtoD_PSEUDO |
| 0U, // UDOT_VG2_M2Z2Z_HtoS_PSEUDO |
| 0U, // UDOT_VG2_M2ZZI_BToS_PSEUDO |
| 0U, // UDOT_VG2_M2ZZI_HToS_PSEUDO |
| 0U, // UDOT_VG2_M2ZZI_HtoD_PSEUDO |
| 0U, // UDOT_VG4_M4Z4Z_BtoS_PSEUDO |
| 0U, // UDOT_VG4_M4Z4Z_HtoD_PSEUDO |
| 0U, // UDOT_VG4_M4Z4Z_HtoS_PSEUDO |
| 0U, // UDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 0U, // UDOT_VG4_M4ZZI_HToS_PSEUDO |
| 0U, // UDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 0U, // UMAX_ZPZZ_UNDEF_B |
| 0U, // UMAX_ZPZZ_UNDEF_D |
| 0U, // UMAX_ZPZZ_UNDEF_H |
| 0U, // UMAX_ZPZZ_UNDEF_S |
| 0U, // UMIN_ZPZZ_UNDEF_B |
| 0U, // UMIN_ZPZZ_UNDEF_D |
| 0U, // UMIN_ZPZZ_UNDEF_H |
| 0U, // UMIN_ZPZZ_UNDEF_S |
| 0U, // UMLAL_MZZI_S_PSEUDO |
| 0U, // UMLAL_MZZ_S_PSEUDO |
| 0U, // UMLAL_VG2_M2Z2Z_S_PSEUDO |
| 0U, // UMLAL_VG2_M2ZZI_S_PSEUDO |
| 0U, // UMLAL_VG2_M2ZZ_S_PSEUDO |
| 0U, // UMLAL_VG4_M4Z4Z_S_PSEUDO |
| 0U, // UMLAL_VG4_M4ZZI_S_PSEUDO |
| 0U, // UMLAL_VG4_M4ZZ_S_PSEUDO |
| 0U, // UMLSL_MZZI_S_PSEUDO |
| 0U, // UMLSL_MZZ_S_PSEUDO |
| 0U, // UMLSL_VG2_M2Z2Z_S_PSEUDO |
| 0U, // UMLSL_VG2_M2ZZI_S_PSEUDO |
| 0U, // UMLSL_VG2_M2ZZ_S_PSEUDO |
| 0U, // UMLSL_VG4_M4Z4Z_S_PSEUDO |
| 0U, // UMLSL_VG4_M4ZZI_S_PSEUDO |
| 0U, // UMLSL_VG4_M4ZZ_S_PSEUDO |
| 0U, // UMOPA_MPPZZ_D_PSEUDO |
| 0U, // UMOPA_MPPZZ_S_PSEUDO |
| 0U, // UMOPS_MPPZZ_D_PSEUDO |
| 0U, // UMOPS_MPPZZ_S_PSEUDO |
| 0U, // UMULH_ZPZZ_UNDEF_B |
| 0U, // UMULH_ZPZZ_UNDEF_D |
| 0U, // UMULH_ZPZZ_UNDEF_H |
| 0U, // UMULH_ZPZZ_UNDEF_S |
| 0U, // UQRSHL_ZPZZ_UNDEF_B |
| 0U, // UQRSHL_ZPZZ_UNDEF_D |
| 0U, // UQRSHL_ZPZZ_UNDEF_H |
| 0U, // UQRSHL_ZPZZ_UNDEF_S |
| 0U, // UQSHL_ZPZI_ZERO_B |
| 0U, // UQSHL_ZPZI_ZERO_D |
| 0U, // UQSHL_ZPZI_ZERO_H |
| 0U, // UQSHL_ZPZI_ZERO_S |
| 0U, // UQSHL_ZPZZ_UNDEF_B |
| 0U, // UQSHL_ZPZZ_UNDEF_D |
| 0U, // UQSHL_ZPZZ_UNDEF_H |
| 0U, // UQSHL_ZPZZ_UNDEF_S |
| 0U, // URECPE_ZPmZ_UNDEF_S |
| 0U, // URSHL_ZPZZ_UNDEF_B |
| 0U, // URSHL_ZPZZ_UNDEF_D |
| 0U, // URSHL_ZPZZ_UNDEF_H |
| 0U, // URSHL_ZPZZ_UNDEF_S |
| 0U, // URSHR_ZPZI_ZERO_B |
| 0U, // URSHR_ZPZI_ZERO_D |
| 0U, // URSHR_ZPZI_ZERO_H |
| 0U, // URSHR_ZPZI_ZERO_S |
| 0U, // URSQRTE_ZPmZ_UNDEF_S |
| 0U, // USDOT_VG2_M2Z2Z_BToS_PSEUDO |
| 0U, // USDOT_VG2_M2ZZI_BToS_PSEUDO |
| 0U, // USDOT_VG4_M4Z4Z_BToS_PSEUDO |
| 0U, // USDOT_VG4_M4ZZI_BToS_PSEUDO |
| 0U, // USMOPA_MPPZZ_D_PSEUDO |
| 0U, // USMOPA_MPPZZ_S_PSEUDO |
| 0U, // USMOPS_MPPZZ_D_PSEUDO |
| 0U, // USMOPS_MPPZZ_S_PSEUDO |
| 0U, // USVDOT_VG4_M4ZZI_BToS_PSEUDO |
| 0U, // UVDOT_VG2_M2ZZI_HtoS_PSEUDO |
| 0U, // UVDOT_VG4_M4ZZI_BtoS_PSEUDO |
| 0U, // UVDOT_VG4_M4ZZI_HtoD_PSEUDO |
| 0U, // UXTB_ZPmZ_UNDEF_D |
| 0U, // UXTB_ZPmZ_UNDEF_H |
| 0U, // UXTB_ZPmZ_UNDEF_S |
| 0U, // UXTH_ZPmZ_UNDEF_D |
| 0U, // UXTH_ZPmZ_UNDEF_S |
| 0U, // UXTW_ZPmZ_UNDEF_D |
| 0U, // ZERO_M_PSEUDO |
| 0U, // ABSWr |
| 0U, // ABSXr |
| 16U, // ABS_ZPmZ_B |
| 32U, // ABS_ZPmZ_D |
| 0U, // ABS_ZPmZ_H |
| 48U, // ABS_ZPmZ_S |
| 0U, // ABSv16i8 |
| 0U, // ABSv1i64 |
| 0U, // ABSv2i32 |
| 0U, // ABSv2i64 |
| 0U, // ABSv4i16 |
| 0U, // ABSv4i32 |
| 0U, // ABSv8i16 |
| 0U, // ABSv8i8 |
| 2112U, // ADCLB_ZZZ_D |
| 4160U, // ADCLB_ZZZ_S |
| 2112U, // ADCLT_ZZZ_D |
| 4160U, // ADCLT_ZZZ_S |
| 6208U, // ADCSWr |
| 6208U, // ADCSXr |
| 6208U, // ADCWr |
| 6208U, // ADCXr |
| 270400U, // ADDG |
| 0U, // ADDHA_MPPZ_D |
| 0U, // ADDHA_MPPZ_S |
| 10304U, // ADDHNB_ZZZ_B |
| 81U, // ADDHNB_ZZZ_H |
| 12353U, // ADDHNB_ZZZ_S |
| 14401U, // ADDHNT_ZZZ_B |
| 49U, // ADDHNT_ZZZ_H |
| 2112U, // ADDHNT_ZZZ_S |
| 16448U, // ADDHNv2i64_v2i32 |
| 18497U, // ADDHNv2i64_v4i32 |
| 16448U, // ADDHNv4i32_v4i16 |
| 18497U, // ADDHNv4i32_v8i16 |
| 18497U, // ADDHNv8i16_v16i8 |
| 16448U, // ADDHNv8i16_v8i8 |
| 6208U, // ADDPL_XXI |
| 33837153U, // ADDP_ZPmZ_B |
| 67383393U, // ADDP_ZPmZ_D |
| 101210225U, // ADDP_ZPmZ_H |
| 134504545U, // ADDP_ZPmZ_S |
| 16448U, // ADDPv16i8 |
| 16448U, // ADDPv2i32 |
| 16448U, // ADDPv2i64 |
| 0U, // ADDPv2i64p |
| 16448U, // ADDPv4i16 |
| 16448U, // ADDPv4i32 |
| 16448U, // ADDPv8i16 |
| 16448U, // ADDPv8i8 |
| 20545U, // ADDQV_VPZ_B |
| 12353U, // ADDQV_VPZ_D |
| 10305U, // ADDQV_VPZ_H |
| 24641U, // ADDQV_VPZ_S |
| 6208U, // ADDSPL_XXI |
| 6208U, // ADDSVL_XXI |
| 26688U, // ADDSWri |
| 28736U, // ADDSWrs |
| 30784U, // ADDSWrx |
| 26688U, // ADDSXri |
| 28736U, // ADDSXrs |
| 30784U, // ADDSXrx |
| 792640U, // ADDSXrx64 |
| 0U, // ADDVA_MPPZ_D |
| 0U, // ADDVA_MPPZ_S |
| 6208U, // ADDVL_XXI |
| 0U, // ADDVv16i8v |
| 0U, // ADDVv4i16v |
| 0U, // ADDVv4i32v |
| 0U, // ADDVv8i16v |
| 0U, // ADDVv8i8v |
| 26688U, // ADDWri |
| 28736U, // ADDWrs |
| 30784U, // ADDWrx |
| 26688U, // ADDXri |
| 28736U, // ADDXrs |
| 30784U, // ADDXrx |
| 792640U, // ADDXrx64 |
| 129U, // ADD_VG2_2ZZ_B |
| 145U, // ADD_VG2_2ZZ_D |
| 113U, // ADD_VG2_2ZZ_H |
| 81U, // ADD_VG2_2ZZ_S |
| 1071265U, // ADD_VG2_M2Z2Z_D |
| 1333425U, // ADD_VG2_M2Z2Z_S |
| 102258849U, // ADD_VG2_M2ZZ_D |
| 102521009U, // ADD_VG2_M2ZZ_S |
| 161U, // ADD_VG2_M2Z_D |
| 177U, // ADD_VG2_M2Z_S |
| 129U, // ADD_VG4_4ZZ_B |
| 145U, // ADD_VG4_4ZZ_D |
| 113U, // ADD_VG4_4ZZ_H |
| 81U, // ADD_VG4_4ZZ_S |
| 1071265U, // ADD_VG4_M4Z4Z_D |
| 1333425U, // ADD_VG4_M4Z4Z_S |
| 102258849U, // ADD_VG4_M4ZZ_D |
| 102521009U, // ADD_VG4_M4ZZ_S |
| 161U, // ADD_VG4_M4Z_D |
| 177U, // ADD_VG4_M4Z_S |
| 32834U, // ADD_ZI_B |
| 34881U, // ADD_ZI_D |
| 193U, // ADD_ZI_H |
| 36930U, // ADD_ZI_S |
| 33837153U, // ADD_ZPmZ_B |
| 67383393U, // ADD_ZPmZ_D |
| 101210225U, // ADD_ZPmZ_H |
| 134504545U, // ADD_ZPmZ_S |
| 20546U, // ADD_ZZZ_B |
| 12353U, // ADD_ZZZ_D |
| 113U, // ADD_ZZZ_H |
| 24642U, // ADD_ZZZ_S |
| 16448U, // ADDv16i8 |
| 6208U, // ADDv1i64 |
| 16448U, // ADDv2i32 |
| 16448U, // ADDv2i64 |
| 16448U, // ADDv4i16 |
| 16448U, // ADDv4i32 |
| 16448U, // ADDv8i16 |
| 16448U, // ADDv8i8 |
| 0U, // ADR |
| 2U, // ADRP |
| 38977U, // ADR_LSL_ZZZ_D_0 |
| 41025U, // ADR_LSL_ZZZ_D_1 |
| 43073U, // ADR_LSL_ZZZ_D_2 |
| 45121U, // ADR_LSL_ZZZ_D_3 |
| 47170U, // ADR_LSL_ZZZ_S_0 |
| 49218U, // ADR_LSL_ZZZ_S_1 |
| 51266U, // ADR_LSL_ZZZ_S_2 |
| 53314U, // ADR_LSL_ZZZ_S_3 |
| 55361U, // ADR_SXTW_ZZZ_D_0 |
| 57409U, // ADR_SXTW_ZZZ_D_1 |
| 59457U, // ADR_SXTW_ZZZ_D_2 |
| 61505U, // ADR_SXTW_ZZZ_D_3 |
| 63553U, // ADR_UXTW_ZZZ_D_0 |
| 65601U, // ADR_UXTW_ZZZ_D_1 |
| 67649U, // ADR_UXTW_ZZZ_D_2 |
| 69697U, // ADR_UXTW_ZZZ_D_3 |
| 20546U, // AESD_ZZZ_B |
| 1U, // AESDrr |
| 20546U, // AESE_ZZZ_B |
| 1U, // AESErr |
| 2U, // AESIMC_ZZ_B |
| 0U, // AESIMCrr |
| 2U, // AESMC_ZZ_B |
| 0U, // AESMCrr |
| 20545U, // ANDQV_VPZ_B |
| 12353U, // ANDQV_VPZ_D |
| 10305U, // ANDQV_VPZ_H |
| 24641U, // ANDQV_VPZ_S |
| 71744U, // ANDSWri |
| 28736U, // ANDSWrs |
| 73792U, // ANDSXri |
| 28736U, // ANDSXrs |
| 33837265U, // ANDS_PPzPP |
| 0U, // ANDV_VPZ_B |
| 0U, // ANDV_VPZ_D |
| 0U, // ANDV_VPZ_H |
| 0U, // ANDV_VPZ_S |
| 71744U, // ANDWri |
| 28736U, // ANDWrs |
| 73792U, // ANDXri |
| 28736U, // ANDXrs |
| 33837265U, // AND_PPzPP |
| 73793U, // AND_ZI |
| 33837153U, // AND_ZPmZ_B |
| 67383393U, // AND_ZPmZ_D |
| 101210225U, // AND_ZPmZ_H |
| 134504545U, // AND_ZPmZ_S |
| 12353U, // AND_ZZZ |
| 16448U, // ANDv16i8 |
| 16448U, // ANDv8i8 |
| 282721U, // ASRD_ZPmI_B |
| 274529U, // ASRD_ZPmI_D |
| 102783089U, // ASRD_ZPmI_H |
| 286817U, // ASRD_ZPmI_S |
| 33837153U, // ASRR_ZPmZ_B |
| 67383393U, // ASRR_ZPmZ_D |
| 101210225U, // ASRR_ZPmZ_H |
| 134504545U, // ASRR_ZPmZ_S |
| 6208U, // ASRVWr |
| 6208U, // ASRVXr |
| 67391585U, // ASR_WIDE_ZPmZ_B |
| 2381937U, // ASR_WIDE_ZPmZ_H |
| 67395681U, // ASR_WIDE_ZPmZ_S |
| 12354U, // ASR_WIDE_ZZZ_B |
| 145U, // ASR_WIDE_ZZZ_H |
| 12354U, // ASR_WIDE_ZZZ_S |
| 282721U, // ASR_ZPmI_B |
| 274529U, // ASR_ZPmI_D |
| 102783089U, // ASR_ZPmI_H |
| 286817U, // ASR_ZPmI_S |
| 33837153U, // ASR_ZPmZ_B |
| 67383393U, // ASR_ZPmZ_D |
| 101210225U, // ASR_ZPmZ_H |
| 134504545U, // ASR_ZPmZ_S |
| 6210U, // ASR_ZZI_B |
| 6209U, // ASR_ZZI_D |
| 225U, // ASR_ZZI_H |
| 6210U, // ASR_ZZI_S |
| 2U, // AUTDA |
| 2U, // AUTDB |
| 0U, // AUTDZA |
| 0U, // AUTDZB |
| 2U, // AUTIA |
| 0U, // AUTIA1716 |
| 0U, // AUTIASP |
| 0U, // AUTIAZ |
| 2U, // AUTIB |
| 0U, // AUTIB1716 |
| 0U, // AUTIBSP |
| 0U, // AUTIBZ |
| 0U, // AUTIZA |
| 0U, // AUTIZB |
| 0U, // AXFLAG |
| 0U, // B |
| 168050752U, // BCAX |
| 67383361U, // BCAX_ZZZZ |
| 0U, // BCcc |
| 20546U, // BDEP_ZZZ_B |
| 12353U, // BDEP_ZZZ_D |
| 113U, // BDEP_ZZZ_H |
| 24642U, // BDEP_ZZZ_S |
| 20546U, // BEXT_ZZZ_B |
| 12353U, // BEXT_ZZZ_D |
| 113U, // BEXT_ZZZ_H |
| 24642U, // BEXT_ZZZ_S |
| 103303233U, // BF16DOTlanev4bf16 |
| 103303233U, // BF16DOTlanev8bf16 |
| 0U, // BFADD_VG2_M2Z_H |
| 0U, // BFADD_VG4_M4Z_H |
| 101210225U, // BFADD_ZPZmZ |
| 113U, // BFADD_ZZZ |
| 241U, // BFCLAMP_VG2_2ZZZ_H |
| 241U, // BFCLAMP_VG4_4ZZZ_H |
| 241U, // BFCLAMP_ZZZ |
| 0U, // BFCVT |
| 0U, // BFCVTN |
| 1U, // BFCVTN2 |
| 2U, // BFCVTNT_ZPmZ |
| 0U, // BFCVTN_Z2Z_StoH |
| 0U, // BFCVT_Z2Z_StoH |
| 2U, // BFCVT_ZPmZ |
| 76033U, // BFDOT_VG2_M2Z2Z_HtoS |
| 2961665U, // BFDOT_VG2_M2ZZI_HtoS |
| 78081U, // BFDOT_VG2_M2ZZ_HtoS |
| 76033U, // BFDOT_VG4_M4Z4Z_HtoS |
| 2961665U, // BFDOT_VG4_M4ZZI_HtoS |
| 78081U, // BFDOT_VG4_M4ZZ_HtoS |
| 103299137U, // BFDOT_ZZI |
| 14401U, // BFDOT_ZZZ |
| 0U, // BFDOTv4bf16 |
| 0U, // BFDOTv8bf16 |
| 273U, // BFMAXNM_VG2_2Z2Z_H |
| 113U, // BFMAXNM_VG2_2ZZ_H |
| 273U, // BFMAXNM_VG4_4Z2Z_H |
| 113U, // BFMAXNM_VG4_4ZZ_H |
| 101210225U, // BFMAXNM_ZPZmZ |
| 273U, // BFMAX_VG2_2Z2Z_H |
| 113U, // BFMAX_VG2_2ZZ_H |
| 273U, // BFMAX_VG4_4Z2Z_H |
| 113U, // BFMAX_VG4_4ZZ_H |
| 101210225U, // BFMAX_ZPZmZ |
| 273U, // BFMINNM_VG2_2Z2Z_H |
| 113U, // BFMINNM_VG2_2ZZ_H |
| 273U, // BFMINNM_VG4_4Z2Z_H |
| 113U, // BFMINNM_VG4_4ZZ_H |
| 101210225U, // BFMINNM_ZPZmZ |
| 273U, // BFMIN_VG2_2Z2Z_H |
| 113U, // BFMIN_VG2_2ZZ_H |
| 273U, // BFMIN_VG4_4Z2Z_H |
| 113U, // BFMIN_VG4_4ZZ_H |
| 101210225U, // BFMIN_ZPZmZ |
| 0U, // BFMLALB |
| 0U, // BFMLALBIdx |
| 14401U, // BFMLALB_ZZZ |
| 103299137U, // BFMLALB_ZZZI |
| 0U, // BFMLALT |
| 0U, // BFMLALTIdx |
| 14401U, // BFMLALT_ZZZ |
| 103299137U, // BFMLALT_ZZZI |
| 80162U, // BFMLAL_MZZI_S |
| 290U, // BFMLAL_MZZ_S |
| 76033U, // BFMLAL_VG2_M2Z2Z_S |
| 2961665U, // BFMLAL_VG2_M2ZZI_S |
| 78081U, // BFMLAL_VG2_M2ZZ_S |
| 76033U, // BFMLAL_VG4_M4Z4Z_S |
| 2961665U, // BFMLAL_VG4_M4ZZI_S |
| 78081U, // BFMLAL_VG4_M4ZZ_S |
| 305U, // BFMLA_VG2_M2Z2Z |
| 321U, // BFMLA_VG2_M2ZZ |
| 80193U, // BFMLA_VG2_M2ZZI |
| 305U, // BFMLA_VG4_M4Z4Z |
| 321U, // BFMLA_VG4_M4ZZ |
| 80193U, // BFMLA_VG4_M4ZZI |
| 103831793U, // BFMLA_ZPmZZ |
| 82161U, // BFMLA_ZZZI |
| 103299137U, // BFMLSLB_ZZZI_S |
| 14401U, // BFMLSLB_ZZZ_S |
| 103299137U, // BFMLSLT_ZZZI_S |
| 14401U, // BFMLSLT_ZZZ_S |
| 80162U, // BFMLSL_MZZI_S |
| 290U, // BFMLSL_MZZ_S |
| 76033U, // BFMLSL_VG2_M2Z2Z_S |
| 2961665U, // BFMLSL_VG2_M2ZZI_S |
| 78081U, // BFMLSL_VG2_M2ZZ_S |
| 76033U, // BFMLSL_VG4_M4Z4Z_S |
| 2961665U, // BFMLSL_VG4_M4ZZI_S |
| 78081U, // BFMLSL_VG4_M4ZZ_S |
| 305U, // BFMLS_VG2_M2Z2Z |
| 321U, // BFMLS_VG2_M2ZZ |
| 80193U, // BFMLS_VG2_M2ZZI |
| 305U, // BFMLS_VG4_M4Z4Z |
| 321U, // BFMLS_VG4_M4ZZ |
| 80193U, // BFMLS_VG4_M4ZZI |
| 103831793U, // BFMLS_ZPmZZ |
| 82161U, // BFMLS_ZZZI |
| 0U, // BFMMLA |
| 14401U, // BFMMLA_ZZZ |
| 0U, // BFMOPA_MPPZZ |
| 0U, // BFMOPA_MPPZZ_H |
| 0U, // BFMOPS_MPPZZ |
| 0U, // BFMOPS_MPPZZ_H |
| 101210225U, // BFMUL_ZPZmZ |
| 113U, // BFMUL_ZZZ |
| 84081U, // BFMUL_ZZZI |
| 201674818U, // BFMWri |
| 201674818U, // BFMXri |
| 0U, // BFSUB_VG2_M2Z_H |
| 0U, // BFSUB_VG4_M4Z_H |
| 101210225U, // BFSUB_ZPZmZ |
| 113U, // BFSUB_ZZZ |
| 2961665U, // BFVDOT_VG2_M2ZZI_HtoS |
| 20546U, // BGRP_ZZZ_B |
| 12353U, // BGRP_ZZZ_D |
| 113U, // BGRP_ZZZ_H |
| 24642U, // BGRP_ZZZ_S |
| 28736U, // BICSWrs |
| 28736U, // BICSXrs |
| 33837265U, // BICS_PPzPP |
| 28736U, // BICWrs |
| 28736U, // BICXrs |
| 33837265U, // BIC_PPzPP |
| 33837153U, // BIC_ZPmZ_B |
| 67383393U, // BIC_ZPmZ_D |
| 101210225U, // BIC_ZPmZ_H |
| 134504545U, // BIC_ZPmZ_S |
| 12353U, // BIC_ZZZ |
| 16448U, // BICv16i8 |
| 2U, // BICv2i32 |
| 2U, // BICv4i16 |
| 2U, // BICv4i32 |
| 2U, // BICv8i16 |
| 16448U, // BICv8i8 |
| 18497U, // BIFv16i8 |
| 18497U, // BIFv8i8 |
| 18497U, // BITv16i8 |
| 18497U, // BITv8i8 |
| 0U, // BL |
| 0U, // BLR |
| 0U, // BLRAA |
| 0U, // BLRAAZ |
| 0U, // BLRAB |
| 0U, // BLRABZ |
| 337U, // BMOPA_MPPZZ_S |
| 337U, // BMOPS_MPPZZ_S |
| 0U, // BR |
| 0U, // BRAA |
| 0U, // BRAAZ |
| 0U, // BRAB |
| 0U, // BRABZ |
| 0U, // BRB_IALL |
| 0U, // BRB_INJ |
| 0U, // BRK |
| 20689U, // BRKAS_PPzP |
| 16U, // BRKA_PPmP |
| 20689U, // BRKA_PPzP |
| 20689U, // BRKBS_PPzP |
| 16U, // BRKB_PPmP |
| 20689U, // BRKB_PPzP |
| 33837265U, // BRKNS_PPzP |
| 33837265U, // BRKN_PPzP |
| 33837265U, // BRKPAS_PPzPP |
| 33837265U, // BRKPA_PPzPP |
| 33837265U, // BRKPBS_PPzPP |
| 33837265U, // BRKPB_PPzPP |
| 67383361U, // BSL1N_ZZZZ |
| 67383361U, // BSL2N_ZZZZ |
| 67383361U, // BSL_ZZZZ |
| 18497U, // BSLv16i8 |
| 18497U, // BSLv8i8 |
| 0U, // Bcc |
| 235163714U, // CADD_ZZI_B |
| 235155521U, // CADD_ZZI_D |
| 3430513U, // CADD_ZZI_H |
| 235167810U, // CADD_ZZI_S |
| 3756386U, // CASAB |
| 3756386U, // CASAH |
| 3756386U, // CASALB |
| 3756386U, // CASALH |
| 3756386U, // CASALW |
| 3756386U, // CASALX |
| 3756386U, // CASAW |
| 3756386U, // CASAX |
| 3756386U, // CASB |
| 3756386U, // CASH |
| 3756386U, // CASLB |
| 3756386U, // CASLH |
| 3756386U, // CASLW |
| 3756386U, // CASLX |
| 0U, // CASPALW |
| 0U, // CASPALX |
| 0U, // CASPAW |
| 0U, // CASPAX |
| 0U, // CASPLW |
| 0U, // CASPLX |
| 0U, // CASPW |
| 0U, // CASPX |
| 3756386U, // CASW |
| 3756386U, // CASX |
| 2U, // CBNZW |
| 2U, // CBNZX |
| 2U, // CBZW |
| 2U, // CBZX |
| 268703808U, // CCMNWi |
| 268703808U, // CCMNWr |
| 268703808U, // CCMNXi |
| 268703808U, // CCMNXr |
| 268703808U, // CCMPWi |
| 268703808U, // CCMPWr |
| 268703808U, // CCMPXi |
| 268703808U, // CCMPXr |
| 304625729U, // CDOT_ZZZI_D |
| 335888403U, // CDOT_ZZZI_S |
| 369375297U, // CDOT_ZZZ_D |
| 3954707U, // CDOT_ZZZ_S |
| 0U, // CFINV |
| 33822785U, // CLASTA_RPZ_B |
| 67377217U, // CLASTA_RPZ_D |
| 402921537U, // CLASTA_RPZ_H |
| 134486081U, // CLASTA_RPZ_S |
| 33822785U, // CLASTA_VPZ_B |
| 67377217U, // CLASTA_VPZ_D |
| 402921537U, // CLASTA_VPZ_H |
| 134486081U, // CLASTA_VPZ_S |
| 33837121U, // CLASTA_ZPZ_B |
| 67383361U, // CLASTA_ZPZ_D |
| 101210225U, // CLASTA_ZPZ_H |
| 134504513U, // CLASTA_ZPZ_S |
| 33822785U, // CLASTB_RPZ_B |
| 67377217U, // CLASTB_RPZ_D |
| 402921537U, // CLASTB_RPZ_H |
| 134486081U, // CLASTB_RPZ_S |
| 33822785U, // CLASTB_VPZ_B |
| 67377217U, // CLASTB_VPZ_D |
| 402921537U, // CLASTB_VPZ_H |
| 134486081U, // CLASTB_VPZ_S |
| 33837121U, // CLASTB_ZPZ_B |
| 67383361U, // CLASTB_ZPZ_D |
| 101210225U, // CLASTB_ZPZ_H |
| 134504513U, // CLASTB_ZPZ_S |
| 0U, // CLREX |
| 0U, // CLSWr |
| 0U, // CLSXr |
| 16U, // CLS_ZPmZ_B |
| 32U, // CLS_ZPmZ_D |
| 0U, // CLS_ZPmZ_H |
| 48U, // CLS_ZPmZ_S |
| 0U, // CLSv16i8 |
| 0U, // CLSv2i32 |
| 0U, // CLSv4i16 |
| 0U, // CLSv4i32 |
| 0U, // CLSv8i16 |
| 0U, // CLSv8i8 |
| 0U, // CLZWr |
| 0U, // CLZXr |
| 16U, // CLZ_ZPmZ_B |
| 32U, // CLZ_ZPmZ_D |
| 0U, // CLZ_ZPmZ_H |
| 48U, // CLZ_ZPmZ_S |
| 0U, // CLZv16i8 |
| 0U, // CLZv2i32 |
| 0U, // CLZv4i16 |
| 0U, // CLZv4i32 |
| 0U, // CLZv8i16 |
| 0U, // CLZv8i8 |
| 16448U, // CMEQv16i8 |
| 368U, // CMEQv16i8rz |
| 6208U, // CMEQv1i64 |
| 368U, // CMEQv1i64rz |
| 16448U, // CMEQv2i32 |
| 368U, // CMEQv2i32rz |
| 16448U, // CMEQv2i64 |
| 368U, // CMEQv2i64rz |
| 16448U, // CMEQv4i16 |
| 368U, // CMEQv4i16rz |
| 16448U, // CMEQv4i32 |
| 368U, // CMEQv4i32rz |
| 16448U, // CMEQv8i16 |
| 368U, // CMEQv8i16rz |
| 16448U, // CMEQv8i8 |
| 368U, // CMEQv8i8rz |
| 16448U, // CMGEv16i8 |
| 368U, // CMGEv16i8rz |
| 6208U, // CMGEv1i64 |
| 368U, // CMGEv1i64rz |
| 16448U, // CMGEv2i32 |
| 368U, // CMGEv2i32rz |
| 16448U, // CMGEv2i64 |
| 368U, // CMGEv2i64rz |
| 16448U, // CMGEv4i16 |
| 368U, // CMGEv4i16rz |
| 16448U, // CMGEv4i32 |
| 368U, // CMGEv4i32rz |
| 16448U, // CMGEv8i16 |
| 368U, // CMGEv8i16rz |
| 16448U, // CMGEv8i8 |
| 368U, // CMGEv8i8rz |
| 16448U, // CMGTv16i8 |
| 368U, // CMGTv16i8rz |
| 6208U, // CMGTv1i64 |
| 368U, // CMGTv1i64rz |
| 16448U, // CMGTv2i32 |
| 368U, // CMGTv2i32rz |
| 16448U, // CMGTv2i64 |
| 368U, // CMGTv2i64rz |
| 16448U, // CMGTv4i16 |
| 368U, // CMGTv4i16rz |
| 16448U, // CMGTv4i32 |
| 368U, // CMGTv4i32rz |
| 16448U, // CMGTv8i16 |
| 368U, // CMGTv8i16rz |
| 16448U, // CMGTv8i8 |
| 368U, // CMGTv8i8rz |
| 16448U, // CMHIv16i8 |
| 6208U, // CMHIv1i64 |
| 16448U, // CMHIv2i32 |
| 16448U, // CMHIv2i64 |
| 16448U, // CMHIv4i16 |
| 16448U, // CMHIv4i32 |
| 16448U, // CMHIv8i16 |
| 16448U, // CMHIv8i8 |
| 16448U, // CMHSv16i8 |
| 6208U, // CMHSv1i64 |
| 16448U, // CMHSv2i32 |
| 16448U, // CMHSv2i64 |
| 16448U, // CMHSv4i16 |
| 16448U, // CMHSv4i32 |
| 16448U, // CMHSv8i16 |
| 16448U, // CMHSv8i8 |
| 335888625U, // CMLA_ZZZI_H |
| 304615488U, // CMLA_ZZZI_S |
| 3954707U, // CMLA_ZZZ_B |
| 369363008U, // CMLA_ZZZ_D |
| 3954929U, // CMLA_ZZZ_H |
| 369365056U, // CMLA_ZZZ_S |
| 368U, // CMLEv16i8rz |
| 368U, // CMLEv1i64rz |
| 368U, // CMLEv2i32rz |
| 368U, // CMLEv2i64rz |
| 368U, // CMLEv4i16rz |
| 368U, // CMLEv4i32rz |
| 368U, // CMLEv8i16rz |
| 368U, // CMLEv8i8rz |
| 368U, // CMLTv16i8rz |
| 368U, // CMLTv1i64rz |
| 368U, // CMLTv2i32rz |
| 368U, // CMLTv2i64rz |
| 368U, // CMLTv4i16rz |
| 368U, // CMLTv4i32rz |
| 368U, // CMLTv8i16rz |
| 368U, // CMLTv8i8rz |
| 282833U, // CMPEQ_PPzZI_B |
| 274641U, // CMPEQ_PPzZI_D |
| 102783091U, // CMPEQ_PPzZI_H |
| 286929U, // CMPEQ_PPzZI_S |
| 33837265U, // CMPEQ_PPzZZ_B |
| 67383505U, // CMPEQ_PPzZZ_D |
| 101210227U, // CMPEQ_PPzZZ_H |
| 134504657U, // CMPEQ_PPzZZ_S |
| 67391697U, // CMPEQ_WIDE_PPzZZ_B |
| 2381939U, // CMPEQ_WIDE_PPzZZ_H |
| 67395793U, // CMPEQ_WIDE_PPzZZ_S |
| 282833U, // CMPGE_PPzZI_B |
| 274641U, // CMPGE_PPzZI_D |
| 102783091U, // CMPGE_PPzZI_H |
| 286929U, // CMPGE_PPzZI_S |
| 33837265U, // CMPGE_PPzZZ_B |
| 67383505U, // CMPGE_PPzZZ_D |
| 101210227U, // CMPGE_PPzZZ_H |
| 134504657U, // CMPGE_PPzZZ_S |
| 67391697U, // CMPGE_WIDE_PPzZZ_B |
| 2381939U, // CMPGE_WIDE_PPzZZ_H |
| 67395793U, // CMPGE_WIDE_PPzZZ_S |
| 282833U, // CMPGT_PPzZI_B |
| 274641U, // CMPGT_PPzZI_D |
| 102783091U, // CMPGT_PPzZI_H |
| 286929U, // CMPGT_PPzZI_S |
| 33837265U, // CMPGT_PPzZZ_B |
| 67383505U, // CMPGT_PPzZZ_D |
| 101210227U, // CMPGT_PPzZZ_H |
| 134504657U, // CMPGT_PPzZZ_S |
| 67391697U, // CMPGT_WIDE_PPzZZ_B |
| 2381939U, // CMPGT_WIDE_PPzZZ_H |
| 67395793U, // CMPGT_WIDE_PPzZZ_S |
| 436490449U, // CMPHI_PPzZI_B |
| 436482257U, // CMPHI_PPzZI_D |
| 4216947U, // CMPHI_PPzZI_H |
| 436494545U, // CMPHI_PPzZI_S |
| 33837265U, // CMPHI_PPzZZ_B |
| 67383505U, // CMPHI_PPzZZ_D |
| 101210227U, // CMPHI_PPzZZ_H |
| 134504657U, // CMPHI_PPzZZ_S |
| 67391697U, // CMPHI_WIDE_PPzZZ_B |
| 2381939U, // CMPHI_WIDE_PPzZZ_H |
| 67395793U, // CMPHI_WIDE_PPzZZ_S |
| 436490449U, // CMPHS_PPzZI_B |
| 436482257U, // CMPHS_PPzZI_D |
| 4216947U, // CMPHS_PPzZI_H |
| 436494545U, // CMPHS_PPzZI_S |
| 33837265U, // CMPHS_PPzZZ_B |
| 67383505U, // CMPHS_PPzZZ_D |
| 101210227U, // CMPHS_PPzZZ_H |
| 134504657U, // CMPHS_PPzZZ_S |
| 67391697U, // CMPHS_WIDE_PPzZZ_B |
| 2381939U, // CMPHS_WIDE_PPzZZ_H |
| 67395793U, // CMPHS_WIDE_PPzZZ_S |
| 282833U, // CMPLE_PPzZI_B |
| 274641U, // CMPLE_PPzZI_D |
| 102783091U, // CMPLE_PPzZI_H |
| 286929U, // CMPLE_PPzZI_S |
| 67391697U, // CMPLE_WIDE_PPzZZ_B |
| 2381939U, // CMPLE_WIDE_PPzZZ_H |
| 67395793U, // CMPLE_WIDE_PPzZZ_S |
| 436490449U, // CMPLO_PPzZI_B |
| 436482257U, // CMPLO_PPzZI_D |
| 4216947U, // CMPLO_PPzZI_H |
| 436494545U, // CMPLO_PPzZI_S |
| 67391697U, // CMPLO_WIDE_PPzZZ_B |
| 2381939U, // CMPLO_WIDE_PPzZZ_H |
| 67395793U, // CMPLO_WIDE_PPzZZ_S |
| 436490449U, // CMPLS_PPzZI_B |
| 436482257U, // CMPLS_PPzZI_D |
| 4216947U, // CMPLS_PPzZI_H |
| 436494545U, // CMPLS_PPzZI_S |
| 67391697U, // CMPLS_WIDE_PPzZZ_B |
| 2381939U, // CMPLS_WIDE_PPzZZ_H |
| 67395793U, // CMPLS_WIDE_PPzZZ_S |
| 282833U, // CMPLT_PPzZI_B |
| 274641U, // CMPLT_PPzZI_D |
| 102783091U, // CMPLT_PPzZI_H |
| 286929U, // CMPLT_PPzZI_S |
| 67391697U, // CMPLT_WIDE_PPzZZ_B |
| 2381939U, // CMPLT_WIDE_PPzZZ_H |
| 67395793U, // CMPLT_WIDE_PPzZZ_S |
| 282833U, // CMPNE_PPzZI_B |
| 274641U, // CMPNE_PPzZI_D |
| 102783091U, // CMPNE_PPzZI_H |
| 286929U, // CMPNE_PPzZI_S |
| 33837265U, // CMPNE_PPzZZ_B |
| 67383505U, // CMPNE_PPzZZ_D |
| 101210227U, // CMPNE_PPzZZ_H |
| 134504657U, // CMPNE_PPzZZ_S |
| 67391697U, // CMPNE_WIDE_PPzZZ_B |
| 2381939U, // CMPNE_WIDE_PPzZZ_H |
| 67395793U, // CMPNE_WIDE_PPzZZ_S |
| 16448U, // CMTSTv16i8 |
| 6208U, // CMTSTv1i64 |
| 16448U, // CMTSTv2i32 |
| 16448U, // CMTSTv2i64 |
| 16448U, // CMTSTv4i16 |
| 16448U, // CMTSTv4i32 |
| 16448U, // CMTSTv8i16 |
| 16448U, // CMTSTv8i8 |
| 16U, // CNOT_ZPmZ_B |
| 32U, // CNOT_ZPmZ_D |
| 0U, // CNOT_ZPmZ_H |
| 48U, // CNOT_ZPmZ_S |
| 387U, // CNTB_XPiI |
| 387U, // CNTD_XPiI |
| 387U, // CNTH_XPiI |
| 3U, // CNTP_XCI_B |
| 3U, // CNTP_XCI_D |
| 3U, // CNTP_XCI_H |
| 3U, // CNTP_XCI_S |
| 20545U, // CNTP_XPP_B |
| 12353U, // CNTP_XPP_D |
| 10305U, // CNTP_XPP_H |
| 24641U, // CNTP_XPP_S |
| 387U, // CNTW_XPiI |
| 0U, // CNTWr |
| 0U, // CNTXr |
| 16U, // CNT_ZPmZ_B |
| 32U, // CNT_ZPmZ_D |
| 0U, // CNT_ZPmZ_H |
| 48U, // CNT_ZPmZ_S |
| 0U, // CNTv16i8 |
| 0U, // CNTv8i8 |
| 12353U, // COMPACT_ZPZ_D |
| 24641U, // COMPACT_ZPZ_S |
| 0U, // CPYE |
| 0U, // CPYEN |
| 0U, // CPYERN |
| 0U, // CPYERT |
| 0U, // CPYERTN |
| 0U, // CPYERTRN |
| 0U, // CPYERTWN |
| 0U, // CPYET |
| 0U, // CPYETN |
| 0U, // CPYETRN |
| 0U, // CPYETWN |
| 0U, // CPYEWN |
| 0U, // CPYEWT |
| 0U, // CPYEWTN |
| 0U, // CPYEWTRN |
| 0U, // CPYEWTWN |
| 0U, // CPYFE |
| 0U, // CPYFEN |
| 0U, // CPYFERN |
| 0U, // CPYFERT |
| 0U, // CPYFERTN |
| 0U, // CPYFERTRN |
| 0U, // CPYFERTWN |
| 0U, // CPYFET |
| 0U, // CPYFETN |
| 0U, // CPYFETRN |
| 0U, // CPYFETWN |
| 0U, // CPYFEWN |
| 0U, // CPYFEWT |
| 0U, // CPYFEWTN |
| 0U, // CPYFEWTRN |
| 0U, // CPYFEWTWN |
| 0U, // CPYFM |
| 0U, // CPYFMN |
| 0U, // CPYFMRN |
| 0U, // CPYFMRT |
| 0U, // CPYFMRTN |
| 0U, // CPYFMRTRN |
| 0U, // CPYFMRTWN |
| 0U, // CPYFMT |
| 0U, // CPYFMTN |
| 0U, // CPYFMTRN |
| 0U, // CPYFMTWN |
| 0U, // CPYFMWN |
| 0U, // CPYFMWT |
| 0U, // CPYFMWTN |
| 0U, // CPYFMWTRN |
| 0U, // CPYFMWTWN |
| 0U, // CPYFP |
| 0U, // CPYFPN |
| 0U, // CPYFPRN |
| 0U, // CPYFPRT |
| 0U, // CPYFPRTN |
| 0U, // CPYFPRTRN |
| 0U, // CPYFPRTWN |
| 0U, // CPYFPT |
| 0U, // CPYFPTN |
| 0U, // CPYFPTRN |
| 0U, // CPYFPTWN |
| 0U, // CPYFPWN |
| 0U, // CPYFPWT |
| 0U, // CPYFPWTN |
| 0U, // CPYFPWTRN |
| 0U, // CPYFPWTWN |
| 0U, // CPYM |
| 0U, // CPYMN |
| 0U, // CPYMRN |
| 0U, // CPYMRT |
| 0U, // CPYMRTN |
| 0U, // CPYMRTRN |
| 0U, // CPYMRTWN |
| 0U, // CPYMT |
| 0U, // CPYMTN |
| 0U, // CPYMTRN |
| 0U, // CPYMTWN |
| 0U, // CPYMWN |
| 0U, // CPYMWT |
| 0U, // CPYMWTN |
| 0U, // CPYMWTRN |
| 0U, // CPYMWTWN |
| 0U, // CPYP |
| 0U, // CPYPN |
| 0U, // CPYPRN |
| 0U, // CPYPRT |
| 0U, // CPYPRTN |
| 0U, // CPYPRTRN |
| 0U, // CPYPRTWN |
| 0U, // CPYPT |
| 0U, // CPYPTN |
| 0U, // CPYPTRN |
| 0U, // CPYPTWN |
| 0U, // CPYPWN |
| 0U, // CPYPWT |
| 0U, // CPYPWTN |
| 0U, // CPYPWTRN |
| 0U, // CPYPWTWN |
| 400U, // CPY_ZPmI_B |
| 416U, // CPY_ZPmI_D |
| 3U, // CPY_ZPmI_H |
| 432U, // CPY_ZPmI_S |
| 448U, // CPY_ZPmR_B |
| 448U, // CPY_ZPmR_D |
| 4U, // CPY_ZPmR_H |
| 448U, // CPY_ZPmR_S |
| 448U, // CPY_ZPmV_B |
| 448U, // CPY_ZPmV_D |
| 4U, // CPY_ZPmV_H |
| 448U, // CPY_ZPmV_S |
| 88273U, // CPY_ZPzI_B |
| 90321U, // CPY_ZPzI_D |
| 467U, // CPY_ZPzI_H |
| 92369U, // CPY_ZPzI_S |
| 6208U, // CRC32Brr |
| 6208U, // CRC32CBrr |
| 6208U, // CRC32CHrr |
| 6208U, // CRC32CWrr |
| 6208U, // CRC32CXrr |
| 6208U, // CRC32Hrr |
| 6208U, // CRC32Wrr |
| 6208U, // CRC32Xrr |
| 268703808U, // CSELWr |
| 268703808U, // CSELXr |
| 268703808U, // CSINCWr |
| 268703808U, // CSINCXr |
| 268703808U, // CSINVWr |
| 268703808U, // CSINVXr |
| 268703808U, // CSNEGWr |
| 268703808U, // CSNEGXr |
| 0U, // CTERMEQ_WW |
| 0U, // CTERMEQ_XX |
| 0U, // CTERMNE_WW |
| 0U, // CTERMNE_XX |
| 0U, // CTZWr |
| 0U, // CTZXr |
| 0U, // DCPS1 |
| 0U, // DCPS2 |
| 0U, // DCPS3 |
| 4U, // DECB_XPiI |
| 4U, // DECD_XPiI |
| 4U, // DECD_ZPiI |
| 4U, // DECH_XPiI |
| 0U, // DECH_ZPiI |
| 2U, // DECP_XP_B |
| 1U, // DECP_XP_D |
| 0U, // DECP_XP_H |
| 2U, // DECP_XP_S |
| 0U, // DECP_ZP_D |
| 0U, // DECP_ZP_H |
| 0U, // DECP_ZP_S |
| 4U, // DECW_XPiI |
| 4U, // DECW_ZPiI |
| 0U, // DMB |
| 0U, // DRPS |
| 0U, // DSB |
| 0U, // DSBnXS |
| 4U, // DUPM_ZI |
| 482U, // DUPQ_ZZI_B |
| 481U, // DUPQ_ZZI_D |
| 4U, // DUPQ_ZZI_H |
| 482U, // DUPQ_ZZI_S |
| 4U, // DUP_ZI_B |
| 4U, // DUP_ZI_D |
| 0U, // DUP_ZI_H |
| 4U, // DUP_ZI_S |
| 0U, // DUP_ZR_B |
| 0U, // DUP_ZR_D |
| 0U, // DUP_ZR_H |
| 0U, // DUP_ZR_S |
| 482U, // DUP_ZZI_B |
| 481U, // DUP_ZZI_D |
| 4U, // DUP_ZZI_H |
| 4U, // DUP_ZZI_Q |
| 482U, // DUP_ZZI_S |
| 480U, // DUPi16 |
| 480U, // DUPi32 |
| 480U, // DUPi64 |
| 480U, // DUPi8 |
| 0U, // DUPv16i8gpr |
| 480U, // DUPv16i8lane |
| 0U, // DUPv2i32gpr |
| 480U, // DUPv2i32lane |
| 0U, // DUPv2i64gpr |
| 480U, // DUPv2i64lane |
| 0U, // DUPv4i16gpr |
| 480U, // DUPv4i16lane |
| 0U, // DUPv4i32gpr |
| 480U, // DUPv4i32lane |
| 0U, // DUPv8i16gpr |
| 480U, // DUPv8i16lane |
| 0U, // DUPv8i8gpr |
| 480U, // DUPv8i8lane |
| 28736U, // EONWrs |
| 28736U, // EONXrs |
| 168050752U, // EOR3 |
| 67383361U, // EOR3_ZZZZ |
| 19U, // EORBT_ZZZ_B |
| 2112U, // EORBT_ZZZ_D |
| 241U, // EORBT_ZZZ_H |
| 4160U, // EORBT_ZZZ_S |
| 20545U, // EORQV_VPZ_B |
| 12353U, // EORQV_VPZ_D |
| 10305U, // EORQV_VPZ_H |
| 24641U, // EORQV_VPZ_S |
| 33837265U, // EORS_PPzPP |
| 19U, // EORTB_ZZZ_B |
| 2112U, // EORTB_ZZZ_D |
| 241U, // EORTB_ZZZ_H |
| 4160U, // EORTB_ZZZ_S |
| 0U, // EORV_VPZ_B |
| 0U, // EORV_VPZ_D |
| 0U, // EORV_VPZ_H |
| 0U, // EORV_VPZ_S |
| 71744U, // EORWri |
| 28736U, // EORWrs |
| 73792U, // EORXri |
| 28736U, // EORXrs |
| 33837265U, // EOR_PPzPP |
| 73793U, // EOR_ZI |
| 33837153U, // EOR_ZPmZ_B |
| 67383393U, // EOR_ZPmZ_D |
| 101210225U, // EOR_ZPmZ_H |
| 134504545U, // EOR_ZPmZ_S |
| 12353U, // EOR_ZZZ |
| 16448U, // EORv16i8 |
| 16448U, // EORv8i8 |
| 0U, // ERET |
| 0U, // ERETAA |
| 0U, // ERETAB |
| 282690U, // EXTQ_ZZI |
| 496U, // EXTRACT_ZPMXI_H_B |
| 496U, // EXTRACT_ZPMXI_H_D |
| 4U, // EXTRACT_ZPMXI_H_H |
| 4U, // EXTRACT_ZPMXI_H_Q |
| 496U, // EXTRACT_ZPMXI_H_S |
| 512U, // EXTRACT_ZPMXI_V_B |
| 512U, // EXTRACT_ZPMXI_V_D |
| 5U, // EXTRACT_ZPMXI_V_H |
| 5U, // EXTRACT_ZPMXI_V_Q |
| 512U, // EXTRACT_ZPMXI_V_S |
| 268352U, // EXTRWrri |
| 268352U, // EXTRXrri |
| 436490306U, // EXT_ZZI |
| 533U, // EXT_ZZI_B |
| 278592U, // EXTv16i8 |
| 278592U, // EXTv8i8 |
| 6208U, // FABD16 |
| 6208U, // FABD32 |
| 6208U, // FABD64 |
| 67383393U, // FABD_ZPmZ_D |
| 101210225U, // FABD_ZPmZ_H |
| 134504545U, // FABD_ZPmZ_S |
| 16448U, // FABDv2f32 |
| 16448U, // FABDv2f64 |
| 16448U, // FABDv4f16 |
| 16448U, // FABDv4f32 |
| 16448U, // FABDv8f16 |
| 0U, // FABSDr |
| 0U, // FABSHr |
| 0U, // FABSSr |
| 32U, // FABS_ZPmZ_D |
| 0U, // FABS_ZPmZ_H |
| 48U, // FABS_ZPmZ_S |
| 0U, // FABSv2f32 |
| 0U, // FABSv2f64 |
| 0U, // FABSv4f16 |
| 0U, // FABSv4f32 |
| 0U, // FABSv8f16 |
| 6208U, // FACGE16 |
| 6208U, // FACGE32 |
| 6208U, // FACGE64 |
| 67383505U, // FACGE_PPzZZ_D |
| 101210227U, // FACGE_PPzZZ_H |
| 134504657U, // FACGE_PPzZZ_S |
| 16448U, // FACGEv2f32 |
| 16448U, // FACGEv2f64 |
| 16448U, // FACGEv4f16 |
| 16448U, // FACGEv4f32 |
| 16448U, // FACGEv8f16 |
| 6208U, // FACGT16 |
| 6208U, // FACGT32 |
| 6208U, // FACGT64 |
| 67383505U, // FACGT_PPzZZ_D |
| 101210227U, // FACGT_PPzZZ_H |
| 134504657U, // FACGT_PPzZZ_S |
| 16448U, // FACGTv2f32 |
| 16448U, // FACGTv2f64 |
| 16448U, // FACGTv4f16 |
| 16448U, // FACGTv4f32 |
| 16448U, // FACGTv8f16 |
| 0U, // FADDA_VPZ_D |
| 241U, // FADDA_VPZ_H |
| 0U, // FADDA_VPZ_S |
| 6208U, // FADDDrr |
| 6208U, // FADDHrr |
| 67383393U, // FADDP_ZPmZZ_D |
| 101210225U, // FADDP_ZPmZZ_H |
| 134504545U, // FADDP_ZPmZZ_S |
| 16448U, // FADDPv2f32 |
| 16448U, // FADDPv2f64 |
| 0U, // FADDPv2i16p |
| 0U, // FADDPv2i32p |
| 0U, // FADDPv2i64p |
| 16448U, // FADDPv4f16 |
| 16448U, // FADDPv4f32 |
| 16448U, // FADDPv8f16 |
| 12353U, // FADDQV_D |
| 10305U, // FADDQV_H |
| 24641U, // FADDQV_S |
| 6208U, // FADDSrr |
| 0U, // FADDV_VPZ_D |
| 0U, // FADDV_VPZ_H |
| 0U, // FADDV_VPZ_S |
| 161U, // FADD_VG2_M2Z_D |
| 0U, // FADD_VG2_M2Z_H |
| 177U, // FADD_VG2_M2Z_S |
| 161U, // FADD_VG4_M4Z_D |
| 0U, // FADD_VG4_M4Z_H |
| 177U, // FADD_VG4_M4Z_S |
| 470036577U, // FADD_ZPmI_D |
| 4479089U, // FADD_ZPmI_H |
| 470048865U, // FADD_ZPmI_S |
| 67383393U, // FADD_ZPmZ_D |
| 101210225U, // FADD_ZPmZ_H |
| 134504545U, // FADD_ZPmZ_S |
| 12353U, // FADD_ZZZ_D |
| 113U, // FADD_ZZZ_H |
| 24642U, // FADD_ZZZ_S |
| 16448U, // FADDv2f32 |
| 16448U, // FADDv2f64 |
| 16448U, // FADDv4f16 |
| 16448U, // FADDv4f32 |
| 16448U, // FADDv8f16 |
| 67383393U, // FCADD_ZPmZ_D |
| 302536817U, // FCADD_ZPmZ_H |
| 134504545U, // FCADD_ZPmZ_S |
| 235159616U, // FCADDv2f32 |
| 235159616U, // FCADDv2f64 |
| 235159616U, // FCADDv4f16 |
| 235159616U, // FCADDv4f32 |
| 235159616U, // FCADDv8f16 |
| 268703808U, // FCCMPDrr |
| 268703808U, // FCCMPEDrr |
| 268703808U, // FCCMPEHrr |
| 268703808U, // FCCMPESrr |
| 268703808U, // FCCMPHrr |
| 268703808U, // FCCMPSrr |
| 33U, // FCLAMP_VG2_2Z2Z_D |
| 241U, // FCLAMP_VG2_2Z2Z_H |
| 49U, // FCLAMP_VG2_2Z2Z_S |
| 33U, // FCLAMP_VG4_4Z4Z_D |
| 241U, // FCLAMP_VG4_4Z4Z_H |
| 49U, // FCLAMP_VG4_4Z4Z_S |
| 2112U, // FCLAMP_ZZZ_D |
| 241U, // FCLAMP_ZZZ_H |
| 4160U, // FCLAMP_ZZZ_S |
| 6208U, // FCMEQ16 |
| 6208U, // FCMEQ32 |
| 6208U, // FCMEQ64 |
| 4731089U, // FCMEQ_PPzZ0_D |
| 94323U, // FCMEQ_PPzZ0_H |
| 4743377U, // FCMEQ_PPzZ0_S |
| 67383505U, // FCMEQ_PPzZZ_D |
| 101210227U, // FCMEQ_PPzZZ_H |
| 134504657U, // FCMEQ_PPzZZ_S |
| 544U, // FCMEQv1i16rz |
| 544U, // FCMEQv1i32rz |
| 544U, // FCMEQv1i64rz |
| 16448U, // FCMEQv2f32 |
| 16448U, // FCMEQv2f64 |
| 544U, // FCMEQv2i32rz |
| 544U, // FCMEQv2i64rz |
| 16448U, // FCMEQv4f16 |
| 16448U, // FCMEQv4f32 |
| 544U, // FCMEQv4i16rz |
| 544U, // FCMEQv4i32rz |
| 16448U, // FCMEQv8f16 |
| 544U, // FCMEQv8i16rz |
| 6208U, // FCMGE16 |
| 6208U, // FCMGE32 |
| 6208U, // FCMGE64 |
| 4731089U, // FCMGE_PPzZ0_D |
| 94323U, // FCMGE_PPzZ0_H |
| 4743377U, // FCMGE_PPzZ0_S |
| 67383505U, // FCMGE_PPzZZ_D |
| 101210227U, // FCMGE_PPzZZ_H |
| 134504657U, // FCMGE_PPzZZ_S |
| 544U, // FCMGEv1i16rz |
| 544U, // FCMGEv1i32rz |
| 544U, // FCMGEv1i64rz |
| 16448U, // FCMGEv2f32 |
| 16448U, // FCMGEv2f64 |
| 544U, // FCMGEv2i32rz |
| 544U, // FCMGEv2i64rz |
| 16448U, // FCMGEv4f16 |
| 16448U, // FCMGEv4f32 |
| 544U, // FCMGEv4i16rz |
| 544U, // FCMGEv4i32rz |
| 16448U, // FCMGEv8f16 |
| 544U, // FCMGEv8i16rz |
| 6208U, // FCMGT16 |
| 6208U, // FCMGT32 |
| 6208U, // FCMGT64 |
| 4731089U, // FCMGT_PPzZ0_D |
| 94323U, // FCMGT_PPzZ0_H |
| 4743377U, // FCMGT_PPzZ0_S |
| 67383505U, // FCMGT_PPzZZ_D |
| 101210227U, // FCMGT_PPzZZ_H |
| 134504657U, // FCMGT_PPzZZ_S |
| 544U, // FCMGTv1i16rz |
| 544U, // FCMGTv1i32rz |
| 544U, // FCMGTv1i64rz |
| 16448U, // FCMGTv2f32 |
| 16448U, // FCMGTv2f64 |
| 544U, // FCMGTv2i32rz |
| 544U, // FCMGTv2i64rz |
| 16448U, // FCMGTv4f16 |
| 16448U, // FCMGTv4f32 |
| 544U, // FCMGTv4i16rz |
| 544U, // FCMGTv4i32rz |
| 16448U, // FCMGTv8f16 |
| 544U, // FCMGTv8i16rz |
| 503580769U, // FCMLA_ZPmZZ_D |
| 305158385U, // FCMLA_ZPmZZ_H |
| 537137249U, // FCMLA_ZPmZZ_S |
| 335888625U, // FCMLA_ZZZI_H |
| 304615488U, // FCMLA_ZZZI_S |
| 369379393U, // FCMLAv2f32 |
| 369379393U, // FCMLAv2f64 |
| 369379393U, // FCMLAv4f16 |
| 304629825U, // FCMLAv4f16_indexed |
| 369379393U, // FCMLAv4f32 |
| 304629825U, // FCMLAv4f32_indexed |
| 369379393U, // FCMLAv8f16 |
| 304629825U, // FCMLAv8f16_indexed |
| 4731089U, // FCMLE_PPzZ0_D |
| 94323U, // FCMLE_PPzZ0_H |
| 4743377U, // FCMLE_PPzZ0_S |
| 544U, // FCMLEv1i16rz |
| 544U, // FCMLEv1i32rz |
| 544U, // FCMLEv1i64rz |
| 544U, // FCMLEv2i32rz |
| 544U, // FCMLEv2i64rz |
| 544U, // FCMLEv4i16rz |
| 544U, // FCMLEv4i32rz |
| 544U, // FCMLEv8i16rz |
| 4731089U, // FCMLT_PPzZ0_D |
| 94323U, // FCMLT_PPzZ0_H |
| 4743377U, // FCMLT_PPzZ0_S |
| 544U, // FCMLTv1i16rz |
| 544U, // FCMLTv1i32rz |
| 544U, // FCMLTv1i64rz |
| 544U, // FCMLTv2i32rz |
| 544U, // FCMLTv2i64rz |
| 544U, // FCMLTv4i16rz |
| 544U, // FCMLTv4i32rz |
| 544U, // FCMLTv8i16rz |
| 4731089U, // FCMNE_PPzZ0_D |
| 94323U, // FCMNE_PPzZ0_H |
| 4743377U, // FCMNE_PPzZ0_S |
| 67383505U, // FCMNE_PPzZZ_D |
| 101210227U, // FCMNE_PPzZZ_H |
| 134504657U, // FCMNE_PPzZZ_S |
| 0U, // FCMPDri |
| 0U, // FCMPDrr |
| 0U, // FCMPEDri |
| 0U, // FCMPEDrr |
| 0U, // FCMPEHri |
| 0U, // FCMPEHrr |
| 0U, // FCMPESri |
| 0U, // FCMPESrr |
| 0U, // FCMPHri |
| 0U, // FCMPHrr |
| 0U, // FCMPSri |
| 0U, // FCMPSrr |
| 67383505U, // FCMUO_PPzZZ_D |
| 101210227U, // FCMUO_PPzZZ_H |
| 134504657U, // FCMUO_PPzZZ_S |
| 560U, // FCPY_ZPmI_D |
| 5U, // FCPY_ZPmI_H |
| 560U, // FCPY_ZPmI_S |
| 268703808U, // FCSELDrrr |
| 268703808U, // FCSELHrrr |
| 268703808U, // FCSELSrrr |
| 0U, // FCVTASUWDr |
| 0U, // FCVTASUWHr |
| 0U, // FCVTASUWSr |
| 0U, // FCVTASUXDr |
| 0U, // FCVTASUXHr |
| 0U, // FCVTASUXSr |
| 0U, // FCVTASv1f16 |
| 0U, // FCVTASv1i32 |
| 0U, // FCVTASv1i64 |
| 0U, // FCVTASv2f32 |
| 0U, // FCVTASv2f64 |
| 0U, // FCVTASv4f16 |
| 0U, // FCVTASv4f32 |
| 0U, // FCVTASv8f16 |
| 0U, // FCVTAUUWDr |
| 0U, // FCVTAUUWHr |
| 0U, // FCVTAUUWSr |
| 0U, // FCVTAUUXDr |
| 0U, // FCVTAUUXHr |
| 0U, // FCVTAUUXSr |
| 0U, // FCVTAUv1f16 |
| 0U, // FCVTAUv1i32 |
| 0U, // FCVTAUv1i64 |
| 0U, // FCVTAUv2f32 |
| 0U, // FCVTAUv2f64 |
| 0U, // FCVTAUv4f16 |
| 0U, // FCVTAUv4f32 |
| 0U, // FCVTAUv8f16 |
| 0U, // FCVTDHr |
| 0U, // FCVTDSr |
| 0U, // FCVTHDr |
| 0U, // FCVTHSr |
| 240U, // FCVTLT_ZPmZ_HtoS |
| 48U, // FCVTLT_ZPmZ_StoD |
| 0U, // FCVTL_2ZZ_H_S |
| 576U, // FCVTLv2i32 |
| 592U, // FCVTLv4i16 |
| 608U, // FCVTLv4i32 |
| 624U, // FCVTLv8i16 |
| 0U, // FCVTMSUWDr |
| 0U, // FCVTMSUWHr |
| 0U, // FCVTMSUWSr |
| 0U, // FCVTMSUXDr |
| 0U, // FCVTMSUXHr |
| 0U, // FCVTMSUXSr |
| 0U, // FCVTMSv1f16 |
| 0U, // FCVTMSv1i32 |
| 0U, // FCVTMSv1i64 |
| 0U, // FCVTMSv2f32 |
| 0U, // FCVTMSv2f64 |
| 0U, // FCVTMSv4f16 |
| 0U, // FCVTMSv4f32 |
| 0U, // FCVTMSv8f16 |
| 0U, // FCVTMUUWDr |
| 0U, // FCVTMUUWHr |
| 0U, // FCVTMUUWSr |
| 0U, // FCVTMUUXDr |
| 0U, // FCVTMUUXHr |
| 0U, // FCVTMUUXSr |
| 0U, // FCVTMUv1f16 |
| 0U, // FCVTMUv1i32 |
| 0U, // FCVTMUv1i64 |
| 0U, // FCVTMUv2f32 |
| 0U, // FCVTMUv2f64 |
| 0U, // FCVTMUv4f16 |
| 0U, // FCVTMUv4f32 |
| 0U, // FCVTMUv8f16 |
| 0U, // FCVTNSUWDr |
| 0U, // FCVTNSUWHr |
| 0U, // FCVTNSUWSr |
| 0U, // FCVTNSUXDr |
| 0U, // FCVTNSUXHr |
| 0U, // FCVTNSUXSr |
| 0U, // FCVTNSv1f16 |
| 0U, // FCVTNSv1i32 |
| 0U, // FCVTNSv1i64 |
| 0U, // FCVTNSv2f32 |
| 0U, // FCVTNSv2f64 |
| 0U, // FCVTNSv4f16 |
| 0U, // FCVTNSv4f32 |
| 0U, // FCVTNSv8f16 |
| 32U, // FCVTNT_ZPmZ_DtoS |
| 2U, // FCVTNT_ZPmZ_StoH |
| 0U, // FCVTNUUWDr |
| 0U, // FCVTNUUWHr |
| 0U, // FCVTNUUWSr |
| 0U, // FCVTNUUXDr |
| 0U, // FCVTNUUXHr |
| 0U, // FCVTNUUXSr |
| 0U, // FCVTNUv1f16 |
| 0U, // FCVTNUv1i32 |
| 0U, // FCVTNUv1i64 |
| 0U, // FCVTNUv2f32 |
| 0U, // FCVTNUv2f64 |
| 0U, // FCVTNUv4f16 |
| 0U, // FCVTNUv4f32 |
| 0U, // FCVTNUv8f16 |
| 0U, // FCVTN_Z2Z_StoH |
| 0U, // FCVTNv2i32 |
| 0U, // FCVTNv4i16 |
| 641U, // FCVTNv4i32 |
| 609U, // FCVTNv8i16 |
| 0U, // FCVTPSUWDr |
| 0U, // FCVTPSUWHr |
| 0U, // FCVTPSUWSr |
| 0U, // FCVTPSUXDr |
| 0U, // FCVTPSUXHr |
| 0U, // FCVTPSUXSr |
| 0U, // FCVTPSv1f16 |
| 0U, // FCVTPSv1i32 |
| 0U, // FCVTPSv1i64 |
| 0U, // FCVTPSv2f32 |
| 0U, // FCVTPSv2f64 |
| 0U, // FCVTPSv4f16 |
| 0U, // FCVTPSv4f32 |
| 0U, // FCVTPSv8f16 |
| 0U, // FCVTPUUWDr |
| 0U, // FCVTPUUWHr |
| 0U, // FCVTPUUWSr |
| 0U, // FCVTPUUXDr |
| 0U, // FCVTPUUXHr |
| 0U, // FCVTPUUXSr |
| 0U, // FCVTPUv1f16 |
| 0U, // FCVTPUv1i32 |
| 0U, // FCVTPUv1i64 |
| 0U, // FCVTPUv2f32 |
| 0U, // FCVTPUv2f64 |
| 0U, // FCVTPUv4f16 |
| 0U, // FCVTPUv4f32 |
| 0U, // FCVTPUv8f16 |
| 0U, // FCVTSDr |
| 0U, // FCVTSHr |
| 32U, // FCVTXNT_ZPmZ_DtoS |
| 0U, // FCVTXNv1i64 |
| 0U, // FCVTXNv2f32 |
| 641U, // FCVTXNv4f32 |
| 32U, // FCVTX_ZPmZ_DtoS |
| 6208U, // FCVTZSSWDri |
| 6208U, // FCVTZSSWHri |
| 6208U, // FCVTZSSWSri |
| 6208U, // FCVTZSSXDri |
| 6208U, // FCVTZSSXHri |
| 6208U, // FCVTZSSXSri |
| 0U, // FCVTZSUWDr |
| 0U, // FCVTZSUWHr |
| 0U, // FCVTZSUWSr |
| 0U, // FCVTZSUXDr |
| 0U, // FCVTZSUXHr |
| 0U, // FCVTZSUXSr |
| 0U, // FCVTZS_2Z2Z_StoS |
| 0U, // FCVTZS_4Z4Z_StoS |
| 32U, // FCVTZS_ZPmZ_DtoD |
| 32U, // FCVTZS_ZPmZ_DtoS |
| 240U, // FCVTZS_ZPmZ_HtoD |
| 0U, // FCVTZS_ZPmZ_HtoH |
| 240U, // FCVTZS_ZPmZ_HtoS |
| 48U, // FCVTZS_ZPmZ_StoD |
| 48U, // FCVTZS_ZPmZ_StoS |
| 6208U, // FCVTZSd |
| 6208U, // FCVTZSh |
| 6208U, // FCVTZSs |
| 0U, // FCVTZSv1f16 |
| 0U, // FCVTZSv1i32 |
| 0U, // FCVTZSv1i64 |
| 0U, // FCVTZSv2f32 |
| 0U, // FCVTZSv2f64 |
| 6208U, // FCVTZSv2i32_shift |
| 6208U, // FCVTZSv2i64_shift |
| 0U, // FCVTZSv4f16 |
| 0U, // FCVTZSv4f32 |
| 6208U, // FCVTZSv4i16_shift |
| 6208U, // FCVTZSv4i32_shift |
| 0U, // FCVTZSv8f16 |
| 6208U, // FCVTZSv8i16_shift |
| 6208U, // FCVTZUSWDri |
| 6208U, // FCVTZUSWHri |
| 6208U, // FCVTZUSWSri |
| 6208U, // FCVTZUSXDri |
| 6208U, // FCVTZUSXHri |
| 6208U, // FCVTZUSXSri |
| 0U, // FCVTZUUWDr |
| 0U, // FCVTZUUWHr |
| 0U, // FCVTZUUWSr |
| 0U, // FCVTZUUXDr |
| 0U, // FCVTZUUXHr |
| 0U, // FCVTZUUXSr |
| 0U, // FCVTZU_2Z2Z_StoS |
| 0U, // FCVTZU_4Z4Z_StoS |
| 32U, // FCVTZU_ZPmZ_DtoD |
| 32U, // FCVTZU_ZPmZ_DtoS |
| 240U, // FCVTZU_ZPmZ_HtoD |
| 0U, // FCVTZU_ZPmZ_HtoH |
| 240U, // FCVTZU_ZPmZ_HtoS |
| 48U, // FCVTZU_ZPmZ_StoD |
| 48U, // FCVTZU_ZPmZ_StoS |
| 6208U, // FCVTZUd |
| 6208U, // FCVTZUh |
| 6208U, // FCVTZUs |
| 0U, // FCVTZUv1f16 |
| 0U, // FCVTZUv1i32 |
| 0U, // FCVTZUv1i64 |
| 0U, // FCVTZUv2f32 |
| 0U, // FCVTZUv2f64 |
| 6208U, // FCVTZUv2i32_shift |
| 6208U, // FCVTZUv2i64_shift |
| 0U, // FCVTZUv4f16 |
| 0U, // FCVTZUv4f32 |
| 6208U, // FCVTZUv4i16_shift |
| 6208U, // FCVTZUv4i32_shift |
| 0U, // FCVTZUv8f16 |
| 6208U, // FCVTZUv8i16_shift |
| 0U, // FCVT_2ZZ_H_S |
| 0U, // FCVT_Z2Z_StoH |
| 5U, // FCVT_ZPmZ_DtoH |
| 32U, // FCVT_ZPmZ_DtoS |
| 240U, // FCVT_ZPmZ_HtoD |
| 240U, // FCVT_ZPmZ_HtoS |
| 48U, // FCVT_ZPmZ_StoD |
| 2U, // FCVT_ZPmZ_StoH |
| 6208U, // FDIVDrr |
| 6208U, // FDIVHrr |
| 67383393U, // FDIVR_ZPmZ_D |
| 101210225U, // FDIVR_ZPmZ_H |
| 134504545U, // FDIVR_ZPmZ_S |
| 6208U, // FDIVSrr |
| 67383393U, // FDIV_ZPmZ_D |
| 101210225U, // FDIV_ZPmZ_H |
| 134504545U, // FDIV_ZPmZ_S |
| 16448U, // FDIVv2f32 |
| 16448U, // FDIVv2f64 |
| 16448U, // FDIVv4f16 |
| 16448U, // FDIVv4f32 |
| 16448U, // FDIVv8f16 |
| 76033U, // FDOT_VG2_M2Z2Z_HtoS |
| 2961665U, // FDOT_VG2_M2ZZI_HtoS |
| 78081U, // FDOT_VG2_M2ZZ_HtoS |
| 76033U, // FDOT_VG4_M4Z4Z_HtoS |
| 2961665U, // FDOT_VG4_M4ZZI_HtoS |
| 78081U, // FDOT_VG4_M4ZZ_HtoS |
| 103299137U, // FDOT_ZZZI_S |
| 14401U, // FDOT_ZZZ_S |
| 5U, // FDUP_ZI_D |
| 0U, // FDUP_ZI_H |
| 5U, // FDUP_ZI_S |
| 1U, // FEXPA_ZZ_D |
| 0U, // FEXPA_ZZ_H |
| 2U, // FEXPA_ZZ_S |
| 0U, // FJCVTZS |
| 32U, // FLOGB_ZPmZ_D |
| 0U, // FLOGB_ZPmZ_H |
| 48U, // FLOGB_ZPmZ_S |
| 268352U, // FMADDDrrr |
| 268352U, // FMADDHrrr |
| 268352U, // FMADDSrrr |
| 503580769U, // FMAD_ZPmZZ_D |
| 103831793U, // FMAD_ZPmZZ_H |
| 537137249U, // FMAD_ZPmZZ_S |
| 6208U, // FMAXDrr |
| 6208U, // FMAXHrr |
| 6208U, // FMAXNMDrr |
| 6208U, // FMAXNMHrr |
| 67383393U, // FMAXNMP_ZPmZZ_D |
| 101210225U, // FMAXNMP_ZPmZZ_H |
| 134504545U, // FMAXNMP_ZPmZZ_S |
| 16448U, // FMAXNMPv2f32 |
| 16448U, // FMAXNMPv2f64 |
| 0U, // FMAXNMPv2i16p |
| 0U, // FMAXNMPv2i32p |
| 0U, // FMAXNMPv2i64p |
| 16448U, // FMAXNMPv4f16 |
| 16448U, // FMAXNMPv4f32 |
| 16448U, // FMAXNMPv8f16 |
| 12353U, // FMAXNMQV_D |
| 10305U, // FMAXNMQV_H |
| 24641U, // FMAXNMQV_S |
| 6208U, // FMAXNMSrr |
| 0U, // FMAXNMV_VPZ_D |
| 0U, // FMAXNMV_VPZ_H |
| 0U, // FMAXNMV_VPZ_S |
| 0U, // FMAXNMVv4i16v |
| 0U, // FMAXNMVv4i32v |
| 0U, // FMAXNMVv8i16v |
| 657U, // FMAXNM_VG2_2Z2Z_D |
| 273U, // FMAXNM_VG2_2Z2Z_H |
| 673U, // FMAXNM_VG2_2Z2Z_S |
| 145U, // FMAXNM_VG2_2ZZ_D |
| 113U, // FMAXNM_VG2_2ZZ_H |
| 81U, // FMAXNM_VG2_2ZZ_S |
| 657U, // FMAXNM_VG4_4Z4Z_D |
| 273U, // FMAXNM_VG4_4Z4Z_H |
| 673U, // FMAXNM_VG4_4Z4Z_S |
| 145U, // FMAXNM_VG4_4ZZ_D |
| 113U, // FMAXNM_VG4_4ZZ_H |
| 81U, // FMAXNM_VG4_4ZZ_S |
| 570699873U, // FMAXNM_ZPmI_D |
| 5003377U, // FMAXNM_ZPmI_H |
| 570712161U, // FMAXNM_ZPmI_S |
| 67383393U, // FMAXNM_ZPmZ_D |
| 101210225U, // FMAXNM_ZPmZ_H |
| 134504545U, // FMAXNM_ZPmZ_S |
| 16448U, // FMAXNMv2f32 |
| 16448U, // FMAXNMv2f64 |
| 16448U, // FMAXNMv4f16 |
| 16448U, // FMAXNMv4f32 |
| 16448U, // FMAXNMv8f16 |
| 67383393U, // FMAXP_ZPmZZ_D |
| 101210225U, // FMAXP_ZPmZZ_H |
| 134504545U, // FMAXP_ZPmZZ_S |
| 16448U, // FMAXPv2f32 |
| 16448U, // FMAXPv2f64 |
| 0U, // FMAXPv2i16p |
| 0U, // FMAXPv2i32p |
| 0U, // FMAXPv2i64p |
| 16448U, // FMAXPv4f16 |
| 16448U, // FMAXPv4f32 |
| 16448U, // FMAXPv8f16 |
| 12353U, // FMAXQV_D |
| 10305U, // FMAXQV_H |
| 24641U, // FMAXQV_S |
| 6208U, // FMAXSrr |
| 0U, // FMAXV_VPZ_D |
| 0U, // FMAXV_VPZ_H |
| 0U, // FMAXV_VPZ_S |
| 0U, // FMAXVv4i16v |
| 0U, // FMAXVv4i32v |
| 0U, // FMAXVv8i16v |
| 657U, // FMAX_VG2_2Z2Z_D |
| 273U, // FMAX_VG2_2Z2Z_H |
| 673U, // FMAX_VG2_2Z2Z_S |
| 145U, // FMAX_VG2_2ZZ_D |
| 113U, // FMAX_VG2_2ZZ_H |
| 81U, // FMAX_VG2_2ZZ_S |
| 657U, // FMAX_VG4_4Z4Z_D |
| 273U, // FMAX_VG4_4Z4Z_H |
| 673U, // FMAX_VG4_4Z4Z_S |
| 145U, // FMAX_VG4_4ZZ_D |
| 113U, // FMAX_VG4_4ZZ_H |
| 81U, // FMAX_VG4_4ZZ_S |
| 570699873U, // FMAX_ZPmI_D |
| 5003377U, // FMAX_ZPmI_H |
| 570712161U, // FMAX_ZPmI_S |
| 67383393U, // FMAX_ZPmZ_D |
| 101210225U, // FMAX_ZPmZ_H |
| 134504545U, // FMAX_ZPmZ_S |
| 16448U, // FMAXv2f32 |
| 16448U, // FMAXv2f64 |
| 16448U, // FMAXv4f16 |
| 16448U, // FMAXv4f32 |
| 16448U, // FMAXv8f16 |
| 6208U, // FMINDrr |
| 6208U, // FMINHrr |
| 6208U, // FMINNMDrr |
| 6208U, // FMINNMHrr |
| 67383393U, // FMINNMP_ZPmZZ_D |
| 101210225U, // FMINNMP_ZPmZZ_H |
| 134504545U, // FMINNMP_ZPmZZ_S |
| 16448U, // FMINNMPv2f32 |
| 16448U, // FMINNMPv2f64 |
| 0U, // FMINNMPv2i16p |
| 0U, // FMINNMPv2i32p |
| 0U, // FMINNMPv2i64p |
| 16448U, // FMINNMPv4f16 |
| 16448U, // FMINNMPv4f32 |
| 16448U, // FMINNMPv8f16 |
| 12353U, // FMINNMQV_D |
| 10305U, // FMINNMQV_H |
| 24641U, // FMINNMQV_S |
| 6208U, // FMINNMSrr |
| 0U, // FMINNMV_VPZ_D |
| 0U, // FMINNMV_VPZ_H |
| 0U, // FMINNMV_VPZ_S |
| 0U, // FMINNMVv4i16v |
| 0U, // FMINNMVv4i32v |
| 0U, // FMINNMVv8i16v |
| 657U, // FMINNM_VG2_2Z2Z_D |
| 273U, // FMINNM_VG2_2Z2Z_H |
| 673U, // FMINNM_VG2_2Z2Z_S |
| 145U, // FMINNM_VG2_2ZZ_D |
| 113U, // FMINNM_VG2_2ZZ_H |
| 81U, // FMINNM_VG2_2ZZ_S |
| 657U, // FMINNM_VG4_4Z4Z_D |
| 273U, // FMINNM_VG4_4Z4Z_H |
| 673U, // FMINNM_VG4_4Z4Z_S |
| 145U, // FMINNM_VG4_4ZZ_D |
| 113U, // FMINNM_VG4_4ZZ_H |
| 81U, // FMINNM_VG4_4ZZ_S |
| 570699873U, // FMINNM_ZPmI_D |
| 5003377U, // FMINNM_ZPmI_H |
| 570712161U, // FMINNM_ZPmI_S |
| 67383393U, // FMINNM_ZPmZ_D |
| 101210225U, // FMINNM_ZPmZ_H |
| 134504545U, // FMINNM_ZPmZ_S |
| 16448U, // FMINNMv2f32 |
| 16448U, // FMINNMv2f64 |
| 16448U, // FMINNMv4f16 |
| 16448U, // FMINNMv4f32 |
| 16448U, // FMINNMv8f16 |
| 67383393U, // FMINP_ZPmZZ_D |
| 101210225U, // FMINP_ZPmZZ_H |
| 134504545U, // FMINP_ZPmZZ_S |
| 16448U, // FMINPv2f32 |
| 16448U, // FMINPv2f64 |
| 0U, // FMINPv2i16p |
| 0U, // FMINPv2i32p |
| 0U, // FMINPv2i64p |
| 16448U, // FMINPv4f16 |
| 16448U, // FMINPv4f32 |
| 16448U, // FMINPv8f16 |
| 12353U, // FMINQV_D |
| 10305U, // FMINQV_H |
| 24641U, // FMINQV_S |
| 6208U, // FMINSrr |
| 0U, // FMINV_VPZ_D |
| 0U, // FMINV_VPZ_H |
| 0U, // FMINV_VPZ_S |
| 0U, // FMINVv4i16v |
| 0U, // FMINVv4i32v |
| 0U, // FMINVv8i16v |
| 657U, // FMIN_VG2_2Z2Z_D |
| 273U, // FMIN_VG2_2Z2Z_H |
| 673U, // FMIN_VG2_2Z2Z_S |
| 145U, // FMIN_VG2_2ZZ_D |
| 113U, // FMIN_VG2_2ZZ_H |
| 81U, // FMIN_VG2_2ZZ_S |
| 657U, // FMIN_VG4_4Z4Z_D |
| 273U, // FMIN_VG4_4Z4Z_H |
| 673U, // FMIN_VG4_4Z4Z_S |
| 145U, // FMIN_VG4_4ZZ_D |
| 113U, // FMIN_VG4_4ZZ_H |
| 81U, // FMIN_VG4_4ZZ_S |
| 570699873U, // FMIN_ZPmI_D |
| 5003377U, // FMIN_ZPmI_H |
| 570712161U, // FMIN_ZPmI_S |
| 67383393U, // FMIN_ZPmZ_D |
| 101210225U, // FMIN_ZPmZ_H |
| 134504545U, // FMIN_ZPmZ_S |
| 16448U, // FMINv2f32 |
| 16448U, // FMINv2f64 |
| 16448U, // FMINv4f16 |
| 16448U, // FMINv4f32 |
| 16448U, // FMINv8f16 |
| 103303233U, // FMLAL2lanev4f16 |
| 103303233U, // FMLAL2lanev8f16 |
| 0U, // FMLAL2v4f16 |
| 0U, // FMLAL2v8f16 |
| 103299137U, // FMLALB_ZZZI_SHH |
| 14401U, // FMLALB_ZZZ_SHH |
| 103299137U, // FMLALT_ZZZI_SHH |
| 14401U, // FMLALT_ZZZ_SHH |
| 80162U, // FMLAL_MZZI_S |
| 290U, // FMLAL_MZZ_S |
| 76033U, // FMLAL_VG2_M2Z2Z_S |
| 2961665U, // FMLAL_VG2_M2ZZI_S |
| 78081U, // FMLAL_VG2_M2ZZ_S |
| 76033U, // FMLAL_VG4_M4Z4Z_S |
| 2961665U, // FMLAL_VG4_M4ZZI_S |
| 78081U, // FMLAL_VG4_M4ZZ_S |
| 103303233U, // FMLALlanev4f16 |
| 103303233U, // FMLALlanev8f16 |
| 0U, // FMLALv4f16 |
| 0U, // FMLALv8f16 |
| 1071265U, // FMLA_VG2_M2Z2Z_D |
| 1333425U, // FMLA_VG2_M2Z2Z_S |
| 305U, // FMLA_VG2_M2Z4Z_H |
| 605575329U, // FMLA_VG2_M2ZZI_D |
| 80193U, // FMLA_VG2_M2ZZI_H |
| 605837489U, // FMLA_VG2_M2ZZI_S |
| 102258849U, // FMLA_VG2_M2ZZ_D |
| 321U, // FMLA_VG2_M2ZZ_H |
| 102521009U, // FMLA_VG2_M2ZZ_S |
| 1071265U, // FMLA_VG4_M4Z4Z_D |
| 305U, // FMLA_VG4_M4Z4Z_H |
| 1333425U, // FMLA_VG4_M4Z4Z_S |
| 605575329U, // FMLA_VG4_M4ZZI_D |
| 80193U, // FMLA_VG4_M4ZZI_H |
| 605837489U, // FMLA_VG4_M4ZZI_S |
| 102258849U, // FMLA_VG4_M4ZZ_D |
| 321U, // FMLA_VG4_M4ZZ_H |
| 102521009U, // FMLA_VG4_M4ZZ_S |
| 503580769U, // FMLA_ZPmZZ_D |
| 103831793U, // FMLA_ZPmZZ_H |
| 537137249U, // FMLA_ZPmZZ_S |
| 103286848U, // FMLA_ZZZI_D |
| 82161U, // FMLA_ZZZI_H |
| 103288896U, // FMLA_ZZZI_S |
| 103303234U, // FMLAv1i16_indexed |
| 103303234U, // FMLAv1i32_indexed |
| 103303234U, // FMLAv1i64_indexed |
| 18497U, // FMLAv2f32 |
| 18497U, // FMLAv2f64 |
| 103303233U, // FMLAv2i32_indexed |
| 103303233U, // FMLAv2i64_indexed |
| 18497U, // FMLAv4f16 |
| 18497U, // FMLAv4f32 |
| 103303233U, // FMLAv4i16_indexed |
| 103303233U, // FMLAv4i32_indexed |
| 18497U, // FMLAv8f16 |
| 103303233U, // FMLAv8i16_indexed |
| 103303233U, // FMLSL2lanev4f16 |
| 103303233U, // FMLSL2lanev8f16 |
| 0U, // FMLSL2v4f16 |
| 0U, // FMLSL2v8f16 |
| 103299137U, // FMLSLB_ZZZI_SHH |
| 14401U, // FMLSLB_ZZZ_SHH |
| 103299137U, // FMLSLT_ZZZI_SHH |
| 14401U, // FMLSLT_ZZZ_SHH |
| 80162U, // FMLSL_MZZI_S |
| 290U, // FMLSL_MZZ_S |
| 76033U, // FMLSL_VG2_M2Z2Z_S |
| 2961665U, // FMLSL_VG2_M2ZZI_S |
| 78081U, // FMLSL_VG2_M2ZZ_S |
| 76033U, // FMLSL_VG4_M4Z4Z_S |
| 2961665U, // FMLSL_VG4_M4ZZI_S |
| 78081U, // FMLSL_VG4_M4ZZ_S |
| 103303233U, // FMLSLlanev4f16 |
| 103303233U, // FMLSLlanev8f16 |
| 0U, // FMLSLv4f16 |
| 0U, // FMLSLv8f16 |
| 1071265U, // FMLS_VG2_M2Z2Z_D |
| 305U, // FMLS_VG2_M2Z2Z_H |
| 1333425U, // FMLS_VG2_M2Z2Z_S |
| 605575329U, // FMLS_VG2_M2ZZI_D |
| 80193U, // FMLS_VG2_M2ZZI_H |
| 605837489U, // FMLS_VG2_M2ZZI_S |
| 102258849U, // FMLS_VG2_M2ZZ_D |
| 321U, // FMLS_VG2_M2ZZ_H |
| 102521009U, // FMLS_VG2_M2ZZ_S |
| 305U, // FMLS_VG4_M4Z2Z_H |
| 1071265U, // FMLS_VG4_M4Z4Z_D |
| 1333425U, // FMLS_VG4_M4Z4Z_S |
| 605575329U, // FMLS_VG4_M4ZZI_D |
| 80193U, // FMLS_VG4_M4ZZI_H |
| 605837489U, // FMLS_VG4_M4ZZI_S |
| 102258849U, // FMLS_VG4_M4ZZ_D |
| 321U, // FMLS_VG4_M4ZZ_H |
| 102521009U, // FMLS_VG4_M4ZZ_S |
| 503580769U, // FMLS_ZPmZZ_D |
| 103831793U, // FMLS_ZPmZZ_H |
| 537137249U, // FMLS_ZPmZZ_S |
| 103286848U, // FMLS_ZZZI_D |
| 82161U, // FMLS_ZZZI_H |
| 103288896U, // FMLS_ZZZI_S |
| 103303234U, // FMLSv1i16_indexed |
| 103303234U, // FMLSv1i32_indexed |
| 103303234U, // FMLSv1i64_indexed |
| 18497U, // FMLSv2f32 |
| 18497U, // FMLSv2f64 |
| 103303233U, // FMLSv2i32_indexed |
| 103303233U, // FMLSv2i64_indexed |
| 18497U, // FMLSv4f16 |
| 18497U, // FMLSv4f32 |
| 103303233U, // FMLSv4i16_indexed |
| 103303233U, // FMLSv4i32_indexed |
| 18497U, // FMLSv8f16 |
| 103303233U, // FMLSv8i16_indexed |
| 2112U, // FMMLA_ZZZ_D |
| 4160U, // FMMLA_ZZZ_S |
| 0U, // FMOPAL_MPPZZ |
| 689U, // FMOPA_MPPZZ_D |
| 0U, // FMOPA_MPPZZ_H |
| 337U, // FMOPA_MPPZZ_S |
| 0U, // FMOPSL_MPPZZ |
| 689U, // FMOPS_MPPZZ_D |
| 0U, // FMOPS_MPPZZ_H |
| 337U, // FMOPS_MPPZZ_S |
| 480U, // FMOVDXHighr |
| 0U, // FMOVDXr |
| 5U, // FMOVDi |
| 0U, // FMOVDr |
| 0U, // FMOVHWr |
| 0U, // FMOVHXr |
| 5U, // FMOVHi |
| 0U, // FMOVHr |
| 0U, // FMOVSWr |
| 5U, // FMOVSi |
| 0U, // FMOVSr |
| 0U, // FMOVWHr |
| 0U, // FMOVWSr |
| 0U, // FMOVXDHighr |
| 0U, // FMOVXDr |
| 0U, // FMOVXHr |
| 5U, // FMOVv2f32_ns |
| 5U, // FMOVv2f64_ns |
| 5U, // FMOVv4f16_ns |
| 5U, // FMOVv4f32_ns |
| 5U, // FMOVv8f16_ns |
| 503580769U, // FMSB_ZPmZZ_D |
| 103831793U, // FMSB_ZPmZZ_H |
| 537137249U, // FMSB_ZPmZZ_S |
| 268352U, // FMSUBDrrr |
| 268352U, // FMSUBHrrr |
| 268352U, // FMSUBSrrr |
| 6208U, // FMULDrr |
| 6208U, // FMULHrr |
| 6208U, // FMULSrr |
| 6208U, // FMULX16 |
| 6208U, // FMULX32 |
| 6208U, // FMULX64 |
| 67383393U, // FMULX_ZPmZ_D |
| 101210225U, // FMULX_ZPmZ_H |
| 134504545U, // FMULX_ZPmZ_S |
| 5259328U, // FMULXv1i16_indexed |
| 5259328U, // FMULXv1i32_indexed |
| 5259328U, // FMULXv1i64_indexed |
| 16448U, // FMULXv2f32 |
| 16448U, // FMULXv2f64 |
| 5259328U, // FMULXv2i32_indexed |
| 5259328U, // FMULXv2i64_indexed |
| 16448U, // FMULXv4f16 |
| 16448U, // FMULXv4f32 |
| 5259328U, // FMULXv4i16_indexed |
| 5259328U, // FMULXv4i32_indexed |
| 16448U, // FMULXv8f16 |
| 5259328U, // FMULXv8i16_indexed |
| 637808737U, // FMUL_ZPmI_D |
| 5527665U, // FMUL_ZPmI_H |
| 637821025U, // FMUL_ZPmI_S |
| 67383393U, // FMUL_ZPmZ_D |
| 101210225U, // FMUL_ZPmZ_H |
| 134504545U, // FMUL_ZPmZ_S |
| 5255233U, // FMUL_ZZZI_D |
| 84081U, // FMUL_ZZZI_H |
| 5267522U, // FMUL_ZZZI_S |
| 12353U, // FMUL_ZZZ_D |
| 113U, // FMUL_ZZZ_H |
| 24642U, // FMUL_ZZZ_S |
| 5259328U, // FMULv1i16_indexed |
| 5259328U, // FMULv1i32_indexed |
| 5259328U, // FMULv1i64_indexed |
| 16448U, // FMULv2f32 |
| 16448U, // FMULv2f64 |
| 5259328U, // FMULv2i32_indexed |
| 5259328U, // FMULv2i64_indexed |
| 16448U, // FMULv4f16 |
| 16448U, // FMULv4f32 |
| 5259328U, // FMULv4i16_indexed |
| 5259328U, // FMULv4i32_indexed |
| 16448U, // FMULv8f16 |
| 5259328U, // FMULv8i16_indexed |
| 0U, // FNEGDr |
| 0U, // FNEGHr |
| 0U, // FNEGSr |
| 32U, // FNEG_ZPmZ_D |
| 0U, // FNEG_ZPmZ_H |
| 48U, // FNEG_ZPmZ_S |
| 0U, // FNEGv2f32 |
| 0U, // FNEGv2f64 |
| 0U, // FNEGv4f16 |
| 0U, // FNEGv4f32 |
| 0U, // FNEGv8f16 |
| 268352U, // FNMADDDrrr |
| 268352U, // FNMADDHrrr |
| 268352U, // FNMADDSrrr |
| 503580769U, // FNMAD_ZPmZZ_D |
| 103831793U, // FNMAD_ZPmZZ_H |
| 537137249U, // FNMAD_ZPmZZ_S |
| 503580769U, // FNMLA_ZPmZZ_D |
| 103831793U, // FNMLA_ZPmZZ_H |
| 537137249U, // FNMLA_ZPmZZ_S |
| 503580769U, // FNMLS_ZPmZZ_D |
| 103831793U, // FNMLS_ZPmZZ_H |
| 537137249U, // FNMLS_ZPmZZ_S |
| 503580769U, // FNMSB_ZPmZZ_D |
| 103831793U, // FNMSB_ZPmZZ_H |
| 537137249U, // FNMSB_ZPmZZ_S |
| 268352U, // FNMSUBDrrr |
| 268352U, // FNMSUBHrrr |
| 268352U, // FNMSUBSrrr |
| 6208U, // FNMULDrr |
| 6208U, // FNMULHrr |
| 6208U, // FNMULSrr |
| 1U, // FRECPE_ZZ_D |
| 0U, // FRECPE_ZZ_H |
| 2U, // FRECPE_ZZ_S |
| 0U, // FRECPEv1f16 |
| 0U, // FRECPEv1i32 |
| 0U, // FRECPEv1i64 |
| 0U, // FRECPEv2f32 |
| 0U, // FRECPEv2f64 |
| 0U, // FRECPEv4f16 |
| 0U, // FRECPEv4f32 |
| 0U, // FRECPEv8f16 |
| 6208U, // FRECPS16 |
| 6208U, // FRECPS32 |
| 6208U, // FRECPS64 |
| 12353U, // FRECPS_ZZZ_D |
| 113U, // FRECPS_ZZZ_H |
| 24642U, // FRECPS_ZZZ_S |
| 16448U, // FRECPSv2f32 |
| 16448U, // FRECPSv2f64 |
| 16448U, // FRECPSv4f16 |
| 16448U, // FRECPSv4f32 |
| 16448U, // FRECPSv8f16 |
| 32U, // FRECPX_ZPmZ_D |
| 0U, // FRECPX_ZPmZ_H |
| 48U, // FRECPX_ZPmZ_S |
| 0U, // FRECPXv1f16 |
| 0U, // FRECPXv1i32 |
| 0U, // FRECPXv1i64 |
| 0U, // FRINT32XDr |
| 0U, // FRINT32XSr |
| 0U, // FRINT32Xv2f32 |
| 0U, // FRINT32Xv2f64 |
| 0U, // FRINT32Xv4f32 |
| 0U, // FRINT32ZDr |
| 0U, // FRINT32ZSr |
| 0U, // FRINT32Zv2f32 |
| 0U, // FRINT32Zv2f64 |
| 0U, // FRINT32Zv4f32 |
| 0U, // FRINT64XDr |
| 0U, // FRINT64XSr |
| 0U, // FRINT64Xv2f32 |
| 0U, // FRINT64Xv2f64 |
| 0U, // FRINT64Xv4f32 |
| 0U, // FRINT64ZDr |
| 0U, // FRINT64ZSr |
| 0U, // FRINT64Zv2f32 |
| 0U, // FRINT64Zv2f64 |
| 0U, // FRINT64Zv4f32 |
| 0U, // FRINTADr |
| 0U, // FRINTAHr |
| 0U, // FRINTASr |
| 0U, // FRINTA_2Z2Z_S |
| 0U, // FRINTA_4Z4Z_S |
| 32U, // FRINTA_ZPmZ_D |
| 0U, // FRINTA_ZPmZ_H |
| 48U, // FRINTA_ZPmZ_S |
| 0U, // FRINTAv2f32 |
| 0U, // FRINTAv2f64 |
| 0U, // FRINTAv4f16 |
| 0U, // FRINTAv4f32 |
| 0U, // FRINTAv8f16 |
| 0U, // FRINTIDr |
| 0U, // FRINTIHr |
| 0U, // FRINTISr |
| 32U, // FRINTI_ZPmZ_D |
| 0U, // FRINTI_ZPmZ_H |
| 48U, // FRINTI_ZPmZ_S |
| 0U, // FRINTIv2f32 |
| 0U, // FRINTIv2f64 |
| 0U, // FRINTIv4f16 |
| 0U, // FRINTIv4f32 |
| 0U, // FRINTIv8f16 |
| 0U, // FRINTMDr |
| 0U, // FRINTMHr |
| 0U, // FRINTMSr |
| 0U, // FRINTM_2Z2Z_S |
| 0U, // FRINTM_4Z4Z_S |
| 32U, // FRINTM_ZPmZ_D |
| 0U, // FRINTM_ZPmZ_H |
| 48U, // FRINTM_ZPmZ_S |
| 0U, // FRINTMv2f32 |
| 0U, // FRINTMv2f64 |
| 0U, // FRINTMv4f16 |
| 0U, // FRINTMv4f32 |
| 0U, // FRINTMv8f16 |
| 0U, // FRINTNDr |
| 0U, // FRINTNHr |
| 0U, // FRINTNSr |
| 0U, // FRINTN_2Z2Z_S |
| 0U, // FRINTN_4Z4Z_S |
| 32U, // FRINTN_ZPmZ_D |
| 0U, // FRINTN_ZPmZ_H |
| 48U, // FRINTN_ZPmZ_S |
| 0U, // FRINTNv2f32 |
| 0U, // FRINTNv2f64 |
| 0U, // FRINTNv4f16 |
| 0U, // FRINTNv4f32 |
| 0U, // FRINTNv8f16 |
| 0U, // FRINTPDr |
| 0U, // FRINTPHr |
| 0U, // FRINTPSr |
| 0U, // FRINTP_2Z2Z_S |
| 0U, // FRINTP_4Z4Z_S |
| 32U, // FRINTP_ZPmZ_D |
| 0U, // FRINTP_ZPmZ_H |
| 48U, // FRINTP_ZPmZ_S |
| 0U, // FRINTPv2f32 |
| 0U, // FRINTPv2f64 |
| 0U, // FRINTPv4f16 |
| 0U, // FRINTPv4f32 |
| 0U, // FRINTPv8f16 |
| 0U, // FRINTXDr |
| 0U, // FRINTXHr |
| 0U, // FRINTXSr |
| 32U, // FRINTX_ZPmZ_D |
| 0U, // FRINTX_ZPmZ_H |
| 48U, // FRINTX_ZPmZ_S |
| 0U, // FRINTXv2f32 |
| 0U, // FRINTXv2f64 |
| 0U, // FRINTXv4f16 |
| 0U, // FRINTXv4f32 |
| 0U, // FRINTXv8f16 |
| 0U, // FRINTZDr |
| 0U, // FRINTZHr |
| 0U, // FRINTZSr |
| 32U, // FRINTZ_ZPmZ_D |
| 0U, // FRINTZ_ZPmZ_H |
| 48U, // FRINTZ_ZPmZ_S |
| 0U, // FRINTZv2f32 |
| 0U, // FRINTZv2f64 |
| 0U, // FRINTZv4f16 |
| 0U, // FRINTZv4f32 |
| 0U, // FRINTZv8f16 |
| 1U, // FRSQRTE_ZZ_D |
| 0U, // FRSQRTE_ZZ_H |
| 2U, // FRSQRTE_ZZ_S |
| 0U, // FRSQRTEv1f16 |
| 0U, // FRSQRTEv1i32 |
| 0U, // FRSQRTEv1i64 |
| 0U, // FRSQRTEv2f32 |
| 0U, // FRSQRTEv2f64 |
| 0U, // FRSQRTEv4f16 |
| 0U, // FRSQRTEv4f32 |
| 0U, // FRSQRTEv8f16 |
| 6208U, // FRSQRTS16 |
| 6208U, // FRSQRTS32 |
| 6208U, // FRSQRTS64 |
| 12353U, // FRSQRTS_ZZZ_D |
| 113U, // FRSQRTS_ZZZ_H |
| 24642U, // FRSQRTS_ZZZ_S |
| 16448U, // FRSQRTSv2f32 |
| 16448U, // FRSQRTSv2f64 |
| 16448U, // FRSQRTSv4f16 |
| 16448U, // FRSQRTSv4f32 |
| 16448U, // FRSQRTSv8f16 |
| 67383393U, // FSCALE_ZPmZ_D |
| 101210225U, // FSCALE_ZPmZ_H |
| 134504545U, // FSCALE_ZPmZ_S |
| 0U, // FSQRTDr |
| 0U, // FSQRTHr |
| 0U, // FSQRTSr |
| 32U, // FSQRT_ZPmZ_D |
| 0U, // FSQRT_ZPmZ_H |
| 48U, // FSQRT_ZPmZ_S |
| 0U, // FSQRTv2f32 |
| 0U, // FSQRTv2f64 |
| 0U, // FSQRTv4f16 |
| 0U, // FSQRTv4f32 |
| 0U, // FSQRTv8f16 |
| 6208U, // FSUBDrr |
| 6208U, // FSUBHrr |
| 470036577U, // FSUBR_ZPmI_D |
| 4479089U, // FSUBR_ZPmI_H |
| 470048865U, // FSUBR_ZPmI_S |
| 67383393U, // FSUBR_ZPmZ_D |
| 101210225U, // FSUBR_ZPmZ_H |
| 134504545U, // FSUBR_ZPmZ_S |
| 6208U, // FSUBSrr |
| 161U, // FSUB_VG2_M2Z_D |
| 0U, // FSUB_VG2_M2Z_H |
| 177U, // FSUB_VG2_M2Z_S |
| 161U, // FSUB_VG4_M4Z_D |
| 0U, // FSUB_VG4_M4Z_H |
| 177U, // FSUB_VG4_M4Z_S |
| 470036577U, // FSUB_ZPmI_D |
| 4479089U, // FSUB_ZPmI_H |
| 470048865U, // FSUB_ZPmI_S |
| 67383393U, // FSUB_ZPmZ_D |
| 101210225U, // FSUB_ZPmZ_H |
| 134504545U, // FSUB_ZPmZ_S |
| 12353U, // FSUB_ZZZ_D |
| 113U, // FSUB_ZZZ_H |
| 24642U, // FSUB_ZZZ_S |
| 16448U, // FSUBv2f32 |
| 16448U, // FSUBv2f64 |
| 16448U, // FSUBv4f16 |
| 16448U, // FSUBv4f32 |
| 16448U, // FSUBv8f16 |
| 274497U, // FTMAD_ZZI_D |
| 102783089U, // FTMAD_ZZI_H |
| 286786U, // FTMAD_ZZI_S |
| 12353U, // FTSMUL_ZZZ_D |
| 113U, // FTSMUL_ZZZ_H |
| 24642U, // FTSMUL_ZZZ_S |
| 12353U, // FTSSEL_ZZZ_D |
| 113U, // FTSSEL_ZZZ_H |
| 24642U, // FTSSEL_ZZZ_S |
| 2961665U, // FVDOT_VG2_M2ZZI_HtoS |
| 673208469U, // GLD1B_D_IMM_REAL |
| 5789925U, // GLD1B_D_REAL |
| 6052069U, // GLD1B_D_SXTW_REAL |
| 6314213U, // GLD1B_D_UXTW_REAL |
| 673208405U, // GLD1B_S_IMM_REAL |
| 6576357U, // GLD1B_S_SXTW_REAL |
| 6838501U, // GLD1B_S_UXTW_REAL |
| 7100565U, // GLD1D_IMM_REAL |
| 5789925U, // GLD1D_REAL |
| 7362789U, // GLD1D_SCALED_REAL |
| 6052069U, // GLD1D_SXTW_REAL |
| 7624933U, // GLD1D_SXTW_SCALED_REAL |
| 6314213U, // GLD1D_UXTW_REAL |
| 7887077U, // GLD1D_UXTW_SCALED_REAL |
| 679237781U, // GLD1H_D_IMM_REAL |
| 5789925U, // GLD1H_D_REAL |
| 8411365U, // GLD1H_D_SCALED_REAL |
| 6052069U, // GLD1H_D_SXTW_REAL |
| 8673509U, // GLD1H_D_SXTW_SCALED_REAL |
| 6314213U, // GLD1H_D_UXTW_REAL |
| 8935653U, // GLD1H_D_UXTW_SCALED_REAL |
| 679237717U, // GLD1H_S_IMM_REAL |
| 6576357U, // GLD1H_S_SXTW_REAL |
| 9197797U, // GLD1H_S_SXTW_SCALED_REAL |
| 6838501U, // GLD1H_S_UXTW_REAL |
| 9459941U, // GLD1H_S_UXTW_SCALED_REAL |
| 673208469U, // GLD1Q |
| 673208469U, // GLD1SB_D_IMM_REAL |
| 5789925U, // GLD1SB_D_REAL |
| 6052069U, // GLD1SB_D_SXTW_REAL |
| 6314213U, // GLD1SB_D_UXTW_REAL |
| 673208405U, // GLD1SB_S_IMM_REAL |
| 6576357U, // GLD1SB_S_SXTW_REAL |
| 6838501U, // GLD1SB_S_UXTW_REAL |
| 679237781U, // GLD1SH_D_IMM_REAL |
| 5789925U, // GLD1SH_D_REAL |
| 8411365U, // GLD1SH_D_SCALED_REAL |
| 6052069U, // GLD1SH_D_SXTW_REAL |
| 8673509U, // GLD1SH_D_SXTW_SCALED_REAL |
| 6314213U, // GLD1SH_D_UXTW_REAL |
| 8935653U, // GLD1SH_D_UXTW_SCALED_REAL |
| 679237717U, // GLD1SH_S_IMM_REAL |
| 6576357U, // GLD1SH_S_SXTW_REAL |
| 9197797U, // GLD1SH_S_SXTW_SCALED_REAL |
| 6838501U, // GLD1SH_S_UXTW_REAL |
| 9459941U, // GLD1SH_S_UXTW_SCALED_REAL |
| 680810645U, // GLD1SW_D_IMM_REAL |
| 5789925U, // GLD1SW_D_REAL |
| 9984229U, // GLD1SW_D_SCALED_REAL |
| 6052069U, // GLD1SW_D_SXTW_REAL |
| 10246373U, // GLD1SW_D_SXTW_SCALED_REAL |
| 6314213U, // GLD1SW_D_UXTW_REAL |
| 10508517U, // GLD1SW_D_UXTW_SCALED_REAL |
| 680810645U, // GLD1W_D_IMM_REAL |
| 5789925U, // GLD1W_D_REAL |
| 9984229U, // GLD1W_D_SCALED_REAL |
| 6052069U, // GLD1W_D_SXTW_REAL |
| 10246373U, // GLD1W_D_SXTW_SCALED_REAL |
| 6314213U, // GLD1W_D_UXTW_REAL |
| 10508517U, // GLD1W_D_UXTW_SCALED_REAL |
| 680810581U, // GLD1W_IMM_REAL |
| 6576357U, // GLD1W_SXTW_REAL |
| 10770661U, // GLD1W_SXTW_SCALED_REAL |
| 6838501U, // GLD1W_UXTW_REAL |
| 11032805U, // GLD1W_UXTW_SCALED_REAL |
| 673208469U, // GLDFF1B_D_IMM_REAL |
| 5789925U, // GLDFF1B_D_REAL |
| 6052069U, // GLDFF1B_D_SXTW_REAL |
| 6314213U, // GLDFF1B_D_UXTW_REAL |
| 673208405U, // GLDFF1B_S_IMM_REAL |
| 6576357U, // GLDFF1B_S_SXTW_REAL |
| 6838501U, // GLDFF1B_S_UXTW_REAL |
| 7100565U, // GLDFF1D_IMM_REAL |
| 5789925U, // GLDFF1D_REAL |
| 7362789U, // GLDFF1D_SCALED_REAL |
| 6052069U, // GLDFF1D_SXTW_REAL |
| 7624933U, // GLDFF1D_SXTW_SCALED_REAL |
| 6314213U, // GLDFF1D_UXTW_REAL |
| 7887077U, // GLDFF1D_UXTW_SCALED_REAL |
| 679237781U, // GLDFF1H_D_IMM_REAL |
| 5789925U, // GLDFF1H_D_REAL |
| 8411365U, // GLDFF1H_D_SCALED_REAL |
| 6052069U, // GLDFF1H_D_SXTW_REAL |
| 8673509U, // GLDFF1H_D_SXTW_SCALED_REAL |
| 6314213U, // GLDFF1H_D_UXTW_REAL |
| 8935653U, // GLDFF1H_D_UXTW_SCALED_REAL |
| 679237717U, // GLDFF1H_S_IMM_REAL |
| 6576357U, // GLDFF1H_S_SXTW_REAL |
| 9197797U, // GLDFF1H_S_SXTW_SCALED_REAL |
| 6838501U, // GLDFF1H_S_UXTW_REAL |
| 9459941U, // GLDFF1H_S_UXTW_SCALED_REAL |
| 673208469U, // GLDFF1SB_D_IMM_REAL |
| 5789925U, // GLDFF1SB_D_REAL |
| 6052069U, // GLDFF1SB_D_SXTW_REAL |
| 6314213U, // GLDFF1SB_D_UXTW_REAL |
| 673208405U, // GLDFF1SB_S_IMM_REAL |
| 6576357U, // GLDFF1SB_S_SXTW_REAL |
| 6838501U, // GLDFF1SB_S_UXTW_REAL |
| 679237781U, // GLDFF1SH_D_IMM_REAL |
| 5789925U, // GLDFF1SH_D_REAL |
| 8411365U, // GLDFF1SH_D_SCALED_REAL |
| 6052069U, // GLDFF1SH_D_SXTW_REAL |
| 8673509U, // GLDFF1SH_D_SXTW_SCALED_REAL |
| 6314213U, // GLDFF1SH_D_UXTW_REAL |
| 8935653U, // GLDFF1SH_D_UXTW_SCALED_REAL |
| 679237717U, // GLDFF1SH_S_IMM_REAL |
| 6576357U, // GLDFF1SH_S_SXTW_REAL |
| 9197797U, // GLDFF1SH_S_SXTW_SCALED_REAL |
| 6838501U, // GLDFF1SH_S_UXTW_REAL |
| 9459941U, // GLDFF1SH_S_UXTW_SCALED_REAL |
| 680810645U, // GLDFF1SW_D_IMM_REAL |
| 5789925U, // GLDFF1SW_D_REAL |
| 9984229U, // GLDFF1SW_D_SCALED_REAL |
| 6052069U, // GLDFF1SW_D_SXTW_REAL |
| 10246373U, // GLDFF1SW_D_SXTW_SCALED_REAL |
| 6314213U, // GLDFF1SW_D_UXTW_REAL |
| 10508517U, // GLDFF1SW_D_UXTW_SCALED_REAL |
| 680810645U, // GLDFF1W_D_IMM_REAL |
| 5789925U, // GLDFF1W_D_REAL |
| 9984229U, // GLDFF1W_D_SCALED_REAL |
| 6052069U, // GLDFF1W_D_SXTW_REAL |
| 10246373U, // GLDFF1W_D_SXTW_SCALED_REAL |
| 6314213U, // GLDFF1W_D_UXTW_REAL |
| 10508517U, // GLDFF1W_D_UXTW_SCALED_REAL |
| 680810581U, // GLDFF1W_IMM_REAL |
| 6576357U, // GLDFF1W_SXTW_REAL |
| 10770661U, // GLDFF1W_SXTW_SCALED_REAL |
| 6838501U, // GLDFF1W_UXTW_REAL |
| 11032805U, // GLDFF1W_UXTW_SCALED_REAL |
| 6208U, // GMI |
| 0U, // HINT |
| 67383505U, // HISTCNT_ZPzZZ_D |
| 134504657U, // HISTCNT_ZPzZZ_S |
| 20546U, // HISTSEG_ZZZ |
| 0U, // HLT |
| 0U, // HVC |
| 4U, // INCB_XPiI |
| 4U, // INCD_XPiI |
| 4U, // INCD_ZPiI |
| 4U, // INCH_XPiI |
| 0U, // INCH_ZPiI |
| 2U, // INCP_XP_B |
| 1U, // INCP_XP_D |
| 0U, // INCP_XP_H |
| 2U, // INCP_XP_S |
| 0U, // INCP_ZP_D |
| 0U, // INCP_ZP_H |
| 0U, // INCP_ZP_S |
| 4U, // INCW_XPiI |
| 4U, // INCW_ZPiI |
| 709U, // INDEX_II_B |
| 6208U, // INDEX_II_D |
| 5U, // INDEX_II_H |
| 6208U, // INDEX_II_S |
| 229U, // INDEX_IR_B |
| 6208U, // INDEX_IR_D |
| 2U, // INDEX_IR_H |
| 6208U, // INDEX_IR_S |
| 96320U, // INDEX_RI_B |
| 6208U, // INDEX_RI_D |
| 721U, // INDEX_RI_H |
| 6208U, // INDEX_RI_S |
| 6208U, // INDEX_RR_B |
| 6208U, // INDEX_RR_D |
| 225U, // INDEX_RR_H |
| 6208U, // INDEX_RR_S |
| 99041U, // INSERT_MXIPZ_H_B |
| 101089U, // INSERT_MXIPZ_H_D |
| 78561U, // INSERT_MXIPZ_H_H |
| 103137U, // INSERT_MXIPZ_H_Q |
| 105185U, // INSERT_MXIPZ_H_S |
| 99041U, // INSERT_MXIPZ_V_B |
| 101089U, // INSERT_MXIPZ_V_D |
| 78561U, // INSERT_MXIPZ_V_H |
| 103137U, // INSERT_MXIPZ_V_Q |
| 105185U, // INSERT_MXIPZ_V_S |
| 2U, // INSR_ZR_B |
| 2U, // INSR_ZR_D |
| 0U, // INSR_ZR_H |
| 2U, // INSR_ZR_S |
| 6U, // INSR_ZV_B |
| 6U, // INSR_ZV_D |
| 0U, // INSR_ZV_H |
| 6U, // INSR_ZV_S |
| 4U, // INSvi16gpr |
| 6U, // INSvi16lane |
| 4U, // INSvi32gpr |
| 6U, // INSvi32lane |
| 4U, // INSvi64gpr |
| 6U, // INSvi64lane |
| 4U, // INSvi8gpr |
| 6U, // INSvi8lane |
| 6208U, // IRG |
| 0U, // ISB |
| 20545U, // LASTA_RPZ_B |
| 12353U, // LASTA_RPZ_D |
| 10305U, // LASTA_RPZ_H |
| 24641U, // LASTA_RPZ_S |
| 20545U, // LASTA_VPZ_B |
| 12353U, // LASTA_VPZ_D |
| 10305U, // LASTA_VPZ_H |
| 24641U, // LASTA_VPZ_S |
| 20545U, // LASTB_RPZ_B |
| 12353U, // LASTB_RPZ_D |
| 10305U, // LASTB_RPZ_H |
| 24641U, // LASTB_RPZ_S |
| 20545U, // LASTB_VPZ_B |
| 12353U, // LASTB_VPZ_D |
| 10305U, // LASTB_VPZ_H |
| 24641U, // LASTB_VPZ_S |
| 11294949U, // LD1B |
| 11294949U, // LD1B_2Z |
| 712792293U, // LD1B_2Z_IMM |
| 11294949U, // LD1B_4Z |
| 714365157U, // LD1B_4Z_IMM |
| 11294949U, // LD1B_D |
| 706762981U, // LD1B_D_IMM_REAL |
| 11294949U, // LD1B_H |
| 706762981U, // LD1B_H_IMM_REAL |
| 706762981U, // LD1B_IMM_REAL |
| 11294949U, // LD1B_S |
| 706762981U, // LD1B_S_IMM_REAL |
| 107254U, // LD1B_VG2_M2ZPXI |
| 109302U, // LD1B_VG2_M2ZPXX |
| 714365157U, // LD1B_VG4_M4ZPXI |
| 11294949U, // LD1B_VG4_M4ZPXX |
| 11557093U, // LD1D |
| 11557093U, // LD1D_2Z |
| 712792293U, // LD1D_2Z_IMM |
| 11557093U, // LD1D_4Z |
| 714365157U, // LD1D_4Z_IMM |
| 706762981U, // LD1D_IMM_REAL |
| 11557093U, // LD1D_Q |
| 706762981U, // LD1D_Q_IMM |
| 712792293U, // LD1D_VG2_M2ZPXI |
| 11557093U, // LD1D_VG2_M2ZPXX |
| 714365157U, // LD1D_VG4_M4ZPXI |
| 11557093U, // LD1D_VG4_M4ZPXX |
| 0U, // LD1Fourv16b |
| 0U, // LD1Fourv16b_POST |
| 0U, // LD1Fourv1d |
| 0U, // LD1Fourv1d_POST |
| 0U, // LD1Fourv2d |
| 0U, // LD1Fourv2d_POST |
| 0U, // LD1Fourv2s |
| 0U, // LD1Fourv2s_POST |
| 0U, // LD1Fourv4h |
| 0U, // LD1Fourv4h_POST |
| 0U, // LD1Fourv4s |
| 0U, // LD1Fourv4s_POST |
| 0U, // LD1Fourv8b |
| 0U, // LD1Fourv8b_POST |
| 0U, // LD1Fourv8h |
| 0U, // LD1Fourv8h_POST |
| 11819237U, // LD1H |
| 11819237U, // LD1H_2Z |
| 712792293U, // LD1H_2Z_IMM |
| 11819237U, // LD1H_4Z |
| 714365157U, // LD1H_4Z_IMM |
| 11819237U, // LD1H_D |
| 706762981U, // LD1H_D_IMM_REAL |
| 706762981U, // LD1H_IMM_REAL |
| 11819237U, // LD1H_S |
| 706762981U, // LD1H_S_IMM_REAL |
| 107254U, // LD1H_VG2_M2ZPXI |
| 111350U, // LD1H_VG2_M2ZPXX |
| 714365157U, // LD1H_VG4_M4ZPXI |
| 11819237U, // LD1H_VG4_M4ZPXX |
| 0U, // LD1Onev16b |
| 0U, // LD1Onev16b_POST |
| 0U, // LD1Onev1d |
| 0U, // LD1Onev1d_POST |
| 0U, // LD1Onev2d |
| 0U, // LD1Onev2d_POST |
| 0U, // LD1Onev2s |
| 0U, // LD1Onev2s_POST |
| 0U, // LD1Onev4h |
| 0U, // LD1Onev4h_POST |
| 0U, // LD1Onev4s |
| 0U, // LD1Onev4s_POST |
| 0U, // LD1Onev8b |
| 0U, // LD1Onev8b_POST |
| 0U, // LD1Onev8h |
| 0U, // LD1Onev8h_POST |
| 673208549U, // LD1RB_D_IMM |
| 673208549U, // LD1RB_H_IMM |
| 673208549U, // LD1RB_IMM |
| 673208549U, // LD1RB_S_IMM |
| 7100645U, // LD1RD_IMM |
| 679237861U, // LD1RH_D_IMM |
| 679237861U, // LD1RH_IMM |
| 679237861U, // LD1RH_S_IMM |
| 11294949U, // LD1RO_B |
| 12081381U, // LD1RO_B_IMM |
| 11557093U, // LD1RO_D |
| 12081381U, // LD1RO_D_IMM |
| 11819237U, // LD1RO_H |
| 12081381U, // LD1RO_H_IMM |
| 12343525U, // LD1RO_W |
| 12081381U, // LD1RO_W_IMM |
| 11294949U, // LD1RQ_B |
| 12605669U, // LD1RQ_B_IMM |
| 11557093U, // LD1RQ_D |
| 12605669U, // LD1RQ_D_IMM |
| 11819237U, // LD1RQ_H |
| 12605669U, // LD1RQ_H_IMM |
| 12343525U, // LD1RQ_W |
| 12605669U, // LD1RQ_W_IMM |
| 673208549U, // LD1RSB_D_IMM |
| 673208549U, // LD1RSB_H_IMM |
| 673208549U, // LD1RSB_S_IMM |
| 679237861U, // LD1RSH_D_IMM |
| 679237861U, // LD1RSH_S_IMM |
| 680810725U, // LD1RSW_IMM |
| 680810725U, // LD1RW_D_IMM |
| 680810725U, // LD1RW_IMM |
| 0U, // LD1Rv16b |
| 0U, // LD1Rv16b_POST |
| 0U, // LD1Rv1d |
| 0U, // LD1Rv1d_POST |
| 0U, // LD1Rv2d |
| 0U, // LD1Rv2d_POST |
| 0U, // LD1Rv2s |
| 0U, // LD1Rv2s_POST |
| 0U, // LD1Rv4h |
| 0U, // LD1Rv4h_POST |
| 0U, // LD1Rv4s |
| 0U, // LD1Rv4s_POST |
| 0U, // LD1Rv8b |
| 0U, // LD1Rv8b_POST |
| 0U, // LD1Rv8h |
| 0U, // LD1Rv8h_POST |
| 11294949U, // LD1SB_D |
| 706762981U, // LD1SB_D_IMM_REAL |
| 11294949U, // LD1SB_H |
| 706762981U, // LD1SB_H_IMM_REAL |
| 11294949U, // LD1SB_S |
| 706762981U, // LD1SB_S_IMM_REAL |
| 11819237U, // LD1SH_D |
| 706762981U, // LD1SH_D_IMM_REAL |
| 11819237U, // LD1SH_S |
| 706762981U, // LD1SH_S_IMM_REAL |
| 12343525U, // LD1SW_D |
| 706762981U, // LD1SW_D_IMM_REAL |
| 0U, // LD1Threev16b |
| 0U, // LD1Threev16b_POST |
| 0U, // LD1Threev1d |
| 0U, // LD1Threev1d_POST |
| 0U, // LD1Threev2d |
| 0U, // LD1Threev2d_POST |
| 0U, // LD1Threev2s |
| 0U, // LD1Threev2s_POST |
| 0U, // LD1Threev4h |
| 0U, // LD1Threev4h_POST |
| 0U, // LD1Threev4s |
| 0U, // LD1Threev4s_POST |
| 0U, // LD1Threev8b |
| 0U, // LD1Threev8b_POST |
| 0U, // LD1Threev8h |
| 0U, // LD1Threev8h_POST |
| 0U, // LD1Twov16b |
| 0U, // LD1Twov16b_POST |
| 0U, // LD1Twov1d |
| 0U, // LD1Twov1d_POST |
| 0U, // LD1Twov2d |
| 0U, // LD1Twov2d_POST |
| 0U, // LD1Twov2s |
| 0U, // LD1Twov2s_POST |
| 0U, // LD1Twov4h |
| 0U, // LD1Twov4h_POST |
| 0U, // LD1Twov4s |
| 0U, // LD1Twov4s_POST |
| 0U, // LD1Twov8b |
| 0U, // LD1Twov8b_POST |
| 0U, // LD1Twov8h |
| 0U, // LD1Twov8h_POST |
| 12343525U, // LD1W |
| 12343525U, // LD1W_2Z |
| 712792293U, // LD1W_2Z_IMM |
| 12343525U, // LD1W_4Z |
| 714365157U, // LD1W_4Z_IMM |
| 12343525U, // LD1W_D |
| 706762981U, // LD1W_D_IMM_REAL |
| 706762981U, // LD1W_IMM_REAL |
| 12343525U, // LD1W_Q |
| 706762981U, // LD1W_Q_IMM |
| 712792293U, // LD1W_VG2_M2ZPXI |
| 12343525U, // LD1W_VG2_M2ZPXX |
| 714365157U, // LD1W_VG4_M4ZPXI |
| 12343525U, // LD1W_VG4_M4ZPXX |
| 12958465U, // LD1_MXIPXX_H_B |
| 13220609U, // LD1_MXIPXX_H_D |
| 13482753U, // LD1_MXIPXX_H_H |
| 13744897U, // LD1_MXIPXX_H_Q |
| 14007041U, // LD1_MXIPXX_H_S |
| 12958465U, // LD1_MXIPXX_V_B |
| 13220609U, // LD1_MXIPXX_V_D |
| 13482753U, // LD1_MXIPXX_V_H |
| 13744897U, // LD1_MXIPXX_V_Q |
| 14007041U, // LD1_MXIPXX_V_S |
| 0U, // LD1i16 |
| 0U, // LD1i16_POST |
| 0U, // LD1i32 |
| 0U, // LD1i32_POST |
| 0U, // LD1i64 |
| 0U, // LD1i64_POST |
| 0U, // LD1i8 |
| 0U, // LD1i8_POST |
| 11294949U, // LD2B |
| 712792293U, // LD2B_IMM |
| 11557093U, // LD2D |
| 712792293U, // LD2D_IMM |
| 11819237U, // LD2H |
| 712792293U, // LD2H_IMM |
| 14178533U, // LD2Q |
| 712792293U, // LD2Q_IMM |
| 0U, // LD2Rv16b |
| 0U, // LD2Rv16b_POST |
| 0U, // LD2Rv1d |
| 0U, // LD2Rv1d_POST |
| 0U, // LD2Rv2d |
| 0U, // LD2Rv2d_POST |
| 0U, // LD2Rv2s |
| 0U, // LD2Rv2s_POST |
| 0U, // LD2Rv4h |
| 0U, // LD2Rv4h_POST |
| 0U, // LD2Rv4s |
| 0U, // LD2Rv4s_POST |
| 0U, // LD2Rv8b |
| 0U, // LD2Rv8b_POST |
| 0U, // LD2Rv8h |
| 0U, // LD2Rv8h_POST |
| 0U, // LD2Twov16b |
| 0U, // LD2Twov16b_POST |
| 0U, // LD2Twov2d |
| 0U, // LD2Twov2d_POST |
| 0U, // LD2Twov2s |
| 0U, // LD2Twov2s_POST |
| 0U, // LD2Twov4h |
| 0U, // LD2Twov4h_POST |
| 0U, // LD2Twov4s |
| 0U, // LD2Twov4s_POST |
| 0U, // LD2Twov8b |
| 0U, // LD2Twov8b_POST |
| 0U, // LD2Twov8h |
| 0U, // LD2Twov8h_POST |
| 12343525U, // LD2W |
| 712792293U, // LD2W_IMM |
| 0U, // LD2i16 |
| 0U, // LD2i16_POST |
| 0U, // LD2i32 |
| 0U, // LD2i32_POST |
| 0U, // LD2i64 |
| 0U, // LD2i64_POST |
| 0U, // LD2i8 |
| 0U, // LD2i8_POST |
| 11294949U, // LD3B |
| 14440677U, // LD3B_IMM |
| 11557093U, // LD3D |
| 14440677U, // LD3D_IMM |
| 11819237U, // LD3H |
| 14440677U, // LD3H_IMM |
| 14178533U, // LD3Q |
| 14440677U, // LD3Q_IMM |
| 0U, // LD3Rv16b |
| 0U, // LD3Rv16b_POST |
| 0U, // LD3Rv1d |
| 0U, // LD3Rv1d_POST |
| 0U, // LD3Rv2d |
| 0U, // LD3Rv2d_POST |
| 0U, // LD3Rv2s |
| 0U, // LD3Rv2s_POST |
| 0U, // LD3Rv4h |
| 0U, // LD3Rv4h_POST |
| 0U, // LD3Rv4s |
| 0U, // LD3Rv4s_POST |
| 0U, // LD3Rv8b |
| 0U, // LD3Rv8b_POST |
| 0U, // LD3Rv8h |
| 0U, // LD3Rv8h_POST |
| 0U, // LD3Threev16b |
| 0U, // LD3Threev16b_POST |
| 0U, // LD3Threev2d |
| 0U, // LD3Threev2d_POST |
| 0U, // LD3Threev2s |
| 0U, // LD3Threev2s_POST |
| 0U, // LD3Threev4h |
| 0U, // LD3Threev4h_POST |
| 0U, // LD3Threev4s |
| 0U, // LD3Threev4s_POST |
| 0U, // LD3Threev8b |
| 0U, // LD3Threev8b_POST |
| 0U, // LD3Threev8h |
| 0U, // LD3Threev8h_POST |
| 12343525U, // LD3W |
| 14440677U, // LD3W_IMM |
| 0U, // LD3i16 |
| 0U, // LD3i16_POST |
| 0U, // LD3i32 |
| 0U, // LD3i32_POST |
| 0U, // LD3i64 |
| 0U, // LD3i64_POST |
| 0U, // LD3i8 |
| 0U, // LD3i8_POST |
| 11294949U, // LD4B |
| 714365157U, // LD4B_IMM |
| 11557093U, // LD4D |
| 714365157U, // LD4D_IMM |
| 0U, // LD4Fourv16b |
| 0U, // LD4Fourv16b_POST |
| 0U, // LD4Fourv2d |
| 0U, // LD4Fourv2d_POST |
| 0U, // LD4Fourv2s |
| 0U, // LD4Fourv2s_POST |
| 0U, // LD4Fourv4h |
| 0U, // LD4Fourv4h_POST |
| 0U, // LD4Fourv4s |
| 0U, // LD4Fourv4s_POST |
| 0U, // LD4Fourv8b |
| 0U, // LD4Fourv8b_POST |
| 0U, // LD4Fourv8h |
| 0U, // LD4Fourv8h_POST |
| 11819237U, // LD4H |
| 714365157U, // LD4H_IMM |
| 14178533U, // LD4Q |
| 714365157U, // LD4Q_IMM |
| 0U, // LD4Rv16b |
| 0U, // LD4Rv16b_POST |
| 0U, // LD4Rv1d |
| 0U, // LD4Rv1d_POST |
| 0U, // LD4Rv2d |
| 0U, // LD4Rv2d_POST |
| 0U, // LD4Rv2s |
| 0U, // LD4Rv2s_POST |
| 0U, // LD4Rv4h |
| 0U, // LD4Rv4h_POST |
| 0U, // LD4Rv4s |
| 0U, // LD4Rv4s_POST |
| 0U, // LD4Rv8b |
| 0U, // LD4Rv8b_POST |
| 0U, // LD4Rv8h |
| 0U, // LD4Rv8h_POST |
| 12343525U, // LD4W |
| 714365157U, // LD4W_IMM |
| 0U, // LD4i16 |
| 0U, // LD4i16_POST |
| 0U, // LD4i32 |
| 0U, // LD4i32_POST |
| 0U, // LD4i64 |
| 0U, // LD4i64_POST |
| 0U, // LD4i8 |
| 0U, // LD4i8_POST |
| 0U, // LD64B |
| 6U, // LDADDAB |
| 6U, // LDADDAH |
| 6U, // LDADDALB |
| 6U, // LDADDALH |
| 6U, // LDADDALW |
| 6U, // LDADDALX |
| 6U, // LDADDAW |
| 6U, // LDADDAX |
| 6U, // LDADDB |
| 6U, // LDADDH |
| 6U, // LDADDLB |
| 6U, // LDADDLH |
| 6U, // LDADDLW |
| 6U, // LDADDLX |
| 6U, // LDADDW |
| 6U, // LDADDX |
| 0U, // LDAP1 |
| 784U, // LDAPRB |
| 784U, // LDAPRH |
| 784U, // LDAPRW |
| 802U, // LDAPRWpre |
| 784U, // LDAPRX |
| 818U, // LDAPRXpre |
| 3676224U, // LDAPURBi |
| 3676224U, // LDAPURHi |
| 3676224U, // LDAPURSBWi |
| 3676224U, // LDAPURSBXi |
| 3676224U, // LDAPURSHWi |
| 3676224U, // LDAPURSHXi |
| 3676224U, // LDAPURSWi |
| 3676224U, // LDAPURXi |
| 784U, // LDAPURbi |
| 784U, // LDAPURdi |
| 784U, // LDAPURhi |
| 3676224U, // LDAPURi |
| 784U, // LDAPURqi |
| 784U, // LDAPURsi |
| 784U, // LDARB |
| 784U, // LDARH |
| 784U, // LDARW |
| 784U, // LDARX |
| 3676512U, // LDAXPW |
| 3676512U, // LDAXPX |
| 784U, // LDAXRB |
| 784U, // LDAXRH |
| 784U, // LDAXRW |
| 784U, // LDAXRX |
| 6U, // LDCLRAB |
| 6U, // LDCLRAH |
| 6U, // LDCLRALB |
| 6U, // LDCLRALH |
| 6U, // LDCLRALW |
| 6U, // LDCLRALX |
| 6U, // LDCLRAW |
| 6U, // LDCLRAX |
| 6U, // LDCLRB |
| 6U, // LDCLRH |
| 6U, // LDCLRLB |
| 6U, // LDCLRLH |
| 6U, // LDCLRLW |
| 6U, // LDCLRLX |
| 115044U, // LDCLRP |
| 115044U, // LDCLRPA |
| 115044U, // LDCLRPAL |
| 115044U, // LDCLRPL |
| 6U, // LDCLRW |
| 6U, // LDCLRX |
| 6U, // LDEORAB |
| 6U, // LDEORAH |
| 6U, // LDEORALB |
| 6U, // LDEORALH |
| 6U, // LDEORALW |
| 6U, // LDEORALX |
| 6U, // LDEORAW |
| 6U, // LDEORAX |
| 6U, // LDEORB |
| 6U, // LDEORH |
| 6U, // LDEORLB |
| 6U, // LDEORLH |
| 6U, // LDEORLW |
| 6U, // LDEORLX |
| 6U, // LDEORW |
| 6U, // LDEORX |
| 11294949U, // LDFF1B_D_REAL |
| 11294949U, // LDFF1B_H_REAL |
| 11294949U, // LDFF1B_REAL |
| 11294949U, // LDFF1B_S_REAL |
| 11557093U, // LDFF1D_REAL |
| 11819237U, // LDFF1H_D_REAL |
| 11819237U, // LDFF1H_REAL |
| 11819237U, // LDFF1H_S_REAL |
| 11294949U, // LDFF1SB_D_REAL |
| 11294949U, // LDFF1SB_H_REAL |
| 11294949U, // LDFF1SB_S_REAL |
| 11819237U, // LDFF1SH_D_REAL |
| 11819237U, // LDFF1SH_S_REAL |
| 12343525U, // LDFF1SW_D_REAL |
| 12343525U, // LDFF1W_D_REAL |
| 12343525U, // LDFF1W_REAL |
| 3786818U, // LDG |
| 784U, // LDGM |
| 3676512U, // LDIAPPW |
| 14766434U, // LDIAPPWpre |
| 3676512U, // LDIAPPX |
| 15028578U, // LDIAPPXpre |
| 784U, // LDLARB |
| 784U, // LDLARH |
| 784U, // LDLARW |
| 784U, // LDLARX |
| 706762981U, // LDNF1B_D_IMM_REAL |
| 706762981U, // LDNF1B_H_IMM_REAL |
| 706762981U, // LDNF1B_IMM_REAL |
| 706762981U, // LDNF1B_S_IMM_REAL |
| 706762981U, // LDNF1D_IMM_REAL |
| 706762981U, // LDNF1H_D_IMM_REAL |
| 706762981U, // LDNF1H_IMM_REAL |
| 706762981U, // LDNF1H_S_IMM_REAL |
| 706762981U, // LDNF1SB_D_IMM_REAL |
| 706762981U, // LDNF1SB_H_IMM_REAL |
| 706762981U, // LDNF1SB_S_IMM_REAL |
| 706762981U, // LDNF1SH_D_IMM_REAL |
| 706762981U, // LDNF1SH_S_IMM_REAL |
| 706762981U, // LDNF1SW_D_IMM_REAL |
| 706762981U, // LDNF1W_D_IMM_REAL |
| 706762981U, // LDNF1W_IMM_REAL |
| 738466144U, // LDNPDi |
| 772020576U, // LDNPQi |
| 805575008U, // LDNPSi |
| 805575008U, // LDNPWi |
| 738466144U, // LDNPXi |
| 11294949U, // LDNT1B_2Z |
| 712792293U, // LDNT1B_2Z_IMM |
| 11294949U, // LDNT1B_4Z |
| 714365157U, // LDNT1B_4Z_IMM |
| 107254U, // LDNT1B_VG2_M2ZPXI |
| 109302U, // LDNT1B_VG2_M2ZPXX |
| 714365157U, // LDNT1B_VG4_M4ZPXI |
| 11294949U, // LDNT1B_VG4_M4ZPXX |
| 706762981U, // LDNT1B_ZRI |
| 11294949U, // LDNT1B_ZRR |
| 673208469U, // LDNT1B_ZZR_D_REAL |
| 673208405U, // LDNT1B_ZZR_S_REAL |
| 11557093U, // LDNT1D_2Z |
| 712792293U, // LDNT1D_2Z_IMM |
| 11557093U, // LDNT1D_4Z |
| 714365157U, // LDNT1D_4Z_IMM |
| 712792293U, // LDNT1D_VG2_M2ZPXI |
| 11557093U, // LDNT1D_VG2_M2ZPXX |
| 714365157U, // LDNT1D_VG4_M4ZPXI |
| 11557093U, // LDNT1D_VG4_M4ZPXX |
| 706762981U, // LDNT1D_ZRI |
| 11557093U, // LDNT1D_ZRR |
| 673208469U, // LDNT1D_ZZR_D_REAL |
| 11819237U, // LDNT1H_2Z |
| 712792293U, // LDNT1H_2Z_IMM |
| 11819237U, // LDNT1H_4Z |
| 714365157U, // LDNT1H_4Z_IMM |
| 107254U, // LDNT1H_VG2_M2ZPXI |
| 111350U, // LDNT1H_VG2_M2ZPXX |
| 714365157U, // LDNT1H_VG4_M4ZPXI |
| 11819237U, // LDNT1H_VG4_M4ZPXX |
| 706762981U, // LDNT1H_ZRI |
| 11819237U, // LDNT1H_ZRR |
| 673208469U, // LDNT1H_ZZR_D_REAL |
| 673208405U, // LDNT1H_ZZR_S_REAL |
| 673208469U, // LDNT1SB_ZZR_D_REAL |
| 673208405U, // LDNT1SB_ZZR_S_REAL |
| 673208469U, // LDNT1SH_ZZR_D_REAL |
| 673208405U, // LDNT1SH_ZZR_S_REAL |
| 673208469U, // LDNT1SW_ZZR_D_REAL |
| 12343525U, // LDNT1W_2Z |
| 712792293U, // LDNT1W_2Z_IMM |
| 12343525U, // LDNT1W_4Z |
| 714365157U, // LDNT1W_4Z_IMM |
| 712792293U, // LDNT1W_VG2_M2ZPXI |
| 12343525U, // LDNT1W_VG2_M2ZPXX |
| 714365157U, // LDNT1W_VG4_M4ZPXI |
| 12343525U, // LDNT1W_VG4_M4ZPXX |
| 706762981U, // LDNT1W_ZRI |
| 12343525U, // LDNT1W_ZRR |
| 673208469U, // LDNT1W_ZZR_D_REAL |
| 673208405U, // LDNT1W_ZZR_S_REAL |
| 738466144U, // LDPDi |
| 854151522U, // LDPDpost |
| 839209314U, // LDPDpre |
| 772020576U, // LDPQi |
| 887705954U, // LDPQpost |
| 872763746U, // LDPQpre |
| 805575008U, // LDPSWi |
| 921260386U, // LDPSWpost |
| 906318178U, // LDPSWpre |
| 805575008U, // LDPSi |
| 921260386U, // LDPSpost |
| 906318178U, // LDPSpre |
| 805575008U, // LDPWi |
| 921260386U, // LDPWpost |
| 906318178U, // LDPWpre |
| 738466144U, // LDPXi |
| 854151522U, // LDPXpost |
| 839209314U, // LDPXpre |
| 118848U, // LDRAAindexed |
| 120898U, // LDRAAwriteback |
| 118848U, // LDRABindexed |
| 120898U, // LDRABwriteback |
| 86850U, // LDRBBpost |
| 15552578U, // LDRBBpre |
| 939792448U, // LDRBBroW |
| 973346880U, // LDRBBroX |
| 122944U, // LDRBBui |
| 86850U, // LDRBpost |
| 15552578U, // LDRBpre |
| 939792448U, // LDRBroW |
| 973346880U, // LDRBroX |
| 122944U, // LDRBui |
| 2U, // LDRDl |
| 86850U, // LDRDpost |
| 15552578U, // LDRDpre |
| 1006901312U, // LDRDroW |
| 1040455744U, // LDRDroX |
| 124992U, // LDRDui |
| 86850U, // LDRHHpost |
| 15552578U, // LDRHHpre |
| 1074010176U, // LDRHHroW |
| 1107564608U, // LDRHHroX |
| 127040U, // LDRHHui |
| 86850U, // LDRHpost |
| 15552578U, // LDRHpre |
| 1074010176U, // LDRHroW |
| 1107564608U, // LDRHroX |
| 127040U, // LDRHui |
| 2U, // LDRQl |
| 86850U, // LDRQpost |
| 15552578U, // LDRQpre |
| 1141119040U, // LDRQroW |
| 1174673472U, // LDRQroX |
| 129088U, // LDRQui |
| 86850U, // LDRSBWpost |
| 15552578U, // LDRSBWpre |
| 939792448U, // LDRSBWroW |
| 973346880U, // LDRSBWroX |
| 122944U, // LDRSBWui |
| 86850U, // LDRSBXpost |
| 15552578U, // LDRSBXpre |
| 939792448U, // LDRSBXroW |
| 973346880U, // LDRSBXroX |
| 122944U, // LDRSBXui |
| 86850U, // LDRSHWpost |
| 15552578U, // LDRSHWpre |
| 1074010176U, // LDRSHWroW |
| 1107564608U, // LDRSHWroX |
| 127040U, // LDRSHWui |
| 86850U, // LDRSHXpost |
| 15552578U, // LDRSHXpre |
| 1074010176U, // LDRSHXroW |
| 1107564608U, // LDRSHXroX |
| 127040U, // LDRSHXui |
| 2U, // LDRSWl |
| 86850U, // LDRSWpost |
| 15552578U, // LDRSWpre |
| 1208227904U, // LDRSWroW |
| 1241782336U, // LDRSWroX |
| 131136U, // LDRSWui |
| 2U, // LDRSl |
| 86850U, // LDRSpost |
| 15552578U, // LDRSpre |
| 1208227904U, // LDRSroW |
| 1241782336U, // LDRSroX |
| 131136U, // LDRSui |
| 2U, // LDRWl |
| 86850U, // LDRWpost |
| 15552578U, // LDRWpre |
| 1208227904U, // LDRWroW |
| 1241782336U, // LDRWroX |
| 131136U, // LDRWui |
| 2U, // LDRXl |
| 86850U, // LDRXpost |
| 15552578U, // LDRXpre |
| 1006901312U, // LDRXroW |
| 1040455744U, // LDRXroX |
| 124992U, // LDRXui |
| 15734848U, // LDR_PXI |
| 784U, // LDR_TX |
| 0U, // LDR_ZA |
| 15734848U, // LDR_ZXI |
| 6U, // LDSETAB |
| 6U, // LDSETAH |
| 6U, // LDSETALB |
| 6U, // LDSETALH |
| 6U, // LDSETALW |
| 6U, // LDSETALX |
| 6U, // LDSETAW |
| 6U, // LDSETAX |
| 6U, // LDSETB |
| 6U, // LDSETH |
| 6U, // LDSETLB |
| 6U, // LDSETLH |
| 6U, // LDSETLW |
| 6U, // LDSETLX |
| 115044U, // LDSETP |
| 115044U, // LDSETPA |
| 115044U, // LDSETPAL |
| 115044U, // LDSETPL |
| 6U, // LDSETW |
| 6U, // LDSETX |
| 6U, // LDSMAXAB |
| 6U, // LDSMAXAH |
| 6U, // LDSMAXALB |
| 6U, // LDSMAXALH |
| 6U, // LDSMAXALW |
| 6U, // LDSMAXALX |
| 6U, // LDSMAXAW |
| 6U, // LDSMAXAX |
| 6U, // LDSMAXB |
| 6U, // LDSMAXH |
| 6U, // LDSMAXLB |
| 6U, // LDSMAXLH |
| 6U, // LDSMAXLW |
| 6U, // LDSMAXLX |
| 6U, // LDSMAXW |
| 6U, // LDSMAXX |
| 6U, // LDSMINAB |
| 6U, // LDSMINAH |
| 6U, // LDSMINALB |
| 6U, // LDSMINALH |
| 6U, // LDSMINALW |
| 6U, // LDSMINALX |
| 6U, // LDSMINAW |
| 6U, // LDSMINAX |
| 6U, // LDSMINB |
| 6U, // LDSMINH |
| 6U, // LDSMINLB |
| 6U, // LDSMINLH |
| 6U, // LDSMINLW |
| 6U, // LDSMINLX |
| 6U, // LDSMINW |
| 6U, // LDSMINX |
| 3676224U, // LDTRBi |
| 3676224U, // LDTRHi |
| 3676224U, // LDTRSBWi |
| 3676224U, // LDTRSBXi |
| 3676224U, // LDTRSHWi |
| 3676224U, // LDTRSHXi |
| 3676224U, // LDTRSWi |
| 3676224U, // LDTRWi |
| 3676224U, // LDTRXi |
| 6U, // LDUMAXAB |
| 6U, // LDUMAXAH |
| 6U, // LDUMAXALB |
| 6U, // LDUMAXALH |
| 6U, // LDUMAXALW |
| 6U, // LDUMAXALX |
| 6U, // LDUMAXAW |
| 6U, // LDUMAXAX |
| 6U, // LDUMAXB |
| 6U, // LDUMAXH |
| 6U, // LDUMAXLB |
| 6U, // LDUMAXLH |
| 6U, // LDUMAXLW |
| 6U, // LDUMAXLX |
| 6U, // LDUMAXW |
| 6U, // LDUMAXX |
| 6U, // LDUMINAB |
| 6U, // LDUMINAH |
| 6U, // LDUMINALB |
| 6U, // LDUMINALH |
| 6U, // LDUMINALW |
| 6U, // LDUMINALX |
| 6U, // LDUMINAW |
| 6U, // LDUMINAX |
| 6U, // LDUMINB |
| 6U, // LDUMINH |
| 6U, // LDUMINLB |
| 6U, // LDUMINLH |
| 6U, // LDUMINLW |
| 6U, // LDUMINLX |
| 6U, // LDUMINW |
| 6U, // LDUMINX |
| 3676224U, // LDURBBi |
| 3676224U, // LDURBi |
| 3676224U, // LDURDi |
| 3676224U, // LDURHHi |
| 3676224U, // LDURHi |
| 3676224U, // LDURQi |
| 3676224U, // LDURSBWi |
| 3676224U, // LDURSBXi |
| 3676224U, // LDURSHWi |
| 3676224U, // LDURSHXi |
| 3676224U, // LDURSWi |
| 3676224U, // LDURSi |
| 3676224U, // LDURWi |
| 3676224U, // LDURXi |
| 3676512U, // LDXPW |
| 3676512U, // LDXPX |
| 784U, // LDXRB |
| 784U, // LDXRH |
| 784U, // LDXRW |
| 784U, // LDXRX |
| 33837153U, // LSLR_ZPmZ_B |
| 67383393U, // LSLR_ZPmZ_D |
| 101210225U, // LSLR_ZPmZ_H |
| 134504545U, // LSLR_ZPmZ_S |
| 6208U, // LSLVWr |
| 6208U, // LSLVXr |
| 67391585U, // LSL_WIDE_ZPmZ_B |
| 2381937U, // LSL_WIDE_ZPmZ_H |
| 67395681U, // LSL_WIDE_ZPmZ_S |
| 12354U, // LSL_WIDE_ZZZ_B |
| 145U, // LSL_WIDE_ZZZ_H |
| 12354U, // LSL_WIDE_ZZZ_S |
| 282721U, // LSL_ZPmI_B |
| 274529U, // LSL_ZPmI_D |
| 102783089U, // LSL_ZPmI_H |
| 286817U, // LSL_ZPmI_S |
| 33837153U, // LSL_ZPmZ_B |
| 67383393U, // LSL_ZPmZ_D |
| 101210225U, // LSL_ZPmZ_H |
| 134504545U, // LSL_ZPmZ_S |
| 6210U, // LSL_ZZI_B |
| 6209U, // LSL_ZZI_D |
| 225U, // LSL_ZZI_H |
| 6210U, // LSL_ZZI_S |
| 33837153U, // LSRR_ZPmZ_B |
| 67383393U, // LSRR_ZPmZ_D |
| 101210225U, // LSRR_ZPmZ_H |
| 134504545U, // LSRR_ZPmZ_S |
| 6208U, // LSRVWr |
| 6208U, // LSRVXr |
| 67391585U, // LSR_WIDE_ZPmZ_B |
| 2381937U, // LSR_WIDE_ZPmZ_H |
| 67395681U, // LSR_WIDE_ZPmZ_S |
| 12354U, // LSR_WIDE_ZZZ_B |
| 145U, // LSR_WIDE_ZZZ_H |
| 12354U, // LSR_WIDE_ZZZ_S |
| 282721U, // LSR_ZPmI_B |
| 274529U, // LSR_ZPmI_D |
| 102783089U, // LSR_ZPmI_H |
| 286817U, // LSR_ZPmI_S |
| 33837153U, // LSR_ZPmZ_B |
| 67383393U, // LSR_ZPmZ_D |
| 101210225U, // LSR_ZPmZ_H |
| 134504545U, // LSR_ZPmZ_S |
| 6210U, // LSR_ZZI_B |
| 6209U, // LSR_ZZI_D |
| 225U, // LSR_ZZI_H |
| 6210U, // LSR_ZZI_S |
| 849U, // LUTI2_2ZTZI_B |
| 849U, // LUTI2_2ZTZI_H |
| 849U, // LUTI2_2ZTZI_S |
| 849U, // LUTI2_4ZTZI_B |
| 849U, // LUTI2_4ZTZI_H |
| 849U, // LUTI2_4ZTZI_S |
| 133184U, // LUTI2_S_2ZTZI_B |
| 133184U, // LUTI2_S_2ZTZI_H |
| 849U, // LUTI2_S_4ZTZI_B |
| 849U, // LUTI2_S_4ZTZI_H |
| 133184U, // LUTI2_ZTZI_B |
| 849U, // LUTI2_ZTZI_H |
| 133184U, // LUTI2_ZTZI_S |
| 849U, // LUTI4_2ZTZI_B |
| 849U, // LUTI4_2ZTZI_H |
| 849U, // LUTI4_2ZTZI_S |
| 849U, // LUTI4_4ZTZI_H |
| 849U, // LUTI4_4ZTZI_S |
| 133184U, // LUTI4_S_2ZTZI_B |
| 133184U, // LUTI4_S_2ZTZI_H |
| 849U, // LUTI4_S_4ZTZI_H |
| 133184U, // LUTI4_ZTZI_B |
| 849U, // LUTI4_ZTZI_H |
| 133184U, // LUTI4_ZTZI_S |
| 268352U, // MADDWrrr |
| 268352U, // MADDXrrr |
| 135265U, // MAD_ZPmZZ_B |
| 503580769U, // MAD_ZPmZZ_D |
| 103831793U, // MAD_ZPmZZ_H |
| 537137249U, // MAD_ZPmZZ_S |
| 33837265U, // MATCH_PPzZZ_B |
| 101210227U, // MATCH_PPzZZ_H |
| 135265U, // MLA_ZPmZZ_B |
| 503580769U, // MLA_ZPmZZ_D |
| 103831793U, // MLA_ZPmZZ_H |
| 537137249U, // MLA_ZPmZZ_S |
| 103286848U, // MLA_ZZZI_D |
| 82161U, // MLA_ZZZI_H |
| 103288896U, // MLA_ZZZI_S |
| 18497U, // MLAv16i8 |
| 18497U, // MLAv2i32 |
| 103303233U, // MLAv2i32_indexed |
| 18497U, // MLAv4i16 |
| 103303233U, // MLAv4i16_indexed |
| 18497U, // MLAv4i32 |
| 103303233U, // MLAv4i32_indexed |
| 18497U, // MLAv8i16 |
| 103303233U, // MLAv8i16_indexed |
| 18497U, // MLAv8i8 |
| 135265U, // MLS_ZPmZZ_B |
| 503580769U, // MLS_ZPmZZ_D |
| 103831793U, // MLS_ZPmZZ_H |
| 537137249U, // MLS_ZPmZZ_S |
| 103286848U, // MLS_ZZZI_D |
| 82161U, // MLS_ZZZI_H |
| 103288896U, // MLS_ZZZI_S |
| 18497U, // MLSv16i8 |
| 18497U, // MLSv2i32 |
| 103303233U, // MLSv2i32_indexed |
| 18497U, // MLSv4i16 |
| 103303233U, // MLSv4i16_indexed |
| 18497U, // MLSv4i32 |
| 103303233U, // MLSv4i32_indexed |
| 18497U, // MLSv8i16 |
| 103303233U, // MLSv8i16_indexed |
| 18497U, // MLSv8i8 |
| 0U, // MOPSSETGE |
| 0U, // MOPSSETGEN |
| 0U, // MOPSSETGET |
| 0U, // MOPSSETGETN |
| 6U, // MOVAZ_2ZMI_H_B |
| 6U, // MOVAZ_2ZMI_H_D |
| 6U, // MOVAZ_2ZMI_H_H |
| 6U, // MOVAZ_2ZMI_H_S |
| 6U, // MOVAZ_2ZMI_V_B |
| 6U, // MOVAZ_2ZMI_V_D |
| 6U, // MOVAZ_2ZMI_V_H |
| 6U, // MOVAZ_2ZMI_V_S |
| 6U, // MOVAZ_4ZMI_H_B |
| 6U, // MOVAZ_4ZMI_H_D |
| 6U, // MOVAZ_4ZMI_H_H |
| 6U, // MOVAZ_4ZMI_H_S |
| 6U, // MOVAZ_4ZMI_V_B |
| 6U, // MOVAZ_4ZMI_V_D |
| 6U, // MOVAZ_4ZMI_V_H |
| 6U, // MOVAZ_4ZMI_V_S |
| 7U, // MOVAZ_VG2_2ZM |
| 7U, // MOVAZ_VG4_4ZM |
| 7U, // MOVAZ_ZMI_H_B |
| 7U, // MOVAZ_ZMI_H_D |
| 137284U, // MOVAZ_ZMI_H_H |
| 137284U, // MOVAZ_ZMI_H_Q |
| 7U, // MOVAZ_ZMI_H_S |
| 7U, // MOVAZ_ZMI_V_B |
| 7U, // MOVAZ_ZMI_V_D |
| 137284U, // MOVAZ_ZMI_V_H |
| 137284U, // MOVAZ_ZMI_V_Q |
| 7U, // MOVAZ_ZMI_V_S |
| 139330U, // MOVA_2ZMXI_H_B |
| 139330U, // MOVA_2ZMXI_H_D |
| 139330U, // MOVA_2ZMXI_H_H |
| 139330U, // MOVA_2ZMXI_H_S |
| 139330U, // MOVA_2ZMXI_V_B |
| 139330U, // MOVA_2ZMXI_V_D |
| 139330U, // MOVA_2ZMXI_V_H |
| 139330U, // MOVA_2ZMXI_V_S |
| 141378U, // MOVA_4ZMXI_H_B |
| 141378U, // MOVA_4ZMXI_H_D |
| 141378U, // MOVA_4ZMXI_H_H |
| 141378U, // MOVA_4ZMXI_H_S |
| 141378U, // MOVA_4ZMXI_V_B |
| 141378U, // MOVA_4ZMXI_V_D |
| 141378U, // MOVA_4ZMXI_V_H |
| 141378U, // MOVA_4ZMXI_V_S |
| 144225U, // MOVA_MXI2Z_H_B |
| 146273U, // MOVA_MXI2Z_H_D |
| 148321U, // MOVA_MXI2Z_H_H |
| 150369U, // MOVA_MXI2Z_H_S |
| 144225U, // MOVA_MXI2Z_V_B |
| 146273U, // MOVA_MXI2Z_V_D |
| 148321U, // MOVA_MXI2Z_V_H |
| 150369U, // MOVA_MXI2Z_V_S |
| 144241U, // MOVA_MXI4Z_H_B |
| 146289U, // MOVA_MXI4Z_H_D |
| 148337U, // MOVA_MXI4Z_H_H |
| 150385U, // MOVA_MXI4Z_H_S |
| 144241U, // MOVA_MXI4Z_V_B |
| 146289U, // MOVA_MXI4Z_V_D |
| 148337U, // MOVA_MXI4Z_V_H |
| 150385U, // MOVA_MXI4Z_V_S |
| 7U, // MOVA_VG2_2ZMXI |
| 161U, // MOVA_VG2_MXI2Z |
| 7U, // MOVA_VG4_4ZMXI |
| 161U, // MOVA_VG4_MXI4Z |
| 7U, // MOVID |
| 7U, // MOVIv16b_ns |
| 7U, // MOVIv2d_ns |
| 903U, // MOVIv2i32 |
| 903U, // MOVIv2s_msl |
| 903U, // MOVIv4i16 |
| 903U, // MOVIv4i32 |
| 903U, // MOVIv4s_msl |
| 7U, // MOVIv8b_ns |
| 903U, // MOVIv8i16 |
| 2U, // MOVKWi |
| 2U, // MOVKXi |
| 903U, // MOVNWi |
| 903U, // MOVNXi |
| 16U, // MOVPRFX_ZPmZ_B |
| 32U, // MOVPRFX_ZPmZ_D |
| 0U, // MOVPRFX_ZPmZ_H |
| 48U, // MOVPRFX_ZPmZ_S |
| 20689U, // MOVPRFX_ZPzZ_B |
| 12497U, // MOVPRFX_ZPzZ_D |
| 115U, // MOVPRFX_ZPzZ_H |
| 24785U, // MOVPRFX_ZPzZ_S |
| 1U, // MOVPRFX_ZZ |
| 0U, // MOVT_TIX |
| 912U, // MOVT_XTI |
| 903U, // MOVZWi |
| 903U, // MOVZXi |
| 0U, // MRRS |
| 7U, // MRS |
| 135265U, // MSB_ZPmZZ_B |
| 503580769U, // MSB_ZPmZZ_D |
| 103831793U, // MSB_ZPmZZ_H |
| 537137249U, // MSB_ZPmZZ_S |
| 0U, // MSR |
| 0U, // MSRR |
| 0U, // MSRpstateImm1 |
| 0U, // MSRpstateImm4 |
| 0U, // MSRpstatesvcrImm1 |
| 268352U, // MSUBWrrr |
| 268352U, // MSUBXrrr |
| 6210U, // MUL_ZI_B |
| 6209U, // MUL_ZI_D |
| 225U, // MUL_ZI_H |
| 6210U, // MUL_ZI_S |
| 33837153U, // MUL_ZPmZ_B |
| 67383393U, // MUL_ZPmZ_D |
| 101210225U, // MUL_ZPmZ_H |
| 134504545U, // MUL_ZPmZ_S |
| 5255233U, // MUL_ZZZI_D |
| 84081U, // MUL_ZZZI_H |
| 5267522U, // MUL_ZZZI_S |
| 20546U, // MUL_ZZZ_B |
| 12353U, // MUL_ZZZ_D |
| 113U, // MUL_ZZZ_H |
| 24642U, // MUL_ZZZ_S |
| 16448U, // MULv16i8 |
| 16448U, // MULv2i32 |
| 5259328U, // MULv2i32_indexed |
| 16448U, // MULv4i16 |
| 5259328U, // MULv4i16_indexed |
| 16448U, // MULv4i32 |
| 5259328U, // MULv4i32_indexed |
| 16448U, // MULv8i16 |
| 5259328U, // MULv8i16_indexed |
| 16448U, // MULv8i8 |
| 903U, // MVNIv2i32 |
| 903U, // MVNIv2s_msl |
| 903U, // MVNIv4i16 |
| 903U, // MVNIv4i32 |
| 903U, // MVNIv4s_msl |
| 903U, // MVNIv8i16 |
| 33837265U, // NANDS_PPzPP |
| 33837265U, // NAND_PPzPP |
| 67383361U, // NBSL_ZZZZ |
| 16U, // NEG_ZPmZ_B |
| 32U, // NEG_ZPmZ_D |
| 0U, // NEG_ZPmZ_H |
| 48U, // NEG_ZPmZ_S |
| 0U, // NEGv16i8 |
| 0U, // NEGv1i64 |
| 0U, // NEGv2i32 |
| 0U, // NEGv2i64 |
| 0U, // NEGv4i16 |
| 0U, // NEGv4i32 |
| 0U, // NEGv8i16 |
| 0U, // NEGv8i8 |
| 33837265U, // NMATCH_PPzZZ_B |
| 101210227U, // NMATCH_PPzZZ_H |
| 33837265U, // NORS_PPzPP |
| 33837265U, // NOR_PPzPP |
| 16U, // NOT_ZPmZ_B |
| 32U, // NOT_ZPmZ_D |
| 0U, // NOT_ZPmZ_H |
| 48U, // NOT_ZPmZ_S |
| 0U, // NOTv16i8 |
| 0U, // NOTv8i8 |
| 33837265U, // ORNS_PPzPP |
| 28736U, // ORNWrs |
| 28736U, // ORNXrs |
| 33837265U, // ORN_PPzPP |
| 16448U, // ORNv16i8 |
| 16448U, // ORNv8i8 |
| 20545U, // ORQV_VPZ_B |
| 12353U, // ORQV_VPZ_D |
| 10305U, // ORQV_VPZ_H |
| 24641U, // ORQV_VPZ_S |
| 33837265U, // ORRS_PPzPP |
| 71744U, // ORRWri |
| 28736U, // ORRWrs |
| 73792U, // ORRXri |
| 28736U, // ORRXrs |
| 33837265U, // ORR_PPzPP |
| 73793U, // ORR_ZI |
| 33837153U, // ORR_ZPmZ_B |
| 67383393U, // ORR_ZPmZ_D |
| 101210225U, // ORR_ZPmZ_H |
| 134504545U, // ORR_ZPmZ_S |
| 12353U, // ORR_ZZZ |
| 16448U, // ORRv16i8 |
| 2U, // ORRv2i32 |
| 2U, // ORRv4i16 |
| 2U, // ORRv4i32 |
| 2U, // ORRv8i16 |
| 16448U, // ORRv8i8 |
| 0U, // ORV_VPZ_B |
| 0U, // ORV_VPZ_D |
| 0U, // ORV_VPZ_H |
| 0U, // ORV_VPZ_S |
| 2U, // PACDA |
| 2U, // PACDB |
| 0U, // PACDZA |
| 0U, // PACDZB |
| 6208U, // PACGA |
| 2U, // PACIA |
| 0U, // PACIA1716 |
| 0U, // PACIASP |
| 0U, // PACIAZ |
| 2U, // PACIB |
| 0U, // PACIB1716 |
| 0U, // PACIBSP |
| 0U, // PACIBZ |
| 0U, // PACIZA |
| 0U, // PACIZB |
| 4U, // PEXT_2PCI_B |
| 4U, // PEXT_2PCI_D |
| 4U, // PEXT_2PCI_H |
| 4U, // PEXT_2PCI_S |
| 486U, // PEXT_PCI_B |
| 486U, // PEXT_PCI_D |
| 4U, // PEXT_PCI_H |
| 486U, // PEXT_PCI_S |
| 0U, // PFALSE |
| 20545U, // PFIRST_B |
| 481U, // PMOV_PZI_B |
| 481U, // PMOV_PZI_D |
| 4U, // PMOV_PZI_H |
| 481U, // PMOV_PZI_S |
| 7U, // PMOV_ZIP_B |
| 5U, // PMOV_ZIP_D |
| 0U, // PMOV_ZIP_H |
| 2U, // PMOV_ZIP_S |
| 24642U, // PMULLB_ZZZ_D |
| 129U, // PMULLB_ZZZ_H |
| 0U, // PMULLB_ZZZ_Q |
| 24642U, // PMULLT_ZZZ_D |
| 129U, // PMULLT_ZZZ_H |
| 0U, // PMULLT_ZZZ_Q |
| 16448U, // PMULLv16i8 |
| 16448U, // PMULLv1i64 |
| 16448U, // PMULLv2i64 |
| 16448U, // PMULLv8i8 |
| 20546U, // PMUL_ZZZ_B |
| 16448U, // PMULv16i8 |
| 16448U, // PMULv8i8 |
| 20545U, // PNEXT_B |
| 12353U, // PNEXT_D |
| 113U, // PNEXT_H |
| 24641U, // PNEXT_S |
| 152001U, // PRFB_D_PZI |
| 929U, // PRFB_D_SCALED |
| 945U, // PRFB_D_SXTW_SCALED |
| 961U, // PRFB_D_UXTW_SCALED |
| 154049U, // PRFB_PRI |
| 977U, // PRFB_PRR |
| 152001U, // PRFB_S_PZI |
| 993U, // PRFB_S_SXTW_SCALED |
| 1009U, // PRFB_S_UXTW_SCALED |
| 1025U, // PRFD_D_PZI |
| 1041U, // PRFD_D_SCALED |
| 1057U, // PRFD_D_SXTW_SCALED |
| 1073U, // PRFD_D_UXTW_SCALED |
| 154049U, // PRFD_PRI |
| 1089U, // PRFD_PRR |
| 1025U, // PRFD_S_PZI |
| 1105U, // PRFD_S_SXTW_SCALED |
| 1121U, // PRFD_S_UXTW_SCALED |
| 1137U, // PRFH_D_PZI |
| 1153U, // PRFH_D_SCALED |
| 1169U, // PRFH_D_SXTW_SCALED |
| 1185U, // PRFH_D_UXTW_SCALED |
| 154049U, // PRFH_PRI |
| 1201U, // PRFH_PRR |
| 1137U, // PRFH_S_PZI |
| 1217U, // PRFH_S_SXTW_SCALED |
| 1233U, // PRFH_S_UXTW_SCALED |
| 2U, // PRFMl |
| 1006901312U, // PRFMroW |
| 1040455744U, // PRFMroX |
| 124992U, // PRFMui |
| 3676224U, // PRFUMi |
| 1249U, // PRFW_D_PZI |
| 1265U, // PRFW_D_SCALED |
| 1281U, // PRFW_D_SXTW_SCALED |
| 1297U, // PRFW_D_UXTW_SCALED |
| 154049U, // PRFW_PRI |
| 1313U, // PRFW_PRR |
| 1249U, // PRFW_S_PZI |
| 1329U, // PRFW_S_SXTW_SCALED |
| 1345U, // PRFW_S_UXTW_SCALED |
| 16011329U, // PSEL_PPPRI_B |
| 16003137U, // PSEL_PPPRI_D |
| 16001089U, // PSEL_PPPRI_H |
| 16015425U, // PSEL_PPPRI_S |
| 2U, // PTEST_PP |
| 3U, // PTRUES_B |
| 3U, // PTRUES_D |
| 0U, // PTRUES_H |
| 3U, // PTRUES_S |
| 3U, // PTRUE_B |
| 0U, // PTRUE_C_B |
| 0U, // PTRUE_C_D |
| 0U, // PTRUE_C_H |
| 0U, // PTRUE_C_S |
| 3U, // PTRUE_D |
| 0U, // PTRUE_H |
| 3U, // PTRUE_S |
| 0U, // PUNPKHI_PP |
| 0U, // PUNPKLO_PP |
| 10304U, // RADDHNB_ZZZ_B |
| 81U, // RADDHNB_ZZZ_H |
| 12353U, // RADDHNB_ZZZ_S |
| 14401U, // RADDHNT_ZZZ_B |
| 49U, // RADDHNT_ZZZ_H |
| 2112U, // RADDHNT_ZZZ_S |
| 16448U, // RADDHNv2i64_v2i32 |
| 18497U, // RADDHNv2i64_v4i32 |
| 16448U, // RADDHNv4i32_v4i16 |
| 18497U, // RADDHNv4i32_v8i16 |
| 18497U, // RADDHNv8i16_v16i8 |
| 16448U, // RADDHNv8i16_v8i8 |
| 16448U, // RAX1 |
| 12353U, // RAX1_ZZZ_D |
| 0U, // RBITWr |
| 0U, // RBITXr |
| 16U, // RBIT_ZPmZ_B |
| 32U, // RBIT_ZPmZ_D |
| 0U, // RBIT_ZPmZ_H |
| 48U, // RBIT_ZPmZ_S |
| 0U, // RBITv16i8 |
| 0U, // RBITv8i8 |
| 3756386U, // RCWCAS |
| 3756386U, // RCWCASA |
| 3756386U, // RCWCASAL |
| 3756386U, // RCWCASL |
| 0U, // RCWCASP |
| 0U, // RCWCASPA |
| 0U, // RCWCASPAL |
| 0U, // RCWCASPL |
| 6U, // RCWCLR |
| 6U, // RCWCLRA |
| 6U, // RCWCLRAL |
| 6U, // RCWCLRL |
| 115044U, // RCWCLRP |
| 115044U, // RCWCLRPA |
| 115044U, // RCWCLRPAL |
| 115044U, // RCWCLRPL |
| 6U, // RCWCLRS |
| 6U, // RCWCLRSA |
| 6U, // RCWCLRSAL |
| 6U, // RCWCLRSL |
| 115044U, // RCWCLRSP |
| 115044U, // RCWCLRSPA |
| 115044U, // RCWCLRSPAL |
| 115044U, // RCWCLRSPL |
| 3756386U, // RCWSCAS |
| 3756386U, // RCWSCASA |
| 3756386U, // RCWSCASAL |
| 3756386U, // RCWSCASL |
| 0U, // RCWSCASP |
| 0U, // RCWSCASPA |
| 0U, // RCWSCASPAL |
| 0U, // RCWSCASPL |
| 6U, // RCWSET |
| 6U, // RCWSETA |
| 6U, // RCWSETAL |
| 6U, // RCWSETL |
| 115044U, // RCWSETP |
| 115044U, // RCWSETPA |
| 115044U, // RCWSETPAL |
| 115044U, // RCWSETPL |
| 6U, // RCWSETS |
| 6U, // RCWSETSA |
| 6U, // RCWSETSAL |
| 6U, // RCWSETSL |
| 115044U, // RCWSETSP |
| 115044U, // RCWSETSPA |
| 115044U, // RCWSETSPAL |
| 115044U, // RCWSETSPL |
| 6U, // RCWSWP |
| 6U, // RCWSWPA |
| 6U, // RCWSWPAL |
| 6U, // RCWSWPL |
| 115044U, // RCWSWPP |
| 115044U, // RCWSWPPA |
| 115044U, // RCWSWPPAL |
| 115044U, // RCWSWPPL |
| 6U, // RCWSWPS |
| 6U, // RCWSWPSA |
| 6U, // RCWSWPSAL |
| 6U, // RCWSWPSL |
| 115044U, // RCWSWPSP |
| 115044U, // RCWSWPSPA |
| 115044U, // RCWSWPSPAL |
| 115044U, // RCWSWPSPL |
| 1361U, // RDFFRS_PPz |
| 1361U, // RDFFR_PPz_REAL |
| 0U, // RDFFR_P_REAL |
| 0U, // RDSVLI_XI |
| 0U, // RDVLI_XI |
| 0U, // RET |
| 0U, // RETAA |
| 0U, // RETAB |
| 0U, // REV16Wr |
| 0U, // REV16Xr |
| 0U, // REV16v16i8 |
| 0U, // REV16v8i8 |
| 0U, // REV32Xr |
| 0U, // REV32v16i8 |
| 0U, // REV32v4i16 |
| 0U, // REV32v8i16 |
| 0U, // REV32v8i8 |
| 0U, // REV64v16i8 |
| 0U, // REV64v2i32 |
| 0U, // REV64v4i16 |
| 0U, // REV64v4i32 |
| 0U, // REV64v8i16 |
| 0U, // REV64v8i8 |
| 32U, // REVB_ZPmZ_D |
| 0U, // REVB_ZPmZ_H |
| 48U, // REVB_ZPmZ_S |
| 8U, // REVD_ZPmZ |
| 32U, // REVH_ZPmZ_D |
| 48U, // REVH_ZPmZ_S |
| 32U, // REVW_ZPmZ_D |
| 0U, // REVWr |
| 0U, // REVXr |
| 2U, // REV_PP_B |
| 1U, // REV_PP_D |
| 0U, // REV_PP_H |
| 2U, // REV_PP_S |
| 2U, // REV_ZZ_B |
| 1U, // REV_ZZ_D |
| 0U, // REV_ZZ_H |
| 2U, // REV_ZZ_S |
| 0U, // RMIF |
| 6208U, // RORVWr |
| 6208U, // RORVXr |
| 0U, // RPRFM |
| 6208U, // RSHRNB_ZZI_B |
| 225U, // RSHRNB_ZZI_H |
| 6209U, // RSHRNB_ZZI_S |
| 86081U, // RSHRNT_ZZI_B |
| 449U, // RSHRNT_ZZI_H |
| 86080U, // RSHRNT_ZZI_S |
| 86081U, // RSHRNv16i8_shift |
| 6208U, // RSHRNv2i32_shift |
| 6208U, // RSHRNv4i16_shift |
| 86081U, // RSHRNv4i32_shift |
| 86081U, // RSHRNv8i16_shift |
| 6208U, // RSHRNv8i8_shift |
| 10304U, // RSUBHNB_ZZZ_B |
| 81U, // RSUBHNB_ZZZ_H |
| 12353U, // RSUBHNB_ZZZ_S |
| 14401U, // RSUBHNT_ZZZ_B |
| 49U, // RSUBHNT_ZZZ_H |
| 2112U, // RSUBHNT_ZZZ_S |
| 16448U, // RSUBHNv2i64_v2i32 |
| 18497U, // RSUBHNv2i64_v4i32 |
| 16448U, // RSUBHNv4i32_v4i16 |
| 18497U, // RSUBHNv4i32_v8i16 |
| 18497U, // RSUBHNv8i16_v16i8 |
| 16448U, // RSUBHNv8i16_v8i8 |
| 4160U, // SABALB_ZZZ_D |
| 17U, // SABALB_ZZZ_H |
| 14401U, // SABALB_ZZZ_S |
| 4160U, // SABALT_ZZZ_D |
| 17U, // SABALT_ZZZ_H |
| 14401U, // SABALT_ZZZ_S |
| 18497U, // SABALv16i8_v8i16 |
| 18497U, // SABALv2i32_v2i64 |
| 18497U, // SABALv4i16_v4i32 |
| 18497U, // SABALv4i32_v2i64 |
| 18497U, // SABALv8i16_v4i32 |
| 18497U, // SABALv8i8_v8i16 |
| 19U, // SABA_ZZZ_B |
| 2112U, // SABA_ZZZ_D |
| 241U, // SABA_ZZZ_H |
| 4160U, // SABA_ZZZ_S |
| 18497U, // SABAv16i8 |
| 18497U, // SABAv2i32 |
| 18497U, // SABAv4i16 |
| 18497U, // SABAv4i32 |
| 18497U, // SABAv8i16 |
| 18497U, // SABAv8i8 |
| 24642U, // SABDLB_ZZZ_D |
| 129U, // SABDLB_ZZZ_H |
| 10304U, // SABDLB_ZZZ_S |
| 24642U, // SABDLT_ZZZ_D |
| 129U, // SABDLT_ZZZ_H |
| 10304U, // SABDLT_ZZZ_S |
| 16448U, // SABDLv16i8_v8i16 |
| 16448U, // SABDLv2i32_v2i64 |
| 16448U, // SABDLv4i16_v4i32 |
| 16448U, // SABDLv4i32_v2i64 |
| 16448U, // SABDLv8i16_v4i32 |
| 16448U, // SABDLv8i8_v8i16 |
| 33837153U, // SABD_ZPmZ_B |
| 67383393U, // SABD_ZPmZ_D |
| 101210225U, // SABD_ZPmZ_H |
| 134504545U, // SABD_ZPmZ_S |
| 16448U, // SABDv16i8 |
| 16448U, // SABDv2i32 |
| 16448U, // SABDv4i16 |
| 16448U, // SABDv4i32 |
| 16448U, // SABDv8i16 |
| 16448U, // SABDv8i8 |
| 4193U, // SADALP_ZPmZ_D |
| 17U, // SADALP_ZPmZ_H |
| 14433U, // SADALP_ZPmZ_S |
| 1U, // SADALPv16i8_v8i16 |
| 1U, // SADALPv2i32_v1i64 |
| 1U, // SADALPv4i16_v2i32 |
| 1U, // SADALPv4i32_v2i64 |
| 1U, // SADALPv8i16_v4i32 |
| 1U, // SADALPv8i8_v4i16 |
| 24642U, // SADDLBT_ZZZ_D |
| 129U, // SADDLBT_ZZZ_H |
| 10304U, // SADDLBT_ZZZ_S |
| 24642U, // SADDLB_ZZZ_D |
| 129U, // SADDLB_ZZZ_H |
| 10304U, // SADDLB_ZZZ_S |
| 0U, // SADDLPv16i8_v8i16 |
| 0U, // SADDLPv2i32_v1i64 |
| 0U, // SADDLPv4i16_v2i32 |
| 0U, // SADDLPv4i32_v2i64 |
| 0U, // SADDLPv8i16_v4i32 |
| 0U, // SADDLPv8i8_v4i16 |
| 24642U, // SADDLT_ZZZ_D |
| 129U, // SADDLT_ZZZ_H |
| 10304U, // SADDLT_ZZZ_S |
| 0U, // SADDLVv16i8v |
| 0U, // SADDLVv4i16v |
| 0U, // SADDLVv4i32v |
| 0U, // SADDLVv8i16v |
| 0U, // SADDLVv8i8v |
| 16448U, // SADDLv16i8_v8i16 |
| 16448U, // SADDLv2i32_v2i64 |
| 16448U, // SADDLv4i16_v4i32 |
| 16448U, // SADDLv4i32_v2i64 |
| 16448U, // SADDLv8i16_v4i32 |
| 16448U, // SADDLv8i8_v8i16 |
| 0U, // SADDV_VPZ_B |
| 0U, // SADDV_VPZ_H |
| 0U, // SADDV_VPZ_S |
| 24641U, // SADDWB_ZZZ_D |
| 129U, // SADDWB_ZZZ_H |
| 10306U, // SADDWB_ZZZ_S |
| 24641U, // SADDWT_ZZZ_D |
| 129U, // SADDWT_ZZZ_H |
| 10306U, // SADDWT_ZZZ_S |
| 16448U, // SADDWv16i8_v8i16 |
| 16448U, // SADDWv2i32_v2i64 |
| 16448U, // SADDWv4i16_v4i32 |
| 16448U, // SADDWv4i32_v2i64 |
| 16448U, // SADDWv8i16_v4i32 |
| 16448U, // SADDWv8i8_v8i16 |
| 0U, // SB |
| 2112U, // SBCLB_ZZZ_D |
| 4160U, // SBCLB_ZZZ_S |
| 2112U, // SBCLT_ZZZ_D |
| 4160U, // SBCLT_ZZZ_S |
| 6208U, // SBCSWr |
| 6208U, // SBCSXr |
| 6208U, // SBCWr |
| 6208U, // SBCXr |
| 268352U, // SBFMWri |
| 268352U, // SBFMXri |
| 17U, // SCLAMP_VG2_2Z2Z_B |
| 33U, // SCLAMP_VG2_2Z2Z_D |
| 241U, // SCLAMP_VG2_2Z2Z_H |
| 49U, // SCLAMP_VG2_2Z2Z_S |
| 17U, // SCLAMP_VG4_4Z4Z_B |
| 33U, // SCLAMP_VG4_4Z4Z_D |
| 241U, // SCLAMP_VG4_4Z4Z_H |
| 49U, // SCLAMP_VG4_4Z4Z_S |
| 20546U, // SCLAMP_ZZZ_B |
| 12353U, // SCLAMP_ZZZ_D |
| 113U, // SCLAMP_ZZZ_H |
| 24642U, // SCLAMP_ZZZ_S |
| 6208U, // SCVTFSWDri |
| 6208U, // SCVTFSWHri |
| 6208U, // SCVTFSWSri |
| 6208U, // SCVTFSXDri |
| 6208U, // SCVTFSXHri |
| 6208U, // SCVTFSXSri |
| 0U, // SCVTFUWDri |
| 0U, // SCVTFUWHri |
| 0U, // SCVTFUWSri |
| 0U, // SCVTFUXDri |
| 0U, // SCVTFUXHri |
| 0U, // SCVTFUXSri |
| 0U, // SCVTF_2Z2Z_StoS |
| 0U, // SCVTF_4Z4Z_StoS |
| 32U, // SCVTF_ZPmZ_DtoD |
| 5U, // SCVTF_ZPmZ_DtoH |
| 32U, // SCVTF_ZPmZ_DtoS |
| 0U, // SCVTF_ZPmZ_HtoH |
| 48U, // SCVTF_ZPmZ_StoD |
| 2U, // SCVTF_ZPmZ_StoH |
| 48U, // SCVTF_ZPmZ_StoS |
| 6208U, // SCVTFd |
| 6208U, // SCVTFh |
| 6208U, // SCVTFs |
| 0U, // SCVTFv1i16 |
| 0U, // SCVTFv1i32 |
| 0U, // SCVTFv1i64 |
| 0U, // SCVTFv2f32 |
| 0U, // SCVTFv2f64 |
| 6208U, // SCVTFv2i32_shift |
| 6208U, // SCVTFv2i64_shift |
| 0U, // SCVTFv4f16 |
| 0U, // SCVTFv4f32 |
| 6208U, // SCVTFv4i16_shift |
| 6208U, // SCVTFv4i32_shift |
| 0U, // SCVTFv8f16 |
| 6208U, // SCVTFv8i16_shift |
| 67383393U, // SDIVR_ZPmZ_D |
| 134504545U, // SDIVR_ZPmZ_S |
| 6208U, // SDIVWr |
| 6208U, // SDIVXr |
| 67383393U, // SDIV_ZPmZ_D |
| 134504545U, // SDIV_ZPmZ_S |
| 157025U, // SDOT_VG2_M2Z2Z_BtoS |
| 76033U, // SDOT_VG2_M2Z2Z_HtoD |
| 76033U, // SDOT_VG2_M2Z2Z_HtoS |
| 2983265U, // SDOT_VG2_M2ZZI_BToS |
| 2961665U, // SDOT_VG2_M2ZZI_HToS |
| 2961665U, // SDOT_VG2_M2ZZI_HtoD |
| 99681U, // SDOT_VG2_M2ZZ_BtoS |
| 78081U, // SDOT_VG2_M2ZZ_HtoD |
| 78081U, // SDOT_VG2_M2ZZ_HtoS |
| 157025U, // SDOT_VG4_M4Z4Z_BtoS |
| 76033U, // SDOT_VG4_M4Z4Z_HtoD |
| 76033U, // SDOT_VG4_M4Z4Z_HtoS |
| 2983265U, // SDOT_VG4_M4ZZI_BToS |
| 2961665U, // SDOT_VG4_M4ZZI_HToS |
| 2961665U, // SDOT_VG4_M4ZZI_HtoD |
| 99681U, // SDOT_VG4_M4ZZ_BtoS |
| 78081U, // SDOT_VG4_M4ZZ_HtoD |
| 78081U, // SDOT_VG4_M4ZZ_HtoS |
| 103299137U, // SDOT_ZZZI_D |
| 103299137U, // SDOT_ZZZI_HtoS |
| 81939U, // SDOT_ZZZI_S |
| 14401U, // SDOT_ZZZ_D |
| 14401U, // SDOT_ZZZ_HtoS |
| 19U, // SDOT_ZZZ_S |
| 103303233U, // SDOTlanev16i8 |
| 103303233U, // SDOTlanev8i8 |
| 0U, // SDOTv16i8 |
| 0U, // SDOTv8i8 |
| 33837121U, // SEL_PPPP |
| 16276849U, // SEL_VG2_2ZP2Z2Z_B |
| 16538257U, // SEL_VG2_2ZP2Z2Z_D |
| 16800017U, // SEL_VG2_2ZP2Z2Z_H |
| 17062561U, // SEL_VG2_2ZP2Z2Z_S |
| 16276849U, // SEL_VG4_4ZP4Z4Z_B |
| 16538257U, // SEL_VG4_4ZP4Z4Z_D |
| 16800017U, // SEL_VG4_4ZP4Z4Z_H |
| 17062561U, // SEL_VG4_4ZP4Z4Z_S |
| 33837121U, // SEL_ZPZZ_B |
| 67383361U, // SEL_ZPZZ_D |
| 101210225U, // SEL_ZPZZ_H |
| 134504513U, // SEL_ZPZZ_S |
| 0U, // SETE |
| 0U, // SETEN |
| 0U, // SETET |
| 0U, // SETETN |
| 0U, // SETF16 |
| 0U, // SETF8 |
| 0U, // SETFFR |
| 0U, // SETGM |
| 0U, // SETGMN |
| 0U, // SETGMT |
| 0U, // SETGMTN |
| 0U, // SETGP |
| 0U, // SETGPN |
| 0U, // SETGPT |
| 0U, // SETGPTN |
| 0U, // SETM |
| 0U, // SETMN |
| 0U, // SETMT |
| 0U, // SETMTN |
| 0U, // SETP |
| 0U, // SETPN |
| 0U, // SETPT |
| 0U, // SETPTN |
| 18498U, // SHA1Crrr |
| 0U, // SHA1Hrr |
| 18498U, // SHA1Mrrr |
| 18498U, // SHA1Prrr |
| 18497U, // SHA1SU0rrr |
| 1U, // SHA1SU1rr |
| 18498U, // SHA256H2rrr |
| 18498U, // SHA256Hrrr |
| 1U, // SHA256SU0rr |
| 18497U, // SHA256SU1rrr |
| 18498U, // SHA512H |
| 18498U, // SHA512H2 |
| 1U, // SHA512SU0 |
| 18497U, // SHA512SU1 |
| 33837153U, // SHADD_ZPmZ_B |
| 67383393U, // SHADD_ZPmZ_D |
| 101210225U, // SHADD_ZPmZ_H |
| 134504545U, // SHADD_ZPmZ_S |
| 16448U, // SHADDv16i8 |
| 16448U, // SHADDv2i32 |
| 16448U, // SHADDv4i16 |
| 16448U, // SHADDv4i32 |
| 16448U, // SHADDv8i16 |
| 16448U, // SHADDv8i8 |
| 1408U, // SHLLv16i8 |
| 1424U, // SHLLv2i32 |
| 1440U, // SHLLv4i16 |
| 1424U, // SHLLv4i32 |
| 1440U, // SHLLv8i16 |
| 1408U, // SHLLv8i8 |
| 6208U, // SHLd |
| 6208U, // SHLv16i8_shift |
| 6208U, // SHLv2i32_shift |
| 6208U, // SHLv2i64_shift |
| 6208U, // SHLv4i16_shift |
| 6208U, // SHLv4i32_shift |
| 6208U, // SHLv8i16_shift |
| 6208U, // SHLv8i8_shift |
| 6208U, // SHRNB_ZZI_B |
| 225U, // SHRNB_ZZI_H |
| 6209U, // SHRNB_ZZI_S |
| 86081U, // SHRNT_ZZI_B |
| 449U, // SHRNT_ZZI_H |
| 86080U, // SHRNT_ZZI_S |
| 86081U, // SHRNv16i8_shift |
| 6208U, // SHRNv2i32_shift |
| 6208U, // SHRNv4i16_shift |
| 86081U, // SHRNv4i32_shift |
| 86081U, // SHRNv8i16_shift |
| 6208U, // SHRNv8i8_shift |
| 33837153U, // SHSUBR_ZPmZ_B |
| 67383393U, // SHSUBR_ZPmZ_D |
| 101210225U, // SHSUBR_ZPmZ_H |
| 134504545U, // SHSUBR_ZPmZ_S |
| 33837153U, // SHSUB_ZPmZ_B |
| 67383393U, // SHSUB_ZPmZ_D |
| 101210225U, // SHSUB_ZPmZ_H |
| 134504545U, // SHSUB_ZPmZ_S |
| 16448U, // SHSUBv16i8 |
| 16448U, // SHSUBv2i32 |
| 16448U, // SHSUBv4i16 |
| 16448U, // SHSUBv4i32 |
| 16448U, // SHSUBv8i16 |
| 16448U, // SHSUBv8i8 |
| 451U, // SLI_ZZI_B |
| 86080U, // SLI_ZZI_D |
| 449U, // SLI_ZZI_H |
| 86080U, // SLI_ZZI_S |
| 86082U, // SLId |
| 86081U, // SLIv16i8_shift |
| 86081U, // SLIv2i32_shift |
| 86081U, // SLIv2i64_shift |
| 86081U, // SLIv4i16_shift |
| 86081U, // SLIv4i32_shift |
| 86081U, // SLIv8i16_shift |
| 86081U, // SLIv8i8_shift |
| 18497U, // SM3PARTW1 |
| 18497U, // SM3PARTW2 |
| 168050752U, // SM3SS1 |
| 103303233U, // SM3TT1A |
| 103303233U, // SM3TT1B |
| 103303233U, // SM3TT2A |
| 103303233U, // SM3TT2B |
| 1U, // SM4E |
| 24642U, // SM4EKEY_ZZZ_S |
| 16448U, // SM4ENCKEY |
| 24642U, // SM4E_ZZZ_S |
| 268352U, // SMADDLrrr |
| 33837153U, // SMAXP_ZPmZ_B |
| 67383393U, // SMAXP_ZPmZ_D |
| 101210225U, // SMAXP_ZPmZ_H |
| 134504545U, // SMAXP_ZPmZ_S |
| 16448U, // SMAXPv16i8 |
| 16448U, // SMAXPv2i32 |
| 16448U, // SMAXPv4i16 |
| 16448U, // SMAXPv4i32 |
| 16448U, // SMAXPv8i16 |
| 16448U, // SMAXPv8i8 |
| 20545U, // SMAXQV_VPZ_B |
| 12353U, // SMAXQV_VPZ_D |
| 10305U, // SMAXQV_VPZ_H |
| 24641U, // SMAXQV_VPZ_S |
| 0U, // SMAXV_VPZ_B |
| 0U, // SMAXV_VPZ_D |
| 0U, // SMAXV_VPZ_H |
| 0U, // SMAXV_VPZ_S |
| 0U, // SMAXVv16i8v |
| 0U, // SMAXVv4i16v |
| 0U, // SMAXVv4i32v |
| 0U, // SMAXVv8i16v |
| 0U, // SMAXVv8i8v |
| 6208U, // SMAXWri |
| 6208U, // SMAXWrr |
| 6208U, // SMAXXri |
| 6208U, // SMAXXrr |
| 1393U, // SMAX_VG2_2Z2Z_B |
| 657U, // SMAX_VG2_2Z2Z_D |
| 273U, // SMAX_VG2_2Z2Z_H |
| 673U, // SMAX_VG2_2Z2Z_S |
| 129U, // SMAX_VG2_2ZZ_B |
| 145U, // SMAX_VG2_2ZZ_D |
| 113U, // SMAX_VG2_2ZZ_H |
| 81U, // SMAX_VG2_2ZZ_S |
| 1393U, // SMAX_VG4_4Z4Z_B |
| 657U, // SMAX_VG4_4Z4Z_D |
| 273U, // SMAX_VG4_4Z4Z_H |
| 673U, // SMAX_VG4_4Z4Z_S |
| 129U, // SMAX_VG4_4ZZ_B |
| 145U, // SMAX_VG4_4ZZ_D |
| 113U, // SMAX_VG4_4ZZ_H |
| 81U, // SMAX_VG4_4ZZ_S |
| 6210U, // SMAX_ZI_B |
| 6209U, // SMAX_ZI_D |
| 225U, // SMAX_ZI_H |
| 6210U, // SMAX_ZI_S |
| 33837153U, // SMAX_ZPmZ_B |
| 67383393U, // SMAX_ZPmZ_D |
| 101210225U, // SMAX_ZPmZ_H |
| 134504545U, // SMAX_ZPmZ_S |
| 16448U, // SMAXv16i8 |
| 16448U, // SMAXv2i32 |
| 16448U, // SMAXv4i16 |
| 16448U, // SMAXv4i32 |
| 16448U, // SMAXv8i16 |
| 16448U, // SMAXv8i8 |
| 0U, // SMC |
| 33837153U, // SMINP_ZPmZ_B |
| 67383393U, // SMINP_ZPmZ_D |
| 101210225U, // SMINP_ZPmZ_H |
| 134504545U, // SMINP_ZPmZ_S |
| 16448U, // SMINPv16i8 |
| 16448U, // SMINPv2i32 |
| 16448U, // SMINPv4i16 |
| 16448U, // SMINPv4i32 |
| 16448U, // SMINPv8i16 |
| 16448U, // SMINPv8i8 |
| 20545U, // SMINQV_VPZ_B |
| 12353U, // SMINQV_VPZ_D |
| 10305U, // SMINQV_VPZ_H |
| 24641U, // SMINQV_VPZ_S |
| 0U, // SMINV_VPZ_B |
| 0U, // SMINV_VPZ_D |
| 0U, // SMINV_VPZ_H |
| 0U, // SMINV_VPZ_S |
| 0U, // SMINVv16i8v |
| 0U, // SMINVv4i16v |
| 0U, // SMINVv4i32v |
| 0U, // SMINVv8i16v |
| 0U, // SMINVv8i8v |
| 6208U, // SMINWri |
| 6208U, // SMINWrr |
| 6208U, // SMINXri |
| 6208U, // SMINXrr |
| 1393U, // SMIN_VG2_2Z2Z_B |
| 657U, // SMIN_VG2_2Z2Z_D |
| 273U, // SMIN_VG2_2Z2Z_H |
| 673U, // SMIN_VG2_2Z2Z_S |
| 129U, // SMIN_VG2_2ZZ_B |
| 145U, // SMIN_VG2_2ZZ_D |
| 113U, // SMIN_VG2_2ZZ_H |
| 81U, // SMIN_VG2_2ZZ_S |
| 1393U, // SMIN_VG4_4Z4Z_B |
| 657U, // SMIN_VG4_4Z4Z_D |
| 273U, // SMIN_VG4_4Z4Z_H |
| 673U, // SMIN_VG4_4Z4Z_S |
| 129U, // SMIN_VG4_4ZZ_B |
| 145U, // SMIN_VG4_4ZZ_D |
| 113U, // SMIN_VG4_4ZZ_H |
| 81U, // SMIN_VG4_4ZZ_S |
| 6210U, // SMIN_ZI_B |
| 6209U, // SMIN_ZI_D |
| 225U, // SMIN_ZI_H |
| 6210U, // SMIN_ZI_S |
| 33837153U, // SMIN_ZPmZ_B |
| 67383393U, // SMIN_ZPmZ_D |
| 101210225U, // SMIN_ZPmZ_H |
| 134504545U, // SMIN_ZPmZ_S |
| 16448U, // SMINv16i8 |
| 16448U, // SMINv2i32 |
| 16448U, // SMINv4i16 |
| 16448U, // SMINv4i32 |
| 16448U, // SMINv8i16 |
| 16448U, // SMINv8i8 |
| 103288896U, // SMLALB_ZZZI_D |
| 103299137U, // SMLALB_ZZZI_S |
| 4160U, // SMLALB_ZZZ_D |
| 17U, // SMLALB_ZZZ_H |
| 14401U, // SMLALB_ZZZ_S |
| 81330U, // SMLALL_MZZI_BtoS |
| 80162U, // SMLALL_MZZI_HtoD |
| 1458U, // SMLALL_MZZ_BtoS |
| 290U, // SMLALL_MZZ_HtoD |
| 157025U, // SMLALL_VG2_M2Z2Z_BtoS |
| 76033U, // SMLALL_VG2_M2Z2Z_HtoD |
| 2983265U, // SMLALL_VG2_M2ZZI_BtoS |
| 2961665U, // SMLALL_VG2_M2ZZI_HtoD |
| 99688U, // SMLALL_VG2_M2ZZ_BtoS |
| 78088U, // SMLALL_VG2_M2ZZ_HtoD |
| 157025U, // SMLALL_VG4_M4Z4Z_BtoS |
| 76033U, // SMLALL_VG4_M4Z4Z_HtoD |
| 2983265U, // SMLALL_VG4_M4ZZI_BtoS |
| 2961665U, // SMLALL_VG4_M4ZZI_HtoD |
| 99688U, // SMLALL_VG4_M4ZZ_BtoS |
| 78088U, // SMLALL_VG4_M4ZZ_HtoD |
| 103288896U, // SMLALT_ZZZI_D |
| 103299137U, // SMLALT_ZZZI_S |
| 4160U, // SMLALT_ZZZ_D |
| 17U, // SMLALT_ZZZ_H |
| 14401U, // SMLALT_ZZZ_S |
| 80162U, // SMLAL_MZZI_S |
| 290U, // SMLAL_MZZ_S |
| 76033U, // SMLAL_VG2_M2Z2Z_S |
| 2961665U, // SMLAL_VG2_M2ZZI_S |
| 78081U, // SMLAL_VG2_M2ZZ_S |
| 76033U, // SMLAL_VG4_M4Z4Z_S |
| 2961665U, // SMLAL_VG4_M4ZZI_S |
| 78081U, // SMLAL_VG4_M4ZZ_S |
| 18497U, // SMLALv16i8_v8i16 |
| 103303233U, // SMLALv2i32_indexed |
| 18497U, // SMLALv2i32_v2i64 |
| 103303233U, // SMLALv4i16_indexed |
| 18497U, // SMLALv4i16_v4i32 |
| 103303233U, // SMLALv4i32_indexed |
| 18497U, // SMLALv4i32_v2i64 |
| 103303233U, // SMLALv8i16_indexed |
| 18497U, // SMLALv8i16_v4i32 |
| 18497U, // SMLALv8i8_v8i16 |
| 103288896U, // SMLSLB_ZZZI_D |
| 103299137U, // SMLSLB_ZZZI_S |
| 4160U, // SMLSLB_ZZZ_D |
| 17U, // SMLSLB_ZZZ_H |
| 14401U, // SMLSLB_ZZZ_S |
| 81330U, // SMLSLL_MZZI_BtoS |
| 80162U, // SMLSLL_MZZI_HtoD |
| 1458U, // SMLSLL_MZZ_BtoS |
| 290U, // SMLSLL_MZZ_HtoD |
| 157025U, // SMLSLL_VG2_M2Z2Z_BtoS |
| 76033U, // SMLSLL_VG2_M2Z2Z_HtoD |
| 2983265U, // SMLSLL_VG2_M2ZZI_BtoS |
| 2961665U, // SMLSLL_VG2_M2ZZI_HtoD |
| 99688U, // SMLSLL_VG2_M2ZZ_BtoS |
| 78088U, // SMLSLL_VG2_M2ZZ_HtoD |
| 157025U, // SMLSLL_VG4_M4Z4Z_BtoS |
| 76033U, // SMLSLL_VG4_M4Z4Z_HtoD |
| 2983265U, // SMLSLL_VG4_M4ZZI_BtoS |
| 2961665U, // SMLSLL_VG4_M4ZZI_HtoD |
| 99688U, // SMLSLL_VG4_M4ZZ_BtoS |
| 78088U, // SMLSLL_VG4_M4ZZ_HtoD |
| 103288896U, // SMLSLT_ZZZI_D |
| 103299137U, // SMLSLT_ZZZI_S |
| 4160U, // SMLSLT_ZZZ_D |
| 17U, // SMLSLT_ZZZ_H |
| 14401U, // SMLSLT_ZZZ_S |
| 80162U, // SMLSL_MZZI_S |
| 290U, // SMLSL_MZZ_S |
| 76033U, // SMLSL_VG2_M2Z2Z_S |
| 2961665U, // SMLSL_VG2_M2ZZI_S |
| 78081U, // SMLSL_VG2_M2ZZ_S |
| 76033U, // SMLSL_VG4_M4Z4Z_S |
| 2961665U, // SMLSL_VG4_M4ZZI_S |
| 78081U, // SMLSL_VG4_M4ZZ_S |
| 18497U, // SMLSLv16i8_v8i16 |
| 103303233U, // SMLSLv2i32_indexed |
| 18497U, // SMLSLv2i32_v2i64 |
| 103303233U, // SMLSLv4i16_indexed |
| 18497U, // SMLSLv4i16_v4i32 |
| 103303233U, // SMLSLv4i32_indexed |
| 18497U, // SMLSLv4i32_v2i64 |
| 103303233U, // SMLSLv8i16_indexed |
| 18497U, // SMLSLv8i16_v4i32 |
| 18497U, // SMLSLv8i8_v8i16 |
| 0U, // SMMLA |
| 19U, // SMMLA_ZZZ |
| 0U, // SMOPA_MPPZZ_D |
| 0U, // SMOPA_MPPZZ_HtoS |
| 0U, // SMOPA_MPPZZ_S |
| 0U, // SMOPS_MPPZZ_D |
| 0U, // SMOPS_MPPZZ_HtoS |
| 0U, // SMOPS_MPPZZ_S |
| 480U, // SMOVvi16to32 |
| 480U, // SMOVvi16to32_idx0 |
| 480U, // SMOVvi16to64 |
| 480U, // SMOVvi16to64_idx0 |
| 480U, // SMOVvi32to64 |
| 480U, // SMOVvi32to64_idx0 |
| 480U, // SMOVvi8to32 |
| 480U, // SMOVvi8to32_idx0 |
| 480U, // SMOVvi8to64 |
| 480U, // SMOVvi8to64_idx0 |
| 268352U, // SMSUBLrrr |
| 33837153U, // SMULH_ZPmZ_B |
| 67383393U, // SMULH_ZPmZ_D |
| 101210225U, // SMULH_ZPmZ_H |
| 134504545U, // SMULH_ZPmZ_S |
| 20546U, // SMULH_ZZZ_B |
| 12353U, // SMULH_ZZZ_D |
| 113U, // SMULH_ZZZ_H |
| 24642U, // SMULH_ZZZ_S |
| 6208U, // SMULHrr |
| 5267522U, // SMULLB_ZZZI_D |
| 5253184U, // SMULLB_ZZZI_S |
| 24642U, // SMULLB_ZZZ_D |
| 129U, // SMULLB_ZZZ_H |
| 10304U, // SMULLB_ZZZ_S |
| 5267522U, // SMULLT_ZZZI_D |
| 5253184U, // SMULLT_ZZZI_S |
| 24642U, // SMULLT_ZZZ_D |
| 129U, // SMULLT_ZZZ_H |
| 10304U, // SMULLT_ZZZ_S |
| 16448U, // SMULLv16i8_v8i16 |
| 5259328U, // SMULLv2i32_indexed |
| 16448U, // SMULLv2i32_v2i64 |
| 5259328U, // SMULLv4i16_indexed |
| 16448U, // SMULLv4i16_v4i32 |
| 5259328U, // SMULLv4i32_indexed |
| 16448U, // SMULLv4i32_v2i64 |
| 5259328U, // SMULLv8i16_indexed |
| 16448U, // SMULLv8i16_v4i32 |
| 16448U, // SMULLv8i8_v8i16 |
| 157761U, // SPLICE_ZPZZ_B |
| 159809U, // SPLICE_ZPZZ_D |
| 273U, // SPLICE_ZPZZ_H |
| 161857U, // SPLICE_ZPZZ_S |
| 33837121U, // SPLICE_ZPZ_B |
| 67383361U, // SPLICE_ZPZ_D |
| 101210225U, // SPLICE_ZPZ_H |
| 134504513U, // SPLICE_ZPZ_S |
| 16U, // SQABS_ZPmZ_B |
| 32U, // SQABS_ZPmZ_D |
| 0U, // SQABS_ZPmZ_H |
| 48U, // SQABS_ZPmZ_S |
| 0U, // SQABSv16i8 |
| 0U, // SQABSv1i16 |
| 0U, // SQABSv1i32 |
| 0U, // SQABSv1i64 |
| 0U, // SQABSv1i8 |
| 0U, // SQABSv2i32 |
| 0U, // SQABSv2i64 |
| 0U, // SQABSv4i16 |
| 0U, // SQABSv4i32 |
| 0U, // SQABSv8i16 |
| 0U, // SQABSv8i8 |
| 32834U, // SQADD_ZI_B |
| 34881U, // SQADD_ZI_D |
| 193U, // SQADD_ZI_H |
| 36930U, // SQADD_ZI_S |
| 33837153U, // SQADD_ZPmZ_B |
| 67383393U, // SQADD_ZPmZ_D |
| 101210225U, // SQADD_ZPmZ_H |
| 134504545U, // SQADD_ZPmZ_S |
| 20546U, // SQADD_ZZZ_B |
| 12353U, // SQADD_ZZZ_D |
| 113U, // SQADD_ZZZ_H |
| 24642U, // SQADD_ZZZ_S |
| 16448U, // SQADDv16i8 |
| 6208U, // SQADDv1i16 |
| 6208U, // SQADDv1i32 |
| 6208U, // SQADDv1i64 |
| 6208U, // SQADDv1i8 |
| 16448U, // SQADDv2i32 |
| 16448U, // SQADDv2i64 |
| 16448U, // SQADDv4i16 |
| 16448U, // SQADDv4i32 |
| 16448U, // SQADDv8i16 |
| 16448U, // SQADDv8i8 |
| 235163714U, // SQCADD_ZZI_B |
| 235155521U, // SQCADD_ZZI_D |
| 3430513U, // SQCADD_ZZI_H |
| 235167810U, // SQCADD_ZZI_S |
| 0U, // SQCVTN_Z2Z_StoH |
| 0U, // SQCVTN_Z4Z_DtoH |
| 8U, // SQCVTN_Z4Z_StoB |
| 0U, // SQCVTUN_Z2Z_StoH |
| 0U, // SQCVTUN_Z4Z_DtoH |
| 8U, // SQCVTUN_Z4Z_StoB |
| 0U, // SQCVTU_Z2Z_StoH |
| 0U, // SQCVTU_Z4Z_DtoH |
| 8U, // SQCVTU_Z4Z_StoB |
| 0U, // SQCVT_Z2Z_StoH |
| 0U, // SQCVT_Z4Z_DtoH |
| 8U, // SQCVT_Z4Z_StoB |
| 4U, // SQDECB_XPiI |
| 8U, // SQDECB_XPiWdI |
| 4U, // SQDECD_XPiI |
| 8U, // SQDECD_XPiWdI |
| 4U, // SQDECD_ZPiI |
| 4U, // SQDECH_XPiI |
| 8U, // SQDECH_XPiWdI |
| 0U, // SQDECH_ZPiI |
| 163906U, // SQDECP_XPWd_B |
| 163905U, // SQDECP_XPWd_D |
| 163904U, // SQDECP_XPWd_H |
| 163906U, // SQDECP_XPWd_S |
| 2U, // SQDECP_XP_B |
| 1U, // SQDECP_XP_D |
| 0U, // SQDECP_XP_H |
| 2U, // SQDECP_XP_S |
| 0U, // SQDECP_ZP_D |
| 0U, // SQDECP_ZP_H |
| 0U, // SQDECP_ZP_S |
| 4U, // SQDECW_XPiI |
| 8U, // SQDECW_XPiWdI |
| 4U, // SQDECW_ZPiI |
| 4160U, // SQDMLALBT_ZZZ_D |
| 17U, // SQDMLALBT_ZZZ_H |
| 14401U, // SQDMLALBT_ZZZ_S |
| 103288896U, // SQDMLALB_ZZZI_D |
| 103299137U, // SQDMLALB_ZZZI_S |
| 4160U, // SQDMLALB_ZZZ_D |
| 17U, // SQDMLALB_ZZZ_H |
| 14401U, // SQDMLALB_ZZZ_S |
| 103288896U, // SQDMLALT_ZZZI_D |
| 103299137U, // SQDMLALT_ZZZI_S |
| 4160U, // SQDMLALT_ZZZ_D |
| 17U, // SQDMLALT_ZZZ_H |
| 14401U, // SQDMLALT_ZZZ_S |
| 86082U, // SQDMLALi16 |
| 86082U, // SQDMLALi32 |
| 103303234U, // SQDMLALv1i32_indexed |
| 103303234U, // SQDMLALv1i64_indexed |
| 103303233U, // SQDMLALv2i32_indexed |
| 18497U, // SQDMLALv2i32_v2i64 |
| 103303233U, // SQDMLALv4i16_indexed |
| 18497U, // SQDMLALv4i16_v4i32 |
| 103303233U, // SQDMLALv4i32_indexed |
| 18497U, // SQDMLALv4i32_v2i64 |
| 103303233U, // SQDMLALv8i16_indexed |
| 18497U, // SQDMLALv8i16_v4i32 |
| 4160U, // SQDMLSLBT_ZZZ_D |
| 17U, // SQDMLSLBT_ZZZ_H |
| 14401U, // SQDMLSLBT_ZZZ_S |
| 103288896U, // SQDMLSLB_ZZZI_D |
| 103299137U, // SQDMLSLB_ZZZI_S |
| 4160U, // SQDMLSLB_ZZZ_D |
| 17U, // SQDMLSLB_ZZZ_H |
| 14401U, // SQDMLSLB_ZZZ_S |
| 103288896U, // SQDMLSLT_ZZZI_D |
| 103299137U, // SQDMLSLT_ZZZI_S |
| 4160U, // SQDMLSLT_ZZZ_D |
| 17U, // SQDMLSLT_ZZZ_H |
| 14401U, // SQDMLSLT_ZZZ_S |
| 86082U, // SQDMLSLi16 |
| 86082U, // SQDMLSLi32 |
| 103303234U, // SQDMLSLv1i32_indexed |
| 103303234U, // SQDMLSLv1i64_indexed |
| 103303233U, // SQDMLSLv2i32_indexed |
| 18497U, // SQDMLSLv2i32_v2i64 |
| 103303233U, // SQDMLSLv4i16_indexed |
| 18497U, // SQDMLSLv4i16_v4i32 |
| 103303233U, // SQDMLSLv4i32_indexed |
| 18497U, // SQDMLSLv4i32_v2i64 |
| 103303233U, // SQDMLSLv8i16_indexed |
| 18497U, // SQDMLSLv8i16_v4i32 |
| 1393U, // SQDMULH_VG2_2Z2Z_B |
| 657U, // SQDMULH_VG2_2Z2Z_D |
| 273U, // SQDMULH_VG2_2Z2Z_H |
| 673U, // SQDMULH_VG2_2Z2Z_S |
| 129U, // SQDMULH_VG2_2ZZ_B |
| 145U, // SQDMULH_VG2_2ZZ_D |
| 113U, // SQDMULH_VG2_2ZZ_H |
| 81U, // SQDMULH_VG2_2ZZ_S |
| 1393U, // SQDMULH_VG4_4Z4Z_B |
| 657U, // SQDMULH_VG4_4Z4Z_D |
| 273U, // SQDMULH_VG4_4Z4Z_H |
| 673U, // SQDMULH_VG4_4Z4Z_S |
| 129U, // SQDMULH_VG4_4ZZ_B |
| 145U, // SQDMULH_VG4_4ZZ_D |
| 113U, // SQDMULH_VG4_4ZZ_H |
| 81U, // SQDMULH_VG4_4ZZ_S |
| 5255233U, // SQDMULH_ZZZI_D |
| 84081U, // SQDMULH_ZZZI_H |
| 5267522U, // SQDMULH_ZZZI_S |
| 20546U, // SQDMULH_ZZZ_B |
| 12353U, // SQDMULH_ZZZ_D |
| 113U, // SQDMULH_ZZZ_H |
| 24642U, // SQDMULH_ZZZ_S |
| 6208U, // SQDMULHv1i16 |
| 5259328U, // SQDMULHv1i16_indexed |
| 6208U, // SQDMULHv1i32 |
| 5259328U, // SQDMULHv1i32_indexed |
| 16448U, // SQDMULHv2i32 |
| 5259328U, // SQDMULHv2i32_indexed |
| 16448U, // SQDMULHv4i16 |
| 5259328U, // SQDMULHv4i16_indexed |
| 16448U, // SQDMULHv4i32 |
| 5259328U, // SQDMULHv4i32_indexed |
| 16448U, // SQDMULHv8i16 |
| 5259328U, // SQDMULHv8i16_indexed |
| 5267522U, // SQDMULLB_ZZZI_D |
| 5253184U, // SQDMULLB_ZZZI_S |
| 24642U, // SQDMULLB_ZZZ_D |
| 129U, // SQDMULLB_ZZZ_H |
| 10304U, // SQDMULLB_ZZZ_S |
| 5267522U, // SQDMULLT_ZZZI_D |
| 5253184U, // SQDMULLT_ZZZI_S |
| 24642U, // SQDMULLT_ZZZ_D |
| 129U, // SQDMULLT_ZZZ_H |
| 10304U, // SQDMULLT_ZZZ_S |
| 6208U, // SQDMULLi16 |
| 6208U, // SQDMULLi32 |
| 5259328U, // SQDMULLv1i32_indexed |
| 5259328U, // SQDMULLv1i64_indexed |
| 5259328U, // SQDMULLv2i32_indexed |
| 16448U, // SQDMULLv2i32_v2i64 |
| 5259328U, // SQDMULLv4i16_indexed |
| 16448U, // SQDMULLv4i16_v4i32 |
| 5259328U, // SQDMULLv4i32_indexed |
| 16448U, // SQDMULLv4i32_v2i64 |
| 5259328U, // SQDMULLv8i16_indexed |
| 16448U, // SQDMULLv8i16_v4i32 |
| 4U, // SQINCB_XPiI |
| 8U, // SQINCB_XPiWdI |
| 4U, // SQINCD_XPiI |
| 8U, // SQINCD_XPiWdI |
| 4U, // SQINCD_ZPiI |
| 4U, // SQINCH_XPiI |
| 8U, // SQINCH_XPiWdI |
| 0U, // SQINCH_ZPiI |
| 163906U, // SQINCP_XPWd_B |
| 163905U, // SQINCP_XPWd_D |
| 163904U, // SQINCP_XPWd_H |
| 163906U, // SQINCP_XPWd_S |
| 2U, // SQINCP_XP_B |
| 1U, // SQINCP_XP_D |
| 0U, // SQINCP_XP_H |
| 2U, // SQINCP_XP_S |
| 0U, // SQINCP_ZP_D |
| 0U, // SQINCP_ZP_H |
| 0U, // SQINCP_ZP_S |
| 4U, // SQINCW_XPiI |
| 8U, // SQINCW_XPiWdI |
| 4U, // SQINCW_ZPiI |
| 16U, // SQNEG_ZPmZ_B |
| 32U, // SQNEG_ZPmZ_D |
| 0U, // SQNEG_ZPmZ_H |
| 48U, // SQNEG_ZPmZ_S |
| 0U, // SQNEGv16i8 |
| 0U, // SQNEGv1i16 |
| 0U, // SQNEGv1i32 |
| 0U, // SQNEGv1i64 |
| 0U, // SQNEGv1i8 |
| 0U, // SQNEGv2i32 |
| 0U, // SQNEGv2i64 |
| 0U, // SQNEGv4i16 |
| 0U, // SQNEGv4i32 |
| 0U, // SQNEGv8i16 |
| 0U, // SQNEGv8i8 |
| 335888625U, // SQRDCMLAH_ZZZI_H |
| 304615488U, // SQRDCMLAH_ZZZI_S |
| 3954707U, // SQRDCMLAH_ZZZ_B |
| 369363008U, // SQRDCMLAH_ZZZ_D |
| 3954929U, // SQRDCMLAH_ZZZ_H |
| 369365056U, // SQRDCMLAH_ZZZ_S |
| 103286848U, // SQRDMLAH_ZZZI_D |
| 82161U, // SQRDMLAH_ZZZI_H |
| 103288896U, // SQRDMLAH_ZZZI_S |
| 19U, // SQRDMLAH_ZZZ_B |
| 2112U, // SQRDMLAH_ZZZ_D |
| 241U, // SQRDMLAH_ZZZ_H |
| 4160U, // SQRDMLAH_ZZZ_S |
| 103303234U, // SQRDMLAHi16_indexed |
| 103303234U, // SQRDMLAHi32_indexed |
| 86082U, // SQRDMLAHv1i16 |
| 86082U, // SQRDMLAHv1i32 |
| 18497U, // SQRDMLAHv2i32 |
| 103303233U, // SQRDMLAHv2i32_indexed |
| 18497U, // SQRDMLAHv4i16 |
| 103303233U, // SQRDMLAHv4i16_indexed |
| 18497U, // SQRDMLAHv4i32 |
| 103303233U, // SQRDMLAHv4i32_indexed |
| 18497U, // SQRDMLAHv8i16 |
| 103303233U, // SQRDMLAHv8i16_indexed |
| 103286848U, // SQRDMLSH_ZZZI_D |
| 82161U, // SQRDMLSH_ZZZI_H |
| 103288896U, // SQRDMLSH_ZZZI_S |
| 19U, // SQRDMLSH_ZZZ_B |
| 2112U, // SQRDMLSH_ZZZ_D |
| 241U, // SQRDMLSH_ZZZ_H |
| 4160U, // SQRDMLSH_ZZZ_S |
| 103303234U, // SQRDMLSHi16_indexed |
| 103303234U, // SQRDMLSHi32_indexed |
| 86082U, // SQRDMLSHv1i16 |
| 86082U, // SQRDMLSHv1i32 |
| 18497U, // SQRDMLSHv2i32 |
| 103303233U, // SQRDMLSHv2i32_indexed |
| 18497U, // SQRDMLSHv4i16 |
| 103303233U, // SQRDMLSHv4i16_indexed |
| 18497U, // SQRDMLSHv4i32 |
| 103303233U, // SQRDMLSHv4i32_indexed |
| 18497U, // SQRDMLSHv8i16 |
| 103303233U, // SQRDMLSHv8i16_indexed |
| 5255233U, // SQRDMULH_ZZZI_D |
| 84081U, // SQRDMULH_ZZZI_H |
| 5267522U, // SQRDMULH_ZZZI_S |
| 20546U, // SQRDMULH_ZZZ_B |
| 12353U, // SQRDMULH_ZZZ_D |
| 113U, // SQRDMULH_ZZZ_H |
| 24642U, // SQRDMULH_ZZZ_S |
| 6208U, // SQRDMULHv1i16 |
| 5259328U, // SQRDMULHv1i16_indexed |
| 6208U, // SQRDMULHv1i32 |
| 5259328U, // SQRDMULHv1i32_indexed |
| 16448U, // SQRDMULHv2i32 |
| 5259328U, // SQRDMULHv2i32_indexed |
| 16448U, // SQRDMULHv4i16 |
| 5259328U, // SQRDMULHv4i16_indexed |
| 16448U, // SQRDMULHv4i32 |
| 5259328U, // SQRDMULHv4i32_indexed |
| 16448U, // SQRDMULHv8i16 |
| 5259328U, // SQRDMULHv8i16_indexed |
| 33837153U, // SQRSHLR_ZPmZ_B |
| 67383393U, // SQRSHLR_ZPmZ_D |
| 101210225U, // SQRSHLR_ZPmZ_H |
| 134504545U, // SQRSHLR_ZPmZ_S |
| 33837153U, // SQRSHL_ZPmZ_B |
| 67383393U, // SQRSHL_ZPmZ_D |
| 101210225U, // SQRSHL_ZPmZ_H |
| 134504545U, // SQRSHL_ZPmZ_S |
| 16448U, // SQRSHLv16i8 |
| 6208U, // SQRSHLv1i16 |
| 6208U, // SQRSHLv1i32 |
| 6208U, // SQRSHLv1i64 |
| 6208U, // SQRSHLv1i8 |
| 16448U, // SQRSHLv2i32 |
| 16448U, // SQRSHLv2i64 |
| 16448U, // SQRSHLv4i16 |
| 16448U, // SQRSHLv4i32 |
| 16448U, // SQRSHLv8i16 |
| 16448U, // SQRSHLv8i8 |
| 6208U, // SQRSHRNB_ZZI_B |
| 225U, // SQRSHRNB_ZZI_H |
| 6209U, // SQRSHRNB_ZZI_S |
| 86081U, // SQRSHRNT_ZZI_B |
| 449U, // SQRSHRNT_ZZI_H |
| 86080U, // SQRSHRNT_ZZI_S |
| 6216U, // SQRSHRN_VG4_Z4ZI_B |
| 225U, // SQRSHRN_VG4_Z4ZI_H |
| 6208U, // SQRSHRNb |
| 6208U, // SQRSHRNh |
| 6208U, // SQRSHRNs |
| 86081U, // SQRSHRNv16i8_shift |
| 6208U, // SQRSHRNv2i32_shift |
| 6208U, // SQRSHRNv4i16_shift |
| 86081U, // SQRSHRNv4i32_shift |
| 86081U, // SQRSHRNv8i16_shift |
| 6208U, // SQRSHRNv8i8_shift |
| 6208U, // SQRSHRUNB_ZZI_B |
| 225U, // SQRSHRUNB_ZZI_H |
| 6209U, // SQRSHRUNB_ZZI_S |
| 86081U, // SQRSHRUNT_ZZI_B |
| 449U, // SQRSHRUNT_ZZI_H |
| 86080U, // SQRSHRUNT_ZZI_S |
| 6216U, // SQRSHRUN_VG4_Z4ZI_B |
| 225U, // SQRSHRUN_VG4_Z4ZI_H |
| 6208U, // SQRSHRUNb |
| 6208U, // SQRSHRUNh |
| 6208U, // SQRSHRUNs |
| 86081U, // SQRSHRUNv16i8_shift |
| 6208U, // SQRSHRUNv2i32_shift |
| 6208U, // SQRSHRUNv4i16_shift |
| 86081U, // SQRSHRUNv4i32_shift |
| 86081U, // SQRSHRUNv8i16_shift |
| 6208U, // SQRSHRUNv8i8_shift |
| 225U, // SQRSHRU_VG2_Z2ZI_H |
| 6216U, // SQRSHRU_VG4_Z4ZI_B |
| 225U, // SQRSHRU_VG4_Z4ZI_H |
| 225U, // SQRSHR_VG2_Z2ZI_H |
| 6216U, // SQRSHR_VG4_Z4ZI_B |
| 225U, // SQRSHR_VG4_Z4ZI_H |
| 33837153U, // SQSHLR_ZPmZ_B |
| 67383393U, // SQSHLR_ZPmZ_D |
| 101210225U, // SQSHLR_ZPmZ_H |
| 134504545U, // SQSHLR_ZPmZ_S |
| 282721U, // SQSHLU_ZPmI_B |
| 274529U, // SQSHLU_ZPmI_D |
| 102783089U, // SQSHLU_ZPmI_H |
| 286817U, // SQSHLU_ZPmI_S |
| 6208U, // SQSHLUb |
| 6208U, // SQSHLUd |
| 6208U, // SQSHLUh |
| 6208U, // SQSHLUs |
| 6208U, // SQSHLUv16i8_shift |
| 6208U, // SQSHLUv2i32_shift |
| 6208U, // SQSHLUv2i64_shift |
| 6208U, // SQSHLUv4i16_shift |
| 6208U, // SQSHLUv4i32_shift |
| 6208U, // SQSHLUv8i16_shift |
| 6208U, // SQSHLUv8i8_shift |
| 282721U, // SQSHL_ZPmI_B |
| 274529U, // SQSHL_ZPmI_D |
| 102783089U, // SQSHL_ZPmI_H |
| 286817U, // SQSHL_ZPmI_S |
| 33837153U, // SQSHL_ZPmZ_B |
| 67383393U, // SQSHL_ZPmZ_D |
| 101210225U, // SQSHL_ZPmZ_H |
| 134504545U, // SQSHL_ZPmZ_S |
| 6208U, // SQSHLb |
| 6208U, // SQSHLd |
| 6208U, // SQSHLh |
| 6208U, // SQSHLs |
| 16448U, // SQSHLv16i8 |
| 6208U, // SQSHLv16i8_shift |
| 6208U, // SQSHLv1i16 |
| 6208U, // SQSHLv1i32 |
| 6208U, // SQSHLv1i64 |
| 6208U, // SQSHLv1i8 |
| 16448U, // SQSHLv2i32 |
| 6208U, // SQSHLv2i32_shift |
| 16448U, // SQSHLv2i64 |
| 6208U, // SQSHLv2i64_shift |
| 16448U, // SQSHLv4i16 |
| 6208U, // SQSHLv4i16_shift |
| 16448U, // SQSHLv4i32 |
| 6208U, // SQSHLv4i32_shift |
| 16448U, // SQSHLv8i16 |
| 6208U, // SQSHLv8i16_shift |
| 16448U, // SQSHLv8i8 |
| 6208U, // SQSHLv8i8_shift |
| 6208U, // SQSHRNB_ZZI_B |
| 225U, // SQSHRNB_ZZI_H |
| 6209U, // SQSHRNB_ZZI_S |
| 86081U, // SQSHRNT_ZZI_B |
| 449U, // SQSHRNT_ZZI_H |
| 86080U, // SQSHRNT_ZZI_S |
| 6208U, // SQSHRNb |
| 6208U, // SQSHRNh |
| 6208U, // SQSHRNs |
| 86081U, // SQSHRNv16i8_shift |
| 6208U, // SQSHRNv2i32_shift |
| 6208U, // SQSHRNv4i16_shift |
| 86081U, // SQSHRNv4i32_shift |
| 86081U, // SQSHRNv8i16_shift |
| 6208U, // SQSHRNv8i8_shift |
| 6208U, // SQSHRUNB_ZZI_B |
| 225U, // SQSHRUNB_ZZI_H |
| 6209U, // SQSHRUNB_ZZI_S |
| 86081U, // SQSHRUNT_ZZI_B |
| 449U, // SQSHRUNT_ZZI_H |
| 86080U, // SQSHRUNT_ZZI_S |
| 6208U, // SQSHRUNb |
| 6208U, // SQSHRUNh |
| 6208U, // SQSHRUNs |
| 86081U, // SQSHRUNv16i8_shift |
| 6208U, // SQSHRUNv2i32_shift |
| 6208U, // SQSHRUNv4i16_shift |
| 86081U, // SQSHRUNv4i32_shift |
| 86081U, // SQSHRUNv8i16_shift |
| 6208U, // SQSHRUNv8i8_shift |
| 33837153U, // SQSUBR_ZPmZ_B |
| 67383393U, // SQSUBR_ZPmZ_D |
| 101210225U, // SQSUBR_ZPmZ_H |
| 134504545U, // SQSUBR_ZPmZ_S |
| 32834U, // SQSUB_ZI_B |
| 34881U, // SQSUB_ZI_D |
| 193U, // SQSUB_ZI_H |
| 36930U, // SQSUB_ZI_S |
| 33837153U, // SQSUB_ZPmZ_B |
| 67383393U, // SQSUB_ZPmZ_D |
| 101210225U, // SQSUB_ZPmZ_H |
| 134504545U, // SQSUB_ZPmZ_S |
| 20546U, // SQSUB_ZZZ_B |
| 12353U, // SQSUB_ZZZ_D |
| 113U, // SQSUB_ZZZ_H |
| 24642U, // SQSUB_ZZZ_S |
| 16448U, // SQSUBv16i8 |
| 6208U, // SQSUBv1i16 |
| 6208U, // SQSUBv1i32 |
| 6208U, // SQSUBv1i64 |
| 6208U, // SQSUBv1i8 |
| 16448U, // SQSUBv2i32 |
| 16448U, // SQSUBv2i64 |
| 16448U, // SQSUBv4i16 |
| 16448U, // SQSUBv4i32 |
| 16448U, // SQSUBv8i16 |
| 16448U, // SQSUBv8i8 |
| 0U, // SQXTNB_ZZ_B |
| 0U, // SQXTNB_ZZ_H |
| 1U, // SQXTNB_ZZ_S |
| 1U, // SQXTNT_ZZ_B |
| 0U, // SQXTNT_ZZ_H |
| 0U, // SQXTNT_ZZ_S |
| 1U, // SQXTNv16i8 |
| 0U, // SQXTNv1i16 |
| 0U, // SQXTNv1i32 |
| 0U, // SQXTNv1i8 |
| 0U, // SQXTNv2i32 |
| 0U, // SQXTNv4i16 |
| 1U, // SQXTNv4i32 |
| 1U, // SQXTNv8i16 |
| 0U, // SQXTNv8i8 |
| 0U, // SQXTUNB_ZZ_B |
| 0U, // SQXTUNB_ZZ_H |
| 1U, // SQXTUNB_ZZ_S |
| 1U, // SQXTUNT_ZZ_B |
| 0U, // SQXTUNT_ZZ_H |
| 0U, // SQXTUNT_ZZ_S |
| 1U, // SQXTUNv16i8 |
| 0U, // SQXTUNv1i16 |
| 0U, // SQXTUNv1i32 |
| 0U, // SQXTUNv1i8 |
| 0U, // SQXTUNv2i32 |
| 0U, // SQXTUNv4i16 |
| 1U, // SQXTUNv4i32 |
| 1U, // SQXTUNv8i16 |
| 0U, // SQXTUNv8i8 |
| 33837153U, // SRHADD_ZPmZ_B |
| 67383393U, // SRHADD_ZPmZ_D |
| 101210225U, // SRHADD_ZPmZ_H |
| 134504545U, // SRHADD_ZPmZ_S |
| 16448U, // SRHADDv16i8 |
| 16448U, // SRHADDv2i32 |
| 16448U, // SRHADDv4i16 |
| 16448U, // SRHADDv4i32 |
| 16448U, // SRHADDv8i16 |
| 16448U, // SRHADDv8i8 |
| 451U, // SRI_ZZI_B |
| 86080U, // SRI_ZZI_D |
| 449U, // SRI_ZZI_H |
| 86080U, // SRI_ZZI_S |
| 86082U, // SRId |
| 86081U, // SRIv16i8_shift |
| 86081U, // SRIv2i32_shift |
| 86081U, // SRIv2i64_shift |
| 86081U, // SRIv4i16_shift |
| 86081U, // SRIv4i32_shift |
| 86081U, // SRIv8i16_shift |
| 86081U, // SRIv8i8_shift |
| 33837153U, // SRSHLR_ZPmZ_B |
| 67383393U, // SRSHLR_ZPmZ_D |
| 101210225U, // SRSHLR_ZPmZ_H |
| 134504545U, // SRSHLR_ZPmZ_S |
| 1393U, // SRSHL_VG2_2Z2Z_B |
| 657U, // SRSHL_VG2_2Z2Z_D |
| 273U, // SRSHL_VG2_2Z2Z_H |
| 673U, // SRSHL_VG2_2Z2Z_S |
| 129U, // SRSHL_VG2_2ZZ_B |
| 145U, // SRSHL_VG2_2ZZ_D |
| 113U, // SRSHL_VG2_2ZZ_H |
| 81U, // SRSHL_VG2_2ZZ_S |
| 1393U, // SRSHL_VG4_4Z4Z_B |
| 657U, // SRSHL_VG4_4Z4Z_D |
| 273U, // SRSHL_VG4_4Z4Z_H |
| 673U, // SRSHL_VG4_4Z4Z_S |
| 129U, // SRSHL_VG4_4ZZ_B |
| 145U, // SRSHL_VG4_4ZZ_D |
| 113U, // SRSHL_VG4_4ZZ_H |
| 81U, // SRSHL_VG4_4ZZ_S |
| 33837153U, // SRSHL_ZPmZ_B |
| 67383393U, // SRSHL_ZPmZ_D |
| 101210225U, // SRSHL_ZPmZ_H |
| 134504545U, // SRSHL_ZPmZ_S |
| 16448U, // SRSHLv16i8 |
| 6208U, // SRSHLv1i64 |
| 16448U, // SRSHLv2i32 |
| 16448U, // SRSHLv2i64 |
| 16448U, // SRSHLv4i16 |
| 16448U, // SRSHLv4i32 |
| 16448U, // SRSHLv8i16 |
| 16448U, // SRSHLv8i8 |
| 282721U, // SRSHR_ZPmI_B |
| 274529U, // SRSHR_ZPmI_D |
| 102783089U, // SRSHR_ZPmI_H |
| 286817U, // SRSHR_ZPmI_S |
| 6208U, // SRSHRd |
| 6208U, // SRSHRv16i8_shift |
| 6208U, // SRSHRv2i32_shift |
| 6208U, // SRSHRv2i64_shift |
| 6208U, // SRSHRv4i16_shift |
| 6208U, // SRSHRv4i32_shift |
| 6208U, // SRSHRv8i16_shift |
| 6208U, // SRSHRv8i8_shift |
| 451U, // SRSRA_ZZI_B |
| 86080U, // SRSRA_ZZI_D |
| 449U, // SRSRA_ZZI_H |
| 86080U, // SRSRA_ZZI_S |
| 86082U, // SRSRAd |
| 86081U, // SRSRAv16i8_shift |
| 86081U, // SRSRAv2i32_shift |
| 86081U, // SRSRAv2i64_shift |
| 86081U, // SRSRAv4i16_shift |
| 86081U, // SRSRAv4i32_shift |
| 86081U, // SRSRAv8i16_shift |
| 86081U, // SRSRAv8i8_shift |
| 6210U, // SSHLLB_ZZI_D |
| 225U, // SSHLLB_ZZI_H |
| 6208U, // SSHLLB_ZZI_S |
| 6210U, // SSHLLT_ZZI_D |
| 225U, // SSHLLT_ZZI_H |
| 6208U, // SSHLLT_ZZI_S |
| 6208U, // SSHLLv16i8_shift |
| 6208U, // SSHLLv2i32_shift |
| 6208U, // SSHLLv4i16_shift |
| 6208U, // SSHLLv4i32_shift |
| 6208U, // SSHLLv8i16_shift |
| 6208U, // SSHLLv8i8_shift |
| 16448U, // SSHLv16i8 |
| 6208U, // SSHLv1i64 |
| 16448U, // SSHLv2i32 |
| 16448U, // SSHLv2i64 |
| 16448U, // SSHLv4i16 |
| 16448U, // SSHLv4i32 |
| 16448U, // SSHLv8i16 |
| 16448U, // SSHLv8i8 |
| 6208U, // SSHRd |
| 6208U, // SSHRv16i8_shift |
| 6208U, // SSHRv2i32_shift |
| 6208U, // SSHRv2i64_shift |
| 6208U, // SSHRv4i16_shift |
| 6208U, // SSHRv4i32_shift |
| 6208U, // SSHRv8i16_shift |
| 6208U, // SSHRv8i8_shift |
| 451U, // SSRA_ZZI_B |
| 86080U, // SSRA_ZZI_D |
| 449U, // SSRA_ZZI_H |
| 86080U, // SSRA_ZZI_S |
| 86082U, // SSRAd |
| 86081U, // SSRAv16i8_shift |
| 86081U, // SSRAv2i32_shift |
| 86081U, // SSRAv2i64_shift |
| 86081U, // SSRAv4i16_shift |
| 86081U, // SSRAv4i32_shift |
| 86081U, // SSRAv8i16_shift |
| 86081U, // SSRAv8i8_shift |
| 5789928U, // SST1B_D |
| 673208472U, // SST1B_D_IMM |
| 6052072U, // SST1B_D_SXTW |
| 6314216U, // SST1B_D_UXTW |
| 673208408U, // SST1B_S_IMM |
| 6576360U, // SST1B_S_SXTW |
| 6838504U, // SST1B_S_UXTW |
| 5789928U, // SST1D |
| 7100568U, // SST1D_IMM |
| 7362792U, // SST1D_SCALED |
| 6052072U, // SST1D_SXTW |
| 7624936U, // SST1D_SXTW_SCALED |
| 6314216U, // SST1D_UXTW |
| 7887080U, // SST1D_UXTW_SCALED |
| 5789928U, // SST1H_D |
| 679237784U, // SST1H_D_IMM |
| 8411368U, // SST1H_D_SCALED |
| 6052072U, // SST1H_D_SXTW |
| 8673512U, // SST1H_D_SXTW_SCALED |
| 6314216U, // SST1H_D_UXTW |
| 8935656U, // SST1H_D_UXTW_SCALED |
| 679237720U, // SST1H_S_IMM |
| 6576360U, // SST1H_S_SXTW |
| 9197800U, // SST1H_S_SXTW_SCALED |
| 6838504U, // SST1H_S_UXTW |
| 9459944U, // SST1H_S_UXTW_SCALED |
| 673208472U, // SST1Q |
| 5789928U, // SST1W_D |
| 680810648U, // SST1W_D_IMM |
| 9984232U, // SST1W_D_SCALED |
| 6052072U, // SST1W_D_SXTW |
| 10246376U, // SST1W_D_SXTW_SCALED |
| 6314216U, // SST1W_D_UXTW |
| 10508520U, // SST1W_D_UXTW_SCALED |
| 680810584U, // SST1W_IMM |
| 6576360U, // SST1W_SXTW |
| 10770664U, // SST1W_SXTW_SCALED |
| 6838504U, // SST1W_UXTW |
| 11032808U, // SST1W_UXTW_SCALED |
| 24642U, // SSUBLBT_ZZZ_D |
| 129U, // SSUBLBT_ZZZ_H |
| 10304U, // SSUBLBT_ZZZ_S |
| 24642U, // SSUBLB_ZZZ_D |
| 129U, // SSUBLB_ZZZ_H |
| 10304U, // SSUBLB_ZZZ_S |
| 24642U, // SSUBLTB_ZZZ_D |
| 129U, // SSUBLTB_ZZZ_H |
| 10304U, // SSUBLTB_ZZZ_S |
| 24642U, // SSUBLT_ZZZ_D |
| 129U, // SSUBLT_ZZZ_H |
| 10304U, // SSUBLT_ZZZ_S |
| 16448U, // SSUBLv16i8_v8i16 |
| 16448U, // SSUBLv2i32_v2i64 |
| 16448U, // SSUBLv4i16_v4i32 |
| 16448U, // SSUBLv4i32_v2i64 |
| 16448U, // SSUBLv8i16_v4i32 |
| 16448U, // SSUBLv8i8_v8i16 |
| 24641U, // SSUBWB_ZZZ_D |
| 129U, // SSUBWB_ZZZ_H |
| 10306U, // SSUBWB_ZZZ_S |
| 24641U, // SSUBWT_ZZZ_D |
| 129U, // SSUBWT_ZZZ_H |
| 10306U, // SSUBWT_ZZZ_S |
| 16448U, // SSUBWv16i8_v8i16 |
| 16448U, // SSUBWv2i32_v2i64 |
| 16448U, // SSUBWv4i16_v4i32 |
| 16448U, // SSUBWv4i32_v2i64 |
| 16448U, // SSUBWv8i16_v4i32 |
| 16448U, // SSUBWv8i8_v8i16 |
| 11294952U, // ST1B |
| 11294952U, // ST1B_2Z |
| 712792296U, // ST1B_2Z_IMM |
| 11294952U, // ST1B_4Z |
| 714365160U, // ST1B_4Z_IMM |
| 11294952U, // ST1B_D |
| 706762984U, // ST1B_D_IMM |
| 11294952U, // ST1B_H |
| 706762984U, // ST1B_H_IMM |
| 706762984U, // ST1B_IMM |
| 11294952U, // ST1B_S |
| 706762984U, // ST1B_S_IMM |
| 1275337062U, // ST1B_VG2_M2ZPXI |
| 1308891494U, // ST1B_VG2_M2ZPXX |
| 714365160U, // ST1B_VG4_M4ZPXI |
| 11294952U, // ST1B_VG4_M4ZPXX |
| 11557096U, // ST1D |
| 11557096U, // ST1D_2Z |
| 712792296U, // ST1D_2Z_IMM |
| 11557096U, // ST1D_4Z |
| 714365160U, // ST1D_4Z_IMM |
| 706762984U, // ST1D_IMM |
| 11557096U, // ST1D_Q |
| 706762984U, // ST1D_Q_IMM |
| 712792296U, // ST1D_VG2_M2ZPXI |
| 11557096U, // ST1D_VG2_M2ZPXX |
| 714365160U, // ST1D_VG4_M4ZPXI |
| 11557096U, // ST1D_VG4_M4ZPXX |
| 0U, // ST1Fourv16b |
| 0U, // ST1Fourv16b_POST |
| 0U, // ST1Fourv1d |
| 0U, // ST1Fourv1d_POST |
| 0U, // ST1Fourv2d |
| 0U, // ST1Fourv2d_POST |
| 0U, // ST1Fourv2s |
| 0U, // ST1Fourv2s_POST |
| 0U, // ST1Fourv4h |
| 0U, // ST1Fourv4h_POST |
| 0U, // ST1Fourv4s |
| 0U, // ST1Fourv4s_POST |
| 0U, // ST1Fourv8b |
| 0U, // ST1Fourv8b_POST |
| 0U, // ST1Fourv8h |
| 0U, // ST1Fourv8h_POST |
| 11819240U, // ST1H |
| 11819240U, // ST1H_2Z |
| 712792296U, // ST1H_2Z_IMM |
| 11819240U, // ST1H_4Z |
| 714365160U, // ST1H_4Z_IMM |
| 11819240U, // ST1H_D |
| 706762984U, // ST1H_D_IMM |
| 706762984U, // ST1H_IMM |
| 11819240U, // ST1H_S |
| 706762984U, // ST1H_S_IMM |
| 1275337062U, // ST1H_VG2_M2ZPXI |
| 1342445926U, // ST1H_VG2_M2ZPXX |
| 714365160U, // ST1H_VG4_M4ZPXI |
| 11819240U, // ST1H_VG4_M4ZPXX |
| 0U, // ST1Onev16b |
| 0U, // ST1Onev16b_POST |
| 0U, // ST1Onev1d |
| 0U, // ST1Onev1d_POST |
| 0U, // ST1Onev2d |
| 0U, // ST1Onev2d_POST |
| 0U, // ST1Onev2s |
| 0U, // ST1Onev2s_POST |
| 0U, // ST1Onev4h |
| 0U, // ST1Onev4h_POST |
| 0U, // ST1Onev4s |
| 0U, // ST1Onev4s_POST |
| 0U, // ST1Onev8b |
| 0U, // ST1Onev8b_POST |
| 0U, // ST1Onev8h |
| 0U, // ST1Onev8h_POST |
| 0U, // ST1Threev16b |
| 0U, // ST1Threev16b_POST |
| 0U, // ST1Threev1d |
| 0U, // ST1Threev1d_POST |
| 0U, // ST1Threev2d |
| 0U, // ST1Threev2d_POST |
| 0U, // ST1Threev2s |
| 0U, // ST1Threev2s_POST |
| 0U, // ST1Threev4h |
| 0U, // ST1Threev4h_POST |
| 0U, // ST1Threev4s |
| 0U, // ST1Threev4s_POST |
| 0U, // ST1Threev8b |
| 0U, // ST1Threev8b_POST |
| 0U, // ST1Threev8h |
| 0U, // ST1Threev8h_POST |
| 0U, // ST1Twov16b |
| 0U, // ST1Twov16b_POST |
| 0U, // ST1Twov1d |
| 0U, // ST1Twov1d_POST |
| 0U, // ST1Twov2d |
| 0U, // ST1Twov2d_POST |
| 0U, // ST1Twov2s |
| 0U, // ST1Twov2s_POST |
| 0U, // ST1Twov4h |
| 0U, // ST1Twov4h_POST |
| 0U, // ST1Twov4s |
| 0U, // ST1Twov4s_POST |
| 0U, // ST1Twov8b |
| 0U, // ST1Twov8b_POST |
| 0U, // ST1Twov8h |
| 0U, // ST1Twov8h_POST |
| 12343528U, // ST1W |
| 12343528U, // ST1W_2Z |
| 712792296U, // ST1W_2Z_IMM |
| 12343528U, // ST1W_4Z |
| 714365160U, // ST1W_4Z_IMM |
| 12343528U, // ST1W_D |
| 706762984U, // ST1W_D_IMM |
| 706762984U, // ST1W_IMM |
| 12343528U, // ST1W_Q |
| 706762984U, // ST1W_Q_IMM |
| 712792296U, // ST1W_VG2_M2ZPXI |
| 12343528U, // ST1W_VG2_M2ZPXX |
| 714365160U, // ST1W_VG4_M4ZPXI |
| 12343528U, // ST1W_VG4_M4ZPXX |
| 13011713U, // ST1_MXIPXX_H_B |
| 13273857U, // ST1_MXIPXX_H_D |
| 13536001U, // ST1_MXIPXX_H_H |
| 13798145U, // ST1_MXIPXX_H_Q |
| 14060289U, // ST1_MXIPXX_H_S |
| 13011713U, // ST1_MXIPXX_V_B |
| 13273857U, // ST1_MXIPXX_V_D |
| 13536001U, // ST1_MXIPXX_V_H |
| 13798145U, // ST1_MXIPXX_V_Q |
| 14060289U, // ST1_MXIPXX_V_S |
| 0U, // ST1i16 |
| 8U, // ST1i16_POST |
| 0U, // ST1i32 |
| 8U, // ST1i32_POST |
| 0U, // ST1i64 |
| 9U, // ST1i64_POST |
| 0U, // ST1i8 |
| 9U, // ST1i8_POST |
| 11294952U, // ST2B |
| 712792296U, // ST2B_IMM |
| 11557096U, // ST2D |
| 712792296U, // ST2D_IMM |
| 3678272U, // ST2GOffset |
| 117570U, // ST2GPostIndex |
| 15583298U, // ST2GPreIndex |
| 11819240U, // ST2H |
| 712792296U, // ST2H_IMM |
| 14178536U, // ST2Q |
| 712792296U, // ST2Q_IMM |
| 0U, // ST2Twov16b |
| 0U, // ST2Twov16b_POST |
| 0U, // ST2Twov2d |
| 0U, // ST2Twov2d_POST |
| 0U, // ST2Twov2s |
| 0U, // ST2Twov2s_POST |
| 0U, // ST2Twov4h |
| 0U, // ST2Twov4h_POST |
| 0U, // ST2Twov4s |
| 0U, // ST2Twov4s_POST |
| 0U, // ST2Twov8b |
| 0U, // ST2Twov8b_POST |
| 0U, // ST2Twov8h |
| 0U, // ST2Twov8h_POST |
| 12343528U, // ST2W |
| 712792296U, // ST2W_IMM |
| 0U, // ST2i16 |
| 8U, // ST2i16_POST |
| 0U, // ST2i32 |
| 9U, // ST2i32_POST |
| 0U, // ST2i64 |
| 9U, // ST2i64_POST |
| 0U, // ST2i8 |
| 8U, // ST2i8_POST |
| 11294952U, // ST3B |
| 14440680U, // ST3B_IMM |
| 11557096U, // ST3D |
| 14440680U, // ST3D_IMM |
| 11819240U, // ST3H |
| 14440680U, // ST3H_IMM |
| 14178536U, // ST3Q |
| 14440680U, // ST3Q_IMM |
| 0U, // ST3Threev16b |
| 0U, // ST3Threev16b_POST |
| 0U, // ST3Threev2d |
| 0U, // ST3Threev2d_POST |
| 0U, // ST3Threev2s |
| 0U, // ST3Threev2s_POST |
| 0U, // ST3Threev4h |
| 0U, // ST3Threev4h_POST |
| 0U, // ST3Threev4s |
| 0U, // ST3Threev4s_POST |
| 0U, // ST3Threev8b |
| 0U, // ST3Threev8b_POST |
| 0U, // ST3Threev8h |
| 0U, // ST3Threev8h_POST |
| 12343528U, // ST3W |
| 14440680U, // ST3W_IMM |
| 0U, // ST3i16 |
| 9U, // ST3i16_POST |
| 0U, // ST3i32 |
| 9U, // ST3i32_POST |
| 0U, // ST3i64 |
| 9U, // ST3i64_POST |
| 0U, // ST3i8 |
| 9U, // ST3i8_POST |
| 11294952U, // ST4B |
| 714365160U, // ST4B_IMM |
| 11557096U, // ST4D |
| 714365160U, // ST4D_IMM |
| 0U, // ST4Fourv16b |
| 0U, // ST4Fourv16b_POST |
| 0U, // ST4Fourv2d |
| 0U, // ST4Fourv2d_POST |
| 0U, // ST4Fourv2s |
| 0U, // ST4Fourv2s_POST |
| 0U, // ST4Fourv4h |
| 0U, // ST4Fourv4h_POST |
| 0U, // ST4Fourv4s |
| 0U, // ST4Fourv4s_POST |
| 0U, // ST4Fourv8b |
| 0U, // ST4Fourv8b_POST |
| 0U, // ST4Fourv8h |
| 0U, // ST4Fourv8h_POST |
| 11819240U, // ST4H |
| 714365160U, // ST4H_IMM |
| 14178536U, // ST4Q |
| 714365160U, // ST4Q_IMM |
| 12343528U, // ST4W |
| 714365160U, // ST4W_IMM |
| 0U, // ST4i16 |
| 9U, // ST4i16_POST |
| 0U, // ST4i32 |
| 9U, // ST4i32_POST |
| 0U, // ST4i64 |
| 9U, // ST4i64_POST |
| 0U, // ST4i8 |
| 8U, // ST4i8_POST |
| 0U, // ST64B |
| 10U, // ST64BV |
| 10U, // ST64BV0 |
| 784U, // STGM |
| 3678272U, // STGOffset |
| 772020576U, // STGPi |
| 117570U, // STGPostIndex |
| 887705954U, // STGPpost |
| 872763746U, // STGPpre |
| 15583298U, // STGPreIndex |
| 3676512U, // STILPW |
| 17387874U, // STILPWpre |
| 3676512U, // STILPX |
| 17650018U, // STILPXpre |
| 0U, // STL1 |
| 784U, // STLLRB |
| 784U, // STLLRH |
| 784U, // STLLRW |
| 784U, // STLLRX |
| 784U, // STLRB |
| 784U, // STLRH |
| 784U, // STLRW |
| 1474U, // STLRWpre |
| 784U, // STLRX |
| 1490U, // STLRXpre |
| 3676224U, // STLURBi |
| 3676224U, // STLURHi |
| 3676224U, // STLURWi |
| 3676224U, // STLURXi |
| 784U, // STLURbi |
| 784U, // STLURdi |
| 784U, // STLURhi |
| 784U, // STLURqi |
| 784U, // STLURsi |
| 17832000U, // STLXPW |
| 17832000U, // STLXPX |
| 3676512U, // STLXRB |
| 3676512U, // STLXRH |
| 3676512U, // STLXRW |
| 3676512U, // STLXRX |
| 738466144U, // STNPDi |
| 772020576U, // STNPQi |
| 805575008U, // STNPSi |
| 805575008U, // STNPWi |
| 738466144U, // STNPXi |
| 11294952U, // STNT1B_2Z |
| 712792296U, // STNT1B_2Z_IMM |
| 11294952U, // STNT1B_4Z |
| 714365160U, // STNT1B_4Z_IMM |
| 1275337062U, // STNT1B_VG2_M2ZPXI |
| 1308891494U, // STNT1B_VG2_M2ZPXX |
| 714365160U, // STNT1B_VG4_M4ZPXI |
| 11294952U, // STNT1B_VG4_M4ZPXX |
| 706762984U, // STNT1B_ZRI |
| 11294952U, // STNT1B_ZRR |
| 673208472U, // STNT1B_ZZR_D_REAL |
| 673208408U, // STNT1B_ZZR_S_REAL |
| 11557096U, // STNT1D_2Z |
| 712792296U, // STNT1D_2Z_IMM |
| 11557096U, // STNT1D_4Z |
| 714365160U, // STNT1D_4Z_IMM |
| 712792296U, // STNT1D_VG2_M2ZPXI |
| 11557096U, // STNT1D_VG2_M2ZPXX |
| 714365160U, // STNT1D_VG4_M4ZPXI |
| 11557096U, // STNT1D_VG4_M4ZPXX |
| 706762984U, // STNT1D_ZRI |
| 11557096U, // STNT1D_ZRR |
| 673208472U, // STNT1D_ZZR_D_REAL |
| 11819240U, // STNT1H_2Z |
| 712792296U, // STNT1H_2Z_IMM |
| 11819240U, // STNT1H_4Z |
| 714365160U, // STNT1H_4Z_IMM |
| 1275337062U, // STNT1H_VG2_M2ZPXI |
| 1342445926U, // STNT1H_VG2_M2ZPXX |
| 714365160U, // STNT1H_VG4_M4ZPXI |
| 11819240U, // STNT1H_VG4_M4ZPXX |
| 706762984U, // STNT1H_ZRI |
| 11819240U, // STNT1H_ZRR |
| 673208472U, // STNT1H_ZZR_D_REAL |
| 673208408U, // STNT1H_ZZR_S_REAL |
| 12343528U, // STNT1W_2Z |
| 712792296U, // STNT1W_2Z_IMM |
| 12343528U, // STNT1W_4Z |
| 714365160U, // STNT1W_4Z_IMM |
| 712792296U, // STNT1W_VG2_M2ZPXI |
| 12343528U, // STNT1W_VG2_M2ZPXX |
| 714365160U, // STNT1W_VG4_M4ZPXI |
| 12343528U, // STNT1W_VG4_M4ZPXX |
| 706762984U, // STNT1W_ZRI |
| 12343528U, // STNT1W_ZRR |
| 673208472U, // STNT1W_ZZR_D_REAL |
| 673208408U, // STNT1W_ZZR_S_REAL |
| 738466144U, // STPDi |
| 854151522U, // STPDpost |
| 839209314U, // STPDpre |
| 772020576U, // STPQi |
| 887705954U, // STPQpost |
| 872763746U, // STPQpre |
| 805575008U, // STPSi |
| 921260386U, // STPSpost |
| 906318178U, // STPSpre |
| 805575008U, // STPWi |
| 921260386U, // STPWpost |
| 906318178U, // STPWpre |
| 738466144U, // STPXi |
| 854151522U, // STPXpost |
| 839209314U, // STPXpre |
| 86850U, // STRBBpost |
| 15552578U, // STRBBpre |
| 939792448U, // STRBBroW |
| 973346880U, // STRBBroX |
| 122944U, // STRBBui |
| 86850U, // STRBpost |
| 15552578U, // STRBpre |
| 939792448U, // STRBroW |
| 973346880U, // STRBroX |
| 122944U, // STRBui |
| 86850U, // STRDpost |
| 15552578U, // STRDpre |
| 1006901312U, // STRDroW |
| 1040455744U, // STRDroX |
| 124992U, // STRDui |
| 86850U, // STRHHpost |
| 15552578U, // STRHHpre |
| 1074010176U, // STRHHroW |
| 1107564608U, // STRHHroX |
| 127040U, // STRHHui |
| 86850U, // STRHpost |
| 15552578U, // STRHpre |
| 1074010176U, // STRHroW |
| 1107564608U, // STRHroX |
| 127040U, // STRHui |
| 86850U, // STRQpost |
| 15552578U, // STRQpre |
| 1141119040U, // STRQroW |
| 1174673472U, // STRQroX |
| 129088U, // STRQui |
| 86850U, // STRSpost |
| 15552578U, // STRSpre |
| 1208227904U, // STRSroW |
| 1241782336U, // STRSroX |
| 131136U, // STRSui |
| 86850U, // STRWpost |
| 15552578U, // STRWpre |
| 1208227904U, // STRWroW |
| 1241782336U, // STRWroX |
| 131136U, // STRWui |
| 86850U, // STRXpost |
| 15552578U, // STRXpre |
| 1006901312U, // STRXroW |
| 1040455744U, // STRXroX |
| 124992U, // STRXui |
| 15734848U, // STR_PXI |
| 784U, // STR_TX |
| 0U, // STR_ZA |
| 15734848U, // STR_ZXI |
| 3676224U, // STTRBi |
| 3676224U, // STTRHi |
| 3676224U, // STTRWi |
| 3676224U, // STTRXi |
| 3676224U, // STURBBi |
| 3676224U, // STURBi |
| 3676224U, // STURDi |
| 3676224U, // STURHHi |
| 3676224U, // STURHi |
| 3676224U, // STURQi |
| 3676224U, // STURSi |
| 3676224U, // STURWi |
| 3676224U, // STURXi |
| 17832000U, // STXPW |
| 17832000U, // STXPX |
| 3676512U, // STXRB |
| 3676512U, // STXRH |
| 3676512U, // STXRW |
| 3676512U, // STXRX |
| 3678272U, // STZ2GOffset |
| 117570U, // STZ2GPostIndex |
| 15583298U, // STZ2GPreIndex |
| 784U, // STZGM |
| 3678272U, // STZGOffset |
| 117570U, // STZGPostIndex |
| 15583298U, // STZGPreIndex |
| 270400U, // SUBG |
| 10304U, // SUBHNB_ZZZ_B |
| 81U, // SUBHNB_ZZZ_H |
| 12353U, // SUBHNB_ZZZ_S |
| 14401U, // SUBHNT_ZZZ_B |
| 49U, // SUBHNT_ZZZ_H |
| 2112U, // SUBHNT_ZZZ_S |
| 16448U, // SUBHNv2i64_v2i32 |
| 18497U, // SUBHNv2i64_v4i32 |
| 16448U, // SUBHNv4i32_v4i16 |
| 18497U, // SUBHNv4i32_v8i16 |
| 18497U, // SUBHNv8i16_v16i8 |
| 16448U, // SUBHNv8i16_v8i8 |
| 6208U, // SUBP |
| 6208U, // SUBPS |
| 32834U, // SUBR_ZI_B |
| 34881U, // SUBR_ZI_D |
| 193U, // SUBR_ZI_H |
| 36930U, // SUBR_ZI_S |
| 33837153U, // SUBR_ZPmZ_B |
| 67383393U, // SUBR_ZPmZ_D |
| 101210225U, // SUBR_ZPmZ_H |
| 134504545U, // SUBR_ZPmZ_S |
| 26688U, // SUBSWri |
| 28736U, // SUBSWrs |
| 30784U, // SUBSWrx |
| 26688U, // SUBSXri |
| 28736U, // SUBSXrs |
| 30784U, // SUBSXrx |
| 792640U, // SUBSXrx64 |
| 26688U, // SUBWri |
| 28736U, // SUBWrs |
| 30784U, // SUBWrx |
| 26688U, // SUBXri |
| 28736U, // SUBXrs |
| 30784U, // SUBXrx |
| 792640U, // SUBXrx64 |
| 1071265U, // SUB_VG2_M2Z2Z_D |
| 1333425U, // SUB_VG2_M2Z2Z_S |
| 102258849U, // SUB_VG2_M2ZZ_D |
| 102521009U, // SUB_VG2_M2ZZ_S |
| 161U, // SUB_VG2_M2Z_D |
| 177U, // SUB_VG2_M2Z_S |
| 1071265U, // SUB_VG4_M4Z4Z_D |
| 1333425U, // SUB_VG4_M4Z4Z_S |
| 102258849U, // SUB_VG4_M4ZZ_D |
| 102521009U, // SUB_VG4_M4ZZ_S |
| 161U, // SUB_VG4_M4Z_D |
| 177U, // SUB_VG4_M4Z_S |
| 32834U, // SUB_ZI_B |
| 34881U, // SUB_ZI_D |
| 193U, // SUB_ZI_H |
| 36930U, // SUB_ZI_S |
| 33837153U, // SUB_ZPmZ_B |
| 67383393U, // SUB_ZPmZ_D |
| 101210225U, // SUB_ZPmZ_H |
| 134504545U, // SUB_ZPmZ_S |
| 20546U, // SUB_ZZZ_B |
| 12353U, // SUB_ZZZ_D |
| 113U, // SUB_ZZZ_H |
| 24642U, // SUB_ZZZ_S |
| 16448U, // SUBv16i8 |
| 6208U, // SUBv1i64 |
| 16448U, // SUBv2i32 |
| 16448U, // SUBv2i64 |
| 16448U, // SUBv4i16 |
| 16448U, // SUBv4i32 |
| 16448U, // SUBv8i16 |
| 16448U, // SUBv8i8 |
| 2983265U, // SUDOT_VG2_M2ZZI_BToS |
| 99681U, // SUDOT_VG2_M2ZZ_BToS |
| 2983265U, // SUDOT_VG4_M4ZZI_BToS |
| 99681U, // SUDOT_VG4_M4ZZ_BToS |
| 81939U, // SUDOT_ZZZI |
| 103303233U, // SUDOTlanev16i8 |
| 103303233U, // SUDOTlanev8i8 |
| 81330U, // SUMLALL_MZZI_BtoS |
| 2983265U, // SUMLALL_VG2_M2ZZI_BtoS |
| 99688U, // SUMLALL_VG2_M2ZZ_BtoS |
| 2983265U, // SUMLALL_VG4_M4ZZI_BtoS |
| 99688U, // SUMLALL_VG4_M4ZZ_BtoS |
| 0U, // SUMOPA_MPPZZ_D |
| 0U, // SUMOPA_MPPZZ_S |
| 0U, // SUMOPS_MPPZZ_D |
| 0U, // SUMOPS_MPPZZ_S |
| 2U, // SUNPKHI_ZZ_D |
| 0U, // SUNPKHI_ZZ_H |
| 0U, // SUNPKHI_ZZ_S |
| 2U, // SUNPKLO_ZZ_D |
| 0U, // SUNPKLO_ZZ_H |
| 0U, // SUNPKLO_ZZ_S |
| 0U, // SUNPK_VG2_2ZZ_D |
| 0U, // SUNPK_VG2_2ZZ_H |
| 0U, // SUNPK_VG2_2ZZ_S |
| 0U, // SUNPK_VG4_4Z2Z_D |
| 0U, // SUNPK_VG4_4Z2Z_H |
| 0U, // SUNPK_VG4_4Z2Z_S |
| 33837153U, // SUQADD_ZPmZ_B |
| 67383393U, // SUQADD_ZPmZ_D |
| 101210225U, // SUQADD_ZPmZ_H |
| 134504545U, // SUQADD_ZPmZ_S |
| 1U, // SUQADDv16i8 |
| 2U, // SUQADDv1i16 |
| 2U, // SUQADDv1i32 |
| 2U, // SUQADDv1i64 |
| 2U, // SUQADDv1i8 |
| 1U, // SUQADDv2i32 |
| 1U, // SUQADDv2i64 |
| 1U, // SUQADDv4i16 |
| 1U, // SUQADDv4i32 |
| 1U, // SUQADDv8i16 |
| 1U, // SUQADDv8i8 |
| 2983265U, // SUVDOT_VG4_M4ZZI_BToS |
| 0U, // SVC |
| 2961665U, // SVDOT_VG2_M2ZZI_HtoS |
| 2983265U, // SVDOT_VG4_M4ZZI_BtoS |
| 2961665U, // SVDOT_VG4_M4ZZI_HtoD |
| 6U, // SWPAB |
| 6U, // SWPAH |
| 6U, // SWPALB |
| 6U, // SWPALH |
| 6U, // SWPALW |
| 6U, // SWPALX |
| 6U, // SWPAW |
| 6U, // SWPAX |
| 6U, // SWPB |
| 6U, // SWPH |
| 6U, // SWPLB |
| 6U, // SWPLH |
| 6U, // SWPLW |
| 6U, // SWPLX |
| 115044U, // SWPP |
| 115044U, // SWPPA |
| 115044U, // SWPPAL |
| 115044U, // SWPPL |
| 6U, // SWPW |
| 6U, // SWPX |
| 32U, // SXTB_ZPmZ_D |
| 0U, // SXTB_ZPmZ_H |
| 48U, // SXTB_ZPmZ_S |
| 32U, // SXTH_ZPmZ_D |
| 48U, // SXTH_ZPmZ_S |
| 32U, // SXTW_ZPmZ_D |
| 168000U, // SYSLxt |
| 1514U, // SYSPxt |
| 1530U, // SYSPxt_XZR |
| 1546U, // SYSxt |
| 133U, // TBLQ_ZZZ_B |
| 10U, // TBLQ_ZZZ_D |
| 113U, // TBLQ_ZZZ_H |
| 24648U, // TBLQ_ZZZ_S |
| 133U, // TBL_ZZZZ_B |
| 10U, // TBL_ZZZZ_D |
| 113U, // TBL_ZZZZ_H |
| 24648U, // TBL_ZZZZ_S |
| 133U, // TBL_ZZZ_B |
| 10U, // TBL_ZZZ_D |
| 113U, // TBL_ZZZ_H |
| 24648U, // TBL_ZZZ_S |
| 1562U, // TBLv16i8Four |
| 1562U, // TBLv16i8One |
| 1562U, // TBLv16i8Three |
| 1562U, // TBLv16i8Two |
| 1578U, // TBLv8i8Four |
| 1578U, // TBLv8i8One |
| 1578U, // TBLv8i8Three |
| 1578U, // TBLv8i8Two |
| 170048U, // TBNZW |
| 170048U, // TBNZX |
| 19U, // TBXQ_ZZZ_B |
| 2112U, // TBXQ_ZZZ_D |
| 241U, // TBXQ_ZZZ_H |
| 4160U, // TBXQ_ZZZ_S |
| 19U, // TBX_ZZZ_B |
| 2112U, // TBX_ZZZ_D |
| 241U, // TBX_ZZZ_H |
| 4160U, // TBX_ZZZ_S |
| 1562U, // TBXv16i8Four |
| 1562U, // TBXv16i8One |
| 1562U, // TBXv16i8Three |
| 1562U, // TBXv16i8Two |
| 1578U, // TBXv8i8Four |
| 1578U, // TBXv8i8One |
| 1578U, // TBXv8i8Three |
| 1578U, // TBXv8i8Two |
| 170048U, // TBZW |
| 170048U, // TBZX |
| 0U, // TCANCEL |
| 0U, // TCOMMIT |
| 0U, // TRCIT |
| 20546U, // TRN1_PPP_B |
| 12353U, // TRN1_PPP_D |
| 113U, // TRN1_PPP_H |
| 24642U, // TRN1_PPP_S |
| 20546U, // TRN1_ZZZ_B |
| 12353U, // TRN1_ZZZ_D |
| 113U, // TRN1_ZZZ_H |
| 1585U, // TRN1_ZZZ_Q |
| 24642U, // TRN1_ZZZ_S |
| 16448U, // TRN1v16i8 |
| 16448U, // TRN1v2i32 |
| 16448U, // TRN1v2i64 |
| 16448U, // TRN1v4i16 |
| 16448U, // TRN1v4i32 |
| 16448U, // TRN1v8i16 |
| 16448U, // TRN1v8i8 |
| 20546U, // TRN2_PPP_B |
| 12353U, // TRN2_PPP_D |
| 113U, // TRN2_PPP_H |
| 24642U, // TRN2_PPP_S |
| 20546U, // TRN2_ZZZ_B |
| 12353U, // TRN2_ZZZ_D |
| 113U, // TRN2_ZZZ_H |
| 1585U, // TRN2_ZZZ_Q |
| 24642U, // TRN2_ZZZ_S |
| 16448U, // TRN2v16i8 |
| 16448U, // TRN2v2i32 |
| 16448U, // TRN2v2i64 |
| 16448U, // TRN2v4i16 |
| 16448U, // TRN2v4i32 |
| 16448U, // TRN2v8i16 |
| 16448U, // TRN2v8i8 |
| 0U, // TSB |
| 0U, // TSTART |
| 0U, // TTEST |
| 4160U, // UABALB_ZZZ_D |
| 17U, // UABALB_ZZZ_H |
| 14401U, // UABALB_ZZZ_S |
| 4160U, // UABALT_ZZZ_D |
| 17U, // UABALT_ZZZ_H |
| 14401U, // UABALT_ZZZ_S |
| 18497U, // UABALv16i8_v8i16 |
| 18497U, // UABALv2i32_v2i64 |
| 18497U, // UABALv4i16_v4i32 |
| 18497U, // UABALv4i32_v2i64 |
| 18497U, // UABALv8i16_v4i32 |
| 18497U, // UABALv8i8_v8i16 |
| 19U, // UABA_ZZZ_B |
| 2112U, // UABA_ZZZ_D |
| 241U, // UABA_ZZZ_H |
| 4160U, // UABA_ZZZ_S |
| 18497U, // UABAv16i8 |
| 18497U, // UABAv2i32 |
| 18497U, // UABAv4i16 |
| 18497U, // UABAv4i32 |
| 18497U, // UABAv8i16 |
| 18497U, // UABAv8i8 |
| 24642U, // UABDLB_ZZZ_D |
| 129U, // UABDLB_ZZZ_H |
| 10304U, // UABDLB_ZZZ_S |
| 24642U, // UABDLT_ZZZ_D |
| 129U, // UABDLT_ZZZ_H |
| 10304U, // UABDLT_ZZZ_S |
| 16448U, // UABDLv16i8_v8i16 |
| 16448U, // UABDLv2i32_v2i64 |
| 16448U, // UABDLv4i16_v4i32 |
| 16448U, // UABDLv4i32_v2i64 |
| 16448U, // UABDLv8i16_v4i32 |
| 16448U, // UABDLv8i8_v8i16 |
| 33837153U, // UABD_ZPmZ_B |
| 67383393U, // UABD_ZPmZ_D |
| 101210225U, // UABD_ZPmZ_H |
| 134504545U, // UABD_ZPmZ_S |
| 16448U, // UABDv16i8 |
| 16448U, // UABDv2i32 |
| 16448U, // UABDv4i16 |
| 16448U, // UABDv4i32 |
| 16448U, // UABDv8i16 |
| 16448U, // UABDv8i8 |
| 4193U, // UADALP_ZPmZ_D |
| 17U, // UADALP_ZPmZ_H |
| 14433U, // UADALP_ZPmZ_S |
| 1U, // UADALPv16i8_v8i16 |
| 1U, // UADALPv2i32_v1i64 |
| 1U, // UADALPv4i16_v2i32 |
| 1U, // UADALPv4i32_v2i64 |
| 1U, // UADALPv8i16_v4i32 |
| 1U, // UADALPv8i8_v4i16 |
| 24642U, // UADDLB_ZZZ_D |
| 129U, // UADDLB_ZZZ_H |
| 10304U, // UADDLB_ZZZ_S |
| 0U, // UADDLPv16i8_v8i16 |
| 0U, // UADDLPv2i32_v1i64 |
| 0U, // UADDLPv4i16_v2i32 |
| 0U, // UADDLPv4i32_v2i64 |
| 0U, // UADDLPv8i16_v4i32 |
| 0U, // UADDLPv8i8_v4i16 |
| 24642U, // UADDLT_ZZZ_D |
| 129U, // UADDLT_ZZZ_H |
| 10304U, // UADDLT_ZZZ_S |
| 0U, // UADDLVv16i8v |
| 0U, // UADDLVv4i16v |
| 0U, // UADDLVv4i32v |
| 0U, // UADDLVv8i16v |
| 0U, // UADDLVv8i8v |
| 16448U, // UADDLv16i8_v8i16 |
| 16448U, // UADDLv2i32_v2i64 |
| 16448U, // UADDLv4i16_v4i32 |
| 16448U, // UADDLv4i32_v2i64 |
| 16448U, // UADDLv8i16_v4i32 |
| 16448U, // UADDLv8i8_v8i16 |
| 0U, // UADDV_VPZ_B |
| 0U, // UADDV_VPZ_D |
| 0U, // UADDV_VPZ_H |
| 0U, // UADDV_VPZ_S |
| 24641U, // UADDWB_ZZZ_D |
| 129U, // UADDWB_ZZZ_H |
| 10306U, // UADDWB_ZZZ_S |
| 24641U, // UADDWT_ZZZ_D |
| 129U, // UADDWT_ZZZ_H |
| 10306U, // UADDWT_ZZZ_S |
| 16448U, // UADDWv16i8_v8i16 |
| 16448U, // UADDWv2i32_v2i64 |
| 16448U, // UADDWv4i16_v4i32 |
| 16448U, // UADDWv4i32_v2i64 |
| 16448U, // UADDWv8i16_v4i32 |
| 16448U, // UADDWv8i8_v8i16 |
| 268352U, // UBFMWri |
| 268352U, // UBFMXri |
| 17U, // UCLAMP_VG2_2Z2Z_B |
| 33U, // UCLAMP_VG2_2Z2Z_D |
| 241U, // UCLAMP_VG2_2Z2Z_H |
| 49U, // UCLAMP_VG2_2Z2Z_S |
| 17U, // UCLAMP_VG4_4Z4Z_B |
| 33U, // UCLAMP_VG4_4Z4Z_D |
| 241U, // UCLAMP_VG4_4Z4Z_H |
| 49U, // UCLAMP_VG4_4Z4Z_S |
| 20546U, // UCLAMP_ZZZ_B |
| 12353U, // UCLAMP_ZZZ_D |
| 113U, // UCLAMP_ZZZ_H |
| 24642U, // UCLAMP_ZZZ_S |
| 6208U, // UCVTFSWDri |
| 6208U, // UCVTFSWHri |
| 6208U, // UCVTFSWSri |
| 6208U, // UCVTFSXDri |
| 6208U, // UCVTFSXHri |
| 6208U, // UCVTFSXSri |
| 0U, // UCVTFUWDri |
| 0U, // UCVTFUWHri |
| 0U, // UCVTFUWSri |
| 0U, // UCVTFUXDri |
| 0U, // UCVTFUXHri |
| 0U, // UCVTFUXSri |
| 0U, // UCVTF_2Z2Z_StoS |
| 0U, // UCVTF_4Z4Z_StoS |
| 32U, // UCVTF_ZPmZ_DtoD |
| 5U, // UCVTF_ZPmZ_DtoH |
| 32U, // UCVTF_ZPmZ_DtoS |
| 0U, // UCVTF_ZPmZ_HtoH |
| 48U, // UCVTF_ZPmZ_StoD |
| 2U, // UCVTF_ZPmZ_StoH |
| 48U, // UCVTF_ZPmZ_StoS |
| 6208U, // UCVTFd |
| 6208U, // UCVTFh |
| 6208U, // UCVTFs |
| 0U, // UCVTFv1i16 |
| 0U, // UCVTFv1i32 |
| 0U, // UCVTFv1i64 |
| 0U, // UCVTFv2f32 |
| 0U, // UCVTFv2f64 |
| 6208U, // UCVTFv2i32_shift |
| 6208U, // UCVTFv2i64_shift |
| 0U, // UCVTFv4f16 |
| 0U, // UCVTFv4f32 |
| 6208U, // UCVTFv4i16_shift |
| 6208U, // UCVTFv4i32_shift |
| 0U, // UCVTFv8f16 |
| 6208U, // UCVTFv8i16_shift |
| 0U, // UDF |
| 67383393U, // UDIVR_ZPmZ_D |
| 134504545U, // UDIVR_ZPmZ_S |
| 6208U, // UDIVWr |
| 6208U, // UDIVXr |
| 67383393U, // UDIV_ZPmZ_D |
| 134504545U, // UDIV_ZPmZ_S |
| 157025U, // UDOT_VG2_M2Z2Z_BtoS |
| 76033U, // UDOT_VG2_M2Z2Z_HtoD |
| 76033U, // UDOT_VG2_M2Z2Z_HtoS |
| 2983265U, // UDOT_VG2_M2ZZI_BToS |
| 2961665U, // UDOT_VG2_M2ZZI_HToS |
| 2961665U, // UDOT_VG2_M2ZZI_HtoD |
| 99681U, // UDOT_VG2_M2ZZ_BtoS |
| 78081U, // UDOT_VG2_M2ZZ_HtoD |
| 78081U, // UDOT_VG2_M2ZZ_HtoS |
| 157025U, // UDOT_VG4_M4Z4Z_BtoS |
| 76033U, // UDOT_VG4_M4Z4Z_HtoD |
| 76033U, // UDOT_VG4_M4Z4Z_HtoS |
| 2983265U, // UDOT_VG4_M4ZZI_BtoS |
| 2961665U, // UDOT_VG4_M4ZZI_HToS |
| 2961665U, // UDOT_VG4_M4ZZI_HtoD |
| 99681U, // UDOT_VG4_M4ZZ_BtoS |
| 78081U, // UDOT_VG4_M4ZZ_HtoD |
| 78081U, // UDOT_VG4_M4ZZ_HtoS |
| 103299137U, // UDOT_ZZZI_D |
| 103299137U, // UDOT_ZZZI_HtoS |
| 81939U, // UDOT_ZZZI_S |
| 14401U, // UDOT_ZZZ_D |
| 14401U, // UDOT_ZZZ_HtoS |
| 19U, // UDOT_ZZZ_S |
| 103303233U, // UDOTlanev16i8 |
| 103303233U, // UDOTlanev8i8 |
| 0U, // UDOTv16i8 |
| 0U, // UDOTv8i8 |
| 33837153U, // UHADD_ZPmZ_B |
| 67383393U, // UHADD_ZPmZ_D |
| 101210225U, // UHADD_ZPmZ_H |
| 134504545U, // UHADD_ZPmZ_S |
| 16448U, // UHADDv16i8 |
| 16448U, // UHADDv2i32 |
| 16448U, // UHADDv4i16 |
| 16448U, // UHADDv4i32 |
| 16448U, // UHADDv8i16 |
| 16448U, // UHADDv8i8 |
| 33837153U, // UHSUBR_ZPmZ_B |
| 67383393U, // UHSUBR_ZPmZ_D |
| 101210225U, // UHSUBR_ZPmZ_H |
| 134504545U, // UHSUBR_ZPmZ_S |
| 33837153U, // UHSUB_ZPmZ_B |
| 67383393U, // UHSUB_ZPmZ_D |
| 101210225U, // UHSUB_ZPmZ_H |
| 134504545U, // UHSUB_ZPmZ_S |
| 16448U, // UHSUBv16i8 |
| 16448U, // UHSUBv2i32 |
| 16448U, // UHSUBv4i16 |
| 16448U, // UHSUBv4i32 |
| 16448U, // UHSUBv8i16 |
| 16448U, // UHSUBv8i8 |
| 268352U, // UMADDLrrr |
| 33837153U, // UMAXP_ZPmZ_B |
| 67383393U, // UMAXP_ZPmZ_D |
| 101210225U, // UMAXP_ZPmZ_H |
| 134504545U, // UMAXP_ZPmZ_S |
| 16448U, // UMAXPv16i8 |
| 16448U, // UMAXPv2i32 |
| 16448U, // UMAXPv4i16 |
| 16448U, // UMAXPv4i32 |
| 16448U, // UMAXPv8i16 |
| 16448U, // UMAXPv8i8 |
| 20545U, // UMAXQV_VPZ_B |
| 12353U, // UMAXQV_VPZ_D |
| 10305U, // UMAXQV_VPZ_H |
| 24641U, // UMAXQV_VPZ_S |
| 0U, // UMAXV_VPZ_B |
| 0U, // UMAXV_VPZ_D |
| 0U, // UMAXV_VPZ_H |
| 0U, // UMAXV_VPZ_S |
| 0U, // UMAXVv16i8v |
| 0U, // UMAXVv4i16v |
| 0U, // UMAXVv4i32v |
| 0U, // UMAXVv8i16v |
| 0U, // UMAXVv8i8v |
| 6208U, // UMAXWri |
| 6208U, // UMAXWrr |
| 6208U, // UMAXXri |
| 6208U, // UMAXXrr |
| 1393U, // UMAX_VG2_2Z2Z_B |
| 657U, // UMAX_VG2_2Z2Z_D |
| 273U, // UMAX_VG2_2Z2Z_H |
| 673U, // UMAX_VG2_2Z2Z_S |
| 129U, // UMAX_VG2_2ZZ_B |
| 145U, // UMAX_VG2_2ZZ_D |
| 113U, // UMAX_VG2_2ZZ_H |
| 81U, // UMAX_VG2_2ZZ_S |
| 1393U, // UMAX_VG4_4Z4Z_B |
| 657U, // UMAX_VG4_4Z4Z_D |
| 273U, // UMAX_VG4_4Z4Z_H |
| 673U, // UMAX_VG4_4Z4Z_S |
| 129U, // UMAX_VG4_4ZZ_B |
| 145U, // UMAX_VG4_4ZZ_D |
| 113U, // UMAX_VG4_4ZZ_H |
| 81U, // UMAX_VG4_4ZZ_S |
| 172098U, // UMAX_ZI_B |
| 172097U, // UMAX_ZI_D |
| 529U, // UMAX_ZI_H |
| 172098U, // UMAX_ZI_S |
| 33837153U, // UMAX_ZPmZ_B |
| 67383393U, // UMAX_ZPmZ_D |
| 101210225U, // UMAX_ZPmZ_H |
| 134504545U, // UMAX_ZPmZ_S |
| 16448U, // UMAXv16i8 |
| 16448U, // UMAXv2i32 |
| 16448U, // UMAXv4i16 |
| 16448U, // UMAXv4i32 |
| 16448U, // UMAXv8i16 |
| 16448U, // UMAXv8i8 |
| 33837153U, // UMINP_ZPmZ_B |
| 67383393U, // UMINP_ZPmZ_D |
| 101210225U, // UMINP_ZPmZ_H |
| 134504545U, // UMINP_ZPmZ_S |
| 16448U, // UMINPv16i8 |
| 16448U, // UMINPv2i32 |
| 16448U, // UMINPv4i16 |
| 16448U, // UMINPv4i32 |
| 16448U, // UMINPv8i16 |
| 16448U, // UMINPv8i8 |
| 20545U, // UMINQV_VPZ_B |
| 12353U, // UMINQV_VPZ_D |
| 10305U, // UMINQV_VPZ_H |
| 24641U, // UMINQV_VPZ_S |
| 0U, // UMINV_VPZ_B |
| 0U, // UMINV_VPZ_D |
| 0U, // UMINV_VPZ_H |
| 0U, // UMINV_VPZ_S |
| 0U, // UMINVv16i8v |
| 0U, // UMINVv4i16v |
| 0U, // UMINVv4i32v |
| 0U, // UMINVv8i16v |
| 0U, // UMINVv8i8v |
| 6208U, // UMINWri |
| 6208U, // UMINWrr |
| 6208U, // UMINXri |
| 6208U, // UMINXrr |
| 1393U, // UMIN_VG2_2Z2Z_B |
| 657U, // UMIN_VG2_2Z2Z_D |
| 273U, // UMIN_VG2_2Z2Z_H |
| 673U, // UMIN_VG2_2Z2Z_S |
| 129U, // UMIN_VG2_2ZZ_B |
| 145U, // UMIN_VG2_2ZZ_D |
| 113U, // UMIN_VG2_2ZZ_H |
| 81U, // UMIN_VG2_2ZZ_S |
| 1393U, // UMIN_VG4_4Z4Z_B |
| 657U, // UMIN_VG4_4Z4Z_D |
| 273U, // UMIN_VG4_4Z4Z_H |
| 673U, // UMIN_VG4_4Z4Z_S |
| 129U, // UMIN_VG4_4ZZ_B |
| 145U, // UMIN_VG4_4ZZ_D |
| 113U, // UMIN_VG4_4ZZ_H |
| 81U, // UMIN_VG4_4ZZ_S |
| 172098U, // UMIN_ZI_B |
| 172097U, // UMIN_ZI_D |
| 529U, // UMIN_ZI_H |
| 172098U, // UMIN_ZI_S |
| 33837153U, // UMIN_ZPmZ_B |
| 67383393U, // UMIN_ZPmZ_D |
| 101210225U, // UMIN_ZPmZ_H |
| 134504545U, // UMIN_ZPmZ_S |
| 16448U, // UMINv16i8 |
| 16448U, // UMINv2i32 |
| 16448U, // UMINv4i16 |
| 16448U, // UMINv4i32 |
| 16448U, // UMINv8i16 |
| 16448U, // UMINv8i8 |
| 103288896U, // UMLALB_ZZZI_D |
| 103299137U, // UMLALB_ZZZI_S |
| 4160U, // UMLALB_ZZZ_D |
| 17U, // UMLALB_ZZZ_H |
| 14401U, // UMLALB_ZZZ_S |
| 81330U, // UMLALL_MZZI_BtoS |
| 80162U, // UMLALL_MZZI_HtoD |
| 1458U, // UMLALL_MZZ_BtoS |
| 290U, // UMLALL_MZZ_HtoD |
| 157025U, // UMLALL_VG2_M2Z2Z_BtoS |
| 76033U, // UMLALL_VG2_M2Z2Z_HtoD |
| 2983265U, // UMLALL_VG2_M2ZZI_BtoS |
| 2961665U, // UMLALL_VG2_M2ZZI_HtoD |
| 99688U, // UMLALL_VG2_M2ZZ_BtoS |
| 78088U, // UMLALL_VG2_M2ZZ_HtoD |
| 157025U, // UMLALL_VG4_M4Z4Z_BtoS |
| 76033U, // UMLALL_VG4_M4Z4Z_HtoD |
| 2983265U, // UMLALL_VG4_M4ZZI_BtoS |
| 2961665U, // UMLALL_VG4_M4ZZI_HtoD |
| 99688U, // UMLALL_VG4_M4ZZ_BtoS |
| 78088U, // UMLALL_VG4_M4ZZ_HtoD |
| 103288896U, // UMLALT_ZZZI_D |
| 103299137U, // UMLALT_ZZZI_S |
| 4160U, // UMLALT_ZZZ_D |
| 17U, // UMLALT_ZZZ_H |
| 14401U, // UMLALT_ZZZ_S |
| 80162U, // UMLAL_MZZI_S |
| 290U, // UMLAL_MZZ_S |
| 76033U, // UMLAL_VG2_M2Z2Z_S |
| 2961665U, // UMLAL_VG2_M2ZZI_S |
| 78081U, // UMLAL_VG2_M2ZZ_S |
| 76033U, // UMLAL_VG4_M4Z4Z_S |
| 2961665U, // UMLAL_VG4_M4ZZI_S |
| 78081U, // UMLAL_VG4_M4ZZ_S |
| 18497U, // UMLALv16i8_v8i16 |
| 103303233U, // UMLALv2i32_indexed |
| 18497U, // UMLALv2i32_v2i64 |
| 103303233U, // UMLALv4i16_indexed |
| 18497U, // UMLALv4i16_v4i32 |
| 103303233U, // UMLALv4i32_indexed |
| 18497U, // UMLALv4i32_v2i64 |
| 103303233U, // UMLALv8i16_indexed |
| 18497U, // UMLALv8i16_v4i32 |
| 18497U, // UMLALv8i8_v8i16 |
| 103288896U, // UMLSLB_ZZZI_D |
| 103299137U, // UMLSLB_ZZZI_S |
| 4160U, // UMLSLB_ZZZ_D |
| 17U, // UMLSLB_ZZZ_H |
| 14401U, // UMLSLB_ZZZ_S |
| 81330U, // UMLSLL_MZZI_BtoS |
| 80162U, // UMLSLL_MZZI_HtoD |
| 1458U, // UMLSLL_MZZ_BtoS |
| 290U, // UMLSLL_MZZ_HtoD |
| 157025U, // UMLSLL_VG2_M2Z2Z_BtoS |
| 76033U, // UMLSLL_VG2_M2Z2Z_HtoD |
| 2983265U, // UMLSLL_VG2_M2ZZI_BtoS |
| 2961665U, // UMLSLL_VG2_M2ZZI_HtoD |
| 99688U, // UMLSLL_VG2_M2ZZ_BtoS |
| 78088U, // UMLSLL_VG2_M2ZZ_HtoD |
| 157025U, // UMLSLL_VG4_M4Z4Z_BtoS |
| 76033U, // UMLSLL_VG4_M4Z4Z_HtoD |
| 2983265U, // UMLSLL_VG4_M4ZZI_BtoS |
| 2961665U, // UMLSLL_VG4_M4ZZI_HtoD |
| 99688U, // UMLSLL_VG4_M4ZZ_BtoS |
| 78088U, // UMLSLL_VG4_M4ZZ_HtoD |
| 103288896U, // UMLSLT_ZZZI_D |
| 103299137U, // UMLSLT_ZZZI_S |
| 4160U, // UMLSLT_ZZZ_D |
| 17U, // UMLSLT_ZZZ_H |
| 14401U, // UMLSLT_ZZZ_S |
| 80162U, // UMLSL_MZZI_S |
| 290U, // UMLSL_MZZ_S |
| 76033U, // UMLSL_VG2_M2Z2Z_S |
| 2961665U, // UMLSL_VG2_M2ZZI_S |
| 78081U, // UMLSL_VG2_M2ZZ_S |
| 76033U, // UMLSL_VG4_M4Z4Z_S |
| 2961665U, // UMLSL_VG4_M4ZZI_S |
| 78081U, // UMLSL_VG4_M4ZZ_S |
| 18497U, // UMLSLv16i8_v8i16 |
| 103303233U, // UMLSLv2i32_indexed |
| 18497U, // UMLSLv2i32_v2i64 |
| 103303233U, // UMLSLv4i16_indexed |
| 18497U, // UMLSLv4i16_v4i32 |
| 103303233U, // UMLSLv4i32_indexed |
| 18497U, // UMLSLv4i32_v2i64 |
| 103303233U, // UMLSLv8i16_indexed |
| 18497U, // UMLSLv8i16_v4i32 |
| 18497U, // UMLSLv8i8_v8i16 |
| 0U, // UMMLA |
| 19U, // UMMLA_ZZZ |
| 0U, // UMOPA_MPPZZ_D |
| 0U, // UMOPA_MPPZZ_HtoS |
| 0U, // UMOPA_MPPZZ_S |
| 0U, // UMOPS_MPPZZ_D |
| 0U, // UMOPS_MPPZZ_HtoS |
| 0U, // UMOPS_MPPZZ_S |
| 480U, // UMOVvi16 |
| 480U, // UMOVvi16_idx0 |
| 480U, // UMOVvi32 |
| 480U, // UMOVvi32_idx0 |
| 480U, // UMOVvi64 |
| 480U, // UMOVvi64_idx0 |
| 480U, // UMOVvi8 |
| 480U, // UMOVvi8_idx0 |
| 268352U, // UMSUBLrrr |
| 33837153U, // UMULH_ZPmZ_B |
| 67383393U, // UMULH_ZPmZ_D |
| 101210225U, // UMULH_ZPmZ_H |
| 134504545U, // UMULH_ZPmZ_S |
| 20546U, // UMULH_ZZZ_B |
| 12353U, // UMULH_ZZZ_D |
| 113U, // UMULH_ZZZ_H |
| 24642U, // UMULH_ZZZ_S |
| 6208U, // UMULHrr |
| 5267522U, // UMULLB_ZZZI_D |
| 5253184U, // UMULLB_ZZZI_S |
| 24642U, // UMULLB_ZZZ_D |
| 129U, // UMULLB_ZZZ_H |
| 10304U, // UMULLB_ZZZ_S |
| 5267522U, // UMULLT_ZZZI_D |
| 5253184U, // UMULLT_ZZZI_S |
| 24642U, // UMULLT_ZZZ_D |
| 129U, // UMULLT_ZZZ_H |
| 10304U, // UMULLT_ZZZ_S |
| 16448U, // UMULLv16i8_v8i16 |
| 5259328U, // UMULLv2i32_indexed |
| 16448U, // UMULLv2i32_v2i64 |
| 5259328U, // UMULLv4i16_indexed |
| 16448U, // UMULLv4i16_v4i32 |
| 5259328U, // UMULLv4i32_indexed |
| 16448U, // UMULLv4i32_v2i64 |
| 5259328U, // UMULLv8i16_indexed |
| 16448U, // UMULLv8i16_v4i32 |
| 16448U, // UMULLv8i8_v8i16 |
| 32834U, // UQADD_ZI_B |
| 34881U, // UQADD_ZI_D |
| 193U, // UQADD_ZI_H |
| 36930U, // UQADD_ZI_S |
| 33837153U, // UQADD_ZPmZ_B |
| 67383393U, // UQADD_ZPmZ_D |
| 101210225U, // UQADD_ZPmZ_H |
| 134504545U, // UQADD_ZPmZ_S |
| 20546U, // UQADD_ZZZ_B |
| 12353U, // UQADD_ZZZ_D |
| 113U, // UQADD_ZZZ_H |
| 24642U, // UQADD_ZZZ_S |
| 16448U, // UQADDv16i8 |
| 6208U, // UQADDv1i16 |
| 6208U, // UQADDv1i32 |
| 6208U, // UQADDv1i64 |
| 6208U, // UQADDv1i8 |
| 16448U, // UQADDv2i32 |
| 16448U, // UQADDv2i64 |
| 16448U, // UQADDv4i16 |
| 16448U, // UQADDv4i32 |
| 16448U, // UQADDv8i16 |
| 16448U, // UQADDv8i8 |
| 0U, // UQCVTN_Z2Z_StoH |
| 0U, // UQCVTN_Z4Z_DtoH |
| 8U, // UQCVTN_Z4Z_StoB |
| 0U, // UQCVT_Z2Z_StoH |
| 0U, // UQCVT_Z4Z_DtoH |
| 8U, // UQCVT_Z4Z_StoB |
| 4U, // UQDECB_WPiI |
| 4U, // UQDECB_XPiI |
| 4U, // UQDECD_WPiI |
| 4U, // UQDECD_XPiI |
| 4U, // UQDECD_ZPiI |
| 4U, // UQDECH_WPiI |
| 4U, // UQDECH_XPiI |
| 0U, // UQDECH_ZPiI |
| 2U, // UQDECP_WP_B |
| 1U, // UQDECP_WP_D |
| 0U, // UQDECP_WP_H |
| 2U, // UQDECP_WP_S |
| 2U, // UQDECP_XP_B |
| 1U, // UQDECP_XP_D |
| 0U, // UQDECP_XP_H |
| 2U, // UQDECP_XP_S |
| 0U, // UQDECP_ZP_D |
| 0U, // UQDECP_ZP_H |
| 0U, // UQDECP_ZP_S |
| 4U, // UQDECW_WPiI |
| 4U, // UQDECW_XPiI |
| 4U, // UQDECW_ZPiI |
| 4U, // UQINCB_WPiI |
| 4U, // UQINCB_XPiI |
| 4U, // UQINCD_WPiI |
| 4U, // UQINCD_XPiI |
| 4U, // UQINCD_ZPiI |
| 4U, // UQINCH_WPiI |
| 4U, // UQINCH_XPiI |
| 0U, // UQINCH_ZPiI |
| 2U, // UQINCP_WP_B |
| 1U, // UQINCP_WP_D |
| 0U, // UQINCP_WP_H |
| 2U, // UQINCP_WP_S |
| 2U, // UQINCP_XP_B |
| 1U, // UQINCP_XP_D |
| 0U, // UQINCP_XP_H |
| 2U, // UQINCP_XP_S |
| 0U, // UQINCP_ZP_D |
| 0U, // UQINCP_ZP_H |
| 0U, // UQINCP_ZP_S |
| 4U, // UQINCW_WPiI |
| 4U, // UQINCW_XPiI |
| 4U, // UQINCW_ZPiI |
| 33837153U, // UQRSHLR_ZPmZ_B |
| 67383393U, // UQRSHLR_ZPmZ_D |
| 101210225U, // UQRSHLR_ZPmZ_H |
| 134504545U, // UQRSHLR_ZPmZ_S |
| 33837153U, // UQRSHL_ZPmZ_B |
| 67383393U, // UQRSHL_ZPmZ_D |
| 101210225U, // UQRSHL_ZPmZ_H |
| 134504545U, // UQRSHL_ZPmZ_S |
| 16448U, // UQRSHLv16i8 |
| 6208U, // UQRSHLv1i16 |
| 6208U, // UQRSHLv1i32 |
| 6208U, // UQRSHLv1i64 |
| 6208U, // UQRSHLv1i8 |
| 16448U, // UQRSHLv2i32 |
| 16448U, // UQRSHLv2i64 |
| 16448U, // UQRSHLv4i16 |
| 16448U, // UQRSHLv4i32 |
| 16448U, // UQRSHLv8i16 |
| 16448U, // UQRSHLv8i8 |
| 6208U, // UQRSHRNB_ZZI_B |
| 225U, // UQRSHRNB_ZZI_H |
| 6209U, // UQRSHRNB_ZZI_S |
| 86081U, // UQRSHRNT_ZZI_B |
| 449U, // UQRSHRNT_ZZI_H |
| 86080U, // UQRSHRNT_ZZI_S |
| 6216U, // UQRSHRN_VG4_Z4ZI_B |
| 225U, // UQRSHRN_VG4_Z4ZI_H |
| 6208U, // UQRSHRNb |
| 6208U, // UQRSHRNh |
| 6208U, // UQRSHRNs |
| 86081U, // UQRSHRNv16i8_shift |
| 6208U, // UQRSHRNv2i32_shift |
| 6208U, // UQRSHRNv4i16_shift |
| 86081U, // UQRSHRNv4i32_shift |
| 86081U, // UQRSHRNv8i16_shift |
| 6208U, // UQRSHRNv8i8_shift |
| 225U, // UQRSHR_VG2_Z2ZI_H |
| 6216U, // UQRSHR_VG4_Z4ZI_B |
| 225U, // UQRSHR_VG4_Z4ZI_H |
| 33837153U, // UQSHLR_ZPmZ_B |
| 67383393U, // UQSHLR_ZPmZ_D |
| 101210225U, // UQSHLR_ZPmZ_H |
| 134504545U, // UQSHLR_ZPmZ_S |
| 282721U, // UQSHL_ZPmI_B |
| 274529U, // UQSHL_ZPmI_D |
| 102783089U, // UQSHL_ZPmI_H |
| 286817U, // UQSHL_ZPmI_S |
| 33837153U, // UQSHL_ZPmZ_B |
| 67383393U, // UQSHL_ZPmZ_D |
| 101210225U, // UQSHL_ZPmZ_H |
| 134504545U, // UQSHL_ZPmZ_S |
| 6208U, // UQSHLb |
| 6208U, // UQSHLd |
| 6208U, // UQSHLh |
| 6208U, // UQSHLs |
| 16448U, // UQSHLv16i8 |
| 6208U, // UQSHLv16i8_shift |
| 6208U, // UQSHLv1i16 |
| 6208U, // UQSHLv1i32 |
| 6208U, // UQSHLv1i64 |
| 6208U, // UQSHLv1i8 |
| 16448U, // UQSHLv2i32 |
| 6208U, // UQSHLv2i32_shift |
| 16448U, // UQSHLv2i64 |
| 6208U, // UQSHLv2i64_shift |
| 16448U, // UQSHLv4i16 |
| 6208U, // UQSHLv4i16_shift |
| 16448U, // UQSHLv4i32 |
| 6208U, // UQSHLv4i32_shift |
| 16448U, // UQSHLv8i16 |
| 6208U, // UQSHLv8i16_shift |
| 16448U, // UQSHLv8i8 |
| 6208U, // UQSHLv8i8_shift |
| 6208U, // UQSHRNB_ZZI_B |
| 225U, // UQSHRNB_ZZI_H |
| 6209U, // UQSHRNB_ZZI_S |
| 86081U, // UQSHRNT_ZZI_B |
| 449U, // UQSHRNT_ZZI_H |
| 86080U, // UQSHRNT_ZZI_S |
| 6208U, // UQSHRNb |
| 6208U, // UQSHRNh |
| 6208U, // UQSHRNs |
| 86081U, // UQSHRNv16i8_shift |
| 6208U, // UQSHRNv2i32_shift |
| 6208U, // UQSHRNv4i16_shift |
| 86081U, // UQSHRNv4i32_shift |
| 86081U, // UQSHRNv8i16_shift |
| 6208U, // UQSHRNv8i8_shift |
| 33837153U, // UQSUBR_ZPmZ_B |
| 67383393U, // UQSUBR_ZPmZ_D |
| 101210225U, // UQSUBR_ZPmZ_H |
| 134504545U, // UQSUBR_ZPmZ_S |
| 32834U, // UQSUB_ZI_B |
| 34881U, // UQSUB_ZI_D |
| 193U, // UQSUB_ZI_H |
| 36930U, // UQSUB_ZI_S |
| 33837153U, // UQSUB_ZPmZ_B |
| 67383393U, // UQSUB_ZPmZ_D |
| 101210225U, // UQSUB_ZPmZ_H |
| 134504545U, // UQSUB_ZPmZ_S |
| 20546U, // UQSUB_ZZZ_B |
| 12353U, // UQSUB_ZZZ_D |
| 113U, // UQSUB_ZZZ_H |
| 24642U, // UQSUB_ZZZ_S |
| 16448U, // UQSUBv16i8 |
| 6208U, // UQSUBv1i16 |
| 6208U, // UQSUBv1i32 |
| 6208U, // UQSUBv1i64 |
| 6208U, // UQSUBv1i8 |
| 16448U, // UQSUBv2i32 |
| 16448U, // UQSUBv2i64 |
| 16448U, // UQSUBv4i16 |
| 16448U, // UQSUBv4i32 |
| 16448U, // UQSUBv8i16 |
| 16448U, // UQSUBv8i8 |
| 0U, // UQXTNB_ZZ_B |
| 0U, // UQXTNB_ZZ_H |
| 1U, // UQXTNB_ZZ_S |
| 1U, // UQXTNT_ZZ_B |
| 0U, // UQXTNT_ZZ_H |
| 0U, // UQXTNT_ZZ_S |
| 1U, // UQXTNv16i8 |
| 0U, // UQXTNv1i16 |
| 0U, // UQXTNv1i32 |
| 0U, // UQXTNv1i8 |
| 0U, // UQXTNv2i32 |
| 0U, // UQXTNv4i16 |
| 1U, // UQXTNv4i32 |
| 1U, // UQXTNv8i16 |
| 0U, // UQXTNv8i8 |
| 48U, // URECPE_ZPmZ_S |
| 0U, // URECPEv2i32 |
| 0U, // URECPEv4i32 |
| 33837153U, // URHADD_ZPmZ_B |
| 67383393U, // URHADD_ZPmZ_D |
| 101210225U, // URHADD_ZPmZ_H |
| 134504545U, // URHADD_ZPmZ_S |
| 16448U, // URHADDv16i8 |
| 16448U, // URHADDv2i32 |
| 16448U, // URHADDv4i16 |
| 16448U, // URHADDv4i32 |
| 16448U, // URHADDv8i16 |
| 16448U, // URHADDv8i8 |
| 33837153U, // URSHLR_ZPmZ_B |
| 67383393U, // URSHLR_ZPmZ_D |
| 101210225U, // URSHLR_ZPmZ_H |
| 134504545U, // URSHLR_ZPmZ_S |
| 1393U, // URSHL_VG2_2Z2Z_B |
| 657U, // URSHL_VG2_2Z2Z_D |
| 273U, // URSHL_VG2_2Z2Z_H |
| 673U, // URSHL_VG2_2Z2Z_S |
| 129U, // URSHL_VG2_2ZZ_B |
| 145U, // URSHL_VG2_2ZZ_D |
| 113U, // URSHL_VG2_2ZZ_H |
| 81U, // URSHL_VG2_2ZZ_S |
| 1393U, // URSHL_VG4_4Z4Z_B |
| 657U, // URSHL_VG4_4Z4Z_D |
| 273U, // URSHL_VG4_4Z4Z_H |
| 673U, // URSHL_VG4_4Z4Z_S |
| 129U, // URSHL_VG4_4ZZ_B |
| 145U, // URSHL_VG4_4ZZ_D |
| 113U, // URSHL_VG4_4ZZ_H |
| 81U, // URSHL_VG4_4ZZ_S |
| 33837153U, // URSHL_ZPmZ_B |
| 67383393U, // URSHL_ZPmZ_D |
| 101210225U, // URSHL_ZPmZ_H |
| 134504545U, // URSHL_ZPmZ_S |
| 16448U, // URSHLv16i8 |
| 6208U, // URSHLv1i64 |
| 16448U, // URSHLv2i32 |
| 16448U, // URSHLv2i64 |
| 16448U, // URSHLv4i16 |
| 16448U, // URSHLv4i32 |
| 16448U, // URSHLv8i16 |
| 16448U, // URSHLv8i8 |
| 282721U, // URSHR_ZPmI_B |
| 274529U, // URSHR_ZPmI_D |
| 102783089U, // URSHR_ZPmI_H |
| 286817U, // URSHR_ZPmI_S |
| 6208U, // URSHRd |
| 6208U, // URSHRv16i8_shift |
| 6208U, // URSHRv2i32_shift |
| 6208U, // URSHRv2i64_shift |
| 6208U, // URSHRv4i16_shift |
| 6208U, // URSHRv4i32_shift |
| 6208U, // URSHRv8i16_shift |
| 6208U, // URSHRv8i8_shift |
| 48U, // URSQRTE_ZPmZ_S |
| 0U, // URSQRTEv2i32 |
| 0U, // URSQRTEv4i32 |
| 451U, // URSRA_ZZI_B |
| 86080U, // URSRA_ZZI_D |
| 449U, // URSRA_ZZI_H |
| 86080U, // URSRA_ZZI_S |
| 86082U, // URSRAd |
| 86081U, // URSRAv16i8_shift |
| 86081U, // URSRAv2i32_shift |
| 86081U, // URSRAv2i64_shift |
| 86081U, // URSRAv4i16_shift |
| 86081U, // URSRAv4i32_shift |
| 86081U, // URSRAv8i16_shift |
| 86081U, // URSRAv8i8_shift |
| 157025U, // USDOT_VG2_M2Z2Z_BToS |
| 2983265U, // USDOT_VG2_M2ZZI_BToS |
| 99681U, // USDOT_VG2_M2ZZ_BToS |
| 157025U, // USDOT_VG4_M4Z4Z_BToS |
| 2983265U, // USDOT_VG4_M4ZZI_BToS |
| 99681U, // USDOT_VG4_M4ZZ_BToS |
| 19U, // USDOT_ZZZ |
| 81939U, // USDOT_ZZZI |
| 103303233U, // USDOTlanev16i8 |
| 103303233U, // USDOTlanev8i8 |
| 0U, // USDOTv16i8 |
| 0U, // USDOTv8i8 |
| 6210U, // USHLLB_ZZI_D |
| 225U, // USHLLB_ZZI_H |
| 6208U, // USHLLB_ZZI_S |
| 6210U, // USHLLT_ZZI_D |
| 225U, // USHLLT_ZZI_H |
| 6208U, // USHLLT_ZZI_S |
| 6208U, // USHLLv16i8_shift |
| 6208U, // USHLLv2i32_shift |
| 6208U, // USHLLv4i16_shift |
| 6208U, // USHLLv4i32_shift |
| 6208U, // USHLLv8i16_shift |
| 6208U, // USHLLv8i8_shift |
| 16448U, // USHLv16i8 |
| 6208U, // USHLv1i64 |
| 16448U, // USHLv2i32 |
| 16448U, // USHLv2i64 |
| 16448U, // USHLv4i16 |
| 16448U, // USHLv4i32 |
| 16448U, // USHLv8i16 |
| 16448U, // USHLv8i8 |
| 6208U, // USHRd |
| 6208U, // USHRv16i8_shift |
| 6208U, // USHRv2i32_shift |
| 6208U, // USHRv2i64_shift |
| 6208U, // USHRv4i16_shift |
| 6208U, // USHRv4i32_shift |
| 6208U, // USHRv8i16_shift |
| 6208U, // USHRv8i8_shift |
| 81330U, // USMLALL_MZZI_BtoS |
| 1458U, // USMLALL_MZZ_BtoS |
| 157025U, // USMLALL_VG2_M2Z2Z_BtoS |
| 2983265U, // USMLALL_VG2_M2ZZI_BtoS |
| 99688U, // USMLALL_VG2_M2ZZ_BtoS |
| 157025U, // USMLALL_VG4_M4Z4Z_BtoS |
| 2983265U, // USMLALL_VG4_M4ZZI_BtoS |
| 99688U, // USMLALL_VG4_M4ZZ_BtoS |
| 0U, // USMMLA |
| 19U, // USMMLA_ZZZ |
| 0U, // USMOPA_MPPZZ_D |
| 0U, // USMOPA_MPPZZ_S |
| 0U, // USMOPS_MPPZZ_D |
| 0U, // USMOPS_MPPZZ_S |
| 33837153U, // USQADD_ZPmZ_B |
| 67383393U, // USQADD_ZPmZ_D |
| 101210225U, // USQADD_ZPmZ_H |
| 134504545U, // USQADD_ZPmZ_S |
| 1U, // USQADDv16i8 |
| 2U, // USQADDv1i16 |
| 2U, // USQADDv1i32 |
| 2U, // USQADDv1i64 |
| 2U, // USQADDv1i8 |
| 1U, // USQADDv2i32 |
| 1U, // USQADDv2i64 |
| 1U, // USQADDv4i16 |
| 1U, // USQADDv4i32 |
| 1U, // USQADDv8i16 |
| 1U, // USQADDv8i8 |
| 451U, // USRA_ZZI_B |
| 86080U, // USRA_ZZI_D |
| 449U, // USRA_ZZI_H |
| 86080U, // USRA_ZZI_S |
| 86082U, // USRAd |
| 86081U, // USRAv16i8_shift |
| 86081U, // USRAv2i32_shift |
| 86081U, // USRAv2i64_shift |
| 86081U, // USRAv4i16_shift |
| 86081U, // USRAv4i32_shift |
| 86081U, // USRAv8i16_shift |
| 86081U, // USRAv8i8_shift |
| 24642U, // USUBLB_ZZZ_D |
| 129U, // USUBLB_ZZZ_H |
| 10304U, // USUBLB_ZZZ_S |
| 24642U, // USUBLT_ZZZ_D |
| 129U, // USUBLT_ZZZ_H |
| 10304U, // USUBLT_ZZZ_S |
| 16448U, // USUBLv16i8_v8i16 |
| 16448U, // USUBLv2i32_v2i64 |
| 16448U, // USUBLv4i16_v4i32 |
| 16448U, // USUBLv4i32_v2i64 |
| 16448U, // USUBLv8i16_v4i32 |
| 16448U, // USUBLv8i8_v8i16 |
| 24641U, // USUBWB_ZZZ_D |
| 129U, // USUBWB_ZZZ_H |
| 10306U, // USUBWB_ZZZ_S |
| 24641U, // USUBWT_ZZZ_D |
| 129U, // USUBWT_ZZZ_H |
| 10306U, // USUBWT_ZZZ_S |
| 16448U, // USUBWv16i8_v8i16 |
| 16448U, // USUBWv2i32_v2i64 |
| 16448U, // USUBWv4i16_v4i32 |
| 16448U, // USUBWv4i32_v2i64 |
| 16448U, // USUBWv8i16_v4i32 |
| 16448U, // USUBWv8i8_v8i16 |
| 2983265U, // USVDOT_VG4_M4ZZI_BToS |
| 2U, // UUNPKHI_ZZ_D |
| 0U, // UUNPKHI_ZZ_H |
| 0U, // UUNPKHI_ZZ_S |
| 2U, // UUNPKLO_ZZ_D |
| 0U, // UUNPKLO_ZZ_H |
| 0U, // UUNPKLO_ZZ_S |
| 0U, // UUNPK_VG2_2ZZ_D |
| 0U, // UUNPK_VG2_2ZZ_H |
| 0U, // UUNPK_VG2_2ZZ_S |
| 0U, // UUNPK_VG4_4Z2Z_D |
| 0U, // UUNPK_VG4_4Z2Z_H |
| 0U, // UUNPK_VG4_4Z2Z_S |
| 2961665U, // UVDOT_VG2_M2ZZI_HtoS |
| 2983265U, // UVDOT_VG4_M4ZZI_BtoS |
| 2961665U, // UVDOT_VG4_M4ZZI_HtoD |
| 32U, // UXTB_ZPmZ_D |
| 0U, // UXTB_ZPmZ_H |
| 48U, // UXTB_ZPmZ_S |
| 32U, // UXTH_ZPmZ_D |
| 48U, // UXTH_ZPmZ_S |
| 32U, // UXTW_ZPmZ_D |
| 20546U, // UZP1_PPP_B |
| 12353U, // UZP1_PPP_D |
| 113U, // UZP1_PPP_H |
| 24642U, // UZP1_PPP_S |
| 20546U, // UZP1_ZZZ_B |
| 12353U, // UZP1_ZZZ_D |
| 113U, // UZP1_ZZZ_H |
| 1585U, // UZP1_ZZZ_Q |
| 24642U, // UZP1_ZZZ_S |
| 16448U, // UZP1v16i8 |
| 16448U, // UZP1v2i32 |
| 16448U, // UZP1v2i64 |
| 16448U, // UZP1v4i16 |
| 16448U, // UZP1v4i32 |
| 16448U, // UZP1v8i16 |
| 16448U, // UZP1v8i8 |
| 20546U, // UZP2_PPP_B |
| 12353U, // UZP2_PPP_D |
| 113U, // UZP2_PPP_H |
| 24642U, // UZP2_PPP_S |
| 20546U, // UZP2_ZZZ_B |
| 12353U, // UZP2_ZZZ_D |
| 113U, // UZP2_ZZZ_H |
| 1585U, // UZP2_ZZZ_Q |
| 24642U, // UZP2_ZZZ_S |
| 16448U, // UZP2v16i8 |
| 16448U, // UZP2v2i32 |
| 16448U, // UZP2v2i64 |
| 16448U, // UZP2v4i16 |
| 16448U, // UZP2v4i32 |
| 16448U, // UZP2v8i16 |
| 16448U, // UZP2v8i8 |
| 20546U, // UZPQ1_ZZZ_B |
| 12353U, // UZPQ1_ZZZ_D |
| 113U, // UZPQ1_ZZZ_H |
| 24642U, // UZPQ1_ZZZ_S |
| 20546U, // UZPQ2_ZZZ_B |
| 12353U, // UZPQ2_ZZZ_D |
| 113U, // UZPQ2_ZZZ_H |
| 24642U, // UZPQ2_ZZZ_S |
| 129U, // UZP_VG2_2ZZZ_B |
| 0U, // UZP_VG2_2ZZZ_D |
| 113U, // UZP_VG2_2ZZZ_H |
| 1585U, // UZP_VG2_2ZZZ_Q |
| 81U, // UZP_VG2_2ZZZ_S |
| 0U, // UZP_VG4_4Z4Z_B |
| 0U, // UZP_VG4_4Z4Z_D |
| 0U, // UZP_VG4_4Z4Z_H |
| 0U, // UZP_VG4_4Z4Z_Q |
| 0U, // UZP_VG4_4Z4Z_S |
| 0U, // WFET |
| 0U, // WFIT |
| 225U, // WHILEGE_2PXX_B |
| 225U, // WHILEGE_2PXX_D |
| 225U, // WHILEGE_2PXX_H |
| 225U, // WHILEGE_2PXX_S |
| 1376000064U, // WHILEGE_CXX_B |
| 1376000064U, // WHILEGE_CXX_D |
| 1376000064U, // WHILEGE_CXX_H |
| 1376000064U, // WHILEGE_CXX_S |
| 6208U, // WHILEGE_PWW_B |
| 6208U, // WHILEGE_PWW_D |
| 225U, // WHILEGE_PWW_H |
| 6208U, // WHILEGE_PWW_S |
| 6208U, // WHILEGE_PXX_B |
| 6208U, // WHILEGE_PXX_D |
| 225U, // WHILEGE_PXX_H |
| 6208U, // WHILEGE_PXX_S |
| 225U, // WHILEGT_2PXX_B |
| 225U, // WHILEGT_2PXX_D |
| 225U, // WHILEGT_2PXX_H |
| 225U, // WHILEGT_2PXX_S |
| 1376000064U, // WHILEGT_CXX_B |
| 1376000064U, // WHILEGT_CXX_D |
| 1376000064U, // WHILEGT_CXX_H |
| 1376000064U, // WHILEGT_CXX_S |
| 6208U, // WHILEGT_PWW_B |
| 6208U, // WHILEGT_PWW_D |
| 225U, // WHILEGT_PWW_H |
| 6208U, // WHILEGT_PWW_S |
| 6208U, // WHILEGT_PXX_B |
| 6208U, // WHILEGT_PXX_D |
| 225U, // WHILEGT_PXX_H |
| 6208U, // WHILEGT_PXX_S |
| 225U, // WHILEHI_2PXX_B |
| 225U, // WHILEHI_2PXX_D |
| 225U, // WHILEHI_2PXX_H |
| 225U, // WHILEHI_2PXX_S |
| 1376000064U, // WHILEHI_CXX_B |
| 1376000064U, // WHILEHI_CXX_D |
| 1376000064U, // WHILEHI_CXX_H |
| 1376000064U, // WHILEHI_CXX_S |
| 6208U, // WHILEHI_PWW_B |
| 6208U, // WHILEHI_PWW_D |
| 225U, // WHILEHI_PWW_H |
| 6208U, // WHILEHI_PWW_S |
| 6208U, // WHILEHI_PXX_B |
| 6208U, // WHILEHI_PXX_D |
| 225U, // WHILEHI_PXX_H |
| 6208U, // WHILEHI_PXX_S |
| 225U, // WHILEHS_2PXX_B |
| 225U, // WHILEHS_2PXX_D |
| 225U, // WHILEHS_2PXX_H |
| 225U, // WHILEHS_2PXX_S |
| 1376000064U, // WHILEHS_CXX_B |
| 1376000064U, // WHILEHS_CXX_D |
| 1376000064U, // WHILEHS_CXX_H |
| 1376000064U, // WHILEHS_CXX_S |
| 6208U, // WHILEHS_PWW_B |
| 6208U, // WHILEHS_PWW_D |
| 225U, // WHILEHS_PWW_H |
| 6208U, // WHILEHS_PWW_S |
| 6208U, // WHILEHS_PXX_B |
| 6208U, // WHILEHS_PXX_D |
| 225U, // WHILEHS_PXX_H |
| 6208U, // WHILEHS_PXX_S |
| 225U, // WHILELE_2PXX_B |
| 225U, // WHILELE_2PXX_D |
| 225U, // WHILELE_2PXX_H |
| 225U, // WHILELE_2PXX_S |
| 1376000064U, // WHILELE_CXX_B |
| 1376000064U, // WHILELE_CXX_D |
| 1376000064U, // WHILELE_CXX_H |
| 1376000064U, // WHILELE_CXX_S |
| 6208U, // WHILELE_PWW_B |
| 6208U, // WHILELE_PWW_D |
| 225U, // WHILELE_PWW_H |
| 6208U, // WHILELE_PWW_S |
| 6208U, // WHILELE_PXX_B |
| 6208U, // WHILELE_PXX_D |
| 225U, // WHILELE_PXX_H |
| 6208U, // WHILELE_PXX_S |
| 225U, // WHILELO_2PXX_B |
| 225U, // WHILELO_2PXX_D |
| 225U, // WHILELO_2PXX_H |
| 225U, // WHILELO_2PXX_S |
| 1376000064U, // WHILELO_CXX_B |
| 1376000064U, // WHILELO_CXX_D |
| 1376000064U, // WHILELO_CXX_H |
| 1376000064U, // WHILELO_CXX_S |
| 6208U, // WHILELO_PWW_B |
| 6208U, // WHILELO_PWW_D |
| 225U, // WHILELO_PWW_H |
| 6208U, // WHILELO_PWW_S |
| 6208U, // WHILELO_PXX_B |
| 6208U, // WHILELO_PXX_D |
| 225U, // WHILELO_PXX_H |
| 6208U, // WHILELO_PXX_S |
| 225U, // WHILELS_2PXX_B |
| 225U, // WHILELS_2PXX_D |
| 225U, // WHILELS_2PXX_H |
| 225U, // WHILELS_2PXX_S |
| 1376000064U, // WHILELS_CXX_B |
| 1376000064U, // WHILELS_CXX_D |
| 1376000064U, // WHILELS_CXX_H |
| 1376000064U, // WHILELS_CXX_S |
| 6208U, // WHILELS_PWW_B |
| 6208U, // WHILELS_PWW_D |
| 225U, // WHILELS_PWW_H |
| 6208U, // WHILELS_PWW_S |
| 6208U, // WHILELS_PXX_B |
| 6208U, // WHILELS_PXX_D |
| 225U, // WHILELS_PXX_H |
| 6208U, // WHILELS_PXX_S |
| 225U, // WHILELT_2PXX_B |
| 225U, // WHILELT_2PXX_D |
| 225U, // WHILELT_2PXX_H |
| 225U, // WHILELT_2PXX_S |
| 1376000064U, // WHILELT_CXX_B |
| 1376000064U, // WHILELT_CXX_D |
| 1376000064U, // WHILELT_CXX_H |
| 1376000064U, // WHILELT_CXX_S |
| 6208U, // WHILELT_PWW_B |
| 6208U, // WHILELT_PWW_D |
| 225U, // WHILELT_PWW_H |
| 6208U, // WHILELT_PWW_S |
| 6208U, // WHILELT_PXX_B |
| 6208U, // WHILELT_PXX_D |
| 225U, // WHILELT_PXX_H |
| 6208U, // WHILELT_PXX_S |
| 6208U, // WHILERW_PXX_B |
| 6208U, // WHILERW_PXX_D |
| 225U, // WHILERW_PXX_H |
| 6208U, // WHILERW_PXX_S |
| 6208U, // WHILEWR_PXX_B |
| 6208U, // WHILEWR_PXX_D |
| 225U, // WHILEWR_PXX_H |
| 6208U, // WHILEWR_PXX_S |
| 0U, // WRFFR |
| 0U, // XAFLAG |
| 278592U, // XAR |
| 282690U, // XAR_ZZZI_B |
| 274497U, // XAR_ZZZI_D |
| 102783089U, // XAR_ZZZI_H |
| 286786U, // XAR_ZZZI_S |
| 0U, // XPACD |
| 0U, // XPACI |
| 0U, // XPACLRI |
| 1U, // XTNv16i8 |
| 0U, // XTNv2i32 |
| 0U, // XTNv4i16 |
| 1U, // XTNv4i32 |
| 1U, // XTNv8i16 |
| 0U, // XTNv8i8 |
| 0U, // ZERO_M |
| 10U, // ZERO_MXI_2Z |
| 10U, // ZERO_MXI_4Z |
| 7U, // ZERO_MXI_VG2_2Z |
| 7U, // ZERO_MXI_VG2_4Z |
| 7U, // ZERO_MXI_VG2_Z |
| 7U, // ZERO_MXI_VG4_2Z |
| 7U, // ZERO_MXI_VG4_4Z |
| 7U, // ZERO_MXI_VG4_Z |
| 0U, // ZERO_T |
| 20546U, // ZIP1_PPP_B |
| 12353U, // ZIP1_PPP_D |
| 113U, // ZIP1_PPP_H |
| 24642U, // ZIP1_PPP_S |
| 20546U, // ZIP1_ZZZ_B |
| 12353U, // ZIP1_ZZZ_D |
| 113U, // ZIP1_ZZZ_H |
| 1585U, // ZIP1_ZZZ_Q |
| 24642U, // ZIP1_ZZZ_S |
| 16448U, // ZIP1v16i8 |
| 16448U, // ZIP1v2i32 |
| 16448U, // ZIP1v2i64 |
| 16448U, // ZIP1v4i16 |
| 16448U, // ZIP1v4i32 |
| 16448U, // ZIP1v8i16 |
| 16448U, // ZIP1v8i8 |
| 20546U, // ZIP2_PPP_B |
| 12353U, // ZIP2_PPP_D |
| 113U, // ZIP2_PPP_H |
| 24642U, // ZIP2_PPP_S |
| 20546U, // ZIP2_ZZZ_B |
| 12353U, // ZIP2_ZZZ_D |
| 113U, // ZIP2_ZZZ_H |
| 1585U, // ZIP2_ZZZ_Q |
| 24642U, // ZIP2_ZZZ_S |
| 16448U, // ZIP2v16i8 |
| 16448U, // ZIP2v2i32 |
| 16448U, // ZIP2v2i64 |
| 16448U, // ZIP2v4i16 |
| 16448U, // ZIP2v4i32 |
| 16448U, // ZIP2v8i16 |
| 16448U, // ZIP2v8i8 |
| 20546U, // ZIPQ1_ZZZ_B |
| 12353U, // ZIPQ1_ZZZ_D |
| 113U, // ZIPQ1_ZZZ_H |
| 24642U, // ZIPQ1_ZZZ_S |
| 20546U, // ZIPQ2_ZZZ_B |
| 12353U, // ZIPQ2_ZZZ_D |
| 113U, // ZIPQ2_ZZZ_H |
| 24642U, // ZIPQ2_ZZZ_S |
| 129U, // ZIP_VG2_2ZZZ_B |
| 0U, // ZIP_VG2_2ZZZ_D |
| 113U, // ZIP_VG2_2ZZZ_H |
| 1585U, // ZIP_VG2_2ZZZ_Q |
| 81U, // ZIP_VG2_2ZZZ_S |
| 0U, // ZIP_VG4_4Z4Z_B |
| 0U, // ZIP_VG4_4Z4Z_D |
| 0U, // ZIP_VG4_4Z4Z_H |
| 0U, // ZIP_VG4_4Z4Z_Q |
| 0U, // ZIP_VG4_4Z4Z_S |
| 225U, // anonymous_15148 |
| 225U, // anonymous_15149 |
| 225U, // anonymous_5481 |
| }; |
| |
| // Emit the opcode for the instruction. |
| uint64_t Bits = 0; |
| Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0; |
| Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32; |
| return {AsmStrs+(Bits & 32767)-1, Bits}; |
| |
| } |
| /// printInstruction - This method is automatically generated by tablegen |
| /// from the instruction set description. |
| LLVM_NO_PROFILE_INSTRUMENT_FUNCTION |
| void AArch64AppleInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) { |
| O << "\t"; |
| |
| auto MnemonicInfo = getMnemonic(MI); |
| |
| O << MnemonicInfo.first; |
| |
| uint64_t Bits = MnemonicInfo.second; |
| assert(Bits != 0 && "Cannot print this instruction."); |
| |
| // Fragment 0 encoded into 7 bits for 78 unique commands. |
| switch ((Bits >> 15) & 127) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... |
| return; |
| break; |
| case 1: |
| // TLSDESCCALL, ABSWr, ABSXr, ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADD... |
| printOperand(MI, 0, STI, O); |
| break; |
| case 2: |
| // ABS_ZPmZ_B, ADDHNB_ZZZ_B, ADDHNT_ZZZ_B, ADDP_ZPmZ_B, ADD_ZI_B, ADD_ZPm... |
| printSVERegOp<'b'>(MI, 0, STI, O); |
| break; |
| case 3: |
| // ABS_ZPmZ_D, ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDP_ZPmZ_D, ADD_ZI_D, ADD_ZPmZ_... |
| printSVERegOp<'d'>(MI, 0, STI, O); |
| break; |
| case 4: |
| // ABS_ZPmZ_H, ADDHNB_ZZZ_H, ADDHNT_ZZZ_H, ADDP_ZPmZ_H, ADD_ZI_H, ADD_ZPm... |
| printSVERegOp<'h'>(MI, 0, STI, O); |
| O << ", "; |
| break; |
| case 5: |
| // ABS_ZPmZ_S, ADCLB_ZZZ_S, ADCLT_ZZZ_S, ADDHNB_ZZZ_S, ADDHNT_ZZZ_S, ADDP... |
| printSVERegOp<'s'>(MI, 0, STI, O); |
| break; |
| case 6: |
| // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... |
| printVRegOperand(MI, 0, STI, O); |
| break; |
| case 7: |
| // ADDHA_MPPZ_D, ADDHA_MPPZ_S, ADDVA_MPPZ_D, ADDVA_MPPZ_S, BFMOPA_MPPZZ, ... |
| printMatrixTile(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 2, STI, O); |
| O << "/m, "; |
| printSVERegOp<>(MI, 3, STI, O); |
| O << "/m, "; |
| break; |
| case 8: |
| // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... |
| printVRegOperand(MI, 1, STI, O); |
| break; |
| case 9: |
| // ADD_VG2_2ZZ_B, ADD_VG4_4ZZ_B, LD1B, LD1B_2Z, LD1B_2Z_IMM, LD1B_4Z, LD1... |
| printTypedVectorList<0,'b'>(MI, 0, STI, O); |
| O << ", "; |
| break; |
| case 10: |
| // ADD_VG2_2ZZ_D, ADD_VG4_4ZZ_D, FCLAMP_VG2_2Z2Z_D, FCLAMP_VG4_4Z4Z_D, FM... |
| printTypedVectorList<0,'d'>(MI, 0, STI, O); |
| O << ", "; |
| break; |
| case 11: |
| // ADD_VG2_2ZZ_H, ADD_VG4_4ZZ_H, BFCLAMP_VG2_2ZZZ_H, BFCLAMP_VG4_4ZZZ_H, ... |
| printTypedVectorList<0,'h'>(MI, 0, STI, O); |
| O << ", "; |
| break; |
| case 12: |
| // ADD_VG2_2ZZ_S, ADD_VG4_4ZZ_S, FCLAMP_VG2_2Z2Z_S, FCLAMP_VG4_4Z4Z_S, FC... |
| printTypedVectorList<0,'s'>(MI, 0, STI, O); |
| O << ", "; |
| break; |
| case 13: |
| // ADD_VG2_M2Z2Z_D, ADD_VG2_M2ZZ_D, ADD_VG2_M2Z_D, ADD_VG4_M4Z4Z_D, ADD_V... |
| printMatrix<64>(MI, 0, STI, O); |
| O << '['; |
| printOperand(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 14: |
| // ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_S, ADD_VG2_M2Z_S, ADD_VG4_M4Z4Z_S, ADD_V... |
| printMatrix<32>(MI, 0, STI, O); |
| O << '['; |
| printOperand(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 15: |
| // ANDV_VPZ_B, EORV_VPZ_B, ORV_VPZ_B, SMAXV_VPZ_B, SMINV_VPZ_B, UMAXV_VPZ... |
| printZPRasFPR<8>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 1, STI, O); |
| O << ", "; |
| printSVERegOp<'b'>(MI, 2, STI, O); |
| return; |
| break; |
| case 16: |
| // ANDV_VPZ_D, EORV_VPZ_D, FADDA_VPZ_D, FADDV_VPZ_D, FMAXNMV_VPZ_D, FMAXV... |
| printZPRasFPR<64>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 1, STI, O); |
| O << ", "; |
| break; |
| case 17: |
| // ANDV_VPZ_H, EORV_VPZ_H, FADDA_VPZ_H, FADDV_VPZ_H, FMAXNMV_VPZ_H, FMAXV... |
| printZPRasFPR<16>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 1, STI, O); |
| O << ", "; |
| break; |
| case 18: |
| // ANDV_VPZ_S, EORV_VPZ_S, FADDA_VPZ_S, FADDV_VPZ_S, FMAXNMV_VPZ_S, FMAXV... |
| printZPRasFPR<32>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 1, STI, O); |
| O << ", "; |
| break; |
| case 19: |
| // AUTDA, AUTDB, AUTDZA, AUTDZB, AUTIA, AUTIB, AUTIZA, AUTIZB, CASAB, CAS... |
| printOperand(MI, 1, STI, O); |
| break; |
| case 20: |
| // B, BL |
| printAlignedLabel(MI, Address, 0, STI, O); |
| return; |
| break; |
| case 21: |
| // BCcc, Bcc |
| printCondCode(MI, 0, STI, O); |
| O << "\t"; |
| printAlignedLabel(MI, Address, 1, STI, O); |
| return; |
| break; |
| case 22: |
| // BFADD_VG2_M2Z_H, BFADD_VG4_M4Z_H, BFMLA_VG2_M2Z2Z, BFMLA_VG2_M2ZZ, BFM... |
| printMatrix<16>(MI, 0, STI, O); |
| O << '['; |
| printOperand(MI, 2, STI, O); |
| O << ", "; |
| printMatrixIndex(MI, 3, STI, O); |
| break; |
| case 23: |
| // BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, SVC, TCANCEL |
| printImmHex(MI, 0, STI, O); |
| return; |
| break; |
| case 24: |
| // CASPALW, CASPAW, CASPLW, CASPW |
| printGPRSeqPairsClassOperand<32>(MI, 1, STI, O); |
| O << ", "; |
| printGPRSeqPairsClassOperand<32>(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 25: |
| // CASPALX, CASPAX, CASPLX, CASPX, RCWCASP, RCWCASPA, RCWCASPAL, RCWCASPL... |
| printGPRSeqPairsClassOperand<64>(MI, 1, STI, O); |
| O << ", "; |
| printGPRSeqPairsClassOperand<64>(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 26: |
| // CPYE, CPYEN, CPYERN, CPYERT, CPYERTN, CPYERTRN, CPYERTWN, CPYET, CPYET... |
| printOperand(MI, 3, STI, O); |
| O << "]!, ["; |
| printOperand(MI, 4, STI, O); |
| O << "]!, "; |
| printOperand(MI, 5, STI, O); |
| O << '!'; |
| return; |
| break; |
| case 27: |
| // DMB, DSB, ISB, TSB |
| printBarrierOption(MI, 0, STI, O); |
| return; |
| break; |
| case 28: |
| // DSBnXS |
| printBarriernXSOption(MI, 0, STI, O); |
| return; |
| break; |
| case 29: |
| // DUP_ZZI_Q, EXTRACT_ZPMXI_H_Q, EXTRACT_ZPMXI_V_Q, MOVAZ_ZMI_H_Q, MOVAZ_... |
| printSVERegOp<'q'>(MI, 0, STI, O); |
| O << ", "; |
| break; |
| case 30: |
| // GLD1Q, LD1D_Q, LD1D_Q_IMM, LD1W_Q, LD1W_Q_IMM, LD2Q, LD2Q_IMM, LD3Q, L... |
| printTypedVectorList<0,'q'>(MI, 0, STI, O); |
| O << ", "; |
| break; |
| case 31: |
| // HINT |
| printImm(MI, 0, STI, O); |
| return; |
| break; |
| case 32: |
| // INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q... |
| printMatrixTileVector<0>(MI, 0, STI, O); |
| O << '['; |
| break; |
| case 33: |
| // INSERT_MXIPZ_V_B, INSERT_MXIPZ_V_D, INSERT_MXIPZ_V_H, INSERT_MXIPZ_V_Q... |
| printMatrixTileVector<1>(MI, 0, STI, O); |
| O << '['; |
| break; |
| case 34: |
| // LD1B_VG2_M2ZPXI, LD1B_VG2_M2ZPXX, LDNT1B_VG2_M2ZPXI, LDNT1B_VG2_M2ZPXX... |
| printTypedVectorList<0, 'b'>(MI, 0, STI, O); |
| break; |
| case 35: |
| // LD1Fourv16b, LD1Onev16b, LD1Rv16b, LD1Threev16b, LD1Twov16b, LD2Rv16b,... |
| printTypedVectorList<16, 'b'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 36: |
| // LD1Fourv16b_POST, LD1Onev16b_POST, LD1Rv16b_POST, LD1Threev16b_POST, L... |
| printTypedVectorList<16, 'b'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 37: |
| // LD1Fourv1d, LD1Onev1d, LD1Rv1d, LD1Threev1d, LD1Twov1d, LD2Rv1d, LD3Rv... |
| printTypedVectorList<1, 'd'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 38: |
| // LD1Fourv1d_POST, LD1Onev1d_POST, LD1Rv1d_POST, LD1Threev1d_POST, LD1Tw... |
| printTypedVectorList<1, 'd'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 39: |
| // LD1Fourv2d, LD1Onev2d, LD1Rv2d, LD1Threev2d, LD1Twov2d, LD2Rv2d, LD2Tw... |
| printTypedVectorList<2, 'd'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 40: |
| // LD1Fourv2d_POST, LD1Onev2d_POST, LD1Rv2d_POST, LD1Threev2d_POST, LD1Tw... |
| printTypedVectorList<2, 'd'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 41: |
| // LD1Fourv2s, LD1Onev2s, LD1Rv2s, LD1Threev2s, LD1Twov2s, LD2Rv2s, LD2Tw... |
| printTypedVectorList<2, 's'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 42: |
| // LD1Fourv2s_POST, LD1Onev2s_POST, LD1Rv2s_POST, LD1Threev2s_POST, LD1Tw... |
| printTypedVectorList<2, 's'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 43: |
| // LD1Fourv4h, LD1Onev4h, LD1Rv4h, LD1Threev4h, LD1Twov4h, LD2Rv4h, LD2Tw... |
| printTypedVectorList<4, 'h'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 44: |
| // LD1Fourv4h_POST, LD1Onev4h_POST, LD1Rv4h_POST, LD1Threev4h_POST, LD1Tw... |
| printTypedVectorList<4, 'h'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 45: |
| // LD1Fourv4s, LD1Onev4s, LD1Rv4s, LD1Threev4s, LD1Twov4s, LD2Rv4s, LD2Tw... |
| printTypedVectorList<4, 's'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 46: |
| // LD1Fourv4s_POST, LD1Onev4s_POST, LD1Rv4s_POST, LD1Threev4s_POST, LD1Tw... |
| printTypedVectorList<4, 's'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 47: |
| // LD1Fourv8b, LD1Onev8b, LD1Rv8b, LD1Threev8b, LD1Twov8b, LD2Rv8b, LD2Tw... |
| printTypedVectorList<8, 'b'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 48: |
| // LD1Fourv8b_POST, LD1Onev8b_POST, LD1Rv8b_POST, LD1Threev8b_POST, LD1Tw... |
| printTypedVectorList<8, 'b'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 49: |
| // LD1Fourv8h, LD1Onev8h, LD1Rv8h, LD1Threev8h, LD1Twov8h, LD2Rv8h, LD2Tw... |
| printTypedVectorList<8, 'h'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 50: |
| // LD1Fourv8h_POST, LD1Onev8h_POST, LD1Rv8h_POST, LD1Threev8h_POST, LD1Tw... |
| printTypedVectorList<8, 'h'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 51: |
| // LD1H_VG2_M2ZPXI, LD1H_VG2_M2ZPXX, LDNT1H_VG2_M2ZPXI, LDNT1H_VG2_M2ZPXX... |
| printTypedVectorList<0, 'h'>(MI, 0, STI, O); |
| break; |
| case 52: |
| // LD1i16, LD2i16, LD3i16, LD4i16, ST1i16_POST, ST2i16_POST, ST3i16_POST,... |
| printTypedVectorList<0, 'h'>(MI, 1, STI, O); |
| printVectorIndex(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| break; |
| case 53: |
| // LD1i16_POST, LD2i16_POST, LD3i16_POST, LD4i16_POST |
| printTypedVectorList<0, 'h'>(MI, 2, STI, O); |
| printVectorIndex(MI, 3, STI, O); |
| O << ", ["; |
| printOperand(MI, 4, STI, O); |
| O << "], "; |
| break; |
| case 54: |
| // LD1i32, LD2i32, LD3i32, LD4i32, ST1i32_POST, ST2i32_POST, ST3i32_POST,... |
| printTypedVectorList<0, 's'>(MI, 1, STI, O); |
| printVectorIndex(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| break; |
| case 55: |
| // LD1i32_POST, LD2i32_POST, LD3i32_POST, LD4i32_POST |
| printTypedVectorList<0, 's'>(MI, 2, STI, O); |
| printVectorIndex(MI, 3, STI, O); |
| O << ", ["; |
| printOperand(MI, 4, STI, O); |
| O << "], "; |
| break; |
| case 56: |
| // LD1i64, LD2i64, LD3i64, LD4i64, LDAP1, ST1i64_POST, ST2i64_POST, ST3i6... |
| printTypedVectorList<0, 'd'>(MI, 1, STI, O); |
| printVectorIndex(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| break; |
| case 57: |
| // LD1i64_POST, LD2i64_POST, LD3i64_POST, LD4i64_POST |
| printTypedVectorList<0, 'd'>(MI, 2, STI, O); |
| printVectorIndex(MI, 3, STI, O); |
| O << ", ["; |
| printOperand(MI, 4, STI, O); |
| O << "], "; |
| break; |
| case 58: |
| // LD1i8, LD2i8, LD3i8, LD4i8, ST1i8_POST, ST2i8_POST, ST3i8_POST, ST4i8_... |
| printTypedVectorList<0, 'b'>(MI, 1, STI, O); |
| printVectorIndex(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| break; |
| case 59: |
| // LD1i8_POST, LD2i8_POST, LD3i8_POST, LD4i8_POST |
| printTypedVectorList<0, 'b'>(MI, 2, STI, O); |
| printVectorIndex(MI, 3, STI, O); |
| O << ", ["; |
| printOperand(MI, 4, STI, O); |
| O << "], "; |
| break; |
| case 60: |
| // LD64B, ST64B |
| printGPR64x8(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 61: |
| // LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL, LDSETP, LDSETPA, LDSETPAL, LDSETPL... |
| printOperand(MI, 2, STI, O); |
| break; |
| case 62: |
| // LDR_PXI, LDR_ZXI, MOVPRFX_ZZ, PMOV_ZIP_B, PMOV_ZIP_D, PMOV_ZIP_H, PMOV... |
| printSVERegOp<>(MI, 0, STI, O); |
| break; |
| case 63: |
| // LDR_ZA, STR_ZA |
| printMatrix<0>(MI, 0, STI, O); |
| O << '['; |
| printOperand(MI, 1, STI, O); |
| O << ", "; |
| printMatrixIndex(MI, 2, STI, O); |
| O << "], ["; |
| printOperand(MI, 3, STI, O); |
| O << ", "; |
| printOperand(MI, 4, STI, O); |
| O << ", mul vl]"; |
| return; |
| break; |
| case 64: |
| // MRRS |
| printGPRSeqPairsClassOperand<64>(MI, 0, STI, O); |
| O << ", "; |
| printMRSSystemRegister(MI, 1, STI, O); |
| return; |
| break; |
| case 65: |
| // MSR, MSRR |
| printMSRSystemRegister(MI, 0, STI, O); |
| O << ", "; |
| break; |
| case 66: |
| // MSRpstateImm1, MSRpstateImm4 |
| printSystemPStateField(MI, 0, STI, O); |
| O << ", "; |
| printOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 67: |
| // MSRpstatesvcrImm1 |
| printSVCROp(MI, 0, STI, O); |
| O << ", "; |
| printOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 68: |
| // PRFB_D_PZI, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_SCALED, PRF... |
| printPrefetchOp<true>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 1, STI, O); |
| O << ", ["; |
| break; |
| case 69: |
| // PRFMl, PRFMroW, PRFMroX, PRFMui, PRFUMi |
| printPrefetchOp(MI, 0, STI, O); |
| break; |
| case 70: |
| // PTRUE_C_B, WHILEGE_CXX_B, WHILEGT_CXX_B, WHILEHI_CXX_B, WHILEHS_CXX_B,... |
| printPredicateAsCounter<8>(MI, 0, STI, O); |
| break; |
| case 71: |
| // PTRUE_C_D, WHILEGE_CXX_D, WHILEGT_CXX_D, WHILEHI_CXX_D, WHILEHS_CXX_D,... |
| printPredicateAsCounter<64>(MI, 0, STI, O); |
| break; |
| case 72: |
| // PTRUE_C_H, WHILEGE_CXX_H, WHILEGT_CXX_H, WHILEHI_CXX_H, WHILEHS_CXX_H,... |
| printPredicateAsCounter<16>(MI, 0, STI, O); |
| break; |
| case 73: |
| // PTRUE_C_S, WHILEGE_CXX_S, WHILEGT_CXX_S, WHILEHI_CXX_S, WHILEHS_CXX_S,... |
| printPredicateAsCounter<32>(MI, 0, STI, O); |
| break; |
| case 74: |
| // RPRFM |
| printRPRFMOperand(MI, 0, STI, O); |
| O << ", "; |
| printOperand(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 75: |
| // ST1i32, ST2i32, ST3i32, ST4i32 |
| printTypedVectorList<0, 's'>(MI, 0, STI, O); |
| printVectorIndex(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 76: |
| // ST1i64, ST2i64, ST3i64, ST4i64, STL1 |
| printTypedVectorList<0, 'd'>(MI, 0, STI, O); |
| printVectorIndex(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 77: |
| // ZERO_M |
| printMatrixTileList(MI, 0, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 1 encoded into 7 bits for 83 unique commands. |
| switch ((Bits >> 22) & 127) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // TLSDESCCALL, AUTDZA, AUTDZB, AUTIZA, AUTIZB, BLR, BLRAAZ, BLRABZ, BR, ... |
| return; |
| break; |
| case 1: |
| // ABSWr, ABSXr, ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ABSv16i8, ABSv1i64, ... |
| O << ", "; |
| break; |
| case 2: |
| // ABS_ZPmZ_H, BFCVTNT_ZPmZ, BFCVT_ZPmZ, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPm... |
| printSVERegOp<>(MI, 2, STI, O); |
| O << "/m, "; |
| break; |
| case 3: |
| // ADDHA_MPPZ_D, ADDVA_MPPZ_D, FMOPA_MPPZZ_D, FMOPS_MPPZZ_D |
| printSVERegOp<'d'>(MI, 4, STI, O); |
| break; |
| case 4: |
| // ADDHA_MPPZ_S, ADDVA_MPPZ_S, BMOPA_MPPZZ_S, BMOPS_MPPZZ_S, FMOPA_MPPZZ_... |
| printSVERegOp<'s'>(MI, 4, STI, O); |
| break; |
| case 5: |
| // ADDHNB_ZZZ_H, RADDHNB_ZZZ_H, RSHRNB_ZZI_H, RSUBHNB_ZZZ_H, SHRNB_ZZI_H,... |
| printSVERegOp<'s'>(MI, 1, STI, O); |
| break; |
| case 6: |
| // ADDHNT_ZZZ_H, ANDV_VPZ_S, EORV_VPZ_S, FADDV_VPZ_S, FCLAMP_VG2_2Z2Z_S, ... |
| printSVERegOp<'s'>(MI, 2, STI, O); |
| break; |
| case 7: |
| // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID... |
| printSVERegOp<>(MI, 1, STI, O); |
| break; |
| case 8: |
| // ADDQV_VPZ_B, ANDQV_VPZ_B, EORQV_VPZ_B, ORQV_VPZ_B, SMAXQV_VPZ_B, SMINQ... |
| O << ".16b, "; |
| break; |
| case 9: |
| // ADDQV_VPZ_D, ANDQV_VPZ_D, EORQV_VPZ_D, FADDQV_D, FCVTLv2i32, FCVTLv4i3... |
| O << ".2d, "; |
| break; |
| case 10: |
| // ADDQV_VPZ_H, ANDQV_VPZ_H, EORQV_VPZ_H, FADDQV_H, FCVTNv8i16, FMAXNMQV_... |
| O << ".8h, "; |
| break; |
| case 11: |
| // ADDQV_VPZ_S, ANDQV_VPZ_S, EORQV_VPZ_S, FADDQV_S, FCVTLv4i16, FCVTLv8i1... |
| O << ".4s, "; |
| break; |
| case 12: |
| // ADD_VG2_2ZZ_B, ADD_VG4_4ZZ_B, SMAX_VG2_2Z2Z_B, SMAX_VG2_2ZZ_B, SMAX_VG... |
| printTypedVectorList<0,'b'>(MI, 1, STI, O); |
| break; |
| case 13: |
| // ADD_VG2_2ZZ_D, ADD_VG4_4ZZ_D, FMAXNM_VG2_2Z2Z_D, FMAXNM_VG2_2ZZ_D, FMA... |
| printTypedVectorList<0,'d'>(MI, 1, STI, O); |
| break; |
| case 14: |
| // ADD_VG2_2ZZ_H, ADD_VG4_4ZZ_H, BFMAXNM_VG2_2Z2Z_H, BFMAXNM_VG2_2ZZ_H, B... |
| printTypedVectorList<0,'h'>(MI, 1, STI, O); |
| break; |
| case 15: |
| // ADD_VG2_2ZZ_S, ADD_VG4_4ZZ_S, BFCVTN_Z2Z_StoH, BFCVT_Z2Z_StoH, FCVTN_Z... |
| printTypedVectorList<0,'s'>(MI, 1, STI, O); |
| break; |
| case 16: |
| // ADD_VG2_M2Z2Z_D, ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_D, ADD_VG2_M2ZZ_S, ADD_... |
| printMatrixIndex(MI, 3, STI, O); |
| break; |
| case 17: |
| // ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_ZZI_H, BDEP_ZZZ_H, BEXT_ZZZ_H... |
| printSVERegOp<'h'>(MI, 1, STI, O); |
| break; |
| case 18: |
| // ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, ADR_LSL_ZZZ_D_2, ADR_LSL_ZZZ_D_3, AD... |
| O << ", ["; |
| break; |
| case 19: |
| // ANDV_VPZ_D, EORV_VPZ_D, FADDV_VPZ_D, FCLAMP_VG2_2Z2Z_D, FCLAMP_VG4_4Z4... |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| break; |
| case 20: |
| // ANDV_VPZ_H, BFCLAMP_VG2_2ZZZ_H, BFCLAMP_VG4_4ZZZ_H, BFCLAMP_ZZZ, BFMLA... |
| printSVERegOp<'h'>(MI, 2, STI, O); |
| break; |
| case 21: |
| // BFADD_VG2_M2Z_H, BFMLA_VG2_M2Z2Z, BFMLA_VG2_M2ZZ, BFMLA_VG2_M2ZZI, BFM... |
| O << ", vgx2], "; |
| printTypedVectorList<0,'h'>(MI, 4, STI, O); |
| break; |
| case 22: |
| // BFADD_VG4_M4Z_H, BFMLA_VG4_M4Z4Z, BFMLA_VG4_M4ZZ, BFMLA_VG4_M4ZZI, BFM... |
| O << ", vgx4], "; |
| printTypedVectorList<0,'h'>(MI, 4, STI, O); |
| break; |
| case 23: |
| // BFMLAL_MZZI_S, BFMLAL_MZZ_S, BFMLAL_VG2_M2Z2Z_S, BFMLAL_VG2_M2ZZI_S, B... |
| printImmRangeScale<2, 1>(MI, 3, STI, O); |
| break; |
| case 24: |
| // BFMOPA_MPPZZ, BFMOPA_MPPZZ_H, BFMOPS_MPPZZ, BFMOPS_MPPZZ_H, FMOPAL_MPP... |
| printSVERegOp<'h'>(MI, 4, STI, O); |
| O << ", "; |
| printSVERegOp<'h'>(MI, 5, STI, O); |
| return; |
| break; |
| case 25: |
| // DECH_ZPiI, INCH_ZPiI, SQDECH_ZPiI, SQINCH_ZPiI, UQDECH_ZPiI, UQINCH_ZP... |
| printSVEPattern(MI, 2, STI, O); |
| O << ", mul "; |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 26: |
| // DUP_ZI_H |
| printImm8OptLsl<int16_t>(MI, 1, STI, O); |
| return; |
| break; |
| case 27: |
| // DUP_ZR_H, INDEX_RI_H, INDEX_RR_H, LD1_MXIPXX_H_B, LD1_MXIPXX_H_D, LD1_... |
| printOperand(MI, 1, STI, O); |
| break; |
| case 28: |
| // DUP_ZZI_Q, TRN1_ZZZ_Q, TRN2_ZZZ_Q, UZP1_ZZZ_Q, UZP2_ZZZ_Q, UZP_VG2_2ZZ... |
| printSVERegOp<'q'>(MI, 1, STI, O); |
| break; |
| case 29: |
| // FADDA_VPZ_D |
| printZPRasFPR<64>(MI, 2, STI, O); |
| O << ", "; |
| printSVERegOp<'d'>(MI, 3, STI, O); |
| return; |
| break; |
| case 30: |
| // FADDA_VPZ_H, INSR_ZV_H |
| printZPRasFPR<16>(MI, 2, STI, O); |
| break; |
| case 31: |
| // FADDA_VPZ_S |
| printZPRasFPR<32>(MI, 2, STI, O); |
| O << ", "; |
| printSVERegOp<'s'>(MI, 3, STI, O); |
| return; |
| break; |
| case 32: |
| // FCMPDri, FCMPEDri, FCMPEHri, FCMPESri, FCMPHri, FCMPSri |
| O << ", #0.0"; |
| return; |
| break; |
| case 33: |
| // FCVTNv2i32, FCVTXNv2f32 |
| O << ".2s, "; |
| printVRegOperand(MI, 1, STI, O); |
| O << ".2d"; |
| return; |
| break; |
| case 34: |
| // FCVTNv4i16 |
| O << ".4h, "; |
| printVRegOperand(MI, 1, STI, O); |
| O << ".4s"; |
| return; |
| break; |
| case 35: |
| // FDUP_ZI_H |
| printFPImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 36: |
| // FMOVXDHighr, INSvi16gpr, INSvi16lane, INSvi32gpr, INSvi32lane, INSvi64... |
| printVectorIndex(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 37: |
| // INDEX_II_H, INDEX_IR_H |
| printSImm<16>(MI, 1, STI, O); |
| O << ", "; |
| break; |
| case 38: |
| // INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q... |
| printOperand(MI, 2, STI, O); |
| break; |
| case 39: |
| // LD1B_2Z, LD1B_2Z_IMM, LD1B_4Z, LD1B_4Z_IMM, LD1B_VG4_M4ZPXI, LD1B_VG4_... |
| printPredicateAsCounter<0>(MI, 1, STI, O); |
| break; |
| case 40: |
| // LD1Fourv16b_POST, LD1Fourv2d_POST, LD1Fourv4s_POST, LD1Fourv8h_POST, L... |
| printPostIncOperand<64>(MI, 3, STI, O); |
| return; |
| break; |
| case 41: |
| // LD1Fourv1d_POST, LD1Fourv2s_POST, LD1Fourv4h_POST, LD1Fourv8b_POST, LD... |
| printPostIncOperand<32>(MI, 3, STI, O); |
| return; |
| break; |
| case 42: |
| // LD1Onev16b_POST, LD1Onev2d_POST, LD1Onev4s_POST, LD1Onev8h_POST, LD1Tw... |
| printPostIncOperand<16>(MI, 3, STI, O); |
| return; |
| break; |
| case 43: |
| // LD1Onev1d_POST, LD1Onev2s_POST, LD1Onev4h_POST, LD1Onev8b_POST, LD1Rv1... |
| printPostIncOperand<8>(MI, 3, STI, O); |
| return; |
| break; |
| case 44: |
| // LD1Rv16b_POST, LD1Rv8b_POST |
| printPostIncOperand<1>(MI, 3, STI, O); |
| return; |
| break; |
| case 45: |
| // LD1Rv2s_POST, LD1Rv4s_POST, LD2Rv4h_POST, LD2Rv8h_POST, LD4Rv16b_POST,... |
| printPostIncOperand<4>(MI, 3, STI, O); |
| return; |
| break; |
| case 46: |
| // LD1Rv4h_POST, LD1Rv8h_POST, LD2Rv16b_POST, LD2Rv8b_POST |
| printPostIncOperand<2>(MI, 3, STI, O); |
| return; |
| break; |
| case 47: |
| // LD1Threev16b_POST, LD1Threev2d_POST, LD1Threev4s_POST, LD1Threev8h_POS... |
| printPostIncOperand<48>(MI, 3, STI, O); |
| return; |
| break; |
| case 48: |
| // LD1Threev1d_POST, LD1Threev2s_POST, LD1Threev4h_POST, LD1Threev8b_POST... |
| printPostIncOperand<24>(MI, 3, STI, O); |
| return; |
| break; |
| case 49: |
| // LD1i16, LD1i32, LD1i64, LD1i8, LD2i16, LD2i32, LD2i64, LD2i8, LD3i16, ... |
| O << ']'; |
| return; |
| break; |
| case 50: |
| // LD1i16_POST, LD2i8_POST |
| printPostIncOperand<2>(MI, 5, STI, O); |
| return; |
| break; |
| case 51: |
| // LD1i32_POST, LD2i16_POST, LD4i8_POST |
| printPostIncOperand<4>(MI, 5, STI, O); |
| return; |
| break; |
| case 52: |
| // LD1i64_POST, LD2i32_POST, LD4i16_POST |
| printPostIncOperand<8>(MI, 5, STI, O); |
| return; |
| break; |
| case 53: |
| // LD1i8_POST |
| printPostIncOperand<1>(MI, 5, STI, O); |
| return; |
| break; |
| case 54: |
| // LD2i64_POST, LD4i32_POST |
| printPostIncOperand<16>(MI, 5, STI, O); |
| return; |
| break; |
| case 55: |
| // LD3Rv16b_POST, LD3Rv8b_POST |
| printPostIncOperand<3>(MI, 3, STI, O); |
| return; |
| break; |
| case 56: |
| // LD3Rv2s_POST, LD3Rv4s_POST |
| printPostIncOperand<12>(MI, 3, STI, O); |
| return; |
| break; |
| case 57: |
| // LD3Rv4h_POST, LD3Rv8h_POST |
| printPostIncOperand<6>(MI, 3, STI, O); |
| return; |
| break; |
| case 58: |
| // LD3i16_POST |
| printPostIncOperand<6>(MI, 5, STI, O); |
| return; |
| break; |
| case 59: |
| // LD3i32_POST |
| printPostIncOperand<12>(MI, 5, STI, O); |
| return; |
| break; |
| case 60: |
| // LD3i64_POST |
| printPostIncOperand<24>(MI, 5, STI, O); |
| return; |
| break; |
| case 61: |
| // LD3i8_POST |
| printPostIncOperand<3>(MI, 5, STI, O); |
| return; |
| break; |
| case 62: |
| // LD4i64_POST |
| printPostIncOperand<32>(MI, 5, STI, O); |
| return; |
| break; |
| case 63: |
| // MOPSSETGE, MOPSSETGEN, MOPSSETGET, MOPSSETGETN, SETE, SETEN, SETET, SE... |
| O << "]!, "; |
| printOperand(MI, 3, STI, O); |
| O << "!, "; |
| printOperand(MI, 4, STI, O); |
| return; |
| break; |
| case 64: |
| // MOVAZ_2ZMI_H_B, MOVAZ_2ZMI_H_D, MOVAZ_2ZMI_H_H, MOVAZ_2ZMI_H_S, MOVAZ_... |
| printMatrixTileVector<0>(MI, 2, STI, O); |
| O << '['; |
| printOperand(MI, 3, STI, O); |
| O << ", "; |
| break; |
| case 65: |
| // MOVAZ_2ZMI_V_B, MOVAZ_2ZMI_V_D, MOVAZ_2ZMI_V_H, MOVAZ_2ZMI_V_S, MOVAZ_... |
| printMatrixTileVector<1>(MI, 2, STI, O); |
| O << '['; |
| printOperand(MI, 3, STI, O); |
| O << ", "; |
| break; |
| case 66: |
| // MOVAZ_VG2_2ZM, MOVAZ_VG4_4ZM |
| printMatrix<64>(MI, 2, STI, O); |
| O << '['; |
| printOperand(MI, 3, STI, O); |
| O << ", "; |
| printMatrixIndex(MI, 4, STI, O); |
| break; |
| case 67: |
| // MOVAZ_ZMI_H_H, MOVAZ_ZMI_H_Q, MOVA_2ZMXI_H_B, MOVA_2ZMXI_H_D, MOVA_2ZM... |
| printMatrixTileVector<0>(MI, 1, STI, O); |
| O << '['; |
| break; |
| case 68: |
| // MOVAZ_ZMI_V_H, MOVAZ_ZMI_V_Q, MOVA_2ZMXI_V_B, MOVA_2ZMXI_V_D, MOVA_2ZM... |
| printMatrixTileVector<1>(MI, 1, STI, O); |
| O << '['; |
| break; |
| case 69: |
| // MOVA_VG2_2ZMXI, MOVA_VG4_4ZMXI |
| printMatrix<64>(MI, 1, STI, O); |
| O << '['; |
| printOperand(MI, 2, STI, O); |
| O << ", "; |
| printMatrixIndex(MI, 3, STI, O); |
| break; |
| case 70: |
| // MOVT_TIX |
| printVectorIndex<8>(MI, 1, STI, O); |
| O << ", "; |
| printOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 71: |
| // MSRR |
| printGPRSeqPairsClassOperand<64>(MI, 1, STI, O); |
| return; |
| break; |
| case 72: |
| // PMULLB_ZZZ_H, PMULLT_ZZZ_H, PUNPKHI_PP, PUNPKLO_PP, SABDLB_ZZZ_H, SABD... |
| printSVERegOp<'b'>(MI, 1, STI, O); |
| break; |
| case 73: |
| // PMULLB_ZZZ_Q, PMULLT_ZZZ_Q, UZP_VG2_2ZZZ_D, ZIP_VG2_2ZZZ_D |
| printSVERegOp<'d'>(MI, 1, STI, O); |
| O << ", "; |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| return; |
| break; |
| case 74: |
| // PTRUES_H, PTRUE_H |
| printSVEPattern(MI, 1, STI, O); |
| return; |
| break; |
| case 75: |
| // SABALB_ZZZ_H, SABALT_ZZZ_H, SADDV_VPZ_B, SCLAMP_VG2_2Z2Z_B, SCLAMP_VG4... |
| printSVERegOp<'b'>(MI, 2, STI, O); |
| break; |
| case 76: |
| // SMLALL_MZZI_BtoS, SMLALL_MZZI_HtoD, SMLALL_MZZ_BtoS, SMLALL_MZZ_HtoD, ... |
| printImmRangeScale<4, 3>(MI, 3, STI, O); |
| break; |
| case 77: |
| // SMOPA_MPPZZ_S, SMOPS_MPPZZ_S, SUMOPA_MPPZZ_S, SUMOPS_MPPZZ_S, UMOPA_MP... |
| printSVERegOp<'b'>(MI, 4, STI, O); |
| O << ", "; |
| printSVERegOp<'b'>(MI, 5, STI, O); |
| return; |
| break; |
| case 78: |
| // ST1i16, ST1i8, ST2i16, ST2i8, ST3i16, ST3i8, ST4i16, ST4i8 |
| printVectorIndex(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 79: |
| // ST1i16_POST, ST1i32_POST, ST1i64_POST, ST1i8_POST, ST2i16_POST, ST2i32... |
| O << "], "; |
| break; |
| case 80: |
| // TBLv8i8Four, TBLv8i8One, TBLv8i8Three, TBLv8i8Two, TBXv8i8Four, TBXv8i... |
| O << ".8b, "; |
| break; |
| case 81: |
| // UZP_VG4_4Z4Z_Q, ZIP_VG4_4Z4Z_Q |
| printTypedVectorList<0,'q'>(MI, 1, STI, O); |
| return; |
| break; |
| case 82: |
| // ZERO_T |
| O << " }"; |
| return; |
| break; |
| } |
| |
| |
| // Fragment 2 encoded into 7 bits for 86 unique commands. |
| switch ((Bits >> 29) & 127) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ABSWr, ABSXr, ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDG, ADDPL_XXI,... |
| printOperand(MI, 1, STI, O); |
| break; |
| case 1: |
| // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, BRKA_PPmP, BRKB_PPmP, CLS_ZPmZ_B, ... |
| printSVERegOp<>(MI, 2, STI, O); |
| O << "/m, "; |
| break; |
| case 2: |
| // ABS_ZPmZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H, FABS_ZPmZ... |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| return; |
| break; |
| case 3: |
| // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... |
| printVRegOperand(MI, 1, STI, O); |
| break; |
| case 4: |
| // ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDHNT_ZZZ_S, CMLA_ZZZ_D, DECP_ZP_D, EORBT_Z... |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| break; |
| case 5: |
| // ADCLB_ZZZ_S, ADCLT_ZZZ_S, CMLA_ZZZI_S, CMLA_ZZZ_S, DECP_ZP_S, EORBT_ZZ... |
| printSVERegOp<'s'>(MI, 2, STI, O); |
| break; |
| case 6: |
| // ADDHA_MPPZ_D, ADDHA_MPPZ_S, ADDVA_MPPZ_D, ADDVA_MPPZ_S, ANDV_VPZ_D, AN... |
| return; |
| break; |
| case 7: |
| // ADDHNB_ZZZ_B, DECP_XP_H, INCP_XP_H, RADDHNB_ZZZ_B, RSHRNB_ZZI_B, RSUBH... |
| printSVERegOp<'h'>(MI, 1, STI, O); |
| break; |
| case 8: |
| // ADDHNB_ZZZ_H, ADDHNT_ZZZ_H, ADD_VG2_2ZZ_B, ADD_VG2_2ZZ_D, ADD_VG2_2ZZ_... |
| O << ", "; |
| break; |
| case 9: |
| // ADDHNB_ZZZ_S, ADD_ZI_D, ADD_ZZZ_D, ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, A... |
| printSVERegOp<'d'>(MI, 1, STI, O); |
| break; |
| case 10: |
| // ADDHNT_ZZZ_B, BFDOT_ZZI, BFDOT_ZZZ, BFMLALB_ZZZ, BFMLALB_ZZZI, BFMLALT... |
| printSVERegOp<'h'>(MI, 2, STI, O); |
| break; |
| case 11: |
| // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... |
| printVRegOperand(MI, 2, STI, O); |
| break; |
| case 12: |
| // ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADDQV_VPZ_B, ADDQV_VPZ_D, ADDQV... |
| printSVERegOp<>(MI, 1, STI, O); |
| break; |
| case 13: |
| // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WID... |
| O << "/m, "; |
| break; |
| case 14: |
| // ADD_VG2_M2Z2Z_D, ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_D, ADD_VG2_M2ZZ_S, ADD_... |
| O << ", vgx2], "; |
| break; |
| case 15: |
| // ADD_VG4_M4Z4Z_D, ADD_VG4_M4Z4Z_S, ADD_VG4_M4ZZ_D, ADD_VG4_M4ZZ_S, ADD_... |
| O << ", vgx4], "; |
| break; |
| case 16: |
| // ADD_ZI_B, ADD_ZZZ_B, AESD_ZZZ_B, AESE_ZZZ_B, AESIMC_ZZ_B, AESMC_ZZ_B, ... |
| printSVERegOp<'b'>(MI, 1, STI, O); |
| break; |
| case 17: |
| // ADD_ZI_S, ADD_ZZZ_S, ADR_LSL_ZZZ_S_0, ADR_LSL_ZZZ_S_1, ADR_LSL_ZZZ_S_2... |
| printSVERegOp<'s'>(MI, 1, STI, O); |
| break; |
| case 18: |
| // ADRP |
| printAdrpLabel(MI, Address, 1, STI, O); |
| return; |
| break; |
| case 19: |
| // AUTDA, AUTDB, AUTIA, AUTIB, BFMWri, BFMXri, CASAB, CASAH, CASALB, CASA... |
| printOperand(MI, 2, STI, O); |
| break; |
| case 20: |
| // BFCVTNT_ZPmZ, BFCVT_ZPmZ, FCVTNT_ZPmZ_StoH, FCVT_ZPmZ_StoH, PMOV_ZIP_S... |
| printSVERegOp<'s'>(MI, 3, STI, O); |
| return; |
| break; |
| case 21: |
| // BFMLAL_MZZI_S, BFMLAL_MZZ_S, BFMLSL_MZZI_S, BFMLSL_MZZ_S, FMLAL_MZZI_S... |
| O << "], "; |
| break; |
| case 22: |
| // BICv2i32, BICv4i16, BICv4i32, BICv8i16, MOVKWi, MOVKXi, ORRv2i32, ORRv... |
| printImm(MI, 2, STI, O); |
| printShifter(MI, 3, STI, O); |
| return; |
| break; |
| case 23: |
| // CBNZW, CBNZX, CBZW, CBZX, LDRDl, LDRQl, LDRSWl, LDRSl, LDRWl, LDRXl, P... |
| printAlignedLabel(MI, Address, 1, STI, O); |
| return; |
| break; |
| case 24: |
| // CDOT_ZZZI_S, CDOT_ZZZ_S, CMLA_ZZZ_B, EORBT_ZZZ_B, EORTB_ZZZ_B, SABA_ZZ... |
| printSVERegOp<'b'>(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 25: |
| // CMPEQ_PPzZI_H, CMPEQ_PPzZZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_PPzZI_H, CMPGE... |
| O << "/z, "; |
| break; |
| case 26: |
| // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI, PTRUES_B, PTRUES_D, PTRUES... |
| printSVEPattern(MI, 1, STI, O); |
| break; |
| case 27: |
| // CNTP_XCI_B |
| printPredicateAsCounter<8>(MI, 1, STI, O); |
| O << ", "; |
| printSVEVecLenSpecifier(MI, 2, STI, O); |
| return; |
| break; |
| case 28: |
| // CNTP_XCI_D |
| printPredicateAsCounter<64>(MI, 1, STI, O); |
| O << ", "; |
| printSVEVecLenSpecifier(MI, 2, STI, O); |
| return; |
| break; |
| case 29: |
| // CNTP_XCI_H |
| printPredicateAsCounter<16>(MI, 1, STI, O); |
| O << ", "; |
| printSVEVecLenSpecifier(MI, 2, STI, O); |
| return; |
| break; |
| case 30: |
| // CNTP_XCI_S |
| printPredicateAsCounter<32>(MI, 1, STI, O); |
| O << ", "; |
| printSVEVecLenSpecifier(MI, 2, STI, O); |
| return; |
| break; |
| case 31: |
| // CPY_ZPmI_H |
| printImm8OptLsl<int16_t>(MI, 3, STI, O); |
| return; |
| break; |
| case 32: |
| // CPY_ZPmR_H, CPY_ZPmV_H, INSvi16gpr, INSvi32gpr, INSvi64gpr, INSvi8gpr,... |
| printOperand(MI, 3, STI, O); |
| break; |
| case 33: |
| // DECB_XPiI, DECD_XPiI, DECD_ZPiI, DECH_XPiI, DECW_XPiI, DECW_ZPiI, INCB... |
| printSVEPattern(MI, 2, STI, O); |
| O << ", mul "; |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 34: |
| // DUPM_ZI |
| printLogicalImm<int64_t>(MI, 1, STI, O); |
| return; |
| break; |
| case 35: |
| // DUPQ_ZZI_H, DUP_ZZI_H, DUP_ZZI_Q, PEXT_2PCI_B, PEXT_2PCI_D, PEXT_2PCI_... |
| printVectorIndex(MI, 2, STI, O); |
| return; |
| break; |
| case 36: |
| // DUP_ZI_B |
| printImm8OptLsl<int8_t>(MI, 1, STI, O); |
| return; |
| break; |
| case 37: |
| // DUP_ZI_D |
| printImm8OptLsl<int64_t>(MI, 1, STI, O); |
| return; |
| break; |
| case 38: |
| // DUP_ZI_S |
| printImm8OptLsl<int32_t>(MI, 1, STI, O); |
| return; |
| break; |
| case 39: |
| // EXTRACT_ZPMXI_H_H, EXTRACT_ZPMXI_H_Q |
| printMatrixTileVector<0>(MI, 3, STI, O); |
| O << '['; |
| printOperand(MI, 4, STI, O); |
| O << ", "; |
| printMatrixIndex(MI, 5, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 40: |
| // EXTRACT_ZPMXI_V_H, EXTRACT_ZPMXI_V_Q |
| printMatrixTileVector<1>(MI, 3, STI, O); |
| O << '['; |
| printOperand(MI, 4, STI, O); |
| O << ", "; |
| printMatrixIndex(MI, 5, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 41: |
| // EXT_ZZI_B, TBLQ_ZZZ_B, TBL_ZZZZ_B, TBL_ZZZ_B |
| printTypedVectorList<0,'b'>(MI, 1, STI, O); |
| O << ", "; |
| break; |
| case 42: |
| // FCPY_ZPmI_H |
| printFPImmOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 43: |
| // FCVT_ZPmZ_DtoH, PMOV_ZIP_D, SCVTF_ZPmZ_DtoH, UCVTF_ZPmZ_DtoH |
| printSVERegOp<'d'>(MI, 3, STI, O); |
| return; |
| break; |
| case 44: |
| // FDUP_ZI_D, FDUP_ZI_S, FMOVDi, FMOVHi, FMOVSi, FMOVv2f32_ns, FMOVv2f64_... |
| printFPImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 45: |
| // GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ... |
| O << "/z, ["; |
| break; |
| case 46: |
| // INDEX_II_B, INDEX_IR_B |
| printSImm<8>(MI, 1, STI, O); |
| O << ", "; |
| break; |
| case 47: |
| // INDEX_II_H |
| printSImm<16>(MI, 2, STI, O); |
| return; |
| break; |
| case 48: |
| // INSR_ZV_B |
| printZPRasFPR<8>(MI, 2, STI, O); |
| return; |
| break; |
| case 49: |
| // INSR_ZV_D |
| printZPRasFPR<64>(MI, 2, STI, O); |
| return; |
| break; |
| case 50: |
| // INSR_ZV_S |
| printZPRasFPR<32>(MI, 2, STI, O); |
| return; |
| break; |
| case 51: |
| // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane |
| printVRegOperand(MI, 3, STI, O); |
| printVectorIndex(MI, 4, STI, O); |
| return; |
| break; |
| case 52: |
| // LD1B_VG2_M2ZPXI, LD1B_VG2_M2ZPXX, LD1H_VG2_M2ZPXI, LD1H_VG2_M2ZPXX, LD... |
| printPredicateAsCounter<0>(MI, 1, STI, O); |
| break; |
| case 53: |
| // LDADDAB, LDADDAH, LDADDALB, LDADDALH, LDADDALW, LDADDALX, LDADDAW, LDA... |
| printOperand(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 54: |
| // MOVAZ_2ZMI_H_B, MOVAZ_2ZMI_H_D, MOVAZ_2ZMI_H_H, MOVAZ_2ZMI_H_S, MOVAZ_... |
| printImmRangeScale<2, 1>(MI, 4, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 55: |
| // MOVAZ_4ZMI_H_B, MOVAZ_4ZMI_H_D, MOVAZ_4ZMI_H_H, MOVAZ_4ZMI_H_S, MOVAZ_... |
| printImmRangeScale<4, 3>(MI, 4, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 56: |
| // MOVAZ_VG2_2ZM, MOVA_VG2_2ZMXI, ZERO_MXI_VG2_2Z, ZERO_MXI_VG2_4Z, ZERO_... |
| O << ", vgx2]"; |
| return; |
| break; |
| case 57: |
| // MOVAZ_VG4_4ZM, MOVA_VG4_4ZMXI, ZERO_MXI_VG4_2Z, ZERO_MXI_VG4_4Z, ZERO_... |
| O << ", vgx4]"; |
| return; |
| break; |
| case 58: |
| // MOVAZ_ZMI_H_B, MOVAZ_ZMI_H_D, MOVAZ_ZMI_H_S |
| printMatrixTileVector<0>(MI, 1, STI, O); |
| O << '['; |
| printOperand(MI, 3, STI, O); |
| O << ", "; |
| printMatrixIndex(MI, 4, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 59: |
| // MOVAZ_ZMI_V_B, MOVAZ_ZMI_V_D, MOVAZ_ZMI_V_S |
| printMatrixTileVector<1>(MI, 1, STI, O); |
| O << '['; |
| printOperand(MI, 3, STI, O); |
| O << ", "; |
| printMatrixIndex(MI, 4, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 60: |
| // MOVID, MOVIv2d_ns |
| printSIMDType10Operand(MI, 1, STI, O); |
| return; |
| break; |
| case 61: |
| // MOVIv16b_ns, MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl... |
| printImm(MI, 1, STI, O); |
| break; |
| case 62: |
| // MRS |
| printMRSSystemRegister(MI, 1, STI, O); |
| return; |
| break; |
| case 63: |
| // PMOV_ZIP_B |
| printSVERegOp<'b'>(MI, 3, STI, O); |
| return; |
| break; |
| case 64: |
| // REVD_ZPmZ |
| printSVERegOp<'q'>(MI, 3, STI, O); |
| return; |
| break; |
| case 65: |
| // SMLALL_VG2_M2ZZ_BtoS, SMLALL_VG2_M2ZZ_HtoD, SMLSLL_VG2_M2ZZ_BtoS, SMLS... |
| O << ", vgx2], "; |
| break; |
| case 66: |
| // SMLALL_VG4_M4ZZ_BtoS, SMLALL_VG4_M4ZZ_HtoD, SMLSLL_VG4_M4ZZ_BtoS, SMLS... |
| O << ", vgx4], "; |
| break; |
| case 67: |
| // SQCVTN_Z4Z_StoB, SQCVTUN_Z4Z_StoB, SQCVTU_Z4Z_StoB, SQCVT_Z4Z_StoB, SQ... |
| printTypedVectorList<0,'s'>(MI, 1, STI, O); |
| break; |
| case 68: |
| // SQDECB_XPiWdI, SQDECD_XPiWdI, SQDECH_XPiWdI, SQDECW_XPiWdI, SQINCB_XPi... |
| printGPR64as32(MI, 1, STI, O); |
| O << ", "; |
| printSVEPattern(MI, 2, STI, O); |
| O << ", mul "; |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 69: |
| // SST1B_D, SST1B_D_IMM, SST1B_D_SXTW, SST1B_D_UXTW, SST1B_S_IMM, SST1B_S... |
| O << ", ["; |
| break; |
| case 70: |
| // ST1i16_POST, ST2i8_POST |
| printPostIncOperand<2>(MI, 4, STI, O); |
| return; |
| break; |
| case 71: |
| // ST1i32_POST, ST2i16_POST, ST4i8_POST |
| printPostIncOperand<4>(MI, 4, STI, O); |
| return; |
| break; |
| case 72: |
| // ST1i64_POST, ST2i32_POST, ST4i16_POST |
| printPostIncOperand<8>(MI, 4, STI, O); |
| return; |
| break; |
| case 73: |
| // ST1i8_POST |
| printPostIncOperand<1>(MI, 4, STI, O); |
| return; |
| break; |
| case 74: |
| // ST2i64_POST, ST4i32_POST |
| printPostIncOperand<16>(MI, 4, STI, O); |
| return; |
| break; |
| case 75: |
| // ST3i16_POST |
| printPostIncOperand<6>(MI, 4, STI, O); |
| return; |
| break; |
| case 76: |
| // ST3i32_POST |
| printPostIncOperand<12>(MI, 4, STI, O); |
| return; |
| break; |
| case 77: |
| // ST3i64_POST |
| printPostIncOperand<24>(MI, 4, STI, O); |
| return; |
| break; |
| case 78: |
| // ST3i8_POST |
| printPostIncOperand<3>(MI, 4, STI, O); |
| return; |
| break; |
| case 79: |
| // ST4i64_POST |
| printPostIncOperand<32>(MI, 4, STI, O); |
| return; |
| break; |
| case 80: |
| // ST64BV, ST64BV0 |
| printGPR64x8(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 81: |
| // SYSPxt, SYSPxt_XZR, SYSxt |
| printSysCROperand(MI, 1, STI, O); |
| O << ", "; |
| printSysCROperand(MI, 2, STI, O); |
| O << ", "; |
| printOperand(MI, 3, STI, O); |
| O << ", "; |
| break; |
| case 82: |
| // TBLQ_ZZZ_D, TBL_ZZZZ_D, TBL_ZZZ_D |
| printTypedVectorList<0,'d'>(MI, 1, STI, O); |
| O << ", "; |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| return; |
| break; |
| case 83: |
| // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBLv8i8Four, TB... |
| printTypedVectorList<16, 'b'>(MI, 1, STI, O); |
| O << ", "; |
| printVRegOperand(MI, 2, STI, O); |
| break; |
| case 84: |
| // TBXv16i8Four, TBXv16i8One, TBXv16i8Three, TBXv16i8Two, TBXv8i8Four, TB... |
| printTypedVectorList<16, 'b'>(MI, 2, STI, O); |
| O << ", "; |
| printVRegOperand(MI, 3, STI, O); |
| break; |
| case 85: |
| // ZERO_MXI_2Z, ZERO_MXI_4Z |
| O << ']'; |
| return; |
| break; |
| } |
| |
| |
| // Fragment 3 encoded into 7 bits for 100 unique commands. |
| switch ((Bits >> 36) & 127) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ABSWr, ABSXr, ABSv16i8, ABSv1i64, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i... |
| return; |
| break; |
| case 1: |
| // ABS_ZPmZ_B, BRKA_PPmP, BRKB_PPmP, CDOT_ZZZI_S, CDOT_ZZZ_S, CLS_ZPmZ_B,... |
| printSVERegOp<'b'>(MI, 3, STI, O); |
| break; |
| case 2: |
| // ABS_ZPmZ_D, CLS_ZPmZ_D, CLZ_ZPmZ_D, CNOT_ZPmZ_D, CNT_ZPmZ_D, FABS_ZPmZ... |
| printSVERegOp<'d'>(MI, 3, STI, O); |
| return; |
| break; |
| case 3: |
| // ABS_ZPmZ_S, ADDHNT_ZZZ_H, CLS_ZPmZ_S, CLZ_ZPmZ_S, CNOT_ZPmZ_S, CNT_ZPm... |
| printSVERegOp<'s'>(MI, 3, STI, O); |
| return; |
| break; |
| case 4: |
| // ADCLB_ZZZ_D, ADCLB_ZZZ_S, ADCLT_ZZZ_D, ADCLT_ZZZ_S, ADCSWr, ADCSXr, AD... |
| O << ", "; |
| break; |
| case 5: |
| // ADDHNB_ZZZ_H, ADD_VG2_2ZZ_S, ADD_VG4_4ZZ_S, FMAXNM_VG2_2ZZ_S, FMAXNM_V... |
| printSVERegOp<'s'>(MI, 2, STI, O); |
| break; |
| case 6: |
| // ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPm... |
| O << "/m, "; |
| break; |
| case 7: |
| // ADDP_ZPmZ_H, ADD_VG2_2ZZ_H, ADD_VG4_4ZZ_H, ADD_ZPmZ_H, ADD_ZZZ_H, AND_... |
| printSVERegOp<'h'>(MI, 2, STI, O); |
| break; |
| case 8: |
| // ADD_VG2_2ZZ_B, ADD_VG4_4ZZ_B, PMULLB_ZZZ_H, PMULLT_ZZZ_H, SABDLB_ZZZ_H... |
| printSVERegOp<'b'>(MI, 2, STI, O); |
| return; |
| break; |
| case 9: |
| // ADD_VG2_2ZZ_D, ADD_VG4_4ZZ_D, ASR_WIDE_ZZZ_H, FMAXNM_VG2_2ZZ_D, FMAXNM... |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| break; |
| case 10: |
| // ADD_VG2_M2Z2Z_D, ADD_VG2_M2ZZ_D, ADD_VG2_M2Z_D, ADD_VG4_M4Z4Z_D, ADD_V... |
| printTypedVectorList<0,'d'>(MI, 4, STI, O); |
| break; |
| case 11: |
| // ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_S, ADD_VG2_M2Z_S, ADD_VG4_M4Z4Z_S, ADD_V... |
| printTypedVectorList<0,'s'>(MI, 4, STI, O); |
| break; |
| case 12: |
| // ADD_ZI_H, SQADD_ZI_H, SQSUB_ZI_H, SUBR_ZI_H, SUB_ZI_H, UQADD_ZI_H, UQS... |
| printImm8OptLsl<uint16_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 13: |
| // ANDS_PPzPP, AND_PPzPP, BICS_PPzPP, BIC_PPzPP, BRKAS_PPzP, BRKA_PPzP, B... |
| O << "/z, "; |
| break; |
| case 14: |
| // ASR_ZZI_H, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, GLD1B_S... |
| printOperand(MI, 2, STI, O); |
| break; |
| case 15: |
| // BFCLAMP_VG2_2ZZZ_H, BFCLAMP_VG4_4ZZZ_H, BFCLAMP_ZZZ, BFMLA_ZPmZZ, BFML... |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| break; |
| case 16: |
| // BFDOT_VG2_M2Z2Z_HtoS, BFDOT_VG2_M2ZZI_HtoS, BFDOT_VG2_M2ZZ_HtoS, BFDOT... |
| printTypedVectorList<0,'h'>(MI, 4, STI, O); |
| O << ", "; |
| break; |
| case 17: |
| // BFMAXNM_VG2_2Z2Z_H, BFMAXNM_VG4_4Z2Z_H, BFMAX_VG2_2Z2Z_H, BFMAX_VG4_4Z... |
| printTypedVectorList<0,'h'>(MI, 2, STI, O); |
| break; |
| case 18: |
| // BFMLAL_MZZI_S, BFMLAL_MZZ_S, BFMLSL_MZZI_S, BFMLSL_MZZ_S, FMLAL_MZZI_S... |
| printSVERegOp<'h'>(MI, 4, STI, O); |
| O << ", "; |
| printSVERegOp<'h'>(MI, 5, STI, O); |
| break; |
| case 19: |
| // BFMLA_VG2_M2Z2Z, BFMLA_VG4_M4Z4Z, BFMLS_VG2_M2Z2Z, BFMLS_VG4_M4Z4Z, FM... |
| printTypedVectorList<0,'h'>(MI, 5, STI, O); |
| return; |
| break; |
| case 20: |
| // BFMLA_VG2_M2ZZ, BFMLA_VG2_M2ZZI, BFMLA_VG4_M4ZZ, BFMLA_VG4_M4ZZI, BFML... |
| printSVERegOp<'h'>(MI, 5, STI, O); |
| break; |
| case 21: |
| // BMOPA_MPPZZ_S, BMOPS_MPPZZ_S, FMOPA_MPPZZ_S, FMOPS_MPPZZ_S |
| printSVERegOp<'s'>(MI, 5, STI, O); |
| return; |
| break; |
| case 22: |
| // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... |
| O << ", ["; |
| break; |
| case 23: |
| // CMEQv16i8rz, CMEQv1i64rz, CMEQv2i32rz, CMEQv2i64rz, CMEQv4i16rz, CMEQv... |
| O << ", #0"; |
| return; |
| break; |
| case 24: |
| // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI |
| O << ", mul "; |
| printOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 25: |
| // CPY_ZPmI_B |
| printImm8OptLsl<int8_t>(MI, 3, STI, O); |
| return; |
| break; |
| case 26: |
| // CPY_ZPmI_D |
| printImm8OptLsl<int64_t>(MI, 3, STI, O); |
| return; |
| break; |
| case 27: |
| // CPY_ZPmI_S |
| printImm8OptLsl<int32_t>(MI, 3, STI, O); |
| return; |
| break; |
| case 28: |
| // CPY_ZPmR_B, CPY_ZPmR_D, CPY_ZPmR_S, CPY_ZPmV_B, CPY_ZPmV_D, CPY_ZPmV_S... |
| printOperand(MI, 3, STI, O); |
| break; |
| case 29: |
| // CPY_ZPzI_H |
| printImm8OptLsl<int16_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 30: |
| // DUPQ_ZZI_B, DUPQ_ZZI_D, DUPQ_ZZI_S, DUP_ZZI_B, DUP_ZZI_D, DUP_ZZI_S, D... |
| printVectorIndex(MI, 2, STI, O); |
| return; |
| break; |
| case 31: |
| // EXTRACT_ZPMXI_H_B, EXTRACT_ZPMXI_H_D, EXTRACT_ZPMXI_H_S |
| printMatrixTileVector<0>(MI, 3, STI, O); |
| O << '['; |
| printOperand(MI, 4, STI, O); |
| O << ", "; |
| printMatrixIndex(MI, 5, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 32: |
| // EXTRACT_ZPMXI_V_B, EXTRACT_ZPMXI_V_D, EXTRACT_ZPMXI_V_S |
| printMatrixTileVector<1>(MI, 3, STI, O); |
| O << '['; |
| printOperand(MI, 4, STI, O); |
| O << ", "; |
| printMatrixIndex(MI, 5, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 33: |
| // EXT_ZZI_B, UMAX_ZI_H, UMIN_ZI_H |
| printImm(MI, 2, STI, O); |
| return; |
| break; |
| case 34: |
| // FCMEQv1i16rz, FCMEQv1i32rz, FCMEQv1i64rz, FCMEQv2i32rz, FCMEQv2i64rz, ... |
| O << ", #0.0"; |
| return; |
| break; |
| case 35: |
| // FCPY_ZPmI_D, FCPY_ZPmI_S |
| printFPImmOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 36: |
| // FCVTLv2i32 |
| O << ".2s"; |
| return; |
| break; |
| case 37: |
| // FCVTLv4i16 |
| O << ".4h"; |
| return; |
| break; |
| case 38: |
| // FCVTLv4i32, FCVTNv8i16 |
| O << ".4s"; |
| return; |
| break; |
| case 39: |
| // FCVTLv8i16 |
| O << ".8h"; |
| return; |
| break; |
| case 40: |
| // FCVTNv4i32, FCVTXNv4f32 |
| O << ".2d"; |
| return; |
| break; |
| case 41: |
| // FMAXNM_VG2_2Z2Z_D, FMAXNM_VG4_4Z4Z_D, FMAX_VG2_2Z2Z_D, FMAX_VG4_4Z4Z_D... |
| printTypedVectorList<0,'d'>(MI, 2, STI, O); |
| break; |
| case 42: |
| // FMAXNM_VG2_2Z2Z_S, FMAXNM_VG4_4Z4Z_S, FMAX_VG2_2Z2Z_S, FMAX_VG4_4Z4Z_S... |
| printTypedVectorList<0,'s'>(MI, 2, STI, O); |
| break; |
| case 43: |
| // FMOPA_MPPZZ_D, FMOPS_MPPZZ_D |
| printSVERegOp<'d'>(MI, 5, STI, O); |
| return; |
| break; |
| case 44: |
| // INDEX_II_B |
| printSImm<8>(MI, 2, STI, O); |
| return; |
| break; |
| case 45: |
| // INDEX_RI_H |
| printSImm<16>(MI, 2, STI, O); |
| return; |
| break; |
| case 46: |
| // INSERT_MXIPZ_H_B, INSERT_MXIPZ_H_D, INSERT_MXIPZ_H_H, INSERT_MXIPZ_H_Q... |
| printMatrixIndex(MI, 3, STI, O); |
| O << "], "; |
| printSVERegOp<>(MI, 4, STI, O); |
| O << "/m, "; |
| break; |
| case 47: |
| // LD1B_VG2_M2ZPXI, LD1B_VG2_M2ZPXX, LD1H_VG2_M2ZPXI, LD1H_VG2_M2ZPXX, LD... |
| O << "/z, ["; |
| printOperand(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 48: |
| // LD1_MXIPXX_H_B, LD1_MXIPXX_H_D, LD1_MXIPXX_H_H, LD1_MXIPXX_H_Q, LD1_MX... |
| printMatrixIndex(MI, 2, STI, O); |
| O << "]}, "; |
| printSVERegOp<>(MI, 3, STI, O); |
| break; |
| case 49: |
| // LDAPRB, LDAPRH, LDAPRW, LDAPRX, LDAPURbi, LDAPURdi, LDAPURhi, LDAPURqi... |
| O << ']'; |
| return; |
| break; |
| case 50: |
| // LDAPRWpre |
| O << "], #4"; |
| return; |
| break; |
| case 51: |
| // LDAPRXpre |
| O << "], #8"; |
| return; |
| break; |
| case 52: |
| // LDRBBpost, LDRBpost, LDRDpost, LDRHHpost, LDRHpost, LDRQpost, LDRSBWpo... |
| O << "], "; |
| break; |
| case 53: |
| // LUTI2_2ZTZI_B, LUTI2_2ZTZI_H, LUTI2_2ZTZI_S, LUTI2_4ZTZI_B, LUTI2_4ZTZ... |
| printSVERegOp<>(MI, 2, STI, O); |
| printVectorIndex(MI, 3, STI, O); |
| return; |
| break; |
| case 54: |
| // MOVA_MXI2Z_H_B, MOVA_MXI2Z_H_D, MOVA_MXI2Z_H_H, MOVA_MXI2Z_H_S, MOVA_M... |
| printImmRangeScale<2, 1>(MI, 3, STI, O); |
| O << "], "; |
| break; |
| case 55: |
| // MOVA_MXI4Z_H_B, MOVA_MXI4Z_H_D, MOVA_MXI4Z_H_H, MOVA_MXI4Z_H_S, MOVA_M... |
| printImmRangeScale<4, 3>(MI, 3, STI, O); |
| O << "], "; |
| break; |
| case 56: |
| // MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl, MOVIv8i16, ... |
| printShifter(MI, 2, STI, O); |
| return; |
| break; |
| case 57: |
| // MOVT_XTI |
| printVectorIndex<8>(MI, 2, STI, O); |
| return; |
| break; |
| case 58: |
| // PRFB_D_SCALED |
| printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 59: |
| // PRFB_D_SXTW_SCALED |
| printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 60: |
| // PRFB_D_UXTW_SCALED |
| printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 61: |
| // PRFB_PRR |
| printRegWithShiftExtend<false, 8, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 62: |
| // PRFB_S_SXTW_SCALED |
| printRegWithShiftExtend<true, 8, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 63: |
| // PRFB_S_UXTW_SCALED |
| printRegWithShiftExtend<false, 8, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 64: |
| // PRFD_D_PZI, PRFD_S_PZI |
| printImmScale<8>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 65: |
| // PRFD_D_SCALED |
| printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 66: |
| // PRFD_D_SXTW_SCALED |
| printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 67: |
| // PRFD_D_UXTW_SCALED |
| printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 68: |
| // PRFD_PRR |
| printRegWithShiftExtend<false, 64, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 69: |
| // PRFD_S_SXTW_SCALED |
| printRegWithShiftExtend<true, 64, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 70: |
| // PRFD_S_UXTW_SCALED |
| printRegWithShiftExtend<false, 64, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 71: |
| // PRFH_D_PZI, PRFH_S_PZI |
| printImmScale<2>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 72: |
| // PRFH_D_SCALED |
| printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 73: |
| // PRFH_D_SXTW_SCALED |
| printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 74: |
| // PRFH_D_UXTW_SCALED |
| printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 75: |
| // PRFH_PRR |
| printRegWithShiftExtend<false, 16, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 76: |
| // PRFH_S_SXTW_SCALED |
| printRegWithShiftExtend<true, 16, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 77: |
| // PRFH_S_UXTW_SCALED |
| printRegWithShiftExtend<false, 16, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 78: |
| // PRFW_D_PZI, PRFW_S_PZI |
| printImmScale<4>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 79: |
| // PRFW_D_SCALED |
| printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 80: |
| // PRFW_D_SXTW_SCALED |
| printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 81: |
| // PRFW_D_UXTW_SCALED |
| printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 82: |
| // PRFW_PRR |
| printRegWithShiftExtend<false, 32, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 83: |
| // PRFW_S_SXTW_SCALED |
| printRegWithShiftExtend<true, 32, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 84: |
| // PRFW_S_UXTW_SCALED |
| printRegWithShiftExtend<false, 32, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 85: |
| // RDFFRS_PPz, RDFFR_PPz_REAL |
| O << "/z"; |
| return; |
| break; |
| case 86: |
| // SDOT_VG2_M2Z2Z_BtoS, SDOT_VG2_M2ZZI_BToS, SDOT_VG2_M2ZZ_BtoS, SDOT_VG4... |
| printTypedVectorList<0,'b'>(MI, 4, STI, O); |
| O << ", "; |
| break; |
| case 87: |
| // SEL_VG2_2ZP2Z2Z_B, SEL_VG4_4ZP4Z4Z_B, SMAX_VG2_2Z2Z_B, SMAX_VG4_4Z4Z_B... |
| printTypedVectorList<0,'b'>(MI, 2, STI, O); |
| break; |
| case 88: |
| // SHLLv16i8, SHLLv8i8 |
| O << ", #8"; |
| return; |
| break; |
| case 89: |
| // SHLLv2i32, SHLLv4i32 |
| O << ", #32"; |
| return; |
| break; |
| case 90: |
| // SHLLv4i16, SHLLv8i16 |
| O << ", #16"; |
| return; |
| break; |
| case 91: |
| // SMLALL_MZZI_BtoS, SMLALL_MZZ_BtoS, SMLSLL_MZZI_BtoS, SMLSLL_MZZ_BtoS, ... |
| printSVERegOp<'b'>(MI, 4, STI, O); |
| O << ", "; |
| printSVERegOp<'b'>(MI, 5, STI, O); |
| break; |
| case 92: |
| // STLRWpre |
| O << ", #-4]!"; |
| return; |
| break; |
| case 93: |
| // STLRXpre |
| O << ", #-8]!"; |
| return; |
| break; |
| case 94: |
| // SYSPxt |
| printGPRSeqPairsClassOperand<64>(MI, 4, STI, O); |
| return; |
| break; |
| case 95: |
| // SYSPxt_XZR |
| printSyspXzrPair(MI, 4, STI, O); |
| return; |
| break; |
| case 96: |
| // SYSxt |
| printOperand(MI, 4, STI, O); |
| return; |
| break; |
| case 97: |
| // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBXv16i8Four, T... |
| O << ".16b"; |
| return; |
| break; |
| case 98: |
| // TBLv8i8Four, TBLv8i8One, TBLv8i8Three, TBLv8i8Two, TBXv8i8Four, TBXv8i... |
| O << ".8b"; |
| return; |
| break; |
| case 99: |
| // TRN1_ZZZ_Q, TRN2_ZZZ_Q, UZP1_ZZZ_Q, UZP2_ZZZ_Q, UZP_VG2_2ZZZ_Q, ZIP1_Z... |
| printSVERegOp<'q'>(MI, 2, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 4 encoded into 7 bits for 85 unique commands. |
| switch ((Bits >> 43) & 127) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ABS_ZPmZ_B, ADDHNB_ZZZ_H, ADD_VG2_2ZZ_D, ADD_VG2_2ZZ_H, ADD_VG2_2ZZ_S,... |
| return; |
| break; |
| case 1: |
| // ADCLB_ZZZ_D, ADCLT_ZZZ_D, ADDHNT_ZZZ_S, CMLA_ZZZ_D, EORBT_ZZZ_D, EORTB... |
| printSVERegOp<'d'>(MI, 3, STI, O); |
| break; |
| case 2: |
| // ADCLB_ZZZ_S, ADCLT_ZZZ_S, CMLA_ZZZI_S, CMLA_ZZZ_S, EORBT_ZZZ_S, EORTB_... |
| printSVERegOp<'s'>(MI, 3, STI, O); |
| break; |
| case 3: |
| // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDSPL_XXI, ADDSVL_XXI, ADDSX... |
| printOperand(MI, 2, STI, O); |
| break; |
| case 4: |
| // ADDG, ST2GOffset, STGOffset, STZ2GOffset, STZGOffset, SUBG |
| printImmScale<16>(MI, 2, STI, O); |
| break; |
| case 5: |
| // ADDHNB_ZZZ_B, ADDQV_VPZ_H, ANDQV_VPZ_H, CNTP_XPP_H, EORQV_VPZ_H, FADDQ... |
| printSVERegOp<'h'>(MI, 2, STI, O); |
| break; |
| case 6: |
| // ADDHNB_ZZZ_S, ADDP_ZPmZ_D, ADDQV_VPZ_D, ADD_ZPmZ_D, ADD_ZZZ_D, ANDQV_V... |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| break; |
| case 7: |
| // ADDHNT_ZZZ_B, BFDOT_ZZI, BFDOT_ZZZ, BFMLALB_ZZZ, BFMLALB_ZZZI, BFMLALT... |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| break; |
| case 8: |
| // ADDHNv2i64_v2i32, ADDHNv4i32_v4i16, ADDHNv8i16_v8i8, ADDPv16i8, ADDPv2... |
| printVRegOperand(MI, 2, STI, O); |
| break; |
| case 9: |
| // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, BF16DOTlanev4bf1... |
| printVRegOperand(MI, 3, STI, O); |
| break; |
| case 10: |
| // ADDP_ZPmZ_B, ADDQV_VPZ_B, ADD_ZPmZ_B, ADD_ZZZ_B, AESD_ZZZ_B, AESE_ZZZ_... |
| printSVERegOp<'b'>(MI, 2, STI, O); |
| break; |
| case 11: |
| // ADDP_ZPmZ_H, ADD_VG2_M2Z2Z_D, ADD_VG2_M2Z2Z_S, ADD_VG2_M2ZZ_D, ADD_VG2... |
| O << ", "; |
| break; |
| case 12: |
| // ADDP_ZPmZ_S, ADDQV_VPZ_S, ADD_ZPmZ_S, ADD_ZZZ_S, ANDQV_VPZ_S, AND_ZPmZ... |
| printSVERegOp<'s'>(MI, 2, STI, O); |
| break; |
| case 13: |
| // ADDSWri, ADDSXri, ADDWri, ADDXri, SUBSWri, SUBSXri, SUBWri, SUBXri |
| printAddSubImm(MI, 2, STI, O); |
| return; |
| break; |
| case 14: |
| // ADDSWrs, ADDSXrs, ADDWrs, ADDXrs, ANDSWrs, ANDSXrs, ANDWrs, ANDXrs, BI... |
| printShiftedRegister(MI, 2, STI, O); |
| return; |
| break; |
| case 15: |
| // ADDSWrx, ADDSXrx, ADDWrx, ADDXrx, SUBSWrx, SUBSXrx, SUBWrx, SUBXrx |
| printExtendedRegister(MI, 2, STI, O); |
| return; |
| break; |
| case 16: |
| // ADD_ZI_B, SQADD_ZI_B, SQSUB_ZI_B, SUBR_ZI_B, SUB_ZI_B, UQADD_ZI_B, UQS... |
| printImm8OptLsl<uint8_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 17: |
| // ADD_ZI_D, SQADD_ZI_D, SQSUB_ZI_D, SUBR_ZI_D, SUB_ZI_D, UQADD_ZI_D, UQS... |
| printImm8OptLsl<uint64_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 18: |
| // ADD_ZI_S, SQADD_ZI_S, SQSUB_ZI_S, SUBR_ZI_S, SUB_ZI_S, UQADD_ZI_S, UQS... |
| printImm8OptLsl<uint32_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 19: |
| // ADR_LSL_ZZZ_D_0 |
| printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 20: |
| // ADR_LSL_ZZZ_D_1 |
| printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 21: |
| // ADR_LSL_ZZZ_D_2 |
| printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 22: |
| // ADR_LSL_ZZZ_D_3 |
| printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 23: |
| // ADR_LSL_ZZZ_S_0 |
| printRegWithShiftExtend<false, 8, 'x', 's'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 24: |
| // ADR_LSL_ZZZ_S_1 |
| printRegWithShiftExtend<false, 16, 'x', 's'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 25: |
| // ADR_LSL_ZZZ_S_2 |
| printRegWithShiftExtend<false, 32, 'x', 's'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 26: |
| // ADR_LSL_ZZZ_S_3 |
| printRegWithShiftExtend<false, 64, 'x', 's'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 27: |
| // ADR_SXTW_ZZZ_D_0 |
| printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 28: |
| // ADR_SXTW_ZZZ_D_1 |
| printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 29: |
| // ADR_SXTW_ZZZ_D_2 |
| printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 30: |
| // ADR_SXTW_ZZZ_D_3 |
| printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 31: |
| // ADR_UXTW_ZZZ_D_0 |
| printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 32: |
| // ADR_UXTW_ZZZ_D_1 |
| printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 33: |
| // ADR_UXTW_ZZZ_D_2 |
| printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 34: |
| // ADR_UXTW_ZZZ_D_3 |
| printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 35: |
| // ANDSWri, ANDWri, EORWri, ORRWri |
| printLogicalImm<int32_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 36: |
| // ANDSXri, ANDXri, AND_ZI, EORXri, EOR_ZI, ORRXri, ORR_ZI |
| printLogicalImm<int64_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 37: |
| // BFDOT_VG2_M2Z2Z_HtoS, BFDOT_VG4_M4Z4Z_HtoS, BFMLAL_VG2_M2Z2Z_S, BFMLAL... |
| printTypedVectorList<0,'h'>(MI, 5, STI, O); |
| return; |
| break; |
| case 38: |
| // BFDOT_VG2_M2ZZI_HtoS, BFDOT_VG2_M2ZZ_HtoS, BFDOT_VG4_M4ZZI_HtoS, BFDOT... |
| printSVERegOp<'h'>(MI, 5, STI, O); |
| break; |
| case 39: |
| // BFMLAL_MZZI_S, BFMLA_VG2_M2ZZI, BFMLA_VG4_M4ZZI, BFMLSL_MZZI_S, BFMLS_... |
| printVectorIndex(MI, 6, STI, O); |
| return; |
| break; |
| case 40: |
| // BFMLA_ZZZI, BFMLS_ZZZI, CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, FMLA_Z... |
| printVectorIndex(MI, 4, STI, O); |
| break; |
| case 41: |
| // BFMUL_ZZZI, FMUL_ZZZI_H, MUL_ZZZI_H, SQDMULH_ZZZI_H, SQRDMULH_ZZZI_H |
| printVectorIndex(MI, 3, STI, O); |
| return; |
| break; |
| case 42: |
| // BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, C... |
| printOperand(MI, 3, STI, O); |
| break; |
| case 43: |
| // CPY_ZPzI_B |
| printImm8OptLsl<int8_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 44: |
| // CPY_ZPzI_D |
| printImm8OptLsl<int64_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 45: |
| // CPY_ZPzI_S |
| printImm8OptLsl<int32_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 46: |
| // FCMEQ_PPzZ0_H, FCMGE_PPzZ0_H, FCMGT_PPzZ0_H, FCMLE_PPzZ0_H, FCMLT_PPzZ... |
| O << ", #0.0"; |
| return; |
| break; |
| case 47: |
| // INDEX_RI_B |
| printSImm<8>(MI, 2, STI, O); |
| return; |
| break; |
| case 48: |
| // INSERT_MXIPZ_H_B, INSERT_MXIPZ_V_B, SDOT_VG2_M2ZZI_BToS, SDOT_VG2_M2ZZ... |
| printSVERegOp<'b'>(MI, 5, STI, O); |
| break; |
| case 49: |
| // INSERT_MXIPZ_H_D, INSERT_MXIPZ_V_D |
| printSVERegOp<'d'>(MI, 5, STI, O); |
| return; |
| break; |
| case 50: |
| // INSERT_MXIPZ_H_Q, INSERT_MXIPZ_V_Q |
| printSVERegOp<'q'>(MI, 5, STI, O); |
| return; |
| break; |
| case 51: |
| // INSERT_MXIPZ_H_S, INSERT_MXIPZ_V_S |
| printSVERegOp<'s'>(MI, 5, STI, O); |
| return; |
| break; |
| case 52: |
| // LD1B_VG2_M2ZPXI, LD1H_VG2_M2ZPXI, LDNT1B_VG2_M2ZPXI, LDNT1H_VG2_M2ZPXI |
| printImmScale<2>(MI, 3, STI, O); |
| O << ", mul vl]"; |
| return; |
| break; |
| case 53: |
| // LD1B_VG2_M2ZPXX, LDNT1B_VG2_M2ZPXX |
| printRegWithShiftExtend<false, 8, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 54: |
| // LD1H_VG2_M2ZPXX, LDNT1H_VG2_M2ZPXX |
| printRegWithShiftExtend<false, 16, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 55: |
| // LD1_MXIPXX_H_B, LD1_MXIPXX_H_D, LD1_MXIPXX_H_H, LD1_MXIPXX_H_Q, LD1_MX... |
| O << "/z, ["; |
| printOperand(MI, 4, STI, O); |
| O << ", "; |
| break; |
| case 56: |
| // LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPL, LDSETP, LDSETPA, LDSETPAL, LDSETPL... |
| printOperand(MI, 4, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 57: |
| // LDG, ST2GPostIndex, ST2GPreIndex, STGPostIndex, STGPreIndex, STZ2GPost... |
| printImmScale<16>(MI, 3, STI, O); |
| break; |
| case 58: |
| // LDRAAindexed, LDRABindexed |
| printImmScale<8>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 59: |
| // LDRAAwriteback, LDRABwriteback |
| printImmScale<8>(MI, 3, STI, O); |
| O << "]!"; |
| return; |
| break; |
| case 60: |
| // LDRBBui, LDRBui, LDRSBWui, LDRSBXui, STRBBui, STRBui |
| printUImm12Offset<1>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 61: |
| // LDRDui, LDRXui, PRFMui, STRDui, STRXui |
| printUImm12Offset<8>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 62: |
| // LDRHHui, LDRHui, LDRSHWui, LDRSHXui, STRHHui, STRHui |
| printUImm12Offset<2>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 63: |
| // LDRQui, STRQui |
| printUImm12Offset<16>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 64: |
| // LDRSWui, LDRSui, LDRWui, STRSui, STRWui |
| printUImm12Offset<4>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 65: |
| // LUTI2_S_2ZTZI_B, LUTI2_S_2ZTZI_H, LUTI2_ZTZI_B, LUTI2_ZTZI_S, LUTI4_S_... |
| printSVERegOp<>(MI, 2, STI, O); |
| printVectorIndex(MI, 3, STI, O); |
| return; |
| break; |
| case 66: |
| // MAD_ZPmZZ_B, MLA_ZPmZZ_B, MLS_ZPmZZ_B, MSB_ZPmZZ_B |
| printSVERegOp<'b'>(MI, 3, STI, O); |
| O << ", "; |
| printSVERegOp<'b'>(MI, 4, STI, O); |
| return; |
| break; |
| case 67: |
| // MOVAZ_ZMI_H_H, MOVAZ_ZMI_H_Q, MOVAZ_ZMI_V_H, MOVAZ_ZMI_V_Q |
| printMatrixIndex(MI, 4, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 68: |
| // MOVA_2ZMXI_H_B, MOVA_2ZMXI_H_D, MOVA_2ZMXI_H_H, MOVA_2ZMXI_H_S, MOVA_2... |
| printImmRangeScale<2, 1>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 69: |
| // MOVA_4ZMXI_H_B, MOVA_4ZMXI_H_D, MOVA_4ZMXI_H_H, MOVA_4ZMXI_H_S, MOVA_4... |
| printImmRangeScale<4, 3>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 70: |
| // MOVA_MXI2Z_H_B, MOVA_MXI2Z_V_B, MOVA_MXI4Z_H_B, MOVA_MXI4Z_V_B |
| printTypedVectorList<0,'b'>(MI, 4, STI, O); |
| return; |
| break; |
| case 71: |
| // MOVA_MXI2Z_H_D, MOVA_MXI2Z_V_D, MOVA_MXI4Z_H_D, MOVA_MXI4Z_V_D |
| printTypedVectorList<0,'d'>(MI, 4, STI, O); |
| return; |
| break; |
| case 72: |
| // MOVA_MXI2Z_H_H, MOVA_MXI2Z_V_H, MOVA_MXI4Z_H_H, MOVA_MXI4Z_V_H |
| printTypedVectorList<0,'h'>(MI, 4, STI, O); |
| return; |
| break; |
| case 73: |
| // MOVA_MXI2Z_H_S, MOVA_MXI2Z_V_S, MOVA_MXI4Z_H_S, MOVA_MXI4Z_V_S |
| printTypedVectorList<0,'s'>(MI, 4, STI, O); |
| return; |
| break; |
| case 74: |
| // PRFB_D_PZI, PRFB_S_PZI |
| O << ']'; |
| return; |
| break; |
| case 75: |
| // PRFB_PRI, PRFD_PRI, PRFH_PRI, PRFW_PRI |
| O << ", mul vl]"; |
| return; |
| break; |
| case 76: |
| // SDOT_VG2_M2Z2Z_BtoS, SDOT_VG4_M4Z4Z_BtoS, SMLALL_VG2_M2Z2Z_BtoS, SMLAL... |
| printTypedVectorList<0,'b'>(MI, 5, STI, O); |
| return; |
| break; |
| case 77: |
| // SPLICE_ZPZZ_B |
| printTypedVectorList<0,'b'>(MI, 2, STI, O); |
| return; |
| break; |
| case 78: |
| // SPLICE_ZPZZ_D |
| printTypedVectorList<0,'d'>(MI, 2, STI, O); |
| return; |
| break; |
| case 79: |
| // SPLICE_ZPZZ_S |
| printTypedVectorList<0,'s'>(MI, 2, STI, O); |
| return; |
| break; |
| case 80: |
| // SQDECP_XPWd_B, SQDECP_XPWd_D, SQDECP_XPWd_H, SQDECP_XPWd_S, SQINCP_XPW... |
| printGPR64as32(MI, 2, STI, O); |
| return; |
| break; |
| case 81: |
| // ST1_MXIPXX_H_B, ST1_MXIPXX_H_D, ST1_MXIPXX_H_H, ST1_MXIPXX_H_Q, ST1_MX... |
| O << ", ["; |
| printOperand(MI, 4, STI, O); |
| O << ", "; |
| break; |
| case 82: |
| // SYSLxt |
| printSysCROperand(MI, 2, STI, O); |
| O << ", "; |
| printSysCROperand(MI, 3, STI, O); |
| O << ", "; |
| printOperand(MI, 4, STI, O); |
| return; |
| break; |
| case 83: |
| // TBNZW, TBNZX, TBZW, TBZX |
| printAlignedLabel(MI, Address, 2, STI, O); |
| return; |
| break; |
| case 84: |
| // UMAX_ZI_B, UMAX_ZI_D, UMAX_ZI_S, UMIN_ZI_B, UMIN_ZI_D, UMIN_ZI_S |
| printImm(MI, 2, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 5 encoded into 7 bits for 69 unique commands. |
| switch ((Bits >> 50) & 127) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ADCLB_ZZZ_D, ADCLB_ZZZ_S, ADCLT_ZZZ_D, ADCLT_ZZZ_S, ADCSWr, ADCSXr, AD... |
| return; |
| break; |
| case 1: |
| // ADDG, ADDP_ZPmZ_B, ADDP_ZPmZ_D, ADDP_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, A... |
| O << ", "; |
| break; |
| case 2: |
| // ADDP_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BFADD_ZP... |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| break; |
| case 3: |
| // ADDSXrx64, ADDXrx64, SUBSXrx64, SUBXrx64 |
| printArithExtend(MI, 3, STI, O); |
| return; |
| break; |
| case 4: |
| // ADD_VG2_M2Z2Z_D, ADD_VG4_M4Z4Z_D, FMLA_VG2_M2Z2Z_D, FMLA_VG4_M4Z4Z_D, ... |
| printTypedVectorList<0,'d'>(MI, 5, STI, O); |
| return; |
| break; |
| case 5: |
| // ADD_VG2_M2Z2Z_S, ADD_VG4_M4Z4Z_S, FMLA_VG2_M2Z2Z_S, FMLA_VG4_M4Z4Z_S, ... |
| printTypedVectorList<0,'s'>(MI, 5, STI, O); |
| return; |
| break; |
| case 6: |
| // ADD_VG2_M2ZZ_D, ADD_VG4_M4ZZ_D, FMLA_VG2_M2ZZI_D, FMLA_VG2_M2ZZ_D, FML... |
| printSVERegOp<'d'>(MI, 5, STI, O); |
| break; |
| case 7: |
| // ADD_VG2_M2ZZ_S, ADD_VG4_M4ZZ_S, FMLA_VG2_M2ZZI_S, FMLA_VG2_M2ZZ_S, FML... |
| printSVERegOp<'s'>(MI, 5, STI, O); |
| break; |
| case 8: |
| // ASRD_ZPmI_H, ASR_ZPmI_H, CMPEQ_PPzZI_H, CMPGE_PPzZI_H, CMPGT_PPzZI_H, ... |
| printOperand(MI, 3, STI, O); |
| break; |
| case 9: |
| // ASR_WIDE_ZPmZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_WIDE_PPzZZ_H, CMPGT_WIDE_PP... |
| printSVERegOp<'d'>(MI, 3, STI, O); |
| return; |
| break; |
| case 10: |
| // BF16DOTlanev4bf16, BF16DOTlanev8bf16, BFDOT_ZZI, BFMLALB_ZZZI, BFMLALT... |
| printVectorIndex(MI, 4, STI, O); |
| break; |
| case 11: |
| // BFDOT_VG2_M2ZZI_HtoS, BFDOT_VG4_M4ZZI_HtoS, BFMLAL_VG2_M2ZZI_S, BFMLAL... |
| printVectorIndex(MI, 6, STI, O); |
| return; |
| break; |
| case 12: |
| // BFMLA_ZPmZZ, BFMLS_ZPmZZ, FCMLA_ZPmZZ_H, FMAD_ZPmZZ_H, FMLA_ZPmZZ_H, F... |
| printSVERegOp<'h'>(MI, 4, STI, O); |
| break; |
| case 13: |
| // CADD_ZZI_H, SQCADD_ZZI_H |
| printComplexRotationOp<180, 90>(MI, 3, STI, O); |
| return; |
| break; |
| case 14: |
| // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... |
| O << ']'; |
| return; |
| break; |
| case 15: |
| // CDOT_ZZZ_S, CMLA_ZZZ_B, CMLA_ZZZ_H, SQRDCMLAH_ZZZ_B, SQRDCMLAH_ZZZ_H |
| printComplexRotationOp<90, 0>(MI, 4, STI, O); |
| return; |
| break; |
| case 16: |
| // CMPHI_PPzZI_H, CMPHS_PPzZI_H, CMPLO_PPzZI_H, CMPLS_PPzZI_H |
| printImm(MI, 3, STI, O); |
| return; |
| break; |
| case 17: |
| // FADD_ZPmI_H, FSUBR_ZPmI_H, FSUB_ZPmI_H |
| printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::one>(MI, 3, STI, O); |
| return; |
| break; |
| case 18: |
| // FCMEQ_PPzZ0_D, FCMEQ_PPzZ0_S, FCMGE_PPzZ0_D, FCMGE_PPzZ0_S, FCMGT_PPzZ... |
| O << ", #0.0"; |
| return; |
| break; |
| case 19: |
| // FMAXNM_ZPmI_H, FMAX_ZPmI_H, FMINNM_ZPmI_H, FMIN_ZPmI_H |
| printExactFPImm<AArch64ExactFPImm::zero, AArch64ExactFPImm::one>(MI, 3, STI, O); |
| return; |
| break; |
| case 20: |
| // FMULXv1i16_indexed, FMULXv1i32_indexed, FMULXv1i64_indexed, FMULXv2i32... |
| printVectorIndex(MI, 3, STI, O); |
| return; |
| break; |
| case 21: |
| // FMUL_ZPmI_H |
| printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::two>(MI, 3, STI, O); |
| return; |
| break; |
| case 22: |
| // GLD1B_D_REAL, GLD1D_REAL, GLD1H_D_REAL, GLD1SB_D_REAL, GLD1SH_D_REAL, ... |
| printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 23: |
| // GLD1B_D_SXTW_REAL, GLD1D_SXTW_REAL, GLD1H_D_SXTW_REAL, GLD1SB_D_SXTW_R... |
| printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 24: |
| // GLD1B_D_UXTW_REAL, GLD1D_UXTW_REAL, GLD1H_D_UXTW_REAL, GLD1SB_D_UXTW_R... |
| printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 25: |
| // GLD1B_S_SXTW_REAL, GLD1H_S_SXTW_REAL, GLD1SB_S_SXTW_REAL, GLD1SH_S_SXT... |
| printRegWithShiftExtend<true, 8, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 26: |
| // GLD1B_S_UXTW_REAL, GLD1H_S_UXTW_REAL, GLD1SB_S_UXTW_REAL, GLD1SH_S_UXT... |
| printRegWithShiftExtend<false, 8, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 27: |
| // GLD1D_IMM_REAL, GLDFF1D_IMM_REAL, LD1RD_IMM, SST1D_IMM |
| printImmScale<8>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 28: |
| // GLD1D_SCALED_REAL, GLDFF1D_SCALED_REAL, SST1D_SCALED |
| printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 29: |
| // GLD1D_SXTW_SCALED_REAL, GLDFF1D_SXTW_SCALED_REAL, SST1D_SXTW_SCALED |
| printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 30: |
| // GLD1D_UXTW_SCALED_REAL, GLDFF1D_UXTW_SCALED_REAL, SST1D_UXTW_SCALED |
| printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 31: |
| // GLD1H_D_IMM_REAL, GLD1H_S_IMM_REAL, GLD1SH_D_IMM_REAL, GLD1SH_S_IMM_RE... |
| printImmScale<2>(MI, 3, STI, O); |
| break; |
| case 32: |
| // GLD1H_D_SCALED_REAL, GLD1SH_D_SCALED_REAL, GLDFF1H_D_SCALED_REAL, GLDF... |
| printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 33: |
| // GLD1H_D_SXTW_SCALED_REAL, GLD1SH_D_SXTW_SCALED_REAL, GLDFF1H_D_SXTW_SC... |
| printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 34: |
| // GLD1H_D_UXTW_SCALED_REAL, GLD1SH_D_UXTW_SCALED_REAL, GLDFF1H_D_UXTW_SC... |
| printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 35: |
| // GLD1H_S_SXTW_SCALED_REAL, GLD1SH_S_SXTW_SCALED_REAL, GLDFF1H_S_SXTW_SC... |
| printRegWithShiftExtend<true, 16, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 36: |
| // GLD1H_S_UXTW_SCALED_REAL, GLD1SH_S_UXTW_SCALED_REAL, GLDFF1H_S_UXTW_SC... |
| printRegWithShiftExtend<false, 16, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 37: |
| // GLD1SW_D_IMM_REAL, GLD1W_D_IMM_REAL, GLD1W_IMM_REAL, GLDFF1SW_D_IMM_RE... |
| printImmScale<4>(MI, 3, STI, O); |
| break; |
| case 38: |
| // GLD1SW_D_SCALED_REAL, GLD1W_D_SCALED_REAL, GLDFF1SW_D_SCALED_REAL, GLD... |
| printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 39: |
| // GLD1SW_D_SXTW_SCALED_REAL, GLD1W_D_SXTW_SCALED_REAL, GLDFF1SW_D_SXTW_S... |
| printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 40: |
| // GLD1SW_D_UXTW_SCALED_REAL, GLD1W_D_UXTW_SCALED_REAL, GLDFF1SW_D_UXTW_S... |
| printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 41: |
| // GLD1W_SXTW_SCALED_REAL, GLDFF1W_SXTW_SCALED_REAL, SST1W_SXTW_SCALED |
| printRegWithShiftExtend<true, 32, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 42: |
| // GLD1W_UXTW_SCALED_REAL, GLDFF1W_UXTW_SCALED_REAL, SST1W_UXTW_SCALED |
| printRegWithShiftExtend<false, 32, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 43: |
| // LD1B, LD1B_2Z, LD1B_4Z, LD1B_D, LD1B_H, LD1B_S, LD1B_VG4_M4ZPXX, LD1RO... |
| printRegWithShiftExtend<false, 8, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 44: |
| // LD1D, LD1D_2Z, LD1D_4Z, LD1D_Q, LD1D_VG2_M2ZPXX, LD1D_VG4_M4ZPXX, LD1R... |
| printRegWithShiftExtend<false, 64, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 45: |
| // LD1H, LD1H_2Z, LD1H_4Z, LD1H_D, LD1H_S, LD1H_VG4_M4ZPXX, LD1RO_H, LD1R... |
| printRegWithShiftExtend<false, 16, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 46: |
| // LD1RO_B_IMM, LD1RO_D_IMM, LD1RO_H_IMM, LD1RO_W_IMM |
| printImmScale<32>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 47: |
| // LD1RO_W, LD1RQ_W, LD1SW_D, LD1W, LD1W_2Z, LD1W_4Z, LD1W_D, LD1W_Q, LD1... |
| printRegWithShiftExtend<false, 32, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 48: |
| // LD1RQ_B_IMM, LD1RQ_D_IMM, LD1RQ_H_IMM, LD1RQ_W_IMM |
| printImmScale<16>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 49: |
| // LD1_MXIPXX_H_B, LD1_MXIPXX_V_B, ST1_MXIPXX_H_B, ST1_MXIPXX_V_B |
| printRegWithShiftExtend<false, 8, 'x', 0>(MI, 5, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 50: |
| // LD1_MXIPXX_H_D, LD1_MXIPXX_V_D, ST1_MXIPXX_H_D, ST1_MXIPXX_V_D |
| printRegWithShiftExtend<false, 64, 'x', 0>(MI, 5, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 51: |
| // LD1_MXIPXX_H_H, LD1_MXIPXX_V_H, ST1_MXIPXX_H_H, ST1_MXIPXX_V_H |
| printRegWithShiftExtend<false, 16, 'x', 0>(MI, 5, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 52: |
| // LD1_MXIPXX_H_Q, LD1_MXIPXX_V_Q, ST1_MXIPXX_H_Q, ST1_MXIPXX_V_Q |
| printRegWithShiftExtend<false, 128, 'x', 0>(MI, 5, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 53: |
| // LD1_MXIPXX_H_S, LD1_MXIPXX_V_S, ST1_MXIPXX_H_S, ST1_MXIPXX_V_S |
| printRegWithShiftExtend<false, 32, 'x', 0>(MI, 5, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 54: |
| // LD2Q, LD3Q, LD4Q, ST2Q, ST3Q, ST4Q |
| printRegWithShiftExtend<false, 128, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 55: |
| // LD3B_IMM, LD3D_IMM, LD3H_IMM, LD3Q_IMM, LD3W_IMM, ST3B_IMM, ST3D_IMM, ... |
| printImmScale<3>(MI, 3, STI, O); |
| O << ", mul vl]"; |
| return; |
| break; |
| case 56: |
| // LDIAPPWpre |
| O << "], #8"; |
| return; |
| break; |
| case 57: |
| // LDIAPPXpre |
| O << "], #16"; |
| return; |
| break; |
| case 58: |
| // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STGPpost,... |
| O << "], "; |
| break; |
| case 59: |
| // LDRBBpre, LDRBpre, LDRDpre, LDRHHpre, LDRHpre, LDRQpre, LDRSBWpre, LDR... |
| O << "]!"; |
| return; |
| break; |
| case 60: |
| // LDR_PXI, LDR_ZXI, STR_PXI, STR_ZXI |
| O << ", mul vl]"; |
| return; |
| break; |
| case 61: |
| // PSEL_PPPRI_B, PSEL_PPPRI_D, PSEL_PPPRI_H, PSEL_PPPRI_S |
| O << '['; |
| printOperand(MI, 3, STI, O); |
| O << ", "; |
| printMatrixIndex(MI, 4, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 62: |
| // SEL_VG2_2ZP2Z2Z_B, SEL_VG4_4ZP4Z4Z_B |
| printTypedVectorList<0,'b'>(MI, 3, STI, O); |
| return; |
| break; |
| case 63: |
| // SEL_VG2_2ZP2Z2Z_D, SEL_VG4_4ZP4Z4Z_D |
| printTypedVectorList<0,'d'>(MI, 3, STI, O); |
| return; |
| break; |
| case 64: |
| // SEL_VG2_2ZP2Z2Z_H, SEL_VG4_4ZP4Z4Z_H |
| printTypedVectorList<0,'h'>(MI, 3, STI, O); |
| return; |
| break; |
| case 65: |
| // SEL_VG2_2ZP2Z2Z_S, SEL_VG4_4ZP4Z4Z_S |
| printTypedVectorList<0,'s'>(MI, 3, STI, O); |
| return; |
| break; |
| case 66: |
| // STILPWpre |
| O << ", #-8]!"; |
| return; |
| break; |
| case 67: |
| // STILPXpre |
| O << ", #-16]!"; |
| return; |
| break; |
| case 68: |
| // STLXPW, STLXPX, STXPW, STXPX |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| } |
| |
| |
| // Fragment 6 encoded into 6 bits for 42 unique commands. |
| switch ((Bits >> 57) & 63) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ADDG, ASRD_ZPmI_B, ASRD_ZPmI_D, ASRD_ZPmI_S, ASR_ZPmI_B, ASR_ZPmI_D, A... |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 1: |
| // ADDP_ZPmZ_B, ADD_ZPmZ_B, ANDS_PPzPP, AND_PPzPP, AND_ZPmZ_B, ASRR_ZPmZ_... |
| printSVERegOp<'b'>(MI, 3, STI, O); |
| return; |
| break; |
| case 2: |
| // ADDP_ZPmZ_D, ADD_ZPmZ_D, AND_ZPmZ_D, ASRR_ZPmZ_D, ASR_WIDE_ZPmZ_B, ASR... |
| printSVERegOp<'d'>(MI, 3, STI, O); |
| break; |
| case 3: |
| // ADDP_ZPmZ_H, ADD_VG2_M2ZZ_D, ADD_VG2_M2ZZ_S, ADD_VG4_M4ZZ_D, ADD_VG4_M... |
| return; |
| break; |
| case 4: |
| // ADDP_ZPmZ_S, ADD_ZPmZ_S, AND_ZPmZ_S, ASRR_ZPmZ_S, ASR_ZPmZ_S, BIC_ZPmZ... |
| printSVERegOp<'s'>(MI, 3, STI, O); |
| break; |
| case 5: |
| // BCAX, EOR3, SM3SS1 |
| printVRegOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 6: |
| // BFMWri, BFMXri |
| printOperand(MI, 4, STI, O); |
| return; |
| break; |
| case 7: |
| // CADD_ZZI_B, CADD_ZZI_D, CADD_ZZI_S, FCADDv2f32, FCADDv2f64, FCADDv4f16... |
| printComplexRotationOp<180, 90>(MI, 3, STI, O); |
| return; |
| break; |
| case 8: |
| // CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi, CCMPXr, CSELWr... |
| printCondCode(MI, 3, STI, O); |
| return; |
| break; |
| case 9: |
| // CDOT_ZZZI_D, CMLA_ZZZI_S, FCADD_ZPmZ_H, FCMLA_ZPmZZ_H, FCMLA_ZZZI_S, F... |
| O << ", "; |
| break; |
| case 10: |
| // CDOT_ZZZI_S, CMLA_ZZZI_H, FCMLA_ZZZI_H, SQRDCMLAH_ZZZI_H |
| printComplexRotationOp<90, 0>(MI, 5, STI, O); |
| return; |
| break; |
| case 11: |
| // CDOT_ZZZ_D, CMLA_ZZZ_D, CMLA_ZZZ_S, FCMLAv2f32, FCMLAv2f64, FCMLAv4f16... |
| printComplexRotationOp<90, 0>(MI, 4, STI, O); |
| return; |
| break; |
| case 12: |
| // CLASTA_RPZ_H, CLASTA_VPZ_H, CLASTB_RPZ_H, CLASTB_VPZ_H |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| return; |
| break; |
| case 13: |
| // CMPHI_PPzZI_B, CMPHI_PPzZI_D, CMPHI_PPzZI_S, CMPHS_PPzZI_B, CMPHS_PPzZ... |
| printImm(MI, 3, STI, O); |
| return; |
| break; |
| case 14: |
| // FADD_ZPmI_D, FADD_ZPmI_S, FSUBR_ZPmI_D, FSUBR_ZPmI_S, FSUB_ZPmI_D, FSU... |
| printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::one>(MI, 3, STI, O); |
| return; |
| break; |
| case 15: |
| // FCMLA_ZPmZZ_D, FMAD_ZPmZZ_D, FMLA_ZPmZZ_D, FMLS_ZPmZZ_D, FMSB_ZPmZZ_D,... |
| printSVERegOp<'d'>(MI, 4, STI, O); |
| break; |
| case 16: |
| // FCMLA_ZPmZZ_S, FMAD_ZPmZZ_S, FMLA_ZPmZZ_S, FMLS_ZPmZZ_S, FMSB_ZPmZZ_S,... |
| printSVERegOp<'s'>(MI, 4, STI, O); |
| break; |
| case 17: |
| // FMAXNM_ZPmI_D, FMAXNM_ZPmI_S, FMAX_ZPmI_D, FMAX_ZPmI_S, FMINNM_ZPmI_D,... |
| printExactFPImm<AArch64ExactFPImm::zero, AArch64ExactFPImm::one>(MI, 3, STI, O); |
| return; |
| break; |
| case 18: |
| // FMLA_VG2_M2ZZI_D, FMLA_VG2_M2ZZI_S, FMLA_VG4_M4ZZI_D, FMLA_VG4_M4ZZI_S... |
| printVectorIndex(MI, 6, STI, O); |
| return; |
| break; |
| case 19: |
| // FMUL_ZPmI_D, FMUL_ZPmI_S |
| printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::two>(MI, 3, STI, O); |
| return; |
| break; |
| case 20: |
| // GLD1B_D_IMM_REAL, GLD1B_S_IMM_REAL, GLD1H_D_IMM_REAL, GLD1H_S_IMM_REAL... |
| O << ']'; |
| return; |
| break; |
| case 21: |
| // LD1B_2Z_IMM, LD1B_4Z_IMM, LD1B_D_IMM_REAL, LD1B_H_IMM_REAL, LD1B_IMM_R... |
| O << ", mul vl]"; |
| return; |
| break; |
| case 22: |
| // LDNPDi, LDNPXi, LDPDi, LDPXi, STNPDi, STNPXi, STPDi, STPXi |
| printImmScale<8>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 23: |
| // LDNPQi, LDPQi, STGPi, STNPQi, STPQi |
| printImmScale<16>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 24: |
| // LDNPSi, LDNPWi, LDPSWi, LDPSi, LDPWi, STNPSi, STNPWi, STPSi, STPWi |
| printImmScale<4>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 25: |
| // LDPDpost, LDPDpre, LDPXpost, LDPXpre, STPDpost, STPDpre, STPXpost, STP... |
| printImmScale<8>(MI, 4, STI, O); |
| break; |
| case 26: |
| // LDPQpost, LDPQpre, STGPpost, STGPpre, STPQpost, STPQpre |
| printImmScale<16>(MI, 4, STI, O); |
| break; |
| case 27: |
| // LDPSWpost, LDPSWpre, LDPSpost, LDPSpre, LDPWpost, LDPWpre, STPSpost, S... |
| printImmScale<4>(MI, 4, STI, O); |
| break; |
| case 28: |
| // LDRBBroW, LDRBroW, LDRSBWroW, LDRSBXroW, STRBBroW, STRBroW |
| printMemExtend<'w', 8>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 29: |
| // LDRBBroX, LDRBroX, LDRSBWroX, LDRSBXroX, STRBBroX, STRBroX |
| printMemExtend<'x', 8>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 30: |
| // LDRDroW, LDRXroW, PRFMroW, STRDroW, STRXroW |
| printMemExtend<'w', 64>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 31: |
| // LDRDroX, LDRXroX, PRFMroX, STRDroX, STRXroX |
| printMemExtend<'x', 64>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 32: |
| // LDRHHroW, LDRHroW, LDRSHWroW, LDRSHXroW, STRHHroW, STRHroW |
| printMemExtend<'w', 16>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 33: |
| // LDRHHroX, LDRHroX, LDRSHWroX, LDRSHXroX, STRHHroX, STRHroX |
| printMemExtend<'x', 16>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 34: |
| // LDRQroW, STRQroW |
| printMemExtend<'w', 128>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 35: |
| // LDRQroX, STRQroX |
| printMemExtend<'x', 128>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 36: |
| // LDRSWroW, LDRSroW, LDRWroW, STRSroW, STRWroW |
| printMemExtend<'w', 32>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 37: |
| // LDRSWroX, LDRSroX, LDRWroX, STRSroX, STRWroX |
| printMemExtend<'x', 32>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 38: |
| // ST1B_VG2_M2ZPXI, ST1H_VG2_M2ZPXI, STNT1B_VG2_M2ZPXI, STNT1H_VG2_M2ZPXI |
| printImmScale<2>(MI, 3, STI, O); |
| O << ", mul vl]"; |
| return; |
| break; |
| case 39: |
| // ST1B_VG2_M2ZPXX, STNT1B_VG2_M2ZPXX |
| printRegWithShiftExtend<false, 8, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 40: |
| // ST1H_VG2_M2ZPXX, STNT1H_VG2_M2ZPXX |
| printRegWithShiftExtend<false, 16, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 41: |
| // WHILEGE_CXX_B, WHILEGE_CXX_D, WHILEGE_CXX_H, WHILEGE_CXX_S, WHILEGT_CX... |
| printSVEVecLenSpecifier(MI, 3, STI, O); |
| return; |
| break; |
| } |
| |
| switch (MI->getOpcode()) { |
| default: llvm_unreachable("Unexpected opcode."); |
| case AArch64::ADDP_ZPmZ_D: |
| case AArch64::ADDP_ZPmZ_S: |
| case AArch64::ADD_ZPmZ_D: |
| case AArch64::ADD_ZPmZ_S: |
| case AArch64::AND_ZPmZ_D: |
| case AArch64::AND_ZPmZ_S: |
| case AArch64::ASRR_ZPmZ_D: |
| case AArch64::ASRR_ZPmZ_S: |
| case AArch64::ASR_WIDE_ZPmZ_B: |
| case AArch64::ASR_WIDE_ZPmZ_S: |
| case AArch64::ASR_ZPmZ_D: |
| case AArch64::ASR_ZPmZ_S: |
| case AArch64::BCAX_ZZZZ: |
| case AArch64::BIC_ZPmZ_D: |
| case AArch64::BIC_ZPmZ_S: |
| case AArch64::BSL1N_ZZZZ: |
| case AArch64::BSL2N_ZZZZ: |
| case AArch64::BSL_ZZZZ: |
| case AArch64::CLASTA_RPZ_D: |
| case AArch64::CLASTA_RPZ_S: |
| case AArch64::CLASTA_VPZ_D: |
| case AArch64::CLASTA_VPZ_S: |
| case AArch64::CLASTA_ZPZ_D: |
| case AArch64::CLASTA_ZPZ_S: |
| case AArch64::CLASTB_RPZ_D: |
| case AArch64::CLASTB_RPZ_S: |
| case AArch64::CLASTB_VPZ_D: |
| case AArch64::CLASTB_VPZ_S: |
| case AArch64::CLASTB_ZPZ_D: |
| case AArch64::CLASTB_ZPZ_S: |
| case AArch64::CMPEQ_PPzZZ_D: |
| case AArch64::CMPEQ_PPzZZ_S: |
| case AArch64::CMPEQ_WIDE_PPzZZ_B: |
| case AArch64::CMPEQ_WIDE_PPzZZ_S: |
| case AArch64::CMPGE_PPzZZ_D: |
| case AArch64::CMPGE_PPzZZ_S: |
| case AArch64::CMPGE_WIDE_PPzZZ_B: |
| case AArch64::CMPGE_WIDE_PPzZZ_S: |
| case AArch64::CMPGT_PPzZZ_D: |
| case AArch64::CMPGT_PPzZZ_S: |
| case AArch64::CMPGT_WIDE_PPzZZ_B: |
| case AArch64::CMPGT_WIDE_PPzZZ_S: |
| case AArch64::CMPHI_PPzZZ_D: |
| case AArch64::CMPHI_PPzZZ_S: |
| case AArch64::CMPHI_WIDE_PPzZZ_B: |
| case AArch64::CMPHI_WIDE_PPzZZ_S: |
| case AArch64::CMPHS_PPzZZ_D: |
| case AArch64::CMPHS_PPzZZ_S: |
| case AArch64::CMPHS_WIDE_PPzZZ_B: |
| case AArch64::CMPHS_WIDE_PPzZZ_S: |
| case AArch64::CMPLE_WIDE_PPzZZ_B: |
| case AArch64::CMPLE_WIDE_PPzZZ_S: |
| case AArch64::CMPLO_WIDE_PPzZZ_B: |
| case AArch64::CMPLO_WIDE_PPzZZ_S: |
| case AArch64::CMPLS_WIDE_PPzZZ_B: |
| case AArch64::CMPLS_WIDE_PPzZZ_S: |
| case AArch64::CMPLT_WIDE_PPzZZ_B: |
| case AArch64::CMPLT_WIDE_PPzZZ_S: |
| case AArch64::CMPNE_PPzZZ_D: |
| case AArch64::CMPNE_PPzZZ_S: |
| case AArch64::CMPNE_WIDE_PPzZZ_B: |
| case AArch64::CMPNE_WIDE_PPzZZ_S: |
| case AArch64::EOR3_ZZZZ: |
| case AArch64::EOR_ZPmZ_D: |
| case AArch64::EOR_ZPmZ_S: |
| case AArch64::FABD_ZPmZ_D: |
| case AArch64::FABD_ZPmZ_S: |
| case AArch64::FACGE_PPzZZ_D: |
| case AArch64::FACGE_PPzZZ_S: |
| case AArch64::FACGT_PPzZZ_D: |
| case AArch64::FACGT_PPzZZ_S: |
| case AArch64::FADDP_ZPmZZ_D: |
| case AArch64::FADDP_ZPmZZ_S: |
| case AArch64::FADD_ZPmZ_D: |
| case AArch64::FADD_ZPmZ_S: |
| case AArch64::FCMEQ_PPzZZ_D: |
| case AArch64::FCMEQ_PPzZZ_S: |
| case AArch64::FCMGE_PPzZZ_D: |
| case AArch64::FCMGE_PPzZZ_S: |
| case AArch64::FCMGT_PPzZZ_D: |
| case AArch64::FCMGT_PPzZZ_S: |
| case AArch64::FCMNE_PPzZZ_D: |
| case AArch64::FCMNE_PPzZZ_S: |
| case AArch64::FCMUO_PPzZZ_D: |
| case AArch64::FCMUO_PPzZZ_S: |
| case AArch64::FDIVR_ZPmZ_D: |
| case AArch64::FDIVR_ZPmZ_S: |
| case AArch64::FDIV_ZPmZ_D: |
| case AArch64::FDIV_ZPmZ_S: |
| case AArch64::FMAD_ZPmZZ_D: |
| case AArch64::FMAD_ZPmZZ_S: |
| case AArch64::FMAXNMP_ZPmZZ_D: |
| case AArch64::FMAXNMP_ZPmZZ_S: |
| case AArch64::FMAXNM_ZPmZ_D: |
| case AArch64::FMAXNM_ZPmZ_S: |
| case AArch64::FMAXP_ZPmZZ_D: |
| case AArch64::FMAXP_ZPmZZ_S: |
| case AArch64::FMAX_ZPmZ_D: |
| case AArch64::FMAX_ZPmZ_S: |
| case AArch64::FMINNMP_ZPmZZ_D: |
| case AArch64::FMINNMP_ZPmZZ_S: |
| case AArch64::FMINNM_ZPmZ_D: |
| case AArch64::FMINNM_ZPmZ_S: |
| case AArch64::FMINP_ZPmZZ_D: |
| case AArch64::FMINP_ZPmZZ_S: |
| case AArch64::FMIN_ZPmZ_D: |
| case AArch64::FMIN_ZPmZ_S: |
| case AArch64::FMLA_ZPmZZ_D: |
| case AArch64::FMLA_ZPmZZ_S: |
| case AArch64::FMLS_ZPmZZ_D: |
| case AArch64::FMLS_ZPmZZ_S: |
| case AArch64::FMSB_ZPmZZ_D: |
| case AArch64::FMSB_ZPmZZ_S: |
| case AArch64::FMULX_ZPmZ_D: |
| case AArch64::FMULX_ZPmZ_S: |
| case AArch64::FMUL_ZPmZ_D: |
| case AArch64::FMUL_ZPmZ_S: |
| case AArch64::FNMAD_ZPmZZ_D: |
| case AArch64::FNMAD_ZPmZZ_S: |
| case AArch64::FNMLA_ZPmZZ_D: |
| case AArch64::FNMLA_ZPmZZ_S: |
| case AArch64::FNMLS_ZPmZZ_D: |
| case AArch64::FNMLS_ZPmZZ_S: |
| case AArch64::FNMSB_ZPmZZ_D: |
| case AArch64::FNMSB_ZPmZZ_S: |
| case AArch64::FSCALE_ZPmZ_D: |
| case AArch64::FSCALE_ZPmZ_S: |
| case AArch64::FSUBR_ZPmZ_D: |
| case AArch64::FSUBR_ZPmZ_S: |
| case AArch64::FSUB_ZPmZ_D: |
| case AArch64::FSUB_ZPmZ_S: |
| case AArch64::HISTCNT_ZPzZZ_D: |
| case AArch64::HISTCNT_ZPzZZ_S: |
| case AArch64::LDPDpost: |
| case AArch64::LDPQpost: |
| case AArch64::LDPSWpost: |
| case AArch64::LDPSpost: |
| case AArch64::LDPWpost: |
| case AArch64::LDPXpost: |
| case AArch64::LSLR_ZPmZ_D: |
| case AArch64::LSLR_ZPmZ_S: |
| case AArch64::LSL_WIDE_ZPmZ_B: |
| case AArch64::LSL_WIDE_ZPmZ_S: |
| case AArch64::LSL_ZPmZ_D: |
| case AArch64::LSL_ZPmZ_S: |
| case AArch64::LSRR_ZPmZ_D: |
| case AArch64::LSRR_ZPmZ_S: |
| case AArch64::LSR_WIDE_ZPmZ_B: |
| case AArch64::LSR_WIDE_ZPmZ_S: |
| case AArch64::LSR_ZPmZ_D: |
| case AArch64::LSR_ZPmZ_S: |
| case AArch64::MAD_ZPmZZ_D: |
| case AArch64::MAD_ZPmZZ_S: |
| case AArch64::MLA_ZPmZZ_D: |
| case AArch64::MLA_ZPmZZ_S: |
| case AArch64::MLS_ZPmZZ_D: |
| case AArch64::MLS_ZPmZZ_S: |
| case AArch64::MSB_ZPmZZ_D: |
| case AArch64::MSB_ZPmZZ_S: |
| case AArch64::MUL_ZPmZ_D: |
| case AArch64::MUL_ZPmZ_S: |
| case AArch64::NBSL_ZZZZ: |
| case AArch64::ORR_ZPmZ_D: |
| case AArch64::ORR_ZPmZ_S: |
| case AArch64::SABD_ZPmZ_D: |
| case AArch64::SABD_ZPmZ_S: |
| case AArch64::SDIVR_ZPmZ_D: |
| case AArch64::SDIVR_ZPmZ_S: |
| case AArch64::SDIV_ZPmZ_D: |
| case AArch64::SDIV_ZPmZ_S: |
| case AArch64::SEL_ZPZZ_D: |
| case AArch64::SEL_ZPZZ_S: |
| case AArch64::SHADD_ZPmZ_D: |
| case AArch64::SHADD_ZPmZ_S: |
| case AArch64::SHSUBR_ZPmZ_D: |
| case AArch64::SHSUBR_ZPmZ_S: |
| case AArch64::SHSUB_ZPmZ_D: |
| case AArch64::SHSUB_ZPmZ_S: |
| case AArch64::SMAXP_ZPmZ_D: |
| case AArch64::SMAXP_ZPmZ_S: |
| case AArch64::SMAX_ZPmZ_D: |
| case AArch64::SMAX_ZPmZ_S: |
| case AArch64::SMINP_ZPmZ_D: |
| case AArch64::SMINP_ZPmZ_S: |
| case AArch64::SMIN_ZPmZ_D: |
| case AArch64::SMIN_ZPmZ_S: |
| case AArch64::SMULH_ZPmZ_D: |
| case AArch64::SMULH_ZPmZ_S: |
| case AArch64::SPLICE_ZPZ_D: |
| case AArch64::SPLICE_ZPZ_S: |
| case AArch64::SQADD_ZPmZ_D: |
| case AArch64::SQADD_ZPmZ_S: |
| case AArch64::SQRSHLR_ZPmZ_D: |
| case AArch64::SQRSHLR_ZPmZ_S: |
| case AArch64::SQRSHL_ZPmZ_D: |
| case AArch64::SQRSHL_ZPmZ_S: |
| case AArch64::SQSHLR_ZPmZ_D: |
| case AArch64::SQSHLR_ZPmZ_S: |
| case AArch64::SQSHL_ZPmZ_D: |
| case AArch64::SQSHL_ZPmZ_S: |
| case AArch64::SQSUBR_ZPmZ_D: |
| case AArch64::SQSUBR_ZPmZ_S: |
| case AArch64::SQSUB_ZPmZ_D: |
| case AArch64::SQSUB_ZPmZ_S: |
| case AArch64::SRHADD_ZPmZ_D: |
| case AArch64::SRHADD_ZPmZ_S: |
| case AArch64::SRSHLR_ZPmZ_D: |
| case AArch64::SRSHLR_ZPmZ_S: |
| case AArch64::SRSHL_ZPmZ_D: |
| case AArch64::SRSHL_ZPmZ_S: |
| case AArch64::STGPpost: |
| case AArch64::STPDpost: |
| case AArch64::STPQpost: |
| case AArch64::STPSpost: |
| case AArch64::STPWpost: |
| case AArch64::STPXpost: |
| case AArch64::SUBR_ZPmZ_D: |
| case AArch64::SUBR_ZPmZ_S: |
| case AArch64::SUB_ZPmZ_D: |
| case AArch64::SUB_ZPmZ_S: |
| case AArch64::SUQADD_ZPmZ_D: |
| case AArch64::SUQADD_ZPmZ_S: |
| case AArch64::UABD_ZPmZ_D: |
| case AArch64::UABD_ZPmZ_S: |
| case AArch64::UDIVR_ZPmZ_D: |
| case AArch64::UDIVR_ZPmZ_S: |
| case AArch64::UDIV_ZPmZ_D: |
| case AArch64::UDIV_ZPmZ_S: |
| case AArch64::UHADD_ZPmZ_D: |
| case AArch64::UHADD_ZPmZ_S: |
| case AArch64::UHSUBR_ZPmZ_D: |
| case AArch64::UHSUBR_ZPmZ_S: |
| case AArch64::UHSUB_ZPmZ_D: |
| case AArch64::UHSUB_ZPmZ_S: |
| case AArch64::UMAXP_ZPmZ_D: |
| case AArch64::UMAXP_ZPmZ_S: |
| case AArch64::UMAX_ZPmZ_D: |
| case AArch64::UMAX_ZPmZ_S: |
| case AArch64::UMINP_ZPmZ_D: |
| case AArch64::UMINP_ZPmZ_S: |
| case AArch64::UMIN_ZPmZ_D: |
| case AArch64::UMIN_ZPmZ_S: |
| case AArch64::UMULH_ZPmZ_D: |
| case AArch64::UMULH_ZPmZ_S: |
| case AArch64::UQADD_ZPmZ_D: |
| case AArch64::UQADD_ZPmZ_S: |
| case AArch64::UQRSHLR_ZPmZ_D: |
| case AArch64::UQRSHLR_ZPmZ_S: |
| case AArch64::UQRSHL_ZPmZ_D: |
| case AArch64::UQRSHL_ZPmZ_S: |
| case AArch64::UQSHLR_ZPmZ_D: |
| case AArch64::UQSHLR_ZPmZ_S: |
| case AArch64::UQSHL_ZPmZ_D: |
| case AArch64::UQSHL_ZPmZ_S: |
| case AArch64::UQSUBR_ZPmZ_D: |
| case AArch64::UQSUBR_ZPmZ_S: |
| case AArch64::UQSUB_ZPmZ_D: |
| case AArch64::UQSUB_ZPmZ_S: |
| case AArch64::URHADD_ZPmZ_D: |
| case AArch64::URHADD_ZPmZ_S: |
| case AArch64::URSHLR_ZPmZ_D: |
| case AArch64::URSHLR_ZPmZ_S: |
| case AArch64::URSHL_ZPmZ_D: |
| case AArch64::URSHL_ZPmZ_S: |
| case AArch64::USQADD_ZPmZ_D: |
| case AArch64::USQADD_ZPmZ_S: |
| return; |
| break; |
| case AArch64::CDOT_ZZZI_D: |
| case AArch64::CMLA_ZZZI_S: |
| case AArch64::FCADD_ZPmZ_H: |
| case AArch64::FCMLA_ZPmZZ_H: |
| case AArch64::FCMLA_ZZZI_S: |
| case AArch64::FCMLAv4f16_indexed: |
| case AArch64::FCMLAv4f32_indexed: |
| case AArch64::FCMLAv8f16_indexed: |
| case AArch64::LDPDpre: |
| case AArch64::LDPQpre: |
| case AArch64::LDPSWpre: |
| case AArch64::LDPSpre: |
| case AArch64::LDPWpre: |
| case AArch64::LDPXpre: |
| case AArch64::SQRDCMLAH_ZZZI_S: |
| case AArch64::STGPpre: |
| case AArch64::STPDpre: |
| case AArch64::STPQpre: |
| case AArch64::STPSpre: |
| case AArch64::STPWpre: |
| case AArch64::STPXpre: |
| switch (MI->getOpcode()) { |
| default: llvm_unreachable("Unexpected opcode."); |
| case AArch64::CDOT_ZZZI_D: |
| case AArch64::CMLA_ZZZI_S: |
| case AArch64::FCMLA_ZPmZZ_H: |
| case AArch64::FCMLA_ZZZI_S: |
| case AArch64::FCMLAv4f16_indexed: |
| case AArch64::FCMLAv4f32_indexed: |
| case AArch64::FCMLAv8f16_indexed: |
| case AArch64::SQRDCMLAH_ZZZI_S: |
| printComplexRotationOp<90, 0>(MI, 5, STI, O); |
| break; |
| case AArch64::FCADD_ZPmZ_H: |
| printComplexRotationOp<180, 90>(MI, 4, STI, O); |
| break; |
| case AArch64::LDPDpre: |
| case AArch64::LDPQpre: |
| case AArch64::LDPSWpre: |
| case AArch64::LDPSpre: |
| case AArch64::LDPWpre: |
| case AArch64::LDPXpre: |
| case AArch64::STGPpre: |
| case AArch64::STPDpre: |
| case AArch64::STPQpre: |
| case AArch64::STPSpre: |
| case AArch64::STPWpre: |
| case AArch64::STPXpre: |
| O << "]!"; |
| break; |
| } |
| return; |
| break; |
| case AArch64::FCADD_ZPmZ_D: |
| case AArch64::FCADD_ZPmZ_S: |
| case AArch64::FCMLA_ZPmZZ_D: |
| case AArch64::FCMLA_ZPmZZ_S: |
| O << ", "; |
| switch (MI->getOpcode()) { |
| default: llvm_unreachable("Unexpected opcode."); |
| case AArch64::FCADD_ZPmZ_D: |
| case AArch64::FCADD_ZPmZ_S: |
| printComplexRotationOp<180, 90>(MI, 4, STI, O); |
| break; |
| case AArch64::FCMLA_ZPmZZ_D: |
| case AArch64::FCMLA_ZPmZZ_S: |
| printComplexRotationOp<90, 0>(MI, 5, STI, O); |
| break; |
| } |
| return; |
| break; |
| } |
| } |
| |
| |
| /// getRegisterName - This method is automatically generated by tblgen |
| /// from the register set description. This returns the assembler name |
| /// for the specified register. |
| const char *AArch64AppleInstPrinter:: |
| getRegisterName(MCRegister Reg, unsigned AltIdx) { |
| unsigned RegNo = Reg.id(); |
| assert(RegNo && RegNo < 716 && "Invalid register number!"); |
| |
| |
| #ifdef __GNUC__ |
| #pragma GCC diagnostic push |
| #pragma GCC diagnostic ignored "-Woverlength-strings" |
| #endif |
| static const char AsmStrsNoRegAltName[] = { |
| /* 0 */ "D7_D8_D9_D10\0" |
| /* 13 */ "P9_P10\0" |
| /* 20 */ "Q7_Q8_Q9_Q10\0" |
| /* 33 */ "Z2_Z10\0" |
| /* 40 */ "Z7_Z8_Z9_Z10\0" |
| /* 53 */ "b10\0" |
| /* 57 */ "d10\0" |
| /* 61 */ "h10\0" |
| /* 65 */ "p10\0" |
| /* 69 */ "q10\0" |
| /* 73 */ "s10\0" |
| /* 77 */ "w10\0" |
| /* 81 */ "x10\0" |
| /* 85 */ "z10\0" |
| /* 89 */ "D17_D18_D19_D20\0" |
| /* 105 */ "Q17_Q18_Q19_Q20\0" |
| /* 121 */ "Z17_Z18_Z19_Z20\0" |
| /* 137 */ "b20\0" |
| /* 141 */ "d20\0" |
| /* 145 */ "h20\0" |
| /* 149 */ "q20\0" |
| /* 153 */ "s20\0" |
| /* 157 */ "w20\0" |
| /* 161 */ "x20\0" |
| /* 165 */ "z20\0" |
| /* 169 */ "D27_D28_D29_D30\0" |
| /* 185 */ "Q27_Q28_Q29_Q30\0" |
| /* 201 */ "Z22_Z30\0" |
| /* 209 */ "Z18_Z22_Z26_Z30\0" |
| /* 225 */ "Z27_Z28_Z29_Z30\0" |
| /* 241 */ "b30\0" |
| /* 245 */ "d30\0" |
| /* 249 */ "h30\0" |
| /* 253 */ "q30\0" |
| /* 257 */ "s30\0" |
| /* 261 */ "w30\0" |
| /* 265 */ "x30\0" |
| /* 269 */ "z30\0" |
| /* 273 */ "D29_D30_D31_D0\0" |
| /* 288 */ "P15_P0\0" |
| /* 295 */ "Q29_Q30_Q31_Q0\0" |
| /* 310 */ "Z29_Z30_Z31_Z0\0" |
| /* 325 */ "b0\0" |
| /* 328 */ "d0\0" |
| /* 331 */ "h0\0" |
| /* 334 */ "p0\0" |
| /* 337 */ "q0\0" |
| /* 340 */ "s0\0" |
| /* 343 */ "zt0\0" |
| /* 347 */ "w0\0" |
| /* 350 */ "x0\0" |
| /* 353 */ "z0\0" |
| /* 356 */ "D8_D9_D10_D11\0" |
| /* 370 */ "P10_P11\0" |
| /* 378 */ "Q8_Q9_Q10_Q11\0" |
| /* 392 */ "W10_W11\0" |
| /* 400 */ "X4_X5_X6_X7_X8_X9_X10_X11\0" |
| /* 426 */ "Z8_Z9_Z10_Z11\0" |
| /* 440 */ "Z3_Z11\0" |
| /* 447 */ "b11\0" |
| /* 451 */ "d11\0" |
| /* 455 */ "h11\0" |
| /* 459 */ "p11\0" |
| /* 463 */ "q11\0" |
| /* 467 */ "s11\0" |
| /* 471 */ "w11\0" |
| /* 475 */ "x11\0" |
| /* 479 */ "z11\0" |
| /* 483 */ "D18_D19_D20_D21\0" |
| /* 499 */ "Q18_Q19_Q20_Q21\0" |
| /* 515 */ "W20_W21\0" |
| /* 523 */ "X14_X15_X16_X17_X18_X19_X20_X21\0" |
| /* 555 */ "Z18_Z19_Z20_Z21\0" |
| /* 571 */ "b21\0" |
| /* 575 */ "d21\0" |
| /* 579 */ "h21\0" |
| /* 583 */ "q21\0" |
| /* 587 */ "s21\0" |
| /* 591 */ "w21\0" |
| /* 595 */ "x21\0" |
| /* 599 */ "z21\0" |
| /* 603 */ "D28_D29_D30_D31\0" |
| /* 619 */ "Q28_Q29_Q30_Q31\0" |
| /* 635 */ "Z28_Z29_Z30_Z31\0" |
| /* 651 */ "Z23_Z31\0" |
| /* 659 */ "Z19_Z23_Z27_Z31\0" |
| /* 675 */ "b31\0" |
| /* 679 */ "d31\0" |
| /* 683 */ "h31\0" |
| /* 687 */ "q31\0" |
| /* 691 */ "s31\0" |
| /* 695 */ "z31\0" |
| /* 699 */ "D30_D31_D0_D1\0" |
| /* 713 */ "P0_P1\0" |
| /* 719 */ "Q30_Q31_Q0_Q1\0" |
| /* 733 */ "W0_W1\0" |
| /* 739 */ "X0_X1\0" |
| /* 745 */ "Z30_Z31_Z0_Z1\0" |
| /* 759 */ "b1\0" |
| /* 762 */ "d1\0" |
| /* 765 */ "h1\0" |
| /* 768 */ "p1\0" |
| /* 771 */ "q1\0" |
| /* 774 */ "s1\0" |
| /* 777 */ "w1\0" |
| /* 780 */ "x1\0" |
| /* 783 */ "z1\0" |
| /* 786 */ "D9_D10_D11_D12\0" |
| /* 801 */ "P11_P12\0" |
| /* 809 */ "Q9_Q10_Q11_Q12\0" |
| /* 824 */ "Z9_Z10_Z11_Z12\0" |
| /* 839 */ "Z4_Z12\0" |
| /* 846 */ "Z0_Z4_Z8_Z12\0" |
| /* 859 */ "b12\0" |
| /* 863 */ "d12\0" |
| /* 867 */ "h12\0" |
| /* 871 */ "p12\0" |
| /* 875 */ "q12\0" |
| /* 879 */ "s12\0" |
| /* 883 */ "w12\0" |
| /* 887 */ "x12\0" |
| /* 891 */ "z12\0" |
| /* 895 */ "D19_D20_D21_D22\0" |
| /* 911 */ "Q19_Q20_Q21_Q22\0" |
| /* 927 */ "Z19_Z20_Z21_Z22\0" |
| /* 943 */ "b22\0" |
| /* 947 */ "d22\0" |
| /* 951 */ "h22\0" |
| /* 955 */ "q22\0" |
| /* 959 */ "s22\0" |
| /* 963 */ "w22\0" |
| /* 967 */ "x22\0" |
| /* 971 */ "z22\0" |
| /* 975 */ "D31_D0_D1_D2\0" |
| /* 988 */ "P1_P2\0" |
| /* 994 */ "Q31_Q0_Q1_Q2\0" |
| /* 1007 */ "Z31_Z0_Z1_Z2\0" |
| /* 1020 */ "b2\0" |
| /* 1023 */ "d2\0" |
| /* 1026 */ "h2\0" |
| /* 1029 */ "p2\0" |
| /* 1032 */ "q2\0" |
| /* 1035 */ "s2\0" |
| /* 1038 */ "w2\0" |
| /* 1041 */ "x2\0" |
| /* 1044 */ "z2\0" |
| /* 1047 */ "D10_D11_D12_D13\0" |
| /* 1063 */ "P12_P13\0" |
| /* 1071 */ "Q10_Q11_Q12_Q13\0" |
| /* 1087 */ "W12_W13\0" |
| /* 1095 */ "X6_X7_X8_X9_X10_X11_X12_X13\0" |
| /* 1123 */ "Z10_Z11_Z12_Z13\0" |
| /* 1139 */ "Z5_Z13\0" |
| /* 1146 */ "Z1_Z5_Z9_Z13\0" |
| /* 1159 */ "b13\0" |
| /* 1163 */ "d13\0" |
| /* 1167 */ "h13\0" |
| /* 1171 */ "p13\0" |
| /* 1175 */ "q13\0" |
| /* 1179 */ "s13\0" |
| /* 1183 */ "w13\0" |
| /* 1187 */ "x13\0" |
| /* 1191 */ "z13\0" |
| /* 1195 */ "D20_D21_D22_D23\0" |
| /* 1211 */ "Q20_Q21_Q22_Q23\0" |
| /* 1227 */ "W22_W23\0" |
| /* 1235 */ "X16_X17_X18_X19_X20_X21_X22_X23\0" |
| /* 1267 */ "Z20_Z21_Z22_Z23\0" |
| /* 1283 */ "b23\0" |
| /* 1287 */ "d23\0" |
| /* 1291 */ "h23\0" |
| /* 1295 */ "q23\0" |
| /* 1299 */ "s23\0" |
| /* 1303 */ "w23\0" |
| /* 1307 */ "x23\0" |
| /* 1311 */ "z23\0" |
| /* 1315 */ "D0_D1_D2_D3\0" |
| /* 1327 */ "P2_P3\0" |
| /* 1333 */ "Q0_Q1_Q2_Q3\0" |
| /* 1345 */ "W2_W3\0" |
| /* 1351 */ "X2_X3\0" |
| /* 1357 */ "Z0_Z1_Z2_Z3\0" |
| /* 1369 */ "b3\0" |
| /* 1372 */ "d3\0" |
| /* 1375 */ "h3\0" |
| /* 1378 */ "p3\0" |
| /* 1381 */ "q3\0" |
| /* 1384 */ "s3\0" |
| /* 1387 */ "w3\0" |
| /* 1390 */ "x3\0" |
| /* 1393 */ "z3\0" |
| /* 1396 */ "D11_D12_D13_D14\0" |
| /* 1412 */ "P13_P14\0" |
| /* 1420 */ "Q11_Q12_Q13_Q14\0" |
| /* 1436 */ "Z2_Z6_Z10_Z14\0" |
| /* 1450 */ "Z11_Z12_Z13_Z14\0" |
| /* 1466 */ "Z6_Z14\0" |
| /* 1473 */ "b14\0" |
| /* 1477 */ "d14\0" |
| /* 1481 */ "h14\0" |
| /* 1485 */ "p14\0" |
| /* 1489 */ "q14\0" |
| /* 1493 */ "s14\0" |
| /* 1497 */ "w14\0" |
| /* 1501 */ "x14\0" |
| /* 1505 */ "z14\0" |
| /* 1509 */ "D21_D22_D23_D24\0" |
| /* 1525 */ "Q21_Q22_Q23_Q24\0" |
| /* 1541 */ "Z21_Z22_Z23_Z24\0" |
| /* 1557 */ "Z16_Z24\0" |
| /* 1565 */ "b24\0" |
| /* 1569 */ "d24\0" |
| /* 1573 */ "h24\0" |
| /* 1577 */ "q24\0" |
| /* 1581 */ "s24\0" |
| /* 1585 */ "w24\0" |
| /* 1589 */ "x24\0" |
| /* 1593 */ "z24\0" |
| /* 1597 */ "D1_D2_D3_D4\0" |
| /* 1609 */ "P3_P4\0" |
| /* 1615 */ "Q1_Q2_Q3_Q4\0" |
| /* 1627 */ "Z1_Z2_Z3_Z4\0" |
| /* 1639 */ "b4\0" |
| /* 1642 */ "d4\0" |
| /* 1645 */ "h4\0" |
| /* 1648 */ "p4\0" |
| /* 1651 */ "q4\0" |
| /* 1654 */ "s4\0" |
| /* 1657 */ "w4\0" |
| /* 1660 */ "x4\0" |
| /* 1663 */ "z4\0" |
| /* 1666 */ "D12_D13_D14_D15\0" |
| /* 1682 */ "P14_P15\0" |
| /* 1690 */ "Q12_Q13_Q14_Q15\0" |
| /* 1706 */ "W14_W15\0" |
| /* 1714 */ "X8_X9_X10_X11_X12_X13_X14_X15\0" |
| /* 1744 */ "Z3_Z7_Z11_Z15\0" |
| /* 1758 */ "Z12_Z13_Z14_Z15\0" |
| /* 1774 */ "Z7_Z15\0" |
| /* 1781 */ "b15\0" |
| /* 1785 */ "d15\0" |
| /* 1789 */ "h15\0" |
| /* 1793 */ "p15\0" |
| /* 1797 */ "q15\0" |
| /* 1801 */ "s15\0" |
| /* 1805 */ "w15\0" |
| /* 1809 */ "x15\0" |
| /* 1813 */ "z15\0" |
| /* 1817 */ "D22_D23_D24_D25\0" |
| /* 1833 */ "Q22_Q23_Q24_Q25\0" |
| /* 1849 */ "W24_W25\0" |
| /* 1857 */ "X18_X19_X20_X21_X22_X23_X24_X25\0" |
| /* 1889 */ "Z22_Z23_Z24_Z25\0" |
| /* 1905 */ "Z17_Z25\0" |
| /* 1913 */ "b25\0" |
| /* 1917 */ "d25\0" |
| /* 1921 */ "h25\0" |
| /* 1925 */ "q25\0" |
| /* 1929 */ "s25\0" |
| /* 1933 */ "w25\0" |
| /* 1937 */ "x25\0" |
| /* 1941 */ "z25\0" |
| /* 1945 */ "D2_D3_D4_D5\0" |
| /* 1957 */ "P4_P5\0" |
| /* 1963 */ "Q2_Q3_Q4_Q5\0" |
| /* 1975 */ "W4_W5\0" |
| /* 1981 */ "X4_X5\0" |
| /* 1987 */ "Z2_Z3_Z4_Z5\0" |
| /* 1999 */ "b5\0" |
| /* 2002 */ "d5\0" |
| /* 2005 */ "h5\0" |
| /* 2008 */ "p5\0" |
| /* 2011 */ "q5\0" |
| /* 2014 */ "s5\0" |
| /* 2017 */ "w5\0" |
| /* 2020 */ "x5\0" |
| /* 2023 */ "z5\0" |
| /* 2026 */ "D13_D14_D15_D16\0" |
| /* 2042 */ "Q13_Q14_Q15_Q16\0" |
| /* 2058 */ "Z13_Z14_Z15_Z16\0" |
| /* 2074 */ "b16\0" |
| /* 2078 */ "d16\0" |
| /* 2082 */ "h16\0" |
| /* 2086 */ "q16\0" |
| /* 2090 */ "s16\0" |
| /* 2094 */ "w16\0" |
| /* 2098 */ "x16\0" |
| /* 2102 */ "z16\0" |
| /* 2106 */ "D23_D24_D25_D26\0" |
| /* 2122 */ "Q23_Q24_Q25_Q26\0" |
| /* 2138 */ "Z23_Z24_Z25_Z26\0" |
| /* 2154 */ "Z18_Z26\0" |
| /* 2162 */ "b26\0" |
| /* 2166 */ "d26\0" |
| /* 2170 */ "h26\0" |
| /* 2174 */ "q26\0" |
| /* 2178 */ "s26\0" |
| /* 2182 */ "w26\0" |
| /* 2186 */ "x26\0" |
| /* 2190 */ "z26\0" |
| /* 2194 */ "D3_D4_D5_D6\0" |
| /* 2206 */ "P5_P6\0" |
| /* 2212 */ "Q3_Q4_Q5_Q6\0" |
| /* 2224 */ "Z3_Z4_Z5_Z6\0" |
| /* 2236 */ "b6\0" |
| /* 2239 */ "d6\0" |
| /* 2242 */ "h6\0" |
| /* 2245 */ "p6\0" |
| /* 2248 */ "q6\0" |
| /* 2251 */ "s6\0" |
| /* 2254 */ "w6\0" |
| /* 2257 */ "x6\0" |
| /* 2260 */ "z6\0" |
| /* 2263 */ "D14_D15_D16_D17\0" |
| /* 2279 */ "Q14_Q15_Q16_Q17\0" |
| /* 2295 */ "W16_W17\0" |
| /* 2303 */ "X10_X11_X12_X13_X14_X15_X16_X17\0" |
| /* 2335 */ "Z14_Z15_Z16_Z17\0" |
| /* 2351 */ "b17\0" |
| /* 2355 */ "d17\0" |
| /* 2359 */ "h17\0" |
| /* 2363 */ "q17\0" |
| /* 2367 */ "s17\0" |
| /* 2371 */ "w17\0" |
| /* 2375 */ "x17\0" |
| /* 2379 */ "z17\0" |
| /* 2383 */ "D24_D25_D26_D27\0" |
| /* 2399 */ "Q24_Q25_Q26_Q27\0" |
| /* 2415 */ "W26_W27\0" |
| /* 2423 */ "X20_X21_X22_X23_X24_X25_X26_X27\0" |
| /* 2455 */ "Z24_Z25_Z26_Z27\0" |
| /* 2471 */ "Z19_Z27\0" |
| /* 2479 */ "b27\0" |
| /* 2483 */ "d27\0" |
| /* 2487 */ "h27\0" |
| /* 2491 */ "q27\0" |
| /* 2495 */ "s27\0" |
| /* 2499 */ "w27\0" |
| /* 2503 */ "x27\0" |
| /* 2507 */ "z27\0" |
| /* 2511 */ "D4_D5_D6_D7\0" |
| /* 2523 */ "P6_P7\0" |
| /* 2529 */ "Q4_Q5_Q6_Q7\0" |
| /* 2541 */ "W6_W7\0" |
| /* 2547 */ "X0_X1_X2_X3_X4_X5_X6_X7\0" |
| /* 2571 */ "Z4_Z5_Z6_Z7\0" |
| /* 2583 */ "b7\0" |
| /* 2586 */ "d7\0" |
| /* 2589 */ "h7\0" |
| /* 2592 */ "p7\0" |
| /* 2595 */ "q7\0" |
| /* 2598 */ "s7\0" |
| /* 2601 */ "w7\0" |
| /* 2604 */ "x7\0" |
| /* 2607 */ "z7\0" |
| /* 2610 */ "D15_D16_D17_D18\0" |
| /* 2626 */ "Q15_Q16_Q17_Q18\0" |
| /* 2642 */ "Z15_Z16_Z17_Z18\0" |
| /* 2658 */ "b18\0" |
| /* 2662 */ "d18\0" |
| /* 2666 */ "h18\0" |
| /* 2670 */ "q18\0" |
| /* 2674 */ "s18\0" |
| /* 2678 */ "w18\0" |
| /* 2682 */ "x18\0" |
| /* 2686 */ "z18\0" |
| /* 2690 */ "D25_D26_D27_D28\0" |
| /* 2706 */ "Q25_Q26_Q27_Q28\0" |
| /* 2722 */ "Z20_Z28\0" |
| /* 2730 */ "Z16_Z20_Z24_Z28\0" |
| /* 2746 */ "Z25_Z26_Z27_Z28\0" |
| /* 2762 */ "b28\0" |
| /* 2766 */ "d28\0" |
| /* 2770 */ "h28\0" |
| /* 2774 */ "q28\0" |
| /* 2778 */ "s28\0" |
| /* 2782 */ "w28\0" |
| /* 2786 */ "x28\0" |
| /* 2790 */ "z28\0" |
| /* 2794 */ "D5_D6_D7_D8\0" |
| /* 2806 */ "P7_P8\0" |
| /* 2812 */ "Q5_Q6_Q7_Q8\0" |
| /* 2824 */ "Z0_Z8\0" |
| /* 2830 */ "Z5_Z6_Z7_Z8\0" |
| /* 2842 */ "b8\0" |
| /* 2845 */ "d8\0" |
| /* 2848 */ "h8\0" |
| /* 2851 */ "p8\0" |
| /* 2854 */ "q8\0" |
| /* 2857 */ "s8\0" |
| /* 2860 */ "w8\0" |
| /* 2863 */ "x8\0" |
| /* 2866 */ "z8\0" |
| /* 2869 */ "D16_D17_D18_D19\0" |
| /* 2885 */ "Q16_Q17_Q18_Q19\0" |
| /* 2901 */ "W18_W19\0" |
| /* 2909 */ "X12_X13_X14_X15_X16_X17_X18_X19\0" |
| /* 2941 */ "Z16_Z17_Z18_Z19\0" |
| /* 2957 */ "b19\0" |
| /* 2961 */ "d19\0" |
| /* 2965 */ "h19\0" |
| /* 2969 */ "q19\0" |
| /* 2973 */ "s19\0" |
| /* 2977 */ "w19\0" |
| /* 2981 */ "x19\0" |
| /* 2985 */ "z19\0" |
| /* 2989 */ "D26_D27_D28_D29\0" |
| /* 3005 */ "Q26_Q27_Q28_Q29\0" |
| /* 3021 */ "W28_W29\0" |
| /* 3029 */ "Z21_Z29\0" |
| /* 3037 */ "Z17_Z21_Z25_Z29\0" |
| /* 3053 */ "Z26_Z27_Z28_Z29\0" |
| /* 3069 */ "b29\0" |
| /* 3073 */ "d29\0" |
| /* 3077 */ "h29\0" |
| /* 3081 */ "q29\0" |
| /* 3085 */ "s29\0" |
| /* 3089 */ "w29\0" |
| /* 3093 */ "x29\0" |
| /* 3097 */ "z29\0" |
| /* 3101 */ "D6_D7_D8_D9\0" |
| /* 3113 */ "P8_P9\0" |
| /* 3119 */ "Q6_Q7_Q8_Q9\0" |
| /* 3131 */ "W8_W9\0" |
| /* 3137 */ "X2_X3_X4_X5_X6_X7_X8_X9\0" |
| /* 3161 */ "Z1_Z9\0" |
| /* 3167 */ "Z6_Z7_Z8_Z9\0" |
| /* 3179 */ "b9\0" |
| /* 3182 */ "d9\0" |
| /* 3185 */ "h9\0" |
| /* 3188 */ "p9\0" |
| /* 3191 */ "q9\0" |
| /* 3194 */ "s9\0" |
| /* 3197 */ "w9\0" |
| /* 3200 */ "x9\0" |
| /* 3203 */ "z9\0" |
| /* 3206 */ "X22_X23_X24_X25_X26_X27_X28_FP\0" |
| /* 3237 */ "W30_WZR\0" |
| /* 3245 */ "LR_XZR\0" |
| /* 3252 */ "za\0" |
| /* 3255 */ "za0.b\0" |
| /* 3261 */ "za0.d\0" |
| /* 3267 */ "za1.d\0" |
| /* 3273 */ "za2.d\0" |
| /* 3279 */ "za3.d\0" |
| /* 3285 */ "za4.d\0" |
| /* 3291 */ "za5.d\0" |
| /* 3297 */ "za6.d\0" |
| /* 3303 */ "za7.d\0" |
| /* 3309 */ "vg\0" |
| /* 3312 */ "za0.h\0" |
| /* 3318 */ "za1.h\0" |
| /* 3324 */ "z10_hi\0" |
| /* 3331 */ "z20_hi\0" |
| /* 3338 */ "z30_hi\0" |
| /* 3345 */ "z0_hi\0" |
| /* 3351 */ "z11_hi\0" |
| /* 3358 */ "z21_hi\0" |
| /* 3365 */ "z31_hi\0" |
| /* 3372 */ "z1_hi\0" |
| /* 3378 */ "z12_hi\0" |
| /* 3385 */ "z22_hi\0" |
| /* 3392 */ "z2_hi\0" |
| /* 3398 */ "z13_hi\0" |
| /* 3405 */ "z23_hi\0" |
| /* 3412 */ "z3_hi\0" |
| /* 3418 */ "z14_hi\0" |
| /* 3425 */ "z24_hi\0" |
| /* 3432 */ "z4_hi\0" |
| /* 3438 */ "z15_hi\0" |
| /* 3445 */ "z25_hi\0" |
| /* 3452 */ "z5_hi\0" |
| /* 3458 */ "z16_hi\0" |
| /* 3465 */ "z26_hi\0" |
| /* 3472 */ "z6_hi\0" |
| /* 3478 */ "z17_hi\0" |
| /* 3485 */ "z27_hi\0" |
| /* 3492 */ "z7_hi\0" |
| /* 3498 */ "z18_hi\0" |
| /* 3505 */ "z28_hi\0" |
| /* 3512 */ "z8_hi\0" |
| /* 3518 */ "z19_hi\0" |
| /* 3525 */ "z29_hi\0" |
| /* 3532 */ "z9_hi\0" |
| /* 3538 */ "wsp\0" |
| /* 3542 */ "za10.q\0" |
| /* 3549 */ "za0.q\0" |
| /* 3555 */ "za11.q\0" |
| /* 3562 */ "za1.q\0" |
| /* 3568 */ "za12.q\0" |
| /* 3575 */ "za2.q\0" |
| /* 3581 */ "za13.q\0" |
| /* 3588 */ "za3.q\0" |
| /* 3594 */ "za14.q\0" |
| /* 3601 */ "za4.q\0" |
| /* 3607 */ "za15.q\0" |
| /* 3614 */ "za5.q\0" |
| /* 3620 */ "za6.q\0" |
| /* 3626 */ "za7.q\0" |
| /* 3632 */ "za8.q\0" |
| /* 3638 */ "za9.q\0" |
| /* 3644 */ "fpcr\0" |
| /* 3649 */ "ffr\0" |
| /* 3653 */ "wzr\0" |
| /* 3657 */ "xzr\0" |
| /* 3661 */ "za0.s\0" |
| /* 3667 */ "za1.s\0" |
| /* 3673 */ "za2.s\0" |
| /* 3679 */ "za3.s\0" |
| /* 3685 */ "nzcv\0" |
| }; |
| #ifdef __GNUC__ |
| #pragma GCC diagnostic pop |
| #endif |
| |
| static const uint16_t RegAsmOffsetNoRegAltName[] = { |
| 3649, 3093, 3644, 265, 3685, 3539, 3309, 3538, 3653, 3657, 3252, 325, 759, 1020, |
| 1369, 1639, 1999, 2236, 2583, 2842, 3179, 53, 447, 859, 1159, 1473, 1781, 2074, |
| 2351, 2658, 2957, 137, 571, 943, 1283, 1565, 1913, 2162, 2479, 2762, 3069, 241, |
| 675, 328, 762, 1023, 1372, 1642, 2002, 2239, 2586, 2845, 3182, 57, 451, 863, |
| 1163, 1477, 1785, 2078, 2355, 2662, 2961, 141, 575, 947, 1287, 1569, 1917, 2166, |
| 2483, 2766, 3073, 245, 679, 331, 765, 1026, 1375, 1645, 2005, 2242, 2589, 2848, |
| 3185, 61, 455, 867, 1167, 1481, 1789, 2082, 2359, 2666, 2965, 145, 579, 951, |
| 1291, 1573, 1921, 2170, 2487, 2770, 3077, 249, 683, 334, 768, 1029, 1378, 1648, |
| 2008, 2245, 2592, 2851, 3188, 65, 459, 871, 1171, 1485, 1793, 337, 771, 1032, |
| 1381, 1651, 2011, 2248, 2595, 2854, 3191, 69, 463, 875, 1175, 1489, 1797, 2086, |
| 2363, 2670, 2969, 149, 583, 955, 1295, 1577, 1925, 2174, 2491, 2774, 3081, 253, |
| 687, 340, 774, 1035, 1384, 1654, 2014, 2251, 2598, 2857, 3194, 73, 467, 879, |
| 1179, 1493, 1801, 2090, 2367, 2674, 2973, 153, 587, 959, 1299, 1581, 1929, 2178, |
| 2495, 2778, 3085, 257, 691, 347, 777, 1038, 1387, 1657, 2017, 2254, 2601, 2860, |
| 3197, 77, 471, 883, 1183, 1497, 1805, 2094, 2371, 2678, 2977, 157, 591, 963, |
| 1303, 1585, 1933, 2182, 2499, 2782, 3089, 261, 350, 780, 1041, 1390, 1660, 2020, |
| 2257, 2604, 2863, 3200, 81, 475, 887, 1187, 1501, 1809, 2098, 2375, 2682, 2981, |
| 161, 595, 967, 1307, 1589, 1937, 2186, 2503, 2786, 353, 783, 1044, 1393, 1663, |
| 2023, 2260, 2607, 2866, 3203, 85, 479, 891, 1191, 1505, 1813, 2102, 2379, 2686, |
| 2985, 165, 599, 971, 1311, 1593, 1941, 2190, 2507, 2790, 3097, 269, 695, 3255, |
| 3261, 3267, 3273, 3279, 3285, 3291, 3297, 3303, 3312, 3318, 3549, 3562, 3575, 3588, |
| 3601, 3614, 3620, 3626, 3632, 3638, 3542, 3555, 3568, 3581, 3594, 3607, 3661, 3667, |
| 3673, 3679, 343, 3345, 3372, 3392, 3412, 3432, 3452, 3472, 3492, 3512, 3532, 3324, |
| 3351, 3378, 3398, 3418, 3438, 3458, 3478, 3498, 3518, 3331, 3358, 3385, 3405, 3425, |
| 3445, 3465, 3485, 3505, 3525, 3338, 3365, 707, 982, 1321, 1603, 1951, 2200, 2517, |
| 2800, 3107, 6, 362, 793, 1055, 1404, 1674, 2034, 2271, 2618, 2877, 97, 491, |
| 903, 1203, 1517, 1825, 2114, 2391, 2698, 2997, 177, 611, 281, 1315, 1597, 1945, |
| 2194, 2511, 2794, 3101, 0, 356, 786, 1047, 1396, 1666, 2026, 2263, 2610, 2869, |
| 89, 483, 895, 1195, 1509, 1817, 2106, 2383, 2690, 2989, 169, 603, 273, 699, |
| 975, 979, 1318, 1600, 1948, 2197, 2514, 2797, 3104, 3, 359, 789, 1051, 1400, |
| 1670, 2030, 2267, 2614, 2873, 93, 487, 899, 1199, 1513, 1821, 2110, 2387, 2694, |
| 2993, 173, 607, 277, 703, 713, 988, 1327, 1609, 1957, 2206, 2523, 2806, 3113, |
| 13, 370, 801, 1063, 1412, 1682, 288, 727, 1001, 1339, 1621, 1969, 2218, 2535, |
| 2818, 3125, 26, 384, 816, 1079, 1428, 1698, 2050, 2287, 2634, 2893, 113, 507, |
| 919, 1219, 1533, 1841, 2130, 2407, 2714, 3013, 193, 627, 303, 1333, 1615, 1963, |
| 2212, 2529, 2812, 3119, 20, 378, 809, 1071, 1420, 1690, 2042, 2279, 2626, 2885, |
| 105, 499, 911, 1211, 1525, 1833, 2122, 2399, 2706, 3005, 185, 619, 295, 719, |
| 994, 998, 1336, 1618, 1966, 2215, 2532, 2815, 3122, 23, 381, 812, 1075, 1424, |
| 1694, 2046, 2283, 2630, 2889, 109, 503, 915, 1215, 1529, 1837, 2126, 2403, 2710, |
| 3009, 189, 623, 299, 723, 3206, 2547, 3137, 400, 1095, 1714, 2303, 2909, 523, |
| 1235, 1857, 2423, 3237, 733, 1345, 1975, 2541, 3131, 392, 1087, 1706, 2295, 2901, |
| 515, 1227, 1849, 2415, 3021, 3245, 3230, 739, 1351, 1981, 2565, 3155, 418, 1115, |
| 1736, 2327, 2933, 547, 1259, 1881, 2447, 753, 1014, 1363, 1633, 1993, 2230, 2577, |
| 2836, 3173, 46, 432, 831, 1131, 1458, 1766, 2066, 2343, 2650, 2949, 129, 563, |
| 935, 1275, 1549, 1897, 2146, 2463, 2754, 3061, 233, 643, 318, 1357, 1627, 1987, |
| 2224, 2571, 2830, 3167, 40, 426, 824, 1123, 1450, 1758, 2058, 2335, 2642, 2941, |
| 121, 555, 927, 1267, 1541, 1889, 2138, 2455, 2746, 3053, 225, 635, 310, 745, |
| 1007, 1011, 1360, 1630, 1990, 2227, 2574, 2833, 3170, 43, 429, 827, 1127, 1454, |
| 1762, 2062, 2339, 2646, 2945, 125, 559, 931, 1271, 1545, 1893, 2142, 2459, 2750, |
| 3057, 229, 639, 314, 749, 1557, 1905, 2154, 2471, 2722, 3029, 201, 651, 2824, |
| 3161, 33, 440, 839, 1139, 1466, 1774, 2730, 3037, 209, 659, 846, 1146, 1436, |
| 1744, |
| }; |
| |
| |
| #ifdef __GNUC__ |
| #pragma GCC diagnostic push |
| #pragma GCC diagnostic ignored "-Woverlength-strings" |
| #endif |
| static const char AsmStrsvlist1[] = { |
| /* 0 */ "\0" |
| }; |
| #ifdef __GNUC__ |
| #pragma GCC diagnostic pop |
| #endif |
| |
| static const uint8_t RegAsmOffsetvlist1[] = { |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, |
| }; |
| |
| |
| #ifdef __GNUC__ |
| #pragma GCC diagnostic push |
| #pragma GCC diagnostic ignored "-Woverlength-strings" |
| #endif |
| static const char AsmStrsvreg[] = { |
| /* 0 */ "v10\0" |
| /* 4 */ "v20\0" |
| /* 8 */ "v30\0" |
| /* 12 */ "v0\0" |
| /* 15 */ "v11\0" |
| /* 19 */ "v21\0" |
| /* 23 */ "v31\0" |
| /* 27 */ "v1\0" |
| /* 30 */ "v12\0" |
| /* 34 */ "v22\0" |
| /* 38 */ "v2\0" |
| /* 41 */ "v13\0" |
| /* 45 */ "v23\0" |
| /* 49 */ "v3\0" |
| /* 52 */ "v14\0" |
| /* 56 */ "v24\0" |
| /* 60 */ "v4\0" |
| /* 63 */ "v15\0" |
| /* 67 */ "v25\0" |
| /* 71 */ "v5\0" |
| /* 74 */ "v16\0" |
| /* 78 */ "v26\0" |
| /* 82 */ "v6\0" |
| /* 85 */ "v17\0" |
| /* 89 */ "v27\0" |
| /* 93 */ "v7\0" |
| /* 96 */ "v18\0" |
| /* 100 */ "v28\0" |
| /* 104 */ "v8\0" |
| /* 107 */ "v19\0" |
| /* 111 */ "v29\0" |
| /* 115 */ "v9\0" |
| }; |
| #ifdef __GNUC__ |
| #pragma GCC diagnostic pop |
| #endif |
| |
| static const uint8_t RegAsmOffsetvreg[] = { |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, |
| 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, |
| 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, |
| 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, |
| 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, |
| 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, |
| 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, |
| 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, |
| 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, |
| 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, |
| 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, |
| 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, |
| 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, |
| 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, |
| 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, |
| 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, |
| 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, |
| 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, |
| 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, |
| 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, |
| }; |
| |
| switch(AltIdx) { |
| default: llvm_unreachable("Invalid register alt name index!"); |
| case AArch64::NoRegAltName: |
| assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) && |
| "Invalid alt name index for register!"); |
| return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]; |
| case AArch64::vlist1: |
| assert(*(AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1]) && |
| "Invalid alt name index for register!"); |
| return AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1]; |
| case AArch64::vreg: |
| assert(*(AsmStrsvreg+RegAsmOffsetvreg[RegNo-1]) && |
| "Invalid alt name index for register!"); |
| return AsmStrsvreg+RegAsmOffsetvreg[RegNo-1]; |
| } |
| } |
| |
| #ifdef PRINT_ALIAS_INSTR |
| #undef PRINT_ALIAS_INSTR |
| |
| static bool AArch64AppleInstPrinterValidateMCOperand(const MCOperand &MCOp, |
| const MCSubtargetInfo &STI, |
| unsigned PredicateIndex); |
| bool AArch64AppleInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) { |
| static const PatternsForOpcode OpToPatterns[] = { |
| {AArch64::ADDSWri, 0, 1 }, |
| {AArch64::ADDSWrs, 1, 3 }, |
| {AArch64::ADDSWrx, 4, 3 }, |
| {AArch64::ADDSXri, 7, 1 }, |
| {AArch64::ADDSXrs, 8, 3 }, |
| {AArch64::ADDSXrx, 11, 1 }, |
| {AArch64::ADDSXrx64, 12, 3 }, |
| {AArch64::ADDWri, 15, 2 }, |
| {AArch64::ADDWrs, 17, 1 }, |
| {AArch64::ADDWrx, 18, 2 }, |
| {AArch64::ADDXri, 20, 2 }, |
| {AArch64::ADDXrs, 22, 1 }, |
| {AArch64::ADDXrx64, 23, 2 }, |
| {AArch64::ANDSWri, 25, 1 }, |
| {AArch64::ANDSWrs, 26, 3 }, |
| {AArch64::ANDSXri, 29, 1 }, |
| {AArch64::ANDSXrs, 30, 3 }, |
| {AArch64::ANDS_PPzPP, 33, 1 }, |
| {AArch64::ANDWrs, 34, 1 }, |
| {AArch64::ANDXrs, 35, 1 }, |
| {AArch64::AND_PPzPP, 36, 1 }, |
| {AArch64::AND_ZI, 37, 3 }, |
| {AArch64::AUTIA1716, 40, 1 }, |
| {AArch64::AUTIASP, 41, 1 }, |
| {AArch64::AUTIAZ, 42, 1 }, |
| {AArch64::AUTIB1716, 43, 1 }, |
| {AArch64::AUTIBSP, 44, 1 }, |
| {AArch64::AUTIBZ, 45, 1 }, |
| {AArch64::BICSWrs, 46, 1 }, |
| {AArch64::BICSXrs, 47, 1 }, |
| {AArch64::BICWrs, 48, 1 }, |
| {AArch64::BICXrs, 49, 1 }, |
| {AArch64::CLREX, 50, 1 }, |
| {AArch64::CNTB_XPiI, 51, 2 }, |
| {AArch64::CNTD_XPiI, 53, 2 }, |
| {AArch64::CNTH_XPiI, 55, 2 }, |
| {AArch64::CNTW_XPiI, 57, 2 }, |
| {AArch64::CPY_ZPmI_B, 59, 1 }, |
| {AArch64::CPY_ZPmI_D, 60, 1 }, |
| {AArch64::CPY_ZPmI_H, 61, 1 }, |
| {AArch64::CPY_ZPmI_S, 62, 1 }, |
| {AArch64::CPY_ZPmR_B, 63, 1 }, |
| {AArch64::CPY_ZPmR_D, 64, 1 }, |
| {AArch64::CPY_ZPmR_H, 65, 1 }, |
| {AArch64::CPY_ZPmR_S, 66, 1 }, |
| {AArch64::CPY_ZPmV_B, 67, 1 }, |
| {AArch64::CPY_ZPmV_D, 68, 1 }, |
| {AArch64::CPY_ZPmV_H, 69, 1 }, |
| {AArch64::CPY_ZPmV_S, 70, 1 }, |
| {AArch64::CPY_ZPzI_B, 71, 1 }, |
| {AArch64::CPY_ZPzI_D, 72, 1 }, |
| {AArch64::CPY_ZPzI_H, 73, 1 }, |
| {AArch64::CPY_ZPzI_S, 74, 1 }, |
| {AArch64::CSINCWr, 75, 2 }, |
| {AArch64::CSINCXr, 77, 2 }, |
| {AArch64::CSINVWr, 79, 2 }, |
| {AArch64::CSINVXr, 81, 2 }, |
| {AArch64::CSNEGWr, 83, 1 }, |
| {AArch64::CSNEGXr, 84, 1 }, |
| {AArch64::DCPS1, 85, 1 }, |
| {AArch64::DCPS2, 86, 1 }, |
| {AArch64::DCPS3, 87, 1 }, |
| {AArch64::DECB_XPiI, 88, 2 }, |
| {AArch64::DECD_XPiI, 90, 2 }, |
| {AArch64::DECD_ZPiI, 92, 2 }, |
| {AArch64::DECH_XPiI, 94, 2 }, |
| {AArch64::DECH_ZPiI, 96, 2 }, |
| {AArch64::DECW_XPiI, 98, 2 }, |
| {AArch64::DECW_ZPiI, 100, 2 }, |
| {AArch64::DSB, 102, 3 }, |
| {AArch64::DUPM_ZI, 105, 6 }, |
| {AArch64::DUP_ZI_B, 111, 1 }, |
| {AArch64::DUP_ZI_D, 112, 2 }, |
| {AArch64::DUP_ZI_H, 114, 2 }, |
| {AArch64::DUP_ZI_S, 116, 2 }, |
| {AArch64::DUP_ZR_B, 118, 1 }, |
| {AArch64::DUP_ZR_D, 119, 1 }, |
| {AArch64::DUP_ZR_H, 120, 1 }, |
| {AArch64::DUP_ZR_S, 121, 1 }, |
| {AArch64::DUP_ZZI_B, 122, 2 }, |
| {AArch64::DUP_ZZI_D, 124, 2 }, |
| {AArch64::DUP_ZZI_H, 126, 2 }, |
| {AArch64::DUP_ZZI_Q, 128, 2 }, |
| {AArch64::DUP_ZZI_S, 130, 2 }, |
| {AArch64::EONWrs, 132, 1 }, |
| {AArch64::EONXrs, 133, 1 }, |
| {AArch64::EORS_PPzPP, 134, 1 }, |
| {AArch64::EORWrs, 135, 1 }, |
| {AArch64::EORXrs, 136, 1 }, |
| {AArch64::EOR_PPzPP, 137, 1 }, |
| {AArch64::EOR_ZI, 138, 3 }, |
| {AArch64::EXTRACT_ZPMXI_H_B, 141, 1 }, |
| {AArch64::EXTRACT_ZPMXI_H_D, 142, 1 }, |
| {AArch64::EXTRACT_ZPMXI_H_H, 143, 1 }, |
| {AArch64::EXTRACT_ZPMXI_H_Q, 144, 1 }, |
| {AArch64::EXTRACT_ZPMXI_H_S, 145, 1 }, |
| {AArch64::EXTRACT_ZPMXI_V_B, 146, 1 }, |
| {AArch64::EXTRACT_ZPMXI_V_D, 147, 1 }, |
| {AArch64::EXTRACT_ZPMXI_V_H, 148, 1 }, |
| {AArch64::EXTRACT_ZPMXI_V_Q, 149, 1 }, |
| {AArch64::EXTRACT_ZPMXI_V_S, 150, 1 }, |
| {AArch64::EXTRWrri, 151, 1 }, |
| {AArch64::EXTRXrri, 152, 1 }, |
| {AArch64::FCPY_ZPmI_D, 153, 1 }, |
| {AArch64::FCPY_ZPmI_H, 154, 1 }, |
| {AArch64::FCPY_ZPmI_S, 155, 1 }, |
| {AArch64::FDUP_ZI_D, 156, 1 }, |
| {AArch64::FDUP_ZI_H, 157, 1 }, |
| {AArch64::FDUP_ZI_S, 158, 1 }, |
| {AArch64::GLD1B_D_IMM_REAL, 159, 1 }, |
| {AArch64::GLD1B_S_IMM_REAL, 160, 1 }, |
| {AArch64::GLD1D_IMM_REAL, 161, 1 }, |
| {AArch64::GLD1H_D_IMM_REAL, 162, 1 }, |
| {AArch64::GLD1H_S_IMM_REAL, 163, 1 }, |
| {AArch64::GLD1Q, 164, 1 }, |
| {AArch64::GLD1SB_D_IMM_REAL, 165, 1 }, |
| {AArch64::GLD1SB_S_IMM_REAL, 166, 1 }, |
| {AArch64::GLD1SH_D_IMM_REAL, 167, 1 }, |
| {AArch64::GLD1SH_S_IMM_REAL, 168, 1 }, |
| {AArch64::GLD1SW_D_IMM_REAL, 169, 1 }, |
| {AArch64::GLD1W_D_IMM_REAL, 170, 1 }, |
| {AArch64::GLD1W_IMM_REAL, 171, 1 }, |
| {AArch64::GLDFF1B_D_IMM_REAL, 172, 1 }, |
| {AArch64::GLDFF1B_S_IMM_REAL, 173, 1 }, |
| {AArch64::GLDFF1D_IMM_REAL, 174, 1 }, |
| {AArch64::GLDFF1H_D_IMM_REAL, 175, 1 }, |
| {AArch64::GLDFF1H_S_IMM_REAL, 176, 1 }, |
| {AArch64::GLDFF1SB_D_IMM_REAL, 177, 1 }, |
| {AArch64::GLDFF1SB_S_IMM_REAL, 178, 1 }, |
| {AArch64::GLDFF1SH_D_IMM_REAL, 179, 1 }, |
| {AArch64::GLDFF1SH_S_IMM_REAL, 180, 1 }, |
| {AArch64::GLDFF1SW_D_IMM_REAL, 181, 1 }, |
| {AArch64::GLDFF1W_D_IMM_REAL, 182, 1 }, |
| {AArch64::GLDFF1W_IMM_REAL, 183, 1 }, |
| {AArch64::HINT, 184, 13 }, |
| {AArch64::INCB_XPiI, 197, 2 }, |
| {AArch64::INCD_XPiI, 199, 2 }, |
| {AArch64::INCD_ZPiI, 201, 2 }, |
| {AArch64::INCH_XPiI, 203, 2 }, |
| {AArch64::INCH_ZPiI, 205, 2 }, |
| {AArch64::INCW_XPiI, 207, 2 }, |
| {AArch64::INCW_ZPiI, 209, 2 }, |
| {AArch64::INSERT_MXIPZ_H_B, 211, 1 }, |
| {AArch64::INSERT_MXIPZ_H_D, 212, 1 }, |
| {AArch64::INSERT_MXIPZ_H_H, 213, 1 }, |
| {AArch64::INSERT_MXIPZ_H_Q, 214, 1 }, |
| {AArch64::INSERT_MXIPZ_H_S, 215, 1 }, |
| {AArch64::INSERT_MXIPZ_V_B, 216, 1 }, |
| {AArch64::INSERT_MXIPZ_V_D, 217, 1 }, |
| {AArch64::INSERT_MXIPZ_V_H, 218, 1 }, |
| {AArch64::INSERT_MXIPZ_V_Q, 219, 1 }, |
| {AArch64::INSERT_MXIPZ_V_S, 220, 1 }, |
| {AArch64::INSvi16gpr, 221, 1 }, |
| {AArch64::INSvi16lane, 222, 1 }, |
| {AArch64::INSvi32gpr, 223, 1 }, |
| {AArch64::INSvi32lane, 224, 1 }, |
| {AArch64::INSvi64gpr, 225, 1 }, |
| {AArch64::INSvi64lane, 226, 1 }, |
| {AArch64::INSvi8gpr, 227, 1 }, |
| {AArch64::INSvi8lane, 228, 1 }, |
| {AArch64::IRG, 229, 1 }, |
| {AArch64::ISB, 230, 1 }, |
| {AArch64::LD1B_2Z_IMM, 231, 1 }, |
| {AArch64::LD1B_4Z_IMM, 232, 1 }, |
| {AArch64::LD1B_D_IMM_REAL, 233, 1 }, |
| {AArch64::LD1B_H_IMM_REAL, 234, 1 }, |
| {AArch64::LD1B_IMM_REAL, 235, 1 }, |
| {AArch64::LD1B_S_IMM_REAL, 236, 1 }, |
| {AArch64::LD1B_VG2_M2ZPXI, 237, 1 }, |
| {AArch64::LD1B_VG4_M4ZPXI, 238, 1 }, |
| {AArch64::LD1D_2Z_IMM, 239, 1 }, |
| {AArch64::LD1D_4Z_IMM, 240, 1 }, |
| {AArch64::LD1D_IMM_REAL, 241, 1 }, |
| {AArch64::LD1D_Q_IMM, 242, 1 }, |
| {AArch64::LD1D_VG2_M2ZPXI, 243, 1 }, |
| {AArch64::LD1D_VG4_M4ZPXI, 244, 1 }, |
| {AArch64::LD1Fourv16b_POST, 245, 1 }, |
| {AArch64::LD1Fourv1d_POST, 246, 1 }, |
| {AArch64::LD1Fourv2d_POST, 247, 1 }, |
| {AArch64::LD1Fourv2s_POST, 248, 1 }, |
| {AArch64::LD1Fourv4h_POST, 249, 1 }, |
| {AArch64::LD1Fourv4s_POST, 250, 1 }, |
| {AArch64::LD1Fourv8b_POST, 251, 1 }, |
| {AArch64::LD1Fourv8h_POST, 252, 1 }, |
| {AArch64::LD1H_2Z_IMM, 253, 1 }, |
| {AArch64::LD1H_4Z_IMM, 254, 1 }, |
| {AArch64::LD1H_D_IMM_REAL, 255, 1 }, |
| {AArch64::LD1H_IMM_REAL, 256, 1 }, |
| {AArch64::LD1H_S_IMM_REAL, 257, 1 }, |
| {AArch64::LD1H_VG2_M2ZPXI, 258, 1 }, |
| {AArch64::LD1H_VG4_M4ZPXI, 259, 1 }, |
| {AArch64::LD1Onev16b_POST, 260, 1 }, |
| {AArch64::LD1Onev1d_POST, 261, 1 }, |
| {AArch64::LD1Onev2d_POST, 262, 1 }, |
| {AArch64::LD1Onev2s_POST, 263, 1 }, |
| {AArch64::LD1Onev4h_POST, 264, 1 }, |
| {AArch64::LD1Onev4s_POST, 265, 1 }, |
| {AArch64::LD1Onev8b_POST, 266, 1 }, |
| {AArch64::LD1Onev8h_POST, 267, 1 }, |
| {AArch64::LD1RB_D_IMM, 268, 1 }, |
| {AArch64::LD1RB_H_IMM, 269, 1 }, |
| {AArch64::LD1RB_IMM, 270, 1 }, |
| {AArch64::LD1RB_S_IMM, 271, 1 }, |
| {AArch64::LD1RD_IMM, 272, 1 }, |
| {AArch64::LD1RH_D_IMM, 273, 1 }, |
| {AArch64::LD1RH_IMM, 274, 1 }, |
| {AArch64::LD1RH_S_IMM, 275, 1 }, |
| {AArch64::LD1RO_B_IMM, 276, 1 }, |
| {AArch64::LD1RO_D_IMM, 277, 1 }, |
| {AArch64::LD1RO_H_IMM, 278, 1 }, |
| {AArch64::LD1RO_W_IMM, 279, 1 }, |
| {AArch64::LD1RQ_B_IMM, 280, 1 }, |
| {AArch64::LD1RQ_D_IMM, 281, 1 }, |
| {AArch64::LD1RQ_H_IMM, 282, 1 }, |
| {AArch64::LD1RQ_W_IMM, 283, 1 }, |
| {AArch64::LD1RSB_D_IMM, 284, 1 }, |
| {AArch64::LD1RSB_H_IMM, 285, 1 }, |
| {AArch64::LD1RSB_S_IMM, 286, 1 }, |
| {AArch64::LD1RSH_D_IMM, 287, 1 }, |
| {AArch64::LD1RSH_S_IMM, 288, 1 }, |
| {AArch64::LD1RSW_IMM, 289, 1 }, |
| {AArch64::LD1RW_D_IMM, 290, 1 }, |
| {AArch64::LD1RW_IMM, 291, 1 }, |
| {AArch64::LD1Rv16b_POST, 292, 1 }, |
| {AArch64::LD1Rv1d_POST, 293, 1 }, |
| {AArch64::LD1Rv2d_POST, 294, 1 }, |
| {AArch64::LD1Rv2s_POST, 295, 1 }, |
| {AArch64::LD1Rv4h_POST, 296, 1 }, |
| {AArch64::LD1Rv4s_POST, 297, 1 }, |
| {AArch64::LD1Rv8b_POST, 298, 1 }, |
| {AArch64::LD1Rv8h_POST, 299, 1 }, |
| {AArch64::LD1SB_D_IMM_REAL, 300, 1 }, |
| {AArch64::LD1SB_H_IMM_REAL, 301, 1 }, |
| {AArch64::LD1SB_S_IMM_REAL, 302, 1 }, |
| {AArch64::LD1SH_D_IMM_REAL, 303, 1 }, |
| {AArch64::LD1SH_S_IMM_REAL, 304, 1 }, |
| {AArch64::LD1SW_D_IMM_REAL, 305, 1 }, |
| {AArch64::LD1Threev16b_POST, 306, 1 }, |
| {AArch64::LD1Threev1d_POST, 307, 1 }, |
| {AArch64::LD1Threev2d_POST, 308, 1 }, |
| {AArch64::LD1Threev2s_POST, 309, 1 }, |
| {AArch64::LD1Threev4h_POST, 310, 1 }, |
| {AArch64::LD1Threev4s_POST, 311, 1 }, |
| {AArch64::LD1Threev8b_POST, 312, 1 }, |
| {AArch64::LD1Threev8h_POST, 313, 1 }, |
| {AArch64::LD1Twov16b_POST, 314, 1 }, |
| {AArch64::LD1Twov1d_POST, 315, 1 }, |
| {AArch64::LD1Twov2d_POST, 316, 1 }, |
| {AArch64::LD1Twov2s_POST, 317, 1 }, |
| {AArch64::LD1Twov4h_POST, 318, 1 }, |
| {AArch64::LD1Twov4s_POST, 319, 1 }, |
| {AArch64::LD1Twov8b_POST, 320, 1 }, |
| {AArch64::LD1Twov8h_POST, 321, 1 }, |
| {AArch64::LD1W_2Z_IMM, 322, 1 }, |
| {AArch64::LD1W_4Z_IMM, 323, 1 }, |
| {AArch64::LD1W_D_IMM_REAL, 324, 1 }, |
| {AArch64::LD1W_IMM_REAL, 325, 1 }, |
| {AArch64::LD1W_Q_IMM, 326, 1 }, |
| {AArch64::LD1W_VG2_M2ZPXI, 327, 1 }, |
| {AArch64::LD1W_VG4_M4ZPXI, 328, 1 }, |
| {AArch64::LD1_MXIPXX_H_B, 329, 1 }, |
| {AArch64::LD1_MXIPXX_H_D, 330, 1 }, |
| {AArch64::LD1_MXIPXX_H_H, 331, 1 }, |
| {AArch64::LD1_MXIPXX_H_Q, 332, 1 }, |
| {AArch64::LD1_MXIPXX_H_S, 333, 1 }, |
| {AArch64::LD1_MXIPXX_V_B, 334, 1 }, |
| {AArch64::LD1_MXIPXX_V_D, 335, 1 }, |
| {AArch64::LD1_MXIPXX_V_H, 336, 1 }, |
| {AArch64::LD1_MXIPXX_V_Q, 337, 1 }, |
| {AArch64::LD1_MXIPXX_V_S, 338, 1 }, |
| {AArch64::LD1i16_POST, 339, 1 }, |
| {AArch64::LD1i32_POST, 340, 1 }, |
| {AArch64::LD1i64_POST, 341, 1 }, |
| {AArch64::LD1i8_POST, 342, 1 }, |
| {AArch64::LD2B_IMM, 343, 1 }, |
| {AArch64::LD2D_IMM, 344, 1 }, |
| {AArch64::LD2H_IMM, 345, 1 }, |
| {AArch64::LD2Q_IMM, 346, 1 }, |
| {AArch64::LD2Rv16b_POST, 347, 1 }, |
| {AArch64::LD2Rv1d_POST, 348, 1 }, |
| {AArch64::LD2Rv2d_POST, 349, 1 }, |
| {AArch64::LD2Rv2s_POST, 350, 1 }, |
| {AArch64::LD2Rv4h_POST, 351, 1 }, |
| {AArch64::LD2Rv4s_POST, 352, 1 }, |
| {AArch64::LD2Rv8b_POST, 353, 1 }, |
| {AArch64::LD2Rv8h_POST, 354, 1 }, |
| {AArch64::LD2Twov16b_POST, 355, 1 }, |
| {AArch64::LD2Twov2d_POST, 356, 1 }, |
| {AArch64::LD2Twov2s_POST, 357, 1 }, |
| {AArch64::LD2Twov4h_POST, 358, 1 }, |
| {AArch64::LD2Twov4s_POST, 359, 1 }, |
| {AArch64::LD2Twov8b_POST, 360, 1 }, |
| {AArch64::LD2Twov8h_POST, 361, 1 }, |
| {AArch64::LD2W_IMM, 362, 1 }, |
| {AArch64::LD2i16_POST, 363, 1 }, |
| {AArch64::LD2i32_POST, 364, 1 }, |
| {AArch64::LD2i64_POST, 365, 1 }, |
| {AArch64::LD2i8_POST, 366, 1 }, |
| {AArch64::LD3B_IMM, 367, 1 }, |
| {AArch64::LD3D_IMM, 368, 1 }, |
| {AArch64::LD3H_IMM, 369, 1 }, |
| {AArch64::LD3Q_IMM, 370, 1 }, |
| {AArch64::LD3Rv16b_POST, 371, 1 }, |
| {AArch64::LD3Rv1d_POST, 372, 1 }, |
| {AArch64::LD3Rv2d_POST, 373, 1 }, |
| {AArch64::LD3Rv2s_POST, 374, 1 }, |
| {AArch64::LD3Rv4h_POST, 375, 1 }, |
| {AArch64::LD3Rv4s_POST, 376, 1 }, |
| {AArch64::LD3Rv8b_POST, 377, 1 }, |
| {AArch64::LD3Rv8h_POST, 378, 1 }, |
| {AArch64::LD3Threev16b_POST, 379, 1 }, |
| {AArch64::LD3Threev2d_POST, 380, 1 }, |
| {AArch64::LD3Threev2s_POST, 381, 1 }, |
| {AArch64::LD3Threev4h_POST, 382, 1 }, |
| {AArch64::LD3Threev4s_POST, 383, 1 }, |
| {AArch64::LD3Threev8b_POST, 384, 1 }, |
| {AArch64::LD3Threev8h_POST, 385, 1 }, |
| {AArch64::LD3W_IMM, 386, 1 }, |
| {AArch64::LD3i16_POST, 387, 1 }, |
| {AArch64::LD3i32_POST, 388, 1 }, |
| {AArch64::LD3i64_POST, 389, 1 }, |
| {AArch64::LD3i8_POST, 390, 1 }, |
| {AArch64::LD4B_IMM, 391, 1 }, |
| {AArch64::LD4D_IMM, 392, 1 }, |
| {AArch64::LD4Fourv16b_POST, 393, 1 }, |
| {AArch64::LD4Fourv2d_POST, 394, 1 }, |
| {AArch64::LD4Fourv2s_POST, 395, 1 }, |
| {AArch64::LD4Fourv4h_POST, 396, 1 }, |
| {AArch64::LD4Fourv4s_POST, 397, 1 }, |
| {AArch64::LD4Fourv8b_POST, 398, 1 }, |
| {AArch64::LD4Fourv8h_POST, 399, 1 }, |
| {AArch64::LD4H_IMM, 400, 1 }, |
| {AArch64::LD4Q_IMM, 401, 1 }, |
| {AArch64::LD4Rv16b_POST, 402, 1 }, |
| {AArch64::LD4Rv1d_POST, 403, 1 }, |
| {AArch64::LD4Rv2d_POST, 404, 1 }, |
| {AArch64::LD4Rv2s_POST, 405, 1 }, |
| {AArch64::LD4Rv4h_POST, 406, 1 }, |
| {AArch64::LD4Rv4s_POST, 407, 1 }, |
| {AArch64::LD4Rv8b_POST, 408, 1 }, |
| {AArch64::LD4Rv8h_POST, 409, 1 }, |
| {AArch64::LD4W_IMM, 410, 1 }, |
| {AArch64::LD4i16_POST, 411, 1 }, |
| {AArch64::LD4i32_POST, 412, 1 }, |
| {AArch64::LD4i64_POST, 413, 1 }, |
| {AArch64::LD4i8_POST, 414, 1 }, |
| {AArch64::LDADDB, 415, 1 }, |
| {AArch64::LDADDH, 416, 1 }, |
| {AArch64::LDADDLB, 417, 1 }, |
| {AArch64::LDADDLH, 418, 1 }, |
| {AArch64::LDADDLW, 419, 1 }, |
| {AArch64::LDADDLX, 420, 1 }, |
| {AArch64::LDADDW, 421, 1 }, |
| {AArch64::LDADDX, 422, 1 }, |
| {AArch64::LDAPURBi, 423, 1 }, |
| {AArch64::LDAPURHi, 424, 1 }, |
| {AArch64::LDAPURSBWi, 425, 1 }, |
| {AArch64::LDAPURSBXi, 426, 1 }, |
| {AArch64::LDAPURSHWi, 427, 1 }, |
| {AArch64::LDAPURSHXi, 428, 1 }, |
| {AArch64::LDAPURSWi, 429, 1 }, |
| {AArch64::LDAPURXi, 430, 1 }, |
| {AArch64::LDAPURbi, 431, 1 }, |
| {AArch64::LDAPURdi, 432, 1 }, |
| {AArch64::LDAPURhi, 433, 1 }, |
| {AArch64::LDAPURi, 434, 1 }, |
| {AArch64::LDAPURqi, 435, 1 }, |
| {AArch64::LDAPURsi, 436, 1 }, |
| {AArch64::LDCLRB, 437, 1 }, |
| {AArch64::LDCLRH, 438, 1 }, |
| {AArch64::LDCLRLB, 439, 1 }, |
| {AArch64::LDCLRLH, 440, 1 }, |
| {AArch64::LDCLRLW, 441, 1 }, |
| {AArch64::LDCLRLX, 442, 1 }, |
| {AArch64::LDCLRW, 443, 1 }, |
| {AArch64::LDCLRX, 444, 1 }, |
| {AArch64::LDEORB, 445, 1 }, |
| {AArch64::LDEORH, 446, 1 }, |
| {AArch64::LDEORLB, 447, 1 }, |
| {AArch64::LDEORLH, 448, 1 }, |
| {AArch64::LDEORLW, 449, 1 }, |
| {AArch64::LDEORLX, 450, 1 }, |
| {AArch64::LDEORW, 451, 1 }, |
| {AArch64::LDEORX, 452, 1 }, |
| {AArch64::LDFF1B_D_REAL, 453, 1 }, |
| {AArch64::LDFF1B_H_REAL, 454, 1 }, |
| {AArch64::LDFF1B_REAL, 455, 1 }, |
| {AArch64::LDFF1B_S_REAL, 456, 1 }, |
| {AArch64::LDFF1D_REAL, 457, 1 }, |
| {AArch64::LDFF1H_D_REAL, 458, 1 }, |
| {AArch64::LDFF1H_REAL, 459, 1 }, |
| {AArch64::LDFF1H_S_REAL, 460, 1 }, |
| {AArch64::LDFF1SB_D_REAL, 461, 1 }, |
| {AArch64::LDFF1SB_H_REAL, 462, 1 }, |
| {AArch64::LDFF1SB_S_REAL, 463, 1 }, |
| {AArch64::LDFF1SH_D_REAL, 464, 1 }, |
| {AArch64::LDFF1SH_S_REAL, 465, 1 }, |
| {AArch64::LDFF1SW_D_REAL, 466, 1 }, |
| {AArch64::LDFF1W_D_REAL, 467, 1 }, |
| {AArch64::LDFF1W_REAL, 468, 1 }, |
| {AArch64::LDG, 469, 1 }, |
| {AArch64::LDNF1B_D_IMM_REAL, 470, 1 }, |
| {AArch64::LDNF1B_H_IMM_REAL, 471, 1 }, |
| {AArch64::LDNF1B_IMM_REAL, 472, 1 }, |
| {AArch64::LDNF1B_S_IMM_REAL, 473, 1 }, |
| {AArch64::LDNF1D_IMM_REAL, 474, 1 }, |
| {AArch64::LDNF1H_D_IMM_REAL, 475, 1 }, |
| {AArch64::LDNF1H_IMM_REAL, 476, 1 }, |
| {AArch64::LDNF1H_S_IMM_REAL, 477, 1 }, |
| {AArch64::LDNF1SB_D_IMM_REAL, 478, 1 }, |
| {AArch64::LDNF1SB_H_IMM_REAL, 479, 1 }, |
| {AArch64::LDNF1SB_S_IMM_REAL, 480, 1 }, |
| {AArch64::LDNF1SH_D_IMM_REAL, 481, 1 }, |
| {AArch64::LDNF1SH_S_IMM_REAL, 482, 1 }, |
| {AArch64::LDNF1SW_D_IMM_REAL, 483, 1 }, |
| {AArch64::LDNF1W_D_IMM_REAL, 484, 1 }, |
| {AArch64::LDNF1W_IMM_REAL, 485, 1 }, |
| {AArch64::LDNPDi, 486, 1 }, |
| {AArch64::LDNPQi, 487, 1 }, |
| {AArch64::LDNPSi, 488, 1 }, |
| {AArch64::LDNPWi, 489, 1 }, |
| {AArch64::LDNPXi, 490, 1 }, |
| {AArch64::LDNT1B_2Z_IMM, 491, 1 }, |
| {AArch64::LDNT1B_4Z_IMM, 492, 1 }, |
| {AArch64::LDNT1B_VG2_M2ZPXI, 493, 1 }, |
| {AArch64::LDNT1B_VG4_M4ZPXI, 494, 1 }, |
| {AArch64::LDNT1B_ZRI, 495, 1 }, |
| {AArch64::LDNT1B_ZZR_D_REAL, 496, 1 }, |
| {AArch64::LDNT1B_ZZR_S_REAL, 497, 1 }, |
| {AArch64::LDNT1D_2Z_IMM, 498, 1 }, |
| {AArch64::LDNT1D_4Z_IMM, 499, 1 }, |
| {AArch64::LDNT1D_VG2_M2ZPXI, 500, 1 }, |
| {AArch64::LDNT1D_VG4_M4ZPXI, 501, 1 }, |
| {AArch64::LDNT1D_ZRI, 502, 1 }, |
| {AArch64::LDNT1D_ZZR_D_REAL, 503, 1 }, |
| {AArch64::LDNT1H_2Z_IMM, 504, 1 }, |
| {AArch64::LDNT1H_4Z_IMM, 505, 1 }, |
| {AArch64::LDNT1H_VG2_M2ZPXI, 506, 1 }, |
| {AArch64::LDNT1H_VG4_M4ZPXI, 507, 1 }, |
| {AArch64::LDNT1H_ZRI, 508, 1 }, |
| {AArch64::LDNT1H_ZZR_D_REAL, 509, 1 }, |
| {AArch64::LDNT1H_ZZR_S_REAL, 510, 1 }, |
| {AArch64::LDNT1SB_ZZR_D_REAL, 511, 1 }, |
| {AArch64::LDNT1SB_ZZR_S_REAL, 512, 1 }, |
| {AArch64::LDNT1SH_ZZR_D_REAL, 513, 1 }, |
| {AArch64::LDNT1SH_ZZR_S_REAL, 514, 1 }, |
| {AArch64::LDNT1SW_ZZR_D_REAL, 515, 1 }, |
| {AArch64::LDNT1W_2Z_IMM, 516, 1 }, |
| {AArch64::LDNT1W_4Z_IMM, 517, 1 }, |
| {AArch64::LDNT1W_VG2_M2ZPXI, 518, 1 }, |
| {AArch64::LDNT1W_VG4_M4ZPXI, 519, 1 }, |
| {AArch64::LDNT1W_ZRI, 520, 1 }, |
| {AArch64::LDNT1W_ZZR_D_REAL, 521, 1 }, |
| {AArch64::LDNT1W_ZZR_S_REAL, 522, 1 }, |
| {AArch64::LDPDi, 523, 1 }, |
| {AArch64::LDPQi, 524, 1 }, |
| {AArch64::LDPSWi, 525, 1 }, |
| {AArch64::LDPSi, 526, 1 }, |
| {AArch64::LDPWi, 527, 1 }, |
| {AArch64::LDPXi, 528, 1 }, |
| {AArch64::LDRAAindexed, 529, 1 }, |
| {AArch64::LDRABindexed, 530, 1 }, |
| {AArch64::LDRBBroX, 531, 1 }, |
| {AArch64::LDRBBui, 532, 1 }, |
| {AArch64::LDRBroX, 533, 1 }, |
| {AArch64::LDRBui, 534, 1 }, |
| {AArch64::LDRDroX, 535, 1 }, |
| {AArch64::LDRDui, 536, 1 }, |
| {AArch64::LDRHHroX, 537, 1 }, |
| {AArch64::LDRHHui, 538, 1 }, |
| {AArch64::LDRHroX, 539, 1 }, |
| {AArch64::LDRHui, 540, 1 }, |
| {AArch64::LDRQroX, 541, 1 }, |
| {AArch64::LDRQui, 542, 1 }, |
| {AArch64::LDRSBWroX, 543, 1 }, |
| {AArch64::LDRSBWui, 544, 1 }, |
| {AArch64::LDRSBXroX, 545, 1 }, |
| {AArch64::LDRSBXui, 546, 1 }, |
| {AArch64::LDRSHWroX, 547, 1 }, |
| {AArch64::LDRSHWui, 548, 1 }, |
| {AArch64::LDRSHXroX, 549, 1 }, |
| {AArch64::LDRSHXui, 550, 1 }, |
| {AArch64::LDRSWroX, 551, 1 }, |
| {AArch64::LDRSWui, 552, 1 }, |
| {AArch64::LDRSroX, 553, 1 }, |
| {AArch64::LDRSui, 554, 1 }, |
| {AArch64::LDRWroX, 555, 1 }, |
| {AArch64::LDRWui, 556, 1 }, |
| {AArch64::LDRXroX, 557, 1 }, |
| {AArch64::LDRXui, 558, 1 }, |
| {AArch64::LDR_PXI, 559, 1 }, |
| {AArch64::LDR_ZA, 560, 1 }, |
| {AArch64::LDR_ZXI, 561, 1 }, |
| {AArch64::LDSETB, 562, 1 }, |
| {AArch64::LDSETH, 563, 1 }, |
| {AArch64::LDSETLB, 564, 1 }, |
| {AArch64::LDSETLH, 565, 1 }, |
| {AArch64::LDSETLW, 566, 1 }, |
| {AArch64::LDSETLX, 567, 1 }, |
| {AArch64::LDSETW, 568, 1 }, |
| {AArch64::LDSETX, 569, 1 }, |
| {AArch64::LDSMAXB, 570, 1 }, |
| {AArch64::LDSMAXH, 571, 1 }, |
| {AArch64::LDSMAXLB, 572, 1 }, |
| {AArch64::LDSMAXLH, 573, 1 }, |
| {AArch64::LDSMAXLW, 574, 1 }, |
| {AArch64::LDSMAXLX, 575, 1 }, |
| {AArch64::LDSMAXW, 576, 1 }, |
| {AArch64::LDSMAXX, 577, 1 }, |
| {AArch64::LDSMINB, 578, 1 }, |
| {AArch64::LDSMINH, 579, 1 }, |
| {AArch64::LDSMINLB, 580, 1 }, |
| {AArch64::LDSMINLH, 581, 1 }, |
| {AArch64::LDSMINLW, 582, 1 }, |
| {AArch64::LDSMINLX, 583, 1 }, |
| {AArch64::LDSMINW, 584, 1 }, |
| {AArch64::LDSMINX, 585, 1 }, |
| {AArch64::LDTRBi, 586, 1 }, |
| {AArch64::LDTRHi, 587, 1 }, |
| {AArch64::LDTRSBWi, 588, 1 }, |
| {AArch64::LDTRSBXi, 589, 1 }, |
| {AArch64::LDTRSHWi, 590, 1 }, |
| {AArch64::LDTRSHXi, 591, 1 }, |
| {AArch64::LDTRSWi, 592, 1 }, |
| {AArch64::LDTRWi, 593, 1 }, |
| {AArch64::LDTRXi, 594, 1 }, |
| {AArch64::LDUMAXB, 595, 1 }, |
| {AArch64::LDUMAXH, 596, 1 }, |
| {AArch64::LDUMAXLB, 597, 1 }, |
| {AArch64::LDUMAXLH, 598, 1 }, |
| {AArch64::LDUMAXLW, 599, 1 }, |
| {AArch64::LDUMAXLX, 600, 1 }, |
| {AArch64::LDUMAXW, 601, 1 }, |
| {AArch64::LDUMAXX, 602, 1 }, |
| {AArch64::LDUMINB, 603, 1 }, |
| {AArch64::LDUMINH, 604, 1 }, |
| {AArch64::LDUMINLB, 605, 1 }, |
| {AArch64::LDUMINLH, 606, 1 }, |
| {AArch64::LDUMINLW, 607, 1 }, |
| {AArch64::LDUMINLX, 608, 1 }, |
| {AArch64::LDUMINW, 609, 1 }, |
| {AArch64::LDUMINX, 610, 1 }, |
| {AArch64::LDURBBi, 611, 1 }, |
| {AArch64::LDURBi, 612, 1 }, |
| {AArch64::LDURDi, 613, 1 }, |
| {AArch64::LDURHHi, 614, 1 }, |
| {AArch64::LDURHi, 615, 1 }, |
| {AArch64::LDURQi, 616, 1 }, |
| {AArch64::LDURSBWi, 617, 1 }, |
| {AArch64::LDURSBXi, 618, 1 }, |
| {AArch64::LDURSHWi, 619, 1 }, |
| {AArch64::LDURSHXi, 620, 1 }, |
| {AArch64::LDURSWi, 621, 1 }, |
| {AArch64::LDURSi, 622, 1 }, |
| {AArch64::LDURWi, 623, 1 }, |
| {AArch64::LDURXi, 624, 1 }, |
| {AArch64::MADDWrrr, 625, 1 }, |
| {AArch64::MADDXrrr, 626, 1 }, |
| {AArch64::MOVA_2ZMXI_H_B, 627, 1 }, |
| {AArch64::MOVA_2ZMXI_H_D, 628, 1 }, |
| {AArch64::MOVA_2ZMXI_H_H, 629, 1 }, |
| {AArch64::MOVA_2ZMXI_H_S, 630, 1 }, |
| {AArch64::MOVA_2ZMXI_V_B, 631, 1 }, |
| {AArch64::MOVA_2ZMXI_V_D, 632, 1 }, |
| {AArch64::MOVA_2ZMXI_V_H, 633, 1 }, |
| {AArch64::MOVA_2ZMXI_V_S, 634, 1 }, |
| {AArch64::MOVA_4ZMXI_H_B, 635, 1 }, |
| {AArch64::MOVA_4ZMXI_H_D, 636, 1 }, |
| {AArch64::MOVA_4ZMXI_H_H, 637, 1 }, |
| {AArch64::MOVA_4ZMXI_H_S, 638, 1 }, |
| {AArch64::MOVA_4ZMXI_V_B, 639, 1 }, |
| {AArch64::MOVA_4ZMXI_V_D, 640, 1 }, |
| {AArch64::MOVA_4ZMXI_V_H, 641, 1 }, |
| {AArch64::MOVA_4ZMXI_V_S, 642, 1 }, |
| {AArch64::MOVA_MXI2Z_H_B, 643, 1 }, |
| {AArch64::MOVA_MXI2Z_H_D, 644, 1 }, |
| {AArch64::MOVA_MXI2Z_H_H, 645, 1 }, |
| {AArch64::MOVA_MXI2Z_H_S, 646, 1 }, |
| {AArch64::MOVA_MXI2Z_V_B, 647, 1 }, |
| {AArch64::MOVA_MXI2Z_V_D, 648, 1 }, |
| {AArch64::MOVA_MXI2Z_V_H, 649, 1 }, |
| {AArch64::MOVA_MXI2Z_V_S, 650, 1 }, |
| {AArch64::MOVA_MXI4Z_H_B, 651, 1 }, |
| {AArch64::MOVA_MXI4Z_H_D, 652, 1 }, |
| {AArch64::MOVA_MXI4Z_H_H, 653, 1 }, |
| {AArch64::MOVA_MXI4Z_H_S, 654, 1 }, |
| {AArch64::MOVA_MXI4Z_V_B, 655, 1 }, |
| {AArch64::MOVA_MXI4Z_V_D, 656, 1 }, |
| {AArch64::MOVA_MXI4Z_V_H, 657, 1 }, |
| {AArch64::MOVA_MXI4Z_V_S, 658, 1 }, |
| {AArch64::MOVA_VG2_2ZMXI, 659, 1 }, |
| {AArch64::MOVA_VG2_MXI2Z, 660, 1 }, |
| {AArch64::MOVA_VG4_4ZMXI, 661, 1 }, |
| {AArch64::MOVA_VG4_MXI4Z, 662, 1 }, |
| {AArch64::MSRpstatesvcrImm1, 663, 6 }, |
| {AArch64::MSUBWrrr, 669, 1 }, |
| {AArch64::MSUBXrrr, 670, 1 }, |
| {AArch64::NOTv16i8, 671, 1 }, |
| {AArch64::NOTv8i8, 672, 1 }, |
| {AArch64::ORNWrs, 673, 3 }, |
| {AArch64::ORNXrs, 676, 3 }, |
| {AArch64::ORRS_PPzPP, 679, 1 }, |
| {AArch64::ORRWrs, 680, 2 }, |
| {AArch64::ORRXrs, 682, 2 }, |
| {AArch64::ORR_PPzPP, 684, 1 }, |
| {AArch64::ORR_ZI, 685, 3 }, |
| {AArch64::ORR_ZZZ, 688, 1 }, |
| {AArch64::ORRv16i8, 689, 1 }, |
| {AArch64::ORRv8i8, 690, 1 }, |
| {AArch64::PACIA1716, 691, 1 }, |
| {AArch64::PACIASP, 692, 1 }, |
| {AArch64::PACIAZ, 693, 1 }, |
| {AArch64::PACIB1716, 694, 1 }, |
| {AArch64::PACIBSP, 695, 1 }, |
| {AArch64::PACIBZ, 696, 1 }, |
| {AArch64::PMOV_PZI_B, 697, 1 }, |
| {AArch64::PMOV_ZIP_B, 698, 1 }, |
| {AArch64::PRFB_D_PZI, 699, 1 }, |
| {AArch64::PRFB_PRI, 700, 1 }, |
| {AArch64::PRFB_S_PZI, 701, 1 }, |
| {AArch64::PRFD_D_PZI, 702, 1 }, |
| {AArch64::PRFD_PRI, 703, 1 }, |
| {AArch64::PRFD_S_PZI, 704, 1 }, |
| {AArch64::PRFH_D_PZI, 705, 1 }, |
| {AArch64::PRFH_PRI, 706, 1 }, |
| {AArch64::PRFH_S_PZI, 707, 1 }, |
| {AArch64::PRFMroX, 708, 1 }, |
| {AArch64::PRFMui, 709, 1 }, |
| {AArch64::PRFUMi, 710, 1 }, |
| {AArch64::PRFW_D_PZI, 711, 1 }, |
| {AArch64::PRFW_PRI, 712, 1 }, |
| {AArch64::PRFW_S_PZI, 713, 1 }, |
| {AArch64::PTRUES_B, 714, 1 }, |
| {AArch64::PTRUES_D, 715, 1 }, |
| {AArch64::PTRUES_H, 716, 1 }, |
| {AArch64::PTRUES_S, 717, 1 }, |
| {AArch64::PTRUE_B, 718, 1 }, |
| {AArch64::PTRUE_D, 719, 1 }, |
| {AArch64::PTRUE_H, 720, 1 }, |
| {AArch64::PTRUE_S, 721, 1 }, |
| {AArch64::RET, 722, 1 }, |
| {AArch64::SBCSWr, 723, 1 }, |
| {AArch64::SBCSXr, 724, 1 }, |
| {AArch64::SBCWr, 725, 1 }, |
| {AArch64::SBCXr, 726, 1 }, |
| {AArch64::SBFMWri, 727, 3 }, |
| {AArch64::SBFMXri, 730, 4 }, |
| {AArch64::SEL_PPPP, 734, 1 }, |
| {AArch64::SEL_ZPZZ_B, 735, 1 }, |
| {AArch64::SEL_ZPZZ_D, 736, 1 }, |
| {AArch64::SEL_ZPZZ_H, 737, 1 }, |
| {AArch64::SEL_ZPZZ_S, 738, 1 }, |
| {AArch64::SMADDLrrr, 739, 1 }, |
| {AArch64::SMSUBLrrr, 740, 1 }, |
| {AArch64::SQDECB_XPiI, 741, 2 }, |
| {AArch64::SQDECB_XPiWdI, 743, 2 }, |
| {AArch64::SQDECD_XPiI, 745, 2 }, |
| {AArch64::SQDECD_XPiWdI, 747, 2 }, |
| {AArch64::SQDECD_ZPiI, 749, 2 }, |
| {AArch64::SQDECH_XPiI, 751, 2 }, |
| {AArch64::SQDECH_XPiWdI, 753, 2 }, |
| {AArch64::SQDECH_ZPiI, 755, 2 }, |
| {AArch64::SQDECW_XPiI, 757, 2 }, |
| {AArch64::SQDECW_XPiWdI, 759, 2 }, |
| {AArch64::SQDECW_ZPiI, 761, 2 }, |
| {AArch64::SQINCB_XPiI, 763, 2 }, |
| {AArch64::SQINCB_XPiWdI, 765, 2 }, |
| {AArch64::SQINCD_XPiI, 767, 2 }, |
| {AArch64::SQINCD_XPiWdI, 769, 2 }, |
| {AArch64::SQINCD_ZPiI, 771, 2 }, |
| {AArch64::SQINCH_XPiI, 773, 2 }, |
| {AArch64::SQINCH_XPiWdI, 775, 2 }, |
| {AArch64::SQINCH_ZPiI, 777, 2 }, |
| {AArch64::SQINCW_XPiI, 779, 2 }, |
| {AArch64::SQINCW_XPiWdI, 781, 2 }, |
| {AArch64::SQINCW_ZPiI, 783, 2 }, |
| {AArch64::SST1B_D_IMM, 785, 1 }, |
| {AArch64::SST1B_S_IMM, 786, 1 }, |
| {AArch64::SST1D_IMM, 787, 1 }, |
| {AArch64::SST1H_D_IMM, 788, 1 }, |
| {AArch64::SST1H_S_IMM, 789, 1 }, |
| {AArch64::SST1Q, 790, 1 }, |
| {AArch64::SST1W_D_IMM, 791, 1 }, |
| {AArch64::SST1W_IMM, 792, 1 }, |
| {AArch64::ST1B_2Z_IMM, 793, 1 }, |
| {AArch64::ST1B_4Z_IMM, 794, 1 }, |
| {AArch64::ST1B_D_IMM, 795, 1 }, |
| {AArch64::ST1B_H_IMM, 796, 1 }, |
| {AArch64::ST1B_IMM, 797, 1 }, |
| {AArch64::ST1B_S_IMM, 798, 1 }, |
| {AArch64::ST1B_VG2_M2ZPXI, 799, 1 }, |
| {AArch64::ST1B_VG4_M4ZPXI, 800, 1 }, |
| {AArch64::ST1D_2Z_IMM, 801, 1 }, |
| {AArch64::ST1D_4Z_IMM, 802, 1 }, |
| {AArch64::ST1D_IMM, 803, 1 }, |
| {AArch64::ST1D_Q_IMM, 804, 1 }, |
| {AArch64::ST1D_VG2_M2ZPXI, 805, 1 }, |
| {AArch64::ST1D_VG4_M4ZPXI, 806, 1 }, |
| {AArch64::ST1Fourv16b_POST, 807, 1 }, |
| {AArch64::ST1Fourv1d_POST, 808, 1 }, |
| {AArch64::ST1Fourv2d_POST, 809, 1 }, |
| {AArch64::ST1Fourv2s_POST, 810, 1 }, |
| {AArch64::ST1Fourv4h_POST, 811, 1 }, |
| {AArch64::ST1Fourv4s_POST, 812, 1 }, |
| {AArch64::ST1Fourv8b_POST, 813, 1 }, |
| {AArch64::ST1Fourv8h_POST, 814, 1 }, |
| {AArch64::ST1H_2Z_IMM, 815, 1 }, |
| {AArch64::ST1H_4Z_IMM, 816, 1 }, |
| {AArch64::ST1H_D_IMM, 817, 1 }, |
| {AArch64::ST1H_IMM, 818, 1 }, |
| {AArch64::ST1H_S_IMM, 819, 1 }, |
| {AArch64::ST1H_VG2_M2ZPXI, 820, 1 }, |
| {AArch64::ST1H_VG4_M4ZPXI, 821, 1 }, |
| {AArch64::ST1Onev16b_POST, 822, 1 }, |
| {AArch64::ST1Onev1d_POST, 823, 1 }, |
| {AArch64::ST1Onev2d_POST, 824, 1 }, |
| {AArch64::ST1Onev2s_POST, 825, 1 }, |
| {AArch64::ST1Onev4h_POST, 826, 1 }, |
| {AArch64::ST1Onev4s_POST, 827, 1 }, |
| {AArch64::ST1Onev8b_POST, 828, 1 }, |
| {AArch64::ST1Onev8h_POST, 829, 1 }, |
| {AArch64::ST1Threev16b_POST, 830, 1 }, |
| {AArch64::ST1Threev1d_POST, 831, 1 }, |
| {AArch64::ST1Threev2d_POST, 832, 1 }, |
| {AArch64::ST1Threev2s_POST, 833, 1 }, |
| {AArch64::ST1Threev4h_POST, 834, 1 }, |
| {AArch64::ST1Threev4s_POST, 835, 1 }, |
| {AArch64::ST1Threev8b_POST, 836, 1 }, |
| {AArch64::ST1Threev8h_POST, 837, 1 }, |
| {AArch64::ST1Twov16b_POST, 838, 1 }, |
| {AArch64::ST1Twov1d_POST, 839, 1 }, |
| {AArch64::ST1Twov2d_POST, 840, 1 }, |
| {AArch64::ST1Twov2s_POST, 841, 1 }, |
| {AArch64::ST1Twov4h_POST, 842, 1 }, |
| {AArch64::ST1Twov4s_POST, 843, 1 }, |
| {AArch64::ST1Twov8b_POST, 844, 1 }, |
| {AArch64::ST1Twov8h_POST, 845, 1 }, |
| {AArch64::ST1W_2Z_IMM, 846, 1 }, |
| {AArch64::ST1W_4Z_IMM, 847, 1 }, |
| {AArch64::ST1W_D_IMM, 848, 1 }, |
| {AArch64::ST1W_IMM, 849, 1 }, |
| {AArch64::ST1W_Q_IMM, 850, 1 }, |
| {AArch64::ST1W_VG2_M2ZPXI, 851, 1 }, |
| {AArch64::ST1W_VG4_M4ZPXI, 852, 1 }, |
| {AArch64::ST1_MXIPXX_H_B, 853, 1 }, |
| {AArch64::ST1_MXIPXX_H_D, 854, 1 }, |
| {AArch64::ST1_MXIPXX_H_H, 855, 1 }, |
| {AArch64::ST1_MXIPXX_H_Q, 856, 1 }, |
| {AArch64::ST1_MXIPXX_H_S, 857, 1 }, |
| {AArch64::ST1_MXIPXX_V_B, 858, 1 }, |
| {AArch64::ST1_MXIPXX_V_D, 859, 1 }, |
| {AArch64::ST1_MXIPXX_V_H, 860, 1 }, |
| {AArch64::ST1_MXIPXX_V_Q, 861, 1 }, |
| {AArch64::ST1_MXIPXX_V_S, 862, 1 }, |
| {AArch64::ST1i16_POST, 863, 1 }, |
| {AArch64::ST1i32_POST, 864, 1 }, |
| {AArch64::ST1i64_POST, 865, 1 }, |
| {AArch64::ST1i8_POST, 866, 1 }, |
| {AArch64::ST2B_IMM, 867, 1 }, |
| {AArch64::ST2D_IMM, 868, 1 }, |
| {AArch64::ST2GOffset, 869, 1 }, |
| {AArch64::ST2H_IMM, 870, 1 }, |
| {AArch64::ST2Q_IMM, 871, 1 }, |
| {AArch64::ST2Twov16b_POST, 872, 1 }, |
| {AArch64::ST2Twov2d_POST, 873, 1 }, |
| {AArch64::ST2Twov2s_POST, 874, 1 }, |
| {AArch64::ST2Twov4h_POST, 875, 1 }, |
| {AArch64::ST2Twov4s_POST, 876, 1 }, |
| {AArch64::ST2Twov8b_POST, 877, 1 }, |
| {AArch64::ST2Twov8h_POST, 878, 1 }, |
| {AArch64::ST2W_IMM, 879, 1 }, |
| {AArch64::ST2i16_POST, 880, 1 }, |
| {AArch64::ST2i32_POST, 881, 1 }, |
| {AArch64::ST2i64_POST, 882, 1 }, |
| {AArch64::ST2i8_POST, 883, 1 }, |
| {AArch64::ST3B_IMM, 884, 1 }, |
| {AArch64::ST3D_IMM, 885, 1 }, |
| {AArch64::ST3H_IMM, 886, 1 }, |
| {AArch64::ST3Q_IMM, 887, 1 }, |
| {AArch64::ST3Threev16b_POST, 888, 1 }, |
| {AArch64::ST3Threev2d_POST, 889, 1 }, |
| {AArch64::ST3Threev2s_POST, 890, 1 }, |
| {AArch64::ST3Threev4h_POST, 891, 1 }, |
| {AArch64::ST3Threev4s_POST, 892, 1 }, |
| {AArch64::ST3Threev8b_POST, 893, 1 }, |
| {AArch64::ST3Threev8h_POST, 894, 1 }, |
| {AArch64::ST3W_IMM, 895, 1 }, |
| {AArch64::ST3i16_POST, 896, 1 }, |
| {AArch64::ST3i32_POST, 897, 1 }, |
| {AArch64::ST3i64_POST, 898, 1 }, |
| {AArch64::ST3i8_POST, 899, 1 }, |
| {AArch64::ST4B_IMM, 900, 1 }, |
| {AArch64::ST4D_IMM, 901, 1 }, |
| {AArch64::ST4Fourv16b_POST, 902, 1 }, |
| {AArch64::ST4Fourv2d_POST, 903, 1 }, |
| {AArch64::ST4Fourv2s_POST, 904, 1 }, |
| {AArch64::ST4Fourv4h_POST, 905, 1 }, |
| {AArch64::ST4Fourv4s_POST, 906, 1 }, |
| {AArch64::ST4Fourv8b_POST, 907, 1 }, |
| {AArch64::ST4Fourv8h_POST, 908, 1 }, |
| {AArch64::ST4H_IMM, 909, 1 }, |
| {AArch64::ST4Q_IMM, 910, 1 }, |
| {AArch64::ST4W_IMM, 911, 1 }, |
| {AArch64::ST4i16_POST, 912, 1 }, |
| {AArch64::ST4i32_POST, 913, 1 }, |
| {AArch64::ST4i64_POST, 914, 1 }, |
| {AArch64::ST4i8_POST, 915, 1 }, |
| {AArch64::STGOffset, 916, 1 }, |
| {AArch64::STGPi, 917, 1 }, |
| {AArch64::STLURBi, 918, 1 }, |
| {AArch64::STLURHi, 919, 1 }, |
| {AArch64::STLURWi, 920, 1 }, |
| {AArch64::STLURXi, 921, 1 }, |
| {AArch64::STLURbi, 922, 1 }, |
| {AArch64::STLURdi, 923, 1 }, |
| {AArch64::STLURhi, 924, 1 }, |
| {AArch64::STLURqi, 925, 1 }, |
| {AArch64::STLURsi, 926, 1 }, |
| {AArch64::STNPDi, 927, 1 }, |
| {AArch64::STNPQi, 928, 1 }, |
| {AArch64::STNPSi, 929, 1 }, |
| {AArch64::STNPWi, 930, 1 }, |
| {AArch64::STNPXi, 931, 1 }, |
| {AArch64::STNT1B_2Z_IMM, 932, 1 }, |
| {AArch64::STNT1B_4Z_IMM, 933, 1 }, |
| {AArch64::STNT1B_VG2_M2ZPXI, 934, 1 }, |
| {AArch64::STNT1B_VG4_M4ZPXI, 935, 1 }, |
| {AArch64::STNT1B_ZRI, 936, 1 }, |
| {AArch64::STNT1B_ZZR_D_REAL, 937, 1 }, |
| {AArch64::STNT1B_ZZR_S_REAL, 938, 1 }, |
| {AArch64::STNT1D_2Z_IMM, 939, 1 }, |
| {AArch64::STNT1D_4Z_IMM, 940, 1 }, |
| {AArch64::STNT1D_VG2_M2ZPXI, 941, 1 }, |
| {AArch64::STNT1D_VG4_M4ZPXI, 942, 1 }, |
| {AArch64::STNT1D_ZRI, 943, 1 }, |
| {AArch64::STNT1D_ZZR_D_REAL, 944, 1 }, |
| {AArch64::STNT1H_2Z_IMM, 945, 1 }, |
| {AArch64::STNT1H_4Z_IMM, 946, 1 }, |
| {AArch64::STNT1H_VG2_M2ZPXI, 947, 1 }, |
| {AArch64::STNT1H_VG4_M4ZPXI, 948, 1 }, |
| {AArch64::STNT1H_ZRI, 949, 1 }, |
| {AArch64::STNT1H_ZZR_D_REAL, 950, 1 }, |
| {AArch64::STNT1H_ZZR_S_REAL, 951, 1 }, |
| {AArch64::STNT1W_2Z_IMM, 952, 1 }, |
| {AArch64::STNT1W_4Z_IMM, 953, 1 }, |
| {AArch64::STNT1W_VG2_M2ZPXI, 954, 1 }, |
| {AArch64::STNT1W_VG4_M4ZPXI, 955, 1 }, |
| {AArch64::STNT1W_ZRI, 956, 1 }, |
| {AArch64::STNT1W_ZZR_D_REAL, 957, 1 }, |
| {AArch64::STNT1W_ZZR_S_REAL, 958, 1 }, |
| {AArch64::STPDi, 959, 1 }, |
| {AArch64::STPQi, 960, 1 }, |
| {AArch64::STPSi, 961, 1 }, |
| {AArch64::STPWi, 962, 1 }, |
| {AArch64::STPXi, 963, 1 }, |
| {AArch64::STRBBroX, 964, 1 }, |
| {AArch64::STRBBui, 965, 1 }, |
| {AArch64::STRBroX, 966, 1 }, |
| {AArch64::STRBui, 967, 1 }, |
| {AArch64::STRDroX, 968, 1 }, |
| {AArch64::STRDui, 969, 1 }, |
| {AArch64::STRHHroX, 970, 1 }, |
| {AArch64::STRHHui, 971, 1 }, |
| {AArch64::STRHroX, 972, 1 }, |
| {AArch64::STRHui, 973, 1 }, |
| {AArch64::STRQroX, 974, 1 }, |
| {AArch64::STRQui, 975, 1 }, |
| {AArch64::STRSroX, 976, 1 }, |
| {AArch64::STRSui, 977, 1 }, |
| {AArch64::STRWroX, 978, 1 }, |
| {AArch64::STRWui, 979, 1 }, |
| {AArch64::STRXroX, 980, 1 }, |
| {AArch64::STRXui, 981, 1 }, |
| {AArch64::STR_PXI, 982, 1 }, |
| {AArch64::STR_ZA, 983, 1 }, |
| {AArch64::STR_ZXI, 984, 1 }, |
| {AArch64::STTRBi, 985, 1 }, |
| {AArch64::STTRHi, 986, 1 }, |
| {AArch64::STTRWi, 987, 1 }, |
| {AArch64::STTRXi, 988, 1 }, |
| {AArch64::STURBBi, 989, 1 }, |
| {AArch64::STURBi, 990, 1 }, |
| {AArch64::STURDi, 991, 1 }, |
| {AArch64::STURHHi, 992, 1 }, |
| {AArch64::STURHi, 993, 1 }, |
| {AArch64::STURQi, 994, 1 }, |
| {AArch64::STURSi, 995, 1 }, |
| {AArch64::STURWi, 996, 1 }, |
| {AArch64::STURXi, 997, 1 }, |
| {AArch64::STZ2GOffset, 998, 1 }, |
| {AArch64::STZGOffset, 999, 1 }, |
| {AArch64::SUBSWri, 1000, 1 }, |
| {AArch64::SUBSWrs, 1001, 5 }, |
| {AArch64::SUBSWrx, 1006, 3 }, |
| {AArch64::SUBSXri, 1009, 1 }, |
| {AArch64::SUBSXrs, 1010, 5 }, |
| {AArch64::SUBSXrx, 1015, 1 }, |
| {AArch64::SUBSXrx64, 1016, 3 }, |
| {AArch64::SUBWrs, 1019, 3 }, |
| {AArch64::SUBWrx, 1022, 2 }, |
| {AArch64::SUBXrs, 1024, 3 }, |
| {AArch64::SUBXrx64, 1027, 2 }, |
| {AArch64::SYSPxt_XZR, 1029, 1 }, |
| {AArch64::SYSxt, 1030, 1 }, |
| {AArch64::UBFMWri, 1031, 3 }, |
| {AArch64::UBFMXri, 1034, 4 }, |
| {AArch64::UMADDLrrr, 1038, 1 }, |
| {AArch64::UMOVvi32, 1039, 1 }, |
| {AArch64::UMOVvi32_idx0, 1040, 1 }, |
| {AArch64::UMOVvi64, 1041, 1 }, |
| {AArch64::UMOVvi64_idx0, 1042, 1 }, |
| {AArch64::UMSUBLrrr, 1043, 1 }, |
| {AArch64::UQDECB_WPiI, 1044, 2 }, |
| {AArch64::UQDECB_XPiI, 1046, 2 }, |
| {AArch64::UQDECD_WPiI, 1048, 2 }, |
| {AArch64::UQDECD_XPiI, 1050, 2 }, |
| {AArch64::UQDECD_ZPiI, 1052, 2 }, |
| {AArch64::UQDECH_WPiI, 1054, 2 }, |
| {AArch64::UQDECH_XPiI, 1056, 2 }, |
| {AArch64::UQDECH_ZPiI, 1058, 2 }, |
| {AArch64::UQDECW_WPiI, 1060, 2 }, |
| {AArch64::UQDECW_XPiI, 1062, 2 }, |
| {AArch64::UQDECW_ZPiI, 1064, 2 }, |
| {AArch64::UQINCB_WPiI, 1066, 2 }, |
| {AArch64::UQINCB_XPiI, 1068, 2 }, |
| {AArch64::UQINCD_WPiI, 1070, 2 }, |
| {AArch64::UQINCD_XPiI, 1072, 2 }, |
| {AArch64::UQINCD_ZPiI, 1074, 2 }, |
| {AArch64::UQINCH_WPiI, 1076, 2 }, |
| {AArch64::UQINCH_XPiI, 1078, 2 }, |
| {AArch64::UQINCH_ZPiI, 1080, 2 }, |
| {AArch64::UQINCW_WPiI, 1082, 2 }, |
| {AArch64::UQINCW_XPiI, 1084, 2 }, |
| {AArch64::UQINCW_ZPiI, 1086, 2 }, |
| {AArch64::XPACLRI, 1088, 1 }, |
| {AArch64::ZERO_M, 1089, 15 }, |
| }; |
| |
| static const AliasPattern Patterns[] = { |
| // AArch64::ADDSWri - 0 |
| {0, 0, 4, 2 }, |
| // AArch64::ADDSWrs - 1 |
| {13, 2, 4, 4 }, |
| {24, 6, 4, 3 }, |
| {39, 9, 4, 4 }, |
| // AArch64::ADDSWrx - 4 |
| {13, 13, 4, 4 }, |
| {55, 17, 4, 3 }, |
| {39, 20, 4, 4 }, |
| // AArch64::ADDSXri - 7 |
| {0, 24, 4, 2 }, |
| // AArch64::ADDSXrs - 8 |
| {13, 26, 4, 4 }, |
| {24, 30, 4, 3 }, |
| {39, 33, 4, 4 }, |
| // AArch64::ADDSXrx - 11 |
| {55, 37, 4, 3 }, |
| // AArch64::ADDSXrx64 - 12 |
| {13, 40, 4, 4 }, |
| {55, 44, 4, 3 }, |
| {39, 47, 4, 4 }, |
| // AArch64::ADDWri - 15 |
| {70, 51, 4, 4 }, |
| {70, 55, 4, 4 }, |
| // AArch64::ADDWrs - 17 |
| {81, 59, 4, 4 }, |
| // AArch64::ADDWrx - 18 |
| {81, 63, 4, 4 }, |
| {81, 67, 4, 4 }, |
| // AArch64::ADDXri - 20 |
| {70, 71, 4, 4 }, |
| {70, 75, 4, 4 }, |
| // AArch64::ADDXrs - 22 |
| {81, 79, 4, 4 }, |
| // AArch64::ADDXrx64 - 23 |
| {81, 83, 4, 4 }, |
| {81, 87, 4, 4 }, |
| // AArch64::ANDSWri - 25 |
| {96, 91, 3, 2 }, |
| // AArch64::ANDSWrs - 26 |
| {109, 93, 4, 4 }, |
| {120, 97, 4, 3 }, |
| {135, 100, 4, 4 }, |
| // AArch64::ANDSXri - 29 |
| {151, 104, 3, 2 }, |
| // AArch64::ANDSXrs - 30 |
| {109, 106, 4, 4 }, |
| {120, 110, 4, 3 }, |
| {135, 113, 4, 4 }, |
| // AArch64::ANDS_PPzPP - 33 |
| {164, 117, 4, 8 }, |
| // AArch64::ANDWrs - 34 |
| {188, 125, 4, 4 }, |
| // AArch64::ANDXrs - 35 |
| {188, 129, 4, 4 }, |
| // AArch64::AND_PPzPP - 36 |
| {203, 133, 4, 8 }, |
| // AArch64::AND_ZI - 37 |
| {226, 141, 3, 7 }, |
| {247, 148, 3, 7 }, |
| {268, 155, 3, 7 }, |
| // AArch64::AUTIA1716 - 40 |
| {289, 162, 0, 3 }, |
| // AArch64::AUTIASP - 41 |
| {299, 165, 0, 3 }, |
| // AArch64::AUTIAZ - 42 |
| {307, 168, 0, 3 }, |
| // AArch64::AUTIB1716 - 43 |
| {314, 171, 0, 3 }, |
| // AArch64::AUTIBSP - 44 |
| {324, 174, 0, 3 }, |
| // AArch64::AUTIBZ - 45 |
| {332, 177, 0, 3 }, |
| // AArch64::BICSWrs - 46 |
| {339, 180, 4, 4 }, |
| // AArch64::BICSXrs - 47 |
| {339, 184, 4, 4 }, |
| // AArch64::BICWrs - 48 |
| {355, 188, 4, 4 }, |
| // AArch64::BICXrs - 49 |
| {355, 192, 4, 4 }, |
| // AArch64::CLREX - 50 |
| {370, 196, 1, 1 }, |
| // AArch64::CNTB_XPiI - 51 |
| {376, 197, 3, 7 }, |
| {384, 204, 3, 7 }, |
| // AArch64::CNTD_XPiI - 53 |
| {398, 211, 3, 7 }, |
| {406, 218, 3, 7 }, |
| // AArch64::CNTH_XPiI - 55 |
| {420, 225, 3, 7 }, |
| {428, 232, 3, 7 }, |
| // AArch64::CNTW_XPiI - 57 |
| {442, 239, 3, 7 }, |
| {450, 246, 3, 7 }, |
| // AArch64::CPY_ZPmI_B - 59 |
| {464, 253, 5, 7 }, |
| // AArch64::CPY_ZPmI_D - 60 |
| {487, 260, 5, 7 }, |
| // AArch64::CPY_ZPmI_H - 61 |
| {510, 267, 5, 7 }, |
| // AArch64::CPY_ZPmI_S - 62 |
| {533, 274, 5, 7 }, |
| // AArch64::CPY_ZPmR_B - 63 |
| {556, 281, 4, 8 }, |
| // AArch64::CPY_ZPmR_D - 64 |
| {577, 289, 4, 8 }, |
| // AArch64::CPY_ZPmR_H - 65 |
| {598, 297, 4, 8 }, |
| // AArch64::CPY_ZPmR_S - 66 |
| {619, 305, 4, 8 }, |
| // AArch64::CPY_ZPmV_B - 67 |
| {556, 313, 4, 8 }, |
| // AArch64::CPY_ZPmV_D - 68 |
| {577, 321, 4, 8 }, |
| // AArch64::CPY_ZPmV_H - 69 |
| {598, 329, 4, 8 }, |
| // AArch64::CPY_ZPmV_S - 70 |
| {619, 337, 4, 8 }, |
| // AArch64::CPY_ZPzI_B - 71 |
| {640, 345, 4, 6 }, |
| // AArch64::CPY_ZPzI_D - 72 |
| {663, 351, 4, 6 }, |
| // AArch64::CPY_ZPzI_H - 73 |
| {686, 357, 4, 6 }, |
| // AArch64::CPY_ZPzI_S - 74 |
| {709, 363, 4, 6 }, |
| // AArch64::CSINCWr - 75 |
| {732, 369, 4, 4 }, |
| {746, 373, 4, 4 }, |
| // AArch64::CSINCXr - 77 |
| {732, 377, 4, 4 }, |
| {746, 381, 4, 4 }, |
| // AArch64::CSINVWr - 79 |
| {764, 385, 4, 4 }, |
| {779, 389, 4, 4 }, |
| // AArch64::CSINVXr - 81 |
| {764, 393, 4, 4 }, |
| {779, 397, 4, 4 }, |
| // AArch64::CSNEGWr - 83 |
| {797, 401, 4, 4 }, |
| // AArch64::CSNEGXr - 84 |
| {797, 405, 4, 4 }, |
| // AArch64::DCPS1 - 85 |
| {815, 409, 1, 1 }, |
| // AArch64::DCPS2 - 86 |
| {821, 410, 1, 1 }, |
| // AArch64::DCPS3 - 87 |
| {827, 411, 1, 4 }, |
| // AArch64::DECB_XPiI - 88 |
| {833, 415, 4, 8 }, |
| {841, 423, 4, 8 }, |
| // AArch64::DECD_XPiI - 90 |
| {855, 431, 4, 8 }, |
| {863, 439, 4, 8 }, |
| // AArch64::DECD_ZPiI - 92 |
| {877, 447, 4, 8 }, |
| {887, 455, 4, 8 }, |
| // AArch64::DECH_XPiI - 94 |
| {903, 463, 4, 8 }, |
| {911, 471, 4, 8 }, |
| // AArch64::DECH_ZPiI - 96 |
| {925, 479, 4, 8 }, |
| {935, 487, 4, 8 }, |
| // AArch64::DECW_XPiI - 98 |
| {951, 495, 4, 8 }, |
| {959, 503, 4, 8 }, |
| // AArch64::DECW_ZPiI - 100 |
| {973, 511, 4, 8 }, |
| {983, 519, 4, 8 }, |
| // AArch64::DSB - 102 |
| {999, 527, 1, 1 }, |
| {1004, 528, 1, 1 }, |
| {1010, 529, 1, 4 }, |
| // AArch64::DUPM_ZI - 105 |
| {1014, 533, 2, 6 }, |
| {1029, 539, 2, 6 }, |
| {1044, 545, 2, 6 }, |
| {1059, 551, 2, 6 }, |
| {1075, 557, 2, 6 }, |
| {1091, 563, 2, 6 }, |
| // AArch64::DUP_ZI_B - 111 |
| {1107, 569, 3, 5 }, |
| // AArch64::DUP_ZI_D - 112 |
| {1122, 574, 3, 5 }, |
| {1137, 579, 3, 7 }, |
| // AArch64::DUP_ZI_H - 114 |
| {1153, 586, 3, 5 }, |
| {1168, 591, 3, 7 }, |
| // AArch64::DUP_ZI_S - 116 |
| {1184, 598, 3, 5 }, |
| {1199, 603, 3, 7 }, |
| // AArch64::DUP_ZR_B - 118 |
| {1215, 610, 2, 6 }, |
| // AArch64::DUP_ZR_D - 119 |
| {1228, 616, 2, 6 }, |
| // AArch64::DUP_ZR_H - 120 |
| {1241, 622, 2, 6 }, |
| // AArch64::DUP_ZR_S - 121 |
| {1254, 628, 2, 6 }, |
| // AArch64::DUP_ZZI_B - 122 |
| {1267, 634, 3, 7 }, |
| {1282, 641, 3, 6 }, |
| // AArch64::DUP_ZZI_D - 124 |
| {1301, 647, 3, 7 }, |
| {1316, 654, 3, 6 }, |
| // AArch64::DUP_ZZI_H - 126 |
| {1335, 660, 3, 7 }, |
| {1350, 667, 3, 6 }, |
| // AArch64::DUP_ZZI_Q - 128 |
| {1369, 673, 3, 7 }, |
| {1384, 680, 3, 6 }, |
| // AArch64::DUP_ZZI_S - 130 |
| {1403, 686, 3, 7 }, |
| {1418, 693, 3, 6 }, |
| // AArch64::EONWrs - 132 |
| {1437, 699, 4, 4 }, |
| // AArch64::EONXrs - 133 |
| {1437, 703, 4, 4 }, |
| // AArch64::EORS_PPzPP - 134 |
| {1452, 707, 4, 8 }, |
| // AArch64::EORWrs - 135 |
| {1476, 715, 4, 4 }, |
| // AArch64::EORXrs - 136 |
| {1476, 719, 4, 4 }, |
| // AArch64::EOR_PPzPP - 137 |
| {1491, 723, 4, 8 }, |
| // AArch64::EOR_ZI - 138 |
| {1514, 731, 3, 7 }, |
| {1535, 738, 3, 7 }, |
| {1556, 745, 3, 7 }, |
| // AArch64::EXTRACT_ZPMXI_H_B - 141 |
| {1577, 752, 6, 8 }, |
| // AArch64::EXTRACT_ZPMXI_H_D - 142 |
| {1610, 760, 6, 8 }, |
| // AArch64::EXTRACT_ZPMXI_H_H - 143 |
| {1643, 768, 6, 8 }, |
| // AArch64::EXTRACT_ZPMXI_H_Q - 144 |
| {1676, 776, 6, 8 }, |
| // AArch64::EXTRACT_ZPMXI_H_S - 145 |
| {1709, 784, 6, 8 }, |
| // AArch64::EXTRACT_ZPMXI_V_B - 146 |
| {1742, 792, 6, 8 }, |
| // AArch64::EXTRACT_ZPMXI_V_D - 147 |
| {1775, 800, 6, 8 }, |
| // AArch64::EXTRACT_ZPMXI_V_H - 148 |
| {1808, 808, 6, 8 }, |
| // AArch64::EXTRACT_ZPMXI_V_Q - 149 |
| {1841, 816, 6, 8 }, |
| // AArch64::EXTRACT_ZPMXI_V_S - 150 |
| {1874, 824, 6, 8 }, |
| // AArch64::EXTRWrri - 151 |
| {1907, 832, 4, 3 }, |
| // AArch64::EXTRXrri - 152 |
| {1907, 835, 4, 3 }, |
| // AArch64::FCPY_ZPmI_D - 153 |
| {1922, 838, 4, 7 }, |
| // AArch64::FCPY_ZPmI_H - 154 |
| {1946, 845, 4, 7 }, |
| // AArch64::FCPY_ZPmI_S - 155 |
| {1970, 852, 4, 7 }, |
| // AArch64::FDUP_ZI_D - 156 |
| {1994, 859, 2, 5 }, |
| // AArch64::FDUP_ZI_H - 157 |
| {2010, 864, 2, 5 }, |
| // AArch64::FDUP_ZI_S - 158 |
| {2026, 869, 2, 5 }, |
| // AArch64::GLD1B_D_IMM_REAL - 159 |
| {2042, 874, 4, 7 }, |
| // AArch64::GLD1B_S_IMM_REAL - 160 |
| {2068, 881, 4, 7 }, |
| // AArch64::GLD1D_IMM_REAL - 161 |
| {2094, 888, 4, 7 }, |
| // AArch64::GLD1H_D_IMM_REAL - 162 |
| {2120, 895, 4, 7 }, |
| // AArch64::GLD1H_S_IMM_REAL - 163 |
| {2146, 902, 4, 7 }, |
| // AArch64::GLD1Q - 164 |
| {2172, 909, 4, 6 }, |
| // AArch64::GLD1SB_D_IMM_REAL - 165 |
| {2198, 915, 4, 7 }, |
| // AArch64::GLD1SB_S_IMM_REAL - 166 |
| {2225, 922, 4, 7 }, |
| // AArch64::GLD1SH_D_IMM_REAL - 167 |
| {2252, 929, 4, 7 }, |
| // AArch64::GLD1SH_S_IMM_REAL - 168 |
| {2279, 936, 4, 7 }, |
| // AArch64::GLD1SW_D_IMM_REAL - 169 |
| {2306, 943, 4, 7 }, |
| // AArch64::GLD1W_D_IMM_REAL - 170 |
| {2333, 950, 4, 7 }, |
| // AArch64::GLD1W_IMM_REAL - 171 |
| {2359, 957, 4, 7 }, |
| // AArch64::GLDFF1B_D_IMM_REAL - 172 |
| {2385, 964, 4, 7 }, |
| // AArch64::GLDFF1B_S_IMM_REAL - 173 |
| {2413, 971, 4, 7 }, |
| // AArch64::GLDFF1D_IMM_REAL - 174 |
| {2441, 978, 4, 7 }, |
| // AArch64::GLDFF1H_D_IMM_REAL - 175 |
| {2469, 985, 4, 7 }, |
| // AArch64::GLDFF1H_S_IMM_REAL - 176 |
| {2497, 992, 4, 7 }, |
| // AArch64::GLDFF1SB_D_IMM_REAL - 177 |
| {2525, 999, 4, 7 }, |
| // AArch64::GLDFF1SB_S_IMM_REAL - 178 |
| {2554, 1006, 4, 7 }, |
| // AArch64::GLDFF1SH_D_IMM_REAL - 179 |
| {2583, 1013, 4, 7 }, |
| // AArch64::GLDFF1SH_S_IMM_REAL - 180 |
| {2612, 1020, 4, 7 }, |
| // AArch64::GLDFF1SW_D_IMM_REAL - 181 |
| {2641, 1027, 4, 7 }, |
| // AArch64::GLDFF1W_D_IMM_REAL - 182 |
| {2670, 1034, 4, 7 }, |
| // AArch64::GLDFF1W_IMM_REAL - 183 |
| {2698, 1041, 4, 7 }, |
| // AArch64::HINT - 184 |
| {2726, 1048, 1, 1 }, |
| {2730, 1049, 1, 1 }, |
| {2736, 1050, 1, 1 }, |
| {2740, 1051, 1, 1 }, |
| {2744, 1052, 1, 1 }, |
| {2748, 1053, 1, 1 }, |
| {2753, 1054, 1, 1 }, |
| {2757, 1055, 1, 4 }, |
| {2761, 1059, 1, 1 }, |
| {2766, 1060, 1, 4 }, |
| {2770, 1064, 1, 4 }, |
| {2779, 1068, 1, 4 }, |
| {2788, 1072, 1, 4 }, |
| // AArch64::INCB_XPiI - 197 |
| {2795, 1076, 4, 8 }, |
| {2803, 1084, 4, 8 }, |
| // AArch64::INCD_XPiI - 199 |
| {2817, 1092, 4, 8 }, |
| {2825, 1100, 4, 8 }, |
| // AArch64::INCD_ZPiI - 201 |
| {2839, 1108, 4, 8 }, |
| {2849, 1116, 4, 8 }, |
| // AArch64::INCH_XPiI - 203 |
| {2865, 1124, 4, 8 }, |
| {2873, 1132, 4, 8 }, |
| // AArch64::INCH_ZPiI - 205 |
| {2887, 1140, 4, 8 }, |
| {2897, 1148, 4, 8 }, |
| // AArch64::INCW_XPiI - 207 |
| {2913, 1156, 4, 8 }, |
| {2921, 1164, 4, 8 }, |
| // AArch64::INCW_ZPiI - 209 |
| {2935, 1172, 4, 8 }, |
| {2945, 1180, 4, 8 }, |
| // AArch64::INSERT_MXIPZ_H_B - 211 |
| {2961, 1188, 6, 9 }, |
| // AArch64::INSERT_MXIPZ_H_D - 212 |
| {2994, 1197, 6, 9 }, |
| // AArch64::INSERT_MXIPZ_H_H - 213 |
| {3027, 1206, 6, 9 }, |
| // AArch64::INSERT_MXIPZ_H_Q - 214 |
| {3060, 1215, 6, 9 }, |
| // AArch64::INSERT_MXIPZ_H_S - 215 |
| {3093, 1224, 6, 9 }, |
| // AArch64::INSERT_MXIPZ_V_B - 216 |
| {3126, 1233, 6, 9 }, |
| // AArch64::INSERT_MXIPZ_V_D - 217 |
| {3159, 1242, 6, 9 }, |
| // AArch64::INSERT_MXIPZ_V_H - 218 |
| {3192, 1251, 6, 9 }, |
| // AArch64::INSERT_MXIPZ_V_Q - 219 |
| {3225, 1260, 6, 9 }, |
| // AArch64::INSERT_MXIPZ_V_S - 220 |
| {3258, 1269, 6, 9 }, |
| // AArch64::INSvi16gpr - 221 |
| {3291, 1278, 4, 7 }, |
| // AArch64::INSvi16lane - 222 |
| {3310, 1285, 5, 7 }, |
| // AArch64::INSvi32gpr - 223 |
| {3335, 1292, 4, 7 }, |
| // AArch64::INSvi32lane - 224 |
| {3354, 1299, 5, 7 }, |
| // AArch64::INSvi64gpr - 225 |
| {3379, 1306, 4, 7 }, |
| // AArch64::INSvi64lane - 226 |
| {3398, 1313, 5, 7 }, |
| // AArch64::INSvi8gpr - 227 |
| {3423, 1320, 4, 7 }, |
| // AArch64::INSvi8lane - 228 |
| {3442, 1327, 5, 7 }, |
| // AArch64::IRG - 229 |
| {3467, 1334, 3, 6 }, |
| // AArch64::ISB - 230 |
| {3478, 1340, 1, 1 }, |
| // AArch64::LD1B_2Z_IMM - 231 |
| {3482, 1341, 4, 8 }, |
| // AArch64::LD1B_4Z_IMM - 232 |
| {3482, 1349, 4, 8 }, |
| // AArch64::LD1B_D_IMM_REAL - 233 |
| {3506, 1357, 4, 8 }, |
| // AArch64::LD1B_H_IMM_REAL - 234 |
| {3530, 1365, 4, 8 }, |
| // AArch64::LD1B_IMM_REAL - 235 |
| {3554, 1373, 4, 8 }, |
| // AArch64::LD1B_S_IMM_REAL - 236 |
| {3578, 1381, 4, 8 }, |
| // AArch64::LD1B_VG2_M2ZPXI - 237 |
| {3602, 1389, 4, 7 }, |
| // AArch64::LD1B_VG4_M4ZPXI - 238 |
| {3626, 1396, 4, 7 }, |
| // AArch64::LD1D_2Z_IMM - 239 |
| {3650, 1403, 4, 8 }, |
| // AArch64::LD1D_4Z_IMM - 240 |
| {3650, 1411, 4, 8 }, |
| // AArch64::LD1D_IMM_REAL - 241 |
| {3674, 1419, 4, 8 }, |
| // AArch64::LD1D_Q_IMM - 242 |
| {3698, 1427, 4, 6 }, |
| // AArch64::LD1D_VG2_M2ZPXI - 243 |
| {3722, 1433, 4, 7 }, |
| // AArch64::LD1D_VG4_M4ZPXI - 244 |
| {3722, 1440, 4, 7 }, |
| // AArch64::LD1Fourv16b_POST - 245 |
| {3746, 1447, 4, 7 }, |
| // AArch64::LD1Fourv1d_POST - 246 |
| {3766, 1454, 4, 7 }, |
| // AArch64::LD1Fourv2d_POST - 247 |
| {3786, 1461, 4, 7 }, |
| // AArch64::LD1Fourv2s_POST - 248 |
| {3806, 1468, 4, 7 }, |
| // AArch64::LD1Fourv4h_POST - 249 |
| {3826, 1475, 4, 7 }, |
| // AArch64::LD1Fourv4s_POST - 250 |
| {3846, 1482, 4, 7 }, |
| // AArch64::LD1Fourv8b_POST - 251 |
| {3866, 1489, 4, 7 }, |
| // AArch64::LD1Fourv8h_POST - 252 |
| {3886, 1496, 4, 7 }, |
| // AArch64::LD1H_2Z_IMM - 253 |
| {3906, 1503, 4, 8 }, |
| // AArch64::LD1H_4Z_IMM - 254 |
| {3906, 1511, 4, 8 }, |
| // AArch64::LD1H_D_IMM_REAL - 255 |
| {3930, 1519, 4, 8 }, |
| // AArch64::LD1H_IMM_REAL - 256 |
| {3954, 1527, 4, 8 }, |
| // AArch64::LD1H_S_IMM_REAL - 257 |
| {3978, 1535, 4, 8 }, |
| // AArch64::LD1H_VG2_M2ZPXI - 258 |
| {4002, 1543, 4, 7 }, |
| // AArch64::LD1H_VG4_M4ZPXI - 259 |
| {4026, 1550, 4, 7 }, |
| // AArch64::LD1Onev16b_POST - 260 |
| {4050, 1557, 4, 7 }, |
| // AArch64::LD1Onev1d_POST - 261 |
| {4070, 1564, 4, 7 }, |
| // AArch64::LD1Onev2d_POST - 262 |
| {4089, 1571, 4, 7 }, |
| // AArch64::LD1Onev2s_POST - 263 |
| {4109, 1578, 4, 7 }, |
| // AArch64::LD1Onev4h_POST - 264 |
| {4128, 1585, 4, 7 }, |
| // AArch64::LD1Onev4s_POST - 265 |
| {4147, 1592, 4, 7 }, |
| // AArch64::LD1Onev8b_POST - 266 |
| {4167, 1599, 4, 7 }, |
| // AArch64::LD1Onev8h_POST - 267 |
| {4186, 1606, 4, 7 }, |
| // AArch64::LD1RB_D_IMM - 268 |
| {4206, 1613, 4, 8 }, |
| // AArch64::LD1RB_H_IMM - 269 |
| {4231, 1621, 4, 8 }, |
| // AArch64::LD1RB_IMM - 270 |
| {4256, 1629, 4, 8 }, |
| // AArch64::LD1RB_S_IMM - 271 |
| {4281, 1637, 4, 8 }, |
| // AArch64::LD1RD_IMM - 272 |
| {4306, 1645, 4, 8 }, |
| // AArch64::LD1RH_D_IMM - 273 |
| {4331, 1653, 4, 8 }, |
| // AArch64::LD1RH_IMM - 274 |
| {4356, 1661, 4, 8 }, |
| // AArch64::LD1RH_S_IMM - 275 |
| {4381, 1669, 4, 8 }, |
| // AArch64::LD1RO_B_IMM - 276 |
| {4406, 1677, 4, 10 }, |
| // AArch64::LD1RO_D_IMM - 277 |
| {4432, 1687, 4, 10 }, |
| // AArch64::LD1RO_H_IMM - 278 |
| {4458, 1697, 4, 10 }, |
| // AArch64::LD1RO_W_IMM - 279 |
| {4484, 1707, 4, 10 }, |
| // AArch64::LD1RQ_B_IMM - 280 |
| {4510, 1717, 4, 8 }, |
| // AArch64::LD1RQ_D_IMM - 281 |
| {4536, 1725, 4, 8 }, |
| // AArch64::LD1RQ_H_IMM - 282 |
| {4562, 1733, 4, 8 }, |
| // AArch64::LD1RQ_W_IMM - 283 |
| {4588, 1741, 4, 8 }, |
| // AArch64::LD1RSB_D_IMM - 284 |
| {4614, 1749, 4, 8 }, |
| // AArch64::LD1RSB_H_IMM - 285 |
| {4640, 1757, 4, 8 }, |
| // AArch64::LD1RSB_S_IMM - 286 |
| {4666, 1765, 4, 8 }, |
| // AArch64::LD1RSH_D_IMM - 287 |
| {4692, 1773, 4, 8 }, |
| // AArch64::LD1RSH_S_IMM - 288 |
| {4718, 1781, 4, 8 }, |
| // AArch64::LD1RSW_IMM - 289 |
| {4744, 1789, 4, 8 }, |
| // AArch64::LD1RW_D_IMM - 290 |
| {4770, 1797, 4, 8 }, |
| // AArch64::LD1RW_IMM - 291 |
| {4795, 1805, 4, 8 }, |
| // AArch64::LD1Rv16b_POST - 292 |
| {4820, 1813, 4, 7 }, |
| // AArch64::LD1Rv1d_POST - 293 |
| {4840, 1820, 4, 7 }, |
| // AArch64::LD1Rv2d_POST - 294 |
| {4860, 1827, 4, 7 }, |
| // AArch64::LD1Rv2s_POST - 295 |
| {4880, 1834, 4, 7 }, |
| // AArch64::LD1Rv4h_POST - 296 |
| {4900, 1841, 4, 7 }, |
| // AArch64::LD1Rv4s_POST - 297 |
| {4920, 1848, 4, 7 }, |
| // AArch64::LD1Rv8b_POST - 298 |
| {4940, 1855, 4, 7 }, |
| // AArch64::LD1Rv8h_POST - 299 |
| {4960, 1862, 4, 7 }, |
| // AArch64::LD1SB_D_IMM_REAL - 300 |
| {4980, 1869, 4, 8 }, |
| // AArch64::LD1SB_H_IMM_REAL - 301 |
| {5005, 1877, 4, 8 }, |
| // AArch64::LD1SB_S_IMM_REAL - 302 |
| {5030, 1885, 4, 8 }, |
| // AArch64::LD1SH_D_IMM_REAL - 303 |
| {5055, 1893, 4, 8 }, |
| // AArch64::LD1SH_S_IMM_REAL - 304 |
| {5080, 1901, 4, 8 }, |
| // AArch64::LD1SW_D_IMM_REAL - 305 |
| {5105, 1909, 4, 8 }, |
| // AArch64::LD1Threev16b_POST - 306 |
| {5130, 1917, 4, 7 }, |
| // AArch64::LD1Threev1d_POST - 307 |
| {5150, 1924, 4, 7 }, |
| // AArch64::LD1Threev2d_POST - 308 |
| {5170, 1931, 4, 7 }, |
| // AArch64::LD1Threev2s_POST - 309 |
| {5190, 1938, 4, 7 }, |
| // AArch64::LD1Threev4h_POST - 310 |
| {5210, 1945, 4, 7 }, |
| // AArch64::LD1Threev4s_POST - 311 |
| {5230, 1952, 4, 7 }, |
| // AArch64::LD1Threev8b_POST - 312 |
| {5250, 1959, 4, 7 }, |
| // AArch64::LD1Threev8h_POST - 313 |
| {5270, 1966, 4, 7 }, |
| // AArch64::LD1Twov16b_POST - 314 |
| {5290, 1973, 4, 7 }, |
| // AArch64::LD1Twov1d_POST - 315 |
| {5310, 1980, 4, 7 }, |
| // AArch64::LD1Twov2d_POST - 316 |
| {5330, 1987, 4, 7 }, |
| // AArch64::LD1Twov2s_POST - 317 |
| {5350, 1994, 4, 7 }, |
| // AArch64::LD1Twov4h_POST - 318 |
| {5370, 2001, 4, 7 }, |
| // AArch64::LD1Twov4s_POST - 319 |
| {5390, 2008, 4, 7 }, |
| // AArch64::LD1Twov8b_POST - 320 |
| {5410, 2015, 4, 7 }, |
| // AArch64::LD1Twov8h_POST - 321 |
| {5430, 2022, 4, 7 }, |
| // AArch64::LD1W_2Z_IMM - 322 |
| {5450, 2029, 4, 8 }, |
| // AArch64::LD1W_4Z_IMM - 323 |
| {5450, 2037, 4, 8 }, |
| // AArch64::LD1W_D_IMM_REAL - 324 |
| {5474, 2045, 4, 8 }, |
| // AArch64::LD1W_IMM_REAL - 325 |
| {5498, 2053, 4, 8 }, |
| // AArch64::LD1W_Q_IMM - 326 |
| {5522, 2061, 4, 6 }, |
| // AArch64::LD1W_VG2_M2ZPXI - 327 |
| {5546, 2067, 4, 7 }, |
| // AArch64::LD1W_VG4_M4ZPXI - 328 |
| {5546, 2074, 4, 7 }, |
| // AArch64::LD1_MXIPXX_H_B - 329 |
| {5570, 2081, 6, 9 }, |
| // AArch64::LD1_MXIPXX_H_D - 330 |
| {5606, 2090, 6, 9 }, |
| // AArch64::LD1_MXIPXX_H_H - 331 |
| {5642, 2099, 6, 9 }, |
| // AArch64::LD1_MXIPXX_H_Q - 332 |
| {5678, 2108, 6, 9 }, |
| // AArch64::LD1_MXIPXX_H_S - 333 |
| {5714, 2117, 6, 9 }, |
| // AArch64::LD1_MXIPXX_V_B - 334 |
| {5750, 2126, 6, 9 }, |
| // AArch64::LD1_MXIPXX_V_D - 335 |
| {5786, 2135, 6, 9 }, |
| // AArch64::LD1_MXIPXX_V_H - 336 |
| {5822, 2144, 6, 9 }, |
| // AArch64::LD1_MXIPXX_V_Q - 337 |
| {5858, 2153, 6, 9 }, |
| // AArch64::LD1_MXIPXX_V_S - 338 |
| {5894, 2162, 6, 9 }, |
| // AArch64::LD1i16_POST - 339 |
| {5930, 2171, 6, 9 }, |
| // AArch64::LD1i32_POST - 340 |
| {5953, 2180, 6, 9 }, |
| // AArch64::LD1i64_POST - 341 |
| {5976, 2189, 6, 9 }, |
| // AArch64::LD1i8_POST - 342 |
| {5999, 2198, 6, 9 }, |
| // AArch64::LD2B_IMM - 343 |
| {6022, 2207, 4, 8 }, |
| // AArch64::LD2D_IMM - 344 |
| {6046, 2215, 4, 8 }, |
| // AArch64::LD2H_IMM - 345 |
| {6070, 2223, 4, 8 }, |
| // AArch64::LD2Q_IMM - 346 |
| {6094, 2231, 4, 8 }, |
| // AArch64::LD2Rv16b_POST - 347 |
| {6118, 2239, 4, 7 }, |
| // AArch64::LD2Rv1d_POST - 348 |
| {6138, 2246, 4, 7 }, |
| // AArch64::LD2Rv2d_POST - 349 |
| {6159, 2253, 4, 7 }, |
| // AArch64::LD2Rv2s_POST - 350 |
| {6180, 2260, 4, 7 }, |
| // AArch64::LD2Rv4h_POST - 351 |
| {6200, 2267, 4, 7 }, |
| // AArch64::LD2Rv4s_POST - 352 |
| {6220, 2274, 4, 7 }, |
| // AArch64::LD2Rv8b_POST - 353 |
| {6240, 2281, 4, 7 }, |
| // AArch64::LD2Rv8h_POST - 354 |
| {6260, 2288, 4, 7 }, |
| // AArch64::LD2Twov16b_POST - 355 |
| {6280, 2295, 4, 7 }, |
| // AArch64::LD2Twov2d_POST - 356 |
| {6300, 2302, 4, 7 }, |
| // AArch64::LD2Twov2s_POST - 357 |
| {6320, 2309, 4, 7 }, |
| // AArch64::LD2Twov4h_POST - 358 |
| {6340, 2316, 4, 7 }, |
| // AArch64::LD2Twov4s_POST - 359 |
| {6360, 2323, 4, 7 }, |
| // AArch64::LD2Twov8b_POST - 360 |
| {6380, 2330, 4, 7 }, |
| // AArch64::LD2Twov8h_POST - 361 |
| {6400, 2337, 4, 7 }, |
| // AArch64::LD2W_IMM - 362 |
| {6420, 2344, 4, 8 }, |
| // AArch64::LD2i16_POST - 363 |
| {6444, 2352, 6, 9 }, |
| // AArch64::LD2i32_POST - 364 |
| {6467, 2361, 6, 9 }, |
| // AArch64::LD2i64_POST - 365 |
| {6490, 2370, 6, 9 }, |
| // AArch64::LD2i8_POST - 366 |
| {6514, 2379, 6, 9 }, |
| // AArch64::LD3B_IMM - 367 |
| {6537, 2388, 4, 8 }, |
| // AArch64::LD3D_IMM - 368 |
| {6561, 2396, 4, 8 }, |
| // AArch64::LD3H_IMM - 369 |
| {6585, 2404, 4, 8 }, |
| // AArch64::LD3Q_IMM - 370 |
| {6609, 2412, 4, 8 }, |
| // AArch64::LD3Rv16b_POST - 371 |
| {6633, 2420, 4, 7 }, |
| // AArch64::LD3Rv1d_POST - 372 |
| {6653, 2427, 4, 7 }, |
| // AArch64::LD3Rv2d_POST - 373 |
| {6674, 2434, 4, 7 }, |
| // AArch64::LD3Rv2s_POST - 374 |
| {6695, 2441, 4, 7 }, |
| // AArch64::LD3Rv4h_POST - 375 |
| {6716, 2448, 4, 7 }, |
| // AArch64::LD3Rv4s_POST - 376 |
| {6736, 2455, 4, 7 }, |
| // AArch64::LD3Rv8b_POST - 377 |
| {6757, 2462, 4, 7 }, |
| // AArch64::LD3Rv8h_POST - 378 |
| {6777, 2469, 4, 7 }, |
| // AArch64::LD3Threev16b_POST - 379 |
| {6797, 2476, 4, 7 }, |
| // AArch64::LD3Threev2d_POST - 380 |
| {6817, 2483, 4, 7 }, |
| // AArch64::LD3Threev2s_POST - 381 |
| {6837, 2490, 4, 7 }, |
| // AArch64::LD3Threev4h_POST - 382 |
| {6857, 2497, 4, 7 }, |
| // AArch64::LD3Threev4s_POST - 383 |
| {6877, 2504, 4, 7 }, |
| // AArch64::LD3Threev8b_POST - 384 |
| {6897, 2511, 4, 7 }, |
| // AArch64::LD3Threev8h_POST - 385 |
| {6917, 2518, 4, 7 }, |
| // AArch64::LD3W_IMM - 386 |
| {6937, 2525, 4, 8 }, |
| // AArch64::LD3i16_POST - 387 |
| {6961, 2533, 6, 9 }, |
| // AArch64::LD3i32_POST - 388 |
| {6984, 2542, 6, 9 }, |
| // AArch64::LD3i64_POST - 389 |
| {7008, 2551, 6, 9 }, |
| // AArch64::LD3i8_POST - 390 |
| {7032, 2560, 6, 9 }, |
| // AArch64::LD4B_IMM - 391 |
| {7055, 2569, 4, 8 }, |
| // AArch64::LD4D_IMM - 392 |
| {7079, 2577, 4, 8 }, |
| // AArch64::LD4Fourv16b_POST - 393 |
| {7103, 2585, 4, 7 }, |
| // AArch64::LD4Fourv2d_POST - 394 |
| {7123, 2592, 4, 7 }, |
| // AArch64::LD4Fourv2s_POST - 395 |
| {7143, 2599, 4, 7 }, |
| // AArch64::LD4Fourv4h_POST - 396 |
| {7163, 2606, 4, 7 }, |
| // AArch64::LD4Fourv4s_POST - 397 |
| {7183, 2613, 4, 7 }, |
| // AArch64::LD4Fourv8b_POST - 398 |
| {7203, 2620, 4, 7 }, |
| // AArch64::LD4Fourv8h_POST - 399 |
| {7223, 2627, 4, 7 }, |
| // AArch64::LD4H_IMM - 400 |
| {7243, 2634, 4, 8 }, |
| // AArch64::LD4Q_IMM - 401 |
| {7267, 2642, 4, 8 }, |
| // AArch64::LD4Rv16b_POST - 402 |
| {7291, 2650, 4, 7 }, |
| // AArch64::LD4Rv1d_POST - 403 |
| {7311, 2657, 4, 7 }, |
| // AArch64::LD4Rv2d_POST - 404 |
| {7332, 2664, 4, 7 }, |
| // AArch64::LD4Rv2s_POST - 405 |
| {7353, 2671, 4, 7 }, |
| // AArch64::LD4Rv4h_POST - 406 |
| {7374, 2678, 4, 7 }, |
| // AArch64::LD4Rv4s_POST - 407 |
| {7394, 2685, 4, 7 }, |
| // AArch64::LD4Rv8b_POST - 408 |
| {7415, 2692, 4, 7 }, |
| // AArch64::LD4Rv8h_POST - 409 |
| {7435, 2699, 4, 7 }, |
| // AArch64::LD4W_IMM - 410 |
| {7455, 2706, 4, 8 }, |
| // AArch64::LD4i16_POST - 411 |
| {7479, 2714, 6, 9 }, |
| // AArch64::LD4i32_POST - 412 |
| {7502, 2723, 6, 9 }, |
| // AArch64::LD4i64_POST - 413 |
| {7526, 2732, 6, 9 }, |
| // AArch64::LD4i8_POST - 414 |
| {7550, 2741, 6, 9 }, |
| // AArch64::LDADDB - 415 |
| {7573, 2750, 3, 6 }, |
| // AArch64::LDADDH - 416 |
| {7589, 2756, 3, 6 }, |
| // AArch64::LDADDLB - 417 |
| {7605, 2762, 3, 6 }, |
| // AArch64::LDADDLH - 418 |
| {7622, 2768, 3, 6 }, |
| // AArch64::LDADDLW - 419 |
| {7639, 2774, 3, 6 }, |
| // AArch64::LDADDLX - 420 |
| {7639, 2780, 3, 6 }, |
| // AArch64::LDADDW - 421 |
| {7655, 2786, 3, 6 }, |
| // AArch64::LDADDX - 422 |
| {7655, 2792, 3, 6 }, |
| // AArch64::LDAPURBi - 423 |
| {7670, 2798, 3, 6 }, |
| // AArch64::LDAPURHi - 424 |
| {7687, 2804, 3, 6 }, |
| // AArch64::LDAPURSBWi - 425 |
| {7704, 2810, 3, 6 }, |
| // AArch64::LDAPURSBXi - 426 |
| {7704, 2816, 3, 6 }, |
| // AArch64::LDAPURSHWi - 427 |
| {7722, 2822, 3, 6 }, |
| // AArch64::LDAPURSHXi - 428 |
| {7722, 2828, 3, 6 }, |
| // AArch64::LDAPURSWi - 429 |
| {7740, 2834, 3, 6 }, |
| // AArch64::LDAPURXi - 430 |
| {7758, 2840, 3, 6 }, |
| // AArch64::LDAPURbi - 431 |
| {7758, 2846, 3, 9 }, |
| // AArch64::LDAPURdi - 432 |
| {7758, 2855, 3, 9 }, |
| // AArch64::LDAPURhi - 433 |
| {7758, 2864, 3, 9 }, |
| // AArch64::LDAPURi - 434 |
| {7758, 2873, 3, 6 }, |
| // AArch64::LDAPURqi - 435 |
| {7758, 2879, 3, 9 }, |
| // AArch64::LDAPURsi - 436 |
| {7758, 2888, 3, 9 }, |
| // AArch64::LDCLRB - 437 |
| {7774, 2897, 3, 6 }, |
| // AArch64::LDCLRH - 438 |
| {7790, 2903, 3, 6 }, |
| // AArch64::LDCLRLB - 439 |
| {7806, 2909, 3, 6 }, |
| // AArch64::LDCLRLH - 440 |
| {7823, 2915, 3, 6 }, |
| // AArch64::LDCLRLW - 441 |
| {7840, 2921, 3, 6 }, |
| // AArch64::LDCLRLX - 442 |
| {7840, 2927, 3, 6 }, |
| // AArch64::LDCLRW - 443 |
| {7856, 2933, 3, 6 }, |
| // AArch64::LDCLRX - 444 |
| {7856, 2939, 3, 6 }, |
| // AArch64::LDEORB - 445 |
| {7871, 2945, 3, 6 }, |
| // AArch64::LDEORH - 446 |
| {7887, 2951, 3, 6 }, |
| // AArch64::LDEORLB - 447 |
| {7903, 2957, 3, 6 }, |
| // AArch64::LDEORLH - 448 |
| {7920, 2963, 3, 6 }, |
| // AArch64::LDEORLW - 449 |
| {7937, 2969, 3, 6 }, |
| // AArch64::LDEORLX - 450 |
| {7937, 2975, 3, 6 }, |
| // AArch64::LDEORW - 451 |
| {7953, 2981, 3, 6 }, |
| // AArch64::LDEORX - 452 |
| {7953, 2987, 3, 6 }, |
| // AArch64::LDFF1B_D_REAL - 453 |
| {7968, 2993, 4, 7 }, |
| // AArch64::LDFF1B_H_REAL - 454 |
| {7994, 3000, 4, 7 }, |
| // AArch64::LDFF1B_REAL - 455 |
| {8020, 3007, 4, 7 }, |
| // AArch64::LDFF1B_S_REAL - 456 |
| {8046, 3014, 4, 7 }, |
| // AArch64::LDFF1D_REAL - 457 |
| {8072, 3021, 4, 7 }, |
| // AArch64::LDFF1H_D_REAL - 458 |
| {8098, 3028, 4, 7 }, |
| // AArch64::LDFF1H_REAL - 459 |
| {8124, 3035, 4, 7 }, |
| // AArch64::LDFF1H_S_REAL - 460 |
| {8150, 3042, 4, 7 }, |
| // AArch64::LDFF1SB_D_REAL - 461 |
| {8176, 3049, 4, 7 }, |
| // AArch64::LDFF1SB_H_REAL - 462 |
| {8203, 3056, 4, 7 }, |
| // AArch64::LDFF1SB_S_REAL - 463 |
| {8230, 3063, 4, 7 }, |
| // AArch64::LDFF1SH_D_REAL - 464 |
| {8257, 3070, 4, 7 }, |
| // AArch64::LDFF1SH_S_REAL - 465 |
| {8284, 3077, 4, 7 }, |
| // AArch64::LDFF1SW_D_REAL - 466 |
| {8311, 3084, 4, 7 }, |
| // AArch64::LDFF1W_D_REAL - 467 |
| {8338, 3091, 4, 7 }, |
| // AArch64::LDFF1W_REAL - 468 |
| {8364, 3098, 4, 7 }, |
| // AArch64::LDG - 469 |
| {8390, 3105, 4, 7 }, |
| // AArch64::LDNF1B_D_IMM_REAL - 470 |
| {8403, 3112, 4, 7 }, |
| // AArch64::LDNF1B_H_IMM_REAL - 471 |
| {8429, 3119, 4, 7 }, |
| // AArch64::LDNF1B_IMM_REAL - 472 |
| {8455, 3126, 4, 7 }, |
| // AArch64::LDNF1B_S_IMM_REAL - 473 |
| {8481, 3133, 4, 7 }, |
| // AArch64::LDNF1D_IMM_REAL - 474 |
| {8507, 3140, 4, 7 }, |
| // AArch64::LDNF1H_D_IMM_REAL - 475 |
| {8533, 3147, 4, 7 }, |
| // AArch64::LDNF1H_IMM_REAL - 476 |
| {8559, 3154, 4, 7 }, |
| // AArch64::LDNF1H_S_IMM_REAL - 477 |
| {8585, 3161, 4, 7 }, |
| // AArch64::LDNF1SB_D_IMM_REAL - 478 |
| {8611, 3168, 4, 7 }, |
| // AArch64::LDNF1SB_H_IMM_REAL - 479 |
| {8638, 3175, 4, 7 }, |
| // AArch64::LDNF1SB_S_IMM_REAL - 480 |
| {8665, 3182, 4, 7 }, |
| // AArch64::LDNF1SH_D_IMM_REAL - 481 |
| {8692, 3189, 4, 7 }, |
| // AArch64::LDNF1SH_S_IMM_REAL - 482 |
| {8719, 3196, 4, 7 }, |
| // AArch64::LDNF1SW_D_IMM_REAL - 483 |
| {8746, 3203, 4, 7 }, |
| // AArch64::LDNF1W_D_IMM_REAL - 484 |
| {8773, 3210, 4, 7 }, |
| // AArch64::LDNF1W_IMM_REAL - 485 |
| {8799, 3217, 4, 7 }, |
| // AArch64::LDNPDi - 486 |
| {8825, 3224, 4, 4 }, |
| // AArch64::LDNPQi - 487 |
| {8825, 3228, 4, 4 }, |
| // AArch64::LDNPSi - 488 |
| {8825, 3232, 4, 4 }, |
| // AArch64::LDNPWi - 489 |
| {8825, 3236, 4, 4 }, |
| // AArch64::LDNPXi - 490 |
| {8825, 3240, 4, 4 }, |
| // AArch64::LDNT1B_2Z_IMM - 491 |
| {8843, 3244, 4, 8 }, |
| // AArch64::LDNT1B_4Z_IMM - 492 |
| {8843, 3252, 4, 8 }, |
| // AArch64::LDNT1B_VG2_M2ZPXI - 493 |
| {8869, 3260, 4, 7 }, |
| // AArch64::LDNT1B_VG4_M4ZPXI - 494 |
| {8895, 3267, 4, 7 }, |
| // AArch64::LDNT1B_ZRI - 495 |
| {8921, 3274, 4, 8 }, |
| // AArch64::LDNT1B_ZZR_D_REAL - 496 |
| {8947, 3282, 4, 7 }, |
| // AArch64::LDNT1B_ZZR_S_REAL - 497 |
| {8975, 3289, 4, 7 }, |
| // AArch64::LDNT1D_2Z_IMM - 498 |
| {9003, 3296, 4, 8 }, |
| // AArch64::LDNT1D_4Z_IMM - 499 |
| {9003, 3304, 4, 8 }, |
| // AArch64::LDNT1D_VG2_M2ZPXI - 500 |
| {9029, 3312, 4, 7 }, |
| // AArch64::LDNT1D_VG4_M4ZPXI - 501 |
| {9029, 3319, 4, 7 }, |
| // AArch64::LDNT1D_ZRI - 502 |
| {9055, 3326, 4, 8 }, |
| // AArch64::LDNT1D_ZZR_D_REAL - 503 |
| {9081, 3334, 4, 7 }, |
| // AArch64::LDNT1H_2Z_IMM - 504 |
| {9109, 3341, 4, 8 }, |
| // AArch64::LDNT1H_4Z_IMM - 505 |
| {9109, 3349, 4, 8 }, |
| // AArch64::LDNT1H_VG2_M2ZPXI - 506 |
| {9135, 3357, 4, 7 }, |
| // AArch64::LDNT1H_VG4_M4ZPXI - 507 |
| {9161, 3364, 4, 7 }, |
| // AArch64::LDNT1H_ZRI - 508 |
| {9187, 3371, 4, 8 }, |
| // AArch64::LDNT1H_ZZR_D_REAL - 509 |
| {9213, 3379, 4, 7 }, |
| // AArch64::LDNT1H_ZZR_S_REAL - 510 |
| {9241, 3386, 4, 7 }, |
| // AArch64::LDNT1SB_ZZR_D_REAL - 511 |
| {9269, 3393, 4, 7 }, |
| // AArch64::LDNT1SB_ZZR_S_REAL - 512 |
| {9298, 3400, 4, 7 }, |
| // AArch64::LDNT1SH_ZZR_D_REAL - 513 |
| {9327, 3407, 4, 7 }, |
| // AArch64::LDNT1SH_ZZR_S_REAL - 514 |
| {9356, 3414, 4, 7 }, |
| // AArch64::LDNT1SW_ZZR_D_REAL - 515 |
| {9385, 3421, 4, 7 }, |
| // AArch64::LDNT1W_2Z_IMM - 516 |
| {9414, 3428, 4, 8 }, |
| // AArch64::LDNT1W_4Z_IMM - 517 |
| {9414, 3436, 4, 8 }, |
| // AArch64::LDNT1W_VG2_M2ZPXI - 518 |
| {9440, 3444, 4, 7 }, |
| // AArch64::LDNT1W_VG4_M4ZPXI - 519 |
| {9440, 3451, 4, 7 }, |
| // AArch64::LDNT1W_ZRI - 520 |
| {9466, 3458, 4, 8 }, |
| // AArch64::LDNT1W_ZZR_D_REAL - 521 |
| {9492, 3466, 4, 7 }, |
| // AArch64::LDNT1W_ZZR_S_REAL - 522 |
| {9520, 3473, 4, 7 }, |
| // AArch64::LDPDi - 523 |
| {9548, 3480, 4, 4 }, |
| // AArch64::LDPQi - 524 |
| {9548, 3484, 4, 4 }, |
| // AArch64::LDPSWi - 525 |
| {9565, 3488, 4, 4 }, |
| // AArch64::LDPSi - 526 |
| {9548, 3492, 4, 4 }, |
| // AArch64::LDPWi - 527 |
| {9548, 3496, 4, 4 }, |
| // AArch64::LDPXi - 528 |
| {9548, 3500, 4, 4 }, |
| // AArch64::LDRAAindexed - 529 |
| {9584, 3504, 3, 6 }, |
| // AArch64::LDRABindexed - 530 |
| {9599, 3510, 3, 6 }, |
| // AArch64::LDRBBroX - 531 |
| {9614, 3516, 5, 5 }, |
| // AArch64::LDRBBui - 532 |
| {9632, 3521, 3, 3 }, |
| // AArch64::LDRBroX - 533 |
| {9646, 3524, 5, 5 }, |
| // AArch64::LDRBui - 534 |
| {9663, 3529, 3, 3 }, |
| // AArch64::LDRDroX - 535 |
| {9646, 3532, 5, 5 }, |
| // AArch64::LDRDui - 536 |
| {9663, 3537, 3, 3 }, |
| // AArch64::LDRHHroX - 537 |
| {9676, 3540, 5, 5 }, |
| // AArch64::LDRHHui - 538 |
| {9694, 3545, 3, 3 }, |
| // AArch64::LDRHroX - 539 |
| {9646, 3548, 5, 5 }, |
| // AArch64::LDRHui - 540 |
| {9663, 3553, 3, 3 }, |
| // AArch64::LDRQroX - 541 |
| {9646, 3556, 5, 5 }, |
| // AArch64::LDRQui - 542 |
| {9663, 3561, 3, 3 }, |
| // AArch64::LDRSBWroX - 543 |
| {9708, 3564, 5, 5 }, |
| // AArch64::LDRSBWui - 544 |
| {9727, 3569, 3, 3 }, |
| // AArch64::LDRSBXroX - 545 |
| {9708, 3572, 5, 5 }, |
| // AArch64::LDRSBXui - 546 |
| {9727, 3577, 3, 3 }, |
| // AArch64::LDRSHWroX - 547 |
| {9742, 3580, 5, 5 }, |
| // AArch64::LDRSHWui - 548 |
| {9761, 3585, 3, 3 }, |
| // AArch64::LDRSHXroX - 549 |
| {9742, 3588, 5, 5 }, |
| // AArch64::LDRSHXui - 550 |
| {9761, 3593, 3, 3 }, |
| // AArch64::LDRSWroX - 551 |
| {9776, 3596, 5, 5 }, |
| // AArch64::LDRSWui - 552 |
| {9795, 3601, 3, 3 }, |
| // AArch64::LDRSroX - 553 |
| {9646, 3604, 5, 5 }, |
| // AArch64::LDRSui - 554 |
| {9663, 3609, 3, 3 }, |
| // AArch64::LDRWroX - 555 |
| {9646, 3612, 5, 5 }, |
| // AArch64::LDRWui - 556 |
| {9663, 3617, 3, 3 }, |
| // AArch64::LDRXroX - 557 |
| {9646, 3620, 5, 5 }, |
| // AArch64::LDRXui - 558 |
| {9663, 3625, 3, 3 }, |
| // AArch64::LDR_PXI - 559 |
| {9810, 3628, 3, 7 }, |
| // AArch64::LDR_ZA - 560 |
| {9825, 3635, 5, 8 }, |
| // AArch64::LDR_ZXI - 561 |
| {9810, 3643, 3, 7 }, |
| // AArch64::LDSETB - 562 |
| {9850, 3650, 3, 6 }, |
| // AArch64::LDSETH - 563 |
| {9866, 3656, 3, 6 }, |
| // AArch64::LDSETLB - 564 |
| {9882, 3662, 3, 6 }, |
| // AArch64::LDSETLH - 565 |
| {9899, 3668, 3, 6 }, |
| // AArch64::LDSETLW - 566 |
| {9916, 3674, 3, 6 }, |
| // AArch64::LDSETLX - 567 |
| {9916, 3680, 3, 6 }, |
| // AArch64::LDSETW - 568 |
| {9932, 3686, 3, 6 }, |
| // AArch64::LDSETX - 569 |
| {9932, 3692, 3, 6 }, |
| // AArch64::LDSMAXB - 570 |
| {9947, 3698, 3, 6 }, |
| // AArch64::LDSMAXH - 571 |
| {9964, 3704, 3, 6 }, |
| // AArch64::LDSMAXLB - 572 |
| {9981, 3710, 3, 6 }, |
| // AArch64::LDSMAXLH - 573 |
| {9999, 3716, 3, 6 }, |
| // AArch64::LDSMAXLW - 574 |
| {10017, 3722, 3, 6 }, |
| // AArch64::LDSMAXLX - 575 |
| {10017, 3728, 3, 6 }, |
| // AArch64::LDSMAXW - 576 |
| {10034, 3734, 3, 6 }, |
| // AArch64::LDSMAXX - 577 |
| {10034, 3740, 3, 6 }, |
| // AArch64::LDSMINB - 578 |
| {10050, 3746, 3, 6 }, |
| // AArch64::LDSMINH - 579 |
| {10067, 3752, 3, 6 }, |
| // AArch64::LDSMINLB - 580 |
| {10084, 3758, 3, 6 }, |
| // AArch64::LDSMINLH - 581 |
| {10102, 3764, 3, 6 }, |
| // AArch64::LDSMINLW - 582 |
| {10120, 3770, 3, 6 }, |
| // AArch64::LDSMINLX - 583 |
| {10120, 3776, 3, 6 }, |
| // AArch64::LDSMINW - 584 |
| {10137, 3782, 3, 6 }, |
| // AArch64::LDSMINX - 585 |
| {10137, 3788, 3, 6 }, |
| // AArch64::LDTRBi - 586 |
| {10153, 3794, 3, 3 }, |
| // AArch64::LDTRHi - 587 |
| {10168, 3797, 3, 3 }, |
| // AArch64::LDTRSBWi - 588 |
| {10183, 3800, 3, 3 }, |
| // AArch64::LDTRSBXi - 589 |
| {10183, 3803, 3, 3 }, |
| // AArch64::LDTRSHWi - 590 |
| {10199, 3806, 3, 3 }, |
| // AArch64::LDTRSHXi - 591 |
| {10199, 3809, 3, 3 }, |
| // AArch64::LDTRSWi - 592 |
| {10215, 3812, 3, 3 }, |
| // AArch64::LDTRWi - 593 |
| {10231, 3815, 3, 3 }, |
| // AArch64::LDTRXi - 594 |
| {10231, 3818, 3, 3 }, |
| // AArch64::LDUMAXB - 595 |
| {10245, 3821, 3, 6 }, |
| // AArch64::LDUMAXH - 596 |
| {10262, 3827, 3, 6 }, |
| // AArch64::LDUMAXLB - 597 |
| {10279, 3833, 3, 6 }, |
| // AArch64::LDUMAXLH - 598 |
| {10297, 3839, 3, 6 }, |
| // AArch64::LDUMAXLW - 599 |
| {10315, 3845, 3, 6 }, |
| // AArch64::LDUMAXLX - 600 |
| {10315, 3851, 3, 6 }, |
| // AArch64::LDUMAXW - 601 |
| {10332, 3857, 3, 6 }, |
| // AArch64::LDUMAXX - 602 |
| {10332, 3863, 3, 6 }, |
| // AArch64::LDUMINB - 603 |
| {10348, 3869, 3, 6 }, |
| // AArch64::LDUMINH - 604 |
| {10365, 3875, 3, 6 }, |
| // AArch64::LDUMINLB - 605 |
| {10382, 3881, 3, 6 }, |
| // AArch64::LDUMINLH - 606 |
| {10400, 3887, 3, 6 }, |
| // AArch64::LDUMINLW - 607 |
| {10418, 3893, 3, 6 }, |
| // AArch64::LDUMINLX - 608 |
| {10418, 3899, 3, 6 }, |
| // AArch64::LDUMINW - 609 |
| {10435, 3905, 3, 6 }, |
| // AArch64::LDUMINX - 610 |
| {10435, 3911, 3, 6 }, |
| // AArch64::LDURBBi - 611 |
| {10451, 3917, 3, 3 }, |
| // AArch64::LDURBi - 612 |
| {10466, 3920, 3, 3 }, |
| // AArch64::LDURDi - 613 |
| {10466, 3923, 3, 3 }, |
| // AArch64::LDURHHi - 614 |
| {10480, 3926, 3, 3 }, |
| // AArch64::LDURHi - 615 |
| {10466, 3929, 3, 3 }, |
| // AArch64::LDURQi - 616 |
| {10466, 3932, 3, 3 }, |
| // AArch64::LDURSBWi - 617 |
| {10495, 3935, 3, 3 }, |
| // AArch64::LDURSBXi - 618 |
| {10495, 3938, 3, 3 }, |
| // AArch64::LDURSHWi - 619 |
| {10511, 3941, 3, 3 }, |
| // AArch64::LDURSHXi - 620 |
| {10511, 3944, 3, 3 }, |
| // AArch64::LDURSWi - 621 |
| {10527, 3947, 3, 3 }, |
| // AArch64::LDURSi - 622 |
| {10466, 3950, 3, 3 }, |
| // AArch64::LDURWi - 623 |
| {10466, 3953, 3, 3 }, |
| // AArch64::LDURXi - 624 |
| {10466, 3956, 3, 3 }, |
| // AArch64::MADDWrrr - 625 |
| {10543, 3959, 4, 4 }, |
| // AArch64::MADDXrrr - 626 |
| {10543, 3963, 4, 4 }, |
| // AArch64::MOVA_2ZMXI_H_B - 627 |
| {10558, 3967, 4, 6 }, |
| // AArch64::MOVA_2ZMXI_H_D - 628 |
| {10583, 3973, 4, 6 }, |
| // AArch64::MOVA_2ZMXI_H_H - 629 |
| {10608, 3979, 4, 6 }, |
| // AArch64::MOVA_2ZMXI_H_S - 630 |
| {10633, 3985, 4, 6 }, |
| // AArch64::MOVA_2ZMXI_V_B - 631 |
| {10658, 3991, 4, 6 }, |
| // AArch64::MOVA_2ZMXI_V_D - 632 |
| {10683, 3997, 4, 6 }, |
| // AArch64::MOVA_2ZMXI_V_H - 633 |
| {10708, 4003, 4, 6 }, |
| // AArch64::MOVA_2ZMXI_V_S - 634 |
| {10733, 4009, 4, 6 }, |
| // AArch64::MOVA_4ZMXI_H_B - 635 |
| {10758, 4015, 4, 6 }, |
| // AArch64::MOVA_4ZMXI_H_D - 636 |
| {10783, 4021, 4, 6 }, |
| // AArch64::MOVA_4ZMXI_H_H - 637 |
| {10808, 4027, 4, 6 }, |
| // AArch64::MOVA_4ZMXI_H_S - 638 |
| {10833, 4033, 4, 6 }, |
| // AArch64::MOVA_4ZMXI_V_B - 639 |
| {10858, 4039, 4, 6 }, |
| // AArch64::MOVA_4ZMXI_V_D - 640 |
| {10883, 4045, 4, 6 }, |
| // AArch64::MOVA_4ZMXI_V_H - 641 |
| {10908, 4051, 4, 6 }, |
| // AArch64::MOVA_4ZMXI_V_S - 642 |
| {10933, 4057, 4, 6 }, |
| // AArch64::MOVA_MXI2Z_H_B - 643 |
| {10958, 4063, 5, 8 }, |
| // AArch64::MOVA_MXI2Z_H_D - 644 |
| {10983, 4071, 5, 8 }, |
| // AArch64::MOVA_MXI2Z_H_H - 645 |
| {11008, 4079, 5, 8 }, |
| // AArch64::MOVA_MXI2Z_H_S - 646 |
| {11033, 4087, 5, 8 }, |
| // AArch64::MOVA_MXI2Z_V_B - 647 |
| {11058, 4095, 5, 8 }, |
| // AArch64::MOVA_MXI2Z_V_D - 648 |
| {11083, 4103, 5, 8 }, |
| // AArch64::MOVA_MXI2Z_V_H - 649 |
| {11108, 4111, 5, 8 }, |
| // AArch64::MOVA_MXI2Z_V_S - 650 |
| {11133, 4119, 5, 8 }, |
| // AArch64::MOVA_MXI4Z_H_B - 651 |
| {11158, 4127, 5, 8 }, |
| // AArch64::MOVA_MXI4Z_H_D - 652 |
| {11183, 4135, 5, 8 }, |
| // AArch64::MOVA_MXI4Z_H_H - 653 |
| {11208, 4143, 5, 8 }, |
| // AArch64::MOVA_MXI4Z_H_S - 654 |
| {11233, 4151, 5, 8 }, |
| // AArch64::MOVA_MXI4Z_V_B - 655 |
| {11258, 4159, 5, 8 }, |
| // AArch64::MOVA_MXI4Z_V_D - 656 |
| {11283, 4167, 5, 8 }, |
| // AArch64::MOVA_MXI4Z_V_H - 657 |
| {11308, 4175, 5, 8 }, |
| // AArch64::MOVA_MXI4Z_V_S - 658 |
| {11333, 4183, 5, 8 }, |
| // AArch64::MOVA_VG2_2ZMXI - 659 |
| {11358, 4191, 4, 6 }, |
| // AArch64::MOVA_VG2_MXI2Z - 660 |
| {11389, 4197, 5, 8 }, |
| // AArch64::MOVA_VG4_4ZMXI - 661 |
| {11420, 4205, 4, 6 }, |
| // AArch64::MOVA_VG4_MXI4Z - 662 |
| {11451, 4211, 5, 8 }, |
| // AArch64::MSRpstatesvcrImm1 - 663 |
| {11482, 4219, 2, 5 }, |
| {11490, 4224, 2, 5 }, |
| {11501, 4229, 2, 5 }, |
| {11512, 4234, 2, 5 }, |
| {11519, 4239, 2, 5 }, |
| {11529, 4244, 2, 5 }, |
| // AArch64::MSUBWrrr - 669 |
| {11539, 4249, 4, 4 }, |
| // AArch64::MSUBXrrr - 670 |
| {11539, 4253, 4, 4 }, |
| // AArch64::NOTv16i8 - 671 |
| {11555, 4257, 2, 2 }, |
| // AArch64::NOTv8i8 - 672 |
| {11574, 4259, 2, 2 }, |
| // AArch64::ORNWrs - 673 |
| {11592, 4261, 4, 4 }, |
| {11603, 4265, 4, 3 }, |
| {11618, 4268, 4, 4 }, |
| // AArch64::ORNXrs - 676 |
| {11592, 4272, 4, 4 }, |
| {11603, 4276, 4, 3 }, |
| {11618, 4279, 4, 4 }, |
| // AArch64::ORRS_PPzPP - 679 |
| {11633, 4283, 4, 8 }, |
| // AArch64::ORRWrs - 680 |
| {11649, 4291, 4, 4 }, |
| {11660, 4295, 4, 4 }, |
| // AArch64::ORRXrs - 682 |
| {11649, 4299, 4, 4 }, |
| {11660, 4303, 4, 4 }, |
| // AArch64::ORR_PPzPP - 684 |
| {11675, 4307, 4, 8 }, |
| // AArch64::ORR_ZI - 685 |
| {11690, 4315, 3, 7 }, |
| {11711, 4322, 3, 7 }, |
| {11732, 4329, 3, 7 }, |
| // AArch64::ORR_ZZZ - 688 |
| {11753, 4336, 3, 7 }, |
| // AArch64::ORRv16i8 - 689 |
| {11768, 4343, 3, 3 }, |
| // AArch64::ORRv8i8 - 690 |
| {11787, 4346, 3, 3 }, |
| // AArch64::PACIA1716 - 691 |
| {11805, 4349, 0, 3 }, |
| // AArch64::PACIASP - 692 |
| {11815, 4352, 0, 3 }, |
| // AArch64::PACIAZ - 693 |
| {11823, 4355, 0, 3 }, |
| // AArch64::PACIB1716 - 694 |
| {11830, 4358, 0, 3 }, |
| // AArch64::PACIBSP - 695 |
| {11840, 4361, 0, 3 }, |
| // AArch64::PACIBZ - 696 |
| {11848, 4364, 0, 3 }, |
| // AArch64::PMOV_PZI_B - 697 |
| {11855, 4367, 3, 7 }, |
| // AArch64::PMOV_ZIP_B - 698 |
| {11871, 4374, 4, 8 }, |
| // AArch64::PRFB_D_PZI - 699 |
| {11887, 4382, 4, 7 }, |
| // AArch64::PRFB_PRI - 700 |
| {11911, 4389, 4, 8 }, |
| // AArch64::PRFB_S_PZI - 701 |
| {11933, 4397, 4, 7 }, |
| // AArch64::PRFD_D_PZI - 702 |
| {11957, 4404, 4, 7 }, |
| // AArch64::PRFD_PRI - 703 |
| {11981, 4411, 4, 8 }, |
| // AArch64::PRFD_S_PZI - 704 |
| {12003, 4419, 4, 7 }, |
| // AArch64::PRFH_D_PZI - 705 |
| {12027, 4426, 4, 7 }, |
| // AArch64::PRFH_PRI - 706 |
| {12051, 4433, 4, 8 }, |
| // AArch64::PRFH_S_PZI - 707 |
| {12073, 4441, 4, 7 }, |
| // AArch64::PRFMroX - 708 |
| {12097, 4448, 5, 5 }, |
| // AArch64::PRFMui - 709 |
| {12117, 4453, 3, 3 }, |
| // AArch64::PRFUMi - 710 |
| {12133, 4456, 3, 3 }, |
| // AArch64::PRFW_D_PZI - 711 |
| {12150, 4459, 4, 7 }, |
| // AArch64::PRFW_PRI - 712 |
| {12174, 4466, 4, 8 }, |
| // AArch64::PRFW_S_PZI - 713 |
| {12196, 4474, 4, 7 }, |
| // AArch64::PTRUES_B - 714 |
| {12220, 4481, 2, 6 }, |
| // AArch64::PTRUES_D - 715 |
| {12232, 4487, 2, 6 }, |
| // AArch64::PTRUES_H - 716 |
| {12244, 4493, 2, 6 }, |
| // AArch64::PTRUES_S - 717 |
| {12256, 4499, 2, 6 }, |
| // AArch64::PTRUE_B - 718 |
| {12268, 4505, 2, 6 }, |
| // AArch64::PTRUE_D - 719 |
| {12279, 4511, 2, 6 }, |
| // AArch64::PTRUE_H - 720 |
| {12290, 4517, 2, 6 }, |
| // AArch64::PTRUE_S - 721 |
| {12301, 4523, 2, 6 }, |
| // AArch64::RET - 722 |
| {12312, 4529, 1, 1 }, |
| // AArch64::SBCSWr - 723 |
| {12316, 4530, 3, 3 }, |
| // AArch64::SBCSXr - 724 |
| {12316, 4533, 3, 3 }, |
| // AArch64::SBCWr - 725 |
| {12328, 4536, 3, 3 }, |
| // AArch64::SBCXr - 726 |
| {12328, 4539, 3, 3 }, |
| // AArch64::SBFMWri - 727 |
| {12339, 4542, 4, 4 }, |
| {12354, 4546, 4, 4 }, |
| {12366, 4550, 4, 4 }, |
| // AArch64::SBFMXri - 730 |
| {12339, 4554, 4, 4 }, |
| {12354, 4558, 4, 4 }, |
| {12366, 4562, 4, 4 }, |
| {12378, 4566, 4, 4 }, |
| // AArch64::SEL_PPPP - 734 |
| {12390, 4570, 4, 8 }, |
| // AArch64::SEL_ZPZZ_B - 735 |
| {12390, 4578, 4, 8 }, |
| // AArch64::SEL_ZPZZ_D - 736 |
| {12413, 4586, 4, 8 }, |
| // AArch64::SEL_ZPZZ_H - 737 |
| {12436, 4594, 4, 8 }, |
| // AArch64::SEL_ZPZZ_S - 738 |
| {12459, 4602, 4, 8 }, |
| // AArch64::SMADDLrrr - 739 |
| {12482, 4610, 4, 4 }, |
| // AArch64::SMSUBLrrr - 740 |
| {12499, 4614, 4, 4 }, |
| // AArch64::SQDECB_XPiI - 741 |
| {12517, 4618, 4, 8 }, |
| {12527, 4626, 4, 8 }, |
| // AArch64::SQDECB_XPiWdI - 743 |
| {12543, 4634, 4, 8 }, |
| {12559, 4642, 4, 8 }, |
| // AArch64::SQDECD_XPiI - 745 |
| {12581, 4650, 4, 8 }, |
| {12591, 4658, 4, 8 }, |
| // AArch64::SQDECD_XPiWdI - 747 |
| {12607, 4666, 4, 8 }, |
| {12623, 4674, 4, 8 }, |
| // AArch64::SQDECD_ZPiI - 749 |
| {12645, 4682, 4, 8 }, |
| {12657, 4690, 4, 8 }, |
| // AArch64::SQDECH_XPiI - 751 |
| {12675, 4698, 4, 8 }, |
| {12685, 4706, 4, 8 }, |
| // AArch64::SQDECH_XPiWdI - 753 |
| {12701, 4714, 4, 8 }, |
| {12717, 4722, 4, 8 }, |
| // AArch64::SQDECH_ZPiI - 755 |
| {12739, 4730, 4, 8 }, |
| {12751, 4738, 4, 8 }, |
| // AArch64::SQDECW_XPiI - 757 |
| {12769, 4746, 4, 8 }, |
| {12779, 4754, 4, 8 }, |
| // AArch64::SQDECW_XPiWdI - 759 |
| {12795, 4762, 4, 8 }, |
| {12811, 4770, 4, 8 }, |
| // AArch64::SQDECW_ZPiI - 761 |
| {12833, 4778, 4, 8 }, |
| {12845, 4786, 4, 8 }, |
| // AArch64::SQINCB_XPiI - 763 |
| {12863, 4794, 4, 8 }, |
| {12873, 4802, 4, 8 }, |
| // AArch64::SQINCB_XPiWdI - 765 |
| {12889, 4810, 4, 8 }, |
| {12905, 4818, 4, 8 }, |
| // AArch64::SQINCD_XPiI - 767 |
| {12927, 4826, 4, 8 }, |
| {12937, 4834, 4, 8 }, |
| // AArch64::SQINCD_XPiWdI - 769 |
| {12953, 4842, 4, 8 }, |
| {12969, 4850, 4, 8 }, |
| // AArch64::SQINCD_ZPiI - 771 |
| {12991, 4858, 4, 8 }, |
| {13003, 4866, 4, 8 }, |
| // AArch64::SQINCH_XPiI - 773 |
| {13021, 4874, 4, 8 }, |
| {13031, 4882, 4, 8 }, |
| // AArch64::SQINCH_XPiWdI - 775 |
| {13047, 4890, 4, 8 }, |
| {13063, 4898, 4, 8 }, |
| // AArch64::SQINCH_ZPiI - 777 |
| {13085, 4906, 4, 8 }, |
| {13097, 4914, 4, 8 }, |
| // AArch64::SQINCW_XPiI - 779 |
| {13115, 4922, 4, 8 }, |
| {13125, 4930, 4, 8 }, |
| // AArch64::SQINCW_XPiWdI - 781 |
| {13141, 4938, 4, 8 }, |
| {13157, 4946, 4, 8 }, |
| // AArch64::SQINCW_ZPiI - 783 |
| {13179, 4954, 4, 8 }, |
| {13191, 4962, 4, 8 }, |
| // AArch64::SST1B_D_IMM - 785 |
| {13209, 4970, 4, 7 }, |
| // AArch64::SST1B_S_IMM - 786 |
| {13233, 4977, 4, 7 }, |
| // AArch64::SST1D_IMM - 787 |
| {13257, 4984, 4, 7 }, |
| // AArch64::SST1H_D_IMM - 788 |
| {13281, 4991, 4, 7 }, |
| // AArch64::SST1H_S_IMM - 789 |
| {13305, 4998, 4, 7 }, |
| // AArch64::SST1Q - 790 |
| {13329, 5005, 4, 6 }, |
| // AArch64::SST1W_D_IMM - 791 |
| {13353, 5011, 4, 7 }, |
| // AArch64::SST1W_IMM - 792 |
| {13377, 5018, 4, 7 }, |
| // AArch64::ST1B_2Z_IMM - 793 |
| {13401, 5025, 4, 8 }, |
| // AArch64::ST1B_4Z_IMM - 794 |
| {13401, 5033, 4, 8 }, |
| // AArch64::ST1B_D_IMM - 795 |
| {13423, 5041, 4, 8 }, |
| // AArch64::ST1B_H_IMM - 796 |
| {13445, 5049, 4, 8 }, |
| // AArch64::ST1B_IMM - 797 |
| {13467, 5057, 4, 8 }, |
| // AArch64::ST1B_S_IMM - 798 |
| {13489, 5065, 4, 8 }, |
| // AArch64::ST1B_VG2_M2ZPXI - 799 |
| {13511, 5073, 4, 7 }, |
| // AArch64::ST1B_VG4_M4ZPXI - 800 |
| {13533, 5080, 4, 7 }, |
| // AArch64::ST1D_2Z_IMM - 801 |
| {13555, 5087, 4, 8 }, |
| // AArch64::ST1D_4Z_IMM - 802 |
| {13555, 5095, 4, 8 }, |
| // AArch64::ST1D_IMM - 803 |
| {13577, 5103, 4, 8 }, |
| // AArch64::ST1D_Q_IMM - 804 |
| {13599, 5111, 4, 6 }, |
| // AArch64::ST1D_VG2_M2ZPXI - 805 |
| {13621, 5117, 4, 7 }, |
| // AArch64::ST1D_VG4_M4ZPXI - 806 |
| {13621, 5124, 4, 7 }, |
| // AArch64::ST1Fourv16b_POST - 807 |
| {13643, 5131, 4, 7 }, |
| // AArch64::ST1Fourv1d_POST - 808 |
| {13663, 5138, 4, 7 }, |
| // AArch64::ST1Fourv2d_POST - 809 |
| {13683, 5145, 4, 7 }, |
| // AArch64::ST1Fourv2s_POST - 810 |
| {13703, 5152, 4, 7 }, |
| // AArch64::ST1Fourv4h_POST - 811 |
| {13723, 5159, 4, 7 }, |
| // AArch64::ST1Fourv4s_POST - 812 |
| {13743, 5166, 4, 7 }, |
| // AArch64::ST1Fourv8b_POST - 813 |
| {13763, 5173, 4, 7 }, |
| // AArch64::ST1Fourv8h_POST - 814 |
| {13783, 5180, 4, 7 }, |
| // AArch64::ST1H_2Z_IMM - 815 |
| {13803, 5187, 4, 8 }, |
| // AArch64::ST1H_4Z_IMM - 816 |
| {13803, 5195, 4, 8 }, |
| // AArch64::ST1H_D_IMM - 817 |
| {13825, 5203, 4, 8 }, |
| // AArch64::ST1H_IMM - 818 |
| {13847, 5211, 4, 8 }, |
| // AArch64::ST1H_S_IMM - 819 |
| {13869, 5219, 4, 8 }, |
| // AArch64::ST1H_VG2_M2ZPXI - 820 |
| {13891, 5227, 4, 7 }, |
| // AArch64::ST1H_VG4_M4ZPXI - 821 |
| {13913, 5234, 4, 7 }, |
| // AArch64::ST1Onev16b_POST - 822 |
| {13935, 5241, 4, 7 }, |
| // AArch64::ST1Onev1d_POST - 823 |
| {13955, 5248, 4, 7 }, |
| // AArch64::ST1Onev2d_POST - 824 |
| {13974, 5255, 4, 7 }, |
| // AArch64::ST1Onev2s_POST - 825 |
| {13994, 5262, 4, 7 }, |
| // AArch64::ST1Onev4h_POST - 826 |
| {14013, 5269, 4, 7 }, |
| // AArch64::ST1Onev4s_POST - 827 |
| {14032, 5276, 4, 7 }, |
| // AArch64::ST1Onev8b_POST - 828 |
| {14052, 5283, 4, 7 }, |
| // AArch64::ST1Onev8h_POST - 829 |
| {14071, 5290, 4, 7 }, |
| // AArch64::ST1Threev16b_POST - 830 |
| {14091, 5297, 4, 7 }, |
| // AArch64::ST1Threev1d_POST - 831 |
| {14111, 5304, 4, 7 }, |
| // AArch64::ST1Threev2d_POST - 832 |
| {14131, 5311, 4, 7 }, |
| // AArch64::ST1Threev2s_POST - 833 |
| {14151, 5318, 4, 7 }, |
| // AArch64::ST1Threev4h_POST - 834 |
| {14171, 5325, 4, 7 }, |
| // AArch64::ST1Threev4s_POST - 835 |
| {14191, 5332, 4, 7 }, |
| // AArch64::ST1Threev8b_POST - 836 |
| {14211, 5339, 4, 7 }, |
| // AArch64::ST1Threev8h_POST - 837 |
| {14231, 5346, 4, 7 }, |
| // AArch64::ST1Twov16b_POST - 838 |
| {14251, 5353, 4, 7 }, |
| // AArch64::ST1Twov1d_POST - 839 |
| {14271, 5360, 4, 7 }, |
| // AArch64::ST1Twov2d_POST - 840 |
| {14291, 5367, 4, 7 }, |
| // AArch64::ST1Twov2s_POST - 841 |
| {14311, 5374, 4, 7 }, |
| // AArch64::ST1Twov4h_POST - 842 |
| {14331, 5381, 4, 7 }, |
| // AArch64::ST1Twov4s_POST - 843 |
| {14351, 5388, 4, 7 }, |
| // AArch64::ST1Twov8b_POST - 844 |
| {14371, 5395, 4, 7 }, |
| // AArch64::ST1Twov8h_POST - 845 |
| {14391, 5402, 4, 7 }, |
| // AArch64::ST1W_2Z_IMM - 846 |
| {14411, 5409, 4, 8 }, |
| // AArch64::ST1W_4Z_IMM - 847 |
| {14411, 5417, 4, 8 }, |
| // AArch64::ST1W_D_IMM - 848 |
| {14433, 5425, 4, 8 }, |
| // AArch64::ST1W_IMM - 849 |
| {14455, 5433, 4, 8 }, |
| // AArch64::ST1W_Q_IMM - 850 |
| {14477, 5441, 4, 6 }, |
| // AArch64::ST1W_VG2_M2ZPXI - 851 |
| {14499, 5447, 4, 7 }, |
| // AArch64::ST1W_VG4_M4ZPXI - 852 |
| {14499, 5454, 4, 7 }, |
| // AArch64::ST1_MXIPXX_H_B - 853 |
| {14521, 5461, 6, 9 }, |
| // AArch64::ST1_MXIPXX_H_D - 854 |
| {14555, 5470, 6, 9 }, |
| // AArch64::ST1_MXIPXX_H_H - 855 |
| {14589, 5479, 6, 9 }, |
| // AArch64::ST1_MXIPXX_H_Q - 856 |
| {14623, 5488, 6, 9 }, |
| // AArch64::ST1_MXIPXX_H_S - 857 |
| {14657, 5497, 6, 9 }, |
| // AArch64::ST1_MXIPXX_V_B - 858 |
| {14691, 5506, 6, 9 }, |
| // AArch64::ST1_MXIPXX_V_D - 859 |
| {14725, 5515, 6, 9 }, |
| // AArch64::ST1_MXIPXX_V_H - 860 |
| {14759, 5524, 6, 9 }, |
| // AArch64::ST1_MXIPXX_V_Q - 861 |
| {14793, 5533, 6, 9 }, |
| // AArch64::ST1_MXIPXX_V_S - 862 |
| {14827, 5542, 6, 9 }, |
| // AArch64::ST1i16_POST - 863 |
| {14861, 5551, 5, 8 }, |
| // AArch64::ST1i32_POST - 864 |
| {14884, 5559, 5, 8 }, |
| // AArch64::ST1i64_POST - 865 |
| {14907, 5567, 5, 8 }, |
| // AArch64::ST1i8_POST - 866 |
| {14930, 5575, 5, 8 }, |
| // AArch64::ST2B_IMM - 867 |
| {14953, 5583, 4, 8 }, |
| // AArch64::ST2D_IMM - 868 |
| {14975, 5591, 4, 8 }, |
| // AArch64::ST2GOffset - 869 |
| {14997, 5599, 3, 6 }, |
| // AArch64::ST2H_IMM - 870 |
| {15011, 5605, 4, 8 }, |
| // AArch64::ST2Q_IMM - 871 |
| {15033, 5613, 4, 8 }, |
| // AArch64::ST2Twov16b_POST - 872 |
| {15055, 5621, 4, 7 }, |
| // AArch64::ST2Twov2d_POST - 873 |
| {15075, 5628, 4, 7 }, |
| // AArch64::ST2Twov2s_POST - 874 |
| {15095, 5635, 4, 7 }, |
| // AArch64::ST2Twov4h_POST - 875 |
| {15115, 5642, 4, 7 }, |
| // AArch64::ST2Twov4s_POST - 876 |
| {15135, 5649, 4, 7 }, |
| // AArch64::ST2Twov8b_POST - 877 |
| {15155, 5656, 4, 7 }, |
| // AArch64::ST2Twov8h_POST - 878 |
| {15175, 5663, 4, 7 }, |
| // AArch64::ST2W_IMM - 879 |
| {15195, 5670, 4, 8 }, |
| // AArch64::ST2i16_POST - 880 |
| {15217, 5678, 5, 8 }, |
| // AArch64::ST2i32_POST - 881 |
| {15240, 5686, 5, 8 }, |
| // AArch64::ST2i64_POST - 882 |
| {15263, 5694, 5, 8 }, |
| // AArch64::ST2i8_POST - 883 |
| {15287, 5702, 5, 8 }, |
| // AArch64::ST3B_IMM - 884 |
| {15310, 5710, 4, 8 }, |
| // AArch64::ST3D_IMM - 885 |
| {15332, 5718, 4, 8 }, |
| // AArch64::ST3H_IMM - 886 |
| {15354, 5726, 4, 8 }, |
| // AArch64::ST3Q_IMM - 887 |
| {15376, 5734, 4, 8 }, |
| // AArch64::ST3Threev16b_POST - 888 |
| {15398, 5742, 4, 7 }, |
| // AArch64::ST3Threev2d_POST - 889 |
| {15418, 5749, 4, 7 }, |
| // AArch64::ST3Threev2s_POST - 890 |
| {15438, 5756, 4, 7 }, |
| // AArch64::ST3Threev4h_POST - 891 |
| {15458, 5763, 4, 7 }, |
| // AArch64::ST3Threev4s_POST - 892 |
| {15478, 5770, 4, 7 }, |
| // AArch64::ST3Threev8b_POST - 893 |
| {15498, 5777, 4, 7 }, |
| // AArch64::ST3Threev8h_POST - 894 |
| {15518, 5784, 4, 7 }, |
| // AArch64::ST3W_IMM - 895 |
| {15538, 5791, 4, 8 }, |
| // AArch64::ST3i16_POST - 896 |
| {15560, 5799, 5, 8 }, |
| // AArch64::ST3i32_POST - 897 |
| {15583, 5807, 5, 8 }, |
| // AArch64::ST3i64_POST - 898 |
| {15607, 5815, 5, 8 }, |
| // AArch64::ST3i8_POST - 899 |
| {15631, 5823, 5, 8 }, |
| // AArch64::ST4B_IMM - 900 |
| {15654, 5831, 4, 8 }, |
| // AArch64::ST4D_IMM - 901 |
| {15676, 5839, 4, 8 }, |
| // AArch64::ST4Fourv16b_POST - 902 |
| {15698, 5847, 4, 7 }, |
| // AArch64::ST4Fourv2d_POST - 903 |
| {15718, 5854, 4, 7 }, |
| // AArch64::ST4Fourv2s_POST - 904 |
| {15738, 5861, 4, 7 }, |
| // AArch64::ST4Fourv4h_POST - 905 |
| {15758, 5868, 4, 7 }, |
| // AArch64::ST4Fourv4s_POST - 906 |
| {15778, 5875, 4, 7 }, |
| // AArch64::ST4Fourv8b_POST - 907 |
| {15798, 5882, 4, 7 }, |
| // AArch64::ST4Fourv8h_POST - 908 |
| {15818, 5889, 4, 7 }, |
| // AArch64::ST4H_IMM - 909 |
| {15838, 5896, 4, 8 }, |
| // AArch64::ST4Q_IMM - 910 |
| {15860, 5904, 4, 8 }, |
| // AArch64::ST4W_IMM - 911 |
| {15882, 5912, 4, 8 }, |
| // AArch64::ST4i16_POST - 912 |
| {15904, 5920, 5, 8 }, |
| // AArch64::ST4i32_POST - 913 |
| {15927, 5928, 5, 8 }, |
| // AArch64::ST4i64_POST - 914 |
| {15951, 5936, 5, 8 }, |
| // AArch64::ST4i8_POST - 915 |
| {15975, 5944, 5, 8 }, |
| // AArch64::STGOffset - 916 |
| {15998, 5952, 3, 6 }, |
| // AArch64::STGPi - 917 |
| {16011, 5958, 4, 7 }, |
| // AArch64::STLURBi - 918 |
| {16029, 5965, 3, 6 }, |
| // AArch64::STLURHi - 919 |
| {16045, 5971, 3, 6 }, |
| // AArch64::STLURWi - 920 |
| {16061, 5977, 3, 6 }, |
| // AArch64::STLURXi - 921 |
| {16061, 5983, 3, 6 }, |
| // AArch64::STLURbi - 922 |
| {16061, 5989, 3, 9 }, |
| // AArch64::STLURdi - 923 |
| {16061, 5998, 3, 9 }, |
| // AArch64::STLURhi - 924 |
| {16061, 6007, 3, 9 }, |
| // AArch64::STLURqi - 925 |
| {16061, 6016, 3, 9 }, |
| // AArch64::STLURsi - 926 |
| {16061, 6025, 3, 9 }, |
| // AArch64::STNPDi - 927 |
| {16076, 6034, 4, 4 }, |
| // AArch64::STNPQi - 928 |
| {16076, 6038, 4, 4 }, |
| // AArch64::STNPSi - 929 |
| {16076, 6042, 4, 4 }, |
| // AArch64::STNPWi - 930 |
| {16076, 6046, 4, 4 }, |
| // AArch64::STNPXi - 931 |
| {16076, 6050, 4, 4 }, |
| // AArch64::STNT1B_2Z_IMM - 932 |
| {16094, 6054, 4, 8 }, |
| // AArch64::STNT1B_4Z_IMM - 933 |
| {16094, 6062, 4, 8 }, |
| // AArch64::STNT1B_VG2_M2ZPXI - 934 |
| {16118, 6070, 4, 7 }, |
| // AArch64::STNT1B_VG4_M4ZPXI - 935 |
| {16142, 6077, 4, 7 }, |
| // AArch64::STNT1B_ZRI - 936 |
| {16166, 6084, 4, 8 }, |
| // AArch64::STNT1B_ZZR_D_REAL - 937 |
| {16190, 6092, 4, 7 }, |
| // AArch64::STNT1B_ZZR_S_REAL - 938 |
| {16216, 6099, 4, 7 }, |
| // AArch64::STNT1D_2Z_IMM - 939 |
| {16242, 6106, 4, 8 }, |
| // AArch64::STNT1D_4Z_IMM - 940 |
| {16242, 6114, 4, 8 }, |
| // AArch64::STNT1D_VG2_M2ZPXI - 941 |
| {16266, 6122, 4, 7 }, |
| // AArch64::STNT1D_VG4_M4ZPXI - 942 |
| {16266, 6129, 4, 7 }, |
| // AArch64::STNT1D_ZRI - 943 |
| {16290, 6136, 4, 8 }, |
| // AArch64::STNT1D_ZZR_D_REAL - 944 |
| {16314, 6144, 4, 7 }, |
| // AArch64::STNT1H_2Z_IMM - 945 |
| {16340, 6151, 4, 8 }, |
| // AArch64::STNT1H_4Z_IMM - 946 |
| {16340, 6159, 4, 8 }, |
| // AArch64::STNT1H_VG2_M2ZPXI - 947 |
| {16364, 6167, 4, 7 }, |
| // AArch64::STNT1H_VG4_M4ZPXI - 948 |
| {16388, 6174, 4, 7 }, |
| // AArch64::STNT1H_ZRI - 949 |
| {16412, 6181, 4, 8 }, |
| // AArch64::STNT1H_ZZR_D_REAL - 950 |
| {16436, 6189, 4, 7 }, |
| // AArch64::STNT1H_ZZR_S_REAL - 951 |
| {16462, 6196, 4, 7 }, |
| // AArch64::STNT1W_2Z_IMM - 952 |
| {16488, 6203, 4, 8 }, |
| // AArch64::STNT1W_4Z_IMM - 953 |
| {16488, 6211, 4, 8 }, |
| // AArch64::STNT1W_VG2_M2ZPXI - 954 |
| {16512, 6219, 4, 7 }, |
| // AArch64::STNT1W_VG4_M4ZPXI - 955 |
| {16512, 6226, 4, 7 }, |
| // AArch64::STNT1W_ZRI - 956 |
| {16536, 6233, 4, 8 }, |
| // AArch64::STNT1W_ZZR_D_REAL - 957 |
| {16560, 6241, 4, 7 }, |
| // AArch64::STNT1W_ZZR_S_REAL - 958 |
| {16586, 6248, 4, 7 }, |
| // AArch64::STPDi - 959 |
| {16612, 6255, 4, 4 }, |
| // AArch64::STPQi - 960 |
| {16612, 6259, 4, 4 }, |
| // AArch64::STPSi - 961 |
| {16612, 6263, 4, 4 }, |
| // AArch64::STPWi - 962 |
| {16612, 6267, 4, 4 }, |
| // AArch64::STPXi - 963 |
| {16612, 6271, 4, 4 }, |
| // AArch64::STRBBroX - 964 |
| {16629, 6275, 5, 5 }, |
| // AArch64::STRBBui - 965 |
| {16647, 6280, 3, 3 }, |
| // AArch64::STRBroX - 966 |
| {16661, 6283, 5, 5 }, |
| // AArch64::STRBui - 967 |
| {16678, 6288, 3, 3 }, |
| // AArch64::STRDroX - 968 |
| {16661, 6291, 5, 5 }, |
| // AArch64::STRDui - 969 |
| {16678, 6296, 3, 3 }, |
| // AArch64::STRHHroX - 970 |
| {16691, 6299, 5, 5 }, |
| // AArch64::STRHHui - 971 |
| {16709, 6304, 3, 3 }, |
| // AArch64::STRHroX - 972 |
| {16661, 6307, 5, 5 }, |
| // AArch64::STRHui - 973 |
| {16678, 6312, 3, 3 }, |
| // AArch64::STRQroX - 974 |
| {16661, 6315, 5, 5 }, |
| // AArch64::STRQui - 975 |
| {16678, 6320, 3, 3 }, |
| // AArch64::STRSroX - 976 |
| {16661, 6323, 5, 5 }, |
| // AArch64::STRSui - 977 |
| {16678, 6328, 3, 3 }, |
| // AArch64::STRWroX - 978 |
| {16661, 6331, 5, 5 }, |
| // AArch64::STRWui - 979 |
| {16678, 6336, 3, 3 }, |
| // AArch64::STRXroX - 980 |
| {16661, 6339, 5, 5 }, |
| // AArch64::STRXui - 981 |
| {16678, 6344, 3, 3 }, |
| // AArch64::STR_PXI - 982 |
| {16723, 6347, 3, 7 }, |
| // AArch64::STR_ZA - 983 |
| {16738, 6354, 5, 8 }, |
| // AArch64::STR_ZXI - 984 |
| {16723, 6362, 3, 7 }, |
| // AArch64::STTRBi - 985 |
| {16763, 6369, 3, 3 }, |
| // AArch64::STTRHi - 986 |
| {16778, 6372, 3, 3 }, |
| // AArch64::STTRWi - 987 |
| {16793, 6375, 3, 3 }, |
| // AArch64::STTRXi - 988 |
| {16793, 6378, 3, 3 }, |
| // AArch64::STURBBi - 989 |
| {16807, 6381, 3, 3 }, |
| // AArch64::STURBi - 990 |
| {16822, 6384, 3, 3 }, |
| // AArch64::STURDi - 991 |
| {16822, 6387, 3, 3 }, |
| // AArch64::STURHHi - 992 |
| {16836, 6390, 3, 3 }, |
| // AArch64::STURHi - 993 |
| {16822, 6393, 3, 3 }, |
| // AArch64::STURQi - 994 |
| {16822, 6396, 3, 3 }, |
| // AArch64::STURSi - 995 |
| {16822, 6399, 3, 3 }, |
| // AArch64::STURWi - 996 |
| {16822, 6402, 3, 3 }, |
| // AArch64::STURXi - 997 |
| {16822, 6405, 3, 3 }, |
| // AArch64::STZ2GOffset - 998 |
| {16851, 6408, 3, 6 }, |
| // AArch64::STZGOffset - 999 |
| {16866, 6414, 3, 6 }, |
| // AArch64::SUBSWri - 1000 |
| {16880, 6420, 4, 2 }, |
| // AArch64::SUBSWrs - 1001 |
| {16893, 6422, 4, 4 }, |
| {16904, 6426, 4, 3 }, |
| {16919, 6429, 4, 4 }, |
| {16931, 6433, 4, 3 }, |
| {16947, 6436, 4, 4 }, |
| // AArch64::SUBSWrx - 1006 |
| {16893, 6440, 4, 4 }, |
| {16963, 6444, 4, 3 }, |
| {16947, 6447, 4, 4 }, |
| // AArch64::SUBSXri - 1009 |
| {16880, 6451, 4, 2 }, |
| // AArch64::SUBSXrs - 1010 |
| {16893, 6453, 4, 4 }, |
| {16904, 6457, 4, 3 }, |
| {16919, 6460, 4, 4 }, |
| {16931, 6464, 4, 3 }, |
| {16947, 6467, 4, 4 }, |
| // AArch64::SUBSXrx - 1015 |
| {16963, 6471, 4, 3 }, |
| // AArch64::SUBSXrx64 - 1016 |
| {16893, 6474, 4, 4 }, |
| {16963, 6478, 4, 3 }, |
| {16947, 6481, 4, 4 }, |
| // AArch64::SUBWrs - 1019 |
| {16978, 6485, 4, 4 }, |
| {16989, 6489, 4, 3 }, |
| {17004, 6492, 4, 4 }, |
| // AArch64::SUBWrx - 1022 |
| {17004, 6496, 4, 4 }, |
| {17004, 6500, 4, 4 }, |
| // AArch64::SUBXrs - 1024 |
| {16978, 6504, 4, 4 }, |
| {16989, 6508, 4, 3 }, |
| {17004, 6511, 4, 4 }, |
| // AArch64::SUBXrx64 - 1027 |
| {17004, 6515, 4, 4 }, |
| {17004, 6519, 4, 4 }, |
| // AArch64::SYSPxt_XZR - 1029 |
| {17019, 6523, 5, 8 }, |
| // AArch64::SYSxt - 1030 |
| {17043, 6531, 5, 5 }, |
| // AArch64::UBFMWri - 1031 |
| {17066, 6536, 4, 4 }, |
| {17081, 6540, 4, 4 }, |
| {17093, 6544, 4, 4 }, |
| // AArch64::UBFMXri - 1034 |
| {17066, 6548, 4, 4 }, |
| {17081, 6552, 4, 4 }, |
| {17093, 6556, 4, 4 }, |
| {17105, 6560, 4, 4 }, |
| // AArch64::UMADDLrrr - 1038 |
| {17117, 6564, 4, 4 }, |
| // AArch64::UMOVvi32 - 1039 |
| {17134, 6568, 3, 5 }, |
| // AArch64::UMOVvi32_idx0 - 1040 |
| {17134, 6573, 3, 6 }, |
| // AArch64::UMOVvi64 - 1041 |
| {17153, 6579, 3, 5 }, |
| // AArch64::UMOVvi64_idx0 - 1042 |
| {17153, 6584, 3, 6 }, |
| // AArch64::UMSUBLrrr - 1043 |
| {17172, 6590, 4, 4 }, |
| // AArch64::UQDECB_WPiI - 1044 |
| {17190, 6594, 4, 8 }, |
| {17200, 6602, 4, 8 }, |
| // AArch64::UQDECB_XPiI - 1046 |
| {17190, 6610, 4, 8 }, |
| {17200, 6618, 4, 8 }, |
| // AArch64::UQDECD_WPiI - 1048 |
| {17216, 6626, 4, 8 }, |
| {17226, 6634, 4, 8 }, |
| // AArch64::UQDECD_XPiI - 1050 |
| {17216, 6642, 4, 8 }, |
| {17226, 6650, 4, 8 }, |
| // AArch64::UQDECD_ZPiI - 1052 |
| {17242, 6658, 4, 8 }, |
| {17254, 6666, 4, 8 }, |
| // AArch64::UQDECH_WPiI - 1054 |
| {17272, 6674, 4, 8 }, |
| {17282, 6682, 4, 8 }, |
| // AArch64::UQDECH_XPiI - 1056 |
| {17272, 6690, 4, 8 }, |
| {17282, 6698, 4, 8 }, |
| // AArch64::UQDECH_ZPiI - 1058 |
| {17298, 6706, 4, 8 }, |
| {17310, 6714, 4, 8 }, |
| // AArch64::UQDECW_WPiI - 1060 |
| {17328, 6722, 4, 8 }, |
| {17338, 6730, 4, 8 }, |
| // AArch64::UQDECW_XPiI - 1062 |
| {17328, 6738, 4, 8 }, |
| {17338, 6746, 4, 8 }, |
| // AArch64::UQDECW_ZPiI - 1064 |
| {17354, 6754, 4, 8 }, |
| {17366, 6762, 4, 8 }, |
| // AArch64::UQINCB_WPiI - 1066 |
| {17384, 6770, 4, 8 }, |
| {17394, 6778, 4, 8 }, |
| // AArch64::UQINCB_XPiI - 1068 |
| {17384, 6786, 4, 8 }, |
| {17394, 6794, 4, 8 }, |
| // AArch64::UQINCD_WPiI - 1070 |
| {17410, 6802, 4, 8 }, |
| {17420, 6810, 4, 8 }, |
| // AArch64::UQINCD_XPiI - 1072 |
| {17410, 6818, 4, 8 }, |
| {17420, 6826, 4, 8 }, |
| // AArch64::UQINCD_ZPiI - 1074 |
| {17436, 6834, 4, 8 }, |
| {17448, 6842, 4, 8 }, |
| // AArch64::UQINCH_WPiI - 1076 |
| {17466, 6850, 4, 8 }, |
| {17476, 6858, 4, 8 }, |
| // AArch64::UQINCH_XPiI - 1078 |
| {17466, 6866, 4, 8 }, |
| {17476, 6874, 4, 8 }, |
| // AArch64::UQINCH_ZPiI - 1080 |
| {17492, 6882, 4, 8 }, |
| {17504, 6890, 4, 8 }, |
| // AArch64::UQINCW_WPiI - 1082 |
| {17522, 6898, 4, 8 }, |
| {17532, 6906, 4, 8 }, |
| // AArch64::UQINCW_XPiI - 1084 |
| {17522, 6914, 4, 8 }, |
| {17532, 6922, 4, 8 }, |
| // AArch64::UQINCW_ZPiI - 1086 |
| {17548, 6930, 4, 8 }, |
| {17560, 6938, 4, 8 }, |
| // AArch64::XPACLRI - 1088 |
| {17578, 6946, 0, 3 }, |
| // AArch64::ZERO_M - 1089 |
| {17586, 6949, 1, 4 }, |
| {17596, 6953, 1, 4 }, |
| {17609, 6957, 1, 4 }, |
| {17622, 6961, 1, 4 }, |
| {17635, 6965, 1, 4 }, |
| {17648, 6969, 1, 4 }, |
| {17661, 6973, 1, 4 }, |
| {17674, 6977, 1, 4 }, |
| {17693, 6981, 1, 4 }, |
| {17712, 6985, 1, 4 }, |
| {17731, 6989, 1, 4 }, |
| {17750, 6993, 1, 4 }, |
| {17775, 6997, 1, 4 }, |
| {17800, 7001, 1, 4 }, |
| {17825, 7005, 1, 4 }, |
| }; |
| |
| static const AliasPatternCond Conds[] = { |
| // (ADDSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - 0 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 2 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) - 6 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (ADDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 9 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) - 13 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| // (ADDSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) - 17 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (ADDSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 20 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| // (ADDSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - 24 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 26 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) - 30 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (ADDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 33 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) - 37 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (ADDSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - 40 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(24)}, |
| // (ADDSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - 44 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (ADDSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 47 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(24)}, |
| // (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0) - 51 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0) - 55 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 59 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) - 63 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| // (ADDWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 67 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| // (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0) - 71 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0) - 75 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 79 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - 83 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(24)}, |
| // (ADDXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 87 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(24)}, |
| // (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2) - 91 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 93 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh) - 97 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (ANDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 100 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2) - 104 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 106 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh) - 110 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (ANDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 113 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 117 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ANDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 125 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ANDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 129 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) - 133 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (AND_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 141 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Custom, 1}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (AND_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 148 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Custom, 2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (AND_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 155 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Custom, 3}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (AUTIA1716) - 162 |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeaturePAuth}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (AUTIASP) - 165 |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeaturePAuth}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (AUTIAZ) - 168 |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeaturePAuth}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (AUTIB1716) - 171 |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeaturePAuth}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (AUTIBSP) - 174 |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeaturePAuth}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (AUTIBZ) - 177 |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeaturePAuth}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (BICSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 180 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (BICSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 184 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (BICWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 188 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (BICXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 192 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (CLREX 15) - 196 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| // (CNTB_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 197 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CNTB_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 204 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CNTD_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 211 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CNTD_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 218 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CNTH_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 225 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CNTH_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 232 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CNTW_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) - 239 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CNTW_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) - 246 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CPY_ZPmI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 253 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 260 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 267 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 274 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CPY_ZPmR_B ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 281 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CPY_ZPmR_D ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn) - 289 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CPY_ZPmR_H ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 297 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CPY_ZPmR_S ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) - 305 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CPY_ZPmV_B ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn) - 313 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CPY_ZPmV_D ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn) - 321 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CPY_ZPmV_H ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn) - 329 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CPY_ZPmV_S ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn) - 337 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CPY_ZPzI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) - 345 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CPY_ZPzI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) - 351 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CPY_ZPzI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) - 357 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CPY_ZPzI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) - 363 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - 369 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_Custom, 4}, |
| // (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 373 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Custom, 4}, |
| // (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - 377 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Custom, 4}, |
| // (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 381 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Custom, 4}, |
| // (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - 385 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_Custom, 4}, |
| // (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 389 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Custom, 4}, |
| // (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - 393 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_Custom, 4}, |
| // (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 397 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Custom, 4}, |
| // (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - 401 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Custom, 4}, |
| // (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - 405 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Custom, 4}, |
| // (DCPS1 0) - 409 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (DCPS2 0) - 410 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (DCPS3 0) - 411 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureEL3}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DECB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 415 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DECB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 423 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DECD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 431 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DECD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 439 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 447 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 455 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DECH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 463 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DECH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 471 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 479 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 487 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DECW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 495 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DECW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 503 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 511 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 519 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DSB 0) - 527 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (DSB 4) - 528 |
| {AliasPatternCond::K_Imm, uint32_t(4)}, |
| // (DSB { 1, 1, 0, 0 }) - 529 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::HasV8_0rOps}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUPM_ZI ZPR16:$Zd, sve_preferred_logical_imm16:$imm) - 533 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Custom, 5}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUPM_ZI ZPR32:$Zd, sve_preferred_logical_imm32:$imm) - 539 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Custom, 6}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUPM_ZI ZPR64:$Zd, sve_preferred_logical_imm64:$imm) - 545 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Custom, 7}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUPM_ZI ZPR8:$Zd, sve_logical_imm8:$imm) - 551 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Custom, 1}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUPM_ZI ZPR16:$Zd, sve_logical_imm16:$imm) - 557 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Custom, 2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUPM_ZI ZPR32:$Zd, sve_logical_imm32:$imm) - 563 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Custom, 3}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZI_B ZPR8:$Zd, cpy_imm8_opt_lsl_i8:$imm) - 569 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZI_D ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm) - 574 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZI_D ZPR64:$Zd, 0, 0) - 579 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZI_H ZPR16:$Zd, cpy_imm8_opt_lsl_i16:$imm) - 586 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZI_H ZPR16:$Zd, 0, 0) - 591 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZI_S ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm) - 598 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZI_S ZPR32:$Zd, 0, 0) - 603 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZR_B ZPR8:$Zd, GPR32sp:$Rn) - 610 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZR_D ZPR64:$Zd, GPR64sp:$Rn) - 616 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZR_H ZPR16:$Zd, GPR32sp:$Rn) - 622 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZR_S ZPR32:$Zd, GPR32sp:$Rn) - 628 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZZI_B ZPR8:$Zd, FPR8asZPR:$Bn, 0) - 634 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZZI_B ZPR8:$Zd, ZPR8:$Zn, sve_elm_idx_extdup_b:$idx) - 641 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZZI_D ZPR64:$Zd, FPR64asZPR:$Dn, 0) - 647 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZZI_D ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx) - 654 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZZI_H ZPR16:$Zd, FPR16asZPR:$Hn, 0) - 660 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZZI_H ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx) - 667 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZZI_Q ZPR128:$Zd, FPR128asZPR:$Qn, 0) - 673 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZZI_Q ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx) - 680 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZZI_S ZPR32:$Zd, FPR32asZPR:$Sn, 0) - 686 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (DUP_ZZI_S ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx) - 693 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (EONWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 699 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (EONXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 703 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) - 707 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (EORWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 715 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (EORXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 719 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) - 723 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (EOR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 731 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Custom, 1}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (EOR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 738 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Custom, 2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (EOR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 745 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Custom, 3}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (EXTRACT_ZPMXI_H_B ZPR8:$Zd, PPR3bAny:$Pg, TileVectorOpH8:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm) - 752 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (EXTRACT_ZPMXI_H_D ZPR64:$Zd, PPR3bAny:$Pg, TileVectorOpH64:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm) - 760 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (EXTRACT_ZPMXI_H_H ZPR16:$Zd, PPR3bAny:$Pg, TileVectorOpH16:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm) - 768 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (EXTRACT_ZPMXI_H_Q ZPR128:$Zd, PPR3bAny:$Pg, TileVectorOpH128:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm) - 776 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (EXTRACT_ZPMXI_H_S ZPR32:$Zd, PPR3bAny:$Pg, TileVectorOpH32:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm) - 784 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (EXTRACT_ZPMXI_V_B ZPR8:$Zd, PPR3bAny:$Pg, TileVectorOpV8:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm) - 792 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (EXTRACT_ZPMXI_V_D ZPR64:$Zd, PPR3bAny:$Pg, TileVectorOpV64:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm) - 800 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (EXTRACT_ZPMXI_V_H ZPR16:$Zd, PPR3bAny:$Pg, TileVectorOpV16:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm) - 808 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (EXTRACT_ZPMXI_V_Q ZPR128:$Zd, PPR3bAny:$Pg, TileVectorOpV128:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm) - 816 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (EXTRACT_ZPMXI_V_S ZPR32:$Zd, PPR3bAny:$Pg, TileVectorOpV32:$ZAn, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm) - 824 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift) - 832 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift) - 835 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (FCPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, fpimm64:$imm8) - 838 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (FCPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, fpimm16:$imm8) - 845 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (FCPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, fpimm32:$imm8) - 852 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (FDUP_ZI_D ZPR64:$Zd, fpimm64:$imm8) - 859 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (FDUP_ZI_H ZPR16:$Zd, fpimm16:$imm8) - 864 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (FDUP_ZI_S ZPR32:$Zd, fpimm32:$imm8) - 869 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLD1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 874 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLD1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 881 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLD1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 888 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLD1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 895 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLD1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 902 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLD1Q Z_q:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 909 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 915 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 922 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 929 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 936 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 943 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLD1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 950 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLD1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 957 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLDFF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 964 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLDFF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 971 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLDFF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 978 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLDFF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 985 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLDFF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 992 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLDFF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 999 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLDFF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 1006 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLDFF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1013 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLDFF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 1020 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLDFF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1027 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLDFF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 1034 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (GLDFF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 1041 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (HINT { 0, 0, 0 }) - 1048 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (HINT { 0, 0, 1 }) - 1049 |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| // (HINT { 0, 1, 0 }) - 1050 |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| // (HINT { 0, 1, 1 }) - 1051 |
| {AliasPatternCond::K_Imm, uint32_t(3)}, |
| // (HINT { 1, 0, 0 }) - 1052 |
| {AliasPatternCond::K_Imm, uint32_t(4)}, |
| // (HINT { 1, 0, 1 }) - 1053 |
| {AliasPatternCond::K_Imm, uint32_t(5)}, |
| // (HINT { 1, 1, 0 }) - 1054 |
| {AliasPatternCond::K_Imm, uint32_t(6)}, |
| // (HINT { 1, 0, 0, 0, 0 }) - 1055 |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRAS}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (HINT 20) - 1059 |
| {AliasPatternCond::K_Imm, uint32_t(20)}, |
| // (HINT 32) - 1060 |
| {AliasPatternCond::K_Imm, uint32_t(32)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureBranchTargetId}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (HINT btihint_op:$op) - 1064 |
| {AliasPatternCond::K_Custom, 8}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureBranchTargetId}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (HINT psbhint_op:$op) - 1068 |
| {AliasPatternCond::K_Custom, 9}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSPE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (HINT 22) - 1072 |
| {AliasPatternCond::K_Imm, uint32_t(22)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureCLRBHB}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INCB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 1076 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INCB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 1084 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INCD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 1092 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INCD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 1100 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 1108 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 1116 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INCH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 1124 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INCH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 1132 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 1140 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 1148 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INCW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 1156 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INCW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) - 1164 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 1172 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 1180 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INSERT_MXIPZ_H_B TileVectorOpH8:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, ZPR8:$Zn) - 1188 |
| {AliasPatternCond::K_RegClass, AArch64::MPR8RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INSERT_MXIPZ_H_D TileVectorOpH64:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, ZPR64:$Zn) - 1197 |
| {AliasPatternCond::K_RegClass, AArch64::MPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INSERT_MXIPZ_H_H TileVectorOpH16:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, ZPR16:$Zn) - 1206 |
| {AliasPatternCond::K_RegClass, AArch64::MPR16RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INSERT_MXIPZ_H_Q TileVectorOpH128:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, ZPR128:$Zn) - 1215 |
| {AliasPatternCond::K_RegClass, AArch64::MPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INSERT_MXIPZ_H_S TileVectorOpH32:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, ZPR32:$Zn) - 1224 |
| {AliasPatternCond::K_RegClass, AArch64::MPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INSERT_MXIPZ_V_B TileVectorOpV8:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, ZPR8:$Zn) - 1233 |
| {AliasPatternCond::K_RegClass, AArch64::MPR8RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INSERT_MXIPZ_V_D TileVectorOpV64:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, ZPR64:$Zn) - 1242 |
| {AliasPatternCond::K_RegClass, AArch64::MPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INSERT_MXIPZ_V_H TileVectorOpV16:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, ZPR16:$Zn) - 1251 |
| {AliasPatternCond::K_RegClass, AArch64::MPR16RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INSERT_MXIPZ_V_Q TileVectorOpV128:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, ZPR128:$Zn) - 1260 |
| {AliasPatternCond::K_RegClass, AArch64::MPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INSERT_MXIPZ_V_S TileVectorOpV32:$ZAd, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, ZPR32:$Zn) - 1269 |
| {AliasPatternCond::K_RegClass, AArch64::MPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INSvi16gpr V128:$dst, VectorIndexH:$idx, GPR32:$src) - 1278 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, VectorIndexH:$idx2) - 1285 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INSvi32gpr V128:$dst, VectorIndexS:$idx, GPR32:$src) - 1292 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, VectorIndexS:$idx2) - 1299 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INSvi64gpr V128:$dst, VectorIndexD:$idx, GPR64:$src) - 1306 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, VectorIndexD:$idx2) - 1313 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INSvi8gpr V128:$dst, VectorIndexB:$idx, GPR32:$src) - 1320 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, VectorIndexB:$idx2) - 1327 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (IRG GPR64sp:$dst, GPR64sp:$src, XZR) - 1334 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureMTE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ISB 15) - 1340 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| // (LD1B_2Z_IMM ZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1341 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1B_4Z_IMM ZZZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1349 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1357 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1B_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1365 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1B_IMM_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1373 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1381 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1B_VG2_M2ZPXI ZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1389 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1B_VG4_M4ZPXI ZZZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1396 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1D_2Z_IMM ZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1403 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1D_4Z_IMM ZZZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1411 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1419 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1D_Q_IMM Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1427 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1D_VG2_M2ZPXI ZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1433 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1D_VG4_M4ZPXI ZZZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1440 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 1447 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 1454 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 1461 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 1468 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 1475 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 1482 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 1489 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 1496 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1H_2Z_IMM ZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1503 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1H_4Z_IMM ZZZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1511 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1519 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1527 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1535 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1H_VG2_M2ZPXI ZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1543 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1H_VG4_M4ZPXI ZZZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 1550 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 1557 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 1564 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 1571 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 1578 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 1585 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 1592 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 1599 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 1606 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1613 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1621 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RB_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1629 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1637 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RD_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1645 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1653 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RH_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1661 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1669 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RO_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1677 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureMatMulFP64}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RO_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1687 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureMatMulFP64}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RO_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1697 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureMatMulFP64}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RO_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1707 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureMatMulFP64}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RQ_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1717 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RQ_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1725 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RQ_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1733 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RQ_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1741 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RSB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1749 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RSB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1757 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RSB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1765 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RSH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1773 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RSH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1781 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RSW_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1789 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1797 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1RW_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1805 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Rv16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 1813 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Rv1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 1820 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Rv2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 1827 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Rv2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 1834 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Rv4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 1841 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Rv4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 1848 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Rv8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 1855 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Rv8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 1862 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1869 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1SB_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1877 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1885 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1893 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1901 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 1909 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 1917 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 1924 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 1931 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 1938 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 1945 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 1952 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 1959 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 1966 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 1973 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 1980 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 1987 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 1994 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 2001 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 2008 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 2015 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 2022 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1W_2Z_IMM ZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 2029 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1W_4Z_IMM ZZZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 2037 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2045 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2053 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1W_Q_IMM Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2061 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1W_VG2_M2ZPXI ZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 2067 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1W_VG4_M4ZPXI ZZZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 2074 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1_MXIPXX_H_B TileVectorOpH8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2081 |
| {AliasPatternCond::K_RegClass, AArch64::MPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1_MXIPXX_H_D TileVectorOpH64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2090 |
| {AliasPatternCond::K_RegClass, AArch64::MPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1_MXIPXX_H_H TileVectorOpH16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2099 |
| {AliasPatternCond::K_RegClass, AArch64::MPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1_MXIPXX_H_Q TileVectorOpH128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2108 |
| {AliasPatternCond::K_RegClass, AArch64::MPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1_MXIPXX_H_S TileVectorOpH32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2117 |
| {AliasPatternCond::K_RegClass, AArch64::MPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1_MXIPXX_V_B TileVectorOpV8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2126 |
| {AliasPatternCond::K_RegClass, AArch64::MPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1_MXIPXX_V_D TileVectorOpV64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2135 |
| {AliasPatternCond::K_RegClass, AArch64::MPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1_MXIPXX_V_H TileVectorOpV16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2144 |
| {AliasPatternCond::K_RegClass, AArch64::MPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1_MXIPXX_V_Q TileVectorOpV128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2153 |
| {AliasPatternCond::K_RegClass, AArch64::MPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1_MXIPXX_V_S TileVectorOpV32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2162 |
| {AliasPatternCond::K_RegClass, AArch64::MPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - 2171 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - 2180 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - 2189 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - 2198 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2207 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2215 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2223 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2Q_IMM ZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2231 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2p1}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2Rv16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 2239 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2Rv1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 2246 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2Rv2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 2253 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2Rv2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 2260 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2Rv4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 2267 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2Rv4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 2274 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2Rv8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 2281 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2Rv8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 2288 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 2295 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 2302 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 2309 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 2316 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 2323 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 2330 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 2337 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2344 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - 2352 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - 2361 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - 2370 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - 2379 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2388 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2396 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2404 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3Q_IMM ZZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2412 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2p1}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3Rv16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 2420 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3Rv1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 2427 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3Rv2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 2434 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3Rv2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 2441 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3Rv4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 2448 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3Rv4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 2455 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3Rv8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 2462 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3Rv8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 2469 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 2476 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 2483 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 2490 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 2497 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 2504 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 2511 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 2518 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2525 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - 2533 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - 2542 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - 2551 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - 2560 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2569 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2577 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 2585 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 2592 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 2599 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 2606 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 2613 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 2620 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 2627 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2634 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4Q_IMM ZZZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2642 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2p1}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4Rv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 2650 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4Rv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 2657 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4Rv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 2664 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4Rv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 2671 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4Rv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 2678 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4Rv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 2685 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4Rv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 2692 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4Rv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 2699 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 2706 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - 2714 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - 2723 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - 2732 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LD4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - 2741 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDADDB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2750 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDADDH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2756 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDADDLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2762 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDADDLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2768 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDADDLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2774 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDADDLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2780 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDADDW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2786 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDADDX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2792 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDAPURBi GPR32:$Rt, GPR64sp:$Rn, 0) - 2798 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC_IMMO}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDAPURHi GPR32:$Rt, GPR64sp:$Rn, 0) - 2804 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC_IMMO}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDAPURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2810 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC_IMMO}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDAPURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2816 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC_IMMO}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDAPURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 2822 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC_IMMO}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDAPURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2828 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC_IMMO}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDAPURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 2834 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC_IMMO}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDAPURXi GPR64:$Rt, GPR64sp:$Rn, 0) - 2840 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC_IMMO}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDAPURbi FPR8:$Rt, GPR64sp:$Rn, 0) - 2846 |
| {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC3}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDAPURdi FPR64:$Rt, GPR64sp:$Rn, 0) - 2855 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC3}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDAPURhi FPR16:$Rt, GPR64sp:$Rn, 0) - 2864 |
| {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC3}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDAPURi GPR32:$Rt, GPR64sp:$Rn, 0) - 2873 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC_IMMO}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDAPURqi FPR128:$Rt, GPR64sp:$Rn, 0) - 2879 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC3}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDAPURsi FPR32:$Rt, GPR64sp:$Rn, 0) - 2888 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC3}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDCLRB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2897 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDCLRH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2903 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDCLRLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2909 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDCLRLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2915 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDCLRLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2921 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDCLRLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2927 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDCLRW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2933 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDCLRX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2939 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDEORB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2945 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDEORH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2951 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDEORLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 2957 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDEORLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 2963 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDEORLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2969 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDEORLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2975 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDEORW WZR, GPR32:$Rs, GPR64sp:$Rn) - 2981 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDEORX XZR, GPR64:$Rs, GPR64sp:$Rn) - 2987 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDFF1B_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 2993 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDFF1B_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3000 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDFF1B_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3007 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDFF1B_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3014 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDFF1D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3021 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDFF1H_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3028 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDFF1H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3035 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDFF1H_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3042 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDFF1SB_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3049 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDFF1SB_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3056 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDFF1SB_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3063 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDFF1SH_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3070 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDFF1SH_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3077 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDFF1SW_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3084 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDFF1W_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3091 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDFF1W_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 3098 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDG GPR64:$Rt, GPR64sp:$Rn, 0) - 3105 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureMTE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3112 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNF1B_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3119 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNF1B_IMM_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3126 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3133 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3140 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3147 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNF1H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3154 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3161 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3168 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNF1SB_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3175 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3182 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3189 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3196 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3203 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3210 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3217 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 3224 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 3228 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 3232 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 3236 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3240 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDNT1B_2Z_IMM ZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3244 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1B_4Z_IMM ZZZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3252 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1B_VG2_M2ZPXI ZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3260 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1B_VG4_M4ZPXI ZZZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3267 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3274 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1B_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3282 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1B_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3289 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1D_2Z_IMM ZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3296 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1D_4Z_IMM ZZZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3304 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1D_VG2_M2ZPXI ZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3312 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1D_VG4_M4ZPXI ZZZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3319 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3326 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1D_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3334 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1H_2Z_IMM ZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3341 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1H_4Z_IMM ZZZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3349 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1H_VG2_M2ZPXI ZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3357 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1H_VG4_M4ZPXI ZZZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3364 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3371 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1H_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3379 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1H_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3386 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1SB_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3393 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1SB_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3400 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1SH_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3407 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1SH_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3414 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1SW_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3421 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1W_2Z_IMM ZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3428 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1W_4Z_IMM ZZZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3436 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1W_VG2_M2ZPXI ZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3444 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1W_VG4_M4ZPXI ZZZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 3451 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 3458 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1W_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 3466 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDNT1W_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 3473 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 3480 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 3484 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDPSWi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3488 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 3492 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 3496 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 3500 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRAAindexed GPR64:$Rt, GPR64sp:$Rn, 0) - 3504 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeaturePAuth}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDRABindexed GPR64:$Rt, GPR64sp:$Rn, 0) - 3510 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeaturePAuth}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3516 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRBBui GPR32:$Rt, GPR64sp:$Rn, 0) - 3521 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3524 |
| {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) - 3529 |
| {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3532 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) - 3537 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3540 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRHHui GPR32:$Rt, GPR64sp:$Rn, 0) - 3545 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3548 |
| {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) - 3553 |
| {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3556 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) - 3561 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSBWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3564 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSBWui GPR32:$Rt, GPR64sp:$Rn, 0) - 3569 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSBXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3572 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSBXui GPR64:$Rt, GPR64sp:$Rn, 0) - 3577 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSHWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3580 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSHWui GPR32:$Rt, GPR64sp:$Rn, 0) - 3585 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSHXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3588 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSHXui GPR64:$Rt, GPR64sp:$Rn, 0) - 3593 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSWroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3596 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSWui GPR64:$Rt, GPR64sp:$Rn, 0) - 3601 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3604 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) - 3609 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3612 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRWui GPR32z:$Rt, GPR64sp:$Rn, 0) - 3617 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 3620 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDRXui GPR64z:$Rt, GPR64sp:$Rn, 0) - 3625 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) - 3628 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDR_ZA MatrixOp:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm4, GPR64sp:$Rn, 0) - 3635 |
| {AliasPatternCond::K_RegClass, AArch64::MPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) - 3643 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSETB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3650 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSETH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3656 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSETLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3662 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSETLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3668 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSETLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3674 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSETLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3680 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSETW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3686 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSETX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3692 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3698 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3704 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3710 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3716 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3722 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3728 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3734 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3740 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSMINB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3746 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSMINH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3752 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3758 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3764 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3770 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3776 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSMINW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3782 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDSMINX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3788 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - 3794 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - 3797 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDTRSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3800 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDTRSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3803 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDTRSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3806 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDTRSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3809 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDTRSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 3812 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3815 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3818 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDUMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3821 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDUMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3827 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDUMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3833 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDUMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3839 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDUMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3845 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDUMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3851 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDUMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3857 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDUMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3863 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDUMINB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3869 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDUMINH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3875 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDUMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) - 3881 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDUMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) - 3887 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDUMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3893 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDUMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3899 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDUMINW WZR, GPR32:$Rs, GPR64sp:$Rn) - 3905 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDUMINX XZR, GPR64:$Rs, GPR64sp:$Rn) - 3911 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureLSE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (LDURBBi GPR32:$Rt, GPR64sp:$Rn, 0) - 3917 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) - 3920 |
| {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) - 3923 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURHHi GPR32:$Rt, GPR64sp:$Rn, 0) - 3926 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) - 3929 |
| {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) - 3932 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3935 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3938 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - 3941 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - 3944 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - 3947 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) - 3950 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURWi GPR32z:$Rt, GPR64sp:$Rn, 0) - 3953 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (LDURXi GPR64z:$Rt, GPR64sp:$Rn, 0) - 3956 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (MADDWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - 3959 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| // (MADDXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - 3963 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| // (MOVA_2ZMXI_H_B ZZ_b_mul_r:$Zd, TileVectorOpH8:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm3s2range:$imm) - 3967 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_2ZMXI_H_D ZZ_d_mul_r:$Zd, TileVectorOpH64:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s2range:$imm) - 3973 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_2ZMXI_H_H ZZ_h_mul_r:$Zd, TileVectorOpH16:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm2s2range:$imm) - 3979 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_2ZMXI_H_S ZZ_s_mul_r:$Zd, TileVectorOpH32:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm1s2range:$imm) - 3985 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_2ZMXI_V_B ZZ_b_mul_r:$Zd, TileVectorOpV8:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm3s2range:$imm) - 3991 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_2ZMXI_V_D ZZ_d_mul_r:$Zd, TileVectorOpV64:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s2range:$imm) - 3997 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_2ZMXI_V_H ZZ_h_mul_r:$Zd, TileVectorOpV16:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm2s2range:$imm) - 4003 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_2ZMXI_V_S ZZ_s_mul_r:$Zd, TileVectorOpV32:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm1s2range:$imm) - 4009 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_4ZMXI_H_B ZZZZ_b_mul_r:$Zd, TileVectorOpH8:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm2s4range:$imm) - 4015 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_4ZMXI_H_D ZZZZ_d_mul_r:$Zd, TileVectorOpH64:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm) - 4021 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_4ZMXI_H_H ZZZZ_h_mul_r:$Zd, TileVectorOpH16:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm1s4range:$imm) - 4027 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_4ZMXI_H_S ZZZZ_s_mul_r:$Zd, TileVectorOpH32:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm) - 4033 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_4ZMXI_V_B ZZZZ_b_mul_r:$Zd, TileVectorOpV8:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm2s4range:$imm) - 4039 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_4ZMXI_V_D ZZZZ_d_mul_r:$Zd, TileVectorOpV64:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm) - 4045 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_4ZMXI_V_H ZZZZ_h_mul_r:$Zd, TileVectorOpV16:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm1s4range:$imm) - 4051 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_4ZMXI_V_S ZZZZ_s_mul_r:$Zd, TileVectorOpV32:$ZAn, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm) - 4057 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_MXI2Z_H_B TileVectorOpH8:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm3s2range:$imm, ZZ_b_mul_r:$Zn) - 4063 |
| {AliasPatternCond::K_RegClass, AArch64::MPR8RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_MXI2Z_H_D TileVectorOpH64:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s2range:$imm, ZZ_d_mul_r:$Zn) - 4071 |
| {AliasPatternCond::K_RegClass, AArch64::MPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_MXI2Z_H_H TileVectorOpH16:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm2s2range:$imm, ZZ_h_mul_r:$Zn) - 4079 |
| {AliasPatternCond::K_RegClass, AArch64::MPR16RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_MXI2Z_H_S TileVectorOpH32:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm1s2range:$imm, ZZ_s_mul_r:$Zn) - 4087 |
| {AliasPatternCond::K_RegClass, AArch64::MPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_MXI2Z_V_B TileVectorOpV8:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm3s2range:$imm, ZZ_b_mul_r:$Zn) - 4095 |
| {AliasPatternCond::K_RegClass, AArch64::MPR8RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_MXI2Z_V_D TileVectorOpV64:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s2range:$imm, ZZ_d_mul_r:$Zn) - 4103 |
| {AliasPatternCond::K_RegClass, AArch64::MPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_MXI2Z_V_H TileVectorOpV16:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm2s2range:$imm, ZZ_h_mul_r:$Zn) - 4111 |
| {AliasPatternCond::K_RegClass, AArch64::MPR16RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_MXI2Z_V_S TileVectorOpV32:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm1s2range:$imm, ZZ_s_mul_r:$Zn) - 4119 |
| {AliasPatternCond::K_RegClass, AArch64::MPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_MXI4Z_H_B TileVectorOpH8:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm2s4range:$imm, ZZZZ_b_mul_r:$Zn) - 4127 |
| {AliasPatternCond::K_RegClass, AArch64::MPR8RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_MXI4Z_H_D TileVectorOpH64:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm, ZZZZ_d_mul_r:$Zn) - 4135 |
| {AliasPatternCond::K_RegClass, AArch64::MPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_MXI4Z_H_H TileVectorOpH16:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm1s4range:$imm, ZZZZ_h_mul_r:$Zn) - 4143 |
| {AliasPatternCond::K_RegClass, AArch64::MPR16RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_MXI4Z_H_S TileVectorOpH32:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm, ZZZZ_s_mul_r:$Zn) - 4151 |
| {AliasPatternCond::K_RegClass, AArch64::MPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_MXI4Z_V_B TileVectorOpV8:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm2s4range:$imm, ZZZZ_b_mul_r:$Zn) - 4159 |
| {AliasPatternCond::K_RegClass, AArch64::MPR8RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_MXI4Z_V_D TileVectorOpV64:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm, ZZZZ_d_mul_r:$Zn) - 4167 |
| {AliasPatternCond::K_RegClass, AArch64::MPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_MXI4Z_V_H TileVectorOpV16:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm1s4range:$imm, ZZZZ_h_mul_r:$Zn) - 4175 |
| {AliasPatternCond::K_RegClass, AArch64::MPR16RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_MXI4Z_V_S TileVectorOpV32:$ZAd, MatrixIndexGPR32Op12_15:$Rs, uimm0s4range:$imm, ZZZZ_s_mul_r:$Zn) - 4183 |
| {AliasPatternCond::K_RegClass, AArch64::MPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_VG2_2ZMXI ZZ_d_mul_r:$Zd, MatrixOp64:$ZAn, MatrixIndexGPR32Op8_11:$Rs, sme_elm_idx0_7:$imm) - 4191 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_8_11RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_VG2_MXI2Z MatrixOp64:$ZAd, MatrixIndexGPR32Op8_11:$Rs, sme_elm_idx0_7:$imm, ZZ_d_mul_r:$Zn) - 4197 |
| {AliasPatternCond::K_RegClass, AArch64::MPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_8_11RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_VG4_4ZMXI ZZZZ_d_mul_r:$Zd, MatrixOp64:$ZAn, MatrixIndexGPR32Op8_11:$Rs, sme_elm_idx0_7:$imm) - 4205 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_8_11RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MOVA_VG4_MXI4Z MatrixOp64:$ZAd, MatrixIndexGPR32Op8_11:$Rs, sme_elm_idx0_7:$imm, ZZZZ_d_mul_r:$Zn) - 4211 |
| {AliasPatternCond::K_RegClass, AArch64::MPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_8_11RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MSRpstatesvcrImm1 { 0, 1, 1 }, { 1 }) - 4219 |
| {AliasPatternCond::K_Imm, uint32_t(3)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MSRpstatesvcrImm1 { 0, 0, 1 }, { 1 }) - 4224 |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MSRpstatesvcrImm1 { 0, 1, 0 }, { 1 }) - 4229 |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MSRpstatesvcrImm1 { 0, 1, 1 }, { 0 }) - 4234 |
| {AliasPatternCond::K_Imm, uint32_t(3)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MSRpstatesvcrImm1 { 0, 0, 1 }, { 0 }) - 4239 |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MSRpstatesvcrImm1 { 0, 1, 0 }, { 0 }) - 4244 |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MSUBWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - 4249 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| // (MSUBXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - 4253 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| // (NOTv16i8 V128:$Vd, V128:$Vn) - 4257 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| // (NOTv8i8 V64:$Vd, V64:$Vn) - 4259 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0) - 4261 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh) - 4265 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (ORNWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 4268 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0) - 4272 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh) - 4276 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (ORNXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 4279 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) - 4283 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0) - 4291 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ORRWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 4295 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0) - 4299 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ORRXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 4303 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) - 4307 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ORR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) - 4315 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Custom, 1}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ORR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) - 4322 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Custom, 2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ORR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) - 4329 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Custom, 3}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn) - 4336 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ORRv16i8 V128:$dst, V128:$src, V128:$src) - 4343 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (ORRv8i8 V64:$dst, V64:$src, V64:$src) - 4346 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (PACIA1716) - 4349 |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeaturePAuth}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PACIASP) - 4352 |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeaturePAuth}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PACIAZ) - 4355 |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeaturePAuth}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PACIB1716) - 4358 |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeaturePAuth}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PACIBSP) - 4361 |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeaturePAuth}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PACIBZ) - 4364 |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeaturePAuth}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PMOV_PZI_B PPR8:$Pd, ZPRAny:$Zn, 0) - 4367 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2p1}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PMOV_ZIP_B ZPRAny:$Zd, 0, PPR8:$Pn) - 4374 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2p1}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PRFB_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4382 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PRFB_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4389 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PRFB_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4397 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PRFD_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4404 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PRFD_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4411 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PRFD_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4419 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PRFH_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4426 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PRFH_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4433 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PRFH_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4441 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PRFMroX prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 4448 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (PRFMui prfop:$Rt, GPR64sp:$Rn, 0) - 4453 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (PRFUMi prfop:$Rt, GPR64sp:$Rn, 0) - 4456 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (PRFW_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4459 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PRFW_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 4466 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PRFW_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4474 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PTRUES_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) - 4481 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PTRUES_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) - 4487 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PTRUES_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) - 4493 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PTRUES_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) - 4499 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PTRUE_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) - 4505 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PTRUE_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) - 4511 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PTRUE_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) - 4517 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (PTRUE_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) - 4523 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (RET LR) - 4529 |
| {AliasPatternCond::K_Reg, AArch64::LR}, |
| // (SBCSWr GPR32:$dst, WZR, GPR32:$src) - 4530 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (SBCSXr GPR64:$dst, XZR, GPR64:$src) - 4533 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (SBCWr GPR32:$dst, WZR, GPR32:$src) - 4536 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (SBCXr GPR64:$dst, XZR, GPR64:$src) - 4539 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) - 4542 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| // (SBFMWri GPR32:$dst, GPR32:$src, 0, 7) - 4546 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| // (SBFMWri GPR32:$dst, GPR32:$src, 0, 15) - 4550 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| // (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) - 4554 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(63)}, |
| // (SBFMXri GPR64:$dst, GPR64:$src, 0, 7) - 4558 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| // (SBFMXri GPR64:$dst, GPR64:$src, 0, 15) - 4562 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| // (SBFMXri GPR64:$dst, GPR64:$src, 0, 31) - 4566 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| // (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd) - 4570 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 0}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SEL_ZPZZ_B ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd) - 4578 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 0}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SEL_ZPZZ_D ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd) - 4586 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 0}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SEL_ZPZZ_H ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd) - 4594 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 0}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SEL_ZPZZ_S ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd) - 4602 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_TiedReg, 0}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 4610 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| // (SMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 4614 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| // (SQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4618 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4626 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4634 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4642 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4650 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4658 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4666 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4674 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4682 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 4690 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4698 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4706 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4714 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4722 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4730 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 4738 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4746 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4754 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4762 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4770 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4778 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 4786 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4794 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4802 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4810 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4818 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4826 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4834 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4842 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4850 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4858 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 4866 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4874 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4882 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4890 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4898 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4906 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 4914 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 4922 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 4930 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) - 4938 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) - 4946 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 4954 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 4962 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4970 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4977 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4984 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 4991 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 4998 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SST1Q Z_q:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 5005 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) - 5011 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) - 5018 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1B_2Z_IMM ZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5025 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1B_4Z_IMM ZZZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5033 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5041 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5049 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5057 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5065 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1B_VG2_M2ZPXI ZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5073 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1B_VG4_M4ZPXI ZZZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5080 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1D_2Z_IMM ZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5087 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1D_4Z_IMM ZZZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5095 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5103 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1D_Q_IMM Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5111 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1D_VG2_M2ZPXI ZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5117 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1D_VG4_M4ZPXI ZZZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5124 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 5131 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - 5138 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 5145 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 5152 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 5159 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 5166 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 5173 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 5180 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1H_2Z_IMM ZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5187 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1H_4Z_IMM ZZZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5195 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5203 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5211 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5219 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1H_VG2_M2ZPXI ZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5227 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1H_VG4_M4ZPXI ZZZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5234 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - 5241 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - 5248 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - 5255 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - 5262 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - 5269 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - 5276 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - 5283 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - 5290 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 5297 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - 5304 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 5311 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 5318 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 5325 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 5332 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 5339 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 5346 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 5353 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - 5360 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 5367 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 5374 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 5381 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 5388 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 5395 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 5402 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1W_2Z_IMM ZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5409 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1W_4Z_IMM ZZZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5417 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5425 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5433 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1W_Q_IMM Z_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5441 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1W_VG2_M2ZPXI ZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5447 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1W_VG4_M4ZPXI ZZZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 5454 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1_MXIPXX_H_B TileVectorOpH8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5461 |
| {AliasPatternCond::K_RegClass, AArch64::MPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1_MXIPXX_H_D TileVectorOpH64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5470 |
| {AliasPatternCond::K_RegClass, AArch64::MPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1_MXIPXX_H_H TileVectorOpH16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5479 |
| {AliasPatternCond::K_RegClass, AArch64::MPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1_MXIPXX_H_Q TileVectorOpH128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5488 |
| {AliasPatternCond::K_RegClass, AArch64::MPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1_MXIPXX_H_S TileVectorOpH32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5497 |
| {AliasPatternCond::K_RegClass, AArch64::MPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1_MXIPXX_V_B TileVectorOpV8:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5506 |
| {AliasPatternCond::K_RegClass, AArch64::MPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1_MXIPXX_V_D TileVectorOpV64:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5515 |
| {AliasPatternCond::K_RegClass, AArch64::MPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1_MXIPXX_V_H TileVectorOpV16:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5524 |
| {AliasPatternCond::K_RegClass, AArch64::MPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1_MXIPXX_V_Q TileVectorOpV128:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_0:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5533 |
| {AliasPatternCond::K_RegClass, AArch64::MPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1_MXIPXX_V_S TileVectorOpV32:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) - 5542 |
| {AliasPatternCond::K_RegClass, AArch64::MPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - 5551 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - 5559 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - 5567 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - 5575 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5583 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5591 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST2GOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 5599 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureMTE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5605 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST2Q_IMM ZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5613 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2p1}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - 5621 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - 5628 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - 5635 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - 5642 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - 5649 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - 5656 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - 5663 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5670 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - 5678 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - 5686 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - 5694 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - 5702 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5710 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5718 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5726 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST3Q_IMM ZZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5734 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2p1}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - 5742 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - 5749 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - 5756 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - 5763 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - 5770 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - 5777 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - 5784 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5791 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR3RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - 5799 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - 5807 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - 5815 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - 5823 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5831 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5839 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - 5847 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - 5854 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - 5861 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - 5868 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - 5875 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - 5882 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::DDDDRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - 5889 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5896 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST4Q_IMM ZZZZ_q:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5904 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2p1}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 5912 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - 5920 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - 5928 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - 5936 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ST4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - 5944 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::QQQQRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STGOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 5952 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureMTE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STGPi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 5958 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureMTE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STLURBi GPR32:$Rt, GPR64sp:$Rn, 0) - 5965 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC_IMMO}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STLURHi GPR32:$Rt, GPR64sp:$Rn, 0) - 5971 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC_IMMO}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STLURWi GPR32:$Rt, GPR64sp:$Rn, 0) - 5977 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC_IMMO}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STLURXi GPR64:$Rt, GPR64sp:$Rn, 0) - 5983 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC_IMMO}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STLURbi FPR8:$Rt, GPR64sp:$Rn, 0) - 5989 |
| {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC3}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STLURdi FPR64:$Rt, GPR64sp:$Rn, 0) - 5998 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC3}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STLURhi FPR16:$Rt, GPR64sp:$Rn, 0) - 6007 |
| {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC3}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STLURqi FPR128:$Rt, GPR64sp:$Rn, 0) - 6016 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC3}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STLURsi FPR32:$Rt, GPR64sp:$Rn, 0) - 6025 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureRCPC3}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 6034 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 6038 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 6042 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 6046 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 6050 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STNT1B_2Z_IMM ZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6054 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1B_4Z_IMM ZZZZ_b_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6062 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1B_VG2_M2ZPXI ZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6070 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1B_VG4_M4ZPXI ZZZZ_b_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6077 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6084 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1B_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 6092 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1B_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 6099 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1D_2Z_IMM ZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6106 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1D_4Z_IMM ZZZZ_d_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6114 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1D_VG2_M2ZPXI ZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6122 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1D_VG4_M4ZPXI ZZZZ_d_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6129 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6136 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1D_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 6144 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1H_2Z_IMM ZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6151 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1H_4Z_IMM ZZZZ_h_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6159 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1H_VG2_M2ZPXI ZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6167 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1H_VG4_M4ZPXI ZZZZ_h_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6174 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6181 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1H_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 6189 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1H_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 6196 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1W_2Z_IMM ZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6203 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2Mul2RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1W_4Z_IMM ZZZZ_s_mul_r:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6211 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4Mul4RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2p1}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1W_VG2_M2ZPXI ZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6219 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR2StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1W_VG4_M4ZPXI ZZZZ_s_strided:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0) - 6226 |
| {AliasPatternCond::K_RegClass, AArch64::ZPR4StridedRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_p8to15RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) - 6233 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1W_ZZR_D_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR) - 6241 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STNT1W_ZZR_S_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR) - 6248 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::PPR_3bRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE2}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) - 6255 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) - 6259 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) - 6263 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) - 6267 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) - 6271 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6275 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRBBui GPR32z:$Rt, GPR64sp:$Rn, 0) - 6280 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6283 |
| {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) - 6288 |
| {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6291 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) - 6296 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6299 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRHHui GPR32z:$Rt, GPR64sp:$Rn, 0) - 6304 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6307 |
| {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) - 6312 |
| {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6315 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) - 6320 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6323 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) - 6328 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6331 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRWui GPR32z:$Rt, GPR64sp:$Rn, 0) - 6336 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - 6339 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STRXui GPR64z:$Rt, GPR64sp:$Rn, 0) - 6344 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) - 6347 |
| {AliasPatternCond::K_RegClass, AArch64::PPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STR_ZA MatrixOp:$ZAt, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm4, GPR64sp:$Rn, 0) - 6354 |
| {AliasPatternCond::K_RegClass, AArch64::MPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::MatrixIndexGPR32_12_15RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) - 6362 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - 6369 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - 6372 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - 6375 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - 6378 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STURBBi GPR32z:$Rt, GPR64sp:$Rn, 0) - 6381 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) - 6384 |
| {AliasPatternCond::K_RegClass, AArch64::FPR8RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) - 6387 |
| {AliasPatternCond::K_RegClass, AArch64::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STURHHi GPR32z:$Rt, GPR64sp:$Rn, 0) - 6390 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) - 6393 |
| {AliasPatternCond::K_RegClass, AArch64::FPR16RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) - 6396 |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) - 6399 |
| {AliasPatternCond::K_RegClass, AArch64::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STURWi GPR32z:$Rt, GPR64sp:$Rn, 0) - 6402 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STURXi GPR64z:$Rt, GPR64sp:$Rn, 0) - 6405 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (STZ2GOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 6408 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureMTE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (STZGOffset GPR64sp:$Rt, GPR64sp:$Rn, 0) - 6414 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureMTE}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SUBSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - 6420 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - 6422 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) - 6426 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0) - 6429 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) - 6433 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (SUBSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 6436 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) - 6440 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| // (SUBSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) - 6444 |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (SUBSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 6447 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| // (SUBSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - 6451 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - 6453 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) - 6457 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0) - 6460 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) - 6464 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (SUBSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 6467 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) - 6471 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (SUBSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - 6474 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(24)}, |
| // (SUBSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - 6478 |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (SUBSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 6481 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(24)}, |
| // (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0) - 6485 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) - 6489 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::WZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| // (SUBWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - 6492 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) - 6496 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| // (SUBWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - 6500 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| // (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0) - 6504 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) - 6508 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| // (SUBXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - 6511 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - 6515 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(24)}, |
| // (SUBXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - 6519 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64spRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64sponlyRegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(24)}, |
| // (SYSPxt_XZR imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) - 6523 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureD128}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (SYSxt imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) - 6531 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| // (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) - 6536 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| // (UBFMWri GPR32:$dst, GPR32:$src, 0, 7) - 6540 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| // (UBFMWri GPR32:$dst, GPR32:$src, 0, 15) - 6544 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| // (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) - 6548 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(63)}, |
| // (UBFMXri GPR64:$dst, GPR64:$src, 0, 7) - 6552 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| // (UBFMXri GPR64:$dst, GPR64:$src, 0, 15) - 6556 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| // (UBFMXri GPR64:$dst, GPR64:$src, 0, 31) - 6560 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| // (UMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 6564 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| // (UMOVvi32 GPR32:$dst, V128:$src, VectorIndexS:$idx) - 6568 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UMOVvi32_idx0 GPR32:$dst, V128:$src, VectorIndex0:$idx) - 6573 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UMOVvi64 GPR64:$dst, V128:$src, VectorIndexD:$idx) - 6579 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UMOVvi64_idx0 GPR64:$dst, V128:$src, VectorIndex0:$idx) - 6584 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::FPR128RegClassID}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureNEON}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - 6590 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Reg, AArch64::XZR}, |
| // (UQDECB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6594 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6602 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6610 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6618 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6626 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6634 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6642 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6650 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 6658 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 6666 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6674 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6682 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6690 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6698 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 6706 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 6714 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6722 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6730 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6738 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6746 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 6754 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 6762 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6770 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6778 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6786 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6794 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6802 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6810 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6818 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6826 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 6834 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) - 6842 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6850 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6858 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6866 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6874 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 6882 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) - 6890 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6898 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) - 6906 |
| {AliasPatternCond::K_RegClass, AArch64::GPR32RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) - 6914 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) - 6922 |
| {AliasPatternCond::K_RegClass, AArch64::GPR64RegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) - 6930 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (UQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) - 6938 |
| {AliasPatternCond::K_RegClass, AArch64::ZPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSVE}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (XPACLRI) - 6946 |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeaturePAuth}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ZERO_M { 1, 1, 1, 1, 1, 1, 1, 1 }) - 6949 |
| {AliasPatternCond::K_Imm, uint32_t(255)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ZERO_M { 0, 1, 0, 1, 0, 1, 0, 1 }) - 6953 |
| {AliasPatternCond::K_Imm, uint32_t(85)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ZERO_M { 1, 0, 1, 0, 1, 0, 1, 0 }) - 6957 |
| {AliasPatternCond::K_Imm, uint32_t(170)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ZERO_M { 0, 0, 0, 1, 0, 0, 0, 1 }) - 6961 |
| {AliasPatternCond::K_Imm, uint32_t(17)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ZERO_M { 0, 0, 1, 0, 0, 0, 1, 0 }) - 6965 |
| {AliasPatternCond::K_Imm, uint32_t(34)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ZERO_M { 0, 1, 0, 0, 0, 1, 0, 0 }) - 6969 |
| {AliasPatternCond::K_Imm, uint32_t(68)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ZERO_M { 1, 0, 0, 0, 1, 0, 0, 0 }) - 6973 |
| {AliasPatternCond::K_Imm, uint32_t(136)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ZERO_M { 0, 0, 1, 1, 0, 0, 1, 1 }) - 6977 |
| {AliasPatternCond::K_Imm, uint32_t(51)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ZERO_M { 1, 0, 0, 1, 1, 0, 0, 1 }) - 6981 |
| {AliasPatternCond::K_Imm, uint32_t(153)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ZERO_M { 0, 1, 1, 0, 0, 1, 1, 0 }) - 6985 |
| {AliasPatternCond::K_Imm, uint32_t(102)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ZERO_M { 1, 1, 0, 0, 1, 1, 0, 0 }) - 6989 |
| {AliasPatternCond::K_Imm, uint32_t(204)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ZERO_M { 0, 1, 1, 1, 0, 1, 1, 1 }) - 6993 |
| {AliasPatternCond::K_Imm, uint32_t(119)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ZERO_M { 1, 0, 1, 1, 1, 0, 1, 1 }) - 6997 |
| {AliasPatternCond::K_Imm, uint32_t(187)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ZERO_M { 1, 1, 0, 1, 1, 1, 0, 1 }) - 7001 |
| {AliasPatternCond::K_Imm, uint32_t(221)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (ZERO_M { 1, 1, 1, 0, 1, 1, 1, 0 }) - 7005 |
| {AliasPatternCond::K_Imm, uint32_t(238)}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureAll}, |
| {AliasPatternCond::K_OrFeature, AArch64::FeatureSME}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| }; |
| |
| static const char AsmStrings[] = |
| /* 0 */ "cmn $\x02, $\xFF\x03\x01\0" |
| /* 13 */ "cmn $\x02, $\x03\0" |
| /* 24 */ "cmn $\x02, $\x03$\xFF\x04\x02\0" |
| /* 39 */ "adds $\x01, $\x02, $\x03\0" |
| /* 55 */ "cmn $\x02, $\x03$\xFF\x04\x03\0" |
| /* 70 */ "mov $\x01, $\x02\0" |
| /* 81 */ "add $\x01, $\x02, $\x03\0" |
| /* 96 */ "tst $\x02, $\xFF\x03\x04\0" |
| /* 109 */ "tst $\x02, $\x03\0" |
| /* 120 */ "tst $\x02, $\x03$\xFF\x04\x02\0" |
| /* 135 */ "ands $\x01, $\x02, $\x03\0" |
| /* 151 */ "tst $\x02, $\xFF\x03\x05\0" |
| /* 164 */ "movs $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" |
| /* 188 */ "and $\x01, $\x02, $\x03\0" |
| /* 203 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" |
| /* 226 */ "and $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0" |
| /* 247 */ "and $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0" |
| /* 268 */ "and $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0" |
| /* 289 */ "autia1716\0" |
| /* 299 */ "autiasp\0" |
| /* 307 */ "autiaz\0" |
| /* 314 */ "autib1716\0" |
| /* 324 */ "autibsp\0" |
| /* 332 */ "autibz\0" |
| /* 339 */ "bics $\x01, $\x02, $\x03\0" |
| /* 355 */ "bic $\x01, $\x02, $\x03\0" |
| /* 370 */ "clrex\0" |
| /* 376 */ "cntb $\x01\0" |
| /* 384 */ "cntb $\x01, $\xFF\x02\x0E\0" |
| /* 398 */ "cntd $\x01\0" |
| /* 406 */ "cntd $\x01, $\xFF\x02\x0E\0" |
| /* 420 */ "cnth $\x01\0" |
| /* 428 */ "cnth $\x01, $\xFF\x02\x0E\0" |
| /* 442 */ "cntw $\x01\0" |
| /* 450 */ "cntw $\x01, $\xFF\x02\x0E\0" |
| /* 464 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x0F\0" |
| /* 487 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x11\0" |
| /* 510 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x12\0" |
| /* 533 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x13\0" |
| /* 556 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\x04\0" |
| /* 577 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\x04\0" |
| /* 598 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\x04\0" |
| /* 619 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\x04\0" |
| /* 640 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x0F\0" |
| /* 663 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/z, $\xFF\x03\x11\0" |
| /* 686 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/z, $\xFF\x03\x12\0" |
| /* 709 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/z, $\xFF\x03\x13\0" |
| /* 732 */ "cset $\x01, $\xFF\x04\x14\0" |
| /* 746 */ "cinc $\x01, $\x02, $\xFF\x04\x14\0" |
| /* 764 */ "csetm $\x01, $\xFF\x04\x14\0" |
| /* 779 */ "cinv $\x01, $\x02, $\xFF\x04\x14\0" |
| /* 797 */ "cneg $\x01, $\x02, $\xFF\x04\x14\0" |
| /* 815 */ "dcps1\0" |
| /* 821 */ "dcps2\0" |
| /* 827 */ "dcps3\0" |
| /* 833 */ "decb $\x01\0" |
| /* 841 */ "decb $\x01, $\xFF\x03\x0E\0" |
| /* 855 */ "decd $\x01\0" |
| /* 863 */ "decd $\x01, $\xFF\x03\x0E\0" |
| /* 877 */ "decd $\xFF\x01\x10\0" |
| /* 887 */ "decd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| /* 903 */ "dech $\x01\0" |
| /* 911 */ "dech $\x01, $\xFF\x03\x0E\0" |
| /* 925 */ "dech $\xFF\x01\x09\0" |
| /* 935 */ "dech $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| /* 951 */ "decw $\x01\0" |
| /* 959 */ "decw $\x01, $\xFF\x03\x0E\0" |
| /* 973 */ "decw $\xFF\x01\x0B\0" |
| /* 983 */ "decw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| /* 999 */ "ssbb\0" |
| /* 1004 */ "pssbb\0" |
| /* 1010 */ "dfb\0" |
| /* 1014 */ "mov $\xFF\x01\x09, $\xFF\x02\x15\0" |
| /* 1029 */ "mov $\xFF\x01\x0B, $\xFF\x02\x16\0" |
| /* 1044 */ "mov $\xFF\x01\x10, $\xFF\x02\x17\0" |
| /* 1059 */ "dupm $\xFF\x01\x06, $\xFF\x02\x08\0" |
| /* 1075 */ "dupm $\xFF\x01\x09, $\xFF\x02\x0A\0" |
| /* 1091 */ "dupm $\xFF\x01\x0B, $\xFF\x02\x04\0" |
| /* 1107 */ "mov $\xFF\x01\x06, $\xFF\x02\x0F\0" |
| /* 1122 */ "mov $\xFF\x01\x10, $\xFF\x02\x11\0" |
| /* 1137 */ "fmov $\xFF\x01\x10, #0.0\0" |
| /* 1153 */ "mov $\xFF\x01\x09, $\xFF\x02\x12\0" |
| /* 1168 */ "fmov $\xFF\x01\x09, #0.0\0" |
| /* 1184 */ "mov $\xFF\x01\x0B, $\xFF\x02\x13\0" |
| /* 1199 */ "fmov $\xFF\x01\x0B, #0.0\0" |
| /* 1215 */ "mov $\xFF\x01\x06, $\x02\0" |
| /* 1228 */ "mov $\xFF\x01\x10, $\x02\0" |
| /* 1241 */ "mov $\xFF\x01\x09, $\x02\0" |
| /* 1254 */ "mov $\xFF\x01\x0B, $\x02\0" |
| /* 1267 */ "mov $\xFF\x01\x06, $\xFF\x02\x18\0" |
| /* 1282 */ "mov $\xFF\x01\x06, $\xFF\x02\x06$\xFF\x03\x19\0" |
| /* 1301 */ "mov $\xFF\x01\x10, $\xFF\x02\x1A\0" |
| /* 1316 */ "mov $\xFF\x01\x10, $\xFF\x02\x10$\xFF\x03\x19\0" |
| /* 1335 */ "mov $\xFF\x01\x09, $\xFF\x02\x1B\0" |
| /* 1350 */ "mov $\xFF\x01\x09, $\xFF\x02\x09$\xFF\x03\x19\0" |
| /* 1369 */ "mov $\xFF\x01\x1C, $\xFF\x02\x1D\0" |
| /* 1384 */ "mov $\xFF\x01\x1C, $\xFF\x02\x1C$\xFF\x03\x19\0" |
| /* 1403 */ "mov $\xFF\x01\x0B, $\xFF\x02\x1E\0" |
| /* 1418 */ "mov $\xFF\x01\x0B, $\xFF\x02\x0B$\xFF\x03\x19\0" |
| /* 1437 */ "eon $\x01, $\x02, $\x03\0" |
| /* 1452 */ "nots $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" |
| /* 1476 */ "eor $\x01, $\x02, $\x03\0" |
| /* 1491 */ "not $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06\0" |
| /* 1514 */ "eor $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0" |
| /* 1535 */ "eor $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0" |
| /* 1556 */ "eor $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0" |
| /* 1577 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0" |
| /* 1610 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0" |
| /* 1643 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0" |
| /* 1676 */ "mov $\xFF\x01\x1C, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0" |
| /* 1709 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x1F[$\x05, $\xFF\x06\x20]\0" |
| /* 1742 */ "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0" |
| /* 1775 */ "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0" |
| /* 1808 */ "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0" |
| /* 1841 */ "mov $\xFF\x01\x1C, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0" |
| /* 1874 */ "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x21[$\x05, $\xFF\x06\x20]\0" |
| /* 1907 */ "ror $\x01, $\x02, $\x04\0" |
| /* 1922 */ "fmov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x22\0" |
| /* 1946 */ "fmov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x22\0" |
| /* 1970 */ "fmov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x22\0" |
| /* 1994 */ "fmov $\xFF\x01\x10, $\xFF\x02\x22\0" |
| /* 2010 */ "fmov $\xFF\x01\x09, $\xFF\x02\x22\0" |
| /* 2026 */ "fmov $\xFF\x01\x0B, $\xFF\x02\x22\0" |
| /* 2042 */ "ld1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2068 */ "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 2094 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2120 */ "ld1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2146 */ "ld1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 2172 */ "ld1q $\xFF\x01\x25, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2198 */ "ld1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2225 */ "ld1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 2252 */ "ld1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2279 */ "ld1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 2306 */ "ld1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2333 */ "ld1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2359 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 2385 */ "ldff1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2413 */ "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 2441 */ "ldff1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2469 */ "ldff1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2497 */ "ldff1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 2525 */ "ldff1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2554 */ "ldff1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 2583 */ "ldff1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2612 */ "ldff1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 2641 */ "ldff1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2670 */ "ldff1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 2698 */ "ldff1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 2726 */ "nop\0" |
| /* 2730 */ "yield\0" |
| /* 2736 */ "wfe\0" |
| /* 2740 */ "wfi\0" |
| /* 2744 */ "sev\0" |
| /* 2748 */ "sevl\0" |
| /* 2753 */ "dgh\0" |
| /* 2757 */ "esb\0" |
| /* 2761 */ "csdb\0" |
| /* 2766 */ "bti\0" |
| /* 2770 */ "bti $\xFF\x01\x26\0" |
| /* 2779 */ "psb $\xFF\x01\x27\0" |
| /* 2788 */ "clrbhb\0" |
| /* 2795 */ "incb $\x01\0" |
| /* 2803 */ "incb $\x01, $\xFF\x03\x0E\0" |
| /* 2817 */ "incd $\x01\0" |
| /* 2825 */ "incd $\x01, $\xFF\x03\x0E\0" |
| /* 2839 */ "incd $\xFF\x01\x10\0" |
| /* 2849 */ "incd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| /* 2865 */ "inch $\x01\0" |
| /* 2873 */ "inch $\x01, $\xFF\x03\x0E\0" |
| /* 2887 */ "inch $\xFF\x01\x09\0" |
| /* 2897 */ "inch $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| /* 2913 */ "incw $\x01\0" |
| /* 2921 */ "incw $\x01, $\xFF\x03\x0E\0" |
| /* 2935 */ "incw $\xFF\x01\x0B\0" |
| /* 2945 */ "incw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| /* 2961 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x06\0" |
| /* 2994 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x10\0" |
| /* 3027 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x09\0" |
| /* 3060 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x1C\0" |
| /* 3093 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x0B\0" |
| /* 3126 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x06\0" |
| /* 3159 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x10\0" |
| /* 3192 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x09\0" |
| /* 3225 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x1C\0" |
| /* 3258 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x20], $\xFF\x05\x07/m, $\xFF\x06\x0B\0" |
| /* 3291 */ "mov.h $\xFF\x01\x0C$\xFF\x03\x19, $\x04\0" |
| /* 3310 */ "mov.h $\xFF\x01\x0C$\xFF\x03\x19, $\xFF\x04\x0C$\xFF\x05\x19\0" |
| /* 3335 */ "mov.s $\xFF\x01\x0C$\xFF\x03\x19, $\x04\0" |
| /* 3354 */ "mov.s $\xFF\x01\x0C$\xFF\x03\x19, $\xFF\x04\x0C$\xFF\x05\x19\0" |
| /* 3379 */ "mov.d $\xFF\x01\x0C$\xFF\x03\x19, $\x04\0" |
| /* 3398 */ "mov.d $\xFF\x01\x0C$\xFF\x03\x19, $\xFF\x04\x0C$\xFF\x05\x19\0" |
| /* 3423 */ "mov.b $\xFF\x01\x0C$\xFF\x03\x19, $\x04\0" |
| /* 3442 */ "mov.b $\xFF\x01\x0C$\xFF\x03\x19, $\xFF\x04\x0C$\xFF\x05\x19\0" |
| /* 3467 */ "irg $\x01, $\x02\0" |
| /* 3478 */ "isb\0" |
| /* 3482 */ "ld1b $\xFF\x01\x28, $\xFF\x02\x29/z, [$\x03]\0" |
| /* 3506 */ "ld1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3530 */ "ld1b $\xFF\x01\x2A, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3554 */ "ld1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3578 */ "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3602 */ "ld1b $\xFF\x01\x2B, $\xFF\x02\x29/z, [$\x03]\0" |
| /* 3626 */ "ld1b $\xFF\x01\x28, $\xFF\x02\x29/z, [$\x03]\0" |
| /* 3650 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x29/z, [$\x03]\0" |
| /* 3674 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3698 */ "ld1d $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3722 */ "ld1d $\xFF\x01\x23, $\xFF\x02\x29/z, [$\x03]\0" |
| /* 3746 */ "ld1 $\xFF\x02\x2C, [$\x01], #64\0" |
| /* 3766 */ "ld1 $\xFF\x02\x2D, [$\x01], #32\0" |
| /* 3786 */ "ld1 $\xFF\x02\x2E, [$\x01], #64\0" |
| /* 3806 */ "ld1 $\xFF\x02\x2F, [$\x01], #32\0" |
| /* 3826 */ "ld1 $\xFF\x02\x30, [$\x01], #32\0" |
| /* 3846 */ "ld1 $\xFF\x02\x31, [$\x01], #64\0" |
| /* 3866 */ "ld1 $\xFF\x02\x32, [$\x01], #32\0" |
| /* 3886 */ "ld1 $\xFF\x02\x33, [$\x01], #64\0" |
| /* 3906 */ "ld1h $\xFF\x01\x2A, $\xFF\x02\x29/z, [$\x03]\0" |
| /* 3930 */ "ld1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3954 */ "ld1h $\xFF\x01\x2A, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 3978 */ "ld1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4002 */ "ld1h $\xFF\x01\x34, $\xFF\x02\x29/z, [$\x03]\0" |
| /* 4026 */ "ld1h $\xFF\x01\x2A, $\xFF\x02\x29/z, [$\x03]\0" |
| /* 4050 */ "ld1 $\xFF\x02\x2C, [$\x01], #16\0" |
| /* 4070 */ "ld1 $\xFF\x02\x2D, [$\x01], #8\0" |
| /* 4089 */ "ld1 $\xFF\x02\x2E, [$\x01], #16\0" |
| /* 4109 */ "ld1 $\xFF\x02\x2F, [$\x01], #8\0" |
| /* 4128 */ "ld1 $\xFF\x02\x30, [$\x01], #8\0" |
| /* 4147 */ "ld1 $\xFF\x02\x31, [$\x01], #16\0" |
| /* 4167 */ "ld1 $\xFF\x02\x32, [$\x01], #8\0" |
| /* 4186 */ "ld1 $\xFF\x02\x33, [$\x01], #16\0" |
| /* 4206 */ "ld1rb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4231 */ "ld1rb $\xFF\x01\x2A, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4256 */ "ld1rb $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4281 */ "ld1rb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4306 */ "ld1rd $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4331 */ "ld1rh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4356 */ "ld1rh $\xFF\x01\x2A, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4381 */ "ld1rh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4406 */ "ld1rob $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4432 */ "ld1rod $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4458 */ "ld1roh $\xFF\x01\x2A, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4484 */ "ld1row $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4510 */ "ld1rqb $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4536 */ "ld1rqd $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4562 */ "ld1rqh $\xFF\x01\x2A, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4588 */ "ld1rqw $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4614 */ "ld1rsb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4640 */ "ld1rsb $\xFF\x01\x2A, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4666 */ "ld1rsb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4692 */ "ld1rsh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4718 */ "ld1rsh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4744 */ "ld1rsw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4770 */ "ld1rw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4795 */ "ld1rw $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 4820 */ "ld1r $\xFF\x02\x2C, [$\x01], #1\0" |
| /* 4840 */ "ld1r $\xFF\x02\x2D, [$\x01], #8\0" |
| /* 4860 */ "ld1r $\xFF\x02\x2E, [$\x01], #8\0" |
| /* 4880 */ "ld1r $\xFF\x02\x2F, [$\x01], #4\0" |
| /* 4900 */ "ld1r $\xFF\x02\x30, [$\x01], #2\0" |
| /* 4920 */ "ld1r $\xFF\x02\x31, [$\x01], #4\0" |
| /* 4940 */ "ld1r $\xFF\x02\x32, [$\x01], #1\0" |
| /* 4960 */ "ld1r $\xFF\x02\x33, [$\x01], #2\0" |
| /* 4980 */ "ld1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 5005 */ "ld1sb $\xFF\x01\x2A, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 5030 */ "ld1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 5055 */ "ld1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 5080 */ "ld1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 5105 */ "ld1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 5130 */ "ld1 $\xFF\x02\x2C, [$\x01], #48\0" |
| /* 5150 */ "ld1 $\xFF\x02\x2D, [$\x01], #24\0" |
| /* 5170 */ "ld1 $\xFF\x02\x2E, [$\x01], #48\0" |
| /* 5190 */ "ld1 $\xFF\x02\x2F, [$\x01], #24\0" |
| /* 5210 */ "ld1 $\xFF\x02\x30, [$\x01], #24\0" |
| /* 5230 */ "ld1 $\xFF\x02\x31, [$\x01], #48\0" |
| /* 5250 */ "ld1 $\xFF\x02\x32, [$\x01], #24\0" |
| /* 5270 */ "ld1 $\xFF\x02\x33, [$\x01], #48\0" |
| /* 5290 */ "ld1 $\xFF\x02\x2C, [$\x01], #32\0" |
| /* 5310 */ "ld1 $\xFF\x02\x2D, [$\x01], #16\0" |
| /* 5330 */ "ld1 $\xFF\x02\x2E, [$\x01], #32\0" |
| /* 5350 */ "ld1 $\xFF\x02\x2F, [$\x01], #16\0" |
| /* 5370 */ "ld1 $\xFF\x02\x30, [$\x01], #16\0" |
| /* 5390 */ "ld1 $\xFF\x02\x31, [$\x01], #32\0" |
| /* 5410 */ "ld1 $\xFF\x02\x32, [$\x01], #16\0" |
| /* 5430 */ "ld1 $\xFF\x02\x33, [$\x01], #32\0" |
| /* 5450 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x29/z, [$\x03]\0" |
| /* 5474 */ "ld1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 5498 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 5522 */ "ld1w $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 5546 */ "ld1w $\xFF\x01\x24, $\xFF\x02\x29/z, [$\x03]\0" |
| /* 5570 */ "ld1b {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| /* 5606 */ "ld1d {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| /* 5642 */ "ld1h {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| /* 5678 */ "ld1q {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| /* 5714 */ "ld1w {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| /* 5750 */ "ld1b {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| /* 5786 */ "ld1d {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| /* 5822 */ "ld1h {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| /* 5858 */ "ld1q {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| /* 5894 */ "ld1w {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07/z, [$\x05]\0" |
| /* 5930 */ "ld1 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #2\0" |
| /* 5953 */ "ld1 $\xFF\x02\x35$\xFF\x04\x19, [$\x01], #4\0" |
| /* 5976 */ "ld1 $\xFF\x02\x36$\xFF\x04\x19, [$\x01], #8\0" |
| /* 5999 */ "ld1 $\xFF\x02\x2B$\xFF\x04\x19, [$\x01], #1\0" |
| /* 6022 */ "ld2b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6046 */ "ld2d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6070 */ "ld2h $\xFF\x01\x2A, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6094 */ "ld2q $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6118 */ "ld2r $\xFF\x02\x2C, [$\x01], #2\0" |
| /* 6138 */ "ld2r $\xFF\x02\x2D, [$\x01], #16\0" |
| /* 6159 */ "ld2r $\xFF\x02\x2E, [$\x01], #16\0" |
| /* 6180 */ "ld2r $\xFF\x02\x2F, [$\x01], #8\0" |
| /* 6200 */ "ld2r $\xFF\x02\x30, [$\x01], #4\0" |
| /* 6220 */ "ld2r $\xFF\x02\x31, [$\x01], #8\0" |
| /* 6240 */ "ld2r $\xFF\x02\x32, [$\x01], #2\0" |
| /* 6260 */ "ld2r $\xFF\x02\x33, [$\x01], #4\0" |
| /* 6280 */ "ld2 $\xFF\x02\x2C, [$\x01], #32\0" |
| /* 6300 */ "ld2 $\xFF\x02\x2E, [$\x01], #32\0" |
| /* 6320 */ "ld2 $\xFF\x02\x2F, [$\x01], #16\0" |
| /* 6340 */ "ld2 $\xFF\x02\x30, [$\x01], #16\0" |
| /* 6360 */ "ld2 $\xFF\x02\x31, [$\x01], #32\0" |
| /* 6380 */ "ld2 $\xFF\x02\x32, [$\x01], #16\0" |
| /* 6400 */ "ld2 $\xFF\x02\x33, [$\x01], #32\0" |
| /* 6420 */ "ld2w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6444 */ "ld2 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #4\0" |
| /* 6467 */ "ld2 $\xFF\x02\x35$\xFF\x04\x19, [$\x01], #8\0" |
| /* 6490 */ "ld2 $\xFF\x02\x36$\xFF\x04\x19, [$\x01], #16\0" |
| /* 6514 */ "ld2 $\xFF\x02\x2B$\xFF\x04\x19, [$\x01], #2\0" |
| /* 6537 */ "ld3b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6561 */ "ld3d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6585 */ "ld3h $\xFF\x01\x2A, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6609 */ "ld3q $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6633 */ "ld3r $\xFF\x02\x2C, [$\x01], #3\0" |
| /* 6653 */ "ld3r $\xFF\x02\x2D, [$\x01], #24\0" |
| /* 6674 */ "ld3r $\xFF\x02\x2E, [$\x01], #24\0" |
| /* 6695 */ "ld3r $\xFF\x02\x2F, [$\x01], #12\0" |
| /* 6716 */ "ld3r $\xFF\x02\x30, [$\x01], #6\0" |
| /* 6736 */ "ld3r $\xFF\x02\x31, [$\x01], #12\0" |
| /* 6757 */ "ld3r $\xFF\x02\x32, [$\x01], #3\0" |
| /* 6777 */ "ld3r $\xFF\x02\x33, [$\x01], #6\0" |
| /* 6797 */ "ld3 $\xFF\x02\x2C, [$\x01], #48\0" |
| /* 6817 */ "ld3 $\xFF\x02\x2E, [$\x01], #48\0" |
| /* 6837 */ "ld3 $\xFF\x02\x2F, [$\x01], #24\0" |
| /* 6857 */ "ld3 $\xFF\x02\x30, [$\x01], #24\0" |
| /* 6877 */ "ld3 $\xFF\x02\x31, [$\x01], #48\0" |
| /* 6897 */ "ld3 $\xFF\x02\x32, [$\x01], #24\0" |
| /* 6917 */ "ld3 $\xFF\x02\x33, [$\x01], #48\0" |
| /* 6937 */ "ld3w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 6961 */ "ld3 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #6\0" |
| /* 6984 */ "ld3 $\xFF\x02\x35$\xFF\x04\x19, [$\x01], #12\0" |
| /* 7008 */ "ld3 $\xFF\x02\x36$\xFF\x04\x19, [$\x01], #24\0" |
| /* 7032 */ "ld3 $\xFF\x02\x2B$\xFF\x04\x19, [$\x01], #3\0" |
| /* 7055 */ "ld4b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7079 */ "ld4d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7103 */ "ld4 $\xFF\x02\x2C, [$\x01], #64\0" |
| /* 7123 */ "ld4 $\xFF\x02\x2E, [$\x01], #64\0" |
| /* 7143 */ "ld4 $\xFF\x02\x2F, [$\x01], #32\0" |
| /* 7163 */ "ld4 $\xFF\x02\x30, [$\x01], #32\0" |
| /* 7183 */ "ld4 $\xFF\x02\x31, [$\x01], #64\0" |
| /* 7203 */ "ld4 $\xFF\x02\x32, [$\x01], #32\0" |
| /* 7223 */ "ld4 $\xFF\x02\x33, [$\x01], #64\0" |
| /* 7243 */ "ld4h $\xFF\x01\x2A, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7267 */ "ld4q $\xFF\x01\x25, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7291 */ "ld4r $\xFF\x02\x2C, [$\x01], #4\0" |
| /* 7311 */ "ld4r $\xFF\x02\x2D, [$\x01], #32\0" |
| /* 7332 */ "ld4r $\xFF\x02\x2E, [$\x01], #32\0" |
| /* 7353 */ "ld4r $\xFF\x02\x2F, [$\x01], #16\0" |
| /* 7374 */ "ld4r $\xFF\x02\x30, [$\x01], #8\0" |
| /* 7394 */ "ld4r $\xFF\x02\x31, [$\x01], #16\0" |
| /* 7415 */ "ld4r $\xFF\x02\x32, [$\x01], #4\0" |
| /* 7435 */ "ld4r $\xFF\x02\x33, [$\x01], #8\0" |
| /* 7455 */ "ld4w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7479 */ "ld4 $\xFF\x02\x34$\xFF\x04\x19, [$\x01], #8\0" |
| /* 7502 */ "ld4 $\xFF\x02\x35$\xFF\x04\x19, [$\x01], #16\0" |
| /* 7526 */ "ld4 $\xFF\x02\x36$\xFF\x04\x19, [$\x01], #32\0" |
| /* 7550 */ "ld4 $\xFF\x02\x2B$\xFF\x04\x19, [$\x01], #4\0" |
| /* 7573 */ "staddb $\x02, [$\x03]\0" |
| /* 7589 */ "staddh $\x02, [$\x03]\0" |
| /* 7605 */ "staddlb $\x02, [$\x03]\0" |
| /* 7622 */ "staddlh $\x02, [$\x03]\0" |
| /* 7639 */ "staddl $\x02, [$\x03]\0" |
| /* 7655 */ "stadd $\x02, [$\x03]\0" |
| /* 7670 */ "ldapurb $\x01, [$\x02]\0" |
| /* 7687 */ "ldapurh $\x01, [$\x02]\0" |
| /* 7704 */ "ldapursb $\x01, [$\x02]\0" |
| /* 7722 */ "ldapursh $\x01, [$\x02]\0" |
| /* 7740 */ "ldapursw $\x01, [$\x02]\0" |
| /* 7758 */ "ldapur $\x01, [$\x02]\0" |
| /* 7774 */ "stclrb $\x02, [$\x03]\0" |
| /* 7790 */ "stclrh $\x02, [$\x03]\0" |
| /* 7806 */ "stclrlb $\x02, [$\x03]\0" |
| /* 7823 */ "stclrlh $\x02, [$\x03]\0" |
| /* 7840 */ "stclrl $\x02, [$\x03]\0" |
| /* 7856 */ "stclr $\x02, [$\x03]\0" |
| /* 7871 */ "steorb $\x02, [$\x03]\0" |
| /* 7887 */ "steorh $\x02, [$\x03]\0" |
| /* 7903 */ "steorlb $\x02, [$\x03]\0" |
| /* 7920 */ "steorlh $\x02, [$\x03]\0" |
| /* 7937 */ "steorl $\x02, [$\x03]\0" |
| /* 7953 */ "steor $\x02, [$\x03]\0" |
| /* 7968 */ "ldff1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 7994 */ "ldff1b $\xFF\x01\x2A, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8020 */ "ldff1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8046 */ "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8072 */ "ldff1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8098 */ "ldff1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8124 */ "ldff1h $\xFF\x01\x2A, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8150 */ "ldff1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8176 */ "ldff1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8203 */ "ldff1sb $\xFF\x01\x2A, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8230 */ "ldff1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8257 */ "ldff1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8284 */ "ldff1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8311 */ "ldff1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8338 */ "ldff1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8364 */ "ldff1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8390 */ "ldg $\x01, [$\x03]\0" |
| /* 8403 */ "ldnf1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8429 */ "ldnf1b $\xFF\x01\x2A, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8455 */ "ldnf1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8481 */ "ldnf1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8507 */ "ldnf1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8533 */ "ldnf1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8559 */ "ldnf1h $\xFF\x01\x2A, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8585 */ "ldnf1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8611 */ "ldnf1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8638 */ "ldnf1sb $\xFF\x01\x2A, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8665 */ "ldnf1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8692 */ "ldnf1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8719 */ "ldnf1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8746 */ "ldnf1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8773 */ "ldnf1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8799 */ "ldnf1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8825 */ "ldnp $\x01, $\x02, [$\x03]\0" |
| /* 8843 */ "ldnt1b $\xFF\x01\x28, $\xFF\x02\x29/z, [$\x03]\0" |
| /* 8869 */ "ldnt1b $\xFF\x01\x2B, $\xFF\x02\x29/z, [$\x03]\0" |
| /* 8895 */ "ldnt1b $\xFF\x01\x28, $\xFF\x02\x29/z, [$\x03]\0" |
| /* 8921 */ "ldnt1b $\xFF\x01\x28, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 8947 */ "ldnt1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 8975 */ "ldnt1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 9003 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x29/z, [$\x03]\0" |
| /* 9029 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x29/z, [$\x03]\0" |
| /* 9055 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 9081 */ "ldnt1d $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 9109 */ "ldnt1h $\xFF\x01\x2A, $\xFF\x02\x29/z, [$\x03]\0" |
| /* 9135 */ "ldnt1h $\xFF\x01\x34, $\xFF\x02\x29/z, [$\x03]\0" |
| /* 9161 */ "ldnt1h $\xFF\x01\x2A, $\xFF\x02\x29/z, [$\x03]\0" |
| /* 9187 */ "ldnt1h $\xFF\x01\x2A, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 9213 */ "ldnt1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 9241 */ "ldnt1h $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 9269 */ "ldnt1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 9298 */ "ldnt1sb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 9327 */ "ldnt1sh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 9356 */ "ldnt1sh $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 9385 */ "ldnt1sw $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 9414 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x29/z, [$\x03]\0" |
| /* 9440 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x29/z, [$\x03]\0" |
| /* 9466 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]\0" |
| /* 9492 */ "ldnt1w $\xFF\x01\x23, $\xFF\x02\x07/z, [$\xFF\x03\x10]\0" |
| /* 9520 */ "ldnt1w $\xFF\x01\x24, $\xFF\x02\x07/z, [$\xFF\x03\x0B]\0" |
| /* 9548 */ "ldp $\x01, $\x02, [$\x03]\0" |
| /* 9565 */ "ldpsw $\x01, $\x02, [$\x03]\0" |
| /* 9584 */ "ldraa $\x01, [$\x02]\0" |
| /* 9599 */ "ldrab $\x01, [$\x02]\0" |
| /* 9614 */ "ldrb $\x01, [$\x02, $\x03]\0" |
| /* 9632 */ "ldrb $\x01, [$\x02]\0" |
| /* 9646 */ "ldr $\x01, [$\x02, $\x03]\0" |
| /* 9663 */ "ldr $\x01, [$\x02]\0" |
| /* 9676 */ "ldrh $\x01, [$\x02, $\x03]\0" |
| /* 9694 */ "ldrh $\x01, [$\x02]\0" |
| /* 9708 */ "ldrsb $\x01, [$\x02, $\x03]\0" |
| /* 9727 */ "ldrsb $\x01, [$\x02]\0" |
| /* 9742 */ "ldrsh $\x01, [$\x02, $\x03]\0" |
| /* 9761 */ "ldrsh $\x01, [$\x02]\0" |
| /* 9776 */ "ldrsw $\x01, [$\x02, $\x03]\0" |
| /* 9795 */ "ldrsw $\x01, [$\x02]\0" |
| /* 9810 */ "ldr $\xFF\x01\x07, [$\x02]\0" |
| /* 9825 */ "ldr $\xFF\x01\x37[$\x02, $\xFF\x03\x20], [$\x04]\0" |
| /* 9850 */ "stsetb $\x02, [$\x03]\0" |
| /* 9866 */ "stseth $\x02, [$\x03]\0" |
| /* 9882 */ "stsetlb $\x02, [$\x03]\0" |
| /* 9899 */ "stsetlh $\x02, [$\x03]\0" |
| /* 9916 */ "stsetl $\x02, [$\x03]\0" |
| /* 9932 */ "stset $\x02, [$\x03]\0" |
| /* 9947 */ "stsmaxb $\x02, [$\x03]\0" |
| /* 9964 */ "stsmaxh $\x02, [$\x03]\0" |
| /* 9981 */ "stsmaxlb $\x02, [$\x03]\0" |
| /* 9999 */ "stsmaxlh $\x02, [$\x03]\0" |
| /* 10017 */ "stsmaxl $\x02, [$\x03]\0" |
| /* 10034 */ "stsmax $\x02, [$\x03]\0" |
| /* 10050 */ "stsminb $\x02, [$\x03]\0" |
| /* 10067 */ "stsminh $\x02, [$\x03]\0" |
| /* 10084 */ "stsminlb $\x02, [$\x03]\0" |
| /* 10102 */ "stsminlh $\x02, [$\x03]\0" |
| /* 10120 */ "stsminl $\x02, [$\x03]\0" |
| /* 10137 */ "stsmin $\x02, [$\x03]\0" |
| /* 10153 */ "ldtrb $\x01, [$\x02]\0" |
| /* 10168 */ "ldtrh $\x01, [$\x02]\0" |
| /* 10183 */ "ldtrsb $\x01, [$\x02]\0" |
| /* 10199 */ "ldtrsh $\x01, [$\x02]\0" |
| /* 10215 */ "ldtrsw $\x01, [$\x02]\0" |
| /* 10231 */ "ldtr $\x01, [$\x02]\0" |
| /* 10245 */ "stumaxb $\x02, [$\x03]\0" |
| /* 10262 */ "stumaxh $\x02, [$\x03]\0" |
| /* 10279 */ "stumaxlb $\x02, [$\x03]\0" |
| /* 10297 */ "stumaxlh $\x02, [$\x03]\0" |
| /* 10315 */ "stumaxl $\x02, [$\x03]\0" |
| /* 10332 */ "stumax $\x02, [$\x03]\0" |
| /* 10348 */ "stuminb $\x02, [$\x03]\0" |
| /* 10365 */ "stuminh $\x02, [$\x03]\0" |
| /* 10382 */ "stuminlb $\x02, [$\x03]\0" |
| /* 10400 */ "stuminlh $\x02, [$\x03]\0" |
| /* 10418 */ "stuminl $\x02, [$\x03]\0" |
| /* 10435 */ "stumin $\x02, [$\x03]\0" |
| /* 10451 */ "ldurb $\x01, [$\x02]\0" |
| /* 10466 */ "ldur $\x01, [$\x02]\0" |
| /* 10480 */ "ldurh $\x01, [$\x02]\0" |
| /* 10495 */ "ldursb $\x01, [$\x02]\0" |
| /* 10511 */ "ldursh $\x01, [$\x02]\0" |
| /* 10527 */ "ldursw $\x01, [$\x02]\0" |
| /* 10543 */ "mul $\x01, $\x02, $\x03\0" |
| /* 10558 */ "mov $\xFF\x01\x28, $\xFF\x02\x1F[$\x03, $\xFF\x04\x38]\0" |
| /* 10583 */ "mov $\xFF\x01\x23, $\xFF\x02\x1F[$\x03, $\xFF\x04\x38]\0" |
| /* 10608 */ "mov $\xFF\x01\x2A, $\xFF\x02\x1F[$\x03, $\xFF\x04\x38]\0" |
| /* 10633 */ "mov $\xFF\x01\x24, $\xFF\x02\x1F[$\x03, $\xFF\x04\x38]\0" |
| /* 10658 */ "mov $\xFF\x01\x28, $\xFF\x02\x21[$\x03, $\xFF\x04\x38]\0" |
| /* 10683 */ "mov $\xFF\x01\x23, $\xFF\x02\x21[$\x03, $\xFF\x04\x38]\0" |
| /* 10708 */ "mov $\xFF\x01\x2A, $\xFF\x02\x21[$\x03, $\xFF\x04\x38]\0" |
| /* 10733 */ "mov $\xFF\x01\x24, $\xFF\x02\x21[$\x03, $\xFF\x04\x38]\0" |
| /* 10758 */ "mov $\xFF\x01\x28, $\xFF\x02\x1F[$\x03, $\xFF\x04\x39]\0" |
| /* 10783 */ "mov $\xFF\x01\x23, $\xFF\x02\x1F[$\x03, $\xFF\x04\x39]\0" |
| /* 10808 */ "mov $\xFF\x01\x2A, $\xFF\x02\x1F[$\x03, $\xFF\x04\x39]\0" |
| /* 10833 */ "mov $\xFF\x01\x24, $\xFF\x02\x1F[$\x03, $\xFF\x04\x39]\0" |
| /* 10858 */ "mov $\xFF\x01\x28, $\xFF\x02\x21[$\x03, $\xFF\x04\x39]\0" |
| /* 10883 */ "mov $\xFF\x01\x23, $\xFF\x02\x21[$\x03, $\xFF\x04\x39]\0" |
| /* 10908 */ "mov $\xFF\x01\x2A, $\xFF\x02\x21[$\x03, $\xFF\x04\x39]\0" |
| /* 10933 */ "mov $\xFF\x01\x24, $\xFF\x02\x21[$\x03, $\xFF\x04\x39]\0" |
| /* 10958 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x38], $\xFF\x05\x28\0" |
| /* 10983 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x38], $\xFF\x05\x23\0" |
| /* 11008 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x38], $\xFF\x05\x2A\0" |
| /* 11033 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x38], $\xFF\x05\x24\0" |
| /* 11058 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x38], $\xFF\x05\x28\0" |
| /* 11083 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x38], $\xFF\x05\x23\0" |
| /* 11108 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x38], $\xFF\x05\x2A\0" |
| /* 11133 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x38], $\xFF\x05\x24\0" |
| /* 11158 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x39], $\xFF\x05\x28\0" |
| /* 11183 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x39], $\xFF\x05\x23\0" |
| /* 11208 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x39], $\xFF\x05\x2A\0" |
| /* 11233 */ "mov $\xFF\x01\x1F[$\x03, $\xFF\x04\x39], $\xFF\x05\x24\0" |
| /* 11258 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x39], $\xFF\x05\x28\0" |
| /* 11283 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x39], $\xFF\x05\x23\0" |
| /* 11308 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x39], $\xFF\x05\x2A\0" |
| /* 11333 */ "mov $\xFF\x01\x21[$\x03, $\xFF\x04\x39], $\xFF\x05\x24\0" |
| /* 11358 */ "mov $\xFF\x01\x23, $\xFF\x02\x3A[$\x03, $\xFF\x04\x20, vgx2]\0" |
| /* 11389 */ "mov $\xFF\x01\x3A[$\x03, $\xFF\x04\x20, vgx2], $\xFF\x05\x23\0" |
| /* 11420 */ "mov $\xFF\x01\x23, $\xFF\x02\x3A[$\x03, $\xFF\x04\x20, vgx4]\0" |
| /* 11451 */ "mov $\xFF\x01\x3A[$\x03, $\xFF\x04\x20, vgx4], $\xFF\x05\x23\0" |
| /* 11482 */ "smstart\0" |
| /* 11490 */ "smstart sm\0" |
| /* 11501 */ "smstart za\0" |
| /* 11512 */ "smstop\0" |
| /* 11519 */ "smstop sm\0" |
| /* 11529 */ "smstop za\0" |
| /* 11539 */ "mneg $\x01, $\x02, $\x03\0" |
| /* 11555 */ "mvn.16b $\xFF\x01\x0C, $\xFF\x02\x0C\0" |
| /* 11574 */ "mvn.8b $\xFF\x01\x0C, $\xFF\x02\x0C\0" |
| /* 11592 */ "mvn $\x01, $\x03\0" |
| /* 11603 */ "mvn $\x01, $\x03$\xFF\x04\x02\0" |
| /* 11618 */ "orn $\x01, $\x02, $\x03\0" |
| /* 11633 */ "movs $\xFF\x01\x06, $\xFF\x02\x06\0" |
| /* 11649 */ "mov $\x01, $\x03\0" |
| /* 11660 */ "orr $\x01, $\x02, $\x03\0" |
| /* 11675 */ "mov $\xFF\x01\x06, $\xFF\x02\x06\0" |
| /* 11690 */ "orr $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08\0" |
| /* 11711 */ "orr $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A\0" |
| /* 11732 */ "orr $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04\0" |
| /* 11753 */ "mov $\xFF\x01\x10, $\xFF\x02\x10\0" |
| /* 11768 */ "mov.16b $\xFF\x01\x0C, $\xFF\x02\x0C\0" |
| /* 11787 */ "mov.8b $\xFF\x01\x0C, $\xFF\x02\x0C\0" |
| /* 11805 */ "pacia1716\0" |
| /* 11815 */ "paciasp\0" |
| /* 11823 */ "paciaz\0" |
| /* 11830 */ "pacib1716\0" |
| /* 11840 */ "pacibsp\0" |
| /* 11848 */ "pacibz\0" |
| /* 11855 */ "pmov $\xFF\x01\x06, $\xFF\x02\x07\0" |
| /* 11871 */ "pmov $\xFF\x01\x07, $\xFF\x04\x06\0" |
| /* 11887 */ "prfb $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 11911 */ "prfb $\xFF\x01\x3C, $\xFF\x02\x07, [$\x03]\0" |
| /* 11933 */ "prfb $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| /* 11957 */ "prfd $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 11981 */ "prfd $\xFF\x01\x3C, $\xFF\x02\x07, [$\x03]\0" |
| /* 12003 */ "prfd $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| /* 12027 */ "prfh $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 12051 */ "prfh $\xFF\x01\x3C, $\xFF\x02\x07, [$\x03]\0" |
| /* 12073 */ "prfh $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| /* 12097 */ "prfm $\xFF\x01\x3D, [$\x02, $\x03]\0" |
| /* 12117 */ "prfm $\xFF\x01\x3D, [$\x02]\0" |
| /* 12133 */ "prfum $\xFF\x01\x3D, [$\x02]\0" |
| /* 12150 */ "prfw $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 12174 */ "prfw $\xFF\x01\x3C, $\xFF\x02\x07, [$\x03]\0" |
| /* 12196 */ "prfw $\xFF\x01\x3C, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| /* 12220 */ "ptrues $\xFF\x01\x06\0" |
| /* 12232 */ "ptrues $\xFF\x01\x10\0" |
| /* 12244 */ "ptrues $\xFF\x01\x09\0" |
| /* 12256 */ "ptrues $\xFF\x01\x0B\0" |
| /* 12268 */ "ptrue $\xFF\x01\x06\0" |
| /* 12279 */ "ptrue $\xFF\x01\x10\0" |
| /* 12290 */ "ptrue $\xFF\x01\x09\0" |
| /* 12301 */ "ptrue $\xFF\x01\x0B\0" |
| /* 12312 */ "ret\0" |
| /* 12316 */ "ngcs $\x01, $\x03\0" |
| /* 12328 */ "ngc $\x01, $\x03\0" |
| /* 12339 */ "asr $\x01, $\x02, $\x03\0" |
| /* 12354 */ "sxtb $\x01, $\x02\0" |
| /* 12366 */ "sxth $\x01, $\x02\0" |
| /* 12378 */ "sxtw $\x01, $\x02\0" |
| /* 12390 */ "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x06\0" |
| /* 12413 */ "mov $\xFF\x01\x10, $\xFF\x02\x07/m, $\xFF\x03\x10\0" |
| /* 12436 */ "mov $\xFF\x01\x09, $\xFF\x02\x07/m, $\xFF\x03\x09\0" |
| /* 12459 */ "mov $\xFF\x01\x0B, $\xFF\x02\x07/m, $\xFF\x03\x0B\0" |
| /* 12482 */ "smull $\x01, $\x02, $\x03\0" |
| /* 12499 */ "smnegl $\x01, $\x02, $\x03\0" |
| /* 12517 */ "sqdecb $\x01\0" |
| /* 12527 */ "sqdecb $\x01, $\xFF\x03\x0E\0" |
| /* 12543 */ "sqdecb $\x01, $\xFF\x02\x3E\0" |
| /* 12559 */ "sqdecb $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| /* 12581 */ "sqdecd $\x01\0" |
| /* 12591 */ "sqdecd $\x01, $\xFF\x03\x0E\0" |
| /* 12607 */ "sqdecd $\x01, $\xFF\x02\x3E\0" |
| /* 12623 */ "sqdecd $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| /* 12645 */ "sqdecd $\xFF\x01\x10\0" |
| /* 12657 */ "sqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| /* 12675 */ "sqdech $\x01\0" |
| /* 12685 */ "sqdech $\x01, $\xFF\x03\x0E\0" |
| /* 12701 */ "sqdech $\x01, $\xFF\x02\x3E\0" |
| /* 12717 */ "sqdech $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| /* 12739 */ "sqdech $\xFF\x01\x09\0" |
| /* 12751 */ "sqdech $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| /* 12769 */ "sqdecw $\x01\0" |
| /* 12779 */ "sqdecw $\x01, $\xFF\x03\x0E\0" |
| /* 12795 */ "sqdecw $\x01, $\xFF\x02\x3E\0" |
| /* 12811 */ "sqdecw $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| /* 12833 */ "sqdecw $\xFF\x01\x0B\0" |
| /* 12845 */ "sqdecw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| /* 12863 */ "sqincb $\x01\0" |
| /* 12873 */ "sqincb $\x01, $\xFF\x03\x0E\0" |
| /* 12889 */ "sqincb $\x01, $\xFF\x02\x3E\0" |
| /* 12905 */ "sqincb $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| /* 12927 */ "sqincd $\x01\0" |
| /* 12937 */ "sqincd $\x01, $\xFF\x03\x0E\0" |
| /* 12953 */ "sqincd $\x01, $\xFF\x02\x3E\0" |
| /* 12969 */ "sqincd $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| /* 12991 */ "sqincd $\xFF\x01\x10\0" |
| /* 13003 */ "sqincd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| /* 13021 */ "sqinch $\x01\0" |
| /* 13031 */ "sqinch $\x01, $\xFF\x03\x0E\0" |
| /* 13047 */ "sqinch $\x01, $\xFF\x02\x3E\0" |
| /* 13063 */ "sqinch $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| /* 13085 */ "sqinch $\xFF\x01\x09\0" |
| /* 13097 */ "sqinch $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| /* 13115 */ "sqincw $\x01\0" |
| /* 13125 */ "sqincw $\x01, $\xFF\x03\x0E\0" |
| /* 13141 */ "sqincw $\x01, $\xFF\x02\x3E\0" |
| /* 13157 */ "sqincw $\x01, $\xFF\x02\x3E, $\xFF\x03\x0E\0" |
| /* 13179 */ "sqincw $\xFF\x01\x0B\0" |
| /* 13191 */ "sqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| /* 13209 */ "st1b $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 13233 */ "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| /* 13257 */ "st1d $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 13281 */ "st1h $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 13305 */ "st1h $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| /* 13329 */ "st1q $\xFF\x01\x25, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 13353 */ "st1w $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 13377 */ "st1w $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| /* 13401 */ "st1b $\xFF\x01\x28, $\xFF\x02\x29, [$\x03]\0" |
| /* 13423 */ "st1b $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| /* 13445 */ "st1b $\xFF\x01\x2A, $\xFF\x02\x07, [$\x03]\0" |
| /* 13467 */ "st1b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0" |
| /* 13489 */ "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| /* 13511 */ "st1b $\xFF\x01\x2B, $\xFF\x02\x29, [$\x03]\0" |
| /* 13533 */ "st1b $\xFF\x01\x28, $\xFF\x02\x29, [$\x03]\0" |
| /* 13555 */ "st1d $\xFF\x01\x23, $\xFF\x02\x29, [$\x03]\0" |
| /* 13577 */ "st1d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| /* 13599 */ "st1d $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| /* 13621 */ "st1d $\xFF\x01\x23, $\xFF\x02\x29, [$\x03]\0" |
| /* 13643 */ "st1 $\xFF\x02\x2C, [$\x01], #64\0" |
| /* 13663 */ "st1 $\xFF\x02\x2D, [$\x01], #32\0" |
| /* 13683 */ "st1 $\xFF\x02\x2E, [$\x01], #64\0" |
| /* 13703 */ "st1 $\xFF\x02\x2F, [$\x01], #32\0" |
| /* 13723 */ "st1 $\xFF\x02\x30, [$\x01], #32\0" |
| /* 13743 */ "st1 $\xFF\x02\x31, [$\x01], #64\0" |
| /* 13763 */ "st1 $\xFF\x02\x32, [$\x01], #32\0" |
| /* 13783 */ "st1 $\xFF\x02\x33, [$\x01], #64\0" |
| /* 13803 */ "st1h $\xFF\x01\x2A, $\xFF\x02\x29, [$\x03]\0" |
| /* 13825 */ "st1h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| /* 13847 */ "st1h $\xFF\x01\x2A, $\xFF\x02\x07, [$\x03]\0" |
| /* 13869 */ "st1h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| /* 13891 */ "st1h $\xFF\x01\x34, $\xFF\x02\x29, [$\x03]\0" |
| /* 13913 */ "st1h $\xFF\x01\x2A, $\xFF\x02\x29, [$\x03]\0" |
| /* 13935 */ "st1 $\xFF\x02\x2C, [$\x01], #16\0" |
| /* 13955 */ "st1 $\xFF\x02\x2D, [$\x01], #8\0" |
| /* 13974 */ "st1 $\xFF\x02\x2E, [$\x01], #16\0" |
| /* 13994 */ "st1 $\xFF\x02\x2F, [$\x01], #8\0" |
| /* 14013 */ "st1 $\xFF\x02\x30, [$\x01], #8\0" |
| /* 14032 */ "st1 $\xFF\x02\x31, [$\x01], #16\0" |
| /* 14052 */ "st1 $\xFF\x02\x32, [$\x01], #8\0" |
| /* 14071 */ "st1 $\xFF\x02\x33, [$\x01], #16\0" |
| /* 14091 */ "st1 $\xFF\x02\x2C, [$\x01], #48\0" |
| /* 14111 */ "st1 $\xFF\x02\x2D, [$\x01], #24\0" |
| /* 14131 */ "st1 $\xFF\x02\x2E, [$\x01], #48\0" |
| /* 14151 */ "st1 $\xFF\x02\x2F, [$\x01], #24\0" |
| /* 14171 */ "st1 $\xFF\x02\x30, [$\x01], #24\0" |
| /* 14191 */ "st1 $\xFF\x02\x31, [$\x01], #48\0" |
| /* 14211 */ "st1 $\xFF\x02\x32, [$\x01], #24\0" |
| /* 14231 */ "st1 $\xFF\x02\x33, [$\x01], #48\0" |
| /* 14251 */ "st1 $\xFF\x02\x2C, [$\x01], #32\0" |
| /* 14271 */ "st1 $\xFF\x02\x2D, [$\x01], #16\0" |
| /* 14291 */ "st1 $\xFF\x02\x2E, [$\x01], #32\0" |
| /* 14311 */ "st1 $\xFF\x02\x2F, [$\x01], #16\0" |
| /* 14331 */ "st1 $\xFF\x02\x30, [$\x01], #16\0" |
| /* 14351 */ "st1 $\xFF\x02\x31, [$\x01], #32\0" |
| /* 14371 */ "st1 $\xFF\x02\x32, [$\x01], #16\0" |
| /* 14391 */ "st1 $\xFF\x02\x33, [$\x01], #32\0" |
| /* 14411 */ "st1w $\xFF\x01\x24, $\xFF\x02\x29, [$\x03]\0" |
| /* 14433 */ "st1w $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| /* 14455 */ "st1w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| /* 14477 */ "st1w $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| /* 14499 */ "st1w $\xFF\x01\x24, $\xFF\x02\x29, [$\x03]\0" |
| /* 14521 */ "st1b {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| /* 14555 */ "st1d {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| /* 14589 */ "st1h {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| /* 14623 */ "st1q {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| /* 14657 */ "st1w {$\xFF\x01\x1F[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| /* 14691 */ "st1b {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| /* 14725 */ "st1d {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| /* 14759 */ "st1h {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| /* 14793 */ "st1q {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| /* 14827 */ "st1w {$\xFF\x01\x21[$\x02, $\xFF\x03\x20]}, $\xFF\x04\x07, [$\x05]\0" |
| /* 14861 */ "st1 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #2\0" |
| /* 14884 */ "st1 $\xFF\x02\x35$\xFF\x03\x19, [$\x01], #4\0" |
| /* 14907 */ "st1 $\xFF\x02\x36$\xFF\x03\x19, [$\x01], #8\0" |
| /* 14930 */ "st1 $\xFF\x02\x2B$\xFF\x03\x19, [$\x01], #1\0" |
| /* 14953 */ "st2b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0" |
| /* 14975 */ "st2d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| /* 14997 */ "st2g $\x01, [$\x02]\0" |
| /* 15011 */ "st2h $\xFF\x01\x2A, $\xFF\x02\x07, [$\x03]\0" |
| /* 15033 */ "st2q $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| /* 15055 */ "st2 $\xFF\x02\x2C, [$\x01], #32\0" |
| /* 15075 */ "st2 $\xFF\x02\x2E, [$\x01], #32\0" |
| /* 15095 */ "st2 $\xFF\x02\x2F, [$\x01], #16\0" |
| /* 15115 */ "st2 $\xFF\x02\x30, [$\x01], #16\0" |
| /* 15135 */ "st2 $\xFF\x02\x31, [$\x01], #32\0" |
| /* 15155 */ "st2 $\xFF\x02\x32, [$\x01], #16\0" |
| /* 15175 */ "st2 $\xFF\x02\x33, [$\x01], #32\0" |
| /* 15195 */ "st2w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| /* 15217 */ "st2 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #4\0" |
| /* 15240 */ "st2 $\xFF\x02\x35$\xFF\x03\x19, [$\x01], #8\0" |
| /* 15263 */ "st2 $\xFF\x02\x36$\xFF\x03\x19, [$\x01], #16\0" |
| /* 15287 */ "st2 $\xFF\x02\x2B$\xFF\x03\x19, [$\x01], #2\0" |
| /* 15310 */ "st3b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0" |
| /* 15332 */ "st3d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| /* 15354 */ "st3h $\xFF\x01\x2A, $\xFF\x02\x07, [$\x03]\0" |
| /* 15376 */ "st3q $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| /* 15398 */ "st3 $\xFF\x02\x2C, [$\x01], #48\0" |
| /* 15418 */ "st3 $\xFF\x02\x2E, [$\x01], #48\0" |
| /* 15438 */ "st3 $\xFF\x02\x2F, [$\x01], #24\0" |
| /* 15458 */ "st3 $\xFF\x02\x30, [$\x01], #24\0" |
| /* 15478 */ "st3 $\xFF\x02\x31, [$\x01], #48\0" |
| /* 15498 */ "st3 $\xFF\x02\x32, [$\x01], #24\0" |
| /* 15518 */ "st3 $\xFF\x02\x33, [$\x01], #48\0" |
| /* 15538 */ "st3w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| /* 15560 */ "st3 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #6\0" |
| /* 15583 */ "st3 $\xFF\x02\x35$\xFF\x03\x19, [$\x01], #12\0" |
| /* 15607 */ "st3 $\xFF\x02\x36$\xFF\x03\x19, [$\x01], #24\0" |
| /* 15631 */ "st3 $\xFF\x02\x2B$\xFF\x03\x19, [$\x01], #3\0" |
| /* 15654 */ "st4b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0" |
| /* 15676 */ "st4d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| /* 15698 */ "st4 $\xFF\x02\x2C, [$\x01], #64\0" |
| /* 15718 */ "st4 $\xFF\x02\x2E, [$\x01], #64\0" |
| /* 15738 */ "st4 $\xFF\x02\x2F, [$\x01], #32\0" |
| /* 15758 */ "st4 $\xFF\x02\x30, [$\x01], #32\0" |
| /* 15778 */ "st4 $\xFF\x02\x31, [$\x01], #64\0" |
| /* 15798 */ "st4 $\xFF\x02\x32, [$\x01], #32\0" |
| /* 15818 */ "st4 $\xFF\x02\x33, [$\x01], #64\0" |
| /* 15838 */ "st4h $\xFF\x01\x2A, $\xFF\x02\x07, [$\x03]\0" |
| /* 15860 */ "st4q $\xFF\x01\x25, $\xFF\x02\x07, [$\x03]\0" |
| /* 15882 */ "st4w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| /* 15904 */ "st4 $\xFF\x02\x34$\xFF\x03\x19, [$\x01], #8\0" |
| /* 15927 */ "st4 $\xFF\x02\x35$\xFF\x03\x19, [$\x01], #16\0" |
| /* 15951 */ "st4 $\xFF\x02\x36$\xFF\x03\x19, [$\x01], #32\0" |
| /* 15975 */ "st4 $\xFF\x02\x2B$\xFF\x03\x19, [$\x01], #4\0" |
| /* 15998 */ "stg $\x01, [$\x02]\0" |
| /* 16011 */ "stgp $\x01, $\x02, [$\x03]\0" |
| /* 16029 */ "stlurb $\x01, [$\x02]\0" |
| /* 16045 */ "stlurh $\x01, [$\x02]\0" |
| /* 16061 */ "stlur $\x01, [$\x02]\0" |
| /* 16076 */ "stnp $\x01, $\x02, [$\x03]\0" |
| /* 16094 */ "stnt1b $\xFF\x01\x28, $\xFF\x02\x29, [$\x03]\0" |
| /* 16118 */ "stnt1b $\xFF\x01\x2B, $\xFF\x02\x29, [$\x03]\0" |
| /* 16142 */ "stnt1b $\xFF\x01\x28, $\xFF\x02\x29, [$\x03]\0" |
| /* 16166 */ "stnt1b $\xFF\x01\x28, $\xFF\x02\x07, [$\x03]\0" |
| /* 16190 */ "stnt1b $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 16216 */ "stnt1b $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| /* 16242 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x29, [$\x03]\0" |
| /* 16266 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x29, [$\x03]\0" |
| /* 16290 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]\0" |
| /* 16314 */ "stnt1d $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 16340 */ "stnt1h $\xFF\x01\x2A, $\xFF\x02\x29, [$\x03]\0" |
| /* 16364 */ "stnt1h $\xFF\x01\x34, $\xFF\x02\x29, [$\x03]\0" |
| /* 16388 */ "stnt1h $\xFF\x01\x2A, $\xFF\x02\x29, [$\x03]\0" |
| /* 16412 */ "stnt1h $\xFF\x01\x2A, $\xFF\x02\x07, [$\x03]\0" |
| /* 16436 */ "stnt1h $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 16462 */ "stnt1h $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| /* 16488 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x29, [$\x03]\0" |
| /* 16512 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x29, [$\x03]\0" |
| /* 16536 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0" |
| /* 16560 */ "stnt1w $\xFF\x01\x23, $\xFF\x02\x07, [$\xFF\x03\x10]\0" |
| /* 16586 */ "stnt1w $\xFF\x01\x24, $\xFF\x02\x07, [$\xFF\x03\x0B]\0" |
| /* 16612 */ "stp $\x01, $\x02, [$\x03]\0" |
| /* 16629 */ "strb $\x01, [$\x02, $\x03]\0" |
| /* 16647 */ "strb $\x01, [$\x02]\0" |
| /* 16661 */ "str $\x01, [$\x02, $\x03]\0" |
| /* 16678 */ "str $\x01, [$\x02]\0" |
| /* 16691 */ "strh $\x01, [$\x02, $\x03]\0" |
| /* 16709 */ "strh $\x01, [$\x02]\0" |
| /* 16723 */ "str $\xFF\x01\x07, [$\x02]\0" |
| /* 16738 */ "str $\xFF\x01\x37[$\x02, $\xFF\x03\x20], [$\x04]\0" |
| /* 16763 */ "sttrb $\x01, [$\x02]\0" |
| /* 16778 */ "sttrh $\x01, [$\x02]\0" |
| /* 16793 */ "sttr $\x01, [$\x02]\0" |
| /* 16807 */ "sturb $\x01, [$\x02]\0" |
| /* 16822 */ "stur $\x01, [$\x02]\0" |
| /* 16836 */ "sturh $\x01, [$\x02]\0" |
| /* 16851 */ "stz2g $\x01, [$\x02]\0" |
| /* 16866 */ "stzg $\x01, [$\x02]\0" |
| /* 16880 */ "cmp $\x02, $\xFF\x03\x01\0" |
| /* 16893 */ "cmp $\x02, $\x03\0" |
| /* 16904 */ "cmp $\x02, $\x03$\xFF\x04\x02\0" |
| /* 16919 */ "negs $\x01, $\x03\0" |
| /* 16931 */ "negs $\x01, $\x03$\xFF\x04\x02\0" |
| /* 16947 */ "subs $\x01, $\x02, $\x03\0" |
| /* 16963 */ "cmp $\x02, $\x03$\xFF\x04\x03\0" |
| /* 16978 */ "neg $\x01, $\x03\0" |
| /* 16989 */ "neg $\x01, $\x03$\xFF\x04\x02\0" |
| /* 17004 */ "sub $\x01, $\x02, $\x03\0" |
| /* 17019 */ "sysp $\x01, $\xFF\x02\x3F, $\xFF\x03\x3F, $\x04\0" |
| /* 17043 */ "sys $\x01, $\xFF\x02\x3F, $\xFF\x03\x3F, $\x04\0" |
| /* 17066 */ "lsr $\x01, $\x02, $\x03\0" |
| /* 17081 */ "uxtb $\x01, $\x02\0" |
| /* 17093 */ "uxth $\x01, $\x02\0" |
| /* 17105 */ "uxtw $\x01, $\x02\0" |
| /* 17117 */ "umull $\x01, $\x02, $\x03\0" |
| /* 17134 */ "mov.s $\x01, $\xFF\x02\x0C$\xFF\x03\x19\0" |
| /* 17153 */ "mov.d $\x01, $\xFF\x02\x0C$\xFF\x03\x19\0" |
| /* 17172 */ "umnegl $\x01, $\x02, $\x03\0" |
| /* 17190 */ "uqdecb $\x01\0" |
| /* 17200 */ "uqdecb $\x01, $\xFF\x03\x0E\0" |
| /* 17216 */ "uqdecd $\x01\0" |
| /* 17226 */ "uqdecd $\x01, $\xFF\x03\x0E\0" |
| /* 17242 */ "uqdecd $\xFF\x01\x10\0" |
| /* 17254 */ "uqdecd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| /* 17272 */ "uqdech $\x01\0" |
| /* 17282 */ "uqdech $\x01, $\xFF\x03\x0E\0" |
| /* 17298 */ "uqdech $\xFF\x01\x09\0" |
| /* 17310 */ "uqdech $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| /* 17328 */ "uqdecw $\x01\0" |
| /* 17338 */ "uqdecw $\x01, $\xFF\x03\x0E\0" |
| /* 17354 */ "uqdecw $\xFF\x01\x0B\0" |
| /* 17366 */ "uqdecw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| /* 17384 */ "uqincb $\x01\0" |
| /* 17394 */ "uqincb $\x01, $\xFF\x03\x0E\0" |
| /* 17410 */ "uqincd $\x01\0" |
| /* 17420 */ "uqincd $\x01, $\xFF\x03\x0E\0" |
| /* 17436 */ "uqincd $\xFF\x01\x10\0" |
| /* 17448 */ "uqincd $\xFF\x01\x10, $\xFF\x03\x0E\0" |
| /* 17466 */ "uqinch $\x01\0" |
| /* 17476 */ "uqinch $\x01, $\xFF\x03\x0E\0" |
| /* 17492 */ "uqinch $\xFF\x01\x09\0" |
| /* 17504 */ "uqinch $\xFF\x01\x09, $\xFF\x03\x0E\0" |
| /* 17522 */ "uqincw $\x01\0" |
| /* 17532 */ "uqincw $\x01, $\xFF\x03\x0E\0" |
| /* 17548 */ "uqincw $\xFF\x01\x0B\0" |
| /* 17560 */ "uqincw $\xFF\x01\x0B, $\xFF\x03\x0E\0" |
| /* 17578 */ "xpaclri\0" |
| /* 17586 */ "zero {za}\0" |
| /* 17596 */ "zero {za0.h}\0" |
| /* 17609 */ "zero {za1.h}\0" |
| /* 17622 */ "zero {za0.s}\0" |
| /* 17635 */ "zero {za1.s}\0" |
| /* 17648 */ "zero {za2.s}\0" |
| /* 17661 */ "zero {za3.s}\0" |
| /* 17674 */ "zero {za0.s,za1.s}\0" |
| /* 17693 */ "zero {za0.s,za3.s}\0" |
| /* 17712 */ "zero {za1.s,za2.s}\0" |
| /* 17731 */ "zero {za2.s,za3.s}\0" |
| /* 17750 */ "zero {za0.s,za1.s,za2.s}\0" |
| /* 17775 */ "zero {za0.s,za1.s,za3.s}\0" |
| /* 17800 */ "zero {za0.s,za2.s,za3.s}\0" |
| /* 17825 */ "zero {za1.s,za2.s,za3.s}\0" |
| ; |
| |
| #ifndef NDEBUG |
| static struct SortCheck { |
| SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) { |
| assert(std::is_sorted( |
| OpToPatterns.begin(), OpToPatterns.end(), |
| [](const PatternsForOpcode &L, const PatternsForOpcode &R) { |
| return L.Opcode < R.Opcode; |
| }) && |
| "tablegen failed to sort opcode patterns"); |
| } |
| } sortCheckVar(OpToPatterns); |
| #endif |
| |
| AliasMatchingData M { |
| ArrayRef(OpToPatterns), |
| ArrayRef(Patterns), |
| ArrayRef(Conds), |
| StringRef(AsmStrings, std::size(AsmStrings)), |
| &AArch64AppleInstPrinterValidateMCOperand, |
| }; |
| const char *AsmString = matchAliasPatterns(MI, &STI, M); |
| if (!AsmString) return false; |
| |
| unsigned I = 0; |
| while (AsmString[I] != ' ' && AsmString[I] != '\t' && |
| AsmString[I] != '$' && AsmString[I] != '\0') |
| ++I; |
| OS << '\t' << StringRef(AsmString, I); |
| if (AsmString[I] != '\0') { |
| if (AsmString[I] == ' ' || AsmString[I] == '\t') { |
| OS << '\t'; |
| ++I; |
| } |
| do { |
| if (AsmString[I] == '$') { |
| ++I; |
| if (AsmString[I] == (char)0xff) { |
| ++I; |
| int OpIdx = AsmString[I++] - 1; |
| int PrintMethodIdx = AsmString[I++] - 1; |
| printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, OS); |
| } else |
| printOperand(MI, unsigned(AsmString[I++]) - 1, STI, OS); |
| } else { |
| OS << AsmString[I++]; |
| } |
| } while (AsmString[I] != '\0'); |
| } |
| |
| return true; |
| } |
| |
| void AArch64AppleInstPrinter::printCustomAliasOperand( |
| const MCInst *MI, uint64_t Address, unsigned OpIdx, |
| unsigned PrintMethodIdx, |
| const MCSubtargetInfo &STI, |
| raw_ostream &OS) { |
| switch (PrintMethodIdx) { |
| default: |
| llvm_unreachable("Unknown PrintMethod kind"); |
| break; |
| case 0: |
| printAddSubImm(MI, OpIdx, STI, OS); |
| break; |
| case 1: |
| printShifter(MI, OpIdx, STI, OS); |
| break; |
| case 2: |
| printArithExtend(MI, OpIdx, STI, OS); |
| break; |
| case 3: |
| printLogicalImm<int32_t>(MI, OpIdx, STI, OS); |
| break; |
| case 4: |
| printLogicalImm<int64_t>(MI, OpIdx, STI, OS); |
| break; |
| case 5: |
| printSVERegOp<'b'>(MI, OpIdx, STI, OS); |
| break; |
| case 6: |
| printSVERegOp<>(MI, OpIdx, STI, OS); |
| break; |
| case 7: |
| printLogicalImm<int8_t>(MI, OpIdx, STI, OS); |
| break; |
| case 8: |
| printSVERegOp<'h'>(MI, OpIdx, STI, OS); |
| break; |
| case 9: |
| printLogicalImm<int16_t>(MI, OpIdx, STI, OS); |
| break; |
| case 10: |
| printSVERegOp<'s'>(MI, OpIdx, STI, OS); |
| break; |
| case 11: |
| printVRegOperand(MI, OpIdx, STI, OS); |
| break; |
| case 12: |
| printImm(MI, OpIdx, STI, OS); |
| break; |
| case 13: |
| printSVEPattern(MI, OpIdx, STI, OS); |
| break; |
| case 14: |
| printImm8OptLsl<int8_t>(MI, OpIdx, STI, OS); |
| break; |
| case 15: |
| printSVERegOp<'d'>(MI, OpIdx, STI, OS); |
| break; |
| case 16: |
| printImm8OptLsl<int64_t>(MI, OpIdx, STI, OS); |
| break; |
| case 17: |
| printImm8OptLsl<int16_t>(MI, OpIdx, STI, OS); |
| break; |
| case 18: |
| printImm8OptLsl<int32_t>(MI, OpIdx, STI, OS); |
| break; |
| case 19: |
| printInverseCondCode(MI, OpIdx, STI, OS); |
| break; |
| case 20: |
| printSVELogicalImm<int16_t>(MI, OpIdx, STI, OS); |
| break; |
| case 21: |
| printSVELogicalImm<int32_t>(MI, OpIdx, STI, OS); |
| break; |
| case 22: |
| printSVELogicalImm<int64_t>(MI, OpIdx, STI, OS); |
| break; |
| case 23: |
| printZPRasFPR<8>(MI, OpIdx, STI, OS); |
| break; |
| case 24: |
| printVectorIndex(MI, OpIdx, STI, OS); |
| break; |
| case 25: |
| printZPRasFPR<64>(MI, OpIdx, STI, OS); |
| break; |
| case 26: |
| printZPRasFPR<16>(MI, OpIdx, STI, OS); |
| break; |
| case 27: |
| printSVERegOp<'q'>(MI, OpIdx, STI, OS); |
| break; |
| case 28: |
| printZPRasFPR<128>(MI, OpIdx, STI, OS); |
| break; |
| case 29: |
| printZPRasFPR<32>(MI, OpIdx, STI, OS); |
| break; |
| case 30: |
| printMatrixTileVector<0>(MI, OpIdx, STI, OS); |
| break; |
| case 31: |
| printMatrixIndex(MI, OpIdx, STI, OS); |
| break; |
| case 32: |
| printMatrixTileVector<1>(MI, OpIdx, STI, OS); |
| break; |
| case 33: |
| printFPImmOperand(MI, OpIdx, STI, OS); |
| break; |
| case 34: |
| printTypedVectorList<0,'d'>(MI, OpIdx, STI, OS); |
| break; |
| case 35: |
| printTypedVectorList<0,'s'>(MI, OpIdx, STI, OS); |
| break; |
| case 36: |
| printTypedVectorList<0,'q'>(MI, OpIdx, STI, OS); |
| break; |
| case 37: |
| printBTIHintOp(MI, OpIdx, STI, OS); |
| break; |
| case 38: |
| printPSBHintOp(MI, OpIdx, STI, OS); |
| break; |
| case 39: |
| printTypedVectorList<0,'b'>(MI, OpIdx, STI, OS); |
| break; |
| case 40: |
| printPredicateAsCounter<0>(MI, OpIdx, STI, OS); |
| break; |
| case 41: |
| printTypedVectorList<0,'h'>(MI, OpIdx, STI, OS); |
| break; |
| case 42: |
| printTypedVectorList<0, 'b'>(MI, OpIdx, STI, OS); |
| break; |
| case 43: |
| printTypedVectorList<16, 'b'>(MI, OpIdx, STI, OS); |
| break; |
| case 44: |
| printTypedVectorList<1, 'd'>(MI, OpIdx, STI, OS); |
| break; |
| case 45: |
| printTypedVectorList<2, 'd'>(MI, OpIdx, STI, OS); |
| break; |
| case 46: |
| printTypedVectorList<2, 's'>(MI, OpIdx, STI, OS); |
| break; |
| case 47: |
| printTypedVectorList<4, 'h'>(MI, OpIdx, STI, OS); |
| break; |
| case 48: |
| printTypedVectorList<4, 's'>(MI, OpIdx, STI, OS); |
| break; |
| case 49: |
| printTypedVectorList<8, 'b'>(MI, OpIdx, STI, OS); |
| break; |
| case 50: |
| printTypedVectorList<8, 'h'>(MI, OpIdx, STI, OS); |
| break; |
| case 51: |
| printTypedVectorList<0, 'h'>(MI, OpIdx, STI, OS); |
| break; |
| case 52: |
| printTypedVectorList<0, 's'>(MI, OpIdx, STI, OS); |
| break; |
| case 53: |
| printTypedVectorList<0, 'd'>(MI, OpIdx, STI, OS); |
| break; |
| case 54: |
| printMatrix<0>(MI, OpIdx, STI, OS); |
| break; |
| case 55: |
| printImmRangeScale<2, 1>(MI, OpIdx, STI, OS); |
| break; |
| case 56: |
| printImmRangeScale<4, 3>(MI, OpIdx, STI, OS); |
| break; |
| case 57: |
| printMatrix<64>(MI, OpIdx, STI, OS); |
| break; |
| case 58: |
| printImmHex(MI, OpIdx, STI, OS); |
| break; |
| case 59: |
| printPrefetchOp<true>(MI, OpIdx, STI, OS); |
| break; |
| case 60: |
| printPrefetchOp(MI, OpIdx, STI, OS); |
| break; |
| case 61: |
| printGPR64as32(MI, OpIdx, STI, OS); |
| break; |
| case 62: |
| printSysCROperand(MI, OpIdx, STI, OS); |
| break; |
| } |
| } |
| |
| static bool AArch64AppleInstPrinterValidateMCOperand(const MCOperand &MCOp, |
| const MCSubtargetInfo &STI, |
| unsigned PredicateIndex) { |
| switch (PredicateIndex) { |
| default: |
| llvm_unreachable("Unknown MCOperandPredicate kind"); |
| break; |
| case 1: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int8_t>(Val); |
| |
| } |
| case 2: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val); |
| |
| } |
| case 3: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val); |
| |
| } |
| case 4: { |
| |
| return MCOp.isImm() && |
| MCOp.getImm() != AArch64CC::AL && |
| MCOp.getImm() != AArch64CC::NV; |
| |
| } |
| case 5: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val) && |
| AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); |
| |
| } |
| case 6: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val) && |
| AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); |
| |
| } |
| case 7: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int64_t>(Val) && |
| AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); |
| |
| } |
| case 8: { |
| |
| // "bti" is an alias to "hint" only for certain values of CRm:Op2 fields. |
| if (!MCOp.isImm()) |
| return false; |
| return AArch64BTIHint::lookupBTIByEncoding(MCOp.getImm() ^ 32) != nullptr; |
| |
| } |
| case 9: { |
| |
| // Check, if operand is valid, to fix exhaustive aliasing in disassembly. |
| // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields. |
| if (!MCOp.isImm()) |
| return false; |
| return AArch64PSBHint::lookupPSBByEncoding(MCOp.getImm()) != nullptr; |
| |
| } |
| } |
| } |
| |
| #endif // PRINT_ALIAS_INSTR |