Subzero, MIPS32: Randomly insert NOP
Patch implements randomlyInsertNop for MIPS32. Separate test case
added because current test is based on function with vector
operands, which MIPS32 does not support yet.
run-pnacl-sz.py updated, to pass -z argument to objdump, so it does
not hide multiple nops (shows ... instead) between instruction.
R=stichnot@chromium.org
Review URL: https://codereview.chromium.org/2340733003 .
Patch from Srdjan Obucina <Srdjan.Obucina@imgtec.com>.
diff --git a/pydir/run-pnacl-sz.py b/pydir/run-pnacl-sz.py
index 580d227..a9267ea 100755
--- a/pydir/run-pnacl-sz.py
+++ b/pydir/run-pnacl-sz.py
@@ -202,10 +202,11 @@
elif output_file_name:
cmd += ['-o', output_file_name]
if args.disassemble:
- # Show wide instruction encodings, diassemble, and show relocs.
+ # Show wide instruction encodings, diassemble, show relocs and
+ # dissasemble zeros.
cmd += (['&&', os.path.join(pnacl_bin_path, GetObjdumpCmd())] +
args.dis_flags +
- ['-w', '-d', '-r'] + TargetDisassemblerFlags(args.target) +
+ ['-w', '-d', '-r', '-z'] + TargetDisassemblerFlags(args.target) +
[output_file_name])
stdout_result = shellcmd(cmd, echo=args.echo_cmd)
diff --git a/src/IceTargetLoweringMIPS32.cpp b/src/IceTargetLoweringMIPS32.cpp
index d74a8d8..c4b6024 100644
--- a/src/IceTargetLoweringMIPS32.cpp
+++ b/src/IceTargetLoweringMIPS32.cpp
@@ -3196,7 +3196,7 @@
RandomNumberGenerator &RNG) {
RandomNumberGeneratorWrapper RNGW(RNG);
if (RNGW.getTrueWithProbability(Probability)) {
- UnimplementedError(getFlags());
+ _nop();
}
}
diff --git a/src/IceTargetLoweringMIPS32.h b/src/IceTargetLoweringMIPS32.h
index 8029386..5cc412f 100644
--- a/src/IceTargetLoweringMIPS32.h
+++ b/src/IceTargetLoweringMIPS32.h
@@ -419,6 +419,8 @@
Context.insert<InstMIPS32Multu>(Dest, Src0, Src1);
}
+ void _nop() { Context.insert<InstMIPS32Sll>(getZero(), getZero(), 0); }
+
void _or(Variable *Dest, Variable *Src0, Variable *Src1) {
Context.insert<InstMIPS32Or>(Dest, Src0, Src1);
}
diff --git a/tests_lit/llvm2ice_tests/nop-insertion-no-vectors.ll b/tests_lit/llvm2ice_tests/nop-insertion-no-vectors.ll
new file mode 100644
index 0000000..497357e
--- /dev/null
+++ b/tests_lit/llvm2ice_tests/nop-insertion-no-vectors.ll
@@ -0,0 +1,208 @@
+; REQUIRES: allow_dump
+
+; RUN: %p2i -i %s --filetype=asm --assemble --disassemble --target=mips32 \
+; RUN: -a -skip-unimplemented -sz-seed=1 -nop-insertion \
+; RUN: -nop-insertion-percentage=50 -max-nops-per-instruction=1 \
+; RUN: | FileCheck %s --check-prefix=MIPS32P50N1
+; RUN: %p2i -i %s --filetype=asm --assemble --disassemble --target=mips32 \
+; RUN: -a -skip-unimplemented -sz-seed=1 -nop-insertion \
+; RUN: -nop-insertion-percentage=110 -max-nops-per-instruction=2 \
+; RUN: | FileCheck %s --check-prefix=MIPS32P110N2
+
+
+define internal i32 @nopInsertion(i32 %a, i32 %b, i32 %c) {
+entry:
+ %a1 = add i32 %a, 1
+ %b1 = add i32 %b, 2
+ %c1 = add i32 %c, 3
+ %a2 = sub i32 %a1, 1
+ %b2 = sub i32 %b1, 2
+ %c2 = sub i32 %c1, 3
+ %a3 = mul i32 %a2, %b2
+ %b3 = mul i32 %a3, %c2
+ ret i32 %b3
+}
+
+; MIPS32P50N1-LABEL: nopInsertion
+; MIPS32P50N1: nop
+; MIPS32P50N1: addiu {{.*}}
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: li {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: addu {{.*}}
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: li {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: addu {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: li {{.*}}
+; MIPS32P50N1: addu {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: li {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: subu {{.*}}
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: li {{.*}}
+; MIPS32P50N1: subu {{.*}}
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: li {{.*}}
+; MIPS32P50N1: subu {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: mul {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: mul {{.*}}
+; MIPS32P50N1: nop
+; MIPS32P50N1: sw {{.*}}
+; MIPS32P50N1: lw {{.*}}
+; MIPS32P50N1: addiu {{.*}}
+; MIPS32P50N1: jr ra
+; MIPS32P50N1: nop
+
+; MIPS32P110N2-LABEL: nopInsertion
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: addiu {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: li {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: addu {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: li {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: addu {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: li {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: addu {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: li {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: subu {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: li {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: subu {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: li {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: subu {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: mul {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: mul {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: sw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: lw {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: addiu {{.*}}
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
+; MIPS32P110N2: jr ra
+; MIPS32P110N2: nop
+; MIPS32P110N2: nop
