third_party/llvm-7.0/llvm/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir

# RUN: llc -mtriple=powerpc64-unknown-linux-gnu -run-pass none -o - %s | FileCheck %s
# PR24724

--- |
  define signext i32 @main(i32* %p) #0 {
  entry:
    %0 = load i32, i32* %p, align 4
    %or = or i32 0, %0
    store i32 %or, i32* %p, align 4
    %lnot.1 = icmp eq i32 undef, 0
    %lnot.ext.1 = zext i1 %lnot.1 to i32
    %shr.i.1 = lshr i32 2072, %lnot.ext.1
    %call.lobit.1 = lshr i32 %shr.i.1, 7
    %1 = and i32 %call.lobit.1, 1
    %or.1 = or i32 %1, %or
    ret i32 %or.1
  }

  attributes #0 = { nounwind "target-cpu"="ppc64" }
...
---
name:            main
tracksRegLiveness: true
registers:
  - { id: 0, class: g8rc_and_g8rc_nox0 }
  - { id: 1, class: gprc }
  - { id: 2, class: gprc }
  - { id: 3, class: gprc }
  - { id: 4, class: g8rc }
liveins:
  - { reg: '$x3', virtual-reg: '%0' }
body: |
  bb.0.entry:
    liveins: $x3

    %0 = COPY $x3
    %1 = LWZ 0, %0 :: (load 4 from %ir.p)
    %2 = LI 0
    %3 = RLWIMI %2, killed %1, 0, 0, 31
    %4 = EXTSW_32_64 killed %3
    $x3 = COPY %4
  ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
    BLR8 implicit $lr8, implicit $rm, implicit $x3
...