third_party/llvm-7.0/llvm/test/CodeGen/ARM/cmp2-peephole-thumb.mir

# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s

# Here we check that the peephole cmp rewrite is not triggered, because
# there is store instruction between the tMUL and tCMP, i.e. there are
# no constants to reorder.

--- |
  ; ModuleID = 'cmp2-peephole-thumb.ll'
  source_filename = "<stdin>"
  target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
  target triple = "thumb-none--eabi"

  define i32 @g(i32 %a, i32 %b) {
  entry:
    %retval = alloca i32, align 4
    %mul = alloca i32, align 4
    %mul1 = mul nsw i32 %a, %b
    store i32 %mul1, i32* %mul, align 4
    %0 = load i32, i32* %mul, align 4
    %cmp = icmp sle i32 %0, 0
    br i1 %cmp, label %if.then, label %if.end

  if.then:                                          ; preds = %entry
    store i32 42, i32* %retval, align 4
    br label %return

  if.end:                                           ; preds = %entry
    store i32 1, i32* %retval, align 4
    br label %return

  return:                                           ; preds = %if.end, %if.then
    %1 = load i32, i32* %retval, align 4
    ret i32 %1
  }

...
---
name:            g
# CHECK-LABEL: name: g
alignment:       1
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: tgpr }
  - { id: 1, class: tgpr }
  - { id: 2, class: tgpr }
  - { id: 3, class: tgpr }
  - { id: 4, class: tgpr }
  - { id: 5, class: tgpr }
liveins:
  - { reg: '$r0', virtual-reg: '%0' }
  - { reg: '$r1', virtual-reg: '%1' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    4
  adjustsStack:    false
  hasCalls:        false
  maxCallFrameSize: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
stack:
  - { id: 0, name: retval, offset: 0, size: 4, alignment: 4, local-offset: -4 }
  - { id: 1, name: mul, offset: 0, size: 4, alignment: 4, local-offset: -8 }

# CHECK: tMUL
# CHECK-NEXT: tSTRspi
# CHECK-NEXT: tCMPi8
body:             |
  bb.0.entry:
    liveins: $r0, $r1

    %1 = COPY $r1
    %0 = COPY $r0
    %2, $cpsr = tMUL %0, %1, 14, $noreg
    tSTRspi %2, %stack.1.mul, 0, 14, $noreg :: (store 4 into %ir.mul)
    tCMPi8 %2, 0, 14, $noreg, implicit-def $cpsr
    tBcc %bb.2.if.end, 12, $cpsr
    tB %bb.1.if.then, 14, $noreg

  bb.1.if.then:
    %4, $cpsr = tMOVi8 42, 14, $noreg
    tSTRspi killed %4, %stack.0.retval, 0, 14, $noreg :: (store 4 into %ir.retval)
    tB %bb.3.return, 14, $noreg

  bb.2.if.end:
    %3, $cpsr = tMOVi8 1, 14, $noreg
    tSTRspi killed %3, %stack.0.retval, 0, 14, $noreg :: (store 4 into %ir.retval)

  bb.3.return:
    %5 = tLDRspi %stack.0.retval, 0, 14, $noreg :: (dereferenceable load 4 from %ir.retval)
    $r0 = COPY %5
    tBX_RET 14, $noreg, implicit $r0

...