| # RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s | |
| --- | |
| name: exp0 | |
| legalized: true | |
| regBankSelected: true | |
| # CHECK: name: exp0 | |
| body: | | |
| bb.0: | |
| liveins: $vgpr0 | |
| %0:vgpr(s32) = COPY $vgpr0 | |
| %1:sgpr(s32) = G_CONSTANT i32 1 | |
| %2:sgpr(s32) = G_CONSTANT i32 15 | |
| %3:sgpr(s1) = G_CONSTANT i1 0 | |
| %4:sgpr(s1) = G_CONSTANT i1 1 | |
| ; CHECK: EXP 1, %0, %0, %0, %0, 0, 0, 15, implicit $exec | |
| G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %1:sgpr(s32), %2:sgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %3:sgpr(s1), %3:sgpr(s1) | |
| ; CHECK: EXP_DONE 1, %0, %0, %0, %0, 0, 0, 15, implicit $exec | |
| G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %1:sgpr(s32), %2:sgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %0:vgpr(s32), %4:sgpr(s1), %3:sgpr(s1) | |
| %5:vgpr(<2 x s16>) = G_BITCAST %0(s32) | |
| ; CHECK: [[UNDEF0:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF | |
| ; CHECK: EXP 1, %0, %0, [[UNDEF0]], [[UNDEF0]], 0, 1, 15, implicit $exec | |
| G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), %1:sgpr(s32), %2:sgpr(s32), %5:vgpr(<2 x s16>), %5:vgpr(<2 x s16>), %3:sgpr(s1), %3:sgpr(s1) | |
| ; CHECK: [[UNDEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF | |
| ; CHECK: EXP_DONE 1, %0, %0, [[UNDEF1]], [[UNDEF1]], 0, 1, 15, implicit $exec | |
| G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), %1:sgpr(s32), %2:sgpr(s32), %5:vgpr(<2 x s16>), %5:vgpr(<2 x s16>), %4:sgpr(s1), %3:sgpr(s1) | |