| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* "Fast" Instruction Selector for the X86 target *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| |
| // FastEmit Immediate Predicate functions. |
| static bool Predicate_i16immSExt8(int64_t Imm) { |
| return isInt<8>(Imm); |
| } |
| static bool Predicate_i32immSExt8(int64_t Imm) { |
| return isInt<8>(Imm); |
| } |
| static bool Predicate_i64immSExt8(int64_t Imm) { |
| return isInt<8>(Imm); |
| } |
| static bool Predicate_i64immSExt32(int64_t Imm) { |
| return isInt<32>(Imm); |
| } |
| static bool Predicate_AndMask64(int64_t Imm) { |
| |
| return isMask_64(Imm) && !isUInt<32>(Imm); |
| |
| } |
| static bool Predicate_BTRMask64(int64_t Imm) { |
| |
| return !isUInt<32>(Imm) && !isInt<32>(Imm) && isPowerOf2_64(~Imm); |
| |
| } |
| static bool Predicate_BTCBTSMask64(int64_t Imm) { |
| |
| return !isInt<32>(Imm) && isPowerOf2_64(Imm); |
| |
| } |
| |
| |
| // FastEmit functions for ISD::ABS. |
| |
| unsigned fastEmit_ISD_ABS_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPABSBZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSSE3() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::PABSBrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPABSBrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ABS_MVT_v32i8_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPABSBZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPABSBYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ABS_MVT_v64i8_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v64i8) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPABSBZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ABS_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPABSWZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSSE3() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::PABSWrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPABSWrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ABS_MVT_v16i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPABSWZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPABSWYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ABS_MVT_v32i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPABSWZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ABS_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPABSDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSSE3() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::PABSDrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPABSDrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ABS_MVT_v8i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPABSDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPABSDYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ABS_MVT_v16i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPABSDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ABS_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPABSQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ABS_MVT_v4i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPABSQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ABS_MVT_v8i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPABSQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ABS_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_ISD_ABS_MVT_v16i8_r(RetVT, Op0); |
| case MVT::v32i8: return fastEmit_ISD_ABS_MVT_v32i8_r(RetVT, Op0); |
| case MVT::v64i8: return fastEmit_ISD_ABS_MVT_v64i8_r(RetVT, Op0); |
| case MVT::v8i16: return fastEmit_ISD_ABS_MVT_v8i16_r(RetVT, Op0); |
| case MVT::v16i16: return fastEmit_ISD_ABS_MVT_v16i16_r(RetVT, Op0); |
| case MVT::v32i16: return fastEmit_ISD_ABS_MVT_v32i16_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_ISD_ABS_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v8i32: return fastEmit_ISD_ABS_MVT_v8i32_r(RetVT, Op0); |
| case MVT::v16i32: return fastEmit_ISD_ABS_MVT_v16i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_ISD_ABS_MVT_v2i64_r(RetVT, Op0); |
| case MVT::v4i64: return fastEmit_ISD_ABS_MVT_v4i64_r(RetVT, Op0); |
| case MVT::v8i64: return fastEmit_ISD_ABS_MVT_v8i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::ANY_EXTEND. |
| |
| unsigned fastEmit_ISD_ANY_EXTEND_MVT_i8_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| return fastEmitInst_r(X86::MOVZX32rr8, &X86::GR32RegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i8: return fastEmit_ISD_ANY_EXTEND_MVT_i8_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::BITCAST. |
| |
| unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VMOVDI2SSZrr, &X86::FR32XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::MOVDI2SSrr, &X86::FR32RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VMOVDI2SSrr, &X86::FR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_BITCAST_MVT_i64_MVT_f64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VMOV64toSDZrr, &X86::FR64XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::MOV64toSDrr, &X86::FR64RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VMOV64toSDrr, &X86::FR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_BITCAST_MVT_i64_MVT_x86mmx_r(unsigned Op0) { |
| if ((Subtarget->hasMMX()) && (Subtarget->is64Bit())) { |
| return fastEmitInst_r(X86::MMX_MOVD64to64rr, &X86::VR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::f64: return fastEmit_ISD_BITCAST_MVT_i64_MVT_f64_r(Op0); |
| case MVT::x86mmx: return fastEmit_ISD_BITCAST_MVT_i64_MVT_x86mmx_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VMOVSS2DIZrr, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::MOVSS2DIrr, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VMOVSS2DIrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VMOVSDto64Zrr, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::MOVSDto64rr, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VMOVSDto64rr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_BITCAST_MVT_f64_MVT_x86mmx_r(unsigned Op0) { |
| if ((Subtarget->hasMMX()) && (Subtarget->hasSSE2())) { |
| return fastEmitInst_r(X86::MMX_MOVFR642Qrr, &X86::VR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i64: return fastEmit_ISD_BITCAST_MVT_f64_MVT_i64_r(Op0); |
| case MVT::x86mmx: return fastEmit_ISD_BITCAST_MVT_f64_MVT_x86mmx_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_BITCAST_MVT_x86mmx_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasMMX()) && (Subtarget->is64Bit())) { |
| return fastEmitInst_r(X86::MMX_MOVD64from64rr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_BITCAST_MVT_x86mmx_MVT_f64_r(unsigned Op0) { |
| if ((Subtarget->hasMMX()) && (Subtarget->hasSSE2())) { |
| return fastEmitInst_r(X86::MMX_MOVQ2FR64rr, &X86::FR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_BITCAST_MVT_x86mmx_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i64: return fastEmit_ISD_BITCAST_MVT_x86mmx_MVT_i64_r(Op0); |
| case MVT::f64: return fastEmit_ISD_BITCAST_MVT_x86mmx_MVT_f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0); |
| case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0); |
| case MVT::x86mmx: return fastEmit_ISD_BITCAST_MVT_x86mmx_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::BRIND. |
| |
| unsigned fastEmit_ISD_BRIND_MVT_i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::isVoid) |
| return 0; |
| if ((!Subtarget->is64Bit())) { |
| return fastEmitInst_r(X86::JMP16r, &X86::GR16RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::isVoid) |
| return 0; |
| if ((!Subtarget->is64Bit())) { |
| return fastEmitInst_r(X86::JMP32r, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::isVoid) |
| return 0; |
| if ((Subtarget->is64Bit())) { |
| return fastEmitInst_r(X86::JMP64r, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i16: return fastEmit_ISD_BRIND_MVT_i16_r(RetVT, Op0); |
| case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::BSWAP. |
| |
| unsigned fastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| return fastEmitInst_r(X86::BSWAP32r, &X86::GR32RegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_BSWAP_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| return fastEmitInst_r(X86::BSWAP64r, &X86::GR64RegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_ISD_BSWAP_MVT_i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::CTLZ. |
| |
| unsigned fastEmit_ISD_CTLZ_MVT_i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i16) |
| return 0; |
| if ((Subtarget->hasLZCNT())) { |
| return fastEmitInst_r(X86::LZCNT16rr, &X86::GR16RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasLZCNT())) { |
| return fastEmitInst_r(X86::LZCNT32rr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| if ((Subtarget->hasLZCNT())) { |
| return fastEmitInst_r(X86::LZCNT64rr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasCDI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPLZCNTDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTLZ_MVT_v8i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i32) |
| return 0; |
| if ((Subtarget->hasCDI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPLZCNTDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTLZ_MVT_v16i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasCDI())) { |
| return fastEmitInst_r(X86::VPLZCNTDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasCDI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPLZCNTQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTLZ_MVT_v4i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i64) |
| return 0; |
| if ((Subtarget->hasCDI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPLZCNTQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTLZ_MVT_v8i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i64) |
| return 0; |
| if ((Subtarget->hasCDI())) { |
| return fastEmitInst_r(X86::VPLZCNTQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i16: return fastEmit_ISD_CTLZ_MVT_i16_r(RetVT, Op0); |
| case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v8i32: return fastEmit_ISD_CTLZ_MVT_v8i32_r(RetVT, Op0); |
| case MVT::v16i32: return fastEmit_ISD_CTLZ_MVT_v16i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0); |
| case MVT::v4i64: return fastEmit_ISD_CTLZ_MVT_v4i64_r(RetVT, Op0); |
| case MVT::v8i64: return fastEmit_ISD_CTLZ_MVT_v8i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::CTPOP. |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i16) |
| return 0; |
| if ((Subtarget->hasPOPCNT())) { |
| return fastEmitInst_r(X86::POPCNT16rr, &X86::GR16RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasPOPCNT())) { |
| return fastEmitInst_r(X86::POPCNT32rr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| if ((Subtarget->hasPOPCNT())) { |
| return fastEmitInst_r(X86::POPCNT64rr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasBITALG()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPOPCNTBZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_v32i8_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32i8) |
| return 0; |
| if ((Subtarget->hasBITALG()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPOPCNTBZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_v64i8_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v64i8) |
| return 0; |
| if ((Subtarget->hasBITALG())) { |
| return fastEmitInst_r(X86::VPOPCNTBZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i16) |
| return 0; |
| if ((Subtarget->hasBITALG()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPOPCNTWZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_v16i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i16) |
| return 0; |
| if ((Subtarget->hasBITALG()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPOPCNTWZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_v32i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasBITALG())) { |
| return fastEmitInst_r(X86::VPOPCNTWZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasVLX()) && (Subtarget->hasVPOPCNTDQ())) { |
| return fastEmitInst_r(X86::VPOPCNTDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_v8i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i32) |
| return 0; |
| if ((Subtarget->hasVLX()) && (Subtarget->hasVPOPCNTDQ())) { |
| return fastEmitInst_r(X86::VPOPCNTDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_v16i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasVPOPCNTDQ())) { |
| return fastEmitInst_r(X86::VPOPCNTDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasVLX()) && (Subtarget->hasVPOPCNTDQ())) { |
| return fastEmitInst_r(X86::VPOPCNTQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_v4i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i64) |
| return 0; |
| if ((Subtarget->hasVLX()) && (Subtarget->hasVPOPCNTDQ())) { |
| return fastEmitInst_r(X86::VPOPCNTQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_v8i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i64) |
| return 0; |
| if ((Subtarget->hasVPOPCNTDQ())) { |
| return fastEmitInst_r(X86::VPOPCNTQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i16: return fastEmit_ISD_CTPOP_MVT_i16_r(RetVT, Op0); |
| case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0); |
| case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0); |
| case MVT::v32i8: return fastEmit_ISD_CTPOP_MVT_v32i8_r(RetVT, Op0); |
| case MVT::v64i8: return fastEmit_ISD_CTPOP_MVT_v64i8_r(RetVT, Op0); |
| case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0); |
| case MVT::v16i16: return fastEmit_ISD_CTPOP_MVT_v16i16_r(RetVT, Op0); |
| case MVT::v32i16: return fastEmit_ISD_CTPOP_MVT_v32i16_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v8i32: return fastEmit_ISD_CTPOP_MVT_v8i32_r(RetVT, Op0); |
| case MVT::v16i32: return fastEmit_ISD_CTPOP_MVT_v16i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0); |
| case MVT::v4i64: return fastEmit_ISD_CTPOP_MVT_v4i64_r(RetVT, Op0); |
| case MVT::v8i64: return fastEmit_ISD_CTPOP_MVT_v8i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::CTTZ. |
| |
| unsigned fastEmit_ISD_CTTZ_MVT_i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i16) |
| return 0; |
| if ((Subtarget->hasBMI())) { |
| return fastEmitInst_r(X86::TZCNT16rr, &X86::GR16RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasBMI())) { |
| return fastEmitInst_r(X86::TZCNT32rr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| if ((Subtarget->hasBMI())) { |
| return fastEmitInst_r(X86::TZCNT64rr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i16: return fastEmit_ISD_CTTZ_MVT_i16_r(RetVT, Op0); |
| case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::CTTZ_ZERO_UNDEF. |
| |
| unsigned fastEmit_ISD_CTTZ_ZERO_UNDEF_MVT_i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i16) |
| return 0; |
| return fastEmitInst_r(X86::BSF16rr, &X86::GR16RegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_CTTZ_ZERO_UNDEF_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| return fastEmitInst_r(X86::BSF32rr, &X86::GR32RegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_CTTZ_ZERO_UNDEF_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| return fastEmitInst_r(X86::BSF64rr, &X86::GR64RegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_CTTZ_ZERO_UNDEF_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i16: return fastEmit_ISD_CTTZ_ZERO_UNDEF_MVT_i16_r(RetVT, Op0); |
| case MVT::i32: return fastEmit_ISD_CTTZ_ZERO_UNDEF_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_ISD_CTTZ_ZERO_UNDEF_MVT_i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FABS. |
| |
| unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((!Subtarget->hasSSE1())) { |
| return fastEmitInst_r(X86::ABS_Fp32, &X86::RFP32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((!Subtarget->hasSSE2())) { |
| return fastEmitInst_r(X86::ABS_Fp64, &X86::RFP64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FABS_MVT_f80_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f80) |
| return 0; |
| if ((Subtarget->hasX87())) { |
| return fastEmitInst_r(X86::ABS_Fp80, &X86::RFP80RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0); |
| case MVT::f80: return fastEmit_ISD_FABS_MVT_f80_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FNEG. |
| |
| unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((!Subtarget->hasSSE1())) { |
| return fastEmitInst_r(X86::CHS_Fp32, &X86::RFP32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((!Subtarget->hasSSE2())) { |
| return fastEmitInst_r(X86::CHS_Fp64, &X86::RFP64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FNEG_MVT_f80_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f80) |
| return 0; |
| if ((Subtarget->hasX87())) { |
| return fastEmitInst_r(X86::CHS_Fp80, &X86::RFP80RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0); |
| case MVT::f80: return fastEmit_ISD_FNEG_MVT_f80_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FP_EXTEND. |
| |
| unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSS2SDrr, &X86::FR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_EXTEND_MVT_v8f16_MVT_v8f32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2PSXZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_EXTEND_MVT_v8f16_MVT_v8f64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTPH2PDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_EXTEND_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f32: return fastEmit_ISD_FP_EXTEND_MVT_v8f16_MVT_v8f32_r(Op0); |
| case MVT::v8f64: return fastEmit_ISD_FP_EXTEND_MVT_v8f16_MVT_v8f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_FP_EXTEND_MVT_v16f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTPH2PSXZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_EXTEND_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2PDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2PDYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_EXTEND_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTPS2PDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0); |
| case MVT::v8f16: return fastEmit_ISD_FP_EXTEND_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v16f16: return fastEmit_ISD_FP_EXTEND_MVT_v16f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_FP_EXTEND_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_ISD_FP_EXTEND_MVT_v8f32_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FP_ROUND. |
| |
| unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSD2SSrr, &X86::FR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FP_TO_SINT. |
| |
| unsigned fastEmit_ISD_FP_TO_SINT_MVT_f16_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTSH2SIZrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_SINT_MVT_f16_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTSH2SI64Zrr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_SINT_MVT_f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f16_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f16_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2SIZrr, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTTSS2SIrr, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2SIrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2SI64Zrr, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTTSS2SI64rr, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2SI64rr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f32_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2SIZrr, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTTSD2SIrr, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2SIrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2SI64Zrr, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTTSD2SI64rr, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2SI64rr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2DQYrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f16: return fastEmit_ISD_FP_TO_SINT_MVT_f16_r(RetVT, Op0); |
| case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f64: return fastEmit_ISD_FP_TO_SINT_MVT_v4f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FP_TO_UINT. |
| |
| unsigned fastEmit_ISD_FP_TO_UINT_MVT_f16_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTSH2USIZrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_UINT_MVT_f16_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTSH2USI64Zrr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_UINT_MVT_f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f16_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f16_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2USIZrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2USI64Zrr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f32_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2USIZrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2USI64Zrr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f16: return fastEmit_ISD_FP_TO_UINT_MVT_f16_r(RetVT, Op0); |
| case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FSQRT. |
| |
| unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::SQRTSSr, &X86::FR32RegClass, Op0); |
| } |
| if ((!Subtarget->hasSSE1())) { |
| return fastEmitInst_r(X86::SQRT_Fp32, &X86::RFP32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::SQRTSDr, &X86::FR64RegClass, Op0); |
| } |
| if ((!Subtarget->hasSSE2())) { |
| return fastEmitInst_r(X86::SQRT_Fp64, &X86::RFP64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSQRT_MVT_f80_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f80) |
| return 0; |
| if ((Subtarget->hasX87())) { |
| return fastEmitInst_r(X86::SQRT_Fp80, &X86::RFP80RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSQRT_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VSQRTPHZ128r, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSQRT_MVT_v16f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VSQRTPHZ256r, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSQRT_MVT_v32f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VSQRTPHZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VSQRTPSZ128r, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::SQRTPSr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VSQRTPSr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSQRT_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f32) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VSQRTPSZ256r, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VSQRTPSYr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSQRT_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VSQRTPSZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VSQRTPDZ128r, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::SQRTPDr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VSQRTPDr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSQRT_MVT_v4f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f64) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VSQRTPDZ256r, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VSQRTPDYr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSQRT_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VSQRTPDZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0); |
| case MVT::f80: return fastEmit_ISD_FSQRT_MVT_f80_r(RetVT, Op0); |
| case MVT::v8f16: return fastEmit_ISD_FSQRT_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v16f16: return fastEmit_ISD_FSQRT_MVT_v16f16_r(RetVT, Op0); |
| case MVT::v32f16: return fastEmit_ISD_FSQRT_MVT_v32f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_ISD_FSQRT_MVT_v8f32_r(RetVT, Op0); |
| case MVT::v16f32: return fastEmit_ISD_FSQRT_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0); |
| case MVT::v4f64: return fastEmit_ISD_FSQRT_MVT_v4f64_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_ISD_FSQRT_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::LLRINT. |
| |
| unsigned fastEmit_ISD_LLRINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSS2SI64Zrr, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSS2SI64rr, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSS2SI64rr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_LLRINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSD2SI64Zrr, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSD2SI64rr, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSD2SI64rr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_LLRINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_LLRINT_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_LLRINT_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::LRINT. |
| |
| unsigned fastEmit_ISD_LRINT_MVT_f32_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSS2SIZrr, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSS2SIrr, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSS2SIrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_LRINT_MVT_f32_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSS2SI64Zrr, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSS2SI64rr, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSS2SI64rr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_LRINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_LRINT_MVT_f32_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_ISD_LRINT_MVT_f32_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_LRINT_MVT_f64_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSD2SIZrr, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSD2SIrr, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSD2SIrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_LRINT_MVT_f64_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSD2SI64Zrr, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSD2SI64rr, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSD2SI64rr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_LRINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_LRINT_MVT_f64_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_ISD_LRINT_MVT_f64_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_LRINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_LRINT_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_LRINT_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::SCALAR_TO_VECTOR. |
| |
| unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VMOVDI2PDIZrr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::MOVDI2PDIrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VMOVDI2PDIrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VMOV64toPQIZrr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::MOV64toPQIrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VMOV64toPQIrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::SIGN_EXTEND. |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i8_MVT_i32_r(unsigned Op0) { |
| return fastEmitInst_r(X86::MOVSX32rr8, &X86::GR32RegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i8_MVT_i64_r(unsigned Op0) { |
| return fastEmitInst_r(X86::MOVSX64rr8, &X86::GR64RegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i8_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i8_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_ISD_SIGN_EXTEND_MVT_i8_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i16_MVT_i32_r(unsigned Op0) { |
| return fastEmitInst_r(X86::MOVSX32rr16, &X86::GR32RegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i16_MVT_i64_r(unsigned Op0) { |
| return fastEmitInst_r(X86::MOVSX64rr16, &X86::GR64RegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i16_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_ISD_SIGN_EXTEND_MVT_i16_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| if ((Subtarget->is64Bit())) { |
| return fastEmitInst_r(X86::MOVSX64rr32, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v2i1_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVM2QZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v4i1_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVM2DZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v4i1_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVM2QZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v4i1_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_ISD_SIGN_EXTEND_MVT_v4i1_MVT_v4i32_r(Op0); |
| case MVT::v4i64: return fastEmit_ISD_SIGN_EXTEND_MVT_v4i1_MVT_v4i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v8i1_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVM2WZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v8i1_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVM2DZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v8i1_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VPMOVM2QZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v8i1_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i1_MVT_v8i16_r(Op0); |
| case MVT::v8i32: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i1_MVT_v8i32_r(Op0); |
| case MVT::v8i64: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i1_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v16i1_MVT_v16i8_r(unsigned Op0) { |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVM2BZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v16i1_MVT_v16i16_r(unsigned Op0) { |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVM2WZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v16i1_MVT_v16i32_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VPMOVM2DZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v16i1_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_ISD_SIGN_EXTEND_MVT_v16i1_MVT_v16i8_r(Op0); |
| case MVT::v16i16: return fastEmit_ISD_SIGN_EXTEND_MVT_v16i1_MVT_v16i16_r(Op0); |
| case MVT::v16i32: return fastEmit_ISD_SIGN_EXTEND_MVT_v16i1_MVT_v16i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v32i1_MVT_v32i8_r(unsigned Op0) { |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVM2BZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v32i1_MVT_v32i16_r(unsigned Op0) { |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPMOVM2WZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v32i1_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v32i8: return fastEmit_ISD_SIGN_EXTEND_MVT_v32i1_MVT_v32i8_r(Op0); |
| case MVT::v32i16: return fastEmit_ISD_SIGN_EXTEND_MVT_v32i1_MVT_v32i16_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v64i1_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v64i8) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPMOVM2BZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v16i8_MVT_v16i16_r(unsigned Op0) { |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPMOVSXBWYrr, &X86::VR256RegClass, Op0); |
| } |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXBWZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v16i8_MVT_v16i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVSXBDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i16: return fastEmit_ISD_SIGN_EXTEND_MVT_v16i8_MVT_v16i16_r(Op0); |
| case MVT::v16i32: return fastEmit_ISD_SIGN_EXTEND_MVT_v16i8_MVT_v16i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v32i8_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPMOVSXBWZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v8i16_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXWDYrr, &X86::VR256RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXWDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v8i16_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVSXWQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i32: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i16_MVT_v8i32_r(Op0); |
| case MVT::v8i64: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i16_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v16i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVSXWDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i64) |
| return 0; |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXDQYrr, &X86::VR256RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXDQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_v8i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVSXDQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i8: return fastEmit_ISD_SIGN_EXTEND_MVT_i8_r(RetVT, Op0); |
| case MVT::i16: return fastEmit_ISD_SIGN_EXTEND_MVT_i16_r(RetVT, Op0); |
| case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0); |
| case MVT::v2i1: return fastEmit_ISD_SIGN_EXTEND_MVT_v2i1_r(RetVT, Op0); |
| case MVT::v4i1: return fastEmit_ISD_SIGN_EXTEND_MVT_v4i1_r(RetVT, Op0); |
| case MVT::v8i1: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i1_r(RetVT, Op0); |
| case MVT::v16i1: return fastEmit_ISD_SIGN_EXTEND_MVT_v16i1_r(RetVT, Op0); |
| case MVT::v32i1: return fastEmit_ISD_SIGN_EXTEND_MVT_v32i1_r(RetVT, Op0); |
| case MVT::v64i1: return fastEmit_ISD_SIGN_EXTEND_MVT_v64i1_r(RetVT, Op0); |
| case MVT::v16i8: return fastEmit_ISD_SIGN_EXTEND_MVT_v16i8_r(RetVT, Op0); |
| case MVT::v32i8: return fastEmit_ISD_SIGN_EXTEND_MVT_v32i8_r(RetVT, Op0); |
| case MVT::v8i16: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i16_r(RetVT, Op0); |
| case MVT::v16i16: return fastEmit_ISD_SIGN_EXTEND_MVT_v16i16_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_ISD_SIGN_EXTEND_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v8i32: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i32_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::SIGN_EXTEND_VECTOR_INREG. |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasSSE41() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::PMOVSXBWrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPMOVSXBWrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXBWZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasSSE41() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::PMOVSXBDrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXBDrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXBDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXBDYrr, &X86::VR256RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXBDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasSSE41() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::PMOVSXBQrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXBQrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXBQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXBQYrr, &X86::VR256RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXBQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVSXBQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v8i16_r(Op0); |
| case MVT::v4i32: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v4i32_r(Op0); |
| case MVT::v8i32: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v8i32_r(Op0); |
| case MVT::v2i64: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v2i64_r(Op0); |
| case MVT::v4i64: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v4i64_r(Op0); |
| case MVT::v8i64: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v8i16_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasSSE41() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::PMOVSXWDrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXWDrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXWDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v8i16_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasSSE41() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::PMOVSXWQrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXWQrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXWQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v8i16_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXWQYrr, &X86::VR256RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXWQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v8i16_MVT_v4i32_r(Op0); |
| case MVT::v2i64: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v8i16_MVT_v2i64_r(Op0); |
| case MVT::v4i64: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v8i16_MVT_v4i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasSSE41() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::PMOVSXDQrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXDQrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSXDQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_r(RetVT, Op0); |
| case MVT::v8i16: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v8i16_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v4i32_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::SINT_TO_FP. |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) { |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSI2SSrr, &X86::FR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) { |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSI2SDrr, &X86::FR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0); |
| case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(unsigned Op0) { |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSI642SSrr, &X86::FR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(unsigned Op0) { |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSI642SDrr, &X86::FR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f32_r(Op0); |
| case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_MVT_f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTW2PHZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v16i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTW2PHZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v32i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTW2PHZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTDQ2PSZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTDQ2PSrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTDQ2PSrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_MVT_v4f64_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTDQ2PDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTDQ2PDYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4f32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_MVT_v4f32_r(Op0); |
| case MVT::v4f64: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_MVT_v4f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i32_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTDQ2PHZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i32_MVT_v8f32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTDQ2PSZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTDQ2PSYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i32_MVT_v8f64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTDQ2PDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_ISD_SINT_TO_FP_MVT_v8i32_MVT_v8f16_r(Op0); |
| case MVT::v8f32: return fastEmit_ISD_SINT_TO_FP_MVT_v8i32_MVT_v8f32_r(Op0); |
| case MVT::v8f64: return fastEmit_ISD_SINT_TO_FP_MVT_v8i32_MVT_v8f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v16i32_MVT_v16f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTDQ2PHZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v16i32_MVT_v16f32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTDQ2PSZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v16i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16f16: return fastEmit_ISD_SINT_TO_FP_MVT_v16i32_MVT_v16f16_r(Op0); |
| case MVT::v16f32: return fastEmit_ISD_SINT_TO_FP_MVT_v16i32_MVT_v16f32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTQQ2PDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i64_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTQQ2PSZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i64_MVT_v4f64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTQQ2PDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4f32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i64_MVT_v4f32_r(Op0); |
| case MVT::v4f64: return fastEmit_ISD_SINT_TO_FP_MVT_v4i64_MVT_v4f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i64_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTQQ2PHZrr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i64_MVT_v8f32_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTQQ2PSZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i64_MVT_v8f64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTQQ2PDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v8i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_ISD_SINT_TO_FP_MVT_v8i64_MVT_v8f16_r(Op0); |
| case MVT::v8f32: return fastEmit_ISD_SINT_TO_FP_MVT_v8i64_MVT_v8f32_r(Op0); |
| case MVT::v8f64: return fastEmit_ISD_SINT_TO_FP_MVT_v8i64_MVT_v8f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0); |
| case MVT::v8i16: return fastEmit_ISD_SINT_TO_FP_MVT_v8i16_r(RetVT, Op0); |
| case MVT::v16i16: return fastEmit_ISD_SINT_TO_FP_MVT_v16i16_r(RetVT, Op0); |
| case MVT::v32i16: return fastEmit_ISD_SINT_TO_FP_MVT_v32i16_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v8i32: return fastEmit_ISD_SINT_TO_FP_MVT_v8i32_r(RetVT, Op0); |
| case MVT::v16i32: return fastEmit_ISD_SINT_TO_FP_MVT_v16i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0); |
| case MVT::v4i64: return fastEmit_ISD_SINT_TO_FP_MVT_v4i64_r(RetVT, Op0); |
| case MVT::v8i64: return fastEmit_ISD_SINT_TO_FP_MVT_v8i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_FP_EXTEND. |
| |
| unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSS2SDrr, &X86::FR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_v8f16_MVT_v8f32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2PSXZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_v8f16_MVT_v8f64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTPH2PDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_v8f16_MVT_v8f32_r(Op0); |
| case MVT::v8f64: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_v8f16_MVT_v8f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_v16f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTPH2PSXZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2PDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2PDYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTPS2PDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(RetVT, Op0); |
| case MVT::v8f16: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v16f16: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_v16f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_v8f32_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_FP_ROUND. |
| |
| unsigned fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSD2SSrr, &X86::FR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f64: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_FP_TO_SINT. |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f16_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTSH2SIZrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f16_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTSH2SI64Zrr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f16_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f16_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2SIZrr, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTTSS2SIrr, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2SIrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2SI64Zrr, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTTSS2SI64rr, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2SI64rr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2SIZrr, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTTSD2SIrr, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2SIrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2SI64Zrr, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTTSD2SI64rr, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2SI64rr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v4f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2DQYrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f16: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f16_r(RetVT, Op0); |
| case MVT::f32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v4f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_FP_TO_UINT. |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f16_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTSH2USIZrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f16_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTSH2USI64Zrr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f16_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f16_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2USIZrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2USI64Zrr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2USIZrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2USI64Zrr, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f16: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f16_r(RetVT, Op0); |
| case MVT::f32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_FSQRT. |
| |
| unsigned fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::SQRTSSr, &X86::FR32RegClass, Op0); |
| } |
| if ((!Subtarget->hasSSE1())) { |
| return fastEmitInst_r(X86::SQRT_Fp32, &X86::RFP32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::SQRTSDr, &X86::FR64RegClass, Op0); |
| } |
| if ((!Subtarget->hasSSE2())) { |
| return fastEmitInst_r(X86::SQRT_Fp64, &X86::RFP64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSQRT_MVT_f80_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f80) |
| return 0; |
| if ((Subtarget->hasX87())) { |
| return fastEmitInst_r(X86::SQRT_Fp80, &X86::RFP80RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VSQRTPHZ128r, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v16f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VSQRTPHZ256r, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v32f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VSQRTPHZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VSQRTPSZ128r, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::SQRTPSr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VSQRTPSr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f32) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VSQRTPSZ256r, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VSQRTPSYr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VSQRTPSZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VSQRTPDZ128r, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::SQRTPDr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VSQRTPDr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v4f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f64) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VSQRTPDZ256r, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VSQRTPDYr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VSQRTPDZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(RetVT, Op0); |
| case MVT::f80: return fastEmit_ISD_STRICT_FSQRT_MVT_f80_r(RetVT, Op0); |
| case MVT::v8f16: return fastEmit_ISD_STRICT_FSQRT_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v16f16: return fastEmit_ISD_STRICT_FSQRT_MVT_v16f16_r(RetVT, Op0); |
| case MVT::v32f16: return fastEmit_ISD_STRICT_FSQRT_MVT_v32f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_STRICT_FSQRT_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_ISD_STRICT_FSQRT_MVT_v8f32_r(RetVT, Op0); |
| case MVT::v16f32: return fastEmit_ISD_STRICT_FSQRT_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_STRICT_FSQRT_MVT_v2f64_r(RetVT, Op0); |
| case MVT::v4f64: return fastEmit_ISD_STRICT_FSQRT_MVT_v4f64_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_ISD_STRICT_FSQRT_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_SINT_TO_FP. |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) { |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSI2SSrr, &X86::FR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) { |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSI2SDrr, &X86::FR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0); |
| case MVT::f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_MVT_f32_r(unsigned Op0) { |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSI642SSrr, &X86::FR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_MVT_f64_r(unsigned Op0) { |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSI642SDrr, &X86::FR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_MVT_f32_r(Op0); |
| case MVT::f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_MVT_f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTW2PHZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v16i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTW2PHZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v32i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTW2PHZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTDQ2PSZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTDQ2PSrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTDQ2PSrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_MVT_v4f64_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTDQ2PDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTDQ2PDYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_MVT_v4f32_r(Op0); |
| case MVT::v4f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_MVT_v4f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i32_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTDQ2PHZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i32_MVT_v8f32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTDQ2PSZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTDQ2PSYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i32_MVT_v8f64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTDQ2PDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i32_MVT_v8f16_r(Op0); |
| case MVT::v8f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i32_MVT_v8f32_r(Op0); |
| case MVT::v8f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i32_MVT_v8f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v16i32_MVT_v16f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTDQ2PHZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v16i32_MVT_v16f32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTDQ2PSZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v16i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16f16: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v16i32_MVT_v16f16_r(Op0); |
| case MVT::v16f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v16i32_MVT_v16f32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTQQ2PDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i64_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTQQ2PSZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i64_MVT_v4f64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTQQ2PDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i64_MVT_v4f32_r(Op0); |
| case MVT::v4f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i64_MVT_v4f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i64_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTQQ2PHZrr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i64_MVT_v8f32_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTQQ2PSZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i64_MVT_v8f64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTQQ2PDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i64_MVT_v8f16_r(Op0); |
| case MVT::v8f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i64_MVT_v8f32_r(Op0); |
| case MVT::v8f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i64_MVT_v8f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_r(RetVT, Op0); |
| case MVT::v8i16: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i16_r(RetVT, Op0); |
| case MVT::v16i16: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v16i16_r(RetVT, Op0); |
| case MVT::v32i16: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v32i16_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v8i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i32_r(RetVT, Op0); |
| case MVT::v16i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v16i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0); |
| case MVT::v4i64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i64_r(RetVT, Op0); |
| case MVT::v8i64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_UINT_TO_FP. |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUW2PHZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v16i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUW2PHZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v32i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTUW2PHZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUDQ2PSZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_MVT_v4f64_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUDQ2PDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4f32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_MVT_v4f32_r(Op0); |
| case MVT::v4f64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_MVT_v4f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v8i32_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUDQ2PHZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v8i32_MVT_v8f32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUDQ2PSZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v8i32_MVT_v8f64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTUDQ2PDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v8i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v8i32_MVT_v8f16_r(Op0); |
| case MVT::v8f32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v8i32_MVT_v8f32_r(Op0); |
| case MVT::v8f64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v8i32_MVT_v8f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v16i32_MVT_v16f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTUDQ2PHZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v16i32_MVT_v16f32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTUDQ2PSZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v16i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16f16: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v16i32_MVT_v16f16_r(Op0); |
| case MVT::v16f32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v16i32_MVT_v16f32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUQQ2PDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i64_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUQQ2PSZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i64_MVT_v4f64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUQQ2PDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4f32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i64_MVT_v4f32_r(Op0); |
| case MVT::v4f64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i64_MVT_v4f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v8i64_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTUQQ2PHZrr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v8i64_MVT_v8f32_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTUQQ2PSZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v8i64_MVT_v8f64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTUQQ2PDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v8i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v8i64_MVT_v8f16_r(Op0); |
| case MVT::v8f32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v8i64_MVT_v8f32_r(Op0); |
| case MVT::v8f64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v8i64_MVT_v8f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v8i16_r(RetVT, Op0); |
| case MVT::v16i16: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v16i16_r(RetVT, Op0); |
| case MVT::v32i16: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v32i16_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v8i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v8i32_r(RetVT, Op0); |
| case MVT::v16i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v16i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0); |
| case MVT::v4i64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i64_r(RetVT, Op0); |
| case MVT::v8i64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v8i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::TRUNCATE. |
| |
| unsigned fastEmit_ISD_TRUNCATE_MVT_i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i8) |
| return 0; |
| if ((Subtarget->is64Bit())) { |
| return fastEmitInst_extractsubreg(RetVT, Op0, X86::sub_8bit); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_TRUNCATE_MVT_i32_MVT_i8_r(unsigned Op0) { |
| if ((Subtarget->is64Bit())) { |
| return fastEmitInst_extractsubreg(MVT::i8, Op0, X86::sub_8bit); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_TRUNCATE_MVT_i32_MVT_i16_r(unsigned Op0) { |
| return fastEmitInst_extractsubreg(MVT::i16, Op0, X86::sub_16bit); |
| } |
| |
| unsigned fastEmit_ISD_TRUNCATE_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i8: return fastEmit_ISD_TRUNCATE_MVT_i32_MVT_i8_r(Op0); |
| case MVT::i16: return fastEmit_ISD_TRUNCATE_MVT_i32_MVT_i16_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_TRUNCATE_MVT_i64_MVT_i8_r(unsigned Op0) { |
| return fastEmitInst_extractsubreg(MVT::i8, Op0, X86::sub_8bit); |
| } |
| |
| unsigned fastEmit_ISD_TRUNCATE_MVT_i64_MVT_i16_r(unsigned Op0) { |
| return fastEmitInst_extractsubreg(MVT::i16, Op0, X86::sub_16bit); |
| } |
| |
| unsigned fastEmit_ISD_TRUNCATE_MVT_i64_MVT_i32_r(unsigned Op0) { |
| return fastEmitInst_extractsubreg(MVT::i32, Op0, X86::sub_32bit); |
| } |
| |
| unsigned fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i8: return fastEmit_ISD_TRUNCATE_MVT_i64_MVT_i8_r(Op0); |
| case MVT::i16: return fastEmit_ISD_TRUNCATE_MVT_i64_MVT_i16_r(Op0); |
| case MVT::i32: return fastEmit_ISD_TRUNCATE_MVT_i64_MVT_i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_TRUNCATE_MVT_v16i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVWBZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_TRUNCATE_MVT_v32i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32i8) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPMOVWBZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_TRUNCATE_MVT_v8i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i16) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVDWZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_TRUNCATE_MVT_v16i32_MVT_v16i8_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVDBZrr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_TRUNCATE_MVT_v16i32_MVT_v16i16_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVDWZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_TRUNCATE_MVT_v16i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_ISD_TRUNCATE_MVT_v16i32_MVT_v16i8_r(Op0); |
| case MVT::v16i16: return fastEmit_ISD_TRUNCATE_MVT_v16i32_MVT_v16i16_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_TRUNCATE_MVT_v4i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVQDZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_TRUNCATE_MVT_v8i64_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVQWZrr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_TRUNCATE_MVT_v8i64_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVQDZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_TRUNCATE_MVT_v8i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_ISD_TRUNCATE_MVT_v8i64_MVT_v8i16_r(Op0); |
| case MVT::v8i32: return fastEmit_ISD_TRUNCATE_MVT_v8i64_MVT_v8i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i16: return fastEmit_ISD_TRUNCATE_MVT_i16_r(RetVT, Op0); |
| case MVT::i32: return fastEmit_ISD_TRUNCATE_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0); |
| case MVT::v16i16: return fastEmit_ISD_TRUNCATE_MVT_v16i16_r(RetVT, Op0); |
| case MVT::v32i16: return fastEmit_ISD_TRUNCATE_MVT_v32i16_r(RetVT, Op0); |
| case MVT::v8i32: return fastEmit_ISD_TRUNCATE_MVT_v8i32_r(RetVT, Op0); |
| case MVT::v16i32: return fastEmit_ISD_TRUNCATE_MVT_v16i32_r(RetVT, Op0); |
| case MVT::v4i64: return fastEmit_ISD_TRUNCATE_MVT_v4i64_r(RetVT, Op0); |
| case MVT::v8i64: return fastEmit_ISD_TRUNCATE_MVT_v8i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::UINT_TO_FP. |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUW2PHZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v16i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUW2PHZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v32i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTUW2PHZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUDQ2PSZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_MVT_v4f64_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUDQ2PDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4f32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_MVT_v4f32_r(Op0); |
| case MVT::v4f64: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_MVT_v4f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i32_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUDQ2PHZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i32_MVT_v8f32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUDQ2PSZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i32_MVT_v8f64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTUDQ2PDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_ISD_UINT_TO_FP_MVT_v8i32_MVT_v8f16_r(Op0); |
| case MVT::v8f32: return fastEmit_ISD_UINT_TO_FP_MVT_v8i32_MVT_v8f32_r(Op0); |
| case MVT::v8f64: return fastEmit_ISD_UINT_TO_FP_MVT_v8i32_MVT_v8f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v16i32_MVT_v16f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTUDQ2PHZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v16i32_MVT_v16f32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTUDQ2PSZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v16i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16f16: return fastEmit_ISD_UINT_TO_FP_MVT_v16i32_MVT_v16f16_r(Op0); |
| case MVT::v16f32: return fastEmit_ISD_UINT_TO_FP_MVT_v16i32_MVT_v16f32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUQQ2PDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i64_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUQQ2PSZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i64_MVT_v4f64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUQQ2PDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4f32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i64_MVT_v4f32_r(Op0); |
| case MVT::v4f64: return fastEmit_ISD_UINT_TO_FP_MVT_v4i64_MVT_v4f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i64_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTUQQ2PHZrr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i64_MVT_v8f32_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTUQQ2PSZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i64_MVT_v8f64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTUQQ2PDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v8i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_ISD_UINT_TO_FP_MVT_v8i64_MVT_v8f16_r(Op0); |
| case MVT::v8f32: return fastEmit_ISD_UINT_TO_FP_MVT_v8i64_MVT_v8f32_r(Op0); |
| case MVT::v8f64: return fastEmit_ISD_UINT_TO_FP_MVT_v8i64_MVT_v8f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_ISD_UINT_TO_FP_MVT_v8i16_r(RetVT, Op0); |
| case MVT::v16i16: return fastEmit_ISD_UINT_TO_FP_MVT_v16i16_r(RetVT, Op0); |
| case MVT::v32i16: return fastEmit_ISD_UINT_TO_FP_MVT_v32i16_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v8i32: return fastEmit_ISD_UINT_TO_FP_MVT_v8i32_r(RetVT, Op0); |
| case MVT::v16i32: return fastEmit_ISD_UINT_TO_FP_MVT_v16i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0); |
| case MVT::v4i64: return fastEmit_ISD_UINT_TO_FP_MVT_v4i64_r(RetVT, Op0); |
| case MVT::v8i64: return fastEmit_ISD_UINT_TO_FP_MVT_v8i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::ZERO_EXTEND. |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_MVT_i8_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| return fastEmitInst_r(X86::MOVZX32rr8, &X86::GR32RegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_MVT_i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| return fastEmitInst_r(X86::MOVZX32rr16, &X86::GR32RegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v16i8_MVT_v16i16_r(unsigned Op0) { |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPMOVZXBWYrr, &X86::VR256RegClass, Op0); |
| } |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXBWZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v16i8_MVT_v16i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVZXBDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i16: return fastEmit_ISD_ZERO_EXTEND_MVT_v16i8_MVT_v16i16_r(Op0); |
| case MVT::v16i32: return fastEmit_ISD_ZERO_EXTEND_MVT_v16i8_MVT_v16i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v32i8_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPMOVZXBWZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v8i16_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXWDYrr, &X86::VR256RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXWDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v8i16_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVZXWQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i32: return fastEmit_ISD_ZERO_EXTEND_MVT_v8i16_MVT_v8i32_r(Op0); |
| case MVT::v8i64: return fastEmit_ISD_ZERO_EXTEND_MVT_v8i16_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v16i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVZXWDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i64) |
| return 0; |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXDQYrr, &X86::VR256RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXDQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_MVT_v8i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVZXDQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i8: return fastEmit_ISD_ZERO_EXTEND_MVT_i8_r(RetVT, Op0); |
| case MVT::i16: return fastEmit_ISD_ZERO_EXTEND_MVT_i16_r(RetVT, Op0); |
| case MVT::v16i8: return fastEmit_ISD_ZERO_EXTEND_MVT_v16i8_r(RetVT, Op0); |
| case MVT::v32i8: return fastEmit_ISD_ZERO_EXTEND_MVT_v32i8_r(RetVT, Op0); |
| case MVT::v8i16: return fastEmit_ISD_ZERO_EXTEND_MVT_v8i16_r(RetVT, Op0); |
| case MVT::v16i16: return fastEmit_ISD_ZERO_EXTEND_MVT_v16i16_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_ISD_ZERO_EXTEND_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v8i32: return fastEmit_ISD_ZERO_EXTEND_MVT_v8i32_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::ZERO_EXTEND_VECTOR_INREG. |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasSSE41() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::PMOVZXBWrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPMOVZXBWrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXBWZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasSSE41() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::PMOVZXBDrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXBDrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXBDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXBDYrr, &X86::VR256RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXBDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasSSE41() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::PMOVZXBQrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXBQrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXBQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXBQYrr, &X86::VR256RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXBQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVZXBQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v8i16_r(Op0); |
| case MVT::v4i32: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v4i32_r(Op0); |
| case MVT::v8i32: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v8i32_r(Op0); |
| case MVT::v2i64: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v2i64_r(Op0); |
| case MVT::v4i64: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v4i64_r(Op0); |
| case MVT::v8i64: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v8i16_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasSSE41() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::PMOVZXWDrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXWDrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXWDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v8i16_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasSSE41() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::PMOVZXWQrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXWQrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXWQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v8i16_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXWQYrr, &X86::VR256RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXWQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v8i16_MVT_v4i32_r(Op0); |
| case MVT::v2i64: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v8i16_MVT_v2i64_r(Op0); |
| case MVT::v4i64: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v8i16_MVT_v4i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasSSE41() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::PMOVZXDQrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXDQrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVZXDQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v16i8_r(RetVT, Op0); |
| case MVT::v8i16: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v8i16_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_MVT_v4i32_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::CALL. |
| |
| unsigned fastEmit_X86ISD_CALL_MVT_i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::isVoid) |
| return 0; |
| if ((!Subtarget->is64Bit())) { |
| return fastEmitInst_r(X86::CALL16r, &X86::GR16RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CALL_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::isVoid) |
| return 0; |
| if ((!Subtarget->is64Bit()) && (Subtarget->useIndirectThunkCalls())) { |
| return fastEmitInst_r(X86::INDIRECT_THUNK_CALL32, &X86::GR32RegClass, Op0); |
| } |
| if ((!Subtarget->is64Bit()) && (!Subtarget->useIndirectThunkCalls())) { |
| return fastEmitInst_r(X86::CALL32r, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CALL_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::isVoid) |
| return 0; |
| if ((Subtarget->is64Bit()) && (Subtarget->useIndirectThunkCalls())) { |
| return fastEmitInst_r(X86::INDIRECT_THUNK_CALL64, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->is64Bit()) && (!Subtarget->useIndirectThunkCalls())) { |
| return fastEmitInst_r(X86::CALL64r, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CALL_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i16: return fastEmit_X86ISD_CALL_MVT_i16_r(RetVT, Op0); |
| case MVT::i32: return fastEmit_X86ISD_CALL_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_X86ISD_CALL_MVT_i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::CONFLICT. |
| |
| unsigned fastEmit_X86ISD_CONFLICT_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasCDI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPCONFLICTDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CONFLICT_MVT_v8i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i32) |
| return 0; |
| if ((Subtarget->hasCDI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPCONFLICTDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CONFLICT_MVT_v16i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasCDI())) { |
| return fastEmitInst_r(X86::VPCONFLICTDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CONFLICT_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasCDI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPCONFLICTQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CONFLICT_MVT_v4i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i64) |
| return 0; |
| if ((Subtarget->hasCDI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPCONFLICTQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CONFLICT_MVT_v8i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i64) |
| return 0; |
| if ((Subtarget->hasCDI())) { |
| return fastEmitInst_r(X86::VPCONFLICTQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CONFLICT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_CONFLICT_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v8i32: return fastEmit_X86ISD_CONFLICT_MVT_v8i32_r(RetVT, Op0); |
| case MVT::v16i32: return fastEmit_X86ISD_CONFLICT_MVT_v16i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_CONFLICT_MVT_v2i64_r(RetVT, Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_CONFLICT_MVT_v4i64_r(RetVT, Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_CONFLICT_MVT_v8i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::CVTNEPS2BF16. |
| |
| unsigned fastEmit_X86ISD_CVTNEPS2BF16_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8bf16) |
| return 0; |
| if ((Subtarget->hasBF16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTNEPS2BF16Z128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTNEPS2BF16_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8bf16) |
| return 0; |
| if ((Subtarget->hasBF16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTNEPS2BF16Z256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTNEPS2BF16_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16bf16) |
| return 0; |
| if ((Subtarget->hasBF16())) { |
| return fastEmitInst_r(X86::VCVTNEPS2BF16Zrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTNEPS2BF16_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v4f32: return fastEmit_X86ISD_CVTNEPS2BF16_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_CVTNEPS2BF16_MVT_v8f32_r(RetVT, Op0); |
| case MVT::v16f32: return fastEmit_X86ISD_CVTNEPS2BF16_MVT_v16f32_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::CVTP2SI. |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v8f16_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2WZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v8f16_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2DQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v8f16_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2DQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v8f16_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2QQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v8f16_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2QQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v8f16_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTPH2QQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_X86ISD_CVTP2SI_MVT_v8f16_MVT_v8i16_r(Op0); |
| case MVT::v4i32: return fastEmit_X86ISD_CVTP2SI_MVT_v8f16_MVT_v4i32_r(Op0); |
| case MVT::v8i32: return fastEmit_X86ISD_CVTP2SI_MVT_v8f16_MVT_v8i32_r(Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_CVTP2SI_MVT_v8f16_MVT_v2i64_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_CVTP2SI_MVT_v8f16_MVT_v4i64_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_CVTP2SI_MVT_v8f16_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v16f16_MVT_v16i16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2WZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v16f16_MVT_v16i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTPH2DQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v16f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i16: return fastEmit_X86ISD_CVTP2SI_MVT_v16f16_MVT_v16i16_r(Op0); |
| case MVT::v16i32: return fastEmit_X86ISD_CVTP2SI_MVT_v16f16_MVT_v16i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v32f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTPH2WZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v4f32_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2DQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTPS2DQrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2DQrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v4f32_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2QQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v4f32_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2QQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_CVTP2SI_MVT_v4f32_MVT_v4i32_r(Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_CVTP2SI_MVT_v4f32_MVT_v2i64_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_CVTP2SI_MVT_v4f32_MVT_v4i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v8f32_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2DQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2DQYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v8f32_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTPS2QQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i32: return fastEmit_X86ISD_CVTP2SI_MVT_v8f32_MVT_v8i32_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_CVTP2SI_MVT_v8f32_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTPS2DQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v2f64_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2DQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTPD2DQrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2DQrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v2f64_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2QQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_CVTP2SI_MVT_v2f64_MVT_v4i32_r(Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_CVTP2SI_MVT_v2f64_MVT_v2i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v4f64_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2DQZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2DQYrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v4f64_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2QQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v4f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_CVTP2SI_MVT_v4f64_MVT_v4i32_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_CVTP2SI_MVT_v4f64_MVT_v4i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v8f64_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTPD2DQZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v8f64_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTPD2QQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i32: return fastEmit_X86ISD_CVTP2SI_MVT_v8f64_MVT_v8i32_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_CVTP2SI_MVT_v8f64_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2SI_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_CVTP2SI_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v16f16: return fastEmit_X86ISD_CVTP2SI_MVT_v16f16_r(RetVT, Op0); |
| case MVT::v32f16: return fastEmit_X86ISD_CVTP2SI_MVT_v32f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_CVTP2SI_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_CVTP2SI_MVT_v8f32_r(RetVT, Op0); |
| case MVT::v16f32: return fastEmit_X86ISD_CVTP2SI_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_CVTP2SI_MVT_v2f64_r(RetVT, Op0); |
| case MVT::v4f64: return fastEmit_X86ISD_CVTP2SI_MVT_v4f64_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_CVTP2SI_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::CVTP2UI. |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v8f16_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2UWZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v8f16_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2UDQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v8f16_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2UDQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v8f16_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2UQQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v8f16_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2UQQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v8f16_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTPH2UQQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_X86ISD_CVTP2UI_MVT_v8f16_MVT_v8i16_r(Op0); |
| case MVT::v4i32: return fastEmit_X86ISD_CVTP2UI_MVT_v8f16_MVT_v4i32_r(Op0); |
| case MVT::v8i32: return fastEmit_X86ISD_CVTP2UI_MVT_v8f16_MVT_v8i32_r(Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_CVTP2UI_MVT_v8f16_MVT_v2i64_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_CVTP2UI_MVT_v8f16_MVT_v4i64_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_CVTP2UI_MVT_v8f16_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v16f16_MVT_v16i16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2UWZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v16f16_MVT_v16i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTPH2UDQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v16f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i16: return fastEmit_X86ISD_CVTP2UI_MVT_v16f16_MVT_v16i16_r(Op0); |
| case MVT::v16i32: return fastEmit_X86ISD_CVTP2UI_MVT_v16f16_MVT_v16i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v32f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTPH2UWZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v4f32_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2UDQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v4f32_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2UQQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v4f32_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2UQQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_CVTP2UI_MVT_v4f32_MVT_v4i32_r(Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_CVTP2UI_MVT_v4f32_MVT_v2i64_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_CVTP2UI_MVT_v4f32_MVT_v4i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v8f32_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2UDQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v8f32_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTPS2UQQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i32: return fastEmit_X86ISD_CVTP2UI_MVT_v8f32_MVT_v8i32_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_CVTP2UI_MVT_v8f32_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTPS2UDQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v2f64_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2UDQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v2f64_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2UQQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_CVTP2UI_MVT_v2f64_MVT_v4i32_r(Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_CVTP2UI_MVT_v2f64_MVT_v2i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v4f64_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2UDQZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v4f64_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2UQQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v4f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_CVTP2UI_MVT_v4f64_MVT_v4i32_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_CVTP2UI_MVT_v4f64_MVT_v4i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v8f64_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTPD2UDQZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v8f64_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTPD2UQQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i32: return fastEmit_X86ISD_CVTP2UI_MVT_v8f64_MVT_v8i32_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_CVTP2UI_MVT_v8f64_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTP2UI_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_CVTP2UI_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v16f16: return fastEmit_X86ISD_CVTP2UI_MVT_v16f16_r(RetVT, Op0); |
| case MVT::v32f16: return fastEmit_X86ISD_CVTP2UI_MVT_v32f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_CVTP2UI_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_CVTP2UI_MVT_v8f32_r(RetVT, Op0); |
| case MVT::v16f32: return fastEmit_X86ISD_CVTP2UI_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_CVTP2UI_MVT_v2f64_r(RetVT, Op0); |
| case MVT::v4f64: return fastEmit_X86ISD_CVTP2UI_MVT_v4f64_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_CVTP2UI_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::CVTPH2PS. |
| |
| unsigned fastEmit_X86ISD_CVTPH2PS_MVT_v8i16_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2PSZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasF16C()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2PSrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTPH2PS_MVT_v8i16_MVT_v8f32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2PSZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasF16C()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2PSYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTPH2PS_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4f32: return fastEmit_X86ISD_CVTPH2PS_MVT_v8i16_MVT_v4f32_r(Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_CVTPH2PS_MVT_v8i16_MVT_v8f32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTPH2PS_MVT_v16i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTPH2PSZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTPH2PS_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_X86ISD_CVTPH2PS_MVT_v8i16_r(RetVT, Op0); |
| case MVT::v16i16: return fastEmit_X86ISD_CVTPH2PS_MVT_v16i16_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::CVTPH2PS_SAE. |
| |
| unsigned fastEmit_X86ISD_CVTPH2PS_SAE_MVT_v16i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTPH2PSZrrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTPH2PS_SAE_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v16i16: return fastEmit_X86ISD_CVTPH2PS_SAE_MVT_v16i16_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::CVTS2SI. |
| |
| unsigned fastEmit_X86ISD_CVTS2SI_MVT_v8f16_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTSH2SIZrr_Int, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTS2SI_MVT_v8f16_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTSH2SI64Zrr_Int, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTS2SI_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_CVTS2SI_MVT_v8f16_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_X86ISD_CVTS2SI_MVT_v8f16_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTS2SI_MVT_v4f32_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSS2SIZrr_Int, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSS2SIrr_Int, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSS2SIrr_Int, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTS2SI_MVT_v4f32_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSS2SI64Zrr_Int, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSS2SI64rr_Int, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSS2SI64rr_Int, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTS2SI_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_CVTS2SI_MVT_v4f32_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_X86ISD_CVTS2SI_MVT_v4f32_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTS2SI_MVT_v2f64_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSD2SIZrr_Int, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSD2SIrr_Int, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSD2SIrr_Int, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTS2SI_MVT_v2f64_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSD2SI64Zrr_Int, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTSD2SI64rr_Int, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSD2SI64rr_Int, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTS2SI_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_CVTS2SI_MVT_v2f64_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_X86ISD_CVTS2SI_MVT_v2f64_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTS2SI_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_CVTS2SI_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_CVTS2SI_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_CVTS2SI_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::CVTS2UI. |
| |
| unsigned fastEmit_X86ISD_CVTS2UI_MVT_v8f16_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTSH2USIZrr_Int, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTS2UI_MVT_v8f16_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTSH2USI64Zrr_Int, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTS2UI_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_CVTS2UI_MVT_v8f16_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_X86ISD_CVTS2UI_MVT_v8f16_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTS2UI_MVT_v4f32_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSS2USIZrr_Int, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTS2UI_MVT_v4f32_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSS2USI64Zrr_Int, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTS2UI_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_CVTS2UI_MVT_v4f32_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_X86ISD_CVTS2UI_MVT_v4f32_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTS2UI_MVT_v2f64_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSD2USIZrr_Int, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTS2UI_MVT_v2f64_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTSD2USI64Zrr_Int, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTS2UI_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_CVTS2UI_MVT_v2f64_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_X86ISD_CVTS2UI_MVT_v2f64_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTS2UI_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_CVTS2UI_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_CVTS2UI_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_CVTS2UI_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::CVTSI2P. |
| |
| unsigned fastEmit_X86ISD_CVTSI2P_MVT_v4i32_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTDQ2PHZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTSI2P_MVT_v4i32_MVT_v2f64_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTDQ2PDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTDQ2PDrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTDQ2PDrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTSI2P_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_CVTSI2P_MVT_v4i32_MVT_v8f16_r(Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_CVTSI2P_MVT_v4i32_MVT_v2f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTSI2P_MVT_v2i64_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTQQ2PHZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTSI2P_MVT_v2i64_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTQQ2PSZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTSI2P_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_CVTSI2P_MVT_v2i64_MVT_v8f16_r(Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_CVTSI2P_MVT_v2i64_MVT_v4f32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTSI2P_MVT_v4i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTQQ2PHZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTSI2P_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_CVTSI2P_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_CVTSI2P_MVT_v2i64_r(RetVT, Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_CVTSI2P_MVT_v4i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::CVTTP2SI. |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v8f16_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2WZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v8f16_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2DQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v8f16_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2DQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v8f16_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2QQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v8f16_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2QQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v8f16_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTPH2QQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_X86ISD_CVTTP2SI_MVT_v8f16_MVT_v8i16_r(Op0); |
| case MVT::v4i32: return fastEmit_X86ISD_CVTTP2SI_MVT_v8f16_MVT_v4i32_r(Op0); |
| case MVT::v8i32: return fastEmit_X86ISD_CVTTP2SI_MVT_v8f16_MVT_v8i32_r(Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_CVTTP2SI_MVT_v8f16_MVT_v2i64_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_CVTTP2SI_MVT_v8f16_MVT_v4i64_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_CVTTP2SI_MVT_v8f16_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v16f16_MVT_v16i16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2WZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v16f16_MVT_v16i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTPH2DQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v16f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i16: return fastEmit_X86ISD_CVTTP2SI_MVT_v16f16_MVT_v16i16_r(Op0); |
| case MVT::v16i32: return fastEmit_X86ISD_CVTTP2SI_MVT_v16f16_MVT_v16i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v32f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTPH2WZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v4f32_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPS2DQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTTPS2DQrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPS2DQrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v4f32_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPS2QQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v4f32_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPS2QQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_CVTTP2SI_MVT_v4f32_MVT_v4i32_r(Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_CVTTP2SI_MVT_v4f32_MVT_v2i64_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_CVTTP2SI_MVT_v4f32_MVT_v4i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v8f32_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPS2DQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPS2DQYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v8f32_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTTPS2QQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i32: return fastEmit_X86ISD_CVTTP2SI_MVT_v8f32_MVT_v8i32_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_CVTTP2SI_MVT_v8f32_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTPS2DQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v2f64_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2DQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTTPD2DQrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2DQrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v2f64_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2QQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_CVTTP2SI_MVT_v2f64_MVT_v4i32_r(Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_CVTTP2SI_MVT_v2f64_MVT_v2i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v4f64_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2DQZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2DQYrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v4f64_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2QQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v4f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_CVTTP2SI_MVT_v4f64_MVT_v4i32_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_CVTTP2SI_MVT_v4f64_MVT_v4i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v8f64_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTPD2DQZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v8f64_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTTPD2QQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i32: return fastEmit_X86ISD_CVTTP2SI_MVT_v8f64_MVT_v8i32_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_CVTTP2SI_MVT_v8f64_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_CVTTP2SI_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v16f16: return fastEmit_X86ISD_CVTTP2SI_MVT_v16f16_r(RetVT, Op0); |
| case MVT::v32f16: return fastEmit_X86ISD_CVTTP2SI_MVT_v32f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_CVTTP2SI_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_CVTTP2SI_MVT_v8f32_r(RetVT, Op0); |
| case MVT::v16f32: return fastEmit_X86ISD_CVTTP2SI_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_CVTTP2SI_MVT_v2f64_r(RetVT, Op0); |
| case MVT::v4f64: return fastEmit_X86ISD_CVTTP2SI_MVT_v4f64_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_CVTTP2SI_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::CVTTP2SI_SAE. |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_SAE_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i64) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTPH2QQZrrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_SAE_MVT_v16f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTPH2DQZrrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_SAE_MVT_v32f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTPH2WZrrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_SAE_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i64) |
| return 0; |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTTPS2QQZrrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_SAE_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTPS2DQZrrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_SAE_MVT_v8f64_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTPD2DQZrrb, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_SAE_MVT_v8f64_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTTPD2QQZrrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_SAE_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i32: return fastEmit_X86ISD_CVTTP2SI_SAE_MVT_v8f64_MVT_v8i32_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_CVTTP2SI_SAE_MVT_v8f64_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2SI_SAE_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_CVTTP2SI_SAE_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v16f16: return fastEmit_X86ISD_CVTTP2SI_SAE_MVT_v16f16_r(RetVT, Op0); |
| case MVT::v32f16: return fastEmit_X86ISD_CVTTP2SI_SAE_MVT_v32f16_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_CVTTP2SI_SAE_MVT_v8f32_r(RetVT, Op0); |
| case MVT::v16f32: return fastEmit_X86ISD_CVTTP2SI_SAE_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_CVTTP2SI_SAE_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::CVTTP2UI. |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v8f16_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2UWZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v8f16_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2UDQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v8f16_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2UDQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v8f16_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2UQQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v8f16_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2UQQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v8f16_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTPH2UQQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_X86ISD_CVTTP2UI_MVT_v8f16_MVT_v8i16_r(Op0); |
| case MVT::v4i32: return fastEmit_X86ISD_CVTTP2UI_MVT_v8f16_MVT_v4i32_r(Op0); |
| case MVT::v8i32: return fastEmit_X86ISD_CVTTP2UI_MVT_v8f16_MVT_v8i32_r(Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_CVTTP2UI_MVT_v8f16_MVT_v2i64_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_CVTTP2UI_MVT_v8f16_MVT_v4i64_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_CVTTP2UI_MVT_v8f16_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v16f16_MVT_v16i16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2UWZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v16f16_MVT_v16i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTPH2UDQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v16f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i16: return fastEmit_X86ISD_CVTTP2UI_MVT_v16f16_MVT_v16i16_r(Op0); |
| case MVT::v16i32: return fastEmit_X86ISD_CVTTP2UI_MVT_v16f16_MVT_v16i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v32f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTPH2UWZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v4f32_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPS2UDQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v4f32_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPS2UQQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v4f32_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPS2UQQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_CVTTP2UI_MVT_v4f32_MVT_v4i32_r(Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_CVTTP2UI_MVT_v4f32_MVT_v2i64_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_CVTTP2UI_MVT_v4f32_MVT_v4i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v8f32_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPS2UDQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v8f32_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTTPS2UQQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i32: return fastEmit_X86ISD_CVTTP2UI_MVT_v8f32_MVT_v8i32_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_CVTTP2UI_MVT_v8f32_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTPS2UDQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v2f64_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2UDQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v2f64_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2UQQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_CVTTP2UI_MVT_v2f64_MVT_v4i32_r(Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_CVTTP2UI_MVT_v2f64_MVT_v2i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v4f64_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2UDQZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v4f64_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2UQQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v4f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_CVTTP2UI_MVT_v4f64_MVT_v4i32_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_CVTTP2UI_MVT_v4f64_MVT_v4i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v8f64_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTPD2UDQZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v8f64_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTTPD2UQQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i32: return fastEmit_X86ISD_CVTTP2UI_MVT_v8f64_MVT_v8i32_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_CVTTP2UI_MVT_v8f64_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_CVTTP2UI_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v16f16: return fastEmit_X86ISD_CVTTP2UI_MVT_v16f16_r(RetVT, Op0); |
| case MVT::v32f16: return fastEmit_X86ISD_CVTTP2UI_MVT_v32f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_CVTTP2UI_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_CVTTP2UI_MVT_v8f32_r(RetVT, Op0); |
| case MVT::v16f32: return fastEmit_X86ISD_CVTTP2UI_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_CVTTP2UI_MVT_v2f64_r(RetVT, Op0); |
| case MVT::v4f64: return fastEmit_X86ISD_CVTTP2UI_MVT_v4f64_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_CVTTP2UI_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::CVTTP2UI_SAE. |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_SAE_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i64) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTPH2UQQZrrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_SAE_MVT_v16f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTPH2UDQZrrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_SAE_MVT_v32f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTPH2UWZrrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_SAE_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i64) |
| return 0; |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTTPS2UQQZrrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_SAE_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTPS2UDQZrrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_SAE_MVT_v8f64_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTPD2UDQZrrb, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_SAE_MVT_v8f64_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTTPD2UQQZrrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_SAE_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i32: return fastEmit_X86ISD_CVTTP2UI_SAE_MVT_v8f64_MVT_v8i32_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_CVTTP2UI_SAE_MVT_v8f64_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTP2UI_SAE_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_CVTTP2UI_SAE_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v16f16: return fastEmit_X86ISD_CVTTP2UI_SAE_MVT_v16f16_r(RetVT, Op0); |
| case MVT::v32f16: return fastEmit_X86ISD_CVTTP2UI_SAE_MVT_v32f16_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_CVTTP2UI_SAE_MVT_v8f32_r(RetVT, Op0); |
| case MVT::v16f32: return fastEmit_X86ISD_CVTTP2UI_SAE_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_CVTTP2UI_SAE_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::CVTTS2SI. |
| |
| unsigned fastEmit_X86ISD_CVTTS2SI_MVT_v8f16_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTSH2SIZrr_Int, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2SI_MVT_v8f16_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTSH2SI64Zrr_Int, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2SI_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_CVTTS2SI_MVT_v8f16_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_X86ISD_CVTTS2SI_MVT_v8f16_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2SI_MVT_v4f32_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2SIZrr_Int, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTTSS2SIrr_Int, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2SIrr_Int, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2SI_MVT_v4f32_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2SI64Zrr_Int, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTTSS2SI64rr_Int, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2SI64rr_Int, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2SI_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_CVTTS2SI_MVT_v4f32_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_X86ISD_CVTTS2SI_MVT_v4f32_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2SI_MVT_v2f64_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2SIZrr_Int, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTTSD2SIrr_Int, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2SIrr_Int, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2SI_MVT_v2f64_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2SI64Zrr_Int, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTTSD2SI64rr_Int, &X86::GR64RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2SI64rr_Int, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2SI_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_CVTTS2SI_MVT_v2f64_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_X86ISD_CVTTS2SI_MVT_v2f64_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2SI_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_CVTTS2SI_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_CVTTS2SI_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_CVTTS2SI_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::CVTTS2SI_SAE. |
| |
| unsigned fastEmit_X86ISD_CVTTS2SI_SAE_MVT_v8f16_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTSH2SIZrrb_Int, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2SI_SAE_MVT_v8f16_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTSH2SI64Zrrb_Int, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2SI_SAE_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_CVTTS2SI_SAE_MVT_v8f16_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_X86ISD_CVTTS2SI_SAE_MVT_v8f16_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2SI_SAE_MVT_v4f32_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2SIZrrb_Int, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2SI_SAE_MVT_v4f32_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2SI64Zrrb_Int, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2SI_SAE_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_CVTTS2SI_SAE_MVT_v4f32_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_X86ISD_CVTTS2SI_SAE_MVT_v4f32_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2SI_SAE_MVT_v2f64_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2SIZrrb_Int, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2SI_SAE_MVT_v2f64_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2SI64Zrrb_Int, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2SI_SAE_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_CVTTS2SI_SAE_MVT_v2f64_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_X86ISD_CVTTS2SI_SAE_MVT_v2f64_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2SI_SAE_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_CVTTS2SI_SAE_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_CVTTS2SI_SAE_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_CVTTS2SI_SAE_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::CVTTS2UI. |
| |
| unsigned fastEmit_X86ISD_CVTTS2UI_MVT_v8f16_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTSH2USIZrr_Int, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2UI_MVT_v8f16_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTSH2USI64Zrr_Int, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2UI_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_CVTTS2UI_MVT_v8f16_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_X86ISD_CVTTS2UI_MVT_v8f16_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2UI_MVT_v4f32_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2USIZrr_Int, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2UI_MVT_v4f32_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2USI64Zrr_Int, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2UI_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_CVTTS2UI_MVT_v4f32_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_X86ISD_CVTTS2UI_MVT_v4f32_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2UI_MVT_v2f64_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2USIZrr_Int, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2UI_MVT_v2f64_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2USI64Zrr_Int, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2UI_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_CVTTS2UI_MVT_v2f64_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_X86ISD_CVTTS2UI_MVT_v2f64_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2UI_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_CVTTS2UI_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_CVTTS2UI_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_CVTTS2UI_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::CVTTS2UI_SAE. |
| |
| unsigned fastEmit_X86ISD_CVTTS2UI_SAE_MVT_v8f16_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTSH2USIZrrb_Int, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2UI_SAE_MVT_v8f16_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTSH2USI64Zrrb_Int, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2UI_SAE_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_CVTTS2UI_SAE_MVT_v8f16_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_X86ISD_CVTTS2UI_SAE_MVT_v8f16_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2UI_SAE_MVT_v4f32_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2USIZrrb_Int, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2UI_SAE_MVT_v4f32_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSS2USI64Zrrb_Int, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2UI_SAE_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_CVTTS2UI_SAE_MVT_v4f32_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_X86ISD_CVTTS2UI_SAE_MVT_v4f32_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2UI_SAE_MVT_v2f64_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2USIZrrb_Int, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2UI_SAE_MVT_v2f64_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTSD2USI64Zrrb_Int, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2UI_SAE_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_CVTTS2UI_SAE_MVT_v2f64_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_X86ISD_CVTTS2UI_SAE_MVT_v2f64_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTTS2UI_SAE_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_CVTTS2UI_SAE_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_CVTTS2UI_SAE_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_CVTTS2UI_SAE_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::CVTUI2P. |
| |
| unsigned fastEmit_X86ISD_CVTUI2P_MVT_v4i32_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUDQ2PHZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTUI2P_MVT_v4i32_MVT_v2f64_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUDQ2PDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTUI2P_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_CVTUI2P_MVT_v4i32_MVT_v8f16_r(Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_CVTUI2P_MVT_v4i32_MVT_v2f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTUI2P_MVT_v2i64_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUQQ2PHZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTUI2P_MVT_v2i64_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUQQ2PSZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTUI2P_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_CVTUI2P_MVT_v2i64_MVT_v8f16_r(Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_CVTUI2P_MVT_v2i64_MVT_v4f32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_CVTUI2P_MVT_v4i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUQQ2PHZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_CVTUI2P_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_CVTUI2P_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_CVTUI2P_MVT_v2i64_r(RetVT, Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_CVTUI2P_MVT_v4i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::DYN_ALLOCA. |
| |
| unsigned fastEmit_X86ISD_DYN_ALLOCA_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::isVoid) |
| return 0; |
| if ((!Subtarget->isTarget64BitLP64())) { |
| return fastEmitInst_r(X86::DYN_ALLOCA_32, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_DYN_ALLOCA_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::isVoid) |
| return 0; |
| if ((Subtarget->is64Bit())) { |
| return fastEmitInst_r(X86::DYN_ALLOCA_64, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_DYN_ALLOCA_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_DYN_ALLOCA_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_X86ISD_DYN_ALLOCA_MVT_i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::EH_RETURN. |
| |
| unsigned fastEmit_X86ISD_EH_RETURN_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::isVoid) |
| return 0; |
| return fastEmitInst_r(X86::EH_RETURN, &X86::GR32RegClass, Op0); |
| } |
| |
| unsigned fastEmit_X86ISD_EH_RETURN_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::isVoid) |
| return 0; |
| return fastEmitInst_r(X86::EH_RETURN64, &X86::GR64RegClass, Op0); |
| } |
| |
| unsigned fastEmit_X86ISD_EH_RETURN_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_EH_RETURN_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_X86ISD_EH_RETURN_MVT_i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::EXP2. |
| |
| unsigned fastEmit_X86ISD_EXP2_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasERI())) { |
| return fastEmitInst_r(X86::VEXP2PSZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_EXP2_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasERI())) { |
| return fastEmitInst_r(X86::VEXP2PDZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_EXP2_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v16f32: return fastEmit_X86ISD_EXP2_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_EXP2_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::EXP2_SAE. |
| |
| unsigned fastEmit_X86ISD_EXP2_SAE_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasERI())) { |
| return fastEmitInst_r(X86::VEXP2PSZrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_EXP2_SAE_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasERI())) { |
| return fastEmitInst_r(X86::VEXP2PDZrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_EXP2_SAE_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v16f32: return fastEmit_X86ISD_EXP2_SAE_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_EXP2_SAE_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::FGETEXP. |
| |
| unsigned fastEmit_X86ISD_FGETEXP_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VGETEXPPHZ128r, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_FGETEXP_MVT_v16f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VGETEXPPHZ256r, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_FGETEXP_MVT_v32f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VGETEXPPHZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_FGETEXP_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VGETEXPPSZ128r, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_FGETEXP_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f32) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VGETEXPPSZ256r, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_FGETEXP_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VGETEXPPSZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_FGETEXP_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VGETEXPPDZ128r, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_FGETEXP_MVT_v4f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f64) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VGETEXPPDZ256r, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_FGETEXP_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VGETEXPPDZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_FGETEXP_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_FGETEXP_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v16f16: return fastEmit_X86ISD_FGETEXP_MVT_v16f16_r(RetVT, Op0); |
| case MVT::v32f16: return fastEmit_X86ISD_FGETEXP_MVT_v32f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_FGETEXP_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_FGETEXP_MVT_v8f32_r(RetVT, Op0); |
| case MVT::v16f32: return fastEmit_X86ISD_FGETEXP_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_FGETEXP_MVT_v2f64_r(RetVT, Op0); |
| case MVT::v4f64: return fastEmit_X86ISD_FGETEXP_MVT_v4f64_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_FGETEXP_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::FGETEXP_SAE. |
| |
| unsigned fastEmit_X86ISD_FGETEXP_SAE_MVT_v32f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VGETEXPPHZrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_FGETEXP_SAE_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VGETEXPPSZrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_FGETEXP_SAE_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VGETEXPPDZrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_FGETEXP_SAE_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v32f16: return fastEmit_X86ISD_FGETEXP_SAE_MVT_v32f16_r(RetVT, Op0); |
| case MVT::v16f32: return fastEmit_X86ISD_FGETEXP_SAE_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_FGETEXP_SAE_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::FRCP. |
| |
| unsigned fastEmit_X86ISD_FRCP_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::RCPSSr, &X86::FR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_FRCP_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::RCPPSr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::VRCPPSr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_FRCP_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f32) |
| return 0; |
| if ((Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::VRCPPSYr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_FRCP_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_X86ISD_FRCP_MVT_f32_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_FRCP_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_FRCP_MVT_v8f32_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::FRSQRT. |
| |
| unsigned fastEmit_X86ISD_FRSQRT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::RSQRTSSr, &X86::FR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_FRSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::RSQRTPSr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::VRSQRTPSr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_FRSQRT_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f32) |
| return 0; |
| if ((Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::VRSQRTPSYr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_FRSQRT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_X86ISD_FRSQRT_MVT_f32_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_FRSQRT_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_FRSQRT_MVT_v8f32_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::MMX_MOVD2W. |
| |
| unsigned fastEmit_X86ISD_MMX_MOVD2W_MVT_x86mmx_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasMMX())) { |
| return fastEmitInst_r(X86::MMX_MOVD64grr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MMX_MOVD2W_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::x86mmx: return fastEmit_X86ISD_MMX_MOVD2W_MVT_x86mmx_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::MMX_MOVW2D. |
| |
| unsigned fastEmit_X86ISD_MMX_MOVW2D_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::x86mmx) |
| return 0; |
| if ((Subtarget->hasMMX())) { |
| return fastEmitInst_r(X86::MMX_MOVD64rr, &X86::VR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MMX_MOVW2D_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_MMX_MOVW2D_MVT_i32_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::MOVDDUP. |
| |
| unsigned fastEmit_X86ISD_MOVDDUP_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasSSE3() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::MOVDDUPrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VMOVDDUPrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVDDUP_MVT_v4f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VMOVDDUPZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VMOVDDUPYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVDDUP_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VMOVDDUPZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVDDUP_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v2f64: return fastEmit_X86ISD_MOVDDUP_MVT_v2f64_r(RetVT, Op0); |
| case MVT::v4f64: return fastEmit_X86ISD_MOVDDUP_MVT_v4f64_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_MOVDDUP_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::MOVDQ2Q. |
| |
| unsigned fastEmit_X86ISD_MOVDQ2Q_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::x86mmx) |
| return 0; |
| if ((Subtarget->hasMMX()) && (Subtarget->hasSSE2())) { |
| return fastEmitInst_r(X86::MMX_MOVDQ2Qrr, &X86::VR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVDQ2Q_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v2i64: return fastEmit_X86ISD_MOVDQ2Q_MVT_v2i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::MOVMSK. |
| |
| unsigned fastEmit_X86ISD_MOVMSK_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::PMOVMSKBrr, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::VPMOVMSKBrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVMSK_MVT_v32i8_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasAVX2())) { |
| return fastEmitInst_r(X86::VPMOVMSKBYrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVMSK_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::MOVMSKPSrr, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::VMOVMSKPSrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVMSK_MVT_v8i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::VMOVMSKPSYrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVMSK_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::MOVMSKPDrr, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::VMOVMSKPDrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVMSK_MVT_v4i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::VMOVMSKPDYrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVMSK_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::MOVMSKPSrr, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::VMOVMSKPSrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVMSK_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::VMOVMSKPSYrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVMSK_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::MOVMSKPDrr, &X86::GR32RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::VMOVMSKPDrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVMSK_MVT_v4f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::VMOVMSKPDYrr, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVMSK_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_X86ISD_MOVMSK_MVT_v16i8_r(RetVT, Op0); |
| case MVT::v32i8: return fastEmit_X86ISD_MOVMSK_MVT_v32i8_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_X86ISD_MOVMSK_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v8i32: return fastEmit_X86ISD_MOVMSK_MVT_v8i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_MOVMSK_MVT_v2i64_r(RetVT, Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_MOVMSK_MVT_v4i64_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_MOVMSK_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_MOVMSK_MVT_v8f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_MOVMSK_MVT_v2f64_r(RetVT, Op0); |
| case MVT::v4f64: return fastEmit_X86ISD_MOVMSK_MVT_v4f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::MOVQ2DQ. |
| |
| unsigned fastEmit_X86ISD_MOVQ2DQ_MVT_x86mmx_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasMMX()) && (Subtarget->hasSSE2())) { |
| return fastEmitInst_r(X86::MMX_MOVQ2DQrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVQ2DQ_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::x86mmx: return fastEmit_X86ISD_MOVQ2DQ_MVT_x86mmx_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::MOVSHDUP. |
| |
| unsigned fastEmit_X86ISD_MOVSHDUP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasSSE3() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::MOVSHDUPrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VMOVSHDUPrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVSHDUP_MVT_v8i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i32) |
| return 0; |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VMOVSHDUPYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVSHDUP_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VMOVSHDUPZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE3() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::MOVSHDUPrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VMOVSHDUPrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVSHDUP_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VMOVSHDUPZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VMOVSHDUPYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVSHDUP_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VMOVSHDUPZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVSHDUP_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_MOVSHDUP_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v8i32: return fastEmit_X86ISD_MOVSHDUP_MVT_v8i32_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_MOVSHDUP_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_MOVSHDUP_MVT_v8f32_r(RetVT, Op0); |
| case MVT::v16f32: return fastEmit_X86ISD_MOVSHDUP_MVT_v16f32_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::MOVSLDUP. |
| |
| unsigned fastEmit_X86ISD_MOVSLDUP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasSSE3() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::MOVSLDUPrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VMOVSLDUPrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVSLDUP_MVT_v8i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i32) |
| return 0; |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VMOVSLDUPYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVSLDUP_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VMOVSLDUPZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE3() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::MOVSLDUPrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VMOVSLDUPrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVSLDUP_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VMOVSLDUPZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VMOVSLDUPYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVSLDUP_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VMOVSLDUPZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_MOVSLDUP_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_MOVSLDUP_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v8i32: return fastEmit_X86ISD_MOVSLDUP_MVT_v8i32_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_MOVSLDUP_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_MOVSLDUP_MVT_v8f32_r(RetVT, Op0); |
| case MVT::v16f32: return fastEmit_X86ISD_MOVSLDUP_MVT_v16f32_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::NT_BRIND. |
| |
| unsigned fastEmit_X86ISD_NT_BRIND_MVT_i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::isVoid) |
| return 0; |
| if ((!Subtarget->is64Bit())) { |
| return fastEmitInst_r(X86::JMP16r_NT, &X86::GR16RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_NT_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::isVoid) |
| return 0; |
| if ((!Subtarget->is64Bit())) { |
| return fastEmitInst_r(X86::JMP32r_NT, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_NT_BRIND_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::isVoid) |
| return 0; |
| if ((Subtarget->is64Bit())) { |
| return fastEmitInst_r(X86::JMP64r_NT, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_NT_BRIND_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i16: return fastEmit_X86ISD_NT_BRIND_MVT_i16_r(RetVT, Op0); |
| case MVT::i32: return fastEmit_X86ISD_NT_BRIND_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_X86ISD_NT_BRIND_MVT_i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::NT_CALL. |
| |
| unsigned fastEmit_X86ISD_NT_CALL_MVT_i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::isVoid) |
| return 0; |
| if ((!Subtarget->is64Bit())) { |
| return fastEmitInst_r(X86::CALL16r_NT, &X86::GR16RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_NT_CALL_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::isVoid) |
| return 0; |
| if ((!Subtarget->is64Bit())) { |
| return fastEmitInst_r(X86::CALL32r_NT, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_NT_CALL_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::isVoid) |
| return 0; |
| if ((Subtarget->is64Bit())) { |
| return fastEmitInst_r(X86::CALL64r_NT, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_NT_CALL_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i16: return fastEmit_X86ISD_NT_CALL_MVT_i16_r(RetVT, Op0); |
| case MVT::i32: return fastEmit_X86ISD_NT_CALL_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_X86ISD_NT_CALL_MVT_i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::PHMINPOS. |
| |
| unsigned fastEmit_X86ISD_PHMINPOS_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i16) |
| return 0; |
| if ((Subtarget->hasSSE41() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::PHMINPOSUWrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::VPHMINPOSUWrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_PHMINPOS_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_X86ISD_PHMINPOS_MVT_v8i16_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::PROBED_ALLOCA. |
| |
| unsigned fastEmit_X86ISD_PROBED_ALLOCA_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((!Subtarget->isTarget64BitLP64())) { |
| return fastEmitInst_r(X86::PROBED_ALLOCA_32, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_PROBED_ALLOCA_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| if ((Subtarget->is64Bit())) { |
| return fastEmitInst_r(X86::PROBED_ALLOCA_64, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_PROBED_ALLOCA_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_PROBED_ALLOCA_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_X86ISD_PROBED_ALLOCA_MVT_i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::RCP14. |
| |
| unsigned fastEmit_X86ISD_RCP14_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VRCPPHZ128r, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RCP14_MVT_v16f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VRCPPHZ256r, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RCP14_MVT_v32f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VRCPPHZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RCP14_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VRCP14PSZ128r, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RCP14_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f32) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VRCP14PSZ256r, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RCP14_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VRCP14PSZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RCP14_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VRCP14PDZ128r, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RCP14_MVT_v4f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f64) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VRCP14PDZ256r, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RCP14_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VRCP14PDZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RCP14_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_RCP14_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v16f16: return fastEmit_X86ISD_RCP14_MVT_v16f16_r(RetVT, Op0); |
| case MVT::v32f16: return fastEmit_X86ISD_RCP14_MVT_v32f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_RCP14_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_RCP14_MVT_v8f32_r(RetVT, Op0); |
| case MVT::v16f32: return fastEmit_X86ISD_RCP14_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_RCP14_MVT_v2f64_r(RetVT, Op0); |
| case MVT::v4f64: return fastEmit_X86ISD_RCP14_MVT_v4f64_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_RCP14_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::RCP28. |
| |
| unsigned fastEmit_X86ISD_RCP28_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasERI())) { |
| return fastEmitInst_r(X86::VRCP28PSZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RCP28_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasERI())) { |
| return fastEmitInst_r(X86::VRCP28PDZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RCP28_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v16f32: return fastEmit_X86ISD_RCP28_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_RCP28_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::RCP28_SAE. |
| |
| unsigned fastEmit_X86ISD_RCP28_SAE_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasERI())) { |
| return fastEmitInst_r(X86::VRCP28PSZrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RCP28_SAE_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasERI())) { |
| return fastEmitInst_r(X86::VRCP28PDZrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RCP28_SAE_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v16f32: return fastEmit_X86ISD_RCP28_SAE_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_RCP28_SAE_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::RSQRT14. |
| |
| unsigned fastEmit_X86ISD_RSQRT14_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VRSQRTPHZ128r, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RSQRT14_MVT_v16f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VRSQRTPHZ256r, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RSQRT14_MVT_v32f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VRSQRTPHZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RSQRT14_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VRSQRT14PSZ128r, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RSQRT14_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f32) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VRSQRT14PSZ256r, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RSQRT14_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VRSQRT14PSZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RSQRT14_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VRSQRT14PDZ128r, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RSQRT14_MVT_v4f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f64) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VRSQRT14PDZ256r, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RSQRT14_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VRSQRT14PDZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RSQRT14_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_RSQRT14_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v16f16: return fastEmit_X86ISD_RSQRT14_MVT_v16f16_r(RetVT, Op0); |
| case MVT::v32f16: return fastEmit_X86ISD_RSQRT14_MVT_v32f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_RSQRT14_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_RSQRT14_MVT_v8f32_r(RetVT, Op0); |
| case MVT::v16f32: return fastEmit_X86ISD_RSQRT14_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_RSQRT14_MVT_v2f64_r(RetVT, Op0); |
| case MVT::v4f64: return fastEmit_X86ISD_RSQRT14_MVT_v4f64_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_RSQRT14_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::RSQRT28. |
| |
| unsigned fastEmit_X86ISD_RSQRT28_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasERI())) { |
| return fastEmitInst_r(X86::VRSQRT28PSZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RSQRT28_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasERI())) { |
| return fastEmitInst_r(X86::VRSQRT28PDZr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RSQRT28_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v16f32: return fastEmit_X86ISD_RSQRT28_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_RSQRT28_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::RSQRT28_SAE. |
| |
| unsigned fastEmit_X86ISD_RSQRT28_SAE_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasERI())) { |
| return fastEmitInst_r(X86::VRSQRT28PSZrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RSQRT28_SAE_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasERI())) { |
| return fastEmitInst_r(X86::VRSQRT28PDZrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_RSQRT28_SAE_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v16f32: return fastEmit_X86ISD_RSQRT28_SAE_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_RSQRT28_SAE_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::SEG_ALLOCA. |
| |
| unsigned fastEmit_X86ISD_SEG_ALLOCA_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((!Subtarget->isTarget64BitLP64())) { |
| return fastEmitInst_r(X86::SEG_ALLOCA_32, &X86::GR32RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_SEG_ALLOCA_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| if ((Subtarget->is64Bit())) { |
| return fastEmitInst_r(X86::SEG_ALLOCA_64, &X86::GR64RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_SEG_ALLOCA_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_SEG_ALLOCA_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_X86ISD_SEG_ALLOCA_MVT_i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::STRICT_CVTPH2PS. |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTPH2PS_MVT_v8i16_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2PSZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasF16C()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2PSrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTPH2PS_MVT_v8i16_MVT_v8f32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2PSZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasF16C()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2PSYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTPH2PS_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4f32: return fastEmit_X86ISD_STRICT_CVTPH2PS_MVT_v8i16_MVT_v4f32_r(Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_STRICT_CVTPH2PS_MVT_v8i16_MVT_v8f32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTPH2PS_MVT_v16i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTPH2PSZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTPH2PS_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_X86ISD_STRICT_CVTPH2PS_MVT_v8i16_r(RetVT, Op0); |
| case MVT::v16i16: return fastEmit_X86ISD_STRICT_CVTPH2PS_MVT_v16i16_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::STRICT_CVTSI2P. |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTSI2P_MVT_v4i32_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTDQ2PHZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTSI2P_MVT_v4i32_MVT_v2f64_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTDQ2PDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTDQ2PDrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTDQ2PDrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTSI2P_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_STRICT_CVTSI2P_MVT_v4i32_MVT_v8f16_r(Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_STRICT_CVTSI2P_MVT_v4i32_MVT_v2f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTSI2P_MVT_v2i64_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTQQ2PHZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTSI2P_MVT_v2i64_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTQQ2PSZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTSI2P_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_STRICT_CVTSI2P_MVT_v2i64_MVT_v8f16_r(Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_STRICT_CVTSI2P_MVT_v2i64_MVT_v4f32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTSI2P_MVT_v4i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTQQ2PHZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTSI2P_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_STRICT_CVTSI2P_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_STRICT_CVTSI2P_MVT_v2i64_r(RetVT, Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_STRICT_CVTSI2P_MVT_v4i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::STRICT_CVTTP2SI. |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f16_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2WZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f16_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2DQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f16_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2DQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f16_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2QQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f16_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2QQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f16_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTPH2QQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f16_MVT_v8i16_r(Op0); |
| case MVT::v4i32: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f16_MVT_v4i32_r(Op0); |
| case MVT::v8i32: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f16_MVT_v8i32_r(Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f16_MVT_v2i64_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f16_MVT_v4i64_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f16_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v16f16_MVT_v16i16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2WZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v16f16_MVT_v16i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTPH2DQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v16f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i16: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v16f16_MVT_v16i16_r(Op0); |
| case MVT::v16i32: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v16f16_MVT_v16i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v32f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTPH2WZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v4f32_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPS2DQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTTPS2DQrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPS2DQrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v4f32_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPS2QQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v4f32_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPS2QQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v4f32_MVT_v4i32_r(Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v4f32_MVT_v2i64_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v4f32_MVT_v4i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f32_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPS2DQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPS2DQYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f32_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTTPS2QQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i32: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f32_MVT_v8i32_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f32_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTPS2DQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v2f64_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2DQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTTPD2DQrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2DQrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v2f64_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2QQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v2f64_MVT_v4i32_r(Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v2f64_MVT_v2i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v4f64_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2DQZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2DQYrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v4f64_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2QQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v4f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v4f64_MVT_v4i32_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v4f64_MVT_v4i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f64_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTPD2DQZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f64_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTTPD2QQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i32: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f64_MVT_v8i32_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f64_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2SI_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v16f16: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v16f16_r(RetVT, Op0); |
| case MVT::v32f16: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v32f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f32_r(RetVT, Op0); |
| case MVT::v16f32: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v2f64_r(RetVT, Op0); |
| case MVT::v4f64: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v4f64_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_STRICT_CVTTP2SI_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::STRICT_CVTTP2UI. |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f16_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2UWZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f16_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2UDQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f16_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2UDQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f16_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2UQQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f16_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2UQQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f16_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTPH2UQQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f16_MVT_v8i16_r(Op0); |
| case MVT::v4i32: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f16_MVT_v4i32_r(Op0); |
| case MVT::v8i32: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f16_MVT_v8i32_r(Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f16_MVT_v2i64_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f16_MVT_v4i64_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f16_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v16f16_MVT_v16i16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPH2UWZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v16f16_MVT_v16i32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTPH2UDQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v16f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i16: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v16f16_MVT_v16i16_r(Op0); |
| case MVT::v16i32: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v16f16_MVT_v16i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v32f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTTPH2UWZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v4f32_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPS2UDQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v4f32_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPS2UQQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v4f32_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPS2UQQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v4f32_MVT_v4i32_r(Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v4f32_MVT_v2i64_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v4f32_MVT_v4i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f32_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPS2UDQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f32_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTTPS2UQQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i32: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f32_MVT_v8i32_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f32_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTPS2UDQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v2f64_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2UDQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v2f64_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2UQQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v2f64_MVT_v4i32_r(Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v2f64_MVT_v2i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v4f64_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2UDQZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v4f64_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTTPD2UQQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v4f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v4f64_MVT_v4i32_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v4f64_MVT_v4i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f64_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTTPD2UDQZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f64_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_r(X86::VCVTTPD2UQQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i32: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f64_MVT_v8i32_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f64_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTTP2UI_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v16f16: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v16f16_r(RetVT, Op0); |
| case MVT::v32f16: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v32f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f32_r(RetVT, Op0); |
| case MVT::v16f32: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v2f64_r(RetVT, Op0); |
| case MVT::v4f64: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v4f64_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_STRICT_CVTTP2UI_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::STRICT_CVTUI2P. |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTUI2P_MVT_v4i32_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUDQ2PHZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTUI2P_MVT_v4i32_MVT_v2f64_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUDQ2PDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTUI2P_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_STRICT_CVTUI2P_MVT_v4i32_MVT_v8f16_r(Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_STRICT_CVTUI2P_MVT_v4i32_MVT_v2f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTUI2P_MVT_v2i64_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUQQ2PHZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTUI2P_MVT_v2i64_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUQQ2PSZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTUI2P_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_STRICT_CVTUI2P_MVT_v2i64_MVT_v8f16_r(Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_STRICT_CVTUI2P_MVT_v2i64_MVT_v4f32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTUI2P_MVT_v4i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTUQQ2PHZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_CVTUI2P_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_STRICT_CVTUI2P_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_STRICT_CVTUI2P_MVT_v2i64_r(RetVT, Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_STRICT_CVTUI2P_MVT_v4i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::STRICT_VFPEXT. |
| |
| unsigned fastEmit_X86ISD_STRICT_VFPEXT_MVT_v8f16_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2PSXZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_VFPEXT_MVT_v8f16_MVT_v2f64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2PDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_VFPEXT_MVT_v8f16_MVT_v4f64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2PDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_VFPEXT_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4f32: return fastEmit_X86ISD_STRICT_VFPEXT_MVT_v8f16_MVT_v4f32_r(Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_STRICT_VFPEXT_MVT_v8f16_MVT_v2f64_r(Op0); |
| case MVT::v4f64: return fastEmit_X86ISD_STRICT_VFPEXT_MVT_v8f16_MVT_v4f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_VFPEXT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2PDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTPS2PDrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2PDrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_VFPEXT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_STRICT_VFPEXT_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_STRICT_VFPEXT_MVT_v4f32_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::STRICT_VFPROUND. |
| |
| unsigned fastEmit_X86ISD_STRICT_VFPROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2PHXZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_VFPROUND_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2PHXZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_VFPROUND_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTPS2PHXZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_VFPROUND_MVT_v2f64_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2PHZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_VFPROUND_MVT_v2f64_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2PSZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTPD2PSrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2PSrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_VFPROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_STRICT_VFPROUND_MVT_v2f64_MVT_v8f16_r(Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_STRICT_VFPROUND_MVT_v2f64_MVT_v4f32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_VFPROUND_MVT_v4f64_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2PHZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_VFPROUND_MVT_v4f64_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2PSZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2PSYrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_VFPROUND_MVT_v4f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_STRICT_VFPROUND_MVT_v4f64_MVT_v8f16_r(Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_STRICT_VFPROUND_MVT_v4f64_MVT_v4f32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_VFPROUND_MVT_v8f64_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTPD2PHZrr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_VFPROUND_MVT_v8f64_MVT_v8f32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTPD2PSZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_VFPROUND_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_STRICT_VFPROUND_MVT_v8f64_MVT_v8f16_r(Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_STRICT_VFPROUND_MVT_v8f64_MVT_v8f32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_STRICT_VFPROUND_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v4f32: return fastEmit_X86ISD_STRICT_VFPROUND_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_STRICT_VFPROUND_MVT_v8f32_r(RetVT, Op0); |
| case MVT::v16f32: return fastEmit_X86ISD_STRICT_VFPROUND_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_STRICT_VFPROUND_MVT_v2f64_r(RetVT, Op0); |
| case MVT::v4f64: return fastEmit_X86ISD_STRICT_VFPROUND_MVT_v4f64_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_STRICT_VFPROUND_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::VBROADCAST. |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_i32_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTDrZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_i32_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTDrZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_i32_MVT_v16i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPBROADCASTDrZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_VBROADCAST_MVT_i32_MVT_v4i32_r(Op0); |
| case MVT::v8i32: return fastEmit_X86ISD_VBROADCAST_MVT_i32_MVT_v8i32_r(Op0); |
| case MVT::v16i32: return fastEmit_X86ISD_VBROADCAST_MVT_i32_MVT_v16i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_i64_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTQrZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_i64_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTQrZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_i64_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPBROADCASTQrZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v2i64: return fastEmit_X86ISD_VBROADCAST_MVT_i64_MVT_v2i64_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_VBROADCAST_MVT_i64_MVT_v4i64_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_VBROADCAST_MVT_i64_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v16i8_MVT_v16i8_r(unsigned Op0) { |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTBZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPBROADCASTBrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v16i8_MVT_v32i8_r(unsigned Op0) { |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTBZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPBROADCASTBYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v16i8_MVT_v64i8_r(unsigned Op0) { |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPBROADCASTBZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_X86ISD_VBROADCAST_MVT_v16i8_MVT_v16i8_r(Op0); |
| case MVT::v32i8: return fastEmit_X86ISD_VBROADCAST_MVT_v16i8_MVT_v32i8_r(Op0); |
| case MVT::v64i8: return fastEmit_X86ISD_VBROADCAST_MVT_v16i8_MVT_v64i8_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v8i16_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTWZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPBROADCASTWrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v8i16_MVT_v16i16_r(unsigned Op0) { |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTWZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPBROADCASTWYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v8i16_MVT_v32i16_r(unsigned Op0) { |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPBROADCASTWZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_X86ISD_VBROADCAST_MVT_v8i16_MVT_v8i16_r(Op0); |
| case MVT::v16i16: return fastEmit_X86ISD_VBROADCAST_MVT_v8i16_MVT_v16i16_r(Op0); |
| case MVT::v32i16: return fastEmit_X86ISD_VBROADCAST_MVT_v8i16_MVT_v32i16_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v4i32_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTDrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v4i32_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTDYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v4i32_MVT_v16i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPBROADCASTDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_VBROADCAST_MVT_v4i32_MVT_v4i32_r(Op0); |
| case MVT::v8i32: return fastEmit_X86ISD_VBROADCAST_MVT_v4i32_MVT_v8i32_r(Op0); |
| case MVT::v16i32: return fastEmit_X86ISD_VBROADCAST_MVT_v4i32_MVT_v16i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v2i64_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTQZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTQrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v2i64_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTQZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTQYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v2i64_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPBROADCASTQZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v2i64: return fastEmit_X86ISD_VBROADCAST_MVT_v2i64_MVT_v2i64_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_VBROADCAST_MVT_v2i64_MVT_v4i64_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_VBROADCAST_MVT_v2i64_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v8f16_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTWZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPBROADCASTWrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v8f16_MVT_v16f16_r(unsigned Op0) { |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTWZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPBROADCASTWYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v8f16_MVT_v32f16_r(unsigned Op0) { |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPBROADCASTWZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_VBROADCAST_MVT_v8f16_MVT_v8f16_r(Op0); |
| case MVT::v16f16: return fastEmit_X86ISD_VBROADCAST_MVT_v8f16_MVT_v16f16_r(Op0); |
| case MVT::v32f16: return fastEmit_X86ISD_VBROADCAST_MVT_v8f16_MVT_v32f16_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v4f32_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VBROADCASTSSZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VBROADCASTSSrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v4f32_MVT_v8f32_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VBROADCASTSSZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VBROADCASTSSYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v4f32_MVT_v16f32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VBROADCASTSSZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4f32: return fastEmit_X86ISD_VBROADCAST_MVT_v4f32_MVT_v4f32_r(Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_VBROADCAST_MVT_v4f32_MVT_v8f32_r(Op0); |
| case MVT::v16f32: return fastEmit_X86ISD_VBROADCAST_MVT_v4f32_MVT_v16f32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v2f64_MVT_v2f64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VMOVDDUPrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VMOVDDUPZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v2f64_MVT_v4f64_r(unsigned Op0) { |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VBROADCASTSDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VBROADCASTSDYrr, &X86::VR256RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v2f64_MVT_v8f64_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VBROADCASTSDZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v2f64: return fastEmit_X86ISD_VBROADCAST_MVT_v2f64_MVT_v2f64_r(Op0); |
| case MVT::v4f64: return fastEmit_X86ISD_VBROADCAST_MVT_v2f64_MVT_v4f64_r(Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_VBROADCAST_MVT_v2f64_MVT_v8f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCAST_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_X86ISD_VBROADCAST_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_X86ISD_VBROADCAST_MVT_i64_r(RetVT, Op0); |
| case MVT::v16i8: return fastEmit_X86ISD_VBROADCAST_MVT_v16i8_r(RetVT, Op0); |
| case MVT::v8i16: return fastEmit_X86ISD_VBROADCAST_MVT_v8i16_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_X86ISD_VBROADCAST_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_VBROADCAST_MVT_v2i64_r(RetVT, Op0); |
| case MVT::v8f16: return fastEmit_X86ISD_VBROADCAST_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_VBROADCAST_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_VBROADCAST_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::VBROADCASTM. |
| |
| unsigned fastEmit_X86ISD_VBROADCASTM_MVT_v8i1_MVT_v2i64_r(unsigned Op0) { |
| if ((Subtarget->hasCDI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTMB2QZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCASTM_MVT_v8i1_MVT_v4i64_r(unsigned Op0) { |
| if ((Subtarget->hasCDI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTMB2QZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCASTM_MVT_v8i1_MVT_v8i64_r(unsigned Op0) { |
| if ((Subtarget->hasCDI())) { |
| return fastEmitInst_r(X86::VPBROADCASTMB2QZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCASTM_MVT_v8i1_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v2i64: return fastEmit_X86ISD_VBROADCASTM_MVT_v8i1_MVT_v2i64_r(Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_VBROADCASTM_MVT_v8i1_MVT_v4i64_r(Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_VBROADCASTM_MVT_v8i1_MVT_v8i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCASTM_MVT_v16i1_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasCDI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTMW2DZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCASTM_MVT_v16i1_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasCDI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPBROADCASTMW2DZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCASTM_MVT_v16i1_MVT_v16i32_r(unsigned Op0) { |
| if ((Subtarget->hasCDI())) { |
| return fastEmitInst_r(X86::VPBROADCASTMW2DZrr, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCASTM_MVT_v16i1_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4i32: return fastEmit_X86ISD_VBROADCASTM_MVT_v16i1_MVT_v4i32_r(Op0); |
| case MVT::v8i32: return fastEmit_X86ISD_VBROADCASTM_MVT_v16i1_MVT_v8i32_r(Op0); |
| case MVT::v16i32: return fastEmit_X86ISD_VBROADCASTM_MVT_v16i1_MVT_v16i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VBROADCASTM_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8i1: return fastEmit_X86ISD_VBROADCASTM_MVT_v8i1_r(RetVT, Op0); |
| case MVT::v16i1: return fastEmit_X86ISD_VBROADCASTM_MVT_v16i1_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::VFPEXT. |
| |
| unsigned fastEmit_X86ISD_VFPEXT_MVT_v8f16_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2PSXZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VFPEXT_MVT_v8f16_MVT_v2f64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2PDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VFPEXT_MVT_v8f16_MVT_v4f64_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPH2PDZ256rr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VFPEXT_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v4f32: return fastEmit_X86ISD_VFPEXT_MVT_v8f16_MVT_v4f32_r(Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_VFPEXT_MVT_v8f16_MVT_v2f64_r(Op0); |
| case MVT::v4f64: return fastEmit_X86ISD_VFPEXT_MVT_v8f16_MVT_v4f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VFPEXT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2PDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTPS2PDrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2PDrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VFPEXT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_VFPEXT_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_VFPEXT_MVT_v4f32_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::VFPEXT_SAE. |
| |
| unsigned fastEmit_X86ISD_VFPEXT_SAE_MVT_v8f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTPH2PDZrrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VFPEXT_SAE_MVT_v16f16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTPH2PSXZrrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VFPEXT_SAE_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTPS2PDZrrb, &X86::VR512RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VFPEXT_SAE_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_VFPEXT_SAE_MVT_v8f16_r(RetVT, Op0); |
| case MVT::v16f16: return fastEmit_X86ISD_VFPEXT_SAE_MVT_v16f16_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_VFPEXT_SAE_MVT_v8f32_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::VFPROUND. |
| |
| unsigned fastEmit_X86ISD_VFPROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2PHXZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VFPROUND_MVT_v8f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPS2PHXZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VFPROUND_MVT_v16f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTPS2PHXZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VFPROUND_MVT_v2f64_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2PHZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VFPROUND_MVT_v2f64_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2PSZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::CVTPD2PSrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2PSrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VFPROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_VFPROUND_MVT_v2f64_MVT_v8f16_r(Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_VFPROUND_MVT_v2f64_MVT_v4f32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VFPROUND_MVT_v4f64_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2PHZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VFPROUND_MVT_v4f64_MVT_v4f32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2PSZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VCVTPD2PSYrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VFPROUND_MVT_v4f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_VFPROUND_MVT_v4f64_MVT_v8f16_r(Op0); |
| case MVT::v4f32: return fastEmit_X86ISD_VFPROUND_MVT_v4f64_MVT_v4f32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VFPROUND_MVT_v8f64_MVT_v8f16_r(unsigned Op0) { |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_r(X86::VCVTPD2PHZrr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VFPROUND_MVT_v8f64_MVT_v8f32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VCVTPD2PSZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VFPROUND_MVT_v8f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v8f16: return fastEmit_X86ISD_VFPROUND_MVT_v8f64_MVT_v8f16_r(Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_VFPROUND_MVT_v8f64_MVT_v8f32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VFPROUND_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v4f32: return fastEmit_X86ISD_VFPROUND_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v8f32: return fastEmit_X86ISD_VFPROUND_MVT_v8f32_r(RetVT, Op0); |
| case MVT::v16f32: return fastEmit_X86ISD_VFPROUND_MVT_v16f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_VFPROUND_MVT_v2f64_r(RetVT, Op0); |
| case MVT::v4f64: return fastEmit_X86ISD_VFPROUND_MVT_v4f64_r(RetVT, Op0); |
| case MVT::v8f64: return fastEmit_X86ISD_VFPROUND_MVT_v8f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::VTRUNC. |
| |
| unsigned fastEmit_X86ISD_VTRUNC_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVWBZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNC_MVT_v4i32_MVT_v16i8_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVDBZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNC_MVT_v4i32_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVDWZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNC_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_X86ISD_VTRUNC_MVT_v4i32_MVT_v16i8_r(Op0); |
| case MVT::v8i16: return fastEmit_X86ISD_VTRUNC_MVT_v4i32_MVT_v8i16_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNC_MVT_v8i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVDBZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNC_MVT_v2i64_MVT_v16i8_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVQBZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNC_MVT_v2i64_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVQWZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNC_MVT_v2i64_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVQDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNC_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_X86ISD_VTRUNC_MVT_v2i64_MVT_v16i8_r(Op0); |
| case MVT::v8i16: return fastEmit_X86ISD_VTRUNC_MVT_v2i64_MVT_v8i16_r(Op0); |
| case MVT::v4i32: return fastEmit_X86ISD_VTRUNC_MVT_v2i64_MVT_v4i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNC_MVT_v4i64_MVT_v16i8_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVQBZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNC_MVT_v4i64_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVQWZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNC_MVT_v4i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_X86ISD_VTRUNC_MVT_v4i64_MVT_v16i8_r(Op0); |
| case MVT::v8i16: return fastEmit_X86ISD_VTRUNC_MVT_v4i64_MVT_v8i16_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNC_MVT_v8i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVQBZrr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNC_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_X86ISD_VTRUNC_MVT_v8i16_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_X86ISD_VTRUNC_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v8i32: return fastEmit_X86ISD_VTRUNC_MVT_v8i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_VTRUNC_MVT_v2i64_r(RetVT, Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_VTRUNC_MVT_v4i64_r(RetVT, Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_VTRUNC_MVT_v8i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::VTRUNCS. |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSWBZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v16i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSWBZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v32i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32i8) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPMOVSWBZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v4i32_MVT_v16i8_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSDBZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v4i32_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSDWZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_X86ISD_VTRUNCS_MVT_v4i32_MVT_v16i8_r(Op0); |
| case MVT::v8i16: return fastEmit_X86ISD_VTRUNCS_MVT_v4i32_MVT_v8i16_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v8i32_MVT_v16i8_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSDBZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v8i32_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSDWZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v8i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_X86ISD_VTRUNCS_MVT_v8i32_MVT_v16i8_r(Op0); |
| case MVT::v8i16: return fastEmit_X86ISD_VTRUNCS_MVT_v8i32_MVT_v8i16_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v16i32_MVT_v16i8_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVSDBZrr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v16i32_MVT_v16i16_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVSDWZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v16i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_X86ISD_VTRUNCS_MVT_v16i32_MVT_v16i8_r(Op0); |
| case MVT::v16i16: return fastEmit_X86ISD_VTRUNCS_MVT_v16i32_MVT_v16i16_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v2i64_MVT_v16i8_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSQBZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v2i64_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSQWZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v2i64_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSQDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_X86ISD_VTRUNCS_MVT_v2i64_MVT_v16i8_r(Op0); |
| case MVT::v8i16: return fastEmit_X86ISD_VTRUNCS_MVT_v2i64_MVT_v8i16_r(Op0); |
| case MVT::v4i32: return fastEmit_X86ISD_VTRUNCS_MVT_v2i64_MVT_v4i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v4i64_MVT_v16i8_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSQBZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v4i64_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSQWZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v4i64_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVSQDZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v4i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_X86ISD_VTRUNCS_MVT_v4i64_MVT_v16i8_r(Op0); |
| case MVT::v8i16: return fastEmit_X86ISD_VTRUNCS_MVT_v4i64_MVT_v8i16_r(Op0); |
| case MVT::v4i32: return fastEmit_X86ISD_VTRUNCS_MVT_v4i64_MVT_v4i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v8i64_MVT_v16i8_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVSQBZrr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v8i64_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVSQWZrr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v8i64_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVSQDZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_MVT_v8i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_X86ISD_VTRUNCS_MVT_v8i64_MVT_v16i8_r(Op0); |
| case MVT::v8i16: return fastEmit_X86ISD_VTRUNCS_MVT_v8i64_MVT_v8i16_r(Op0); |
| case MVT::v8i32: return fastEmit_X86ISD_VTRUNCS_MVT_v8i64_MVT_v8i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCS_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_X86ISD_VTRUNCS_MVT_v8i16_r(RetVT, Op0); |
| case MVT::v16i16: return fastEmit_X86ISD_VTRUNCS_MVT_v16i16_r(RetVT, Op0); |
| case MVT::v32i16: return fastEmit_X86ISD_VTRUNCS_MVT_v32i16_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_X86ISD_VTRUNCS_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v8i32: return fastEmit_X86ISD_VTRUNCS_MVT_v8i32_r(RetVT, Op0); |
| case MVT::v16i32: return fastEmit_X86ISD_VTRUNCS_MVT_v16i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_VTRUNCS_MVT_v2i64_r(RetVT, Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_VTRUNCS_MVT_v4i64_r(RetVT, Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_VTRUNCS_MVT_v8i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::VTRUNCUS. |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVUSWBZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v16i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVUSWBZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v32i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v32i8) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_r(X86::VPMOVUSWBZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v4i32_MVT_v16i8_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVUSDBZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v4i32_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVUSDWZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_X86ISD_VTRUNCUS_MVT_v4i32_MVT_v16i8_r(Op0); |
| case MVT::v8i16: return fastEmit_X86ISD_VTRUNCUS_MVT_v4i32_MVT_v8i16_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v8i32_MVT_v16i8_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVUSDBZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v8i32_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVUSDWZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v8i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_X86ISD_VTRUNCUS_MVT_v8i32_MVT_v16i8_r(Op0); |
| case MVT::v8i16: return fastEmit_X86ISD_VTRUNCUS_MVT_v8i32_MVT_v8i16_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v16i32_MVT_v16i8_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVUSDBZrr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v16i32_MVT_v16i16_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVUSDWZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v16i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_X86ISD_VTRUNCUS_MVT_v16i32_MVT_v16i8_r(Op0); |
| case MVT::v16i16: return fastEmit_X86ISD_VTRUNCUS_MVT_v16i32_MVT_v16i16_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v2i64_MVT_v16i8_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVUSQBZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v2i64_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVUSQWZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v2i64_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVUSQDZ128rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_X86ISD_VTRUNCUS_MVT_v2i64_MVT_v16i8_r(Op0); |
| case MVT::v8i16: return fastEmit_X86ISD_VTRUNCUS_MVT_v2i64_MVT_v8i16_r(Op0); |
| case MVT::v4i32: return fastEmit_X86ISD_VTRUNCUS_MVT_v2i64_MVT_v4i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v4i64_MVT_v16i8_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVUSQBZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v4i64_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVUSQWZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v4i64_MVT_v4i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_r(X86::VPMOVUSQDZ256rr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v4i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_X86ISD_VTRUNCUS_MVT_v4i64_MVT_v16i8_r(Op0); |
| case MVT::v8i16: return fastEmit_X86ISD_VTRUNCUS_MVT_v4i64_MVT_v8i16_r(Op0); |
| case MVT::v4i32: return fastEmit_X86ISD_VTRUNCUS_MVT_v4i64_MVT_v4i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v8i64_MVT_v16i8_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVUSQBZrr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v8i64_MVT_v8i16_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVUSQWZrr, &X86::VR128XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v8i64_MVT_v8i32_r(unsigned Op0) { |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VPMOVUSQDZrr, &X86::VR256XRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_MVT_v8i64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_X86ISD_VTRUNCUS_MVT_v8i64_MVT_v16i8_r(Op0); |
| case MVT::v8i16: return fastEmit_X86ISD_VTRUNCUS_MVT_v8i64_MVT_v8i16_r(Op0); |
| case MVT::v8i32: return fastEmit_X86ISD_VTRUNCUS_MVT_v8i64_MVT_v8i32_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_X86ISD_VTRUNCUS_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_X86ISD_VTRUNCUS_MVT_v8i16_r(RetVT, Op0); |
| case MVT::v16i16: return fastEmit_X86ISD_VTRUNCUS_MVT_v16i16_r(RetVT, Op0); |
| case MVT::v32i16: return fastEmit_X86ISD_VTRUNCUS_MVT_v32i16_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_X86ISD_VTRUNCUS_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v8i32: return fastEmit_X86ISD_VTRUNCUS_MVT_v8i32_r(RetVT, Op0); |
| case MVT::v16i32: return fastEmit_X86ISD_VTRUNCUS_MVT_v16i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_X86ISD_VTRUNCUS_MVT_v2i64_r(RetVT, Op0); |
| case MVT::v4i64: return fastEmit_X86ISD_VTRUNCUS_MVT_v4i64_r(RetVT, Op0); |
| case MVT::v8i64: return fastEmit_X86ISD_VTRUNCUS_MVT_v8i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for X86ISD::VZEXT_MOVL. |
| |
| unsigned fastEmit_X86ISD_VZEXT_MOVL_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VMOVZPQILo2PQIZrr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::MOVZPQILo2PQIrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VMOVZPQILo2PQIrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VZEXT_MOVL_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VMOVZPQILo2PQIZrr, &X86::VR128XRegClass, Op0); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_r(X86::MOVZPQILo2PQIrr, &X86::VR128RegClass, Op0); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_r(X86::VMOVZPQILo2PQIrr, &X86::VR128RegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_X86ISD_VZEXT_MOVL_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v2i64: return fastEmit_X86ISD_VZEXT_MOVL_MVT_v2i64_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_X86ISD_VZEXT_MOVL_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // Top-level FastEmit function. |
| |
| unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0) override { |
| switch (Opcode) { |
| case ISD::ABS: return fastEmit_ISD_ABS_r(VT, RetVT, Op0); |
| case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0); |
| case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0); |
| case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0); |
| case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0); |
| case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0); |
| case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0); |
| case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0); |
| case ISD::CTTZ_ZERO_UNDEF: return fastEmit_ISD_CTTZ_ZERO_UNDEF_r(VT, RetVT, Op0); |
| case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0); |
| case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0); |
| case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0); |
| case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0); |
| case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0); |
| case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0); |
| case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0); |
| case ISD::LLRINT: return fastEmit_ISD_LLRINT_r(VT, RetVT, Op0); |
| case ISD::LRINT: return fastEmit_ISD_LRINT_r(VT, RetVT, Op0); |
| case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0); |
| case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0); |
| case ISD::SIGN_EXTEND_VECTOR_INREG: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_r(VT, RetVT, Op0); |
| case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0); |
| case ISD::STRICT_FP_EXTEND: return fastEmit_ISD_STRICT_FP_EXTEND_r(VT, RetVT, Op0); |
| case ISD::STRICT_FP_ROUND: return fastEmit_ISD_STRICT_FP_ROUND_r(VT, RetVT, Op0); |
| case ISD::STRICT_FP_TO_SINT: return fastEmit_ISD_STRICT_FP_TO_SINT_r(VT, RetVT, Op0); |
| case ISD::STRICT_FP_TO_UINT: return fastEmit_ISD_STRICT_FP_TO_UINT_r(VT, RetVT, Op0); |
| case ISD::STRICT_FSQRT: return fastEmit_ISD_STRICT_FSQRT_r(VT, RetVT, Op0); |
| case ISD::STRICT_SINT_TO_FP: return fastEmit_ISD_STRICT_SINT_TO_FP_r(VT, RetVT, Op0); |
| case ISD::STRICT_UINT_TO_FP: return fastEmit_ISD_STRICT_UINT_TO_FP_r(VT, RetVT, Op0); |
| case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0); |
| case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0); |
| case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0); |
| case ISD::ZERO_EXTEND_VECTOR_INREG: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_r(VT, RetVT, Op0); |
| case X86ISD::CALL: return fastEmit_X86ISD_CALL_r(VT, RetVT, Op0); |
| case X86ISD::CONFLICT: return fastEmit_X86ISD_CONFLICT_r(VT, RetVT, Op0); |
| case X86ISD::CVTNEPS2BF16: return fastEmit_X86ISD_CVTNEPS2BF16_r(VT, RetVT, Op0); |
| case X86ISD::CVTP2SI: return fastEmit_X86ISD_CVTP2SI_r(VT, RetVT, Op0); |
| case X86ISD::CVTP2UI: return fastEmit_X86ISD_CVTP2UI_r(VT, RetVT, Op0); |
| case X86ISD::CVTPH2PS: return fastEmit_X86ISD_CVTPH2PS_r(VT, RetVT, Op0); |
| case X86ISD::CVTPH2PS_SAE: return fastEmit_X86ISD_CVTPH2PS_SAE_r(VT, RetVT, Op0); |
| case X86ISD::CVTS2SI: return fastEmit_X86ISD_CVTS2SI_r(VT, RetVT, Op0); |
| case X86ISD::CVTS2UI: return fastEmit_X86ISD_CVTS2UI_r(VT, RetVT, Op0); |
| case X86ISD::CVTSI2P: return fastEmit_X86ISD_CVTSI2P_r(VT, RetVT, Op0); |
| case X86ISD::CVTTP2SI: return fastEmit_X86ISD_CVTTP2SI_r(VT, RetVT, Op0); |
| case X86ISD::CVTTP2SI_SAE: return fastEmit_X86ISD_CVTTP2SI_SAE_r(VT, RetVT, Op0); |
| case X86ISD::CVTTP2UI: return fastEmit_X86ISD_CVTTP2UI_r(VT, RetVT, Op0); |
| case X86ISD::CVTTP2UI_SAE: return fastEmit_X86ISD_CVTTP2UI_SAE_r(VT, RetVT, Op0); |
| case X86ISD::CVTTS2SI: return fastEmit_X86ISD_CVTTS2SI_r(VT, RetVT, Op0); |
| case X86ISD::CVTTS2SI_SAE: return fastEmit_X86ISD_CVTTS2SI_SAE_r(VT, RetVT, Op0); |
| case X86ISD::CVTTS2UI: return fastEmit_X86ISD_CVTTS2UI_r(VT, RetVT, Op0); |
| case X86ISD::CVTTS2UI_SAE: return fastEmit_X86ISD_CVTTS2UI_SAE_r(VT, RetVT, Op0); |
| case X86ISD::CVTUI2P: return fastEmit_X86ISD_CVTUI2P_r(VT, RetVT, Op0); |
| case X86ISD::DYN_ALLOCA: return fastEmit_X86ISD_DYN_ALLOCA_r(VT, RetVT, Op0); |
| case X86ISD::EH_RETURN: return fastEmit_X86ISD_EH_RETURN_r(VT, RetVT, Op0); |
| case X86ISD::EXP2: return fastEmit_X86ISD_EXP2_r(VT, RetVT, Op0); |
| case X86ISD::EXP2_SAE: return fastEmit_X86ISD_EXP2_SAE_r(VT, RetVT, Op0); |
| case X86ISD::FGETEXP: return fastEmit_X86ISD_FGETEXP_r(VT, RetVT, Op0); |
| case X86ISD::FGETEXP_SAE: return fastEmit_X86ISD_FGETEXP_SAE_r(VT, RetVT, Op0); |
| case X86ISD::FRCP: return fastEmit_X86ISD_FRCP_r(VT, RetVT, Op0); |
| case X86ISD::FRSQRT: return fastEmit_X86ISD_FRSQRT_r(VT, RetVT, Op0); |
| case X86ISD::MMX_MOVD2W: return fastEmit_X86ISD_MMX_MOVD2W_r(VT, RetVT, Op0); |
| case X86ISD::MMX_MOVW2D: return fastEmit_X86ISD_MMX_MOVW2D_r(VT, RetVT, Op0); |
| case X86ISD::MOVDDUP: return fastEmit_X86ISD_MOVDDUP_r(VT, RetVT, Op0); |
| case X86ISD::MOVDQ2Q: return fastEmit_X86ISD_MOVDQ2Q_r(VT, RetVT, Op0); |
| case X86ISD::MOVMSK: return fastEmit_X86ISD_MOVMSK_r(VT, RetVT, Op0); |
| case X86ISD::MOVQ2DQ: return fastEmit_X86ISD_MOVQ2DQ_r(VT, RetVT, Op0); |
| case X86ISD::MOVSHDUP: return fastEmit_X86ISD_MOVSHDUP_r(VT, RetVT, Op0); |
| case X86ISD::MOVSLDUP: return fastEmit_X86ISD_MOVSLDUP_r(VT, RetVT, Op0); |
| case X86ISD::NT_BRIND: return fastEmit_X86ISD_NT_BRIND_r(VT, RetVT, Op0); |
| case X86ISD::NT_CALL: return fastEmit_X86ISD_NT_CALL_r(VT, RetVT, Op0); |
| case X86ISD::PHMINPOS: return fastEmit_X86ISD_PHMINPOS_r(VT, RetVT, Op0); |
| case X86ISD::PROBED_ALLOCA: return fastEmit_X86ISD_PROBED_ALLOCA_r(VT, RetVT, Op0); |
| case X86ISD::RCP14: return fastEmit_X86ISD_RCP14_r(VT, RetVT, Op0); |
| case X86ISD::RCP28: return fastEmit_X86ISD_RCP28_r(VT, RetVT, Op0); |
| case X86ISD::RCP28_SAE: return fastEmit_X86ISD_RCP28_SAE_r(VT, RetVT, Op0); |
| case X86ISD::RSQRT14: return fastEmit_X86ISD_RSQRT14_r(VT, RetVT, Op0); |
| case X86ISD::RSQRT28: return fastEmit_X86ISD_RSQRT28_r(VT, RetVT, Op0); |
| case X86ISD::RSQRT28_SAE: return fastEmit_X86ISD_RSQRT28_SAE_r(VT, RetVT, Op0); |
| case X86ISD::SEG_ALLOCA: return fastEmit_X86ISD_SEG_ALLOCA_r(VT, RetVT, Op0); |
| case X86ISD::STRICT_CVTPH2PS: return fastEmit_X86ISD_STRICT_CVTPH2PS_r(VT, RetVT, Op0); |
| case X86ISD::STRICT_CVTSI2P: return fastEmit_X86ISD_STRICT_CVTSI2P_r(VT, RetVT, Op0); |
| case X86ISD::STRICT_CVTTP2SI: return fastEmit_X86ISD_STRICT_CVTTP2SI_r(VT, RetVT, Op0); |
| case X86ISD::STRICT_CVTTP2UI: return fastEmit_X86ISD_STRICT_CVTTP2UI_r(VT, RetVT, Op0); |
| case X86ISD::STRICT_CVTUI2P: return fastEmit_X86ISD_STRICT_CVTUI2P_r(VT, RetVT, Op0); |
| case X86ISD::STRICT_VFPEXT: return fastEmit_X86ISD_STRICT_VFPEXT_r(VT, RetVT, Op0); |
| case X86ISD::STRICT_VFPROUND: return fastEmit_X86ISD_STRICT_VFPROUND_r(VT, RetVT, Op0); |
| case X86ISD::VBROADCAST: return fastEmit_X86ISD_VBROADCAST_r(VT, RetVT, Op0); |
| case X86ISD::VBROADCASTM: return fastEmit_X86ISD_VBROADCASTM_r(VT, RetVT, Op0); |
| case X86ISD::VFPEXT: return fastEmit_X86ISD_VFPEXT_r(VT, RetVT, Op0); |
| case X86ISD::VFPEXT_SAE: return fastEmit_X86ISD_VFPEXT_SAE_r(VT, RetVT, Op0); |
| case X86ISD::VFPROUND: return fastEmit_X86ISD_VFPROUND_r(VT, RetVT, Op0); |
| case X86ISD::VTRUNC: return fastEmit_X86ISD_VTRUNC_r(VT, RetVT, Op0); |
| case X86ISD::VTRUNCS: return fastEmit_X86ISD_VTRUNCS_r(VT, RetVT, Op0); |
| case X86ISD::VTRUNCUS: return fastEmit_X86ISD_VTRUNCUS_r(VT, RetVT, Op0); |
| case X86ISD::VZEXT_MOVL: return fastEmit_X86ISD_VZEXT_MOVL_r(VT, RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::ADD. |
| |
| unsigned fastEmit_ISD_ADD_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i8) |
| return 0; |
| return fastEmitInst_rr(X86::ADD8rr, &X86::GR8RegClass, Op0, Op1); |
| } |
| |
| unsigned fastEmit_ISD_ADD_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i16) |
| return 0; |
| return fastEmitInst_rr(X86::ADD16rr, &X86::GR16RegClass, Op0, Op1); |
| } |
| |
| unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| return fastEmitInst_rr(X86::ADD32rr, &X86::GR32RegClass, Op0, Op1); |
| } |
| |
| unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| return fastEmitInst_rr(X86::ADD64rr, &X86::GR64RegClass, Op0, Op1); |
| } |
| |
| unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPADDBZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PADDBrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPADDBrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ADD_MVT_v32i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPADDBZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPADDBYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ADD_MVT_v64i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v64i8) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPADDBZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPADDWZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PADDWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPADDWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ADD_MVT_v16i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPADDWZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPADDWYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ADD_MVT_v32i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPADDWZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPADDDZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PADDDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPADDDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ADD_MVT_v8i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPADDDZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPADDDYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ADD_MVT_v16i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPADDDZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPADDQZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PADDQrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPADDQrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ADD_MVT_v4i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4i64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPADDQZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPADDQYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ADD_MVT_v8i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPADDQZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::i8: return fastEmit_ISD_ADD_MVT_i8_rr(RetVT, Op0, Op1); |
| case MVT::i16: return fastEmit_ISD_ADD_MVT_i16_rr(RetVT, Op0, Op1); |
| case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1); |
| case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1); |
| case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1); |
| case MVT::v32i8: return fastEmit_ISD_ADD_MVT_v32i8_rr(RetVT, Op0, Op1); |
| case MVT::v64i8: return fastEmit_ISD_ADD_MVT_v64i8_rr(RetVT, Op0, Op1); |
| case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1); |
| case MVT::v16i16: return fastEmit_ISD_ADD_MVT_v16i16_rr(RetVT, Op0, Op1); |
| case MVT::v32i16: return fastEmit_ISD_ADD_MVT_v32i16_rr(RetVT, Op0, Op1); |
| case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1); |
| case MVT::v8i32: return fastEmit_ISD_ADD_MVT_v8i32_rr(RetVT, Op0, Op1); |
| case MVT::v16i32: return fastEmit_ISD_ADD_MVT_v16i32_rr(RetVT, Op0, Op1); |
| case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1); |
| case MVT::v4i64: return fastEmit_ISD_ADD_MVT_v4i64_rr(RetVT, Op0, Op1); |
| case MVT::v8i64: return fastEmit_ISD_ADD_MVT_v8i64_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::AND. |
| |
| unsigned fastEmit_ISD_AND_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i8) |
| return 0; |
| return fastEmitInst_rr(X86::AND8rr, &X86::GR8RegClass, Op0, Op1); |
| } |
| |
| unsigned fastEmit_ISD_AND_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i16) |
| return 0; |
| return fastEmitInst_rr(X86::AND16rr, &X86::GR16RegClass, Op0, Op1); |
| } |
| |
| unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| return fastEmitInst_rr(X86::AND32rr, &X86::GR32RegClass, Op0, Op1); |
| } |
| |
| unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| return fastEmitInst_rr(X86::AND64rr, &X86::GR64RegClass, Op0, Op1); |
| } |
| |
| unsigned fastEmit_ISD_AND_MVT_v8i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i1) |
| return 0; |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_rr(X86::KANDBrr, &X86::VK8RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AND_MVT_v16i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i1) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::KANDWrr, &X86::VK16RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AND_MVT_v32i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i1) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::KANDDrr, &X86::VK32RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AND_MVT_v64i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v64i1) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::KANDQrr, &X86::VK64RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPANDQZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PANDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPANDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AND_MVT_v32i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i8) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPANDQZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX2())) { |
| return fastEmitInst_rr(X86::VANDPSYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPANDYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AND_MVT_v64i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v64i8) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPANDQZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i16) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPANDQZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PANDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPANDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AND_MVT_v16i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i16) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPANDQZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX2())) { |
| return fastEmitInst_rr(X86::VANDPSYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPANDYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AND_MVT_v32i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPANDQZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PANDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPANDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPANDDZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AND_MVT_v8i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i32) |
| return 0; |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX2())) { |
| return fastEmitInst_rr(X86::VANDPSYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPANDYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPANDDZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AND_MVT_v16i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPANDDZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPANDQZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PANDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPANDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AND_MVT_v4i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4i64) |
| return 0; |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX2())) { |
| return fastEmitInst_rr(X86::VANDPSYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPANDQZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPANDYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AND_MVT_v8i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPANDQZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::i8: return fastEmit_ISD_AND_MVT_i8_rr(RetVT, Op0, Op1); |
| case MVT::i16: return fastEmit_ISD_AND_MVT_i16_rr(RetVT, Op0, Op1); |
| case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1); |
| case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1); |
| case MVT::v8i1: return fastEmit_ISD_AND_MVT_v8i1_rr(RetVT, Op0, Op1); |
| case MVT::v16i1: return fastEmit_ISD_AND_MVT_v16i1_rr(RetVT, Op0, Op1); |
| case MVT::v32i1: return fastEmit_ISD_AND_MVT_v32i1_rr(RetVT, Op0, Op1); |
| case MVT::v64i1: return fastEmit_ISD_AND_MVT_v64i1_rr(RetVT, Op0, Op1); |
| case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op1); |
| case MVT::v32i8: return fastEmit_ISD_AND_MVT_v32i8_rr(RetVT, Op0, Op1); |
| case MVT::v64i8: return fastEmit_ISD_AND_MVT_v64i8_rr(RetVT, Op0, Op1); |
| case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op1); |
| case MVT::v16i16: return fastEmit_ISD_AND_MVT_v16i16_rr(RetVT, Op0, Op1); |
| case MVT::v32i16: return fastEmit_ISD_AND_MVT_v32i16_rr(RetVT, Op0, Op1); |
| case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1); |
| case MVT::v8i32: return fastEmit_ISD_AND_MVT_v8i32_rr(RetVT, Op0, Op1); |
| case MVT::v16i32: return fastEmit_ISD_AND_MVT_v16i32_rr(RetVT, Op0, Op1); |
| case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op1); |
| case MVT::v4i64: return fastEmit_ISD_AND_MVT_v4i64_rr(RetVT, Op0, Op1); |
| case MVT::v8i64: return fastEmit_ISD_AND_MVT_v8i64_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::AVGCEILU. |
| |
| unsigned fastEmit_ISD_AVGCEILU_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPAVGBZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PAVGBrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPAVGBrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AVGCEILU_MVT_v32i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPAVGBZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPAVGBYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AVGCEILU_MVT_v64i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v64i8) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPAVGBZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AVGCEILU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPAVGWZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PAVGWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPAVGWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AVGCEILU_MVT_v16i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPAVGWZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPAVGWYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AVGCEILU_MVT_v32i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPAVGWZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_AVGCEILU_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_ISD_AVGCEILU_MVT_v16i8_rr(RetVT, Op0, Op1); |
| case MVT::v32i8: return fastEmit_ISD_AVGCEILU_MVT_v32i8_rr(RetVT, Op0, Op1); |
| case MVT::v64i8: return fastEmit_ISD_AVGCEILU_MVT_v64i8_rr(RetVT, Op0, Op1); |
| case MVT::v8i16: return fastEmit_ISD_AVGCEILU_MVT_v8i16_rr(RetVT, Op0, Op1); |
| case MVT::v16i16: return fastEmit_ISD_AVGCEILU_MVT_v16i16_rr(RetVT, Op0, Op1); |
| case MVT::v32i16: return fastEmit_ISD_AVGCEILU_MVT_v32i16_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FADD. |
| |
| unsigned fastEmit_ISD_FADD_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_rr(X86::VADDSHZrr, &X86::FR16XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VADDSSZrr, &X86::FR32XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::ADDSSrr, &X86::FR32RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VADDSSrr, &X86::FR32RegClass, Op0, Op1); |
| } |
| if ((!Subtarget->hasSSE1())) { |
| return fastEmitInst_rr(X86::ADD_Fp32, &X86::RFP32RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VADDSDZrr, &X86::FR64XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::ADDSDrr, &X86::FR64RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VADDSDrr, &X86::FR64RegClass, Op0, Op1); |
| } |
| if ((!Subtarget->hasSSE2())) { |
| return fastEmitInst_rr(X86::ADD_Fp64, &X86::RFP64RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FADD_MVT_f80_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f80) |
| return 0; |
| if ((Subtarget->hasX87())) { |
| return fastEmitInst_rr(X86::ADD_Fp80, &X86::RFP80RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FADD_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VADDPHZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FADD_MVT_v16f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VADDPHZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FADD_MVT_v32f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_rr(X86::VADDPHZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VADDPSZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::ADDPSrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VADDPSrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FADD_MVT_v8f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VADDPSZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VADDPSYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FADD_MVT_v16f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VADDPSZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VADDPDZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::ADDPDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VADDPDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FADD_MVT_v4f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VADDPDZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VADDPDYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FADD_MVT_v8f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VADDPDZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::f16: return fastEmit_ISD_FADD_MVT_f16_rr(RetVT, Op0, Op1); |
| case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1); |
| case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1); |
| case MVT::f80: return fastEmit_ISD_FADD_MVT_f80_rr(RetVT, Op0, Op1); |
| case MVT::v8f16: return fastEmit_ISD_FADD_MVT_v8f16_rr(RetVT, Op0, Op1); |
| case MVT::v16f16: return fastEmit_ISD_FADD_MVT_v16f16_rr(RetVT, Op0, Op1); |
| case MVT::v32f16: return fastEmit_ISD_FADD_MVT_v32f16_rr(RetVT, Op0, Op1); |
| case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1); |
| case MVT::v8f32: return fastEmit_ISD_FADD_MVT_v8f32_rr(RetVT, Op0, Op1); |
| case MVT::v16f32: return fastEmit_ISD_FADD_MVT_v16f32_rr(RetVT, Op0, Op1); |
| case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1); |
| case MVT::v4f64: return fastEmit_ISD_FADD_MVT_v4f64_rr(RetVT, Op0, Op1); |
| case MVT::v8f64: return fastEmit_ISD_FADD_MVT_v8f64_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FDIV. |
| |
| unsigned fastEmit_ISD_FDIV_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_rr(X86::VDIVSHZrr, &X86::FR16XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VDIVSSZrr, &X86::FR32XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::DIVSSrr, &X86::FR32RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VDIVSSrr, &X86::FR32RegClass, Op0, Op1); |
| } |
| if ((!Subtarget->hasSSE1())) { |
| return fastEmitInst_rr(X86::DIV_Fp32, &X86::RFP32RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VDIVSDZrr, &X86::FR64XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::DIVSDrr, &X86::FR64RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VDIVSDrr, &X86::FR64RegClass, Op0, Op1); |
| } |
| if ((!Subtarget->hasSSE2())) { |
| return fastEmitInst_rr(X86::DIV_Fp64, &X86::RFP64RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FDIV_MVT_f80_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f80) |
| return 0; |
| if ((Subtarget->hasX87())) { |
| return fastEmitInst_rr(X86::DIV_Fp80, &X86::RFP80RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FDIV_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VDIVPHZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FDIV_MVT_v16f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VDIVPHZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FDIV_MVT_v32f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_rr(X86::VDIVPHZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VDIVPSZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::DIVPSrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VDIVPSrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FDIV_MVT_v8f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VDIVPSZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VDIVPSYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FDIV_MVT_v16f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VDIVPSZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VDIVPDZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::DIVPDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VDIVPDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FDIV_MVT_v4f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VDIVPDZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VDIVPDYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FDIV_MVT_v8f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VDIVPDZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::f16: return fastEmit_ISD_FDIV_MVT_f16_rr(RetVT, Op0, Op1); |
| case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1); |
| case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1); |
| case MVT::f80: return fastEmit_ISD_FDIV_MVT_f80_rr(RetVT, Op0, Op1); |
| case MVT::v8f16: return fastEmit_ISD_FDIV_MVT_v8f16_rr(RetVT, Op0, Op1); |
| case MVT::v16f16: return fastEmit_ISD_FDIV_MVT_v16f16_rr(RetVT, Op0, Op1); |
| case MVT::v32f16: return fastEmit_ISD_FDIV_MVT_v32f16_rr(RetVT, Op0, Op1); |
| case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1); |
| case MVT::v8f32: return fastEmit_ISD_FDIV_MVT_v8f32_rr(RetVT, Op0, Op1); |
| case MVT::v16f32: return fastEmit_ISD_FDIV_MVT_v16f32_rr(RetVT, Op0, Op1); |
| case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1); |
| case MVT::v4f64: return fastEmit_ISD_FDIV_MVT_v4f64_rr(RetVT, Op0, Op1); |
| case MVT::v8f64: return fastEmit_ISD_FDIV_MVT_v8f64_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FMUL. |
| |
| unsigned fastEmit_ISD_FMUL_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_rr(X86::VMULSHZrr, &X86::FR16XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VMULSSZrr, &X86::FR32XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::MULSSrr, &X86::FR32RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VMULSSrr, &X86::FR32RegClass, Op0, Op1); |
| } |
| if ((!Subtarget->hasSSE1())) { |
| return fastEmitInst_rr(X86::MUL_Fp32, &X86::RFP32RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VMULSDZrr, &X86::FR64XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::MULSDrr, &X86::FR64RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VMULSDrr, &X86::FR64RegClass, Op0, Op1); |
| } |
| if ((!Subtarget->hasSSE2())) { |
| return fastEmitInst_rr(X86::MUL_Fp64, &X86::RFP64RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FMUL_MVT_f80_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f80) |
| return 0; |
| if ((Subtarget->hasX87())) { |
| return fastEmitInst_rr(X86::MUL_Fp80, &X86::RFP80RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FMUL_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VMULPHZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FMUL_MVT_v16f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VMULPHZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FMUL_MVT_v32f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_rr(X86::VMULPHZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VMULPSZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::MULPSrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VMULPSrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FMUL_MVT_v8f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VMULPSZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VMULPSYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FMUL_MVT_v16f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VMULPSZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VMULPDZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::MULPDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VMULPDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FMUL_MVT_v4f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VMULPDZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VMULPDYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FMUL_MVT_v8f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VMULPDZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::f16: return fastEmit_ISD_FMUL_MVT_f16_rr(RetVT, Op0, Op1); |
| case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1); |
| case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1); |
| case MVT::f80: return fastEmit_ISD_FMUL_MVT_f80_rr(RetVT, Op0, Op1); |
| case MVT::v8f16: return fastEmit_ISD_FMUL_MVT_v8f16_rr(RetVT, Op0, Op1); |
| case MVT::v16f16: return fastEmit_ISD_FMUL_MVT_v16f16_rr(RetVT, Op0, Op1); |
| case MVT::v32f16: return fastEmit_ISD_FMUL_MVT_v32f16_rr(RetVT, Op0, Op1); |
| case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1); |
| case MVT::v8f32: return fastEmit_ISD_FMUL_MVT_v8f32_rr(RetVT, Op0, Op1); |
| case MVT::v16f32: return fastEmit_ISD_FMUL_MVT_v16f32_rr(RetVT, Op0, Op1); |
| case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1); |
| case MVT::v4f64: return fastEmit_ISD_FMUL_MVT_v4f64_rr(RetVT, Op0, Op1); |
| case MVT::v8f64: return fastEmit_ISD_FMUL_MVT_v8f64_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FSUB. |
| |
| unsigned fastEmit_ISD_FSUB_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_rr(X86::VSUBSHZrr, &X86::FR16XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VSUBSSZrr, &X86::FR32XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::SUBSSrr, &X86::FR32RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VSUBSSrr, &X86::FR32RegClass, Op0, Op1); |
| } |
| if ((!Subtarget->hasSSE1())) { |
| return fastEmitInst_rr(X86::SUB_Fp32, &X86::RFP32RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VSUBSDZrr, &X86::FR64XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::SUBSDrr, &X86::FR64RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VSUBSDrr, &X86::FR64RegClass, Op0, Op1); |
| } |
| if ((!Subtarget->hasSSE2())) { |
| return fastEmitInst_rr(X86::SUB_Fp64, &X86::RFP64RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSUB_MVT_f80_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f80) |
| return 0; |
| if ((Subtarget->hasX87())) { |
| return fastEmitInst_rr(X86::SUB_Fp80, &X86::RFP80RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSUB_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VSUBPHZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSUB_MVT_v16f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VSUBPHZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSUB_MVT_v32f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_rr(X86::VSUBPHZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VSUBPSZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::SUBPSrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VSUBPSrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSUB_MVT_v8f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VSUBPSZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VSUBPSYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSUB_MVT_v16f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VSUBPSZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VSUBPDZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::SUBPDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VSUBPDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSUB_MVT_v4f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VSUBPDZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VSUBPDYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSUB_MVT_v8f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VSUBPDZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::f16: return fastEmit_ISD_FSUB_MVT_f16_rr(RetVT, Op0, Op1); |
| case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1); |
| case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1); |
| case MVT::f80: return fastEmit_ISD_FSUB_MVT_f80_rr(RetVT, Op0, Op1); |
| case MVT::v8f16: return fastEmit_ISD_FSUB_MVT_v8f16_rr(RetVT, Op0, Op1); |
| case MVT::v16f16: return fastEmit_ISD_FSUB_MVT_v16f16_rr(RetVT, Op0, Op1); |
| case MVT::v32f16: return fastEmit_ISD_FSUB_MVT_v32f16_rr(RetVT, Op0, Op1); |
| case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1); |
| case MVT::v8f32: return fastEmit_ISD_FSUB_MVT_v8f32_rr(RetVT, Op0, Op1); |
| case MVT::v16f32: return fastEmit_ISD_FSUB_MVT_v16f32_rr(RetVT, Op0, Op1); |
| case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1); |
| case MVT::v4f64: return fastEmit_ISD_FSUB_MVT_v4f64_rr(RetVT, Op0, Op1); |
| case MVT::v8f64: return fastEmit_ISD_FSUB_MVT_v8f64_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::MUL. |
| |
| unsigned fastEmit_ISD_MUL_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i8) |
| return 0; |
| BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY), X86::AL).addReg(Op0); |
| return fastEmitInst_r(X86::MUL8r, &X86::GR8RegClass, Op1); |
| } |
| |
| unsigned fastEmit_ISD_MUL_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i16) |
| return 0; |
| return fastEmitInst_rr(X86::IMUL16rr, &X86::GR16RegClass, Op0, Op1); |
| } |
| |
| unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| return fastEmitInst_rr(X86::IMUL32rr, &X86::GR32RegClass, Op0, Op1); |
| } |
| |
| unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| return fastEmitInst_rr(X86::IMUL64rr, &X86::GR64RegClass, Op0, Op1); |
| } |
| |
| unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMULLWZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PMULLWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMULLWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_MUL_MVT_v16i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMULLWZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMULLWYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_MUL_MVT_v32i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMULLWZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMULLDZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE41() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PMULLDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMULLDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_MUL_MVT_v8i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMULLDZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMULLDYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_MUL_MVT_v16i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPMULLDZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMULLQZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_MUL_MVT_v4i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4i64) |
| return 0; |
| if ((Subtarget->hasDQI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMULLQZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_MUL_MVT_v8i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i64) |
| return 0; |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_rr(X86::VPMULLQZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::i8: return fastEmit_ISD_MUL_MVT_i8_rr(RetVT, Op0, Op1); |
| case MVT::i16: return fastEmit_ISD_MUL_MVT_i16_rr(RetVT, Op0, Op1); |
| case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1); |
| case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1); |
| case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op1); |
| case MVT::v16i16: return fastEmit_ISD_MUL_MVT_v16i16_rr(RetVT, Op0, Op1); |
| case MVT::v32i16: return fastEmit_ISD_MUL_MVT_v32i16_rr(RetVT, Op0, Op1); |
| case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1); |
| case MVT::v8i32: return fastEmit_ISD_MUL_MVT_v8i32_rr(RetVT, Op0, Op1); |
| case MVT::v16i32: return fastEmit_ISD_MUL_MVT_v16i32_rr(RetVT, Op0, Op1); |
| case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1); |
| case MVT::v4i64: return fastEmit_ISD_MUL_MVT_v4i64_rr(RetVT, Op0, Op1); |
| case MVT::v8i64: return fastEmit_ISD_MUL_MVT_v8i64_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::MULHS. |
| |
| unsigned fastEmit_ISD_MULHS_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMULHWZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PMULHWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMULHWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_MULHS_MVT_v16i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMULHWZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMULHWYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_MULHS_MVT_v32i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMULHWZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_ISD_MULHS_MVT_v8i16_rr(RetVT, Op0, Op1); |
| case MVT::v16i16: return fastEmit_ISD_MULHS_MVT_v16i16_rr(RetVT, Op0, Op1); |
| case MVT::v32i16: return fastEmit_ISD_MULHS_MVT_v32i16_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::MULHU. |
| |
| unsigned fastEmit_ISD_MULHU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMULHUWZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PMULHUWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMULHUWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_MULHU_MVT_v16i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMULHUWZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMULHUWYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_MULHU_MVT_v32i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMULHUWZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::v8i16: return fastEmit_ISD_MULHU_MVT_v8i16_rr(RetVT, Op0, Op1); |
| case MVT::v16i16: return fastEmit_ISD_MULHU_MVT_v16i16_rr(RetVT, Op0, Op1); |
| case MVT::v32i16: return fastEmit_ISD_MULHU_MVT_v32i16_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::OR. |
| |
| unsigned fastEmit_ISD_OR_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i8) |
| return 0; |
| return fastEmitInst_rr(X86::OR8rr, &X86::GR8RegClass, Op0, Op1); |
| } |
| |
| unsigned fastEmit_ISD_OR_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i16) |
| return 0; |
| return fastEmitInst_rr(X86::OR16rr, &X86::GR16RegClass, Op0, Op1); |
| } |
| |
| unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| return fastEmitInst_rr(X86::OR32rr, &X86::GR32RegClass, Op0, Op1); |
| } |
| |
| unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| return fastEmitInst_rr(X86::OR64rr, &X86::GR64RegClass, Op0, Op1); |
| } |
| |
| unsigned fastEmit_ISD_OR_MVT_v8i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i1) |
| return 0; |
| if ((Subtarget->hasDQI())) { |
| return fastEmitInst_rr(X86::KORBrr, &X86::VK8RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_OR_MVT_v16i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i1) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::KORWrr, &X86::VK16RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_OR_MVT_v32i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i1) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::KORDrr, &X86::VK32RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_OR_MVT_v64i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v64i1) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::KORQrr, &X86::VK64RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPORQZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PORrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPORrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_OR_MVT_v32i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i8) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPORQZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX2())) { |
| return fastEmitInst_rr(X86::VORPSYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPORYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_OR_MVT_v64i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v64i8) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPORQZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i16) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPORQZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PORrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPORrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_OR_MVT_v16i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i16) |
| return 0; |
| if ((Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPORQZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX2())) { |
| return fastEmitInst_rr(X86::VORPSYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPORYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_OR_MVT_v32i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPORQZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PORrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPORrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPORDZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_OR_MVT_v8i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i32) |
| return 0; |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX2())) { |
| return fastEmitInst_rr(X86::VORPSYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPORYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPORDZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_OR_MVT_v16i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPORDZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPORQZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PORrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPORrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_OR_MVT_v4i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4i64) |
| return 0; |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX2())) { |
| return fastEmitInst_rr(X86::VORPSYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPORQZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPORYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_OR_MVT_v8i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPORQZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::i8: return fastEmit_ISD_OR_MVT_i8_rr(RetVT, Op0, Op1); |
| case MVT::i16: return fastEmit_ISD_OR_MVT_i16_rr(RetVT, Op0, Op1); |
| case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1); |
| case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1); |
| case MVT::v8i1: return fastEmit_ISD_OR_MVT_v8i1_rr(RetVT, Op0, Op1); |
| case MVT::v16i1: return fastEmit_ISD_OR_MVT_v16i1_rr(RetVT, Op0, Op1); |
| case MVT::v32i1: return fastEmit_ISD_OR_MVT_v32i1_rr(RetVT, Op0, Op1); |
| case MVT::v64i1: return fastEmit_ISD_OR_MVT_v64i1_rr(RetVT, Op0, Op1); |
| case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op1); |
| case MVT::v32i8: return fastEmit_ISD_OR_MVT_v32i8_rr(RetVT, Op0, Op1); |
| case MVT::v64i8: return fastEmit_ISD_OR_MVT_v64i8_rr(RetVT, Op0, Op1); |
| case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op1); |
| case MVT::v16i16: return fastEmit_ISD_OR_MVT_v16i16_rr(RetVT, Op0, Op1); |
| case MVT::v32i16: return fastEmit_ISD_OR_MVT_v32i16_rr(RetVT, Op0, Op1); |
| case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1); |
| case MVT::v8i32: return fastEmit_ISD_OR_MVT_v8i32_rr(RetVT, Op0, Op1); |
| case MVT::v16i32: return fastEmit_ISD_OR_MVT_v16i32_rr(RetVT, Op0, Op1); |
| case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op1); |
| case MVT::v4i64: return fastEmit_ISD_OR_MVT_v4i64_rr(RetVT, Op0, Op1); |
| case MVT::v8i64: return fastEmit_ISD_OR_MVT_v8i64_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::ROTL. |
| |
| unsigned fastEmit_ISD_ROTL_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i8) |
| return 0; |
| BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1); |
| return fastEmitInst_r(X86::ROL8rCL, &X86::GR8RegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_ROTL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasXOP())) { |
| return fastEmitInst_rr(X86::VPROTBrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ROTL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i16) |
| return 0; |
| if ((Subtarget->hasXOP())) { |
| return fastEmitInst_rr(X86::VPROTWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ROTL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPROLVDZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasXOP())) { |
| return fastEmitInst_rr(X86::VPROTDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ROTL_MVT_v8i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPROLVDZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ROTL_MVT_v16i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPROLVDZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ROTL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPROLVQZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasXOP())) { |
| return fastEmitInst_rr(X86::VPROTQrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ROTL_MVT_v4i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4i64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPROLVQZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ROTL_MVT_v8i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPROLVQZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ROTL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::i8: return fastEmit_ISD_ROTL_MVT_i8_rr(RetVT, Op0, Op1); |
| case MVT::v16i8: return fastEmit_ISD_ROTL_MVT_v16i8_rr(RetVT, Op0, Op1); |
| case MVT::v8i16: return fastEmit_ISD_ROTL_MVT_v8i16_rr(RetVT, Op0, Op1); |
| case MVT::v4i32: return fastEmit_ISD_ROTL_MVT_v4i32_rr(RetVT, Op0, Op1); |
| case MVT::v8i32: return fastEmit_ISD_ROTL_MVT_v8i32_rr(RetVT, Op0, Op1); |
| case MVT::v16i32: return fastEmit_ISD_ROTL_MVT_v16i32_rr(RetVT, Op0, Op1); |
| case MVT::v2i64: return fastEmit_ISD_ROTL_MVT_v2i64_rr(RetVT, Op0, Op1); |
| case MVT::v4i64: return fastEmit_ISD_ROTL_MVT_v4i64_rr(RetVT, Op0, Op1); |
| case MVT::v8i64: return fastEmit_ISD_ROTL_MVT_v8i64_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::ROTR. |
| |
| unsigned fastEmit_ISD_ROTR_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i8) |
| return 0; |
| BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1); |
| return fastEmitInst_r(X86::ROR8rCL, &X86::GR8RegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_ROTR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPRORVDZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ROTR_MVT_v8i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPRORVDZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ROTR_MVT_v16i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPRORVDZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ROTR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPRORVQZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ROTR_MVT_v4i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4i64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPRORVQZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ROTR_MVT_v8i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPRORVQZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::i8: return fastEmit_ISD_ROTR_MVT_i8_rr(RetVT, Op0, Op1); |
| case MVT::v4i32: return fastEmit_ISD_ROTR_MVT_v4i32_rr(RetVT, Op0, Op1); |
| case MVT::v8i32: return fastEmit_ISD_ROTR_MVT_v8i32_rr(RetVT, Op0, Op1); |
| case MVT::v16i32: return fastEmit_ISD_ROTR_MVT_v16i32_rr(RetVT, Op0, Op1); |
| case MVT::v2i64: return fastEmit_ISD_ROTR_MVT_v2i64_rr(RetVT, Op0, Op1); |
| case MVT::v4i64: return fastEmit_ISD_ROTR_MVT_v4i64_rr(RetVT, Op0, Op1); |
| case MVT::v8i64: return fastEmit_ISD_ROTR_MVT_v8i64_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::SADDSAT. |
| |
| unsigned fastEmit_ISD_SADDSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPADDSBZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PADDSBrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPADDSBrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SADDSAT_MVT_v32i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPADDSBZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPADDSBYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SADDSAT_MVT_v64i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v64i8) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPADDSBZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SADDSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPADDSWZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PADDSWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPADDSWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SADDSAT_MVT_v16i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPADDSWZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPADDSWYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SADDSAT_MVT_v32i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPADDSWZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SADDSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_ISD_SADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1); |
| case MVT::v32i8: return fastEmit_ISD_SADDSAT_MVT_v32i8_rr(RetVT, Op0, Op1); |
| case MVT::v64i8: return fastEmit_ISD_SADDSAT_MVT_v64i8_rr(RetVT, Op0, Op1); |
| case MVT::v8i16: return fastEmit_ISD_SADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1); |
| case MVT::v16i16: return fastEmit_ISD_SADDSAT_MVT_v16i16_rr(RetVT, Op0, Op1); |
| case MVT::v32i16: return fastEmit_ISD_SADDSAT_MVT_v32i16_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::SHL. |
| |
| unsigned fastEmit_ISD_SHL_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i8) |
| return 0; |
| BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1); |
| return fastEmitInst_r(X86::SHL8rCL, &X86::GR8RegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::i8: return fastEmit_ISD_SHL_MVT_i8_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::SMAX. |
| |
| unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMAXSBZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE41() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PMAXSBrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMAXSBrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMAX_MVT_v32i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMAXSBZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMAXSBYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMAX_MVT_v64i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v64i8) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMAXSBZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMAXSWZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PMAXSWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMAXSWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMAX_MVT_v16i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMAXSWZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMAXSWYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMAX_MVT_v32i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMAXSWZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMAXSDZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE41() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PMAXSDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMAXSDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMAX_MVT_v8i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMAXSDZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMAXSDYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMAX_MVT_v16i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPMAXSDZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMAXSQZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMAX_MVT_v4i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4i64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMAXSQZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMAX_MVT_v8i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPMAXSQZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1); |
| case MVT::v32i8: return fastEmit_ISD_SMAX_MVT_v32i8_rr(RetVT, Op0, Op1); |
| case MVT::v64i8: return fastEmit_ISD_SMAX_MVT_v64i8_rr(RetVT, Op0, Op1); |
| case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1); |
| case MVT::v16i16: return fastEmit_ISD_SMAX_MVT_v16i16_rr(RetVT, Op0, Op1); |
| case MVT::v32i16: return fastEmit_ISD_SMAX_MVT_v32i16_rr(RetVT, Op0, Op1); |
| case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1); |
| case MVT::v8i32: return fastEmit_ISD_SMAX_MVT_v8i32_rr(RetVT, Op0, Op1); |
| case MVT::v16i32: return fastEmit_ISD_SMAX_MVT_v16i32_rr(RetVT, Op0, Op1); |
| case MVT::v2i64: return fastEmit_ISD_SMAX_MVT_v2i64_rr(RetVT, Op0, Op1); |
| case MVT::v4i64: return fastEmit_ISD_SMAX_MVT_v4i64_rr(RetVT, Op0, Op1); |
| case MVT::v8i64: return fastEmit_ISD_SMAX_MVT_v8i64_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::SMIN. |
| |
| unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMINSBZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE41() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PMINSBrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMINSBrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMIN_MVT_v32i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMINSBZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMINSBYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMIN_MVT_v64i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v64i8) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMINSBZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMINSWZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PMINSWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMINSWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMIN_MVT_v16i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMINSWZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMINSWYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMIN_MVT_v32i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPMINSWZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMINSDZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE41() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PMINSDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMINSDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMIN_MVT_v8i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMINSDZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMINSDYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMIN_MVT_v16i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPMINSDZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMINSQZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMIN_MVT_v4i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4i64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPMINSQZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMIN_MVT_v8i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPMINSQZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1); |
| case MVT::v32i8: return fastEmit_ISD_SMIN_MVT_v32i8_rr(RetVT, Op0, Op1); |
| case MVT::v64i8: return fastEmit_ISD_SMIN_MVT_v64i8_rr(RetVT, Op0, Op1); |
| case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1); |
| case MVT::v16i16: return fastEmit_ISD_SMIN_MVT_v16i16_rr(RetVT, Op0, Op1); |
| case MVT::v32i16: return fastEmit_ISD_SMIN_MVT_v32i16_rr(RetVT, Op0, Op1); |
| case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1); |
| case MVT::v8i32: return fastEmit_ISD_SMIN_MVT_v8i32_rr(RetVT, Op0, Op1); |
| case MVT::v16i32: return fastEmit_ISD_SMIN_MVT_v16i32_rr(RetVT, Op0, Op1); |
| case MVT::v2i64: return fastEmit_ISD_SMIN_MVT_v2i64_rr(RetVT, Op0, Op1); |
| case MVT::v4i64: return fastEmit_ISD_SMIN_MVT_v4i64_rr(RetVT, Op0, Op1); |
| case MVT::v8i64: return fastEmit_ISD_SMIN_MVT_v8i64_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::SRA. |
| |
| unsigned fastEmit_ISD_SRA_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i8) |
| return 0; |
| BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1); |
| return fastEmitInst_r(X86::SAR8rCL, &X86::GR8RegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::i8: return fastEmit_ISD_SRA_MVT_i8_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::SRL. |
| |
| unsigned fastEmit_ISD_SRL_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i8) |
| return 0; |
| BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1); |
| return fastEmitInst_r(X86::SHR8rCL, &X86::GR8RegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::i8: return fastEmit_ISD_SRL_MVT_i8_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::SSUBSAT. |
| |
| unsigned fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPSUBSBZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PSUBSBrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPSUBSBrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SSUBSAT_MVT_v32i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPSUBSBZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPSUBSBYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SSUBSAT_MVT_v64i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v64i8) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPSUBSBZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPSUBSWZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PSUBSWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPSUBSWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SSUBSAT_MVT_v16i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPSUBSWZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPSUBSWYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SSUBSAT_MVT_v32i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPSUBSWZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SSUBSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::v16i8: return fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1); |
| case MVT::v32i8: return fastEmit_ISD_SSUBSAT_MVT_v32i8_rr(RetVT, Op0, Op1); |
| case MVT::v64i8: return fastEmit_ISD_SSUBSAT_MVT_v64i8_rr(RetVT, Op0, Op1); |
| case MVT::v8i16: return fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1); |
| case MVT::v16i16: return fastEmit_ISD_SSUBSAT_MVT_v16i16_rr(RetVT, Op0, Op1); |
| case MVT::v32i16: return fastEmit_ISD_SSUBSAT_MVT_v32i16_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_FADD. |
| |
| unsigned fastEmit_ISD_STRICT_FADD_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_rr(X86::VADDSHZrr, &X86::FR16XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VADDSSZrr, &X86::FR32XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::ADDSSrr, &X86::FR32RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VADDSSrr, &X86::FR32RegClass, Op0, Op1); |
| } |
| if ((!Subtarget->hasSSE1())) { |
| return fastEmitInst_rr(X86::ADD_Fp32, &X86::RFP32RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VADDSDZrr, &X86::FR64XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::ADDSDrr, &X86::FR64RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VADDSDrr, &X86::FR64RegClass, Op0, Op1); |
| } |
| if ((!Subtarget->hasSSE2())) { |
| return fastEmitInst_rr(X86::ADD_Fp64, &X86::RFP64RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FADD_MVT_f80_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f80) |
| return 0; |
| if ((Subtarget->hasX87())) { |
| return fastEmitInst_rr(X86::ADD_Fp80, &X86::RFP80RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FADD_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VADDPHZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FADD_MVT_v16f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VADDPHZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FADD_MVT_v32f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_rr(X86::VADDPHZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VADDPSZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::ADDPSrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VADDPSrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FADD_MVT_v8f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VADDPSZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VADDPSYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FADD_MVT_v16f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VADDPSZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VADDPDZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::ADDPDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VADDPDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FADD_MVT_v4f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VADDPDZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VADDPDYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FADD_MVT_v8f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VADDPDZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::f16: return fastEmit_ISD_STRICT_FADD_MVT_f16_rr(RetVT, Op0, Op1); |
| case MVT::f32: return fastEmit_ISD_STRICT_FADD_MVT_f32_rr(RetVT, Op0, Op1); |
| case MVT::f64: return fastEmit_ISD_STRICT_FADD_MVT_f64_rr(RetVT, Op0, Op1); |
| case MVT::f80: return fastEmit_ISD_STRICT_FADD_MVT_f80_rr(RetVT, Op0, Op1); |
| case MVT::v8f16: return fastEmit_ISD_STRICT_FADD_MVT_v8f16_rr(RetVT, Op0, Op1); |
| case MVT::v16f16: return fastEmit_ISD_STRICT_FADD_MVT_v16f16_rr(RetVT, Op0, Op1); |
| case MVT::v32f16: return fastEmit_ISD_STRICT_FADD_MVT_v32f16_rr(RetVT, Op0, Op1); |
| case MVT::v4f32: return fastEmit_ISD_STRICT_FADD_MVT_v4f32_rr(RetVT, Op0, Op1); |
| case MVT::v8f32: return fastEmit_ISD_STRICT_FADD_MVT_v8f32_rr(RetVT, Op0, Op1); |
| case MVT::v16f32: return fastEmit_ISD_STRICT_FADD_MVT_v16f32_rr(RetVT, Op0, Op1); |
| case MVT::v2f64: return fastEmit_ISD_STRICT_FADD_MVT_v2f64_rr(RetVT, Op0, Op1); |
| case MVT::v4f64: return fastEmit_ISD_STRICT_FADD_MVT_v4f64_rr(RetVT, Op0, Op1); |
| case MVT::v8f64: return fastEmit_ISD_STRICT_FADD_MVT_v8f64_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_FDIV. |
| |
| unsigned fastEmit_ISD_STRICT_FDIV_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_rr(X86::VDIVSHZrr, &X86::FR16XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VDIVSSZrr, &X86::FR32XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::DIVSSrr, &X86::FR32RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VDIVSSrr, &X86::FR32RegClass, Op0, Op1); |
| } |
| if ((!Subtarget->hasSSE1())) { |
| return fastEmitInst_rr(X86::DIV_Fp32, &X86::RFP32RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VDIVSDZrr, &X86::FR64XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::DIVSDrr, &X86::FR64RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VDIVSDrr, &X86::FR64RegClass, Op0, Op1); |
| } |
| if ((!Subtarget->hasSSE2())) { |
| return fastEmitInst_rr(X86::DIV_Fp64, &X86::RFP64RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FDIV_MVT_f80_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f80) |
| return 0; |
| if ((Subtarget->hasX87())) { |
| return fastEmitInst_rr(X86::DIV_Fp80, &X86::RFP80RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FDIV_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VDIVPHZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FDIV_MVT_v16f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VDIVPHZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FDIV_MVT_v32f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_rr(X86::VDIVPHZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VDIVPSZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::DIVPSrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VDIVPSrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FDIV_MVT_v8f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VDIVPSZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VDIVPSYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FDIV_MVT_v16f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VDIVPSZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VDIVPDZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::DIVPDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VDIVPDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FDIV_MVT_v4f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VDIVPDZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VDIVPDYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FDIV_MVT_v8f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VDIVPDZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::f16: return fastEmit_ISD_STRICT_FDIV_MVT_f16_rr(RetVT, Op0, Op1); |
| case MVT::f32: return fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(RetVT, Op0, Op1); |
| case MVT::f64: return fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(RetVT, Op0, Op1); |
| case MVT::f80: return fastEmit_ISD_STRICT_FDIV_MVT_f80_rr(RetVT, Op0, Op1); |
| case MVT::v8f16: return fastEmit_ISD_STRICT_FDIV_MVT_v8f16_rr(RetVT, Op0, Op1); |
| case MVT::v16f16: return fastEmit_ISD_STRICT_FDIV_MVT_v16f16_rr(RetVT, Op0, Op1); |
| case MVT::v32f16: return fastEmit_ISD_STRICT_FDIV_MVT_v32f16_rr(RetVT, Op0, Op1); |
| case MVT::v4f32: return fastEmit_ISD_STRICT_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1); |
| case MVT::v8f32: return fastEmit_ISD_STRICT_FDIV_MVT_v8f32_rr(RetVT, Op0, Op1); |
| case MVT::v16f32: return fastEmit_ISD_STRICT_FDIV_MVT_v16f32_rr(RetVT, Op0, Op1); |
| case MVT::v2f64: return fastEmit_ISD_STRICT_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1); |
| case MVT::v4f64: return fastEmit_ISD_STRICT_FDIV_MVT_v4f64_rr(RetVT, Op0, Op1); |
| case MVT::v8f64: return fastEmit_ISD_STRICT_FDIV_MVT_v8f64_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_FMUL. |
| |
| unsigned fastEmit_ISD_STRICT_FMUL_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_rr(X86::VMULSHZrr, &X86::FR16XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VMULSSZrr, &X86::FR32XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::MULSSrr, &X86::FR32RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VMULSSrr, &X86::FR32RegClass, Op0, Op1); |
| } |
| if ((!Subtarget->hasSSE1())) { |
| return fastEmitInst_rr(X86::MUL_Fp32, &X86::RFP32RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VMULSDZrr, &X86::FR64XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::MULSDrr, &X86::FR64RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VMULSDrr, &X86::FR64RegClass, Op0, Op1); |
| } |
| if ((!Subtarget->hasSSE2())) { |
| return fastEmitInst_rr(X86::MUL_Fp64, &X86::RFP64RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FMUL_MVT_f80_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f80) |
| return 0; |
| if ((Subtarget->hasX87())) { |
| return fastEmitInst_rr(X86::MUL_Fp80, &X86::RFP80RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FMUL_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VMULPHZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FMUL_MVT_v16f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VMULPHZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FMUL_MVT_v32f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_rr(X86::VMULPHZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VMULPSZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::MULPSrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VMULPSrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FMUL_MVT_v8f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VMULPSZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VMULPSYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FMUL_MVT_v16f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VMULPSZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VMULPDZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::MULPDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VMULPDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FMUL_MVT_v4f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VMULPDZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VMULPDYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FMUL_MVT_v8f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VMULPDZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::f16: return fastEmit_ISD_STRICT_FMUL_MVT_f16_rr(RetVT, Op0, Op1); |
| case MVT::f32: return fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(RetVT, Op0, Op1); |
| case MVT::f64: return fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(RetVT, Op0, Op1); |
| case MVT::f80: return fastEmit_ISD_STRICT_FMUL_MVT_f80_rr(RetVT, Op0, Op1); |
| case MVT::v8f16: return fastEmit_ISD_STRICT_FMUL_MVT_v8f16_rr(RetVT, Op0, Op1); |
| case MVT::v16f16: return fastEmit_ISD_STRICT_FMUL_MVT_v16f16_rr(RetVT, Op0, Op1); |
| case MVT::v32f16: return fastEmit_ISD_STRICT_FMUL_MVT_v32f16_rr(RetVT, Op0, Op1); |
| case MVT::v4f32: return fastEmit_ISD_STRICT_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1); |
| case MVT::v8f32: return fastEmit_ISD_STRICT_FMUL_MVT_v8f32_rr(RetVT, Op0, Op1); |
| case MVT::v16f32: return fastEmit_ISD_STRICT_FMUL_MVT_v16f32_rr(RetVT, Op0, Op1); |
| case MVT::v2f64: return fastEmit_ISD_STRICT_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1); |
| case MVT::v4f64: return fastEmit_ISD_STRICT_FMUL_MVT_v4f64_rr(RetVT, Op0, Op1); |
| case MVT::v8f64: return fastEmit_ISD_STRICT_FMUL_MVT_v8f64_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_FSUB. |
| |
| unsigned fastEmit_ISD_STRICT_FSUB_MVT_f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_rr(X86::VSUBSHZrr, &X86::FR16XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VSUBSSZrr, &X86::FR32XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::SUBSSrr, &X86::FR32RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VSUBSSrr, &X86::FR32RegClass, Op0, Op1); |
| } |
| if ((!Subtarget->hasSSE1())) { |
| return fastEmitInst_rr(X86::SUB_Fp32, &X86::RFP32RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VSUBSDZrr, &X86::FR64XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::SUBSDrr, &X86::FR64RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX() && !Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VSUBSDrr, &X86::FR64RegClass, Op0, Op1); |
| } |
| if ((!Subtarget->hasSSE2())) { |
| return fastEmitInst_rr(X86::SUB_Fp64, &X86::RFP64RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSUB_MVT_f80_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::f80) |
| return 0; |
| if ((Subtarget->hasX87())) { |
| return fastEmitInst_rr(X86::SUB_Fp80, &X86::RFP80RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSUB_MVT_v8f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VSUBPHZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSUB_MVT_v16f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16f16) |
| return 0; |
| if ((Subtarget->hasFP16()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VSUBPHZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSUB_MVT_v32f16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32f16) |
| return 0; |
| if ((Subtarget->hasFP16())) { |
| return fastEmitInst_rr(X86::VSUBPHZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VSUBPSZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE1() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::SUBPSrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VSUBPSrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSUB_MVT_v8f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VSUBPSZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VSUBPSYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSUB_MVT_v16f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16f32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VSUBPSZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VSUBPDZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::SUBPDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VSUBPDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSUB_MVT_v4f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4f64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VSUBPDZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VSUBPDYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSUB_MVT_v8f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8f64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VSUBPDZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::f16: return fastEmit_ISD_STRICT_FSUB_MVT_f16_rr(RetVT, Op0, Op1); |
| case MVT::f32: return fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(RetVT, Op0, Op1); |
| case MVT::f64: return fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(RetVT, Op0, Op1); |
| case MVT::f80: return fastEmit_ISD_STRICT_FSUB_MVT_f80_rr(RetVT, Op0, Op1); |
| case MVT::v8f16: return fastEmit_ISD_STRICT_FSUB_MVT_v8f16_rr(RetVT, Op0, Op1); |
| case MVT::v16f16: return fastEmit_ISD_STRICT_FSUB_MVT_v16f16_rr(RetVT, Op0, Op1); |
| case MVT::v32f16: return fastEmit_ISD_STRICT_FSUB_MVT_v32f16_rr(RetVT, Op0, Op1); |
| case MVT::v4f32: return fastEmit_ISD_STRICT_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1); |
| case MVT::v8f32: return fastEmit_ISD_STRICT_FSUB_MVT_v8f32_rr(RetVT, Op0, Op1); |
| case MVT::v16f32: return fastEmit_ISD_STRICT_FSUB_MVT_v16f32_rr(RetVT, Op0, Op1); |
| case MVT::v2f64: return fastEmit_ISD_STRICT_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1); |
| case MVT::v4f64: return fastEmit_ISD_STRICT_FSUB_MVT_v4f64_rr(RetVT, Op0, Op1); |
| case MVT::v8f64: return fastEmit_ISD_STRICT_FSUB_MVT_v8f64_rr(RetVT, Op0, Op1); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::SUB. |
| |
| unsigned fastEmit_ISD_SUB_MVT_i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i8) |
| return 0; |
| return fastEmitInst_rr(X86::SUB8rr, &X86::GR8RegClass, Op0, Op1); |
| } |
| |
| unsigned fastEmit_ISD_SUB_MVT_i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i16) |
| return 0; |
| return fastEmitInst_rr(X86::SUB16rr, &X86::GR16RegClass, Op0, Op1); |
| } |
| |
| unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| return fastEmitInst_rr(X86::SUB32rr, &X86::GR32RegClass, Op0, Op1); |
| } |
| |
| unsigned fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| return fastEmitInst_rr(X86::SUB64rr, &X86::GR64RegClass, Op0, Op1); |
| } |
| |
| unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPSUBBZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PSUBBrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPSUBBrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SUB_MVT_v32i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i8) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPSUBBZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPSUBBYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SUB_MVT_v64i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v64i8) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPSUBBZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPSUBWZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PSUBWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPSUBWrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SUB_MVT_v16i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i16) |
| return 0; |
| if ((Subtarget->hasBWI()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPSUBWZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX() || !Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPSUBWYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SUB_MVT_v32i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v32i16) |
| return 0; |
| if ((Subtarget->hasBWI())) { |
| return fastEmitInst_rr(X86::VPSUBWZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPSUBDZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PSUBDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPSUBDrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SUB_MVT_v8i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i32) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPSUBDZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPSUBDYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SUB_MVT_v16i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v16i32) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPSUBDZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPSUBQZ128rr, &X86::VR128XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasSSE2() && !Subtarget->hasAVX())) { |
| return fastEmitInst_rr(X86::PSUBQrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPSUBQrr, &X86::VR128RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SUB_MVT_v4i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v4i64) |
| return 0; |
| if ((Subtarget->hasAVX512()) && (Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPSUBQZ256rr, &X86::VR256XRegClass, Op0, Op1); |
| } |
| if ((Subtarget->hasAVX2()) && (!Subtarget->hasVLX())) { |
| return fastEmitInst_rr(X86::VPSUBQYrr, &X86::VR256RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SUB_MVT_v8i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
| if (RetVT.SimpleTy != MVT::v8i64) |
| return 0; |
| if ((Subtarget->hasAVX512())) { |
| return fastEmitInst_rr(X86::VPSUBQZrr, &X86::VR512RegClass, Op0, Op1); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
| switch (VT.SimpleTy) { |
| case MVT::i8: return fastEmit_ISD_SUB_MVT_i8_rr(RetVT, Op0, Op1); |
| case MVT::i16: return fastEmit_ISD_SUB_MVT_i16_rr(RetVT, Op0, Op1); |
| case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op1); |
| case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op1); |
| case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1); |
| case MVT::v32i8: return fastEmit_ISD_SUB_MVT_v32i8_rr(RetVT, Op0, Op1); |
| case MVT::v64i8: return fastEmit_ISD_SUB_MVT_v64i8_rr(RetVT, Op0, Op1); |
| case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1); |
| case MVT::v16i16: return fastEmit_ISD_SUB_MVT_v16i16_rr(RetVT, Op0, Op1); |
| case MVT::v32i16: return fastEmit_ISD_SUB_MVT_v32i16_rr(RetVT, Op0, Op1); |
| |
